if_ixgb.h revision 211913
1/******************************************************************************* 2 3Copyright (c) 2001-2004, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgb/if_ixgb.h 211913 2010-08-28 00:34:22Z yongari $*/ 34 35#ifndef _IXGB_H_DEFINED_ 36#define _IXGB_H_DEFINED_ 37 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/mbuf.h> 42#include <sys/protosw.h> 43#include <sys/socket.h> 44#include <sys/malloc.h> 45#include <sys/module.h> 46#include <sys/kernel.h> 47#include <sys/sockio.h> 48 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <net/bpf.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in_systm.h> 61#include <netinet/in.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64#include <netinet/udp.h> 65 66#include <sys/bus.h> 67#include <machine/bus.h> 68#include <sys/rman.h> 69#include <machine/resource.h> 70#if __FreeBSD_version >= 502000 71#include <dev/pci/pcivar.h> 72#include <dev/pci/pcireg.h> 73#else 74#include <pci/pcivar.h> 75#include <pci/pcireg.h> 76#endif 77#include <sys/proc.h> 78#include <sys/sysctl.h> 79#include <sys/endian.h> 80 81#include <dev/ixgb/ixgb_hw.h> 82#include <dev/ixgb/ixgb_ee.h> 83#include <dev/ixgb/ixgb_ids.h> 84 85/* Tunables */ 86 87/* 88 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 89 * number of transmit descriptors allocated by the driver. Increasing this 90 * value allows the driver to queue more transmits. Each descriptor is 16 91 * bytes. 92 */ 93#define IXGB_MAX_TXD 256 94 95/* 96 * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the 97 * number of receive descriptors allocated by the driver. Increasing this 98 * value allows the driver to buffer more incoming packets. Each descriptor 99 * is 16 bytes. A receive buffer is also allocated for each descriptor. The 100 * maximum MTU size is 16110. 101 * 102 */ 103#define IXGB_MAX_RXD 1024 104 105/* 106 * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value 107 * delays the generation of transmit interrupts in units of 1.024 108 * microseconds. Transmit interrupt reduction can improve CPU efficiency if 109 * properly tuned for specific network traffic. If the system is reporting 110 * dropped transmits, this value may be set too high causing the driver to 111 * run out of available transmit descriptors. 112 */ 113#define TIDV 32 114 115/* 116 * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value 117 * delays the generation of receive interrupts in units of 1.024 118 * microseconds. Receive interrupt reduction can improve CPU efficiency if 119 * properly tuned for specific network traffic. Increasing this value adds 120 * extra latency to frame reception and can end up decreasing the throughput 121 * of TCP traffic. If the system is reporting dropped receives, this value 122 * may be set too high, causing the driver to run out of available receive 123 * descriptors. 124 * 125 */ 126#define RDTR 72 127 128 129/* 130 * This parameter controls the maximum no of times the driver will loop in 131 * the isr. Minimum Value = 1 132 */ 133#define IXGB_MAX_INTR 3 134 135 136/* 137 * Inform the stack about transmit checksum offload capabilities. 138 */ 139#define IXGB_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 140 141/* 142 * This parameter controls the duration of transmit watchdog timer. 143 */ 144#define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */ 145 146/* 147 * This parameter controls when the driver calls the routine to reclaim 148 * transmit descriptors. 149 */ 150#define IXGB_TX_CLEANUP_THRESHOLD IXGB_MAX_TXD / 8 151 152/* 153 * Flow Control Types. 154 * 1. ixgb_fc_none - Flow Control Disabled 155 * 2. ixgb_fc_rx_pause - Flow Control Receive Only 156 * 3. ixgb_fc_tx_pause - Flow Control Transmit Only 157 * 4. ixgb_fc_full - Flow Control Enabled 158 */ 159#define FLOW_CONTROL_NONE ixgb_fc_none 160#define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause 161#define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause 162#define FLOW_CONTROL_FULL ixgb_fc_full 163 164/* 165 * Set the flow control type. Assign one of the above flow control types to be enabled. 166 * Default Value: FLOW_CONTROL_FULL 167 */ 168#define FLOW_CONTROL FLOW_CONTROL_FULL 169 170/* 171 * Receive Flow control low threshold (when we send a resume frame) (FCRTL) 172 * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be 173 * less than high threshold by at least 8 bytes Default Value: 163,840 174 * (0x28000) 175 */ 176#define FCRTL 0x28000 177 178/* 179 * Receive Flow control high threshold (when we send a pause frame) (FCRTH) 180 * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default 181 * Value: 196,608 (0x30000) 182 */ 183#define FCRTH 0x30000 184 185/* 186 * Flow control request timeout (how long to pause the link partner's tx) 187 * (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100) 188 */ 189#define FCPAUSE 0x100 190 191/* Tunables -- End */ 192 193 194#define IXGB_VENDOR_ID 0x8086 195#define IXGB_MMBA 0x0010 /* Mem base address */ 196#define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 197 198#define IOCTL_CMD_TYPE u_long 199#define MAX_NUM_MULTICAST_ADDRESSES 128 200#define PCI_ANY_ID (~0U) 201#define ETHER_ALIGN 2 202 203/* Defines for printing debug information */ 204#define DEBUG_INIT 0 205#define DEBUG_IOCTL 0 206#define DEBUG_HW 0 207#define _SV_ 0 208 209#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 210#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 211#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 212#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 213#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 214#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 215#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 216#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 217#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 218 219 220/* Supported RX Buffer Sizes */ 221#define IXGB_RXBUFFER_2048 2048 222#define IXGB_RXBUFFER_4096 4096 223#define IXGB_RXBUFFER_8192 8192 224#define IXGB_RXBUFFER_16384 16384 225 226#define IXGB_MAX_SCATTER 100 227 228/* 229 * ****************************************************************************** 230 * vendor_info_array 231 * 232 * This array contains the list of Subvendor/Subdevice IDs on which the driver 233 * should load. 234 * 235***************************************************************************** 236 */ 237typedef struct _ixgb_vendor_info_t { 238 unsigned int vendor_id; 239 unsigned int device_id; 240 unsigned int subvendor_id; 241 unsigned int subdevice_id; 242 unsigned int index; 243} ixgb_vendor_info_t; 244 245 246struct ixgb_buffer { 247 struct mbuf *m_head; 248 bus_dmamap_t map; /* bus_dma map for packet */ 249}; 250 251/* 252 * Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free. 253 */ 254struct ixgb_dma_alloc { 255 bus_addr_t dma_paddr; 256 caddr_t dma_vaddr; 257 bus_dma_tag_t dma_tag; 258 bus_dmamap_t dma_map; 259 bus_dma_segment_t dma_seg; 260 bus_size_t dma_size; 261 int dma_nseg; 262}; 263 264typedef enum _XSUM_CONTEXT_T { 265 OFFLOAD_NONE, 266 OFFLOAD_TCP_IP, 267 OFFLOAD_UDP_IP 268} XSUM_CONTEXT_T; 269 270/* Our adapter structure */ 271struct adapter { 272 struct ifnet *ifp; 273 struct adapter *next; 274 struct adapter *prev; 275 struct ixgb_hw hw; 276 277 /* FreeBSD operating-system-specific structures */ 278 struct ixgb_osdep osdep; 279 struct device *dev; 280 struct resource *res_memory; 281 struct resource *res_ioport; 282 struct resource *res_interrupt; 283 void *int_handler_tag; 284 struct ifmedia media; 285 struct callout timer; 286 int io_rid; 287 int tx_timer; 288 struct mtx mtx; 289 290 /* Info about the board itself */ 291 u_int32_t part_num; 292 u_int8_t link_active; 293 u_int16_t link_speed; 294 u_int16_t link_duplex; 295 u_int32_t tx_int_delay; 296 u_int32_t tx_abs_int_delay; 297 u_int32_t rx_int_delay; 298 u_int32_t rx_abs_int_delay; 299 300 int raidc; 301 302 XSUM_CONTEXT_T active_checksum_context; 303 304 /* 305 * Transmit definitions 306 * 307 * We have an array of num_tx_desc descriptors (handled by the 308 * controller) paired with an array of tx_buffers (at 309 * tx_buffer_area). The index of the next available descriptor is 310 * next_avail_tx_desc. The number of remaining tx_desc is 311 * num_tx_desc_avail. 312 */ 313 struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */ 314 struct ixgb_tx_desc *tx_desc_base; 315 u_int32_t next_avail_tx_desc; 316 u_int32_t oldest_used_tx_desc; 317 volatile u_int16_t num_tx_desc_avail; 318 u_int16_t num_tx_desc; 319 u_int32_t txd_cmd; 320 struct ixgb_buffer *tx_buffer_area; 321 bus_dma_tag_t txtag; /* dma tag for tx */ 322 323 /* 324 * Receive definitions 325 * 326 * we have an array of num_rx_desc rx_desc (handled by the controller), 327 * and paired with an array of rx_buffers (at rx_buffer_area). The 328 * next pair to check on receive is at offset next_rx_desc_to_check 329 */ 330 struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */ 331 struct ixgb_rx_desc *rx_desc_base; 332 u_int32_t next_rx_desc_to_check; 333 u_int16_t num_rx_desc; 334 u_int32_t rx_buffer_len; 335 struct ixgb_buffer *rx_buffer_area; 336 bus_dma_tag_t rxtag; /* dma tag for Rx */ 337 u_int32_t next_rx_desc_to_use; 338 339 340 /* Jumbo frame */ 341 struct mbuf *fmp; 342 struct mbuf *lmp; 343 344 struct sysctl_ctx_list sysctl_ctx; 345 struct sysctl_oid *sysctl_tree; 346 347 /* Multicast array memory */ 348 u_int8_t *mta; 349 /* Misc stats maintained by the driver */ 350 unsigned long dropped_pkts; 351 unsigned long mbuf_alloc_failed; 352 unsigned long mbuf_cluster_failed; 353 unsigned long no_tx_desc_avail1; 354 unsigned long no_tx_desc_avail2; 355 unsigned long no_tx_map_avail; 356 unsigned long no_tx_dma_setup; 357 358 boolean_t in_detach; 359 360 /* Board specific private data */ 361#ifdef _SV_ 362 struct ixgb_sv_stats { 363 uint64_t icr_rxdmt0; 364 uint64_t icr_rxo; 365 uint64_t icr_rxt0; 366 uint64_t icr_TXDW; 367 } sv_stats; 368 unsigned long no_pkts_avail; 369 unsigned long clean_tx_interrupts; 370#endif 371 372 struct ixgb_hw_stats stats; 373}; 374 375#define IXGB_LOCK_INIT(_sc, _name) \ 376 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 377#define IXGB_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 378#define IXGB_LOCK(_sc) mtx_lock(&(_sc)->mtx) 379#define IXGB_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 380#define IXGB_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 381 382#endif /* _IXGB_H_DEFINED_ */ 383