if_iwmreg.h revision 330218
1/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2/* $FreeBSD: stable/11/sys/dev/iwm/if_iwmreg.h 330218 2018-03-01 06:48:18Z eadler $ */ 3 4/****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66#ifndef __IF_IWM_REG_H__ 67#define __IF_IWM_REG_H__ 68 69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72/* 73 * BEGIN iwl-csr.h 74 */ 75 76/* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101#define IWM_CSR_GP_CNTRL (0x024) 102 103/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104#define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106/* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114#define IWM_CSR_HW_REV (0x028) 115 116/* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122#define IWM_CSR_EEPROM_REG (0x02c) 123#define IWM_CSR_EEPROM_GP (0x030) 124#define IWM_CSR_OTP_GP_REG (0x034) 125 126#define IWM_CSR_GIO_REG (0x03C) 127#define IWM_CSR_GP_UCODE_REG (0x048) 128#define IWM_CSR_GP_DRIVER_REG (0x050) 129 130/* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139#define IWM_CSR_MBOX_SET_REG (0x088) 140#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142#define IWM_CSR_LED_REG (0x094) 143#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147/* GIO Chicken Bits (PCI Express bus link power management) */ 148#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150/* Analog phase-lock-loop configuration */ 151#define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153/* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161#define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233/* GPIO */ 234#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238/* RESET */ 239#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246/* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296/* HW REV */ 297#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300/** 301 * hw_rev values 302 */ 303enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307}; 308 309 310#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329/* EEPROM REG */ 330#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335/* EEPROM GP */ 336#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343/* One-time-programmable memory general purpose reg */ 344#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349/* GP REG */ 350#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357/* CSR GIO */ 358#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360/* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394/* GP Driver */ 395#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404/* GIO Chicken Bits (PCI Express bus link power management) */ 405#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408/* LED */ 409#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410#define IWM_CSR_LED_REG_TURN_ON (0x60) 411#define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413/* ANA_PLL */ 414#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416/* HPET MEM debug */ 417#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419/* DRAM INT TABLE */ 420#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424/* SECURE boot registers */ 425#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429}; 430 431#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439}; 440 441#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 443 444#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446 447#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 448#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 449 450#define IWM_CSR_SECURE_TIME_OUT (100) 451 452/* extended range in FW SRAM */ 453#define IWM_FW_MEM_EXTENDED_START 0x40000 454#define IWM_FW_MEM_EXTENDED_END 0x57FFF 455 456/* FW chicken bits */ 457#define IWM_LMPM_CHICK 0xa01ff8 458#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 459 460#define IWM_FH_TCSR_0_REG0 (0x1D00) 461 462/* 463 * HBUS (Host-side Bus) 464 * 465 * HBUS registers are mapped directly into PCI bus space, but are used 466 * to indirectly access device's internal memory or registers that 467 * may be powered-down. 468 * 469 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 470 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 471 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 472 * internal resources. 473 * 474 * Do not use iwl_write32()/iwl_read32() family to access these registers; 475 * these provide only simple PCI bus access, without waking up the MAC. 476 */ 477#define IWM_HBUS_BASE (0x400) 478 479/* 480 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 481 * structures, error log, event log, verifying uCode load). 482 * First write to address register, then read from or write to data register 483 * to complete the job. Once the address register is set up, accesses to 484 * data registers auto-increment the address by one dword. 485 * Bit usage for address registers (read or write): 486 * 0-31: memory address within device 487 */ 488#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 489#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 490#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 491#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 492 493/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 494#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 495#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 496 497/* 498 * Registers for accessing device's internal peripheral registers 499 * (e.g. SCD, BSM, etc.). First write to address register, 500 * then read from or write to data register to complete the job. 501 * Bit usage for address registers (read or write): 502 * 0-15: register address (offset) within device 503 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 504 */ 505#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 506#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 507#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 508#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 509 510/* enable the ID buf for read */ 511#define IWM_WFPM_PS_CTL_CLR 0xa0300c 512#define IWM_WFMP_MAC_ADDR_0 0xa03080 513#define IWM_WFMP_MAC_ADDR_1 0xa03084 514#define IWM_LMPM_PMG_EN 0xa01cec 515#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 516#define IWM_RFIC_REG_RD 0xad0470 517#define IWM_WFPM_CTRL_REG 0xa03030 518#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 519#define IWM_ENABLE_WFPM 0x80000000 520 521#define IWM_AUX_MISC_REG 0xa200b0 522#define IWM_HW_STEP_LOCATION_BITS 24 523 524#define IWM_AUX_MISC_MASTER1_EN 0xa20818 525#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 526#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 527#define IWM_RSA_ENABLE 0xa24b08 528#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 529#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 530#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 531#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 532#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 533#define IWM_SB_CPU_1_STATUS 0xa01e30 534#define IWM_SB_CPU_2_STATUS 0Xa01e34 535 536/* Used to enable DBGM */ 537#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 538 539/* 540 * Per-Tx-queue write pointer (index, really!) 541 * Indicates index to next TFD that driver will fill (1 past latest filled). 542 * Bit usage: 543 * 0-7: queue write index 544 * 11-8: queue selector 545 */ 546#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 547 548/********************************************************** 549 * CSR values 550 **********************************************************/ 551 /* 552 * host interrupt timeout value 553 * used with setting interrupt coalescing timer 554 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 555 * 556 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 557 */ 558#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 559#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 560#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 561#define IWM_HOST_INT_OPER_MODE (1 << 31) 562 563/***************************************************************************** 564 * 7000/3000 series SHR DTS addresses * 565 *****************************************************************************/ 566 567/* Diode Results Register Structure: */ 568enum iwm_dtd_diode_reg { 569 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 570 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 571 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 572 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 573 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 574 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 575/* Those are the masks INSIDE the flags bit-field: */ 576 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 577 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 578 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 579 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 580}; 581 582/* 583 * END iwl-csr.h 584 */ 585 586/* 587 * BEGIN iwl-fw.h 588 */ 589 590/** 591 * enum iwm_ucode_tlv_flag - ucode API flags 592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 593 * was a separate TLV but moved here to save space. 594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 595 * treats good CRC threshold as a boolean 596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 597 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 598 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 599 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 600 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 601 * offload profile config command. 602 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 603 * (rather than two) IPv6 addresses 604 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 605 * from the probe request template. 606 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 607 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 608 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 609 * single bound interface). 610 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 611 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 612 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 613 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 614 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 615 * 616 */ 617enum iwm_ucode_tlv_flag { 618 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 619 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 620 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 621 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 622 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 623 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 624 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 625 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 626 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 627 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 628 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 629 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 630 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 631 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 632 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 633 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 634 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 635 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 636 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 637}; 638 639#define IWM_UCODE_TLV_FLAG_BITS \ 640 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 641Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 642L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 643P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 644 645/** 646 * enum iwm_ucode_tlv_api - ucode api 647 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 648 * longer than the passive one, which is essential for fragmented scan. 649 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 650 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 651 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 652 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 653 * instead of 3. 654 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 655 * (command version 3) that supports per-chain limits 656 * 657 * @IWM_NUM_UCODE_TLV_API: number of bits used 658 */ 659enum iwm_ucode_tlv_api { 660 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 661 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 662 IWM_UCODE_TLV_API_WIDE_CMD_HDR = 14, 663 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 664 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = 24, 665 IWM_UCODE_TLV_API_TX_POWER_CHAIN = 27, 666 667 IWM_NUM_UCODE_TLV_API = 32 668}; 669 670#define IWM_UCODE_TLV_API_BITS \ 671 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 672 673/** 674 * enum iwm_ucode_tlv_capa - ucode capabilities 675 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 676 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 677 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 678 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 679 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 680 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 681 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 682 * tx power value into TPC Report action frame and Link Measurement Report 683 * action frame 684 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 685 * channel in DS parameter set element in probe requests. 686 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 687 * probe requests. 688 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 689 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 690 * which also implies support for the scheduler configuration command 691 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 692 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 693 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 694 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 695 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 696 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 697 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 698 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 699 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 700 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 701 * sources for the MCC. This TLV bit is a future replacement to 702 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 703 * is supported. 704 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 705 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 706 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 707 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 708 * 0=no support) 709 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 710 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 711 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 712 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 713 * antenna the beacon should be transmitted 714 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 715 * from AP and will send it upon d0i3 exit. 716 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 717 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 718 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 719 * thresholds reporting 720 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 721 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 722 * regular image. 723 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 724 * memory addresses from the firmware. 725 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 726 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 727 * 0=no support) 728 * 729 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 730 */ 731enum iwm_ucode_tlv_capa { 732 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 733 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 734 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 735 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 736 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 737 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 738 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 739 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 740 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 741 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 742 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 743 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 744 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 745 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 746 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 747 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 748 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 749 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 750 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 751 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 752 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 753 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 754 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 755 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 756 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 757 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 758 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 759 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 760 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 761 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 762 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 763 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 764 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 765 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 766 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 767 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 768 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 769 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 770 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 771 772 IWM_NUM_UCODE_TLV_CAPA = 128 773}; 774 775/* The default calibrate table size if not specified by firmware file */ 776#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 777#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 778#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 779 780/* The default max probe length if not specified by the firmware file */ 781#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 782 783/* 784 * enumeration of ucode section. 785 * This enumeration is used directly for older firmware (before 16.0). 786 * For new firmware, there can be up to 4 sections (see below) but the 787 * first one packaged into the firmware file is the DATA section and 788 * some debugging code accesses that. 789 */ 790enum iwm_ucode_sec { 791 IWM_UCODE_SECTION_DATA, 792 IWM_UCODE_SECTION_INST, 793}; 794/* 795 * For 16.0 uCode and above, there is no differentiation between sections, 796 * just an offset to the HW address. 797 */ 798#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 799#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 800 801/* uCode version contains 4 values: Major/Minor/API/Serial */ 802#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 803#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 804#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 805#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 806 807/* 808 * Calibration control struct. 809 * Sent as part of the phy configuration command. 810 * @flow_trigger: bitmap for which calibrations to perform according to 811 * flow triggers. 812 * @event_trigger: bitmap for which calibrations to perform according to 813 * event triggers. 814 */ 815struct iwm_tlv_calib_ctrl { 816 uint32_t flow_trigger; 817 uint32_t event_trigger; 818} __packed; 819 820enum iwm_fw_phy_cfg { 821 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 822 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 823 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 824 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 825 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 826 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 827 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 828 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 829 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 830 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 831}; 832 833#define IWM_UCODE_MAX_CS 1 834 835/** 836 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 837 * @cipher: a cipher suite selector 838 * @flags: cipher scheme flags (currently reserved for a future use) 839 * @hdr_len: a size of MPDU security header 840 * @pn_len: a size of PN 841 * @pn_off: an offset of pn from the beginning of the security header 842 * @key_idx_off: an offset of key index byte in the security header 843 * @key_idx_mask: a bit mask of key_idx bits 844 * @key_idx_shift: bit shift needed to get key_idx 845 * @mic_len: mic length in bytes 846 * @hw_cipher: a HW cipher index used in host commands 847 */ 848struct iwm_fw_cipher_scheme { 849 uint32_t cipher; 850 uint8_t flags; 851 uint8_t hdr_len; 852 uint8_t pn_len; 853 uint8_t pn_off; 854 uint8_t key_idx_off; 855 uint8_t key_idx_mask; 856 uint8_t key_idx_shift; 857 uint8_t mic_len; 858 uint8_t hw_cipher; 859} __packed; 860 861/** 862 * struct iwm_fw_cscheme_list - a cipher scheme list 863 * @size: a number of entries 864 * @cs: cipher scheme entries 865 */ 866struct iwm_fw_cscheme_list { 867 uint8_t size; 868 struct iwm_fw_cipher_scheme cs[]; 869} __packed; 870 871/* 872 * END iwl-fw.h 873 */ 874 875/* 876 * BEGIN iwl-fw-file.h 877 */ 878 879/* v1/v2 uCode file layout */ 880struct iwm_ucode_header { 881 uint32_t ver; /* major/minor/API/serial */ 882 union { 883 struct { 884 uint32_t inst_size; /* bytes of runtime code */ 885 uint32_t data_size; /* bytes of runtime data */ 886 uint32_t init_size; /* bytes of init code */ 887 uint32_t init_data_size; /* bytes of init data */ 888 uint32_t boot_size; /* bytes of bootstrap code */ 889 uint8_t data[0]; /* in same order as sizes */ 890 } v1; 891 struct { 892 uint32_t build; /* build number */ 893 uint32_t inst_size; /* bytes of runtime code */ 894 uint32_t data_size; /* bytes of runtime data */ 895 uint32_t init_size; /* bytes of init code */ 896 uint32_t init_data_size; /* bytes of init data */ 897 uint32_t boot_size; /* bytes of bootstrap code */ 898 uint8_t data[0]; /* in same order as sizes */ 899 } v2; 900 } u; 901}; 902 903/* 904 * new TLV uCode file layout 905 * 906 * The new TLV file format contains TLVs, that each specify 907 * some piece of data. 908 */ 909 910enum iwm_ucode_tlv_type { 911 IWM_UCODE_TLV_INVALID = 0, /* unused */ 912 IWM_UCODE_TLV_INST = 1, 913 IWM_UCODE_TLV_DATA = 2, 914 IWM_UCODE_TLV_INIT = 3, 915 IWM_UCODE_TLV_INIT_DATA = 4, 916 IWM_UCODE_TLV_BOOT = 5, 917 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 918 IWM_UCODE_TLV_PAN = 7, 919 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 920 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 921 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 922 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 923 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 924 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 925 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 926 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 927 IWM_UCODE_TLV_WOWLAN_INST = 16, 928 IWM_UCODE_TLV_WOWLAN_DATA = 17, 929 IWM_UCODE_TLV_FLAGS = 18, 930 IWM_UCODE_TLV_SEC_RT = 19, 931 IWM_UCODE_TLV_SEC_INIT = 20, 932 IWM_UCODE_TLV_SEC_WOWLAN = 21, 933 IWM_UCODE_TLV_DEF_CALIB = 22, 934 IWM_UCODE_TLV_PHY_SKU = 23, 935 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 936 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 937 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 938 IWM_UCODE_TLV_NUM_OF_CPU = 27, 939 IWM_UCODE_TLV_CSCHEME = 28, 940 941 /* 942 * Following two are not in our base tag, but allow 943 * handling ucode version 9. 944 */ 945 IWM_UCODE_TLV_API_CHANGES_SET = 29, 946 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 947 948 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 949 IWM_UCODE_TLV_PAGING = 32, 950 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 951 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 952 IWM_UCODE_TLV_FW_VERSION = 36, 953 IWM_UCODE_TLV_FW_DBG_DEST = 38, 954 IWM_UCODE_TLV_FW_DBG_CONF = 39, 955 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 956 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 957 IWM_UCODE_TLV_FW_MEM_SEG = 51, 958}; 959 960struct iwm_ucode_tlv { 961 uint32_t type; /* see above */ 962 uint32_t length; /* not including type/length fields */ 963 uint8_t data[0]; 964}; 965 966struct iwm_ucode_api { 967 uint32_t api_index; 968 uint32_t api_flags; 969} __packed; 970 971struct iwm_ucode_capa { 972 uint32_t api_index; 973 uint32_t api_capa; 974} __packed; 975 976#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 977 978struct iwm_tlv_ucode_header { 979 /* 980 * The TLV style ucode header is distinguished from 981 * the v1/v2 style header by first four bytes being 982 * zero, as such is an invalid combination of 983 * major/minor/API/serial versions. 984 */ 985 uint32_t zero; 986 uint32_t magic; 987 uint8_t human_readable[64]; 988 uint32_t ver; /* major/minor/API/serial */ 989 uint32_t build; 990 uint64_t ignore; 991 /* 992 * The data contained herein has a TLV layout, 993 * see above for the TLV header and types. 994 * Note that each TLV is padded to a length 995 * that is a multiple of 4 for alignment. 996 */ 997 uint8_t data[0]; 998}; 999 1000/* 1001 * END iwl-fw-file.h 1002 */ 1003 1004/* 1005 * BEGIN iwl-prph.h 1006 */ 1007 1008/* 1009 * Registers in this file are internal, not PCI bus memory mapped. 1010 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1011 */ 1012#define IWM_PRPH_BASE (0x00000) 1013#define IWM_PRPH_END (0xFFFFF) 1014 1015/* APMG (power management) constants */ 1016#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1017#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1018#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1019#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1020#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1021#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1022#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1023#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1024#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1025#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1026#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1027 1028#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1029#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1030#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1031 1032#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1033#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1034#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1035#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1036#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1037#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1038#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1039 1040#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1041 1042#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1043 1044/* Device system time */ 1045#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1046 1047/* Device NMI register */ 1048#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1049#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1050#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1051#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1052#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1053 1054/* 1055 * Device reset for family 8000 1056 * write to bit 24 in order to reset the CPU 1057 */ 1058#define IWM_RELEASE_CPU_RESET 0x300c 1059#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1060 1061 1062/***************************************************************************** 1063 * 7000/3000 series SHR DTS addresses * 1064 *****************************************************************************/ 1065 1066#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1067#define IWM_DTSC_CFG_MODE (0x00a10604) 1068#define IWM_DTSC_VREF_AVG (0x00a10648) 1069#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1070#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1071#define IWM_DTSC_PTAT_AVG (0x00a10650) 1072 1073 1074/** 1075 * Tx Scheduler 1076 * 1077 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1078 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1079 * host DRAM. It steers each frame's Tx command (which contains the frame 1080 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1081 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1082 * but one DMA channel may take input from several queues. 1083 * 1084 * Tx DMA FIFOs have dedicated purposes. 1085 * 1086 * For 5000 series and up, they are used differently 1087 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1088 * 1089 * 0 -- EDCA BK (background) frames, lowest priority 1090 * 1 -- EDCA BE (best effort) frames, normal priority 1091 * 2 -- EDCA VI (video) frames, higher priority 1092 * 3 -- EDCA VO (voice) and management frames, highest priority 1093 * 4 -- unused 1094 * 5 -- unused 1095 * 6 -- unused 1096 * 7 -- Commands 1097 * 1098 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1099 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1100 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1101 * 1102 * The driver sets up each queue to work in one of two modes: 1103 * 1104 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1105 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1106 * contains TFDs for a unique combination of Recipient Address (RA) 1107 * and Traffic Identifier (TID), that is, traffic of a given 1108 * Quality-Of-Service (QOS) priority, destined for a single station. 1109 * 1110 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1111 * each frame within the BA window, including whether it's been transmitted, 1112 * and whether it's been acknowledged by the receiving station. The device 1113 * automatically processes block-acks received from the receiving STA, 1114 * and reschedules un-acked frames to be retransmitted (successful 1115 * Tx completion may end up being out-of-order). 1116 * 1117 * The driver must maintain the queue's Byte Count table in host DRAM 1118 * for this mode. 1119 * This mode does not support fragmentation. 1120 * 1121 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1122 * The device may automatically retry Tx, but will retry only one frame 1123 * at a time, until receiving ACK from receiving station, or reaching 1124 * retry limit and giving up. 1125 * 1126 * The command queue (#4/#9) must use this mode! 1127 * This mode does not require use of the Byte Count table in host DRAM. 1128 * 1129 * Driver controls scheduler operation via 3 means: 1130 * 1) Scheduler registers 1131 * 2) Shared scheduler data base in internal SRAM 1132 * 3) Shared data in host DRAM 1133 * 1134 * Initialization: 1135 * 1136 * When loading, driver should allocate memory for: 1137 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1138 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1139 * (1024 bytes for each queue). 1140 * 1141 * After receiving "Alive" response from uCode, driver must initialize 1142 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1143 * the driver can't issue commands!): 1144 */ 1145#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1146 1147/** 1148 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1149 * can keep track of at one time when creating block-ack chains of frames. 1150 * Note that "64" matches the number of ack bits in a block-ack packet. 1151 */ 1152#define IWM_SCD_WIN_SIZE 64 1153#define IWM_SCD_FRAME_LIMIT 64 1154 1155#define IWM_SCD_TXFIFO_POS_TID (0) 1156#define IWM_SCD_TXFIFO_POS_RA (4) 1157#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1158 1159/* agn SCD */ 1160#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1161#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1162#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1163#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1164#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1165 1166#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1167#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1168#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1169#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1170#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1171#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1172#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1173#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1174#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1175#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1176 1177/* Context Data */ 1178#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1179#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1180 1181/* Tx status */ 1182#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1183#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1184 1185/* Translation Data */ 1186#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1187#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1188 1189#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1190 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1191 1192#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1193 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1194 1195#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1196 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1197 1198#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1199 1200#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1201#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1202#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1203#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1204#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1205#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1206#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1207#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1208#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1209#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1210#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1211 1212static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1213{ 1214 if (chnl < 20) 1215 return IWM_SCD_BASE + 0x18 + chnl * 4; 1216 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1217} 1218 1219static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1220{ 1221 if (chnl < 20) 1222 return IWM_SCD_BASE + 0x68 + chnl * 4; 1223 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1224} 1225 1226static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1227{ 1228 if (chnl < 20) 1229 return IWM_SCD_BASE + 0x10c + chnl * 4; 1230 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1231} 1232 1233/*********************** END TX SCHEDULER *************************************/ 1234 1235/* Oscillator clock */ 1236#define IWM_OSC_CLK (0xa04068) 1237#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1238 1239/* 1240 * END iwl-prph.h 1241 */ 1242 1243/* 1244 * BEGIN iwl-fh.h 1245 */ 1246 1247/****************************/ 1248/* Flow Handler Definitions */ 1249/****************************/ 1250 1251/** 1252 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1253 * Addresses are offsets from device's PCI hardware base address. 1254 */ 1255#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1256#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1257 1258/** 1259 * Keep-Warm (KW) buffer base address. 1260 * 1261 * Driver must allocate a 4KByte buffer that is for keeping the 1262 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1263 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1264 * from going into a power-savings mode that would cause higher DRAM latency, 1265 * and possible data over/under-runs, before all Tx/Rx is complete. 1266 * 1267 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1268 * of the buffer, which must be 4K aligned. Once this is set up, the device 1269 * automatically invokes keep-warm accesses when normal accesses might not 1270 * be sufficient to maintain fast DRAM response. 1271 * 1272 * Bit fields: 1273 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1274 */ 1275#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1276 1277 1278/** 1279 * TFD Circular Buffers Base (CBBC) addresses 1280 * 1281 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1282 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1283 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1284 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1285 * aligned (address bits 0-7 must be 0). 1286 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1287 * for them are in different places. 1288 * 1289 * Bit fields in each pointer register: 1290 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1291 */ 1292#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1293#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1294#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1295#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1296#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1297#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1298 1299/* Find TFD CB base pointer for given queue */ 1300static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1301{ 1302 if (chnl < 16) 1303 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1304 if (chnl < 20) 1305 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1306 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1307} 1308 1309 1310/** 1311 * Rx SRAM Control and Status Registers (RSCSR) 1312 * 1313 * These registers provide handshake between driver and device for the Rx queue 1314 * (this queue handles *all* command responses, notifications, Rx data, etc. 1315 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1316 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1317 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1318 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1319 * mapping between RBDs and RBs. 1320 * 1321 * Driver must allocate host DRAM memory for the following, and set the 1322 * physical address of each into device registers: 1323 * 1324 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1325 * entries (although any power of 2, up to 4096, is selectable by driver). 1326 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1327 * (typically 4K, although 8K or 16K are also selectable by driver). 1328 * Driver sets up RB size and number of RBDs in the CB via Rx config 1329 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1330 * 1331 * Bit fields within one RBD: 1332 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1333 * 1334 * Driver sets physical address [35:8] of base of RBD circular buffer 1335 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1336 * 1337 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1338 * (RBs) have been filled, via a "write pointer", actually the index of 1339 * the RB's corresponding RBD within the circular buffer. Driver sets 1340 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1341 * 1342 * Bit fields in lower dword of Rx status buffer (upper dword not used 1343 * by driver: 1344 * 31-12: Not used by driver 1345 * 11- 0: Index of last filled Rx buffer descriptor 1346 * (device writes, driver reads this value) 1347 * 1348 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1349 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1350 * and update the device's "write" index register, 1351 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1352 * 1353 * This "write" index corresponds to the *next* RBD that the driver will make 1354 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1355 * the circular buffer. This value should initially be 0 (before preparing any 1356 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1357 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1358 * "read" index has advanced past 1! See below). 1359 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1360 * 1361 * As the device fills RBs (referenced from contiguous RBDs within the circular 1362 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1363 * to tell the driver the index of the latest filled RBD. The driver must 1364 * read this "read" index from DRAM after receiving an Rx interrupt from device 1365 * 1366 * The driver must also internally keep track of a third index, which is the 1367 * next RBD to process. When receiving an Rx interrupt, driver should process 1368 * all filled but unprocessed RBs up to, but not including, the RB 1369 * corresponding to the "read" index. For example, if "read" index becomes "1", 1370 * driver may process the RB pointed to by RBD 0. Depending on volume of 1371 * traffic, there may be many RBs to process. 1372 * 1373 * If read index == write index, device thinks there is no room to put new data. 1374 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1375 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1376 * and "read" indexes; that is, make sure that there are no more than 254 1377 * buffers waiting to be filled. 1378 */ 1379#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1380#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1381#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1382 1383/** 1384 * Physical base address of 8-byte Rx Status buffer. 1385 * Bit fields: 1386 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1387 */ 1388#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1389 1390/** 1391 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1392 * Bit fields: 1393 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1394 */ 1395#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1396 1397/** 1398 * Rx write pointer (index, really!). 1399 * Bit fields: 1400 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1401 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1402 */ 1403#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1404#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1405 1406#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1407#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1408 1409/** 1410 * Rx Config/Status Registers (RCSR) 1411 * Rx Config Reg for channel 0 (only channel used) 1412 * 1413 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1414 * normal operation (see bit fields). 1415 * 1416 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1417 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1418 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1419 * 1420 * Bit fields: 1421 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1422 * '10' operate normally 1423 * 29-24: reserved 1424 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1425 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1426 * 19-18: reserved 1427 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1428 * '10' 12K, '11' 16K. 1429 * 15-14: reserved 1430 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1431 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1432 * typical value 0x10 (about 1/2 msec) 1433 * 3- 0: reserved 1434 */ 1435#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1436#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1437#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1438 1439#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1440#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1441#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1442 1443#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1444#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1445#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1446#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1447#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1448#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1449 1450#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1451#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1452#define IWM_RX_RB_TIMEOUT (0x11) 1453 1454#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1455#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1456#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1457 1458#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1459#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1460#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1461#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1462 1463#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1464#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1465#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1466 1467/** 1468 * Rx Shared Status Registers (RSSR) 1469 * 1470 * After stopping Rx DMA channel (writing 0 to 1471 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1472 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1473 * 1474 * Bit fields: 1475 * 24: 1 = Channel 0 is idle 1476 * 1477 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1478 * contain default values that should not be altered by the driver. 1479 */ 1480#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1481#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1482 1483#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1484#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1485#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1486 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1487 1488#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1489 1490#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1491 1492/* TFDB Area - TFDs buffer table */ 1493#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1494#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1495#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1496#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1497#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1498 1499/** 1500 * Transmit DMA Channel Control/Status Registers (TCSR) 1501 * 1502 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1503 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1504 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1505 * 1506 * To use a Tx DMA channel, driver must initialize its 1507 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1508 * 1509 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1510 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1511 * 1512 * All other bits should be 0. 1513 * 1514 * Bit fields: 1515 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1516 * '10' operate normally 1517 * 29- 4: Reserved, set to "0" 1518 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1519 * 2- 0: Reserved, set to "0" 1520 */ 1521#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1522#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1523 1524/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1525#define IWM_FH_TCSR_CHNL_NUM (8) 1526 1527/* TCSR: tx_config register values */ 1528#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1529 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1530#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1531 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1532#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1533 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1534 1535#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1536#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1537 1538#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1539#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1540 1541#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1542#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1543#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1544 1545#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1546#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1547#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1548 1549#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1550#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1551#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1552 1553#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1554#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1555#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1556 1557#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1558#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1559 1560/** 1561 * Tx Shared Status Registers (TSSR) 1562 * 1563 * After stopping Tx DMA channel (writing 0 to 1564 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1565 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1566 * (channel's buffers empty | no pending requests). 1567 * 1568 * Bit fields: 1569 * 31-24: 1 = Channel buffers empty (channel 7:0) 1570 * 23-16: 1 = No pending requests (channel 7:0) 1571 */ 1572#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1573#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1574 1575#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1576 1577/** 1578 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1579 * 31: Indicates an address error when accessed to internal memory 1580 * uCode/driver must write "1" in order to clear this flag 1581 * 30: Indicates that Host did not send the expected number of dwords to FH 1582 * uCode/driver must write "1" in order to clear this flag 1583 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1584 * command was received from the scheduler while the TRB was already full 1585 * with previous command 1586 * uCode/driver must write "1" in order to clear this flag 1587 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1588 * bit is set, it indicates that the FH has received a full indication 1589 * from the RTC TxFIFO and the current value of the TxCredit counter was 1590 * not equal to zero. This mean that the credit mechanism was not 1591 * synchronized to the TxFIFO status 1592 * uCode/driver must write "1" in order to clear this flag 1593 */ 1594#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1595#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1596 1597#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1598 1599/* Tx service channels */ 1600#define IWM_FH_SRVC_CHNL (9) 1601#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1602#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1603#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1604 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1605 1606#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1607#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1608 (_chan) * 4) 1609 1610/* Instruct FH to increment the retry count of a packet when 1611 * it is brought from the memory to TX-FIFO 1612 */ 1613#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1614 1615#define IWM_RX_QUEUE_SIZE 256 1616#define IWM_RX_QUEUE_MASK 255 1617#define IWM_RX_QUEUE_SIZE_LOG 8 1618 1619/* 1620 * RX related structures and functions 1621 */ 1622#define IWM_RX_FREE_BUFFERS 64 1623#define IWM_RX_LOW_WATERMARK 8 1624 1625/** 1626 * struct iwm_rb_status - reseve buffer status 1627 * host memory mapped FH registers 1628 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1629 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1630 * @finished_rb_num [0:11] - Indicates the index of the current RB 1631 * in which the last frame was written to 1632 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1633 * which was transferred 1634 */ 1635struct iwm_rb_status { 1636 uint16_t closed_rb_num; 1637 uint16_t closed_fr_num; 1638 uint16_t finished_rb_num; 1639 uint16_t finished_fr_nam; 1640 uint32_t unused; 1641} __packed; 1642 1643 1644#define IWM_TFD_QUEUE_SIZE_MAX (256) 1645#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1646#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1647 IWM_TFD_QUEUE_SIZE_BC_DUP) 1648#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1649#define IWM_NUM_OF_TBS 20 1650 1651static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1652{ 1653 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1654} 1655/** 1656 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1657 * 1658 * This structure contains dma address and length of transmission address 1659 * 1660 * @lo: low [31:0] portion of the dma address of TX buffer 1661 * every even is unaligned on 16 bit boundary 1662 * @hi_n_len 0-3 [35:32] portion of dma 1663 * 4-15 length of the tx buffer 1664 */ 1665struct iwm_tfd_tb { 1666 uint32_t lo; 1667 uint16_t hi_n_len; 1668} __packed; 1669 1670/** 1671 * struct iwm_tfd 1672 * 1673 * Transmit Frame Descriptor (TFD) 1674 * 1675 * @ __reserved1[3] reserved 1676 * @ num_tbs 0-4 number of active tbs 1677 * 5 reserved 1678 * 6-7 padding (not used) 1679 * @ tbs[20] transmit frame buffer descriptors 1680 * @ __pad padding 1681 * 1682 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1683 * Both driver and device share these circular buffers, each of which must be 1684 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1685 * 1686 * Driver must indicate the physical address of the base of each 1687 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1688 * 1689 * Each TFD contains pointer/size information for up to 20 data buffers 1690 * in host DRAM. These buffers collectively contain the (one) frame described 1691 * by the TFD. Each buffer must be a single contiguous block of memory within 1692 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1693 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1694 * Tx frame, up to 8 KBytes in size. 1695 * 1696 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1697 */ 1698struct iwm_tfd { 1699 uint8_t __reserved1[3]; 1700 uint8_t num_tbs; 1701 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1702 uint32_t __pad; 1703} __packed; 1704 1705/* Keep Warm Size */ 1706#define IWM_KW_SIZE 0x1000 /* 4k */ 1707 1708/* Fixed (non-configurable) rx data from phy */ 1709 1710/** 1711 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1712 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1713 * @tfd_offset 0-12 - tx command byte count 1714 * 12-16 - station index 1715 */ 1716struct iwm_agn_scd_bc_tbl { 1717 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1718} __packed; 1719 1720/* 1721 * END iwl-fh.h 1722 */ 1723 1724/* 1725 * BEGIN mvm/fw-api.h 1726 */ 1727 1728/* Maximum number of Tx queues. */ 1729#define IWM_MVM_MAX_QUEUES 31 1730 1731/* Tx queue numbers */ 1732enum { 1733 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1734 IWM_MVM_CMD_QUEUE = 9, 1735 IWM_MVM_AUX_QUEUE = 15, 1736}; 1737 1738enum iwm_mvm_tx_fifo { 1739 IWM_MVM_TX_FIFO_BK = 0, 1740 IWM_MVM_TX_FIFO_BE, 1741 IWM_MVM_TX_FIFO_VI, 1742 IWM_MVM_TX_FIFO_VO, 1743 IWM_MVM_TX_FIFO_MCAST = 5, 1744 IWM_MVM_TX_FIFO_CMD = 7, 1745}; 1746 1747#define IWM_MVM_STATION_COUNT 16 1748 1749/* commands */ 1750enum { 1751 IWM_MVM_ALIVE = 0x1, 1752 IWM_REPLY_ERROR = 0x2, 1753 1754 IWM_INIT_COMPLETE_NOTIF = 0x4, 1755 1756 /* PHY context commands */ 1757 IWM_PHY_CONTEXT_CMD = 0x8, 1758 IWM_DBG_CFG = 0x9, 1759 1760 /* UMAC scan commands */ 1761 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1762 IWM_SCAN_CFG_CMD = 0xc, 1763 IWM_SCAN_REQ_UMAC = 0xd, 1764 IWM_SCAN_ABORT_UMAC = 0xe, 1765 IWM_SCAN_COMPLETE_UMAC = 0xf, 1766 1767 /* station table */ 1768 IWM_ADD_STA_KEY = 0x17, 1769 IWM_ADD_STA = 0x18, 1770 IWM_REMOVE_STA = 0x19, 1771 1772 /* TX */ 1773 IWM_TX_CMD = 0x1c, 1774 IWM_TXPATH_FLUSH = 0x1e, 1775 IWM_MGMT_MCAST_KEY = 0x1f, 1776 1777 /* scheduler config */ 1778 IWM_SCD_QUEUE_CFG = 0x1d, 1779 1780 /* global key */ 1781 IWM_WEP_KEY = 0x20, 1782 1783 /* MAC and Binding commands */ 1784 IWM_MAC_CONTEXT_CMD = 0x28, 1785 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1786 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1787 IWM_BINDING_CONTEXT_CMD = 0x2b, 1788 IWM_TIME_QUOTA_CMD = 0x2c, 1789 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1790 1791 IWM_LQ_CMD = 0x4e, 1792 1793 /* paging block to FW cpu2 */ 1794 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1795 1796 /* Scan offload */ 1797 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1798 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1799 IWM_HOT_SPOT_CMD = 0x53, 1800 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1801 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1802 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1803 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1804 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1805 1806 /* Phy */ 1807 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1808 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1809 /* IWM_PHY_DB_CMD = 0x6c, */ 1810 1811 /* Power - legacy power table command */ 1812 IWM_POWER_TABLE_CMD = 0x77, 1813 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1814 1815 /* Thermal Throttling*/ 1816 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1817 1818 /* Scanning */ 1819 IWM_SCAN_ABORT_CMD = 0x81, 1820 IWM_SCAN_START_NOTIFICATION = 0x82, 1821 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1822 1823 /* NVM */ 1824 IWM_NVM_ACCESS_CMD = 0x88, 1825 1826 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1827 1828 IWM_BEACON_NOTIFICATION = 0x90, 1829 IWM_BEACON_TEMPLATE_CMD = 0x91, 1830 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1831 IWM_BT_CONFIG = 0x9b, 1832 IWM_STATISTICS_NOTIFICATION = 0x9d, 1833 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1834 1835 /* RF-KILL commands and notifications */ 1836 IWM_CARD_STATE_CMD = 0xa0, 1837 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1838 1839 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1840 1841 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1842 1843 /* Power - new power table command */ 1844 IWM_MAC_PM_POWER_TABLE = 0xa9, 1845 1846 IWM_REPLY_RX_PHY_CMD = 0xc0, 1847 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1848 IWM_BA_NOTIF = 0xc5, 1849 1850 /* Location Aware Regulatory */ 1851 IWM_MCC_UPDATE_CMD = 0xc8, 1852 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1853 1854 /* BT Coex */ 1855 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1856 IWM_BT_COEX_PROT_ENV = 0xcd, 1857 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1858 IWM_BT_COEX_CI = 0x5d, 1859 1860 IWM_REPLY_SF_CFG_CMD = 0xd1, 1861 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1862 1863 /* DTS measurements */ 1864 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1865 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1866 1867 IWM_REPLY_DEBUG_CMD = 0xf0, 1868 IWM_DEBUG_LOG_MSG = 0xf7, 1869 1870 IWM_MCAST_FILTER_CMD = 0xd0, 1871 1872 /* D3 commands/notifications */ 1873 IWM_D3_CONFIG_CMD = 0xd3, 1874 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1875 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1876 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1877 1878 /* for WoWLAN in particular */ 1879 IWM_WOWLAN_PATTERNS = 0xe0, 1880 IWM_WOWLAN_CONFIGURATION = 0xe1, 1881 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1882 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1883 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1884 IWM_WOWLAN_GET_STATUSES = 0xe5, 1885 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1886 1887 /* and for NetDetect */ 1888 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1889 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1890 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1891 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1892 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1893 1894 IWM_REPLY_MAX = 0xff, 1895}; 1896 1897enum iwm_phy_ops_subcmd_ids { 1898 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1899 IWM_CTDP_CONFIG_CMD = 0x03, 1900 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1901 IWM_CT_KILL_NOTIFICATION = 0xFE, 1902 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1903}; 1904 1905/* command groups */ 1906enum { 1907 IWM_LEGACY_GROUP = 0x0, 1908 IWM_LONG_GROUP = 0x1, 1909 IWM_SYSTEM_GROUP = 0x2, 1910 IWM_MAC_CONF_GROUP = 0x3, 1911 IWM_PHY_OPS_GROUP = 0x4, 1912 IWM_DATA_PATH_GROUP = 0x5, 1913 IWM_PROT_OFFLOAD_GROUP = 0xb, 1914}; 1915 1916/** 1917 * struct iwm_cmd_response - generic response struct for most commands 1918 * @status: status of the command asked, changes for each one 1919 */ 1920struct iwm_cmd_response { 1921 uint32_t status; 1922}; 1923 1924/* 1925 * struct iwm_tx_ant_cfg_cmd 1926 * @valid: valid antenna configuration 1927 */ 1928struct iwm_tx_ant_cfg_cmd { 1929 uint32_t valid; 1930} __packed; 1931 1932/** 1933 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1934 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1935 * @flags: (reserved for future implementation) 1936 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1937 * @pwr_restriction: TX power restriction in dBms. 1938 */ 1939struct iwm_reduce_tx_power_cmd { 1940 uint8_t flags; 1941 uint8_t mac_context_id; 1942 uint16_t pwr_restriction; 1943} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1944 1945/* 1946 * Calibration control struct. 1947 * Sent as part of the phy configuration command. 1948 * @flow_trigger: bitmap for which calibrations to perform according to 1949 * flow triggers. 1950 * @event_trigger: bitmap for which calibrations to perform according to 1951 * event triggers. 1952 */ 1953struct iwm_calib_ctrl { 1954 uint32_t flow_trigger; 1955 uint32_t event_trigger; 1956} __packed; 1957 1958/* This enum defines the bitmap of various calibrations to enable in both 1959 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1960 */ 1961enum iwm_calib_cfg { 1962 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1963 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1964 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1965 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1966 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1967 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1968 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1969 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1970 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1971 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1972 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1973 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1974 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1975 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1976 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1977 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1978 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1979 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1980 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1981}; 1982 1983/* 1984 * Phy configuration command. 1985 */ 1986struct iwm_phy_cfg_cmd { 1987 uint32_t phy_cfg; 1988 struct iwm_calib_ctrl calib_control; 1989} __packed; 1990 1991#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1992#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1993#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1994#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1995#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1996#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1997#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1998#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1999#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2000#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2001 2002 2003/* Target of the IWM_NVM_ACCESS_CMD */ 2004enum { 2005 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2006 IWM_NVM_ACCESS_TARGET_OTP = 1, 2007 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2008}; 2009 2010/* Section types for IWM_NVM_ACCESS_CMD */ 2011enum { 2012 IWM_NVM_SECTION_TYPE_SW = 1, 2013 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2014 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2015 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2016 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2017 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2018 IWM_NVM_MAX_NUM_SECTIONS = 13, 2019}; 2020 2021/** 2022 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2023 * @op_code: 0 - read, 1 - write 2024 * @target: IWM_NVM_ACCESS_TARGET_* 2025 * @type: IWM_NVM_SECTION_TYPE_* 2026 * @offset: offset in bytes into the section 2027 * @length: in bytes, to read/write 2028 * @data: if write operation, the data to write. On read its empty 2029 */ 2030struct iwm_nvm_access_cmd { 2031 uint8_t op_code; 2032 uint8_t target; 2033 uint16_t type; 2034 uint16_t offset; 2035 uint16_t length; 2036 uint8_t data[]; 2037} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2038 2039#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2040 2041/* 2042 * struct iwm_fw_paging_cmd - paging layout 2043 * 2044 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2045 * 2046 * Send to FW the paging layout in the driver. 2047 * 2048 * @flags: various flags for the command 2049 * @block_size: the block size in powers of 2 2050 * @block_num: number of blocks specified in the command. 2051 * @device_phy_addr: virtual addresses from device side 2052*/ 2053struct iwm_fw_paging_cmd { 2054 uint32_t flags; 2055 uint32_t block_size; 2056 uint32_t block_num; 2057 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2058} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2059 2060/* 2061 * Fw items ID's 2062 * 2063 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2064 * download 2065 */ 2066enum iwm_fw_item_id { 2067 IWM_FW_ITEM_ID_PAGING = 3, 2068}; 2069 2070/* 2071 * struct iwm_fw_get_item_cmd - get an item from the fw 2072 */ 2073struct iwm_fw_get_item_cmd { 2074 uint32_t item_id; 2075} __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2076 2077/** 2078 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2079 * @offset: offset in bytes into the section 2080 * @length: in bytes, either how much was written or read 2081 * @type: IWM_NVM_SECTION_TYPE_* 2082 * @status: 0 for success, fail otherwise 2083 * @data: if read operation, the data returned. Empty on write. 2084 */ 2085struct iwm_nvm_access_resp { 2086 uint16_t offset; 2087 uint16_t length; 2088 uint16_t type; 2089 uint16_t status; 2090 uint8_t data[]; 2091} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2092 2093/* IWM_MVM_ALIVE 0x1 */ 2094 2095/* alive response is_valid values */ 2096#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2097#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2098 2099/* alive response ver_type values */ 2100enum { 2101 IWM_FW_TYPE_HW = 0, 2102 IWM_FW_TYPE_PROT = 1, 2103 IWM_FW_TYPE_AP = 2, 2104 IWM_FW_TYPE_WOWLAN = 3, 2105 IWM_FW_TYPE_TIMING = 4, 2106 IWM_FW_TYPE_WIPAN = 5 2107}; 2108 2109/* alive response ver_subtype values */ 2110enum { 2111 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2112 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2113 IWM_FW_SUBTYPE_REDUCED = 2, 2114 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2115 IWM_FW_SUBTYPE_WOWLAN = 4, 2116 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2117 IWM_FW_SUBTYPE_WIPAN = 6, 2118 IWM_FW_SUBTYPE_INITIALIZE = 9 2119}; 2120 2121#define IWM_ALIVE_STATUS_ERR 0xDEAD 2122#define IWM_ALIVE_STATUS_OK 0xCAFE 2123 2124#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2125 2126struct iwm_mvm_alive_resp_ver1 { 2127 uint16_t status; 2128 uint16_t flags; 2129 uint8_t ucode_minor; 2130 uint8_t ucode_major; 2131 uint16_t id; 2132 uint8_t api_minor; 2133 uint8_t api_major; 2134 uint8_t ver_subtype; 2135 uint8_t ver_type; 2136 uint8_t mac; 2137 uint8_t opt; 2138 uint16_t reserved2; 2139 uint32_t timestamp; 2140 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2141 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2142 uint32_t cpu_register_ptr; 2143 uint32_t dbgm_config_ptr; 2144 uint32_t alive_counter_ptr; 2145 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2146} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2147 2148struct iwm_mvm_alive_resp_ver2 { 2149 uint16_t status; 2150 uint16_t flags; 2151 uint8_t ucode_minor; 2152 uint8_t ucode_major; 2153 uint16_t id; 2154 uint8_t api_minor; 2155 uint8_t api_major; 2156 uint8_t ver_subtype; 2157 uint8_t ver_type; 2158 uint8_t mac; 2159 uint8_t opt; 2160 uint16_t reserved2; 2161 uint32_t timestamp; 2162 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2163 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2164 uint32_t cpu_register_ptr; 2165 uint32_t dbgm_config_ptr; 2166 uint32_t alive_counter_ptr; 2167 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2168 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2169 uint32_t st_fwrd_size; 2170 uint8_t umac_minor; /* UMAC version: minor */ 2171 uint8_t umac_major; /* UMAC version: major */ 2172 uint16_t umac_id; /* UMAC version: id */ 2173 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2174 uint32_t dbg_print_buff_addr; 2175} __packed; /* ALIVE_RES_API_S_VER_2 */ 2176 2177struct iwm_mvm_alive_resp { 2178 uint16_t status; 2179 uint16_t flags; 2180 uint32_t ucode_minor; 2181 uint32_t ucode_major; 2182 uint8_t ver_subtype; 2183 uint8_t ver_type; 2184 uint8_t mac; 2185 uint8_t opt; 2186 uint32_t timestamp; 2187 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2188 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2189 uint32_t cpu_register_ptr; 2190 uint32_t dbgm_config_ptr; 2191 uint32_t alive_counter_ptr; 2192 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2193 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2194 uint32_t st_fwrd_size; 2195 uint32_t umac_minor; /* UMAC version: minor */ 2196 uint32_t umac_major; /* UMAC version: major */ 2197 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2198 uint32_t dbg_print_buff_addr; 2199} __packed; /* ALIVE_RES_API_S_VER_3 */ 2200 2201/* Error response/notification */ 2202enum { 2203 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2204 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2205 IWM_FW_ERR_SERVICE = 0x2, 2206 IWM_FW_ERR_ARC_MEMORY = 0x3, 2207 IWM_FW_ERR_ARC_CODE = 0x4, 2208 IWM_FW_ERR_WATCH_DOG = 0x5, 2209 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2210 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2211 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2212 IWM_FW_ERR_UNEXPECTED = 0xFE, 2213 IWM_FW_ERR_FATAL = 0xFF 2214}; 2215 2216/** 2217 * struct iwm_error_resp - FW error indication 2218 * ( IWM_REPLY_ERROR = 0x2 ) 2219 * @error_type: one of IWM_FW_ERR_* 2220 * @cmd_id: the command ID for which the error occurred 2221 * @bad_cmd_seq_num: sequence number of the erroneous command 2222 * @error_service: which service created the error, applicable only if 2223 * error_type = 2, otherwise 0 2224 * @timestamp: TSF in usecs. 2225 */ 2226struct iwm_error_resp { 2227 uint32_t error_type; 2228 uint8_t cmd_id; 2229 uint8_t reserved1; 2230 uint16_t bad_cmd_seq_num; 2231 uint32_t error_service; 2232 uint64_t timestamp; 2233} __packed; 2234 2235 2236/* Common PHY, MAC and Bindings definitions */ 2237 2238#define IWM_MAX_MACS_IN_BINDING (3) 2239#define IWM_MAX_BINDINGS (4) 2240#define IWM_AUX_BINDING_INDEX (3) 2241#define IWM_MAX_PHYS (4) 2242 2243/* Used to extract ID and color from the context dword */ 2244#define IWM_FW_CTXT_ID_POS (0) 2245#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2246#define IWM_FW_CTXT_COLOR_POS (8) 2247#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2248#define IWM_FW_CTXT_INVALID (0xffffffff) 2249 2250#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2251 (_color << IWM_FW_CTXT_COLOR_POS)) 2252 2253/* Possible actions on PHYs, MACs and Bindings */ 2254enum { 2255 IWM_FW_CTXT_ACTION_STUB = 0, 2256 IWM_FW_CTXT_ACTION_ADD, 2257 IWM_FW_CTXT_ACTION_MODIFY, 2258 IWM_FW_CTXT_ACTION_REMOVE, 2259 IWM_FW_CTXT_ACTION_NUM 2260}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2261 2262/* Time Events */ 2263 2264/* Time Event types, according to MAC type */ 2265enum iwm_time_event_type { 2266 /* BSS Station Events */ 2267 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2268 IWM_TE_BSS_STA_ASSOC, 2269 IWM_TE_BSS_EAP_DHCP_PROT, 2270 IWM_TE_BSS_QUIET_PERIOD, 2271 2272 /* P2P Device Events */ 2273 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2274 IWM_TE_P2P_DEVICE_LISTEN, 2275 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2276 IWM_TE_P2P_DEVICE_FULL_SCAN, 2277 2278 /* P2P Client Events */ 2279 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2280 IWM_TE_P2P_CLIENT_ASSOC, 2281 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2282 2283 /* P2P GO Events */ 2284 IWM_TE_P2P_GO_ASSOC_PROT, 2285 IWM_TE_P2P_GO_REPETITIVE_NOA, 2286 IWM_TE_P2P_GO_CT_WINDOW, 2287 2288 /* WiDi Sync Events */ 2289 IWM_TE_WIDI_TX_SYNC, 2290 2291 IWM_TE_MAX 2292}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2293 2294 2295 2296/* Time event - defines for command API v1 */ 2297 2298/* 2299 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2300 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2301 * the first fragment is scheduled. 2302 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2303 * the first 2 fragments are scheduled. 2304 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2305 * number of fragments are valid. 2306 * 2307 * Other than the constant defined above, specifying a fragmentation value 'x' 2308 * means that the event can be fragmented but only the first 'x' will be 2309 * scheduled. 2310 */ 2311enum { 2312 IWM_TE_V1_FRAG_NONE = 0, 2313 IWM_TE_V1_FRAG_SINGLE = 1, 2314 IWM_TE_V1_FRAG_DUAL = 2, 2315 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2316}; 2317 2318/* If a Time Event can be fragmented, this is the max number of fragments */ 2319#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2320/* Repeat the time event endlessly (until removed) */ 2321#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2322/* If a Time Event has bounded repetitions, this is the maximal value */ 2323#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2324 2325/* Time Event dependencies: none, on another TE, or in a specific time */ 2326enum { 2327 IWM_TE_V1_INDEPENDENT = 0, 2328 IWM_TE_V1_DEP_OTHER = (1 << 0), 2329 IWM_TE_V1_DEP_TSF = (1 << 1), 2330 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2331}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2332 2333/* 2334 * @IWM_TE_V1_NOTIF_NONE: no notifications 2335 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2336 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2337 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2338 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2339 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2340 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2341 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2342 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2343 * 2344 * Supported Time event notifications configuration. 2345 * A notification (both event and fragment) includes a status indicating weather 2346 * the FW was able to schedule the event or not. For fragment start/end 2347 * notification the status is always success. There is no start/end fragment 2348 * notification for monolithic events. 2349 */ 2350enum { 2351 IWM_TE_V1_NOTIF_NONE = 0, 2352 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2353 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2354 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2355 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2356 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2357 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2358 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2359 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2360 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2361}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2362 2363/* Time event - defines for command API */ 2364 2365/* 2366 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2367 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2368 * the first fragment is scheduled. 2369 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2370 * the first 2 fragments are scheduled. 2371 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2372 * number of fragments are valid. 2373 * 2374 * Other than the constant defined above, specifying a fragmentation value 'x' 2375 * means that the event can be fragmented but only the first 'x' will be 2376 * scheduled. 2377 */ 2378enum { 2379 IWM_TE_V2_FRAG_NONE = 0, 2380 IWM_TE_V2_FRAG_SINGLE = 1, 2381 IWM_TE_V2_FRAG_DUAL = 2, 2382 IWM_TE_V2_FRAG_MAX = 0xfe, 2383 IWM_TE_V2_FRAG_ENDLESS = 0xff 2384}; 2385 2386/* Repeat the time event endlessly (until removed) */ 2387#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2388/* If a Time Event has bounded repetitions, this is the maximal value */ 2389#define IWM_TE_V2_REPEAT_MAX 0xfe 2390 2391#define IWM_TE_V2_PLACEMENT_POS 12 2392#define IWM_TE_V2_ABSENCE_POS 15 2393 2394/* Time event policy values 2395 * A notification (both event and fragment) includes a status indicating weather 2396 * the FW was able to schedule the event or not. For fragment start/end 2397 * notification the status is always success. There is no start/end fragment 2398 * notification for monolithic events. 2399 * 2400 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2401 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2402 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2403 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2404 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2405 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2406 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2407 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2408 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2409 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2410 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2411 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2412 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2413 */ 2414enum { 2415 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2416 2417 /* notifications (event start/stop, fragment start/stop) */ 2418 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2419 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2420 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2421 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2422 2423 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2424 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2425 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2426 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2427 2428 IWM_TE_V2_NOTIF_MSK = 0xff, 2429 2430 /* placement characteristics */ 2431 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2432 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2433 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2434 2435 /* are we present or absent during the Time Event. */ 2436 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2437}; 2438 2439/** 2440 * struct iwm_time_event_cmd_api - configuring Time Events 2441 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2442 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2443 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2444 * @id_and_color: ID and color of the relevant MAC 2445 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2446 * @id: this field has two meanings, depending on the action: 2447 * If the action is ADD, then it means the type of event to add. 2448 * For all other actions it is the unique event ID assigned when the 2449 * event was added by the FW. 2450 * @apply_time: When to start the Time Event (in GP2) 2451 * @max_delay: maximum delay to event's start (apply time), in TU 2452 * @depends_on: the unique ID of the event we depend on (if any) 2453 * @interval: interval between repetitions, in TU 2454 * @duration: duration of event in TU 2455 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2456 * @max_frags: maximal number of fragments the Time Event can be divided to 2457 * @policy: defines whether uCode shall notify the host or other uCode modules 2458 * on event and/or fragment start and/or end 2459 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2460 * IWM_TE_EVENT_SOCIOPATHIC 2461 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2462 */ 2463struct iwm_time_event_cmd { 2464 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2465 uint32_t id_and_color; 2466 uint32_t action; 2467 uint32_t id; 2468 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2469 uint32_t apply_time; 2470 uint32_t max_delay; 2471 uint32_t depends_on; 2472 uint32_t interval; 2473 uint32_t duration; 2474 uint8_t repeat; 2475 uint8_t max_frags; 2476 uint16_t policy; 2477} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2478 2479/** 2480 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2481 * @status: bit 0 indicates success, all others specify errors 2482 * @id: the Time Event type 2483 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2484 * @id_and_color: ID and color of the relevant MAC 2485 */ 2486struct iwm_time_event_resp { 2487 uint32_t status; 2488 uint32_t id; 2489 uint32_t unique_id; 2490 uint32_t id_and_color; 2491} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2492 2493/** 2494 * struct iwm_time_event_notif - notifications of time event start/stop 2495 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2496 * @timestamp: action timestamp in GP2 2497 * @session_id: session's unique id 2498 * @unique_id: unique id of the Time Event itself 2499 * @id_and_color: ID and color of the relevant MAC 2500 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2501 * @status: true if scheduled, false otherwise (not executed) 2502 */ 2503struct iwm_time_event_notif { 2504 uint32_t timestamp; 2505 uint32_t session_id; 2506 uint32_t unique_id; 2507 uint32_t id_and_color; 2508 uint32_t action; 2509 uint32_t status; 2510} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2511 2512 2513/* Bindings and Time Quota */ 2514 2515/** 2516 * struct iwm_binding_cmd - configuring bindings 2517 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2518 * @id_and_color: ID and color of the relevant Binding 2519 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2520 * @macs: array of MAC id and colors which belong to the binding 2521 * @phy: PHY id and color which belongs to the binding 2522 */ 2523struct iwm_binding_cmd { 2524 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2525 uint32_t id_and_color; 2526 uint32_t action; 2527 /* IWM_BINDING_DATA_API_S_VER_1 */ 2528 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2529 uint32_t phy; 2530} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2531 2532/* The maximal number of fragments in the FW's schedule session */ 2533#define IWM_MVM_MAX_QUOTA 128 2534 2535/** 2536 * struct iwm_time_quota_data - configuration of time quota per binding 2537 * @id_and_color: ID and color of the relevant Binding 2538 * @quota: absolute time quota in TU. The scheduler will try to divide the 2539 * remainig quota (after Time Events) according to this quota. 2540 * @max_duration: max uninterrupted context duration in TU 2541 */ 2542struct iwm_time_quota_data { 2543 uint32_t id_and_color; 2544 uint32_t quota; 2545 uint32_t max_duration; 2546} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2547 2548/** 2549 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2550 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2551 * @quotas: allocations per binding 2552 */ 2553struct iwm_time_quota_cmd { 2554 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2555} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2556 2557 2558/* PHY context */ 2559 2560/* Supported bands */ 2561#define IWM_PHY_BAND_5 (0) 2562#define IWM_PHY_BAND_24 (1) 2563 2564/* Supported channel width, vary if there is VHT support */ 2565#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2566#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2567#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2568#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2569 2570/* 2571 * Control channel position: 2572 * For legacy set bit means upper channel, otherwise lower. 2573 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2574 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2575 * center_freq 2576 * | 2577 * 40Mhz |_______|_______| 2578 * 80Mhz |_______|_______|_______|_______| 2579 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2580 * code 011 010 001 000 | 100 101 110 111 2581 */ 2582#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2583#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2584#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2585#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2586#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2587#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2588#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2589#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2590 2591/* 2592 * @band: IWM_PHY_BAND_* 2593 * @channel: channel number 2594 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2595 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2596 */ 2597struct iwm_fw_channel_info { 2598 uint8_t band; 2599 uint8_t channel; 2600 uint8_t width; 2601 uint8_t ctrl_pos; 2602} __packed; 2603 2604#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2605#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2606 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2607#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2608#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2609 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2610#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2611#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2612 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2613#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2614#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2615 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2616#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2617#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2618 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2619#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2620#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2621 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2622#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2623#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2624 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2625 2626/* TODO: fix the value, make it depend on firmware at runtime? */ 2627#define IWM_NUM_PHY_CTX 3 2628 2629/* TODO: complete missing documentation */ 2630/** 2631 * struct iwm_phy_context_cmd - config of the PHY context 2632 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2633 * @id_and_color: ID and color of the relevant Binding 2634 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2635 * @apply_time: 0 means immediate apply and context switch. 2636 * other value means apply new params after X usecs 2637 * @tx_param_color: ??? 2638 * @channel_info: 2639 * @txchain_info: ??? 2640 * @rxchain_info: ??? 2641 * @acquisition_data: ??? 2642 * @dsp_cfg_flags: set to 0 2643 */ 2644struct iwm_phy_context_cmd { 2645 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2646 uint32_t id_and_color; 2647 uint32_t action; 2648 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2649 uint32_t apply_time; 2650 uint32_t tx_param_color; 2651 struct iwm_fw_channel_info ci; 2652 uint32_t txchain_info; 2653 uint32_t rxchain_info; 2654 uint32_t acquisition_data; 2655 uint32_t dsp_cfg_flags; 2656} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2657 2658#define IWM_RX_INFO_PHY_CNT 8 2659#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2660#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2661#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2662#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2663#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2664#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2665#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2666 2667#define IWM_RX_INFO_AGC_IDX 1 2668#define IWM_RX_INFO_RSSI_AB_IDX 2 2669#define IWM_OFDM_AGC_A_MSK 0x0000007f 2670#define IWM_OFDM_AGC_A_POS 0 2671#define IWM_OFDM_AGC_B_MSK 0x00003f80 2672#define IWM_OFDM_AGC_B_POS 7 2673#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2674#define IWM_OFDM_AGC_CODE_POS 20 2675#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2676#define IWM_OFDM_RSSI_A_POS 0 2677#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2678#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2679#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2680#define IWM_OFDM_RSSI_B_POS 16 2681#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2682#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2683 2684/** 2685 * struct iwm_rx_phy_info - phy info 2686 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2687 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2688 * @cfg_phy_cnt: configurable DSP phy data byte count 2689 * @stat_id: configurable DSP phy data set ID 2690 * @reserved1: 2691 * @system_timestamp: GP2 at on air rise 2692 * @timestamp: TSF at on air rise 2693 * @beacon_time_stamp: beacon at on-air rise 2694 * @phy_flags: general phy flags: band, modulation, ... 2695 * @channel: channel number 2696 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2697 * @rate_n_flags: IWM_RATE_MCS_* 2698 * @byte_count: frame's byte-count 2699 * @frame_time: frame's time on the air, based on byte count and frame rate 2700 * calculation 2701 * @mac_active_msk: what MACs were active when the frame was received 2702 * 2703 * Before each Rx, the device sends this data. It contains PHY information 2704 * about the reception of the packet. 2705 */ 2706struct iwm_rx_phy_info { 2707 uint8_t non_cfg_phy_cnt; 2708 uint8_t cfg_phy_cnt; 2709 uint8_t stat_id; 2710 uint8_t reserved1; 2711 uint32_t system_timestamp; 2712 uint64_t timestamp; 2713 uint32_t beacon_time_stamp; 2714 uint16_t phy_flags; 2715#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2716 uint16_t channel; 2717 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2718 uint8_t rate; 2719 uint8_t rflags; 2720 uint16_t xrflags; 2721 uint32_t byte_count; 2722 uint16_t mac_active_msk; 2723 uint16_t frame_time; 2724} __packed; 2725 2726struct iwm_rx_mpdu_res_start { 2727 uint16_t byte_count; 2728 uint16_t reserved; 2729} __packed; 2730 2731/** 2732 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2733 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2734 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2735 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2736 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2737 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2738 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2739 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2740 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2741 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2742 */ 2743enum iwm_rx_phy_flags { 2744 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2745 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2746 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2747 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2748 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2749 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2750 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2751 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2752 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2753 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2754}; 2755 2756/** 2757 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2758 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2759 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2760 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2761 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2762 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2763 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2764 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2765 * in the driver. 2766 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2767 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2768 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2769 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2770 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2771 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2772 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2773 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2774 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2775 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2776 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2777 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2778 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2779 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2780 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2781 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2782 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2783 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2784 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2785 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2786 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2787 */ 2788enum iwm_mvm_rx_status { 2789 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2790 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2791 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2792 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2793 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2794 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2795 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2796 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2797 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2798 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2799 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2800 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2801 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2802 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2803 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2804 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2805 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2806 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2807 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2808 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2809 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2810 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2811 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2812 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2813 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2814 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2815 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2816}; 2817 2818/** 2819 * struct iwm_radio_version_notif - information on the radio version 2820 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2821 * @radio_flavor: 2822 * @radio_step: 2823 * @radio_dash: 2824 */ 2825struct iwm_radio_version_notif { 2826 uint32_t radio_flavor; 2827 uint32_t radio_step; 2828 uint32_t radio_dash; 2829} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2830 2831enum iwm_card_state_flags { 2832 IWM_CARD_ENABLED = 0x00, 2833 IWM_HW_CARD_DISABLED = 0x01, 2834 IWM_SW_CARD_DISABLED = 0x02, 2835 IWM_CT_KILL_CARD_DISABLED = 0x04, 2836 IWM_HALT_CARD_DISABLED = 0x08, 2837 IWM_CARD_DISABLED_MSK = 0x0f, 2838 IWM_CARD_IS_RX_ON = 0x10, 2839}; 2840 2841/** 2842 * struct iwm_radio_version_notif - information on the radio version 2843 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2844 * @flags: %iwm_card_state_flags 2845 */ 2846struct iwm_card_state_notif { 2847 uint32_t flags; 2848} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2849 2850/** 2851 * struct iwm_missed_beacons_notif - information on missed beacons 2852 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2853 * @mac_id: interface ID 2854 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2855 * beacons since last RX. 2856 * @consec_missed_beacons: number of consecutive missed beacons 2857 * @num_expected_beacons: 2858 * @num_recvd_beacons: 2859 */ 2860struct iwm_missed_beacons_notif { 2861 uint32_t mac_id; 2862 uint32_t consec_missed_beacons_since_last_rx; 2863 uint32_t consec_missed_beacons; 2864 uint32_t num_expected_beacons; 2865 uint32_t num_recvd_beacons; 2866} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2867 2868/** 2869 * struct iwm_mfuart_load_notif - mfuart image version & status 2870 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2871 * @installed_ver: installed image version 2872 * @external_ver: external image version 2873 * @status: MFUART loading status 2874 * @duration: MFUART loading time 2875*/ 2876struct iwm_mfuart_load_notif { 2877 uint32_t installed_ver; 2878 uint32_t external_ver; 2879 uint32_t status; 2880 uint32_t duration; 2881} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2882 2883/** 2884 * struct iwm_set_calib_default_cmd - set default value for calibration. 2885 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2886 * @calib_index: the calibration to set value for 2887 * @length: of data 2888 * @data: the value to set for the calibration result 2889 */ 2890struct iwm_set_calib_default_cmd { 2891 uint16_t calib_index; 2892 uint16_t length; 2893 uint8_t data[0]; 2894} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2895 2896#define IWM_MAX_PORT_ID_NUM 2 2897#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2898 2899/** 2900 * struct iwm_mcast_filter_cmd - configure multicast filter. 2901 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2902 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2903 * to identify network interface adopted in host-device IF. 2904 * It is used by FW as index in array of addresses. This array has 2905 * IWM_MAX_PORT_ID_NUM members. 2906 * @count: Number of MAC addresses in the array 2907 * @pass_all: Set 1 to pass all multicast packets. 2908 * @bssid: current association BSSID. 2909 * @addr_list: Place holder for array of MAC addresses. 2910 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2911 */ 2912struct iwm_mcast_filter_cmd { 2913 uint8_t filter_own; 2914 uint8_t port_id; 2915 uint8_t count; 2916 uint8_t pass_all; 2917 uint8_t bssid[6]; 2918 uint8_t reserved[2]; 2919 uint8_t addr_list[0]; 2920} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2921 2922struct iwm_mvm_statistics_dbg { 2923 uint32_t burst_check; 2924 uint32_t burst_count; 2925 uint32_t wait_for_silence_timeout_cnt; 2926 uint32_t reserved[3]; 2927} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2928 2929struct iwm_mvm_statistics_div { 2930 uint32_t tx_on_a; 2931 uint32_t tx_on_b; 2932 uint32_t exec_time; 2933 uint32_t probe_time; 2934 uint32_t rssi_ant; 2935 uint32_t reserved2; 2936} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2937 2938struct iwm_mvm_statistics_general_common { 2939 uint32_t temperature; /* radio temperature */ 2940 uint32_t temperature_m; /* radio voltage */ 2941 struct iwm_mvm_statistics_dbg dbg; 2942 uint32_t sleep_time; 2943 uint32_t slots_out; 2944 uint32_t slots_idle; 2945 uint32_t ttl_timestamp; 2946 struct iwm_mvm_statistics_div div; 2947 uint32_t rx_enable_counter; 2948 /* 2949 * num_of_sos_states: 2950 * count the number of times we have to re-tune 2951 * in order to get out of bad PHY status 2952 */ 2953 uint32_t num_of_sos_states; 2954} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 2955 2956struct iwm_mvm_statistics_rx_non_phy { 2957 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2958 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2959 uint32_t non_bssid_frames; /* number of frames with BSSID that 2960 * doesn't belong to the STA BSSID */ 2961 uint32_t filtered_frames; /* count frames that were dumped in the 2962 * filtering process */ 2963 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2964 * our serving channel */ 2965 uint32_t channel_beacons; /* beacons with our bss id and in our 2966 * serving channel */ 2967 uint32_t num_missed_bcon; /* number of missed beacons */ 2968 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2969 * ADC was in saturation */ 2970 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2971 * for INA */ 2972 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2973 uint32_t interference_data_flag; /* flag for interference data 2974 * availability. 1 when data is 2975 * available. */ 2976 uint32_t channel_load; /* counts RX Enable time in uSec */ 2977 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2978 * and CCK) counter */ 2979 uint32_t beacon_rssi_a; 2980 uint32_t beacon_rssi_b; 2981 uint32_t beacon_rssi_c; 2982 uint32_t beacon_energy_a; 2983 uint32_t beacon_energy_b; 2984 uint32_t beacon_energy_c; 2985 uint32_t num_bt_kills; 2986 uint32_t mac_id; 2987 uint32_t directed_data_mpdu; 2988} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2989 2990struct iwm_mvm_statistics_rx_phy { 2991 uint32_t ina_cnt; 2992 uint32_t fina_cnt; 2993 uint32_t plcp_err; 2994 uint32_t crc32_err; 2995 uint32_t overrun_err; 2996 uint32_t early_overrun_err; 2997 uint32_t crc32_good; 2998 uint32_t false_alarm_cnt; 2999 uint32_t fina_sync_err_cnt; 3000 uint32_t sfd_timeout; 3001 uint32_t fina_timeout; 3002 uint32_t unresponded_rts; 3003 uint32_t rxe_frame_limit_overrun; 3004 uint32_t sent_ack_cnt; 3005 uint32_t sent_cts_cnt; 3006 uint32_t sent_ba_rsp_cnt; 3007 uint32_t dsp_self_kill; 3008 uint32_t mh_format_err; 3009 uint32_t re_acq_main_rssi_sum; 3010 uint32_t reserved; 3011} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3012 3013struct iwm_mvm_statistics_rx_ht_phy { 3014 uint32_t plcp_err; 3015 uint32_t overrun_err; 3016 uint32_t early_overrun_err; 3017 uint32_t crc32_good; 3018 uint32_t crc32_err; 3019 uint32_t mh_format_err; 3020 uint32_t agg_crc32_good; 3021 uint32_t agg_mpdu_cnt; 3022 uint32_t agg_cnt; 3023 uint32_t unsupport_mcs; 3024} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3025 3026#define IWM_MAX_CHAINS 3 3027 3028struct iwm_mvm_statistics_tx_non_phy_agg { 3029 uint32_t ba_timeout; 3030 uint32_t ba_reschedule_frames; 3031 uint32_t scd_query_agg_frame_cnt; 3032 uint32_t scd_query_no_agg; 3033 uint32_t scd_query_agg; 3034 uint32_t scd_query_mismatch; 3035 uint32_t frame_not_ready; 3036 uint32_t underrun; 3037 uint32_t bt_prio_kill; 3038 uint32_t rx_ba_rsp_cnt; 3039 int8_t txpower[IWM_MAX_CHAINS]; 3040 int8_t reserved; 3041 uint32_t reserved2; 3042} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3043 3044struct iwm_mvm_statistics_tx_channel_width { 3045 uint32_t ext_cca_narrow_ch20[1]; 3046 uint32_t ext_cca_narrow_ch40[2]; 3047 uint32_t ext_cca_narrow_ch80[3]; 3048 uint32_t ext_cca_narrow_ch160[4]; 3049 uint32_t last_tx_ch_width_indx; 3050 uint32_t rx_detected_per_ch_width[4]; 3051 uint32_t success_per_ch_width[4]; 3052 uint32_t fail_per_ch_width[4]; 3053}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3054 3055struct iwm_mvm_statistics_tx { 3056 uint32_t preamble_cnt; 3057 uint32_t rx_detected_cnt; 3058 uint32_t bt_prio_defer_cnt; 3059 uint32_t bt_prio_kill_cnt; 3060 uint32_t few_bytes_cnt; 3061 uint32_t cts_timeout; 3062 uint32_t ack_timeout; 3063 uint32_t expected_ack_cnt; 3064 uint32_t actual_ack_cnt; 3065 uint32_t dump_msdu_cnt; 3066 uint32_t burst_abort_next_frame_mismatch_cnt; 3067 uint32_t burst_abort_missing_next_frame_cnt; 3068 uint32_t cts_timeout_collision; 3069 uint32_t ack_or_ba_timeout_collision; 3070 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3071 struct iwm_mvm_statistics_tx_channel_width channel_width; 3072} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3073 3074 3075struct iwm_mvm_statistics_bt_activity { 3076 uint32_t hi_priority_tx_req_cnt; 3077 uint32_t hi_priority_tx_denied_cnt; 3078 uint32_t lo_priority_tx_req_cnt; 3079 uint32_t lo_priority_tx_denied_cnt; 3080 uint32_t hi_priority_rx_req_cnt; 3081 uint32_t hi_priority_rx_denied_cnt; 3082 uint32_t lo_priority_rx_req_cnt; 3083 uint32_t lo_priority_rx_denied_cnt; 3084} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3085 3086struct iwm_mvm_statistics_general { 3087 struct iwm_mvm_statistics_general_common common; 3088 uint32_t beacon_filtered; 3089 uint32_t missed_beacons; 3090 int8_t beacon_filter_average_energy; 3091 int8_t beacon_filter_reason; 3092 int8_t beacon_filter_current_energy; 3093 int8_t beacon_filter_reserved; 3094 uint32_t beacon_filter_delta_time; 3095 struct iwm_mvm_statistics_bt_activity bt_activity; 3096} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3097 3098struct iwm_mvm_statistics_rx { 3099 struct iwm_mvm_statistics_rx_phy ofdm; 3100 struct iwm_mvm_statistics_rx_phy cck; 3101 struct iwm_mvm_statistics_rx_non_phy general; 3102 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3103} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3104 3105/* 3106 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3107 * 3108 * By default, uCode issues this notification after receiving a beacon 3109 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3110 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3111 * 3112 * Statistics counters continue to increment beacon after beacon, but are 3113 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3114 * 0x9c with CLEAR_STATS bit set (see above). 3115 * 3116 * uCode also issues this notification during scans. uCode clears statistics 3117 * appropriately so that each notification contains statistics for only the 3118 * one channel that has just been scanned. 3119 */ 3120 3121struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3122 uint32_t flag; 3123 struct iwm_mvm_statistics_rx rx; 3124 struct iwm_mvm_statistics_tx tx; 3125 struct iwm_mvm_statistics_general general; 3126} __packed; 3127 3128/*********************************** 3129 * Smart Fifo API 3130 ***********************************/ 3131/* Smart Fifo state */ 3132enum iwm_sf_state { 3133 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3134 IWM_SF_FULL_ON, 3135 IWM_SF_UNINIT, 3136 IWM_SF_INIT_OFF, 3137 IWM_SF_HW_NUM_STATES 3138}; 3139 3140/* Smart Fifo possible scenario */ 3141enum iwm_sf_scenario { 3142 IWM_SF_SCENARIO_SINGLE_UNICAST, 3143 IWM_SF_SCENARIO_AGG_UNICAST, 3144 IWM_SF_SCENARIO_MULTICAST, 3145 IWM_SF_SCENARIO_BA_RESP, 3146 IWM_SF_SCENARIO_TX_RESP, 3147 IWM_SF_NUM_SCENARIO 3148}; 3149 3150#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3151#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3152 3153/* smart FIFO default values */ 3154#define IWM_SF_W_MARK_SISO 4096 3155#define IWM_SF_W_MARK_MIMO2 8192 3156#define IWM_SF_W_MARK_MIMO3 6144 3157#define IWM_SF_W_MARK_LEGACY 4096 3158#define IWM_SF_W_MARK_SCAN 4096 3159 3160/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3161#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3162#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3163#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3164#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3165#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3166#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3167#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3168#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3169#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3170#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3171 3172/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3173#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3174#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3175#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3176#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3177#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3178#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3179#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3180#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3181#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3182#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3183 3184#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3185 3186#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3187 3188/** 3189 * Smart Fifo configuration command. 3190 * @state: smart fifo state, types listed in iwm_sf_state. 3191 * @watermark: Minimum allowed available free space in RXF for transient state. 3192 * @long_delay_timeouts: aging and idle timer values for each scenario 3193 * in long delay state. 3194 * @full_on_timeouts: timer values for each scenario in full on state. 3195 */ 3196struct iwm_sf_cfg_cmd { 3197 uint32_t state; 3198 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3199 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3200 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3201} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3202 3203/* 3204 * END mvm/fw-api.h 3205 */ 3206 3207/* 3208 * BEGIN mvm/fw-api-mac.h 3209 */ 3210 3211/* 3212 * The first MAC indices (starting from 0) 3213 * are available to the driver, AUX follows 3214 */ 3215#define IWM_MAC_INDEX_AUX 4 3216#define IWM_MAC_INDEX_MIN_DRIVER 0 3217#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3218 3219enum iwm_ac { 3220 IWM_AC_BK, 3221 IWM_AC_BE, 3222 IWM_AC_VI, 3223 IWM_AC_VO, 3224 IWM_AC_NUM, 3225}; 3226 3227/** 3228 * enum iwm_mac_protection_flags - MAC context flags 3229 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3230 * this will require CCK RTS/CTS2self. 3231 * RTS/CTS will protect full burst time. 3232 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3233 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3234 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3235 */ 3236enum iwm_mac_protection_flags { 3237 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3238 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3239 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3240 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3241}; 3242 3243#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3244#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3245 3246/** 3247 * enum iwm_mac_types - Supported MAC types 3248 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3249 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3250 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3251 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3252 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3253 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3254 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3255 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3256 * @IWM_FW_MAC_TYPE_GO: P2P GO 3257 * @IWM_FW_MAC_TYPE_TEST: ? 3258 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3259 */ 3260enum iwm_mac_types { 3261 IWM_FW_MAC_TYPE_FIRST = 1, 3262 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3263 IWM_FW_MAC_TYPE_LISTENER, 3264 IWM_FW_MAC_TYPE_PIBSS, 3265 IWM_FW_MAC_TYPE_IBSS, 3266 IWM_FW_MAC_TYPE_BSS_STA, 3267 IWM_FW_MAC_TYPE_P2P_DEVICE, 3268 IWM_FW_MAC_TYPE_P2P_STA, 3269 IWM_FW_MAC_TYPE_GO, 3270 IWM_FW_MAC_TYPE_TEST, 3271 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3272}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3273 3274/** 3275 * enum iwm_tsf_id - TSF hw timer ID 3276 * @IWM_TSF_ID_A: use TSF A 3277 * @IWM_TSF_ID_B: use TSF B 3278 * @IWM_TSF_ID_C: use TSF C 3279 * @IWM_TSF_ID_D: use TSF D 3280 * @IWM_NUM_TSF_IDS: number of TSF timers available 3281 */ 3282enum iwm_tsf_id { 3283 IWM_TSF_ID_A = 0, 3284 IWM_TSF_ID_B = 1, 3285 IWM_TSF_ID_C = 2, 3286 IWM_TSF_ID_D = 3, 3287 IWM_NUM_TSF_IDS = 4, 3288}; /* IWM_TSF_ID_API_E_VER_1 */ 3289 3290/** 3291 * struct iwm_mac_data_ap - configuration data for AP MAC context 3292 * @beacon_time: beacon transmit time in system time 3293 * @beacon_tsf: beacon transmit time in TSF 3294 * @bi: beacon interval in TU 3295 * @bi_reciprocal: 2^32 / bi 3296 * @dtim_interval: dtim transmit time in TU 3297 * @dtim_reciprocal: 2^32 / dtim_interval 3298 * @mcast_qid: queue ID for multicast traffic 3299 * @beacon_template: beacon template ID 3300 */ 3301struct iwm_mac_data_ap { 3302 uint32_t beacon_time; 3303 uint64_t beacon_tsf; 3304 uint32_t bi; 3305 uint32_t bi_reciprocal; 3306 uint32_t dtim_interval; 3307 uint32_t dtim_reciprocal; 3308 uint32_t mcast_qid; 3309 uint32_t beacon_template; 3310} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3311 3312/** 3313 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3314 * @beacon_time: beacon transmit time in system time 3315 * @beacon_tsf: beacon transmit time in TSF 3316 * @bi: beacon interval in TU 3317 * @bi_reciprocal: 2^32 / bi 3318 * @beacon_template: beacon template ID 3319 */ 3320struct iwm_mac_data_ibss { 3321 uint32_t beacon_time; 3322 uint64_t beacon_tsf; 3323 uint32_t bi; 3324 uint32_t bi_reciprocal; 3325 uint32_t beacon_template; 3326} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3327 3328/** 3329 * struct iwm_mac_data_sta - configuration data for station MAC context 3330 * @is_assoc: 1 for associated state, 0 otherwise 3331 * @dtim_time: DTIM arrival time in system time 3332 * @dtim_tsf: DTIM arrival time in TSF 3333 * @bi: beacon interval in TU, applicable only when associated 3334 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3335 * @dtim_interval: DTIM interval in TU, applicable only when associated 3336 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3337 * @listen_interval: in beacon intervals, applicable only when associated 3338 * @assoc_id: unique ID assigned by the AP during association 3339 */ 3340struct iwm_mac_data_sta { 3341 uint32_t is_assoc; 3342 uint32_t dtim_time; 3343 uint64_t dtim_tsf; 3344 uint32_t bi; 3345 uint32_t bi_reciprocal; 3346 uint32_t dtim_interval; 3347 uint32_t dtim_reciprocal; 3348 uint32_t listen_interval; 3349 uint32_t assoc_id; 3350 uint32_t assoc_beacon_arrive_time; 3351} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3352 3353/** 3354 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3355 * @ap: iwm_mac_data_ap struct with most config data 3356 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3357 * 0 indicates that there is no CT window. 3358 * @opp_ps_enabled: indicate that opportunistic PS allowed 3359 */ 3360struct iwm_mac_data_go { 3361 struct iwm_mac_data_ap ap; 3362 uint32_t ctwin; 3363 uint32_t opp_ps_enabled; 3364} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3365 3366/** 3367 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3368 * @sta: iwm_mac_data_sta struct with most config data 3369 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3370 * 0 indicates that there is no CT window. 3371 */ 3372struct iwm_mac_data_p2p_sta { 3373 struct iwm_mac_data_sta sta; 3374 uint32_t ctwin; 3375} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3376 3377/** 3378 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3379 * @stats_interval: interval in TU between statistics notifications to host. 3380 */ 3381struct iwm_mac_data_pibss { 3382 uint32_t stats_interval; 3383} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3384 3385/* 3386 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3387 * context. 3388 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3389 * other channels as well. This should be to true only in case that the 3390 * device is discoverable and there is an active GO. Note that setting this 3391 * field when not needed, will increase the number of interrupts and have 3392 * effect on the platform power, as this setting opens the Rx filters on 3393 * all macs. 3394 */ 3395struct iwm_mac_data_p2p_dev { 3396 uint32_t is_disc_extended; 3397} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3398 3399/** 3400 * enum iwm_mac_filter_flags - MAC context filter flags 3401 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3402 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3403 * control frames to the host 3404 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3405 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3406 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3407 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3408 * (in station mode when associated) 3409 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3410 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3411 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3412 */ 3413enum iwm_mac_filter_flags { 3414 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3415 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3416 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3417 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3418 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3419 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3420 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3421 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3422 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3423}; 3424 3425/** 3426 * enum iwm_mac_qos_flags - QoS flags 3427 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3428 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3429 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3430 * 3431 */ 3432enum iwm_mac_qos_flags { 3433 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3434 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3435 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3436}; 3437 3438/** 3439 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3440 * @cw_min: Contention window, start value in numbers of slots. 3441 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3442 * @cw_max: Contention window, max value in numbers of slots. 3443 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3444 * @aifsn: Number of slots in Arbitration Interframe Space (before 3445 * performing random backoff timing prior to Tx). Device default 1. 3446 * @fifos_mask: FIFOs used by this MAC for this AC 3447 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3448 * 3449 * One instance of this config struct for each of 4 EDCA access categories 3450 * in struct iwm_qosparam_cmd. 3451 * 3452 * Device will automatically increase contention window by (2*CW) + 1 for each 3453 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3454 * value, to cap the CW value. 3455 */ 3456struct iwm_ac_qos { 3457 uint16_t cw_min; 3458 uint16_t cw_max; 3459 uint8_t aifsn; 3460 uint8_t fifos_mask; 3461 uint16_t edca_txop; 3462} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3463 3464/** 3465 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3466 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3467 * @id_and_color: ID and color of the MAC 3468 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3469 * @mac_type: one of IWM_FW_MAC_TYPE_* 3470 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3471 * @node_addr: MAC address 3472 * @bssid_addr: BSSID 3473 * @cck_rates: basic rates available for CCK 3474 * @ofdm_rates: basic rates available for OFDM 3475 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3476 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3477 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3478 * @filter_flags: combination of IWM_MAC_FILTER_* 3479 * @qos_flags: from IWM_MAC_QOS_FLG_* 3480 * @ac: one iwm_mac_qos configuration for each AC 3481 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3482 */ 3483struct iwm_mac_ctx_cmd { 3484 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3485 uint32_t id_and_color; 3486 uint32_t action; 3487 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3488 uint32_t mac_type; 3489 uint32_t tsf_id; 3490 uint8_t node_addr[6]; 3491 uint16_t reserved_for_node_addr; 3492 uint8_t bssid_addr[6]; 3493 uint16_t reserved_for_bssid_addr; 3494 uint32_t cck_rates; 3495 uint32_t ofdm_rates; 3496 uint32_t protection_flags; 3497 uint32_t cck_short_preamble; 3498 uint32_t short_slot; 3499 uint32_t filter_flags; 3500 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3501 uint32_t qos_flags; 3502 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3503 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3504 union { 3505 struct iwm_mac_data_ap ap; 3506 struct iwm_mac_data_go go; 3507 struct iwm_mac_data_sta sta; 3508 struct iwm_mac_data_p2p_sta p2p_sta; 3509 struct iwm_mac_data_p2p_dev p2p_dev; 3510 struct iwm_mac_data_pibss pibss; 3511 struct iwm_mac_data_ibss ibss; 3512 }; 3513} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3514 3515static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3516{ 3517 if (!v) 3518 return 0; 3519 return 0xFFFFFFFF / v; 3520} 3521 3522#define IWM_NONQOS_SEQ_GET 0x1 3523#define IWM_NONQOS_SEQ_SET 0x2 3524struct iwm_nonqos_seq_query_cmd { 3525 uint32_t get_set_flag; 3526 uint32_t mac_id_n_color; 3527 uint16_t value; 3528 uint16_t reserved; 3529} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3530 3531/* 3532 * END mvm/fw-api-mac.h 3533 */ 3534 3535/* 3536 * BEGIN mvm/fw-api-power.h 3537 */ 3538 3539/* Power Management Commands, Responses, Notifications */ 3540 3541/* Radio LP RX Energy Threshold measured in dBm */ 3542#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3543#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3544#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3545 3546/** 3547 * enum iwm_scan_flags - masks for power table command flags 3548 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3549 * receiver and transmitter. '0' - does not allow. 3550 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3551 * '1' Driver enables PM (use rest of parameters) 3552 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3553 * '1' PM could sleep over DTIM till listen Interval. 3554 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3555 * access categories are both delivery and trigger enabled. 3556 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3557 * PBW Snoozing enabled 3558 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3559 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3560 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3561 * detection enablement 3562*/ 3563enum iwm_power_flags { 3564 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3565 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3566 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3567 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3568 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3569 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3570 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3571 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3572}; 3573 3574#define IWM_POWER_VEC_SIZE 5 3575 3576/** 3577 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3578 * is used also with a new power API for device wide power settings. 3579 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3580 * 3581 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3582 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3583 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3584 * set regardless of power scheme or current power state. 3585 * FW use this value also when PM is disabled. 3586 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3587 * PSM transition - legacy PM 3588 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3589 * PSM transition - legacy PM 3590 * @sleep_interval: not in use 3591 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3592 * is set. For example, if it is required to skip over 3593 * one DTIM, this value need to be set to 2 (DTIM periods). 3594 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3595 * Default: 80dbm 3596 */ 3597struct iwm_powertable_cmd { 3598 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3599 uint16_t flags; 3600 uint8_t keep_alive_seconds; 3601 uint8_t debug_flags; 3602 uint32_t rx_data_timeout; 3603 uint32_t tx_data_timeout; 3604 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3605 uint32_t skip_dtim_periods; 3606 uint32_t lprx_rssi_threshold; 3607} __packed; 3608 3609/** 3610 * enum iwm_device_power_flags - masks for device power command flags 3611 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3612 * receiver and transmitter. '0' - does not allow. 3613 */ 3614enum iwm_device_power_flags { 3615 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3616}; 3617 3618/** 3619 * struct iwm_device_power_cmd - device wide power command. 3620 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3621 * 3622 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3623 */ 3624struct iwm_device_power_cmd { 3625 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3626 uint16_t flags; 3627 uint16_t reserved; 3628} __packed; 3629 3630/** 3631 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3632 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3633 * @id_and_color: MAC contex identifier 3634 * @flags: Power table command flags from POWER_FLAGS_* 3635 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3636 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3637 * set regardless of power scheme or current power state. 3638 * FW use this value also when PM is disabled. 3639 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3640 * PSM transition - legacy PM 3641 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3642 * PSM transition - legacy PM 3643 * @sleep_interval: not in use 3644 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3645 * is set. For example, if it is required to skip over 3646 * one DTIM, this value need to be set to 2 (DTIM periods). 3647 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3648 * PSM transition - uAPSD 3649 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3650 * PSM transition - uAPSD 3651 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3652 * Default: 80dbm 3653 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3654 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3655 * from the AP [msec] 3656 * @snooze_window: A window of time in which PBW snoozing insures that all 3657 * packets received. It is also the minimum time from last 3658 * received unicast RX packet, before client stops snoozing 3659 * for data. [msec] 3660 * @snooze_step: TBD 3661 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3662 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3663 * each corresponding AC. 3664 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3665 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3666 * values. 3667 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3668 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3669 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3670 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3671 * @limited_ps_threshold: 3672*/ 3673struct iwm_mac_power_cmd { 3674 /* CONTEXT_DESC_API_T_VER_1 */ 3675 uint32_t id_and_color; 3676 3677 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3678 uint16_t flags; 3679 uint16_t keep_alive_seconds; 3680 uint32_t rx_data_timeout; 3681 uint32_t tx_data_timeout; 3682 uint32_t rx_data_timeout_uapsd; 3683 uint32_t tx_data_timeout_uapsd; 3684 uint8_t lprx_rssi_threshold; 3685 uint8_t skip_dtim_periods; 3686 uint16_t snooze_interval; 3687 uint16_t snooze_window; 3688 uint8_t snooze_step; 3689 uint8_t qndp_tid; 3690 uint8_t uapsd_ac_flags; 3691 uint8_t uapsd_max_sp; 3692 uint8_t heavy_tx_thld_packets; 3693 uint8_t heavy_rx_thld_packets; 3694 uint8_t heavy_tx_thld_percentage; 3695 uint8_t heavy_rx_thld_percentage; 3696 uint8_t limited_ps_threshold; 3697 uint8_t reserved; 3698} __packed; 3699 3700/* 3701 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3702 * associated AP is identified as improperly implementing uAPSD protocol. 3703 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3704 * @sta_id: index of station in uCode's station table - associated AP ID in 3705 * this context. 3706 */ 3707struct iwm_uapsd_misbehaving_ap_notif { 3708 uint32_t sta_id; 3709 uint8_t mac_id; 3710 uint8_t reserved[3]; 3711} __packed; 3712 3713/** 3714 * struct iwm_beacon_filter_cmd 3715 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3716 * @id_and_color: MAC contex identifier 3717 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3718 * to driver if delta in Energy values calculated for this and last 3719 * passed beacon is greater than this threshold. Zero value means that 3720 * the Energy change is ignored for beacon filtering, and beacon will 3721 * not be forced to be sent to driver regardless of this delta. Typical 3722 * energy delta 5dB. 3723 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3724 * Send beacon to driver if delta in Energy values calculated for this 3725 * and last passed beacon is greater than this threshold. Zero value 3726 * means that the Energy change is ignored for beacon filtering while in 3727 * Roaming state, typical energy delta 1dB. 3728 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3729 * calculated for current beacon is less than the threshold, use 3730 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3731 * Threshold. Typical energy threshold is -72dBm. 3732 * @bf_temp_threshold: This threshold determines the type of temperature 3733 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3734 * If the current temperature is above this threshold - Fast filter 3735 * will be used, If the current temperature is below this threshold - 3736 * Slow filter will be used. 3737 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3738 * calculated for this and the last passed beacon is greater than this 3739 * threshold. Zero value means that the temperature change is ignored for 3740 * beacon filtering; beacons will not be forced to be sent to driver 3741 * regardless of whether its temperature has been changed. 3742 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3743 * calculated for this and the last passed beacon is greater than this 3744 * threshold. Zero value means that the temperature change is ignored for 3745 * beacon filtering; beacons will not be forced to be sent to driver 3746 * regardless of whether its temperature has been changed. 3747 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3748 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3749 * for a specific period of time. Units: Beacons. 3750 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3751 * for a longer period of time then this escape-timeout. Units: Beacons. 3752 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3753 */ 3754struct iwm_beacon_filter_cmd { 3755 uint32_t bf_energy_delta; 3756 uint32_t bf_roaming_energy_delta; 3757 uint32_t bf_roaming_state; 3758 uint32_t bf_temp_threshold; 3759 uint32_t bf_temp_fast_filter; 3760 uint32_t bf_temp_slow_filter; 3761 uint32_t bf_enable_beacon_filter; 3762 uint32_t bf_debug_flag; 3763 uint32_t bf_escape_timer; 3764 uint32_t ba_escape_timer; 3765 uint32_t ba_enable_beacon_abort; 3766} __packed; 3767 3768/* Beacon filtering and beacon abort */ 3769#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3770#define IWM_BF_ENERGY_DELTA_MAX 255 3771#define IWM_BF_ENERGY_DELTA_MIN 0 3772 3773#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3774#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3775#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3776 3777#define IWM_BF_ROAMING_STATE_DEFAULT 72 3778#define IWM_BF_ROAMING_STATE_MAX 255 3779#define IWM_BF_ROAMING_STATE_MIN 0 3780 3781#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3782#define IWM_BF_TEMP_THRESHOLD_MAX 255 3783#define IWM_BF_TEMP_THRESHOLD_MIN 0 3784 3785#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3786#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3787#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3788 3789#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3790#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3791#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3792 3793#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3794 3795#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3796 3797#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3798#define IWM_BF_ESCAPE_TIMER_MAX 1024 3799#define IWM_BF_ESCAPE_TIMER_MIN 0 3800 3801#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3802#define IWM_BA_ESCAPE_TIMER_D3 9 3803#define IWM_BA_ESCAPE_TIMER_MAX 1024 3804#define IWM_BA_ESCAPE_TIMER_MIN 0 3805 3806#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3807 3808#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3809 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3810 .bf_roaming_energy_delta = \ 3811 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3812 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3813 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3814 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3815 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3816 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3817 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3818 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3819 3820/* 3821 * END mvm/fw-api-power.h 3822 */ 3823 3824/* 3825 * BEGIN mvm/fw-api-rs.h 3826 */ 3827 3828/* 3829 * These serve as indexes into 3830 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3831 * TODO: avoid overlap between legacy and HT rates 3832 */ 3833enum { 3834 IWM_RATE_1M_INDEX = 0, 3835 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3836 IWM_RATE_2M_INDEX, 3837 IWM_RATE_5M_INDEX, 3838 IWM_RATE_11M_INDEX, 3839 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3840 IWM_RATE_6M_INDEX, 3841 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3842 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3843 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3844 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3845 IWM_RATE_9M_INDEX, 3846 IWM_RATE_12M_INDEX, 3847 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3848 IWM_RATE_18M_INDEX, 3849 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3850 IWM_RATE_24M_INDEX, 3851 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3852 IWM_RATE_36M_INDEX, 3853 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3854 IWM_RATE_48M_INDEX, 3855 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3856 IWM_RATE_54M_INDEX, 3857 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3858 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3859 IWM_RATE_60M_INDEX, 3860 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3861 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3862 IWM_RATE_MCS_8_INDEX, 3863 IWM_RATE_MCS_9_INDEX, 3864 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3865 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3866 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3867}; 3868 3869#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3870 3871/* fw API values for legacy bit rates, both OFDM and CCK */ 3872enum { 3873 IWM_RATE_6M_PLCP = 13, 3874 IWM_RATE_9M_PLCP = 15, 3875 IWM_RATE_12M_PLCP = 5, 3876 IWM_RATE_18M_PLCP = 7, 3877 IWM_RATE_24M_PLCP = 9, 3878 IWM_RATE_36M_PLCP = 11, 3879 IWM_RATE_48M_PLCP = 1, 3880 IWM_RATE_54M_PLCP = 3, 3881 IWM_RATE_1M_PLCP = 10, 3882 IWM_RATE_2M_PLCP = 20, 3883 IWM_RATE_5M_PLCP = 55, 3884 IWM_RATE_11M_PLCP = 110, 3885 IWM_RATE_INVM_PLCP = -1, 3886}; 3887 3888/* 3889 * rate_n_flags bit fields 3890 * 3891 * The 32-bit value has different layouts in the low 8 bites depending on the 3892 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3893 * for CCK and OFDM). 3894 * 3895 * High-throughput (HT) rate format 3896 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3897 * Very High-throughput (VHT) rate format 3898 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3899 * Legacy OFDM rate format for bits 7:0 3900 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3901 * Legacy CCK rate format for bits 7:0: 3902 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3903 */ 3904 3905/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3906#define IWM_RATE_MCS_HT_POS 8 3907#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3908 3909/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3910#define IWM_RATE_MCS_CCK_POS 9 3911#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3912 3913/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3914#define IWM_RATE_MCS_VHT_POS 26 3915#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3916 3917 3918/* 3919 * High-throughput (HT) rate format for bits 7:0 3920 * 3921 * 2-0: MCS rate base 3922 * 0) 6 Mbps 3923 * 1) 12 Mbps 3924 * 2) 18 Mbps 3925 * 3) 24 Mbps 3926 * 4) 36 Mbps 3927 * 5) 48 Mbps 3928 * 6) 54 Mbps 3929 * 7) 60 Mbps 3930 * 4-3: 0) Single stream (SISO) 3931 * 1) Dual stream (MIMO) 3932 * 2) Triple stream (MIMO) 3933 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3934 * (bits 7-6 are zero) 3935 * 3936 * Together the low 5 bits work out to the MCS index because we don't 3937 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3938 * streams and 16-23 have three streams. We could also support MCS 32 3939 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3940 */ 3941#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3942#define IWM_RATE_HT_MCS_NSS_POS 3 3943#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3944 3945/* Bit 10: (1) Use Green Field preamble */ 3946#define IWM_RATE_HT_MCS_GF_POS 10 3947#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3948 3949#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3950 3951/* 3952 * Very High-throughput (VHT) rate format for bits 7:0 3953 * 3954 * 3-0: VHT MCS (0-9) 3955 * 5-4: number of streams - 1: 3956 * 0) Single stream (SISO) 3957 * 1) Dual stream (MIMO) 3958 * 2) Triple stream (MIMO) 3959 */ 3960 3961/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3962#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3963#define IWM_RATE_VHT_MCS_NSS_POS 4 3964#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3965 3966/* 3967 * Legacy OFDM rate format for bits 7:0 3968 * 3969 * 3-0: 0xD) 6 Mbps 3970 * 0xF) 9 Mbps 3971 * 0x5) 12 Mbps 3972 * 0x7) 18 Mbps 3973 * 0x9) 24 Mbps 3974 * 0xB) 36 Mbps 3975 * 0x1) 48 Mbps 3976 * 0x3) 54 Mbps 3977 * (bits 7-4 are 0) 3978 * 3979 * Legacy CCK rate format for bits 7:0: 3980 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3981 * 3982 * 6-0: 10) 1 Mbps 3983 * 20) 2 Mbps 3984 * 55) 5.5 Mbps 3985 * 110) 11 Mbps 3986 * (bit 7 is 0) 3987 */ 3988#define IWM_RATE_LEGACY_RATE_MSK 0xff 3989 3990 3991/* 3992 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 3993 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 3994 */ 3995#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 3996#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3997#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3998#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3999#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4000#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4001 4002/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4003#define IWM_RATE_MCS_SGI_POS 13 4004#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4005 4006/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4007#define IWM_RATE_MCS_ANT_POS 14 4008#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4009#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4010#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4011#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4012 IWM_RATE_MCS_ANT_B_MSK) 4013#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4014 IWM_RATE_MCS_ANT_C_MSK) 4015#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4016#define IWM_RATE_MCS_ANT_NUM 3 4017 4018/* Bit 17-18: (0) SS, (1) SS*2 */ 4019#define IWM_RATE_MCS_STBC_POS 17 4020#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4021 4022/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4023#define IWM_RATE_MCS_BF_POS 19 4024#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4025 4026/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4027#define IWM_RATE_MCS_ZLF_POS 20 4028#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4029 4030/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4031#define IWM_RATE_MCS_DUP_POS 24 4032#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4033 4034/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4035#define IWM_RATE_MCS_LDPC_POS 27 4036#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4037 4038 4039/* Link Quality definitions */ 4040 4041/* # entries in rate scale table to support Tx retries */ 4042#define IWM_LQ_MAX_RETRY_NUM 16 4043 4044/* Link quality command flags bit fields */ 4045 4046/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4047#define IWM_LQ_FLAG_USE_RTS_POS 0 4048#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4049 4050/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4051#define IWM_LQ_FLAG_COLOR_POS 1 4052#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4053 4054/* Bit 4-5: Tx RTS BW Signalling 4055 * (0) No RTS BW signalling 4056 * (1) Static BW signalling 4057 * (2) Dynamic BW signalling 4058 */ 4059#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4060#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4061#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4062#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4063 4064/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4065 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4066 */ 4067#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4068#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4069 4070/** 4071 * struct iwm_lq_cmd - link quality command 4072 * @sta_id: station to update 4073 * @control: not used 4074 * @flags: combination of IWM_LQ_FLAG_* 4075 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4076 * and SISO rates 4077 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4078 * Should be ANT_[ABC] 4079 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4080 * @initial_rate_index: first index from rs_table per AC category 4081 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4082 * value of 100 is one usec. Range is 100 to 8000 4083 * @agg_disable_start_th: try-count threshold for starting aggregation. 4084 * If a frame has higher try-count, it should not be selected for 4085 * starting an aggregation sequence. 4086 * @agg_frame_cnt_limit: max frame count in an aggregation. 4087 * 0: no limit 4088 * 1: no aggregation (one frame per aggregation) 4089 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4090 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4091 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4092 * @bf_params: beam forming params, currently not used 4093 */ 4094struct iwm_lq_cmd { 4095 uint8_t sta_id; 4096 uint8_t reserved1; 4097 uint16_t control; 4098 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4099 uint8_t flags; 4100 uint8_t mimo_delim; 4101 uint8_t single_stream_ant_msk; 4102 uint8_t dual_stream_ant_msk; 4103 uint8_t initial_rate_index[IWM_AC_NUM]; 4104 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4105 uint16_t agg_time_limit; 4106 uint8_t agg_disable_start_th; 4107 uint8_t agg_frame_cnt_limit; 4108 uint32_t reserved2; 4109 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4110 uint32_t bf_params; 4111}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4112 4113/* 4114 * END mvm/fw-api-rs.h 4115 */ 4116 4117/* 4118 * BEGIN mvm/fw-api-tx.h 4119 */ 4120 4121/** 4122 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4123 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4124 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4125 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4126 * Otherwise, use rate_n_flags from the TX command 4127 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4128 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4129 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4130 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4131 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4132 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4133 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4134 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4135 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4136 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4137 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4138 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4139 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4140 * Should be set for beacons and probe responses 4141 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4142 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4143 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4144 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4145 * Should be set for 26/30 length MAC headers 4146 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4147 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4148 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4149 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4150 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4151 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4152 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4153 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4154 */ 4155enum iwm_tx_flags { 4156 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4157 IWM_TX_CMD_FLG_ACK = (1 << 3), 4158 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4159 IWM_TX_CMD_FLG_BA = (1 << 5), 4160 IWM_TX_CMD_FLG_BAR = (1 << 6), 4161 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4162 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4163 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4164 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4165 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4166 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4167 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4168 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4169 IWM_TX_CMD_FLG_TSF = (1 << 16), 4170 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4171 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4172 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4173 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4174 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4175 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4176 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4177 IWM_TX_CMD_FLG_DUR = (1 << 25), 4178 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4179 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4180 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4181 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4182}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4183 4184/** 4185 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4186 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4187 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4188 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4189 */ 4190enum iwm_tx_pm_timeouts { 4191 IWM_PM_FRAME_NONE = 0, 4192 IWM_PM_FRAME_MGMT = 2, 4193 IWM_PM_FRAME_ASSOC = 3, 4194}; 4195 4196/* 4197 * TX command security control 4198 */ 4199#define IWM_TX_CMD_SEC_WEP 0x01 4200#define IWM_TX_CMD_SEC_CCM 0x02 4201#define IWM_TX_CMD_SEC_TKIP 0x03 4202#define IWM_TX_CMD_SEC_EXT 0x04 4203#define IWM_TX_CMD_SEC_MSK 0x07 4204#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4205#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4206#define IWM_TX_CMD_SEC_KEY128 0x08 4207 4208/* TODO: how does these values are OK with only 16 bit variable??? */ 4209/* 4210 * TX command next frame info 4211 * 4212 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4213 * bit 3 - immediate ACK required 4214 * bit 4 - rate is taken from STA table 4215 * bit 5 - frame belongs to BA stream 4216 * bit 6 - immediate BA response expected 4217 * bit 7 - unused 4218 * bits 8:15 - Station ID 4219 * bits 16:31 - rate 4220 */ 4221#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4222#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4223#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4224#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4225#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4226#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4227#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4228#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4229#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4230 4231/* 4232 * TX command Frame life time in us - to be written in pm_frame_timeout 4233 */ 4234#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4235#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4236#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4237#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4238 4239/* 4240 * TID for non QoS frames - to be written in tid_tspec 4241 */ 4242#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4243 4244/* 4245 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4246 */ 4247#define IWM_DEFAULT_TX_RETRY 15 4248#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4249#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4250#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4251#define IWM_LOW_RETRY_LIMIT 7 4252 4253/* TODO: complete documentation for try_cnt and btkill_cnt */ 4254/** 4255 * struct iwm_tx_cmd - TX command struct to FW 4256 * ( IWM_TX_CMD = 0x1c ) 4257 * @len: in bytes of the payload, see below for details 4258 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4259 * Used for fragmentation and bursting, but not in 11n aggregation. 4260 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4261 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4262 * cleared. Combination of IWM_RATE_MCS_* 4263 * @sta_id: index of destination station in FW station table 4264 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4265 * @initial_rate_index: index into the rate table for initial TX attempt. 4266 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4267 * @key: security key 4268 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4269 * @life_time: frame life time (usecs??) 4270 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4271 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4272 * @dram_msb_ptr: upper bits of the scratch physical address 4273 * @rts_retry_limit: max attempts for RTS 4274 * @data_retry_limit: max attempts to send the data packet 4275 * @tid_spec: TID/tspec 4276 * @pm_frame_timeout: PM TX frame timeout 4277 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4278 * specified by HCCA protocol 4279 * 4280 * The byte count (both len and next_frame_len) includes MAC header 4281 * (24/26/30/32 bytes) 4282 * + 2 bytes pad if 26/30 header size 4283 * + 8 byte IV for CCM or TKIP (not used for WEP) 4284 * + Data payload 4285 * + 8-byte MIC (not used for CCM/WEP) 4286 * It does not include post-MAC padding, i.e., 4287 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4288 * Range of len: 14-2342 bytes. 4289 * 4290 * After the struct fields the MAC header is placed, plus any padding, 4291 * and then the actial payload. 4292 */ 4293struct iwm_tx_cmd { 4294 uint16_t len; 4295 uint16_t next_frame_len; 4296 uint32_t tx_flags; 4297 struct { 4298 uint8_t try_cnt; 4299 uint8_t btkill_cnt; 4300 uint16_t reserved; 4301 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4302 uint32_t rate_n_flags; 4303 uint8_t sta_id; 4304 uint8_t sec_ctl; 4305 uint8_t initial_rate_index; 4306 uint8_t reserved2; 4307 uint8_t key[16]; 4308 uint16_t next_frame_flags; 4309 uint16_t reserved3; 4310 uint32_t life_time; 4311 uint32_t dram_lsb_ptr; 4312 uint8_t dram_msb_ptr; 4313 uint8_t rts_retry_limit; 4314 uint8_t data_retry_limit; 4315 uint8_t tid_tspec; 4316 uint16_t pm_frame_timeout; 4317 uint16_t driver_txop; 4318 uint8_t payload[0]; 4319 struct ieee80211_frame hdr[0]; 4320} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4321 4322/* 4323 * TX response related data 4324 */ 4325 4326/* 4327 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4328 * @IWM_TX_STATUS_SUCCESS: 4329 * @IWM_TX_STATUS_DIRECT_DONE: 4330 * @IWM_TX_STATUS_POSTPONE_DELAY: 4331 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4332 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4333 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4334 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4335 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4336 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4337 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4338 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4339 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4340 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4341 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4342 * @IWM_TX_STATUS_FAIL_DEST_PS: 4343 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4344 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4345 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4346 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4347 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4348 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4349 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4350 * @IWM_TX_STATUS_FAIL_FW_DROP: 4351 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4352 * STA table 4353 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4354 * @IWM_TX_MODE_MSK: 4355 * @IWM_TX_MODE_NO_BURST: 4356 * @IWM_TX_MODE_IN_BURST_SEQ: 4357 * @IWM_TX_MODE_FIRST_IN_BURST: 4358 * @IWM_TX_QUEUE_NUM_MSK: 4359 * 4360 * Valid only if frame_count =1 4361 * TODO: complete documentation 4362 */ 4363enum iwm_tx_status { 4364 IWM_TX_STATUS_MSK = 0x000000ff, 4365 IWM_TX_STATUS_SUCCESS = 0x01, 4366 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4367 /* postpone TX */ 4368 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4369 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4370 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4371 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4372 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4373 /* abort TX */ 4374 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4375 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4376 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4377 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4378 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4379 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4380 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4381 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4382 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4383 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4384 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4385 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4386 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4387 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4388 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4389 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4390 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4391 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4392 IWM_TX_MODE_MSK = 0x00000f00, 4393 IWM_TX_MODE_NO_BURST = 0x00000000, 4394 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4395 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4396 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4397 IWM_TX_NARROW_BW_MSK = 0x00060000, 4398 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4399 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4400 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4401}; 4402 4403/* 4404 * enum iwm_tx_agg_status - TX aggregation status 4405 * @IWM_AGG_TX_STATE_STATUS_MSK: 4406 * @IWM_AGG_TX_STATE_TRANSMITTED: 4407 * @IWM_AGG_TX_STATE_UNDERRUN: 4408 * @IWM_AGG_TX_STATE_BT_PRIO: 4409 * @IWM_AGG_TX_STATE_FEW_BYTES: 4410 * @IWM_AGG_TX_STATE_ABORT: 4411 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4412 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4413 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4414 * @IWM_AGG_TX_STATE_SCD_QUERY: 4415 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4416 * @IWM_AGG_TX_STATE_RESPONSE: 4417 * @IWM_AGG_TX_STATE_DUMP_TX: 4418 * @IWM_AGG_TX_STATE_DELAY_TX: 4419 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4420 * occur if tx failed for this frame when it was a member of a previous 4421 * aggregation block). If rate scaling is used, retry count indicates the 4422 * rate table entry used for all frames in the new agg. 4423 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4424 * this frame 4425 * 4426 * TODO: complete documentation 4427 */ 4428enum iwm_tx_agg_status { 4429 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4430 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4431 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4432 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4433 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4434 IWM_AGG_TX_STATE_ABORT = 0x008, 4435 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4436 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4437 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4438 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4439 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4440 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4441 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4442 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4443 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4444 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4445}; 4446 4447#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4448 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4449 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4450 4451/* 4452 * The mask below describes a status where we are absolutely sure that the MPDU 4453 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4454 * written the bytes to the TXE, but we know nothing about what the DSP did. 4455 */ 4456#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4457 IWM_AGG_TX_STATE_ABORT | \ 4458 IWM_AGG_TX_STATE_SCD_QUERY) 4459 4460/* 4461 * IWM_REPLY_TX = 0x1c (response) 4462 * 4463 * This response may be in one of two slightly different formats, indicated 4464 * by the frame_count field: 4465 * 4466 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4467 * frame. Multiple attempts, at various bit rates, may have been made for 4468 * this frame. 4469 * 4470 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4471 * frames that used block-acknowledge. All frames were transmitted at 4472 * same rate. Rate scaling may have been used if first frame in this new 4473 * agg block failed in previous agg block(s). 4474 * 4475 * Note that, for aggregation, ACK (block-ack) status is not delivered 4476 * here; block-ack has not been received by the time the device records 4477 * this status. 4478 * This status relates to reasons the tx might have been blocked or aborted 4479 * within the device, rather than whether it was received successfully by 4480 * the destination station. 4481 */ 4482 4483/** 4484 * struct iwm_agg_tx_status - per packet TX aggregation status 4485 * @status: enum iwm_tx_agg_status 4486 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4487 */ 4488struct iwm_agg_tx_status { 4489 uint16_t status; 4490 uint16_t sequence; 4491} __packed; 4492 4493/* 4494 * definitions for initial rate index field 4495 * bits [3:0] initial rate index 4496 * bits [6:4] rate table color, used for the initial rate 4497 * bit-7 invalid rate indication 4498 */ 4499#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4500#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4501#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4502 4503#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4504#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4505 4506/** 4507 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4508 * ( IWM_REPLY_TX = 0x1c ) 4509 * @frame_count: 1 no aggregation, >1 aggregation 4510 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4511 * @failure_rts: num of failures due to unsuccessful RTS 4512 * @failure_frame: num failures due to no ACK (unused for agg) 4513 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4514 * Tx of all the batch. IWM_RATE_MCS_* 4515 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4516 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4517 * in usec. 4518 * @pa_status: tx power info 4519 * @pa_integ_res_a: tx power info 4520 * @pa_integ_res_b: tx power info 4521 * @pa_integ_res_c: tx power info 4522 * @measurement_req_id: tx power info 4523 * @tfd_info: TFD information set by the FH 4524 * @seq_ctl: sequence control from the Tx cmd 4525 * @byte_cnt: byte count from the Tx cmd 4526 * @tlc_info: TLC rate info 4527 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4528 * @frame_ctrl: frame control 4529 * @status: for non-agg: frame status IWM_TX_STATUS_* 4530 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4531 * follow this one, up to frame_count. 4532 * 4533 * After the array of statuses comes the SSN of the SCD. Look at 4534 * %iwm_mvm_get_scd_ssn for more details. 4535 */ 4536struct iwm_mvm_tx_resp { 4537 uint8_t frame_count; 4538 uint8_t bt_kill_count; 4539 uint8_t failure_rts; 4540 uint8_t failure_frame; 4541 uint32_t initial_rate; 4542 uint16_t wireless_media_time; 4543 4544 uint8_t pa_status; 4545 uint8_t pa_integ_res_a[3]; 4546 uint8_t pa_integ_res_b[3]; 4547 uint8_t pa_integ_res_c[3]; 4548 uint16_t measurement_req_id; 4549 uint16_t reserved; 4550 4551 uint32_t tfd_info; 4552 uint16_t seq_ctl; 4553 uint16_t byte_cnt; 4554 uint8_t tlc_info; 4555 uint8_t ra_tid; 4556 uint16_t frame_ctrl; 4557 4558 struct iwm_agg_tx_status status; 4559} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4560 4561/** 4562 * struct iwm_mvm_ba_notif - notifies about reception of BA 4563 * ( IWM_BA_NOTIF = 0xc5 ) 4564 * @sta_addr_lo32: lower 32 bits of the MAC address 4565 * @sta_addr_hi16: upper 16 bits of the MAC address 4566 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4567 * @tid: tid of the session 4568 * @seq_ctl: 4569 * @bitmap: the bitmap of the BA notification as seen in the air 4570 * @scd_flow: the tx queue this BA relates to 4571 * @scd_ssn: the index of the last contiguously sent packet 4572 * @txed: number of Txed frames in this batch 4573 * @txed_2_done: number of Acked frames in this batch 4574 */ 4575struct iwm_mvm_ba_notif { 4576 uint32_t sta_addr_lo32; 4577 uint16_t sta_addr_hi16; 4578 uint16_t reserved; 4579 4580 uint8_t sta_id; 4581 uint8_t tid; 4582 uint16_t seq_ctl; 4583 uint64_t bitmap; 4584 uint16_t scd_flow; 4585 uint16_t scd_ssn; 4586 uint8_t txed; 4587 uint8_t txed_2_done; 4588 uint16_t reserved1; 4589} __packed; 4590 4591/* 4592 * struct iwm_mac_beacon_cmd - beacon template command 4593 * @tx: the tx commands associated with the beacon frame 4594 * @template_id: currently equal to the mac context id of the coresponding 4595 * mac. 4596 * @tim_idx: the offset of the tim IE in the beacon 4597 * @tim_size: the length of the tim IE 4598 * @frame: the template of the beacon frame 4599 */ 4600struct iwm_mac_beacon_cmd { 4601 struct iwm_tx_cmd tx; 4602 uint32_t template_id; 4603 uint32_t tim_idx; 4604 uint32_t tim_size; 4605 struct ieee80211_frame frame[0]; 4606} __packed; 4607 4608struct iwm_beacon_notif { 4609 struct iwm_mvm_tx_resp beacon_notify_hdr; 4610 uint64_t tsf; 4611 uint32_t ibss_mgr_status; 4612} __packed; 4613 4614/** 4615 * enum iwm_dump_control - dump (flush) control flags 4616 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4617 * and the TFD queues are empty. 4618 */ 4619enum iwm_dump_control { 4620 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4621}; 4622 4623/** 4624 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4625 * @queues_ctl: bitmap of queues to flush 4626 * @flush_ctl: control flags 4627 * @reserved: reserved 4628 */ 4629struct iwm_tx_path_flush_cmd { 4630 uint32_t queues_ctl; 4631 uint16_t flush_ctl; 4632 uint16_t reserved; 4633} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4634 4635/** 4636 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4637 * @tx_resp: the Tx response from the fw (agg or non-agg) 4638 * 4639 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4640 * it can't know that everything will go well until the end of the AMPDU, it 4641 * can't know in advance the number of MPDUs that will be sent in the current 4642 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4643 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4644 * of the batch. This is why the SSN of the SCD is written at the end of the 4645 * whole struct at a variable offset. This function knows how to cope with the 4646 * variable offset and returns the SSN of the SCD. 4647 */ 4648static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4649{ 4650 return le32_to_cpup((uint32_t *)&tx_resp->status + 4651 tx_resp->frame_count) & 0xfff; 4652} 4653 4654/* 4655 * END mvm/fw-api-tx.h 4656 */ 4657 4658/* 4659 * BEGIN mvm/fw-api-scan.h 4660 */ 4661 4662/** 4663 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4664 * @token: 4665 * @sta_id: station id 4666 * @tid: 4667 * @scd_queue: scheduler queue to confiug 4668 * @enable: 1 queue enable, 0 queue disable 4669 * @aggregate: 1 aggregated queue, 0 otherwise 4670 * @tx_fifo: %enum iwm_mvm_tx_fifo 4671 * @window: BA window size 4672 * @ssn: SSN for the BA agreement 4673 */ 4674struct iwm_scd_txq_cfg_cmd { 4675 uint8_t token; 4676 uint8_t sta_id; 4677 uint8_t tid; 4678 uint8_t scd_queue; 4679 uint8_t enable; 4680 uint8_t aggregate; 4681 uint8_t tx_fifo; 4682 uint8_t window; 4683 uint16_t ssn; 4684 uint16_t reserved; 4685} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4686 4687/** 4688 * struct iwm_scd_txq_cfg_rsp 4689 * @token: taken from the command 4690 * @sta_id: station id from the command 4691 * @tid: tid from the command 4692 * @scd_queue: scd_queue from the command 4693 */ 4694struct iwm_scd_txq_cfg_rsp { 4695 uint8_t token; 4696 uint8_t sta_id; 4697 uint8_t tid; 4698 uint8_t scd_queue; 4699} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4700 4701 4702/* Scan Commands, Responses, Notifications */ 4703 4704/* Masks for iwm_scan_channel.type flags */ 4705#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4706#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4707 4708/* Max number of IEs for direct SSID scans in a command */ 4709#define IWM_PROBE_OPTION_MAX 20 4710 4711/** 4712 * struct iwm_ssid_ie - directed scan network information element 4713 * 4714 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4715 * selected by "type" bit field in struct iwm_scan_channel; 4716 * each channel may select different ssids from among the 20 entries. 4717 * SSID IEs get transmitted in reverse order of entry. 4718 */ 4719struct iwm_ssid_ie { 4720 uint8_t id; 4721 uint8_t len; 4722 uint8_t ssid[IEEE80211_NWID_LEN]; 4723} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4724 4725/* scan offload */ 4726#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4727#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4728#define IWM_SCAN_MAX_PROFILES 11 4729#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4730 4731/* Default watchdog (in MS) for scheduled scan iteration */ 4732#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4733 4734#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4735#define IWM_CAN_ABORT_STATUS 1 4736 4737#define IWM_FULL_SCAN_MULTIPLIER 5 4738#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4739#define IWM_MAX_SCHED_SCAN_PLANS 2 4740 4741/** 4742 * iwm_scan_schedule_lmac - schedule of scan offload 4743 * @delay: delay between iterations, in seconds. 4744 * @iterations: num of scan iterations 4745 * @full_scan_mul: number of partial scans before each full scan 4746 */ 4747struct iwm_scan_schedule_lmac { 4748 uint16_t delay; 4749 uint8_t iterations; 4750 uint8_t full_scan_mul; 4751} __packed; /* SCAN_SCHEDULE_API_S */ 4752 4753/** 4754 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4755 * @tx_flags: combination of TX_CMD_FLG_* 4756 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4757 * cleared. Combination of RATE_MCS_* 4758 * @sta_id: index of destination station in FW station table 4759 * @reserved: for alignment and future use 4760 */ 4761struct iwm_scan_req_tx_cmd { 4762 uint32_t tx_flags; 4763 uint32_t rate_n_flags; 4764 uint8_t sta_id; 4765 uint8_t reserved[3]; 4766} __packed; 4767 4768enum iwm_scan_channel_flags_lmac { 4769 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4770 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4771}; 4772 4773/** 4774 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4775 * @flags: bits 1-20: directed scan to i'th ssid 4776 * other bits &enum iwm_scan_channel_flags_lmac 4777 * @channel_number: channel number 1-13 etc 4778 * @iter_count: scan iteration on this channel 4779 * @iter_interval: interval in seconds between iterations on one channel 4780 */ 4781struct iwm_scan_channel_cfg_lmac { 4782 uint32_t flags; 4783 uint16_t channel_num; 4784 uint16_t iter_count; 4785 uint32_t iter_interval; 4786} __packed; 4787 4788/* 4789 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4790 * @offset: offset in the data block 4791 * @len: length of the segment 4792 */ 4793struct iwm_scan_probe_segment { 4794 uint16_t offset; 4795 uint16_t len; 4796} __packed; 4797 4798/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4799 * @mac_header: first (and common) part of the probe 4800 * @band_data: band specific data 4801 * @common_data: last (and common) part of the probe 4802 * @buf: raw data block 4803 */ 4804struct iwm_scan_probe_req { 4805 struct iwm_scan_probe_segment mac_header; 4806 struct iwm_scan_probe_segment band_data[2]; 4807 struct iwm_scan_probe_segment common_data; 4808 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4809} __packed; 4810 4811enum iwm_scan_channel_flags { 4812 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4813 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4814 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4815}; 4816 4817/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4818 * @flags: enum iwm_scan_channel_flags 4819 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4820 * involved. 4821 * 1 - EBS is disabled. 4822 * 2 - every second scan will be full scan(and so on). 4823 */ 4824struct iwm_scan_channel_opt { 4825 uint16_t flags; 4826 uint16_t non_ebs_ratio; 4827} __packed; 4828 4829/** 4830 * iwm_mvm_lmac_scan_flags 4831 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4832 * without filtering. 4833 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4834 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4835 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4836 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4837 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4838 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4839 * and DS parameter set IEs into probe requests. 4840 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4841 * 1, 6 and 11. 4842 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4843 */ 4844enum iwm_mvm_lmac_scan_flags { 4845 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4846 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4847 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4848 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4849 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4850 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4851 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4852 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4853 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4854}; 4855 4856enum iwm_scan_priority { 4857 IWM_SCAN_PRIORITY_LOW, 4858 IWM_SCAN_PRIORITY_MEDIUM, 4859 IWM_SCAN_PRIORITY_HIGH, 4860}; 4861 4862/** 4863 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4864 * @reserved1: for alignment and future use 4865 * @channel_num: num of channels to scan 4866 * @active-dwell: dwell time for active channels 4867 * @passive-dwell: dwell time for passive channels 4868 * @fragmented-dwell: dwell time for fragmented passive scan 4869 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4870 * @reserved2: for alignment and future use 4871 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4872 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4873 * @max_out_time: max time (in TU) to be out of associated channel 4874 * @suspend_time: pause scan this long (TUs) when returning to service channel 4875 * @flags: RXON flags 4876 * @filter_flags: RXON filter 4877 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4878 * @direct_scan: list of SSIDs for directed active scan 4879 * @scan_prio: enum iwm_scan_priority 4880 * @iter_num: number of scan iterations 4881 * @delay: delay in seconds before first iteration 4882 * @schedule: two scheduling plans. The first one is finite, the second one can 4883 * be infinite. 4884 * @channel_opt: channel optimization options, for full and partial scan 4885 * @data: channel configuration and probe request packet. 4886 */ 4887struct iwm_scan_req_lmac { 4888 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4889 uint32_t reserved1; 4890 uint8_t n_channels; 4891 uint8_t active_dwell; 4892 uint8_t passive_dwell; 4893 uint8_t fragmented_dwell; 4894 uint8_t extended_dwell; 4895 uint8_t reserved2; 4896 uint16_t rx_chain_select; 4897 uint32_t scan_flags; 4898 uint32_t max_out_time; 4899 uint32_t suspend_time; 4900 /* RX_ON_FLAGS_API_S_VER_1 */ 4901 uint32_t flags; 4902 uint32_t filter_flags; 4903 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4904 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4905 uint32_t scan_prio; 4906 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4907 uint32_t iter_num; 4908 uint32_t delay; 4909 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4910 struct iwm_scan_channel_opt channel_opt[2]; 4911 uint8_t data[]; 4912} __packed; 4913 4914/** 4915 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4916 * @last_schedule_line: last schedule line executed (fast or regular) 4917 * @last_schedule_iteration: last scan iteration executed before scan abort 4918 * @status: enum iwm_scan_offload_complete_status 4919 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4920 * @time_after_last_iter; time in seconds elapsed after last iteration 4921 */ 4922struct iwm_periodic_scan_complete { 4923 uint8_t last_schedule_line; 4924 uint8_t last_schedule_iteration; 4925 uint8_t status; 4926 uint8_t ebs_status; 4927 uint32_t time_after_last_iter; 4928 uint32_t reserved; 4929} __packed; 4930 4931/* How many statistics are gathered for each channel */ 4932#define IWM_SCAN_RESULTS_STATISTICS 1 4933 4934/** 4935 * enum iwm_scan_complete_status - status codes for scan complete notifications 4936 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4937 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4938 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4939 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4940 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4941 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4942 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4943 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4944 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4945 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4946 * (not an error!) 4947 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4948 * asked for 4949 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4950*/ 4951enum iwm_scan_complete_status { 4952 IWM_SCAN_COMP_STATUS_OK = 0x1, 4953 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4954 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4955 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4956 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4957 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4958 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4959 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4960 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4961 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4962 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4963 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4964}; 4965 4966/** 4967 * struct iwm_scan_results_notif - scan results for one channel 4968 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4969 * @channel: which channel the results are from 4970 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4971 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4972 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4973 * @duration: duration spent in channel, in usecs 4974 * @statistics: statistics gathered for this channel 4975 */ 4976struct iwm_scan_results_notif { 4977 uint8_t channel; 4978 uint8_t band; 4979 uint8_t probe_status; 4980 uint8_t num_probe_not_sent; 4981 uint32_t duration; 4982 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 4983} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 4984 4985enum iwm_scan_framework_client { 4986 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4987 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 4988 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 4989}; 4990 4991/** 4992 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 4993 * @ssid: MAC address to filter out 4994 * @reported_rssi: AP rssi reported to the host 4995 * @client_bitmap: clients ignore this entry - enum scan_framework_client 4996 */ 4997struct iwm_scan_offload_blacklist { 4998 uint8_t ssid[IEEE80211_ADDR_LEN]; 4999 uint8_t reported_rssi; 5000 uint8_t client_bitmap; 5001} __packed; 5002 5003enum iwm_scan_offload_network_type { 5004 IWM_NETWORK_TYPE_BSS = 1, 5005 IWM_NETWORK_TYPE_IBSS = 2, 5006 IWM_NETWORK_TYPE_ANY = 3, 5007}; 5008 5009enum iwm_scan_offload_band_selection { 5010 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5011 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5012 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5013}; 5014 5015/** 5016 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5017 * @ssid_index: index to ssid list in fixed part 5018 * @unicast_cipher: encryption olgorithm to match - bitmap 5019 * @aut_alg: authentication olgorithm to match - bitmap 5020 * @network_type: enum iwm_scan_offload_network_type 5021 * @band_selection: enum iwm_scan_offload_band_selection 5022 * @client_bitmap: clients waiting for match - enum scan_framework_client 5023 */ 5024struct iwm_scan_offload_profile { 5025 uint8_t ssid_index; 5026 uint8_t unicast_cipher; 5027 uint8_t auth_alg; 5028 uint8_t network_type; 5029 uint8_t band_selection; 5030 uint8_t client_bitmap; 5031 uint8_t reserved[2]; 5032} __packed; 5033 5034/** 5035 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5036 * @blaclist: AP list to filter off from scan results 5037 * @profiles: profiles to search for match 5038 * @blacklist_len: length of blacklist 5039 * @num_profiles: num of profiles in the list 5040 * @match_notify: clients waiting for match found notification 5041 * @pass_match: clients waiting for the results 5042 * @active_clients: active clients bitmap - enum scan_framework_client 5043 * @any_beacon_notify: clients waiting for match notification without match 5044 */ 5045struct iwm_scan_offload_profile_cfg { 5046 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5047 uint8_t blacklist_len; 5048 uint8_t num_profiles; 5049 uint8_t match_notify; 5050 uint8_t pass_match; 5051 uint8_t active_clients; 5052 uint8_t any_beacon_notify; 5053 uint8_t reserved[2]; 5054} __packed; 5055 5056enum iwm_scan_offload_complete_status { 5057 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5058 IWM_SCAN_OFFLOAD_ABORTED = 2, 5059}; 5060 5061/** 5062 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5063 * SCAN_COMPLETE_NTF_API_S_VER_3 5064 * @scanned_channels: number of channels scanned (and number of valid results) 5065 * @status: one of SCAN_COMP_STATUS_* 5066 * @bt_status: BT on/off status 5067 * @last_channel: last channel that was scanned 5068 * @tsf_low: TSF timer (lower half) in usecs 5069 * @tsf_high: TSF timer (higher half) in usecs 5070 * @results: an array of scan results, only "scanned_channels" of them are valid 5071 */ 5072struct iwm_lmac_scan_complete_notif { 5073 uint8_t scanned_channels; 5074 uint8_t status; 5075 uint8_t bt_status; 5076 uint8_t last_channel; 5077 uint32_t tsf_low; 5078 uint32_t tsf_high; 5079 struct iwm_scan_results_notif results[]; 5080} __packed; 5081 5082 5083/* 5084 * END mvm/fw-api-scan.h 5085 */ 5086 5087/* 5088 * BEGIN mvm/fw-api-sta.h 5089 */ 5090 5091/* UMAC Scan API */ 5092 5093/* The maximum of either of these cannot exceed 8, because we use an 5094 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5095 */ 5096#define IWM_MVM_MAX_UMAC_SCANS 8 5097#define IWM_MVM_MAX_LMAC_SCANS 1 5098 5099enum iwm_scan_config_flags { 5100 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5101 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5102 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5103 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5104 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5105 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5106 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5107 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5108 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5109 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5110 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5111 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5112 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5113 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5114 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5115 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5116 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5117 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5118 5119 /* Bits 26-31 are for num of channels in channel_array */ 5120#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5121}; 5122 5123enum iwm_scan_config_rates { 5124 /* OFDM basic rates */ 5125 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5126 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5127 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5128 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5129 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5130 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5131 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5132 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5133 /* CCK basic rates */ 5134 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5135 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5136 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5137 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5138 5139 /* Bits 16-27 are for supported rates */ 5140#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5141}; 5142 5143enum iwm_channel_flags { 5144 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5145 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5146 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5147 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5148}; 5149 5150/** 5151 * struct iwm_scan_config 5152 * @flags: enum scan_config_flags 5153 * @tx_chains: valid_tx antenna - ANT_* definitions 5154 * @rx_chains: valid_rx antenna - ANT_* definitions 5155 * @legacy_rates: default legacy rates - enum scan_config_rates 5156 * @out_of_channel_time: default max out of serving channel time 5157 * @suspend_time: default max suspend time 5158 * @dwell_active: default dwell time for active scan 5159 * @dwell_passive: default dwell time for passive scan 5160 * @dwell_fragmented: default dwell time for fragmented scan 5161 * @dwell_extended: default dwell time for channels 1, 6 and 11 5162 * @mac_addr: default mac address to be used in probes 5163 * @bcast_sta_id: the index of the station in the fw 5164 * @channel_flags: default channel flags - enum iwm_channel_flags 5165 * scan_config_channel_flag 5166 * @channel_array: default supported channels 5167 */ 5168struct iwm_scan_config { 5169 uint32_t flags; 5170 uint32_t tx_chains; 5171 uint32_t rx_chains; 5172 uint32_t legacy_rates; 5173 uint32_t out_of_channel_time; 5174 uint32_t suspend_time; 5175 uint8_t dwell_active; 5176 uint8_t dwell_passive; 5177 uint8_t dwell_fragmented; 5178 uint8_t dwell_extended; 5179 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5180 uint8_t bcast_sta_id; 5181 uint8_t channel_flags; 5182 uint8_t channel_array[]; 5183} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5184 5185/** 5186 * iwm_umac_scan_flags 5187 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5188 * can be preempted by other scan requests with higher priority. 5189 * The low priority scan will be resumed when the higher proirity scan is 5190 * completed. 5191 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5192 * when scan starts. 5193 */ 5194enum iwm_umac_scan_flags { 5195 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5196 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5197}; 5198 5199enum iwm_umac_scan_uid_offsets { 5200 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5201 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5202}; 5203 5204enum iwm_umac_scan_general_flags { 5205 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5206 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5207 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5208 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5209 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5210 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5211 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5212 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5213 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5214 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5215 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5216}; 5217 5218/** 5219 * struct iwm_scan_channel_cfg_umac 5220 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5221 * @channel_num: channel number 1-13 etc. 5222 * @iter_count: repetition count for the channel. 5223 * @iter_interval: interval between two scan iterations on one channel. 5224 */ 5225struct iwm_scan_channel_cfg_umac { 5226 uint32_t flags; 5227#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5228 5229 uint8_t channel_num; 5230 uint8_t iter_count; 5231 uint16_t iter_interval; 5232} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5233 5234/** 5235 * struct iwm_scan_umac_schedule 5236 * @interval: interval in seconds between scan iterations 5237 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5238 * @reserved: for alignment and future use 5239 */ 5240struct iwm_scan_umac_schedule { 5241 uint16_t interval; 5242 uint8_t iter_count; 5243 uint8_t reserved; 5244} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5245 5246/** 5247 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5248 * parameters following channels configuration array. 5249 * @schedule: two scheduling plans. 5250 * @delay: delay in TUs before starting the first scan iteration 5251 * @reserved: for future use and alignment 5252 * @preq: probe request with IEs blocks 5253 * @direct_scan: list of SSIDs for directed active scan 5254 */ 5255struct iwm_scan_req_umac_tail { 5256 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5257 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5258 uint16_t delay; 5259 uint16_t reserved; 5260 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5261 struct iwm_scan_probe_req preq; 5262 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5263} __packed; 5264 5265/** 5266 * struct iwm_scan_req_umac 5267 * @flags: &enum iwm_umac_scan_flags 5268 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5269 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5270 * @general_flags: &enum iwm_umac_scan_general_flags 5271 * @extended_dwell: dwell time for channels 1, 6 and 11 5272 * @active_dwell: dwell time for active scan 5273 * @passive_dwell: dwell time for passive scan 5274 * @fragmented_dwell: dwell time for fragmented passive scan 5275 * @max_out_time: max out of serving channel time 5276 * @suspend_time: max suspend time 5277 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5278 * @channel_flags: &enum iwm_scan_channel_flags 5279 * @n_channels: num of channels in scan request 5280 * @reserved: for future use and alignment 5281 * @data: &struct iwm_scan_channel_cfg_umac and 5282 * &struct iwm_scan_req_umac_tail 5283 */ 5284struct iwm_scan_req_umac { 5285 uint32_t flags; 5286 uint32_t uid; 5287 uint32_t ooc_priority; 5288 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5289 uint32_t general_flags; 5290 uint8_t extended_dwell; 5291 uint8_t active_dwell; 5292 uint8_t passive_dwell; 5293 uint8_t fragmented_dwell; 5294 uint32_t max_out_time; 5295 uint32_t suspend_time; 5296 uint32_t scan_priority; 5297 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5298 uint8_t channel_flags; 5299 uint8_t n_channels; 5300 uint16_t reserved; 5301 uint8_t data[]; 5302} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5303 5304/** 5305 * struct iwm_umac_scan_abort 5306 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5307 * @flags: reserved 5308 */ 5309struct iwm_umac_scan_abort { 5310 uint32_t uid; 5311 uint32_t flags; 5312} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5313 5314/** 5315 * struct iwm_umac_scan_complete 5316 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5317 * @last_schedule: last scheduling line 5318 * @last_iter: last scan iteration number 5319 * @scan status: &enum iwm_scan_offload_complete_status 5320 * @ebs_status: &enum iwm_scan_ebs_status 5321 * @time_from_last_iter: time elapsed from last iteration 5322 * @reserved: for future use 5323 */ 5324struct iwm_umac_scan_complete { 5325 uint32_t uid; 5326 uint8_t last_schedule; 5327 uint8_t last_iter; 5328 uint8_t status; 5329 uint8_t ebs_status; 5330 uint32_t time_from_last_iter; 5331 uint32_t reserved; 5332} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5333 5334#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5335/** 5336 * struct iwm_scan_offload_profile_match - match information 5337 * @bssid: matched bssid 5338 * @channel: channel where the match occurred 5339 * @energy: 5340 * @matching_feature: 5341 * @matching_channels: bitmap of channels that matched, referencing 5342 * the channels passed in tue scan offload request 5343 */ 5344struct iwm_scan_offload_profile_match { 5345 uint8_t bssid[IEEE80211_ADDR_LEN]; 5346 uint16_t reserved; 5347 uint8_t channel; 5348 uint8_t energy; 5349 uint8_t matching_feature; 5350 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5351} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5352 5353/** 5354 * struct iwm_scan_offload_profiles_query - match results query response 5355 * @matched_profiles: bitmap of matched profiles, referencing the 5356 * matches passed in the scan offload request 5357 * @last_scan_age: age of the last offloaded scan 5358 * @n_scans_done: number of offloaded scans done 5359 * @gp2_d0u: GP2 when D0U occurred 5360 * @gp2_invoked: GP2 when scan offload was invoked 5361 * @resume_while_scanning: not used 5362 * @self_recovery: obsolete 5363 * @reserved: reserved 5364 * @matches: array of match information, one for each match 5365 */ 5366struct iwm_scan_offload_profiles_query { 5367 uint32_t matched_profiles; 5368 uint32_t last_scan_age; 5369 uint32_t n_scans_done; 5370 uint32_t gp2_d0u; 5371 uint32_t gp2_invoked; 5372 uint8_t resume_while_scanning; 5373 uint8_t self_recovery; 5374 uint16_t reserved; 5375 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5376} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5377 5378/** 5379 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5380 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5381 * @scanned_channels: number of channels scanned and number of valid elements in 5382 * results array 5383 * @status: one of SCAN_COMP_STATUS_* 5384 * @bt_status: BT on/off status 5385 * @last_channel: last channel that was scanned 5386 * @tsf_low: TSF timer (lower half) in usecs 5387 * @tsf_high: TSF timer (higher half) in usecs 5388 * @results: array of scan results, only "scanned_channels" of them are valid 5389 */ 5390struct iwm_umac_scan_iter_complete_notif { 5391 uint32_t uid; 5392 uint8_t scanned_channels; 5393 uint8_t status; 5394 uint8_t bt_status; 5395 uint8_t last_channel; 5396 uint32_t tsf_low; 5397 uint32_t tsf_high; 5398 struct iwm_scan_results_notif results[]; 5399} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5400 5401/* Please keep this enum *SORTED* by hex value. 5402 * Needed for binary search, otherwise a warning will be triggered. 5403 */ 5404enum iwm_scan_subcmd_ids { 5405 IWM_GSCAN_START_CMD = 0x0, 5406 IWM_GSCAN_STOP_CMD = 0x1, 5407 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5408 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5409 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5410 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5411 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5412 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5413 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5414}; 5415 5416/* STA API */ 5417 5418/** 5419 * enum iwm_sta_flags - flags for the ADD_STA host command 5420 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5421 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5422 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5423 * @IWM_STA_FLG_PS: set if STA is in Power Save 5424 * @IWM_STA_FLG_INVALID: set if STA is invalid 5425 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5426 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5427 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5428 * @IWM_STA_FLG_PAN: STA is for PAN interface 5429 * @IWM_STA_FLG_CLASS_AUTH: 5430 * @IWM_STA_FLG_CLASS_ASSOC: 5431 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5432 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5433 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5434 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5435 * initialised by driver and can be updated by fw upon reception of 5436 * action frames that can change the channel width. When cleared the fw 5437 * will send all the frames in 20MHz even when FAT channel is requested. 5438 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5439 * driver and can be updated by fw upon reception of action frames. 5440 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5441 */ 5442enum iwm_sta_flags { 5443 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5444 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5445 5446 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5447 5448 IWM_STA_FLG_PS = (1 << 8), 5449 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5450 IWM_STA_FLG_PAN = (1 << 13), 5451 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5452 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5453 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5454 5455 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5456 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5457 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5458 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5459 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5460 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5461 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5462 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5463 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5464 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5465 5466 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5467 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5468 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5469 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5470 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5471 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5472 5473 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5474 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5475 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5476 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5477 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5478 5479 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5480 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5481 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5482 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5483}; 5484 5485/** 5486 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5487 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5488 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5489 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5490 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5491 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5492 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5493 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5494 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5495 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5496 * station info array (1 - n 1X mode) 5497 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5498 * @IWM_STA_KEY_NOT_VALID: key is invalid 5499 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5500 * @IWM_STA_KEY_MULTICAST: set for multical key 5501 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5502 */ 5503enum iwm_sta_key_flag { 5504 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5505 IWM_STA_KEY_FLG_WEP = (1 << 0), 5506 IWM_STA_KEY_FLG_CCM = (2 << 0), 5507 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5508 IWM_STA_KEY_FLG_EXT = (4 << 0), 5509 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5510 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5511 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5512 5513 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5514 IWM_STA_KEY_FLG_KEYID_POS = 8, 5515 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5516 IWM_STA_KEY_NOT_VALID = (1 << 11), 5517 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5518 IWM_STA_KEY_MULTICAST = (1 << 14), 5519 IWM_STA_KEY_MFP = (1 << 15), 5520}; 5521 5522/** 5523 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5524 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5525 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5526 * @IWM_STA_MODIFY_TX_RATE: unused 5527 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5528 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5529 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5530 * @IWM_STA_MODIFY_PROT_TH: 5531 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5532 */ 5533enum iwm_sta_modify_flag { 5534 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5535 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5536 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5537 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5538 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5539 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5540 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5541 IWM_STA_MODIFY_QUEUES = (1 << 7), 5542}; 5543 5544#define IWM_STA_MODE_MODIFY 1 5545 5546/** 5547 * enum iwm_sta_sleep_flag - type of sleep of the station 5548 * @IWM_STA_SLEEP_STATE_AWAKE: 5549 * @IWM_STA_SLEEP_STATE_PS_POLL: 5550 * @IWM_STA_SLEEP_STATE_UAPSD: 5551 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5552 * (last) released frame 5553 */ 5554enum iwm_sta_sleep_flag { 5555 IWM_STA_SLEEP_STATE_AWAKE = 0, 5556 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5557 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5558 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5559}; 5560 5561/* STA ID and color bits definitions */ 5562#define IWM_STA_ID_SEED (0x0f) 5563#define IWM_STA_ID_POS (0) 5564#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5565 5566#define IWM_STA_COLOR_SEED (0x7) 5567#define IWM_STA_COLOR_POS (4) 5568#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5569 5570#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5571 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5572#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5573 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5574 5575#define IWM_STA_KEY_MAX_NUM (16) 5576#define IWM_STA_KEY_IDX_INVALID (0xff) 5577#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5578#define IWM_MAX_GLOBAL_KEYS (4) 5579#define IWM_STA_KEY_LEN_WEP40 (5) 5580#define IWM_STA_KEY_LEN_WEP104 (13) 5581 5582/** 5583 * struct iwm_mvm_keyinfo - key information 5584 * @key_flags: type %iwm_sta_key_flag 5585 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5586 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5587 * @key_offset: key offset in the fw's key table 5588 * @key: 16-byte unicast decryption key 5589 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5590 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5591 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5592 */ 5593struct iwm_mvm_keyinfo { 5594 uint16_t key_flags; 5595 uint8_t tkip_rx_tsc_byte2; 5596 uint8_t reserved1; 5597 uint16_t tkip_rx_ttak[5]; 5598 uint8_t key_offset; 5599 uint8_t reserved2; 5600 uint8_t key[16]; 5601 uint64_t tx_secur_seq_cnt; 5602 uint64_t hw_tkip_mic_rx_key; 5603 uint64_t hw_tkip_mic_tx_key; 5604} __packed; 5605 5606#define IWM_ADD_STA_STATUS_MASK 0xFF 5607#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5608#define IWM_ADD_STA_BAID_MASK 0x7F00 5609#define IWM_ADD_STA_BAID_SHIFT 8 5610 5611/** 5612 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5613 * ( REPLY_ADD_STA = 0x18 ) 5614 * @add_modify: 1: modify existing, 0: add new station 5615 * @awake_acs: 5616 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5617 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5618 * @mac_id_n_color: the Mac context this station belongs to 5619 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5620 * @sta_id: index of station in uCode's station table 5621 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5622 * alone. 1 - modify, 0 - don't change. 5623 * @station_flags: look at %iwm_sta_flags 5624 * @station_flags_msk: what of %station_flags have changed 5625 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5626 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5627 * add_immediate_ba_ssn. 5628 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5629 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5630 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5631 * add_immediate_ba_tid. 5632 * @sleep_tx_count: number of packets to transmit to station even though it is 5633 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5634 * keeps track of STA sleep state. 5635 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5636 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5637 * mac-addr. 5638 * @beamform_flags: beam forming controls 5639 * @tfd_queue_msk: tfd queues used by this station 5640 * 5641 * The device contains an internal table of per-station information, with info 5642 * on security keys, aggregation parameters, and Tx rates for initial Tx 5643 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5644 * 5645 * ADD_STA sets up the table entry for one station, either creating a new 5646 * entry, or modifying a pre-existing one. 5647 */ 5648struct iwm_mvm_add_sta_cmd { 5649 uint8_t add_modify; 5650 uint8_t awake_acs; 5651 uint16_t tid_disable_tx; 5652 uint32_t mac_id_n_color; 5653 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5654 uint16_t reserved2; 5655 uint8_t sta_id; 5656 uint8_t modify_mask; 5657 uint16_t reserved3; 5658 uint32_t station_flags; 5659 uint32_t station_flags_msk; 5660 uint8_t add_immediate_ba_tid; 5661 uint8_t remove_immediate_ba_tid; 5662 uint16_t add_immediate_ba_ssn; 5663 uint16_t sleep_tx_count; 5664 uint16_t sleep_state_flags; 5665 uint16_t assoc_id; 5666 uint16_t beamform_flags; 5667 uint32_t tfd_queue_msk; 5668} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5669 5670/** 5671 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5672 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5673 * @sta_id: index of station in uCode's station table 5674 * @key_offset: key offset in key storage 5675 * @key_flags: type %iwm_sta_key_flag 5676 * @key: key material data 5677 * @key2: key material data 5678 * @rx_secur_seq_cnt: RX security sequence counter for the key 5679 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5680 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5681 */ 5682struct iwm_mvm_add_sta_key_cmd { 5683 uint8_t sta_id; 5684 uint8_t key_offset; 5685 uint16_t key_flags; 5686 uint8_t key[16]; 5687 uint8_t key2[16]; 5688 uint8_t rx_secur_seq_cnt[16]; 5689 uint8_t tkip_rx_tsc_byte2; 5690 uint8_t reserved; 5691 uint16_t tkip_rx_ttak[5]; 5692} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5693 5694/** 5695 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5696 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5697 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5698 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5699 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5700 * that doesn't exist. 5701 */ 5702enum iwm_mvm_add_sta_rsp_status { 5703 IWM_ADD_STA_SUCCESS = 0x1, 5704 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5705 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5706 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5707}; 5708 5709/** 5710 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5711 * ( IWM_REMOVE_STA = 0x19 ) 5712 * @sta_id: the station id of the station to be removed 5713 */ 5714struct iwm_mvm_rm_sta_cmd { 5715 uint8_t sta_id; 5716 uint8_t reserved[3]; 5717} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5718 5719/** 5720 * struct iwm_mvm_mgmt_mcast_key_cmd 5721 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5722 * @ctrl_flags: %iwm_sta_key_flag 5723 * @IGTK: 5724 * @K1: IGTK master key 5725 * @K2: IGTK sub key 5726 * @sta_id: station ID that support IGTK 5727 * @key_id: 5728 * @receive_seq_cnt: initial RSC/PN needed for replay check 5729 */ 5730struct iwm_mvm_mgmt_mcast_key_cmd { 5731 uint32_t ctrl_flags; 5732 uint8_t IGTK[16]; 5733 uint8_t K1[16]; 5734 uint8_t K2[16]; 5735 uint32_t key_id; 5736 uint32_t sta_id; 5737 uint64_t receive_seq_cnt; 5738} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5739 5740struct iwm_mvm_wep_key { 5741 uint8_t key_index; 5742 uint8_t key_offset; 5743 uint16_t reserved1; 5744 uint8_t key_size; 5745 uint8_t reserved2[3]; 5746 uint8_t key[16]; 5747} __packed; 5748 5749struct iwm_mvm_wep_key_cmd { 5750 uint32_t mac_id_n_color; 5751 uint8_t num_keys; 5752 uint8_t decryption_type; 5753 uint8_t flags; 5754 uint8_t reserved; 5755 struct iwm_mvm_wep_key wep_key[0]; 5756} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5757 5758/* 5759 * END mvm/fw-api-sta.h 5760 */ 5761 5762/* 5763 * BT coex 5764 */ 5765 5766enum iwm_bt_coex_mode { 5767 IWM_BT_COEX_DISABLE = 0x0, 5768 IWM_BT_COEX_NW = 0x1, 5769 IWM_BT_COEX_BT = 0x2, 5770 IWM_BT_COEX_WIFI = 0x3, 5771}; /* BT_COEX_MODES_E */ 5772 5773enum iwm_bt_coex_enabled_modules { 5774 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5775 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5776 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5777 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5778 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5779}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5780 5781/** 5782 * struct iwm_bt_coex_cmd - bt coex configuration command 5783 * @mode: enum %iwm_bt_coex_mode 5784 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5785 * 5786 * The structure is used for the BT_COEX command. 5787 */ 5788struct iwm_bt_coex_cmd { 5789 uint32_t mode; 5790 uint32_t enabled_modules; 5791} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5792 5793 5794/* 5795 * Location Aware Regulatory (LAR) API - MCC updates 5796 */ 5797 5798/** 5799 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5800 * regulatory profile according to the given MCC (Mobile Country Code). 5801 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5802 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5803 * MCC in the cmd response will be the relevant MCC in the NVM. 5804 * @mcc: given mobile country code 5805 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5806 * @reserved: reserved for alignment 5807 */ 5808struct iwm_mcc_update_cmd_v1 { 5809 uint16_t mcc; 5810 uint8_t source_id; 5811 uint8_t reserved; 5812} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5813 5814/** 5815 * struct iwm_mcc_update_cmd - Request the device to update geographic 5816 * regulatory profile according to the given MCC (Mobile Country Code). 5817 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5818 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5819 * MCC in the cmd response will be the relevant MCC in the NVM. 5820 * @mcc: given mobile country code 5821 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5822 * @reserved: reserved for alignment 5823 * @key: integrity key for MCC API OEM testing 5824 * @reserved2: reserved 5825 */ 5826struct iwm_mcc_update_cmd { 5827 uint16_t mcc; 5828 uint8_t source_id; 5829 uint8_t reserved; 5830 uint32_t key; 5831 uint32_t reserved2[5]; 5832} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5833 5834/** 5835 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5836 * Contains the new channel control profile map, if changed, and the new MCC 5837 * (mobile country code). 5838 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5839 * @status: see &enum iwm_mcc_update_status 5840 * @mcc: the new applied MCC 5841 * @cap: capabilities for all channels which matches the MCC 5842 * @source_id: the MCC source, see iwm_mcc_source 5843 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5844 * channels, depending on platform) 5845 * @channels: channel control data map, DWORD for each channel. Only the first 5846 * 16bits are used. 5847 */ 5848struct iwm_mcc_update_resp_v1 { 5849 uint32_t status; 5850 uint16_t mcc; 5851 uint8_t cap; 5852 uint8_t source_id; 5853 uint32_t n_channels; 5854 uint32_t channels[0]; 5855} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5856 5857/** 5858 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5859 * Contains the new channel control profile map, if changed, and the new MCC 5860 * (mobile country code). 5861 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5862 * @status: see &enum iwm_mcc_update_status 5863 * @mcc: the new applied MCC 5864 * @cap: capabilities for all channels which matches the MCC 5865 * @source_id: the MCC source, see iwm_mcc_source 5866 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5867 * @reserved: reserved. 5868 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5869 * channels, depending on platform) 5870 * @channels: channel control data map, DWORD for each channel. Only the first 5871 * 16bits are used. 5872 */ 5873struct iwm_mcc_update_resp { 5874 uint32_t status; 5875 uint16_t mcc; 5876 uint8_t cap; 5877 uint8_t source_id; 5878 uint16_t time; 5879 uint16_t reserved; 5880 uint32_t n_channels; 5881 uint32_t channels[0]; 5882} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5883 5884/** 5885 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5886 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5887 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5888 * the cellular and connectivity cores that gets updates of the mcc, and 5889 * notifies the ucode directly of any mcc change. 5890 * The ucode requests the driver to request the device to update geographic 5891 * regulatory profile according to the given MCC (Mobile Country Code). 5892 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5893 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5894 * MCC in the cmd response will be the relevant MCC in the NVM. 5895 * @mcc: given mobile country code 5896 * @source_id: identity of the change originator, see iwm_mcc_source 5897 * @reserved1: reserved for alignment 5898 */ 5899struct iwm_mcc_chub_notif { 5900 uint16_t mcc; 5901 uint8_t source_id; 5902 uint8_t reserved1; 5903} __packed; /* LAR_MCC_NOTIFY_S */ 5904 5905enum iwm_mcc_update_status { 5906 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5907 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5908 IWM_MCC_RESP_INVALID, 5909 IWM_MCC_RESP_NVM_DISABLED, 5910 IWM_MCC_RESP_ILLEGAL, 5911 IWM_MCC_RESP_LOW_PRIORITY, 5912 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5913 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5914 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5915}; 5916 5917enum iwm_mcc_source { 5918 IWM_MCC_SOURCE_OLD_FW = 0, 5919 IWM_MCC_SOURCE_ME = 1, 5920 IWM_MCC_SOURCE_BIOS = 2, 5921 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5922 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5923 IWM_MCC_SOURCE_WIFI = 5, 5924 IWM_MCC_SOURCE_RESERVED = 6, 5925 IWM_MCC_SOURCE_DEFAULT = 7, 5926 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5927 IWM_MCC_SOURCE_MCC_API = 9, 5928 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5929 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5930}; 5931 5932/** 5933 * struct iwm_dts_measurement_notif_v1 - measurements notification 5934 * 5935 * @temp: the measured temperature 5936 * @voltage: the measured voltage 5937 */ 5938struct iwm_dts_measurement_notif_v1 { 5939 int32_t temp; 5940 int32_t voltage; 5941} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5942 5943/** 5944 * struct iwm_dts_measurement_notif_v2 - measurements notification 5945 * 5946 * @temp: the measured temperature 5947 * @voltage: the measured voltage 5948 * @threshold_idx: the trip index that was crossed 5949 */ 5950struct iwm_dts_measurement_notif_v2 { 5951 int32_t temp; 5952 int32_t voltage; 5953 int32_t threshold_idx; 5954} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5955 5956/* 5957 * Some cherry-picked definitions 5958 */ 5959 5960#define IWM_FRAME_LIMIT 64 5961 5962/* 5963 * These functions retrieve specific information from the id field in 5964 * the iwm_host_cmd struct which contains the command id, the group id, 5965 * and the version of the command and vice versa. 5966*/ 5967static inline uint8_t 5968iwm_cmd_opcode(uint32_t cmdid) 5969{ 5970 return cmdid & 0xff; 5971} 5972 5973static inline uint8_t 5974iwm_cmd_groupid(uint32_t cmdid) 5975{ 5976 return ((cmdid & 0xff00) >> 8); 5977} 5978 5979static inline uint8_t 5980iwm_cmd_version(uint32_t cmdid) 5981{ 5982 return ((cmdid & 0xff0000) >> 16); 5983} 5984 5985static inline uint32_t 5986iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 5987{ 5988 return opcode + (groupid << 8) + (version << 16); 5989} 5990 5991/* make uint16_t wide id out of uint8_t group and opcode */ 5992#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 5993 5994/* due to the conversion, this group is special */ 5995#define IWM_ALWAYS_LONG_GROUP 1 5996 5997struct iwm_cmd_header { 5998 uint8_t code; 5999 uint8_t flags; 6000 uint8_t idx; 6001 uint8_t qid; 6002} __packed; 6003 6004struct iwm_cmd_header_wide { 6005 uint8_t opcode; 6006 uint8_t group_id; 6007 uint8_t idx; 6008 uint8_t qid; 6009 uint16_t length; 6010 uint8_t reserved; 6011 uint8_t version; 6012} __packed; 6013 6014/** 6015 * enum iwm_power_scheme 6016 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6017 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6018 * @IWM_POWER_LEVEL_LP - Low Power 6019 */ 6020enum iwm_power_scheme { 6021 IWM_POWER_SCHEME_CAM = 1, 6022 IWM_POWER_SCHEME_BPS, 6023 IWM_POWER_SCHEME_LP 6024}; 6025 6026#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6027#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6028#define IWM_CMD_FAILED_MSK 0x40 6029 6030/** 6031 * struct iwm_device_cmd 6032 * 6033 * For allocation of the command and tx queues, this establishes the overall 6034 * size of the largest command we send to uCode, except for commands that 6035 * aren't fully copied and use other TFD space. 6036 */ 6037struct iwm_device_cmd { 6038 union { 6039 struct { 6040 struct iwm_cmd_header hdr; 6041 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6042 }; 6043 struct { 6044 struct iwm_cmd_header_wide hdr_wide; 6045 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6046 sizeof(struct iwm_cmd_header_wide) + 6047 sizeof(struct iwm_cmd_header)]; 6048 }; 6049 }; 6050} __packed; 6051 6052struct iwm_rx_packet { 6053 /* 6054 * The first 4 bytes of the RX frame header contain both the RX frame 6055 * size and some flags. 6056 * Bit fields: 6057 * 31: flag flush RB request 6058 * 30: flag ignore TC (terminal counter) request 6059 * 29: flag fast IRQ request 6060 * 28-14: Reserved 6061 * 13-00: RX frame size 6062 */ 6063 uint32_t len_n_flags; 6064 struct iwm_cmd_header hdr; 6065 uint8_t data[]; 6066} __packed; 6067 6068#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6069#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6070#define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6071 6072static inline uint32_t 6073iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6074{ 6075 6076 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6077} 6078 6079static inline uint32_t 6080iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6081{ 6082 6083 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6084} 6085 6086 6087#define IWM_MIN_DBM -100 6088#define IWM_MAX_DBM -33 /* realistic guess */ 6089 6090#define IWM_READ(sc, reg) \ 6091 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6092 6093#define IWM_WRITE(sc, reg, val) \ 6094 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6095 6096#define IWM_WRITE_1(sc, reg, val) \ 6097 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6098 6099#define IWM_SETBITS(sc, reg, mask) \ 6100 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6101 6102#define IWM_CLRBITS(sc, reg, mask) \ 6103 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6104 6105#define IWM_BARRIER_WRITE(sc) \ 6106 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6107 BUS_SPACE_BARRIER_WRITE) 6108 6109#define IWM_BARRIER_READ_WRITE(sc) \ 6110 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6111 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6112 6113#endif /* __IF_IWM_REG_H__ */ 6114