1/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2/* $FreeBSD: stable/11/sys/dev/iwm/if_iwmreg.h 330446 2018-03-05 06:59:30Z eadler $ */ 3 4/****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66#ifndef __IF_IWM_REG_H__ 67#define __IF_IWM_REG_H__ 68 69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72/* 73 * BEGIN iwl-csr.h 74 */ 75 76/* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101#define IWM_CSR_GP_CNTRL (0x024) 102 103/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104#define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106/* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114#define IWM_CSR_HW_REV (0x028) 115 116/* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122#define IWM_CSR_EEPROM_REG (0x02c) 123#define IWM_CSR_EEPROM_GP (0x030) 124#define IWM_CSR_OTP_GP_REG (0x034) 125 126#define IWM_CSR_GIO_REG (0x03C) 127#define IWM_CSR_GP_UCODE_REG (0x048) 128#define IWM_CSR_GP_DRIVER_REG (0x050) 129 130/* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139#define IWM_CSR_MBOX_SET_REG (0x088) 140#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142#define IWM_CSR_LED_REG (0x094) 143#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147/* GIO Chicken Bits (PCI Express bus link power management) */ 148#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150/* Analog phase-lock-loop configuration */ 151#define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153/* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161#define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233/* GPIO */ 234#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238/* RESET */ 239#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246/* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296/* HW REV */ 297#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300/** 301 * hw_rev values 302 */ 303enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307}; 308 309 310#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329/* EEPROM REG */ 330#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335/* EEPROM GP */ 336#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343/* One-time-programmable memory general purpose reg */ 344#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349/* GP REG */ 350#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357/* CSR GIO */ 358#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360/* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394/* GP Driver */ 395#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404/* GIO Chicken Bits (PCI Express bus link power management) */ 405#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408/* LED */ 409#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410#define IWM_CSR_LED_REG_TURN_ON (0x60) 411#define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413/* ANA_PLL */ 414#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416/* HPET MEM debug */ 417#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419/* DRAM INT TABLE */ 420#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424/* SECURE boot registers */ 425#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429}; 430 431#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439}; 440 441#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 443 444#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446 447#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 448#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 449 450#define IWM_CSR_SECURE_TIME_OUT (100) 451 452/* extended range in FW SRAM */ 453#define IWM_FW_MEM_EXTENDED_START 0x40000 454#define IWM_FW_MEM_EXTENDED_END 0x57FFF 455 456/* FW chicken bits */ 457#define IWM_LMPM_CHICK 0xa01ff8 458#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 459 460#define IWM_FH_TCSR_0_REG0 (0x1D00) 461 462/* 463 * HBUS (Host-side Bus) 464 * 465 * HBUS registers are mapped directly into PCI bus space, but are used 466 * to indirectly access device's internal memory or registers that 467 * may be powered-down. 468 * 469 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 470 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 471 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 472 * internal resources. 473 * 474 * Do not use iwl_write32()/iwl_read32() family to access these registers; 475 * these provide only simple PCI bus access, without waking up the MAC. 476 */ 477#define IWM_HBUS_BASE (0x400) 478 479/* 480 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 481 * structures, error log, event log, verifying uCode load). 482 * First write to address register, then read from or write to data register 483 * to complete the job. Once the address register is set up, accesses to 484 * data registers auto-increment the address by one dword. 485 * Bit usage for address registers (read or write): 486 * 0-31: memory address within device 487 */ 488#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 489#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 490#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 491#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 492 493/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 494#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 495#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 496 497/* 498 * Registers for accessing device's internal peripheral registers 499 * (e.g. SCD, BSM, etc.). First write to address register, 500 * then read from or write to data register to complete the job. 501 * Bit usage for address registers (read or write): 502 * 0-15: register address (offset) within device 503 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 504 */ 505#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 506#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 507#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 508#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 509 510/* enable the ID buf for read */ 511#define IWM_WFPM_PS_CTL_CLR 0xa0300c 512#define IWM_WFMP_MAC_ADDR_0 0xa03080 513#define IWM_WFMP_MAC_ADDR_1 0xa03084 514#define IWM_LMPM_PMG_EN 0xa01cec 515#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 516#define IWM_RFIC_REG_RD 0xad0470 517#define IWM_WFPM_CTRL_REG 0xa03030 518#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 519#define IWM_ENABLE_WFPM 0x80000000 520 521#define IWM_AUX_MISC_REG 0xa200b0 522#define IWM_HW_STEP_LOCATION_BITS 24 523 524#define IWM_AUX_MISC_MASTER1_EN 0xa20818 525#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 526#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 527#define IWM_RSA_ENABLE 0xa24b08 528#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 529#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 530#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 531#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 532#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 533#define IWM_SB_CPU_1_STATUS 0xa01e30 534#define IWM_SB_CPU_2_STATUS 0Xa01e34 535 536/* Used to enable DBGM */ 537#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 538 539/* 540 * Per-Tx-queue write pointer (index, really!) 541 * Indicates index to next TFD that driver will fill (1 past latest filled). 542 * Bit usage: 543 * 0-7: queue write index 544 * 11-8: queue selector 545 */ 546#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 547 548/********************************************************** 549 * CSR values 550 **********************************************************/ 551 /* 552 * host interrupt timeout value 553 * used with setting interrupt coalescing timer 554 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 555 * 556 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 557 */ 558#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 559#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 560#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 561#define IWM_HOST_INT_OPER_MODE (1 << 31) 562 563/***************************************************************************** 564 * 7000/3000 series SHR DTS addresses * 565 *****************************************************************************/ 566 567/* Diode Results Register Structure: */ 568enum iwm_dtd_diode_reg { 569 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 570 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 571 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 572 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 573 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 574 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 575/* Those are the masks INSIDE the flags bit-field: */ 576 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 577 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 578 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 579 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 580}; 581 582/* 583 * END iwl-csr.h 584 */ 585 586/* 587 * BEGIN iwl-fw.h 588 */ 589 590/** 591 * enum iwm_ucode_tlv_flag - ucode API flags 592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 593 * was a separate TLV but moved here to save space. 594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 595 * treats good CRC threshold as a boolean 596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 597 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 598 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 599 * offload profile config command. 600 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 601 * (rather than two) IPv6 addresses 602 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 603 * from the probe request template. 604 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 605 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 606 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 607 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 608 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 609 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 610 */ 611enum iwm_ucode_tlv_flag { 612 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 613 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 614 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 615 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 616 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 617 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 618 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 619 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 620 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 621 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 622 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 623 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 624}; 625 626#define IWM_UCODE_TLV_FLAG_BITS \ 627 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 628Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 629L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 630P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 631 632/** 633 * enum iwm_ucode_tlv_api - ucode api 634 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 635 * longer than the passive one, which is essential for fragmented scan. 636 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 637 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 638 * 639 * @IWM_NUM_UCODE_TLV_API: number of bits used 640 */ 641enum iwm_ucode_tlv_api { 642 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 643 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 644 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 645 646 IWM_NUM_UCODE_TLV_API = 32 647}; 648 649#define IWM_UCODE_TLV_API_BITS \ 650 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 651 652/** 653 * enum iwm_ucode_tlv_capa - ucode capabilities 654 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 655 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 656 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 657 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 658 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 659 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 660 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 661 * tx power value into TPC Report action frame and Link Measurement Report 662 * action frame 663 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 664 * channel in DS parameter set element in probe requests. 665 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 666 * probe requests. 667 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 668 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 669 * which also implies support for the scheduler configuration command 670 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 671 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 672 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 673 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 674 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 675 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 676 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 677 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 678 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 679 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 680 * sources for the MCC. This TLV bit is a future replacement to 681 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 682 * is supported. 683 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 684 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 685 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 686 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 687 * 0=no support) 688 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 689 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 690 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 691 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 692 * antenna the beacon should be transmitted 693 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 694 * from AP and will send it upon d0i3 exit. 695 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 696 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 697 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 698 * thresholds reporting 699 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 700 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 701 * regular image. 702 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 703 * memory addresses from the firmware. 704 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 705 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 706 * 0=no support) 707 * 708 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 709 */ 710enum iwm_ucode_tlv_capa { 711 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 712 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 713 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 714 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 715 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 716 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 717 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 718 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 719 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 720 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 721 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 722 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 723 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 724 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 725 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 726 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 727 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 728 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 729 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 730 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 731 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 732 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 733 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 734 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 735 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 736 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 737 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 738 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 739 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 740 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 741 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 742 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 743 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 744 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 745 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 746 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 747 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 748 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 749 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 750 751 IWM_NUM_UCODE_TLV_CAPA = 128 752}; 753 754/* The default calibrate table size if not specified by firmware file */ 755#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 756#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 757#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 758 759/* The default max probe length if not specified by the firmware file */ 760#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 761 762/* 763 * enumeration of ucode section. 764 * This enumeration is used directly for older firmware (before 16.0). 765 * For new firmware, there can be up to 4 sections (see below) but the 766 * first one packaged into the firmware file is the DATA section and 767 * some debugging code accesses that. 768 */ 769enum iwm_ucode_sec { 770 IWM_UCODE_SECTION_DATA, 771 IWM_UCODE_SECTION_INST, 772}; 773/* 774 * For 16.0 uCode and above, there is no differentiation between sections, 775 * just an offset to the HW address. 776 */ 777#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 778#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 779 780/* uCode version contains 4 values: Major/Minor/API/Serial */ 781#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 782#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 783#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 784#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 785 786/* 787 * Calibration control struct. 788 * Sent as part of the phy configuration command. 789 * @flow_trigger: bitmap for which calibrations to perform according to 790 * flow triggers. 791 * @event_trigger: bitmap for which calibrations to perform according to 792 * event triggers. 793 */ 794struct iwm_tlv_calib_ctrl { 795 uint32_t flow_trigger; 796 uint32_t event_trigger; 797} __packed; 798 799enum iwm_fw_phy_cfg { 800 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 801 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 802 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 803 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 804 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 805 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 806 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 807 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 808 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 809 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 810}; 811 812#define IWM_UCODE_MAX_CS 1 813 814/** 815 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 816 * @cipher: a cipher suite selector 817 * @flags: cipher scheme flags (currently reserved for a future use) 818 * @hdr_len: a size of MPDU security header 819 * @pn_len: a size of PN 820 * @pn_off: an offset of pn from the beginning of the security header 821 * @key_idx_off: an offset of key index byte in the security header 822 * @key_idx_mask: a bit mask of key_idx bits 823 * @key_idx_shift: bit shift needed to get key_idx 824 * @mic_len: mic length in bytes 825 * @hw_cipher: a HW cipher index used in host commands 826 */ 827struct iwm_fw_cipher_scheme { 828 uint32_t cipher; 829 uint8_t flags; 830 uint8_t hdr_len; 831 uint8_t pn_len; 832 uint8_t pn_off; 833 uint8_t key_idx_off; 834 uint8_t key_idx_mask; 835 uint8_t key_idx_shift; 836 uint8_t mic_len; 837 uint8_t hw_cipher; 838} __packed; 839 840/** 841 * struct iwm_fw_cscheme_list - a cipher scheme list 842 * @size: a number of entries 843 * @cs: cipher scheme entries 844 */ 845struct iwm_fw_cscheme_list { 846 uint8_t size; 847 struct iwm_fw_cipher_scheme cs[]; 848} __packed; 849 850/* 851 * END iwl-fw.h 852 */ 853 854/* 855 * BEGIN iwl-fw-file.h 856 */ 857 858/* v1/v2 uCode file layout */ 859struct iwm_ucode_header { 860 uint32_t ver; /* major/minor/API/serial */ 861 union { 862 struct { 863 uint32_t inst_size; /* bytes of runtime code */ 864 uint32_t data_size; /* bytes of runtime data */ 865 uint32_t init_size; /* bytes of init code */ 866 uint32_t init_data_size; /* bytes of init data */ 867 uint32_t boot_size; /* bytes of bootstrap code */ 868 uint8_t data[0]; /* in same order as sizes */ 869 } v1; 870 struct { 871 uint32_t build; /* build number */ 872 uint32_t inst_size; /* bytes of runtime code */ 873 uint32_t data_size; /* bytes of runtime data */ 874 uint32_t init_size; /* bytes of init code */ 875 uint32_t init_data_size; /* bytes of init data */ 876 uint32_t boot_size; /* bytes of bootstrap code */ 877 uint8_t data[0]; /* in same order as sizes */ 878 } v2; 879 } u; 880}; 881 882/* 883 * new TLV uCode file layout 884 * 885 * The new TLV file format contains TLVs, that each specify 886 * some piece of data. 887 */ 888 889enum iwm_ucode_tlv_type { 890 IWM_UCODE_TLV_INVALID = 0, /* unused */ 891 IWM_UCODE_TLV_INST = 1, 892 IWM_UCODE_TLV_DATA = 2, 893 IWM_UCODE_TLV_INIT = 3, 894 IWM_UCODE_TLV_INIT_DATA = 4, 895 IWM_UCODE_TLV_BOOT = 5, 896 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 897 IWM_UCODE_TLV_PAN = 7, 898 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 899 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 900 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 901 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 902 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 903 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 904 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 905 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 906 IWM_UCODE_TLV_WOWLAN_INST = 16, 907 IWM_UCODE_TLV_WOWLAN_DATA = 17, 908 IWM_UCODE_TLV_FLAGS = 18, 909 IWM_UCODE_TLV_SEC_RT = 19, 910 IWM_UCODE_TLV_SEC_INIT = 20, 911 IWM_UCODE_TLV_SEC_WOWLAN = 21, 912 IWM_UCODE_TLV_DEF_CALIB = 22, 913 IWM_UCODE_TLV_PHY_SKU = 23, 914 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 915 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 916 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 917 IWM_UCODE_TLV_NUM_OF_CPU = 27, 918 IWM_UCODE_TLV_CSCHEME = 28, 919 920 /* 921 * Following two are not in our base tag, but allow 922 * handling ucode version 9. 923 */ 924 IWM_UCODE_TLV_API_CHANGES_SET = 29, 925 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 926 927 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 928 IWM_UCODE_TLV_PAGING = 32, 929 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 930 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 931 IWM_UCODE_TLV_FW_VERSION = 36, 932 IWM_UCODE_TLV_FW_DBG_DEST = 38, 933 IWM_UCODE_TLV_FW_DBG_CONF = 39, 934 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 935 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 936 IWM_UCODE_TLV_FW_MEM_SEG = 51, 937}; 938 939struct iwm_ucode_tlv { 940 uint32_t type; /* see above */ 941 uint32_t length; /* not including type/length fields */ 942 uint8_t data[0]; 943}; 944 945struct iwm_ucode_api { 946 uint32_t api_index; 947 uint32_t api_flags; 948} __packed; 949 950struct iwm_ucode_capa { 951 uint32_t api_index; 952 uint32_t api_capa; 953} __packed; 954 955#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 956 957struct iwm_tlv_ucode_header { 958 /* 959 * The TLV style ucode header is distinguished from 960 * the v1/v2 style header by first four bytes being 961 * zero, as such is an invalid combination of 962 * major/minor/API/serial versions. 963 */ 964 uint32_t zero; 965 uint32_t magic; 966 uint8_t human_readable[64]; 967 uint32_t ver; /* major/minor/API/serial */ 968 uint32_t build; 969 uint64_t ignore; 970 /* 971 * The data contained herein has a TLV layout, 972 * see above for the TLV header and types. 973 * Note that each TLV is padded to a length 974 * that is a multiple of 4 for alignment. 975 */ 976 uint8_t data[0]; 977}; 978 979/* 980 * END iwl-fw-file.h 981 */ 982 983/* 984 * BEGIN iwl-prph.h 985 */ 986 987/* 988 * Registers in this file are internal, not PCI bus memory mapped. 989 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 990 */ 991#define IWM_PRPH_BASE (0x00000) 992#define IWM_PRPH_END (0xFFFFF) 993 994/* APMG (power management) constants */ 995#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 996#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 997#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 998#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 999#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1000#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1001#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1002#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1003#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1004#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1005#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1006 1007#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1008#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1009#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1010 1011#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1012#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1013#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1014#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1015#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1016#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1017#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1018 1019#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1020 1021#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1022 1023/* Device system time */ 1024#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1025 1026/* Device NMI register */ 1027#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1028#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1029#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1030#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1031#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1032 1033/* 1034 * Device reset for family 8000 1035 * write to bit 24 in order to reset the CPU 1036 */ 1037#define IWM_RELEASE_CPU_RESET 0x300c 1038#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1039 1040 1041/***************************************************************************** 1042 * 7000/3000 series SHR DTS addresses * 1043 *****************************************************************************/ 1044 1045#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1046#define IWM_DTSC_CFG_MODE (0x00a10604) 1047#define IWM_DTSC_VREF_AVG (0x00a10648) 1048#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1049#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1050#define IWM_DTSC_PTAT_AVG (0x00a10650) 1051 1052 1053/** 1054 * Tx Scheduler 1055 * 1056 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1057 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1058 * host DRAM. It steers each frame's Tx command (which contains the frame 1059 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1060 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1061 * but one DMA channel may take input from several queues. 1062 * 1063 * Tx DMA FIFOs have dedicated purposes. 1064 * 1065 * For 5000 series and up, they are used differently 1066 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1067 * 1068 * 0 -- EDCA BK (background) frames, lowest priority 1069 * 1 -- EDCA BE (best effort) frames, normal priority 1070 * 2 -- EDCA VI (video) frames, higher priority 1071 * 3 -- EDCA VO (voice) and management frames, highest priority 1072 * 4 -- unused 1073 * 5 -- unused 1074 * 6 -- unused 1075 * 7 -- Commands 1076 * 1077 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1078 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1079 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1080 * 1081 * The driver sets up each queue to work in one of two modes: 1082 * 1083 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1084 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1085 * contains TFDs for a unique combination of Recipient Address (RA) 1086 * and Traffic Identifier (TID), that is, traffic of a given 1087 * Quality-Of-Service (QOS) priority, destined for a single station. 1088 * 1089 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1090 * each frame within the BA window, including whether it's been transmitted, 1091 * and whether it's been acknowledged by the receiving station. The device 1092 * automatically processes block-acks received from the receiving STA, 1093 * and reschedules un-acked frames to be retransmitted (successful 1094 * Tx completion may end up being out-of-order). 1095 * 1096 * The driver must maintain the queue's Byte Count table in host DRAM 1097 * for this mode. 1098 * This mode does not support fragmentation. 1099 * 1100 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1101 * The device may automatically retry Tx, but will retry only one frame 1102 * at a time, until receiving ACK from receiving station, or reaching 1103 * retry limit and giving up. 1104 * 1105 * The command queue (#4/#9) must use this mode! 1106 * This mode does not require use of the Byte Count table in host DRAM. 1107 * 1108 * Driver controls scheduler operation via 3 means: 1109 * 1) Scheduler registers 1110 * 2) Shared scheduler data base in internal SRAM 1111 * 3) Shared data in host DRAM 1112 * 1113 * Initialization: 1114 * 1115 * When loading, driver should allocate memory for: 1116 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1117 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1118 * (1024 bytes for each queue). 1119 * 1120 * After receiving "Alive" response from uCode, driver must initialize 1121 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1122 * the driver can't issue commands!): 1123 */ 1124#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1125 1126/** 1127 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1128 * can keep track of at one time when creating block-ack chains of frames. 1129 * Note that "64" matches the number of ack bits in a block-ack packet. 1130 */ 1131#define IWM_SCD_WIN_SIZE 64 1132#define IWM_SCD_FRAME_LIMIT 64 1133 1134#define IWM_SCD_TXFIFO_POS_TID (0) 1135#define IWM_SCD_TXFIFO_POS_RA (4) 1136#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1137 1138/* agn SCD */ 1139#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1140#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1141#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1142#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1143#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1144 1145#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1146#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1147#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1148#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1149#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1150#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1151#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1152#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1153#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1154#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1155 1156/* Context Data */ 1157#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1158#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1159 1160/* Tx status */ 1161#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1162#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1163 1164/* Translation Data */ 1165#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1166#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1167 1168#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1169 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1170 1171#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1172 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1173 1174#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1175 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1176 1177#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1178 1179#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1180#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1181#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1182#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1183#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1184#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1185#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1186#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1187#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1188#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1189#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1190 1191static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1192{ 1193 if (chnl < 20) 1194 return IWM_SCD_BASE + 0x18 + chnl * 4; 1195 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1196} 1197 1198static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1199{ 1200 if (chnl < 20) 1201 return IWM_SCD_BASE + 0x68 + chnl * 4; 1202 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1203} 1204 1205static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1206{ 1207 if (chnl < 20) 1208 return IWM_SCD_BASE + 0x10c + chnl * 4; 1209 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1210} 1211 1212/*********************** END TX SCHEDULER *************************************/ 1213 1214/* Oscillator clock */ 1215#define IWM_OSC_CLK (0xa04068) 1216#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1217 1218/* 1219 * END iwl-prph.h 1220 */ 1221 1222/* 1223 * BEGIN iwl-fh.h 1224 */ 1225 1226/****************************/ 1227/* Flow Handler Definitions */ 1228/****************************/ 1229 1230/** 1231 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1232 * Addresses are offsets from device's PCI hardware base address. 1233 */ 1234#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1235#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1236 1237/** 1238 * Keep-Warm (KW) buffer base address. 1239 * 1240 * Driver must allocate a 4KByte buffer that is for keeping the 1241 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1242 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1243 * from going into a power-savings mode that would cause higher DRAM latency, 1244 * and possible data over/under-runs, before all Tx/Rx is complete. 1245 * 1246 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1247 * of the buffer, which must be 4K aligned. Once this is set up, the device 1248 * automatically invokes keep-warm accesses when normal accesses might not 1249 * be sufficient to maintain fast DRAM response. 1250 * 1251 * Bit fields: 1252 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1253 */ 1254#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1255 1256 1257/** 1258 * TFD Circular Buffers Base (CBBC) addresses 1259 * 1260 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1261 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1262 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1263 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1264 * aligned (address bits 0-7 must be 0). 1265 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1266 * for them are in different places. 1267 * 1268 * Bit fields in each pointer register: 1269 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1270 */ 1271#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1272#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1273#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1274#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1275#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1276#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1277 1278/* Find TFD CB base pointer for given queue */ 1279static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1280{ 1281 if (chnl < 16) 1282 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1283 if (chnl < 20) 1284 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1285 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1286} 1287 1288 1289/** 1290 * Rx SRAM Control and Status Registers (RSCSR) 1291 * 1292 * These registers provide handshake between driver and device for the Rx queue 1293 * (this queue handles *all* command responses, notifications, Rx data, etc. 1294 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1295 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1296 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1297 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1298 * mapping between RBDs and RBs. 1299 * 1300 * Driver must allocate host DRAM memory for the following, and set the 1301 * physical address of each into device registers: 1302 * 1303 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1304 * entries (although any power of 2, up to 4096, is selectable by driver). 1305 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1306 * (typically 4K, although 8K or 16K are also selectable by driver). 1307 * Driver sets up RB size and number of RBDs in the CB via Rx config 1308 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1309 * 1310 * Bit fields within one RBD: 1311 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1312 * 1313 * Driver sets physical address [35:8] of base of RBD circular buffer 1314 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1315 * 1316 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1317 * (RBs) have been filled, via a "write pointer", actually the index of 1318 * the RB's corresponding RBD within the circular buffer. Driver sets 1319 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1320 * 1321 * Bit fields in lower dword of Rx status buffer (upper dword not used 1322 * by driver: 1323 * 31-12: Not used by driver 1324 * 11- 0: Index of last filled Rx buffer descriptor 1325 * (device writes, driver reads this value) 1326 * 1327 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1328 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1329 * and update the device's "write" index register, 1330 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1331 * 1332 * This "write" index corresponds to the *next* RBD that the driver will make 1333 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1334 * the circular buffer. This value should initially be 0 (before preparing any 1335 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1336 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1337 * "read" index has advanced past 1! See below). 1338 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1339 * 1340 * As the device fills RBs (referenced from contiguous RBDs within the circular 1341 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1342 * to tell the driver the index of the latest filled RBD. The driver must 1343 * read this "read" index from DRAM after receiving an Rx interrupt from device 1344 * 1345 * The driver must also internally keep track of a third index, which is the 1346 * next RBD to process. When receiving an Rx interrupt, driver should process 1347 * all filled but unprocessed RBs up to, but not including, the RB 1348 * corresponding to the "read" index. For example, if "read" index becomes "1", 1349 * driver may process the RB pointed to by RBD 0. Depending on volume of 1350 * traffic, there may be many RBs to process. 1351 * 1352 * If read index == write index, device thinks there is no room to put new data. 1353 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1354 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1355 * and "read" indexes; that is, make sure that there are no more than 254 1356 * buffers waiting to be filled. 1357 */ 1358#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1359#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1360#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1361 1362/** 1363 * Physical base address of 8-byte Rx Status buffer. 1364 * Bit fields: 1365 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1366 */ 1367#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1368 1369/** 1370 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1371 * Bit fields: 1372 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1373 */ 1374#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1375 1376/** 1377 * Rx write pointer (index, really!). 1378 * Bit fields: 1379 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1380 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1381 */ 1382#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1383#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1384 1385#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1386#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1387 1388/** 1389 * Rx Config/Status Registers (RCSR) 1390 * Rx Config Reg for channel 0 (only channel used) 1391 * 1392 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1393 * normal operation (see bit fields). 1394 * 1395 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1396 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1397 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1398 * 1399 * Bit fields: 1400 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1401 * '10' operate normally 1402 * 29-24: reserved 1403 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1404 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1405 * 19-18: reserved 1406 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1407 * '10' 12K, '11' 16K. 1408 * 15-14: reserved 1409 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1410 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1411 * typical value 0x10 (about 1/2 msec) 1412 * 3- 0: reserved 1413 */ 1414#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1415#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1416#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1417 1418#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1419#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1420#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1421 1422#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1423#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1424#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1425#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1426#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1427#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1428 1429#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1430#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1431#define IWM_RX_RB_TIMEOUT (0x11) 1432 1433#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1434#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1435#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1436 1437#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1438#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1439#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1440#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1441 1442#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1443#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1444#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1445 1446/** 1447 * Rx Shared Status Registers (RSSR) 1448 * 1449 * After stopping Rx DMA channel (writing 0 to 1450 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1451 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1452 * 1453 * Bit fields: 1454 * 24: 1 = Channel 0 is idle 1455 * 1456 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1457 * contain default values that should not be altered by the driver. 1458 */ 1459#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1460#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1461 1462#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1463#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1464#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1465 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1466 1467#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1468 1469#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1470 1471/* TFDB Area - TFDs buffer table */ 1472#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1473#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1474#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1475#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1476#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1477 1478/** 1479 * Transmit DMA Channel Control/Status Registers (TCSR) 1480 * 1481 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1482 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1483 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1484 * 1485 * To use a Tx DMA channel, driver must initialize its 1486 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1487 * 1488 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1489 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1490 * 1491 * All other bits should be 0. 1492 * 1493 * Bit fields: 1494 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1495 * '10' operate normally 1496 * 29- 4: Reserved, set to "0" 1497 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1498 * 2- 0: Reserved, set to "0" 1499 */ 1500#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1501#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1502 1503/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1504#define IWM_FH_TCSR_CHNL_NUM (8) 1505 1506/* TCSR: tx_config register values */ 1507#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1508 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1509#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1510 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1511#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1512 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1513 1514#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1515#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1516 1517#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1518#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1519 1520#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1521#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1522#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1523 1524#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1525#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1526#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1527 1528#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1529#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1530#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1531 1532#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1533#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1534#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1535 1536#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1537#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1538 1539/** 1540 * Tx Shared Status Registers (TSSR) 1541 * 1542 * After stopping Tx DMA channel (writing 0 to 1543 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1544 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1545 * (channel's buffers empty | no pending requests). 1546 * 1547 * Bit fields: 1548 * 31-24: 1 = Channel buffers empty (channel 7:0) 1549 * 23-16: 1 = No pending requests (channel 7:0) 1550 */ 1551#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1552#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1553 1554#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1555 1556/** 1557 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1558 * 31: Indicates an address error when accessed to internal memory 1559 * uCode/driver must write "1" in order to clear this flag 1560 * 30: Indicates that Host did not send the expected number of dwords to FH 1561 * uCode/driver must write "1" in order to clear this flag 1562 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1563 * command was received from the scheduler while the TRB was already full 1564 * with previous command 1565 * uCode/driver must write "1" in order to clear this flag 1566 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1567 * bit is set, it indicates that the FH has received a full indication 1568 * from the RTC TxFIFO and the current value of the TxCredit counter was 1569 * not equal to zero. This mean that the credit mechanism was not 1570 * synchronized to the TxFIFO status 1571 * uCode/driver must write "1" in order to clear this flag 1572 */ 1573#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1574#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1575 1576#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1577 1578/* Tx service channels */ 1579#define IWM_FH_SRVC_CHNL (9) 1580#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1581#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1582#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1583 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1584 1585#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1586#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1587 (_chan) * 4) 1588 1589/* Instruct FH to increment the retry count of a packet when 1590 * it is brought from the memory to TX-FIFO 1591 */ 1592#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1593 1594#define IWM_RX_QUEUE_SIZE 256 1595#define IWM_RX_QUEUE_MASK 255 1596#define IWM_RX_QUEUE_SIZE_LOG 8 1597 1598/* 1599 * RX related structures and functions 1600 */ 1601#define IWM_RX_FREE_BUFFERS 64 1602#define IWM_RX_LOW_WATERMARK 8 1603 1604/** 1605 * struct iwm_rb_status - reseve buffer status 1606 * host memory mapped FH registers 1607 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1608 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1609 * @finished_rb_num [0:11] - Indicates the index of the current RB 1610 * in which the last frame was written to 1611 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1612 * which was transferred 1613 */ 1614struct iwm_rb_status { 1615 uint16_t closed_rb_num; 1616 uint16_t closed_fr_num; 1617 uint16_t finished_rb_num; 1618 uint16_t finished_fr_nam; 1619 uint32_t unused; 1620} __packed; 1621 1622 1623#define IWM_TFD_QUEUE_SIZE_MAX (256) 1624#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1625#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1626 IWM_TFD_QUEUE_SIZE_BC_DUP) 1627#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1628#define IWM_NUM_OF_TBS 20 1629 1630static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1631{ 1632 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1633} 1634/** 1635 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1636 * 1637 * This structure contains dma address and length of transmission address 1638 * 1639 * @lo: low [31:0] portion of the dma address of TX buffer 1640 * every even is unaligned on 16 bit boundary 1641 * @hi_n_len 0-3 [35:32] portion of dma 1642 * 4-15 length of the tx buffer 1643 */ 1644struct iwm_tfd_tb { 1645 uint32_t lo; 1646 uint16_t hi_n_len; 1647} __packed; 1648 1649/** 1650 * struct iwm_tfd 1651 * 1652 * Transmit Frame Descriptor (TFD) 1653 * 1654 * @ __reserved1[3] reserved 1655 * @ num_tbs 0-4 number of active tbs 1656 * 5 reserved 1657 * 6-7 padding (not used) 1658 * @ tbs[20] transmit frame buffer descriptors 1659 * @ __pad padding 1660 * 1661 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1662 * Both driver and device share these circular buffers, each of which must be 1663 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1664 * 1665 * Driver must indicate the physical address of the base of each 1666 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1667 * 1668 * Each TFD contains pointer/size information for up to 20 data buffers 1669 * in host DRAM. These buffers collectively contain the (one) frame described 1670 * by the TFD. Each buffer must be a single contiguous block of memory within 1671 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1672 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1673 * Tx frame, up to 8 KBytes in size. 1674 * 1675 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1676 */ 1677struct iwm_tfd { 1678 uint8_t __reserved1[3]; 1679 uint8_t num_tbs; 1680 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1681 uint32_t __pad; 1682} __packed; 1683 1684/* Keep Warm Size */ 1685#define IWM_KW_SIZE 0x1000 /* 4k */ 1686 1687/* Fixed (non-configurable) rx data from phy */ 1688 1689/** 1690 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1691 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1692 * @tfd_offset 0-12 - tx command byte count 1693 * 12-16 - station index 1694 */ 1695struct iwm_agn_scd_bc_tbl { 1696 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1697} __packed; 1698 1699/* 1700 * END iwl-fh.h 1701 */ 1702 1703/* 1704 * BEGIN mvm/fw-api.h 1705 */ 1706 1707/* Maximum number of Tx queues. */ 1708#define IWM_MVM_MAX_QUEUES 31 1709 1710/* Tx queue numbers */ 1711enum { 1712 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1713 IWM_MVM_CMD_QUEUE = 9, 1714 IWM_MVM_AUX_QUEUE = 15, 1715}; 1716 1717enum iwm_mvm_tx_fifo { 1718 IWM_MVM_TX_FIFO_BK = 0, 1719 IWM_MVM_TX_FIFO_BE, 1720 IWM_MVM_TX_FIFO_VI, 1721 IWM_MVM_TX_FIFO_VO, 1722 IWM_MVM_TX_FIFO_MCAST = 5, 1723 IWM_MVM_TX_FIFO_CMD = 7, 1724}; 1725 1726#define IWM_MVM_STATION_COUNT 16 1727 1728/* commands */ 1729enum { 1730 IWM_MVM_ALIVE = 0x1, 1731 IWM_REPLY_ERROR = 0x2, 1732 1733 IWM_INIT_COMPLETE_NOTIF = 0x4, 1734 1735 /* PHY context commands */ 1736 IWM_PHY_CONTEXT_CMD = 0x8, 1737 IWM_DBG_CFG = 0x9, 1738 1739 /* UMAC scan commands */ 1740 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1741 IWM_SCAN_CFG_CMD = 0xc, 1742 IWM_SCAN_REQ_UMAC = 0xd, 1743 IWM_SCAN_ABORT_UMAC = 0xe, 1744 IWM_SCAN_COMPLETE_UMAC = 0xf, 1745 1746 /* station table */ 1747 IWM_ADD_STA_KEY = 0x17, 1748 IWM_ADD_STA = 0x18, 1749 IWM_REMOVE_STA = 0x19, 1750 1751 /* TX */ 1752 IWM_TX_CMD = 0x1c, 1753 IWM_TXPATH_FLUSH = 0x1e, 1754 IWM_MGMT_MCAST_KEY = 0x1f, 1755 1756 /* scheduler config */ 1757 IWM_SCD_QUEUE_CFG = 0x1d, 1758 1759 /* global key */ 1760 IWM_WEP_KEY = 0x20, 1761 1762 /* MAC and Binding commands */ 1763 IWM_MAC_CONTEXT_CMD = 0x28, 1764 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1765 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1766 IWM_BINDING_CONTEXT_CMD = 0x2b, 1767 IWM_TIME_QUOTA_CMD = 0x2c, 1768 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1769 1770 IWM_LQ_CMD = 0x4e, 1771 1772 /* paging block to FW cpu2 */ 1773 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1774 1775 /* Scan offload */ 1776 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1777 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1778 IWM_HOT_SPOT_CMD = 0x53, 1779 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1780 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1781 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1782 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1783 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1784 1785 /* Phy */ 1786 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1787 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1788 IWM_PHY_DB_CMD = 0x6c, 1789 1790 /* Power - legacy power table command */ 1791 IWM_POWER_TABLE_CMD = 0x77, 1792 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1793 1794 /* Thermal Throttling*/ 1795 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1796 1797 /* Scanning */ 1798 IWM_SCAN_ABORT_CMD = 0x81, 1799 IWM_SCAN_START_NOTIFICATION = 0x82, 1800 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1801 1802 /* NVM */ 1803 IWM_NVM_ACCESS_CMD = 0x88, 1804 1805 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1806 1807 IWM_BEACON_NOTIFICATION = 0x90, 1808 IWM_BEACON_TEMPLATE_CMD = 0x91, 1809 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1810 IWM_BT_CONFIG = 0x9b, 1811 IWM_STATISTICS_NOTIFICATION = 0x9d, 1812 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1813 1814 /* RF-KILL commands and notifications */ 1815 IWM_CARD_STATE_CMD = 0xa0, 1816 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1817 1818 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1819 1820 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1821 1822 /* Power - new power table command */ 1823 IWM_MAC_PM_POWER_TABLE = 0xa9, 1824 1825 IWM_REPLY_RX_PHY_CMD = 0xc0, 1826 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1827 IWM_BA_NOTIF = 0xc5, 1828 1829 /* Location Aware Regulatory */ 1830 IWM_MCC_UPDATE_CMD = 0xc8, 1831 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1832 1833 /* BT Coex */ 1834 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1835 IWM_BT_COEX_PROT_ENV = 0xcd, 1836 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1837 IWM_BT_COEX_CI = 0x5d, 1838 1839 IWM_REPLY_SF_CFG_CMD = 0xd1, 1840 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1841 1842 /* DTS measurements */ 1843 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1844 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1845 1846 IWM_REPLY_DEBUG_CMD = 0xf0, 1847 IWM_DEBUG_LOG_MSG = 0xf7, 1848 1849 IWM_MCAST_FILTER_CMD = 0xd0, 1850 1851 /* D3 commands/notifications */ 1852 IWM_D3_CONFIG_CMD = 0xd3, 1853 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1854 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1855 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1856 1857 /* for WoWLAN in particular */ 1858 IWM_WOWLAN_PATTERNS = 0xe0, 1859 IWM_WOWLAN_CONFIGURATION = 0xe1, 1860 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1861 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1862 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1863 IWM_WOWLAN_GET_STATUSES = 0xe5, 1864 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1865 1866 /* and for NetDetect */ 1867 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1868 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1869 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1870 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1871 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1872 1873 IWM_REPLY_MAX = 0xff, 1874}; 1875 1876enum iwm_phy_ops_subcmd_ids { 1877 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1878 IWM_CTDP_CONFIG_CMD = 0x03, 1879 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1880 IWM_CT_KILL_NOTIFICATION = 0xFE, 1881 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1882}; 1883 1884/* command groups */ 1885enum { 1886 IWM_LEGACY_GROUP = 0x0, 1887 IWM_LONG_GROUP = 0x1, 1888 IWM_SYSTEM_GROUP = 0x2, 1889 IWM_MAC_CONF_GROUP = 0x3, 1890 IWM_PHY_OPS_GROUP = 0x4, 1891 IWM_DATA_PATH_GROUP = 0x5, 1892 IWM_PROT_OFFLOAD_GROUP = 0xb, 1893}; 1894 1895/** 1896 * struct iwm_cmd_response - generic response struct for most commands 1897 * @status: status of the command asked, changes for each one 1898 */ 1899struct iwm_cmd_response { 1900 uint32_t status; 1901}; 1902 1903/* 1904 * struct iwm_tx_ant_cfg_cmd 1905 * @valid: valid antenna configuration 1906 */ 1907struct iwm_tx_ant_cfg_cmd { 1908 uint32_t valid; 1909} __packed; 1910 1911/** 1912 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1913 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1914 * @flags: (reserved for future implementation) 1915 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1916 * @pwr_restriction: TX power restriction in dBms. 1917 */ 1918struct iwm_reduce_tx_power_cmd { 1919 uint8_t flags; 1920 uint8_t mac_context_id; 1921 uint16_t pwr_restriction; 1922} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1923 1924/* 1925 * Calibration control struct. 1926 * Sent as part of the phy configuration command. 1927 * @flow_trigger: bitmap for which calibrations to perform according to 1928 * flow triggers. 1929 * @event_trigger: bitmap for which calibrations to perform according to 1930 * event triggers. 1931 */ 1932struct iwm_calib_ctrl { 1933 uint32_t flow_trigger; 1934 uint32_t event_trigger; 1935} __packed; 1936 1937/* This enum defines the bitmap of various calibrations to enable in both 1938 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1939 */ 1940enum iwm_calib_cfg { 1941 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1942 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1943 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1944 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1945 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1946 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1947 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1948 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1949 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1950 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1951 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1952 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1953 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1954 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1955 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1956 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1957 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1958 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1959 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1960}; 1961 1962/* 1963 * Phy configuration command. 1964 */ 1965struct iwm_phy_cfg_cmd { 1966 uint32_t phy_cfg; 1967 struct iwm_calib_ctrl calib_control; 1968} __packed; 1969 1970#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1971#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1972#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1973#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1974#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1975#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1976#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1977#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1978#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1979#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1980 1981 1982/* Target of the IWM_NVM_ACCESS_CMD */ 1983enum { 1984 IWM_NVM_ACCESS_TARGET_CACHE = 0, 1985 IWM_NVM_ACCESS_TARGET_OTP = 1, 1986 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1987}; 1988 1989/* Section types for IWM_NVM_ACCESS_CMD */ 1990enum { 1991 IWM_NVM_SECTION_TYPE_SW = 1, 1992 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 1993 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 1994 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 1995 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 1996 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 1997 IWM_NVM_MAX_NUM_SECTIONS = 13, 1998}; 1999 2000/** 2001 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2002 * @op_code: 0 - read, 1 - write 2003 * @target: IWM_NVM_ACCESS_TARGET_* 2004 * @type: IWM_NVM_SECTION_TYPE_* 2005 * @offset: offset in bytes into the section 2006 * @length: in bytes, to read/write 2007 * @data: if write operation, the data to write. On read its empty 2008 */ 2009struct iwm_nvm_access_cmd { 2010 uint8_t op_code; 2011 uint8_t target; 2012 uint16_t type; 2013 uint16_t offset; 2014 uint16_t length; 2015 uint8_t data[]; 2016} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2017 2018#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2019 2020/* 2021 * struct iwm_fw_paging_cmd - paging layout 2022 * 2023 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2024 * 2025 * Send to FW the paging layout in the driver. 2026 * 2027 * @flags: various flags for the command 2028 * @block_size: the block size in powers of 2 2029 * @block_num: number of blocks specified in the command. 2030 * @device_phy_addr: virtual addresses from device side 2031*/ 2032struct iwm_fw_paging_cmd { 2033 uint32_t flags; 2034 uint32_t block_size; 2035 uint32_t block_num; 2036 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2037} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2038 2039/* 2040 * Fw items ID's 2041 * 2042 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2043 * download 2044 */ 2045enum iwm_fw_item_id { 2046 IWM_FW_ITEM_ID_PAGING = 3, 2047}; 2048 2049/* 2050 * struct iwm_fw_get_item_cmd - get an item from the fw 2051 */ 2052struct iwm_fw_get_item_cmd { 2053 uint32_t item_id; 2054} __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2055 2056/** 2057 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2058 * @offset: offset in bytes into the section 2059 * @length: in bytes, either how much was written or read 2060 * @type: IWM_NVM_SECTION_TYPE_* 2061 * @status: 0 for success, fail otherwise 2062 * @data: if read operation, the data returned. Empty on write. 2063 */ 2064struct iwm_nvm_access_resp { 2065 uint16_t offset; 2066 uint16_t length; 2067 uint16_t type; 2068 uint16_t status; 2069 uint8_t data[]; 2070} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2071 2072/* IWM_MVM_ALIVE 0x1 */ 2073 2074/* alive response is_valid values */ 2075#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2076#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2077 2078/* alive response ver_type values */ 2079enum { 2080 IWM_FW_TYPE_HW = 0, 2081 IWM_FW_TYPE_PROT = 1, 2082 IWM_FW_TYPE_AP = 2, 2083 IWM_FW_TYPE_WOWLAN = 3, 2084 IWM_FW_TYPE_TIMING = 4, 2085 IWM_FW_TYPE_WIPAN = 5 2086}; 2087 2088/* alive response ver_subtype values */ 2089enum { 2090 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2091 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2092 IWM_FW_SUBTYPE_REDUCED = 2, 2093 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2094 IWM_FW_SUBTYPE_WOWLAN = 4, 2095 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2096 IWM_FW_SUBTYPE_WIPAN = 6, 2097 IWM_FW_SUBTYPE_INITIALIZE = 9 2098}; 2099 2100#define IWM_ALIVE_STATUS_ERR 0xDEAD 2101#define IWM_ALIVE_STATUS_OK 0xCAFE 2102 2103#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2104 2105struct iwm_mvm_alive_resp_ver1 { 2106 uint16_t status; 2107 uint16_t flags; 2108 uint8_t ucode_minor; 2109 uint8_t ucode_major; 2110 uint16_t id; 2111 uint8_t api_minor; 2112 uint8_t api_major; 2113 uint8_t ver_subtype; 2114 uint8_t ver_type; 2115 uint8_t mac; 2116 uint8_t opt; 2117 uint16_t reserved2; 2118 uint32_t timestamp; 2119 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2120 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2121 uint32_t cpu_register_ptr; 2122 uint32_t dbgm_config_ptr; 2123 uint32_t alive_counter_ptr; 2124 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2125} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2126 2127struct iwm_mvm_alive_resp_ver2 { 2128 uint16_t status; 2129 uint16_t flags; 2130 uint8_t ucode_minor; 2131 uint8_t ucode_major; 2132 uint16_t id; 2133 uint8_t api_minor; 2134 uint8_t api_major; 2135 uint8_t ver_subtype; 2136 uint8_t ver_type; 2137 uint8_t mac; 2138 uint8_t opt; 2139 uint16_t reserved2; 2140 uint32_t timestamp; 2141 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2142 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2143 uint32_t cpu_register_ptr; 2144 uint32_t dbgm_config_ptr; 2145 uint32_t alive_counter_ptr; 2146 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2147 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2148 uint32_t st_fwrd_size; 2149 uint8_t umac_minor; /* UMAC version: minor */ 2150 uint8_t umac_major; /* UMAC version: major */ 2151 uint16_t umac_id; /* UMAC version: id */ 2152 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2153 uint32_t dbg_print_buff_addr; 2154} __packed; /* ALIVE_RES_API_S_VER_2 */ 2155 2156struct iwm_mvm_alive_resp { 2157 uint16_t status; 2158 uint16_t flags; 2159 uint32_t ucode_minor; 2160 uint32_t ucode_major; 2161 uint8_t ver_subtype; 2162 uint8_t ver_type; 2163 uint8_t mac; 2164 uint8_t opt; 2165 uint32_t timestamp; 2166 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2167 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2168 uint32_t cpu_register_ptr; 2169 uint32_t dbgm_config_ptr; 2170 uint32_t alive_counter_ptr; 2171 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2172 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2173 uint32_t st_fwrd_size; 2174 uint32_t umac_minor; /* UMAC version: minor */ 2175 uint32_t umac_major; /* UMAC version: major */ 2176 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2177 uint32_t dbg_print_buff_addr; 2178} __packed; /* ALIVE_RES_API_S_VER_3 */ 2179 2180/* Error response/notification */ 2181enum { 2182 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2183 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2184 IWM_FW_ERR_SERVICE = 0x2, 2185 IWM_FW_ERR_ARC_MEMORY = 0x3, 2186 IWM_FW_ERR_ARC_CODE = 0x4, 2187 IWM_FW_ERR_WATCH_DOG = 0x5, 2188 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2189 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2190 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2191 IWM_FW_ERR_UNEXPECTED = 0xFE, 2192 IWM_FW_ERR_FATAL = 0xFF 2193}; 2194 2195/** 2196 * struct iwm_error_resp - FW error indication 2197 * ( IWM_REPLY_ERROR = 0x2 ) 2198 * @error_type: one of IWM_FW_ERR_* 2199 * @cmd_id: the command ID for which the error occurred 2200 * @bad_cmd_seq_num: sequence number of the erroneous command 2201 * @error_service: which service created the error, applicable only if 2202 * error_type = 2, otherwise 0 2203 * @timestamp: TSF in usecs. 2204 */ 2205struct iwm_error_resp { 2206 uint32_t error_type; 2207 uint8_t cmd_id; 2208 uint8_t reserved1; 2209 uint16_t bad_cmd_seq_num; 2210 uint32_t error_service; 2211 uint64_t timestamp; 2212} __packed; 2213 2214 2215/* Common PHY, MAC and Bindings definitions */ 2216 2217#define IWM_MAX_MACS_IN_BINDING (3) 2218#define IWM_MAX_BINDINGS (4) 2219#define IWM_AUX_BINDING_INDEX (3) 2220#define IWM_MAX_PHYS (4) 2221 2222/* Used to extract ID and color from the context dword */ 2223#define IWM_FW_CTXT_ID_POS (0) 2224#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2225#define IWM_FW_CTXT_COLOR_POS (8) 2226#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2227#define IWM_FW_CTXT_INVALID (0xffffffff) 2228 2229#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2230 (_color << IWM_FW_CTXT_COLOR_POS)) 2231 2232/* Possible actions on PHYs, MACs and Bindings */ 2233enum { 2234 IWM_FW_CTXT_ACTION_STUB = 0, 2235 IWM_FW_CTXT_ACTION_ADD, 2236 IWM_FW_CTXT_ACTION_MODIFY, 2237 IWM_FW_CTXT_ACTION_REMOVE, 2238 IWM_FW_CTXT_ACTION_NUM 2239}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2240 2241/* Time Events */ 2242 2243/* Time Event types, according to MAC type */ 2244enum iwm_time_event_type { 2245 /* BSS Station Events */ 2246 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2247 IWM_TE_BSS_STA_ASSOC, 2248 IWM_TE_BSS_EAP_DHCP_PROT, 2249 IWM_TE_BSS_QUIET_PERIOD, 2250 2251 /* P2P Device Events */ 2252 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2253 IWM_TE_P2P_DEVICE_LISTEN, 2254 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2255 IWM_TE_P2P_DEVICE_FULL_SCAN, 2256 2257 /* P2P Client Events */ 2258 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2259 IWM_TE_P2P_CLIENT_ASSOC, 2260 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2261 2262 /* P2P GO Events */ 2263 IWM_TE_P2P_GO_ASSOC_PROT, 2264 IWM_TE_P2P_GO_REPETITIVE_NOA, 2265 IWM_TE_P2P_GO_CT_WINDOW, 2266 2267 /* WiDi Sync Events */ 2268 IWM_TE_WIDI_TX_SYNC, 2269 2270 IWM_TE_MAX 2271}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2272 2273 2274 2275/* Time event - defines for command API v1 */ 2276 2277/* 2278 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2279 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2280 * the first fragment is scheduled. 2281 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2282 * the first 2 fragments are scheduled. 2283 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2284 * number of fragments are valid. 2285 * 2286 * Other than the constant defined above, specifying a fragmentation value 'x' 2287 * means that the event can be fragmented but only the first 'x' will be 2288 * scheduled. 2289 */ 2290enum { 2291 IWM_TE_V1_FRAG_NONE = 0, 2292 IWM_TE_V1_FRAG_SINGLE = 1, 2293 IWM_TE_V1_FRAG_DUAL = 2, 2294 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2295}; 2296 2297/* If a Time Event can be fragmented, this is the max number of fragments */ 2298#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2299/* Repeat the time event endlessly (until removed) */ 2300#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2301/* If a Time Event has bounded repetitions, this is the maximal value */ 2302#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2303 2304/* Time Event dependencies: none, on another TE, or in a specific time */ 2305enum { 2306 IWM_TE_V1_INDEPENDENT = 0, 2307 IWM_TE_V1_DEP_OTHER = (1 << 0), 2308 IWM_TE_V1_DEP_TSF = (1 << 1), 2309 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2310}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2311 2312/* 2313 * @IWM_TE_V1_NOTIF_NONE: no notifications 2314 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2315 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2316 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2317 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2318 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2319 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2320 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2321 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2322 * 2323 * Supported Time event notifications configuration. 2324 * A notification (both event and fragment) includes a status indicating weather 2325 * the FW was able to schedule the event or not. For fragment start/end 2326 * notification the status is always success. There is no start/end fragment 2327 * notification for monolithic events. 2328 */ 2329enum { 2330 IWM_TE_V1_NOTIF_NONE = 0, 2331 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2332 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2333 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2334 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2335 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2336 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2337 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2338 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2339 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2340}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2341 2342/* Time event - defines for command API */ 2343 2344/* 2345 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2346 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2347 * the first fragment is scheduled. 2348 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2349 * the first 2 fragments are scheduled. 2350 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2351 * number of fragments are valid. 2352 * 2353 * Other than the constant defined above, specifying a fragmentation value 'x' 2354 * means that the event can be fragmented but only the first 'x' will be 2355 * scheduled. 2356 */ 2357enum { 2358 IWM_TE_V2_FRAG_NONE = 0, 2359 IWM_TE_V2_FRAG_SINGLE = 1, 2360 IWM_TE_V2_FRAG_DUAL = 2, 2361 IWM_TE_V2_FRAG_MAX = 0xfe, 2362 IWM_TE_V2_FRAG_ENDLESS = 0xff 2363}; 2364 2365/* Repeat the time event endlessly (until removed) */ 2366#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2367/* If a Time Event has bounded repetitions, this is the maximal value */ 2368#define IWM_TE_V2_REPEAT_MAX 0xfe 2369 2370#define IWM_TE_V2_PLACEMENT_POS 12 2371#define IWM_TE_V2_ABSENCE_POS 15 2372 2373/* Time event policy values 2374 * A notification (both event and fragment) includes a status indicating weather 2375 * the FW was able to schedule the event or not. For fragment start/end 2376 * notification the status is always success. There is no start/end fragment 2377 * notification for monolithic events. 2378 * 2379 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2380 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2381 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2382 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2383 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2384 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2385 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2386 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2387 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2388 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2389 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2390 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2391 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2392 */ 2393enum { 2394 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2395 2396 /* notifications (event start/stop, fragment start/stop) */ 2397 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2398 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2399 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2400 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2401 2402 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2403 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2404 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2405 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2406 2407 IWM_TE_V2_NOTIF_MSK = 0xff, 2408 2409 /* placement characteristics */ 2410 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2411 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2412 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2413 2414 /* are we present or absent during the Time Event. */ 2415 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2416}; 2417 2418/** 2419 * struct iwm_time_event_cmd_api - configuring Time Events 2420 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2421 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2422 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2423 * @id_and_color: ID and color of the relevant MAC 2424 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2425 * @id: this field has two meanings, depending on the action: 2426 * If the action is ADD, then it means the type of event to add. 2427 * For all other actions it is the unique event ID assigned when the 2428 * event was added by the FW. 2429 * @apply_time: When to start the Time Event (in GP2) 2430 * @max_delay: maximum delay to event's start (apply time), in TU 2431 * @depends_on: the unique ID of the event we depend on (if any) 2432 * @interval: interval between repetitions, in TU 2433 * @duration: duration of event in TU 2434 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2435 * @max_frags: maximal number of fragments the Time Event can be divided to 2436 * @policy: defines whether uCode shall notify the host or other uCode modules 2437 * on event and/or fragment start and/or end 2438 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2439 * IWM_TE_EVENT_SOCIOPATHIC 2440 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2441 */ 2442struct iwm_time_event_cmd { 2443 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2444 uint32_t id_and_color; 2445 uint32_t action; 2446 uint32_t id; 2447 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2448 uint32_t apply_time; 2449 uint32_t max_delay; 2450 uint32_t depends_on; 2451 uint32_t interval; 2452 uint32_t duration; 2453 uint8_t repeat; 2454 uint8_t max_frags; 2455 uint16_t policy; 2456} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2457 2458/** 2459 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2460 * @status: bit 0 indicates success, all others specify errors 2461 * @id: the Time Event type 2462 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2463 * @id_and_color: ID and color of the relevant MAC 2464 */ 2465struct iwm_time_event_resp { 2466 uint32_t status; 2467 uint32_t id; 2468 uint32_t unique_id; 2469 uint32_t id_and_color; 2470} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2471 2472/** 2473 * struct iwm_time_event_notif - notifications of time event start/stop 2474 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2475 * @timestamp: action timestamp in GP2 2476 * @session_id: session's unique id 2477 * @unique_id: unique id of the Time Event itself 2478 * @id_and_color: ID and color of the relevant MAC 2479 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2480 * @status: true if scheduled, false otherwise (not executed) 2481 */ 2482struct iwm_time_event_notif { 2483 uint32_t timestamp; 2484 uint32_t session_id; 2485 uint32_t unique_id; 2486 uint32_t id_and_color; 2487 uint32_t action; 2488 uint32_t status; 2489} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2490 2491 2492/* Bindings and Time Quota */ 2493 2494/** 2495 * struct iwm_binding_cmd - configuring bindings 2496 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2497 * @id_and_color: ID and color of the relevant Binding 2498 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2499 * @macs: array of MAC id and colors which belong to the binding 2500 * @phy: PHY id and color which belongs to the binding 2501 */ 2502struct iwm_binding_cmd { 2503 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2504 uint32_t id_and_color; 2505 uint32_t action; 2506 /* IWM_BINDING_DATA_API_S_VER_1 */ 2507 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2508 uint32_t phy; 2509} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2510 2511/* The maximal number of fragments in the FW's schedule session */ 2512#define IWM_MVM_MAX_QUOTA 128 2513 2514/** 2515 * struct iwm_time_quota_data - configuration of time quota per binding 2516 * @id_and_color: ID and color of the relevant Binding 2517 * @quota: absolute time quota in TU. The scheduler will try to divide the 2518 * remainig quota (after Time Events) according to this quota. 2519 * @max_duration: max uninterrupted context duration in TU 2520 */ 2521struct iwm_time_quota_data { 2522 uint32_t id_and_color; 2523 uint32_t quota; 2524 uint32_t max_duration; 2525} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2526 2527/** 2528 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2529 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2530 * @quotas: allocations per binding 2531 */ 2532struct iwm_time_quota_cmd { 2533 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2534} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2535 2536 2537/* PHY context */ 2538 2539/* Supported bands */ 2540#define IWM_PHY_BAND_5 (0) 2541#define IWM_PHY_BAND_24 (1) 2542 2543/* Supported channel width, vary if there is VHT support */ 2544#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2545#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2546#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2547#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2548 2549/* 2550 * Control channel position: 2551 * For legacy set bit means upper channel, otherwise lower. 2552 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2553 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2554 * center_freq 2555 * | 2556 * 40Mhz |_______|_______| 2557 * 80Mhz |_______|_______|_______|_______| 2558 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2559 * code 011 010 001 000 | 100 101 110 111 2560 */ 2561#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2562#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2563#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2564#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2565#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2566#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2567#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2568#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2569 2570/* 2571 * @band: IWM_PHY_BAND_* 2572 * @channel: channel number 2573 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2574 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2575 */ 2576struct iwm_fw_channel_info { 2577 uint8_t band; 2578 uint8_t channel; 2579 uint8_t width; 2580 uint8_t ctrl_pos; 2581} __packed; 2582 2583#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2584#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2585 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2586#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2587#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2588 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2589#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2590#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2591 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2592#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2593#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2594 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2595#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2596#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2597 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2598#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2599#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2600 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2601#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2602#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2603 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2604 2605/* TODO: fix the value, make it depend on firmware at runtime? */ 2606#define IWM_NUM_PHY_CTX 3 2607 2608/* TODO: complete missing documentation */ 2609/** 2610 * struct iwm_phy_context_cmd - config of the PHY context 2611 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2612 * @id_and_color: ID and color of the relevant Binding 2613 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2614 * @apply_time: 0 means immediate apply and context switch. 2615 * other value means apply new params after X usecs 2616 * @tx_param_color: ??? 2617 * @channel_info: 2618 * @txchain_info: ??? 2619 * @rxchain_info: ??? 2620 * @acquisition_data: ??? 2621 * @dsp_cfg_flags: set to 0 2622 */ 2623struct iwm_phy_context_cmd { 2624 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2625 uint32_t id_and_color; 2626 uint32_t action; 2627 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2628 uint32_t apply_time; 2629 uint32_t tx_param_color; 2630 struct iwm_fw_channel_info ci; 2631 uint32_t txchain_info; 2632 uint32_t rxchain_info; 2633 uint32_t acquisition_data; 2634 uint32_t dsp_cfg_flags; 2635} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2636 2637#define IWM_RX_INFO_PHY_CNT 8 2638#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2639#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2640#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2641#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2642#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2643#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2644#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2645 2646#define IWM_RX_INFO_AGC_IDX 1 2647#define IWM_RX_INFO_RSSI_AB_IDX 2 2648#define IWM_OFDM_AGC_A_MSK 0x0000007f 2649#define IWM_OFDM_AGC_A_POS 0 2650#define IWM_OFDM_AGC_B_MSK 0x00003f80 2651#define IWM_OFDM_AGC_B_POS 7 2652#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2653#define IWM_OFDM_AGC_CODE_POS 20 2654#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2655#define IWM_OFDM_RSSI_A_POS 0 2656#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2657#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2658#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2659#define IWM_OFDM_RSSI_B_POS 16 2660#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2661#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2662 2663/** 2664 * struct iwm_rx_phy_info - phy info 2665 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2666 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2667 * @cfg_phy_cnt: configurable DSP phy data byte count 2668 * @stat_id: configurable DSP phy data set ID 2669 * @reserved1: 2670 * @system_timestamp: GP2 at on air rise 2671 * @timestamp: TSF at on air rise 2672 * @beacon_time_stamp: beacon at on-air rise 2673 * @phy_flags: general phy flags: band, modulation, ... 2674 * @channel: channel number 2675 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2676 * @rate_n_flags: IWM_RATE_MCS_* 2677 * @byte_count: frame's byte-count 2678 * @frame_time: frame's time on the air, based on byte count and frame rate 2679 * calculation 2680 * @mac_active_msk: what MACs were active when the frame was received 2681 * 2682 * Before each Rx, the device sends this data. It contains PHY information 2683 * about the reception of the packet. 2684 */ 2685struct iwm_rx_phy_info { 2686 uint8_t non_cfg_phy_cnt; 2687 uint8_t cfg_phy_cnt; 2688 uint8_t stat_id; 2689 uint8_t reserved1; 2690 uint32_t system_timestamp; 2691 uint64_t timestamp; 2692 uint32_t beacon_time_stamp; 2693 uint16_t phy_flags; 2694#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2695 uint16_t channel; 2696 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2697 uint8_t rate; 2698 uint8_t rflags; 2699 uint16_t xrflags; 2700 uint32_t byte_count; 2701 uint16_t mac_active_msk; 2702 uint16_t frame_time; 2703} __packed; 2704 2705struct iwm_rx_mpdu_res_start { 2706 uint16_t byte_count; 2707 uint16_t reserved; 2708} __packed; 2709 2710/** 2711 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2712 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2713 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2714 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2715 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2716 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2717 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2718 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2719 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2720 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2721 */ 2722enum iwm_rx_phy_flags { 2723 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2724 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2725 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2726 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2727 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2728 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2729 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2730 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2731 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2732 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2733}; 2734 2735/** 2736 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2737 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2738 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2739 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2740 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2741 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2742 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2743 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2744 * in the driver. 2745 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2746 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2747 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2748 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2749 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2750 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2751 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2752 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2753 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2754 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2755 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2756 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2757 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2758 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2759 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2760 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2761 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2762 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2763 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2764 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2765 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2766 */ 2767enum iwm_mvm_rx_status { 2768 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2769 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2770 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2771 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2772 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2773 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2774 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2775 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2776 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2777 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2778 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2779 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2780 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2781 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2782 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2783 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2784 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2785 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2786 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2787 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2788 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2789 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2790 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2791 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2792 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2793 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2794 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2795}; 2796 2797/** 2798 * struct iwm_radio_version_notif - information on the radio version 2799 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2800 * @radio_flavor: 2801 * @radio_step: 2802 * @radio_dash: 2803 */ 2804struct iwm_radio_version_notif { 2805 uint32_t radio_flavor; 2806 uint32_t radio_step; 2807 uint32_t radio_dash; 2808} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2809 2810enum iwm_card_state_flags { 2811 IWM_CARD_ENABLED = 0x00, 2812 IWM_HW_CARD_DISABLED = 0x01, 2813 IWM_SW_CARD_DISABLED = 0x02, 2814 IWM_CT_KILL_CARD_DISABLED = 0x04, 2815 IWM_HALT_CARD_DISABLED = 0x08, 2816 IWM_CARD_DISABLED_MSK = 0x0f, 2817 IWM_CARD_IS_RX_ON = 0x10, 2818}; 2819 2820/** 2821 * struct iwm_radio_version_notif - information on the radio version 2822 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2823 * @flags: %iwm_card_state_flags 2824 */ 2825struct iwm_card_state_notif { 2826 uint32_t flags; 2827} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2828 2829/** 2830 * struct iwm_missed_beacons_notif - information on missed beacons 2831 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2832 * @mac_id: interface ID 2833 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2834 * beacons since last RX. 2835 * @consec_missed_beacons: number of consecutive missed beacons 2836 * @num_expected_beacons: 2837 * @num_recvd_beacons: 2838 */ 2839struct iwm_missed_beacons_notif { 2840 uint32_t mac_id; 2841 uint32_t consec_missed_beacons_since_last_rx; 2842 uint32_t consec_missed_beacons; 2843 uint32_t num_expected_beacons; 2844 uint32_t num_recvd_beacons; 2845} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2846 2847/** 2848 * struct iwm_mfuart_load_notif - mfuart image version & status 2849 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2850 * @installed_ver: installed image version 2851 * @external_ver: external image version 2852 * @status: MFUART loading status 2853 * @duration: MFUART loading time 2854*/ 2855struct iwm_mfuart_load_notif { 2856 uint32_t installed_ver; 2857 uint32_t external_ver; 2858 uint32_t status; 2859 uint32_t duration; 2860} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2861 2862/** 2863 * struct iwm_set_calib_default_cmd - set default value for calibration. 2864 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2865 * @calib_index: the calibration to set value for 2866 * @length: of data 2867 * @data: the value to set for the calibration result 2868 */ 2869struct iwm_set_calib_default_cmd { 2870 uint16_t calib_index; 2871 uint16_t length; 2872 uint8_t data[0]; 2873} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2874 2875#define IWM_MAX_PORT_ID_NUM 2 2876#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2877 2878/** 2879 * struct iwm_mcast_filter_cmd - configure multicast filter. 2880 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2881 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2882 * to identify network interface adopted in host-device IF. 2883 * It is used by FW as index in array of addresses. This array has 2884 * IWM_MAX_PORT_ID_NUM members. 2885 * @count: Number of MAC addresses in the array 2886 * @pass_all: Set 1 to pass all multicast packets. 2887 * @bssid: current association BSSID. 2888 * @addr_list: Place holder for array of MAC addresses. 2889 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2890 */ 2891struct iwm_mcast_filter_cmd { 2892 uint8_t filter_own; 2893 uint8_t port_id; 2894 uint8_t count; 2895 uint8_t pass_all; 2896 uint8_t bssid[6]; 2897 uint8_t reserved[2]; 2898 uint8_t addr_list[0]; 2899} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2900 2901/* 2902 * The first MAC indices (starting from 0) 2903 * are available to the driver, AUX follows 2904 */ 2905#define IWM_MAC_INDEX_AUX 4 2906#define IWM_MAC_INDEX_MIN_DRIVER 0 2907#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2908#define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1) 2909 2910/*********************************** 2911 * Statistics API 2912 ***********************************/ 2913struct iwm_mvm_statistics_dbg { 2914 uint32_t burst_check; 2915 uint32_t burst_count; 2916 uint32_t wait_for_silence_timeout_cnt; 2917 uint32_t reserved[3]; 2918} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2919 2920struct iwm_mvm_statistics_div { 2921 uint32_t tx_on_a; 2922 uint32_t tx_on_b; 2923 uint32_t exec_time; 2924 uint32_t probe_time; 2925 uint32_t rssi_ant; 2926 uint32_t reserved2; 2927} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2928 2929struct iwm_mvm_statistics_rx_non_phy { 2930 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2931 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2932 uint32_t non_bssid_frames; /* number of frames with BSSID that 2933 * doesn't belong to the STA BSSID */ 2934 uint32_t filtered_frames; /* count frames that were dumped in the 2935 * filtering process */ 2936 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2937 * our serving channel */ 2938 uint32_t channel_beacons; /* beacons with our bss id and in our 2939 * serving channel */ 2940 uint32_t num_missed_bcon; /* number of missed beacons */ 2941 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2942 * ADC was in saturation */ 2943 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2944 * for INA */ 2945 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2946 uint32_t interference_data_flag; /* flag for interference data 2947 * availability. 1 when data is 2948 * available. */ 2949 uint32_t channel_load; /* counts RX Enable time in uSec */ 2950 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2951 * and CCK) counter */ 2952 uint32_t beacon_rssi_a; 2953 uint32_t beacon_rssi_b; 2954 uint32_t beacon_rssi_c; 2955 uint32_t beacon_energy_a; 2956 uint32_t beacon_energy_b; 2957 uint32_t beacon_energy_c; 2958 uint32_t num_bt_kills; 2959 uint32_t mac_id; 2960 uint32_t directed_data_mpdu; 2961} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2962 2963struct iwm_mvm_statistics_rx_phy { 2964 uint32_t ina_cnt; 2965 uint32_t fina_cnt; 2966 uint32_t plcp_err; 2967 uint32_t crc32_err; 2968 uint32_t overrun_err; 2969 uint32_t early_overrun_err; 2970 uint32_t crc32_good; 2971 uint32_t false_alarm_cnt; 2972 uint32_t fina_sync_err_cnt; 2973 uint32_t sfd_timeout; 2974 uint32_t fina_timeout; 2975 uint32_t unresponded_rts; 2976 uint32_t rxe_frame_limit_overrun; 2977 uint32_t sent_ack_cnt; 2978 uint32_t sent_cts_cnt; 2979 uint32_t sent_ba_rsp_cnt; 2980 uint32_t dsp_self_kill; 2981 uint32_t mh_format_err; 2982 uint32_t re_acq_main_rssi_sum; 2983 uint32_t reserved; 2984} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2985 2986struct iwm_mvm_statistics_rx_ht_phy { 2987 uint32_t plcp_err; 2988 uint32_t overrun_err; 2989 uint32_t early_overrun_err; 2990 uint32_t crc32_good; 2991 uint32_t crc32_err; 2992 uint32_t mh_format_err; 2993 uint32_t agg_crc32_good; 2994 uint32_t agg_mpdu_cnt; 2995 uint32_t agg_cnt; 2996 uint32_t unsupport_mcs; 2997} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 2998 2999struct iwm_mvm_statistics_tx_non_phy { 3000 uint32_t preamble_cnt; 3001 uint32_t rx_detected_cnt; 3002 uint32_t bt_prio_defer_cnt; 3003 uint32_t bt_prio_kill_cnt; 3004 uint32_t few_bytes_cnt; 3005 uint32_t cts_timeout; 3006 uint32_t ack_timeout; 3007 uint32_t expected_ack_cnt; 3008 uint32_t actual_ack_cnt; 3009 uint32_t dump_msdu_cnt; 3010 uint32_t burst_abort_next_frame_mismatch_cnt; 3011 uint32_t burst_abort_missing_next_frame_cnt; 3012 uint32_t cts_timeout_collision; 3013 uint32_t ack_or_ba_timeout_collision; 3014} __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */ 3015 3016#define IWM_MAX_CHAINS 3 3017 3018struct iwm_mvm_statistics_tx_non_phy_agg { 3019 uint32_t ba_timeout; 3020 uint32_t ba_reschedule_frames; 3021 uint32_t scd_query_agg_frame_cnt; 3022 uint32_t scd_query_no_agg; 3023 uint32_t scd_query_agg; 3024 uint32_t scd_query_mismatch; 3025 uint32_t frame_not_ready; 3026 uint32_t underrun; 3027 uint32_t bt_prio_kill; 3028 uint32_t rx_ba_rsp_cnt; 3029 int8_t txpower[IWM_MAX_CHAINS]; 3030 int8_t reserved; 3031 uint32_t reserved2; 3032} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3033 3034struct iwm_mvm_statistics_tx_channel_width { 3035 uint32_t ext_cca_narrow_ch20[1]; 3036 uint32_t ext_cca_narrow_ch40[2]; 3037 uint32_t ext_cca_narrow_ch80[3]; 3038 uint32_t ext_cca_narrow_ch160[4]; 3039 uint32_t last_tx_ch_width_indx; 3040 uint32_t rx_detected_per_ch_width[4]; 3041 uint32_t success_per_ch_width[4]; 3042 uint32_t fail_per_ch_width[4]; 3043}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3044 3045struct iwm_mvm_statistics_tx { 3046 struct iwm_mvm_statistics_tx_non_phy general; 3047 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3048 struct iwm_mvm_statistics_tx_channel_width channel_width; 3049} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3050 3051 3052struct iwm_mvm_statistics_bt_activity { 3053 uint32_t hi_priority_tx_req_cnt; 3054 uint32_t hi_priority_tx_denied_cnt; 3055 uint32_t lo_priority_tx_req_cnt; 3056 uint32_t lo_priority_tx_denied_cnt; 3057 uint32_t hi_priority_rx_req_cnt; 3058 uint32_t hi_priority_rx_denied_cnt; 3059 uint32_t lo_priority_rx_req_cnt; 3060 uint32_t lo_priority_rx_denied_cnt; 3061} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3062 3063struct iwm_mvm_statistics_general_v8 { 3064 uint32_t radio_temperature; 3065 uint32_t radio_voltage; 3066 struct iwm_mvm_statistics_dbg dbg; 3067 uint32_t sleep_time; 3068 uint32_t slots_out; 3069 uint32_t slots_idle; 3070 uint32_t ttl_timestamp; 3071 struct iwm_mvm_statistics_div slow_div; 3072 uint32_t rx_enable_counter; 3073 /* 3074 * num_of_sos_states: 3075 * count the number of times we have to re-tune 3076 * in order to get out of bad PHY status 3077 */ 3078 uint32_t num_of_sos_states; 3079 uint32_t beacon_filtered; 3080 uint32_t missed_beacons; 3081 uint8_t beacon_filter_average_energy; 3082 uint8_t beacon_filter_reason; 3083 uint8_t beacon_filter_current_energy; 3084 uint8_t beacon_filter_reserved; 3085 uint32_t beacon_filter_delta_time; 3086 struct iwm_mvm_statistics_bt_activity bt_activity; 3087 uint64_t rx_time; 3088 uint64_t on_time_rf; 3089 uint64_t on_time_scan; 3090 uint64_t tx_time; 3091 uint32_t beacon_counter[IWM_NUM_MAC_INDEX]; 3092 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX]; 3093 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)]; 3094} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */ 3095 3096struct iwm_mvm_statistics_rx { 3097 struct iwm_mvm_statistics_rx_phy ofdm; 3098 struct iwm_mvm_statistics_rx_phy cck; 3099 struct iwm_mvm_statistics_rx_non_phy general; 3100 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3101} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3102 3103/* 3104 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3105 * 3106 * By default, uCode issues this notification after receiving a beacon 3107 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3108 * IWM_STATISTICS_CMD (0x9c), below. 3109 */ 3110 3111struct iwm_notif_statistics_v10 { 3112 uint32_t flag; 3113 struct iwm_mvm_statistics_rx rx; 3114 struct iwm_mvm_statistics_tx tx; 3115 struct iwm_mvm_statistics_general_v8 general; 3116} __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */ 3117 3118#define IWM_STATISTICS_FLG_CLEAR 0x1 3119#define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2 3120 3121struct iwm_statistics_cmd { 3122 uint32_t flags; 3123} __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */ 3124 3125/*********************************** 3126 * Smart Fifo API 3127 ***********************************/ 3128/* Smart Fifo state */ 3129enum iwm_sf_state { 3130 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3131 IWM_SF_FULL_ON, 3132 IWM_SF_UNINIT, 3133 IWM_SF_INIT_OFF, 3134 IWM_SF_HW_NUM_STATES 3135}; 3136 3137/* Smart Fifo possible scenario */ 3138enum iwm_sf_scenario { 3139 IWM_SF_SCENARIO_SINGLE_UNICAST, 3140 IWM_SF_SCENARIO_AGG_UNICAST, 3141 IWM_SF_SCENARIO_MULTICAST, 3142 IWM_SF_SCENARIO_BA_RESP, 3143 IWM_SF_SCENARIO_TX_RESP, 3144 IWM_SF_NUM_SCENARIO 3145}; 3146 3147#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3148#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3149 3150/* smart FIFO default values */ 3151#define IWM_SF_W_MARK_SISO 4096 3152#define IWM_SF_W_MARK_MIMO2 8192 3153#define IWM_SF_W_MARK_MIMO3 6144 3154#define IWM_SF_W_MARK_LEGACY 4096 3155#define IWM_SF_W_MARK_SCAN 4096 3156 3157/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3158#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3159#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3160#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3161#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3162#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3163#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3164#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3165#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3166#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3167#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3168 3169/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3170#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3171#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3172#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3173#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3174#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3175#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3176#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3177#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3178#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3179#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3180 3181#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3182 3183#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3184 3185/** 3186 * Smart Fifo configuration command. 3187 * @state: smart fifo state, types listed in iwm_sf_state. 3188 * @watermark: Minimum allowed available free space in RXF for transient state. 3189 * @long_delay_timeouts: aging and idle timer values for each scenario 3190 * in long delay state. 3191 * @full_on_timeouts: timer values for each scenario in full on state. 3192 */ 3193struct iwm_sf_cfg_cmd { 3194 uint32_t state; 3195 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3196 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3197 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3198} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3199 3200/* 3201 * END mvm/fw-api.h 3202 */ 3203 3204/* 3205 * BEGIN mvm/fw-api-mac.h 3206 */ 3207 3208enum iwm_ac { 3209 IWM_AC_BK, 3210 IWM_AC_BE, 3211 IWM_AC_VI, 3212 IWM_AC_VO, 3213 IWM_AC_NUM, 3214}; 3215 3216/** 3217 * enum iwm_mac_protection_flags - MAC context flags 3218 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3219 * this will require CCK RTS/CTS2self. 3220 * RTS/CTS will protect full burst time. 3221 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3222 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3223 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3224 */ 3225enum iwm_mac_protection_flags { 3226 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3227 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3228 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3229 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3230}; 3231 3232#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3233#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3234 3235/** 3236 * enum iwm_mac_types - Supported MAC types 3237 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3238 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3239 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3240 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3241 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3242 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3243 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3244 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3245 * @IWM_FW_MAC_TYPE_GO: P2P GO 3246 * @IWM_FW_MAC_TYPE_TEST: ? 3247 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3248 */ 3249enum iwm_mac_types { 3250 IWM_FW_MAC_TYPE_FIRST = 1, 3251 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3252 IWM_FW_MAC_TYPE_LISTENER, 3253 IWM_FW_MAC_TYPE_PIBSS, 3254 IWM_FW_MAC_TYPE_IBSS, 3255 IWM_FW_MAC_TYPE_BSS_STA, 3256 IWM_FW_MAC_TYPE_P2P_DEVICE, 3257 IWM_FW_MAC_TYPE_P2P_STA, 3258 IWM_FW_MAC_TYPE_GO, 3259 IWM_FW_MAC_TYPE_TEST, 3260 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3261}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3262 3263/** 3264 * enum iwm_tsf_id - TSF hw timer ID 3265 * @IWM_TSF_ID_A: use TSF A 3266 * @IWM_TSF_ID_B: use TSF B 3267 * @IWM_TSF_ID_C: use TSF C 3268 * @IWM_TSF_ID_D: use TSF D 3269 * @IWM_NUM_TSF_IDS: number of TSF timers available 3270 */ 3271enum iwm_tsf_id { 3272 IWM_TSF_ID_A = 0, 3273 IWM_TSF_ID_B = 1, 3274 IWM_TSF_ID_C = 2, 3275 IWM_TSF_ID_D = 3, 3276 IWM_NUM_TSF_IDS = 4, 3277}; /* IWM_TSF_ID_API_E_VER_1 */ 3278 3279/** 3280 * struct iwm_mac_data_ap - configuration data for AP MAC context 3281 * @beacon_time: beacon transmit time in system time 3282 * @beacon_tsf: beacon transmit time in TSF 3283 * @bi: beacon interval in TU 3284 * @bi_reciprocal: 2^32 / bi 3285 * @dtim_interval: dtim transmit time in TU 3286 * @dtim_reciprocal: 2^32 / dtim_interval 3287 * @mcast_qid: queue ID for multicast traffic 3288 * @beacon_template: beacon template ID 3289 */ 3290struct iwm_mac_data_ap { 3291 uint32_t beacon_time; 3292 uint64_t beacon_tsf; 3293 uint32_t bi; 3294 uint32_t bi_reciprocal; 3295 uint32_t dtim_interval; 3296 uint32_t dtim_reciprocal; 3297 uint32_t mcast_qid; 3298 uint32_t beacon_template; 3299} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3300 3301/** 3302 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3303 * @beacon_time: beacon transmit time in system time 3304 * @beacon_tsf: beacon transmit time in TSF 3305 * @bi: beacon interval in TU 3306 * @bi_reciprocal: 2^32 / bi 3307 * @beacon_template: beacon template ID 3308 */ 3309struct iwm_mac_data_ibss { 3310 uint32_t beacon_time; 3311 uint64_t beacon_tsf; 3312 uint32_t bi; 3313 uint32_t bi_reciprocal; 3314 uint32_t beacon_template; 3315} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3316 3317/** 3318 * struct iwm_mac_data_sta - configuration data for station MAC context 3319 * @is_assoc: 1 for associated state, 0 otherwise 3320 * @dtim_time: DTIM arrival time in system time 3321 * @dtim_tsf: DTIM arrival time in TSF 3322 * @bi: beacon interval in TU, applicable only when associated 3323 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3324 * @dtim_interval: DTIM interval in TU, applicable only when associated 3325 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3326 * @listen_interval: in beacon intervals, applicable only when associated 3327 * @assoc_id: unique ID assigned by the AP during association 3328 */ 3329struct iwm_mac_data_sta { 3330 uint32_t is_assoc; 3331 uint32_t dtim_time; 3332 uint64_t dtim_tsf; 3333 uint32_t bi; 3334 uint32_t bi_reciprocal; 3335 uint32_t dtim_interval; 3336 uint32_t dtim_reciprocal; 3337 uint32_t listen_interval; 3338 uint32_t assoc_id; 3339 uint32_t assoc_beacon_arrive_time; 3340} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3341 3342/** 3343 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3344 * @ap: iwm_mac_data_ap struct with most config data 3345 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3346 * 0 indicates that there is no CT window. 3347 * @opp_ps_enabled: indicate that opportunistic PS allowed 3348 */ 3349struct iwm_mac_data_go { 3350 struct iwm_mac_data_ap ap; 3351 uint32_t ctwin; 3352 uint32_t opp_ps_enabled; 3353} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3354 3355/** 3356 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3357 * @sta: iwm_mac_data_sta struct with most config data 3358 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3359 * 0 indicates that there is no CT window. 3360 */ 3361struct iwm_mac_data_p2p_sta { 3362 struct iwm_mac_data_sta sta; 3363 uint32_t ctwin; 3364} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3365 3366/** 3367 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3368 * @stats_interval: interval in TU between statistics notifications to host. 3369 */ 3370struct iwm_mac_data_pibss { 3371 uint32_t stats_interval; 3372} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3373 3374/* 3375 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3376 * context. 3377 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3378 * other channels as well. This should be to true only in case that the 3379 * device is discoverable and there is an active GO. Note that setting this 3380 * field when not needed, will increase the number of interrupts and have 3381 * effect on the platform power, as this setting opens the Rx filters on 3382 * all macs. 3383 */ 3384struct iwm_mac_data_p2p_dev { 3385 uint32_t is_disc_extended; 3386} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3387 3388/** 3389 * enum iwm_mac_filter_flags - MAC context filter flags 3390 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3391 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3392 * control frames to the host 3393 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3394 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3395 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3396 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3397 * (in station mode when associated) 3398 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3399 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3400 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3401 */ 3402enum iwm_mac_filter_flags { 3403 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3404 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3405 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3406 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3407 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3408 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3409 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3410 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3411 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3412}; 3413 3414/** 3415 * enum iwm_mac_qos_flags - QoS flags 3416 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3417 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3418 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3419 * 3420 */ 3421enum iwm_mac_qos_flags { 3422 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3423 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3424 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3425}; 3426 3427/** 3428 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3429 * @cw_min: Contention window, start value in numbers of slots. 3430 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3431 * @cw_max: Contention window, max value in numbers of slots. 3432 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3433 * @aifsn: Number of slots in Arbitration Interframe Space (before 3434 * performing random backoff timing prior to Tx). Device default 1. 3435 * @fifos_mask: FIFOs used by this MAC for this AC 3436 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3437 * 3438 * One instance of this config struct for each of 4 EDCA access categories 3439 * in struct iwm_qosparam_cmd. 3440 * 3441 * Device will automatically increase contention window by (2*CW) + 1 for each 3442 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3443 * value, to cap the CW value. 3444 */ 3445struct iwm_ac_qos { 3446 uint16_t cw_min; 3447 uint16_t cw_max; 3448 uint8_t aifsn; 3449 uint8_t fifos_mask; 3450 uint16_t edca_txop; 3451} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3452 3453/** 3454 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3455 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3456 * @id_and_color: ID and color of the MAC 3457 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3458 * @mac_type: one of IWM_FW_MAC_TYPE_* 3459 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3460 * @node_addr: MAC address 3461 * @bssid_addr: BSSID 3462 * @cck_rates: basic rates available for CCK 3463 * @ofdm_rates: basic rates available for OFDM 3464 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3465 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3466 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3467 * @filter_flags: combination of IWM_MAC_FILTER_* 3468 * @qos_flags: from IWM_MAC_QOS_FLG_* 3469 * @ac: one iwm_mac_qos configuration for each AC 3470 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3471 */ 3472struct iwm_mac_ctx_cmd { 3473 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3474 uint32_t id_and_color; 3475 uint32_t action; 3476 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3477 uint32_t mac_type; 3478 uint32_t tsf_id; 3479 uint8_t node_addr[6]; 3480 uint16_t reserved_for_node_addr; 3481 uint8_t bssid_addr[6]; 3482 uint16_t reserved_for_bssid_addr; 3483 uint32_t cck_rates; 3484 uint32_t ofdm_rates; 3485 uint32_t protection_flags; 3486 uint32_t cck_short_preamble; 3487 uint32_t short_slot; 3488 uint32_t filter_flags; 3489 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3490 uint32_t qos_flags; 3491 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3492 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3493 union { 3494 struct iwm_mac_data_ap ap; 3495 struct iwm_mac_data_go go; 3496 struct iwm_mac_data_sta sta; 3497 struct iwm_mac_data_p2p_sta p2p_sta; 3498 struct iwm_mac_data_p2p_dev p2p_dev; 3499 struct iwm_mac_data_pibss pibss; 3500 struct iwm_mac_data_ibss ibss; 3501 }; 3502} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3503 3504static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3505{ 3506 if (!v) 3507 return 0; 3508 return 0xFFFFFFFF / v; 3509} 3510 3511#define IWM_NONQOS_SEQ_GET 0x1 3512#define IWM_NONQOS_SEQ_SET 0x2 3513struct iwm_nonqos_seq_query_cmd { 3514 uint32_t get_set_flag; 3515 uint32_t mac_id_n_color; 3516 uint16_t value; 3517 uint16_t reserved; 3518} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3519 3520/* 3521 * END mvm/fw-api-mac.h 3522 */ 3523 3524/* 3525 * BEGIN mvm/fw-api-power.h 3526 */ 3527 3528/* Power Management Commands, Responses, Notifications */ 3529 3530/* Radio LP RX Energy Threshold measured in dBm */ 3531#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3532#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3533#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3534 3535/** 3536 * enum iwm_scan_flags - masks for power table command flags 3537 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3538 * receiver and transmitter. '0' - does not allow. 3539 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3540 * '1' Driver enables PM (use rest of parameters) 3541 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3542 * '1' PM could sleep over DTIM till listen Interval. 3543 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3544 * access categories are both delivery and trigger enabled. 3545 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3546 * PBW Snoozing enabled 3547 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3548 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3549 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3550 * detection enablement 3551*/ 3552enum iwm_power_flags { 3553 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3554 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3555 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3556 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3557 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3558 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3559 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3560 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3561}; 3562 3563#define IWM_POWER_VEC_SIZE 5 3564 3565/** 3566 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3567 * is used also with a new power API for device wide power settings. 3568 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3569 * 3570 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3571 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3572 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3573 * set regardless of power scheme or current power state. 3574 * FW use this value also when PM is disabled. 3575 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3576 * PSM transition - legacy PM 3577 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3578 * PSM transition - legacy PM 3579 * @sleep_interval: not in use 3580 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3581 * is set. For example, if it is required to skip over 3582 * one DTIM, this value need to be set to 2 (DTIM periods). 3583 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3584 * Default: 80dbm 3585 */ 3586struct iwm_powertable_cmd { 3587 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3588 uint16_t flags; 3589 uint8_t keep_alive_seconds; 3590 uint8_t debug_flags; 3591 uint32_t rx_data_timeout; 3592 uint32_t tx_data_timeout; 3593 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3594 uint32_t skip_dtim_periods; 3595 uint32_t lprx_rssi_threshold; 3596} __packed; 3597 3598/** 3599 * enum iwm_device_power_flags - masks for device power command flags 3600 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3601 * receiver and transmitter. '0' - does not allow. 3602 */ 3603enum iwm_device_power_flags { 3604 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3605}; 3606 3607/** 3608 * struct iwm_device_power_cmd - device wide power command. 3609 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3610 * 3611 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3612 */ 3613struct iwm_device_power_cmd { 3614 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3615 uint16_t flags; 3616 uint16_t reserved; 3617} __packed; 3618 3619/** 3620 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3621 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3622 * @id_and_color: MAC contex identifier 3623 * @flags: Power table command flags from POWER_FLAGS_* 3624 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3625 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3626 * set regardless of power scheme or current power state. 3627 * FW use this value also when PM is disabled. 3628 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3629 * PSM transition - legacy PM 3630 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3631 * PSM transition - legacy PM 3632 * @sleep_interval: not in use 3633 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3634 * is set. For example, if it is required to skip over 3635 * one DTIM, this value need to be set to 2 (DTIM periods). 3636 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3637 * PSM transition - uAPSD 3638 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3639 * PSM transition - uAPSD 3640 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3641 * Default: 80dbm 3642 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3643 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3644 * from the AP [msec] 3645 * @snooze_window: A window of time in which PBW snoozing insures that all 3646 * packets received. It is also the minimum time from last 3647 * received unicast RX packet, before client stops snoozing 3648 * for data. [msec] 3649 * @snooze_step: TBD 3650 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3651 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3652 * each corresponding AC. 3653 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3654 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3655 * values. 3656 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3657 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3658 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3659 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3660 * @limited_ps_threshold: 3661*/ 3662struct iwm_mac_power_cmd { 3663 /* CONTEXT_DESC_API_T_VER_1 */ 3664 uint32_t id_and_color; 3665 3666 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3667 uint16_t flags; 3668 uint16_t keep_alive_seconds; 3669 uint32_t rx_data_timeout; 3670 uint32_t tx_data_timeout; 3671 uint32_t rx_data_timeout_uapsd; 3672 uint32_t tx_data_timeout_uapsd; 3673 uint8_t lprx_rssi_threshold; 3674 uint8_t skip_dtim_periods; 3675 uint16_t snooze_interval; 3676 uint16_t snooze_window; 3677 uint8_t snooze_step; 3678 uint8_t qndp_tid; 3679 uint8_t uapsd_ac_flags; 3680 uint8_t uapsd_max_sp; 3681 uint8_t heavy_tx_thld_packets; 3682 uint8_t heavy_rx_thld_packets; 3683 uint8_t heavy_tx_thld_percentage; 3684 uint8_t heavy_rx_thld_percentage; 3685 uint8_t limited_ps_threshold; 3686 uint8_t reserved; 3687} __packed; 3688 3689/* 3690 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3691 * associated AP is identified as improperly implementing uAPSD protocol. 3692 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3693 * @sta_id: index of station in uCode's station table - associated AP ID in 3694 * this context. 3695 */ 3696struct iwm_uapsd_misbehaving_ap_notif { 3697 uint32_t sta_id; 3698 uint8_t mac_id; 3699 uint8_t reserved[3]; 3700} __packed; 3701 3702/** 3703 * struct iwm_beacon_filter_cmd 3704 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3705 * @id_and_color: MAC contex identifier 3706 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3707 * to driver if delta in Energy values calculated for this and last 3708 * passed beacon is greater than this threshold. Zero value means that 3709 * the Energy change is ignored for beacon filtering, and beacon will 3710 * not be forced to be sent to driver regardless of this delta. Typical 3711 * energy delta 5dB. 3712 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3713 * Send beacon to driver if delta in Energy values calculated for this 3714 * and last passed beacon is greater than this threshold. Zero value 3715 * means that the Energy change is ignored for beacon filtering while in 3716 * Roaming state, typical energy delta 1dB. 3717 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3718 * calculated for current beacon is less than the threshold, use 3719 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3720 * Threshold. Typical energy threshold is -72dBm. 3721 * @bf_temp_threshold: This threshold determines the type of temperature 3722 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3723 * If the current temperature is above this threshold - Fast filter 3724 * will be used, If the current temperature is below this threshold - 3725 * Slow filter will be used. 3726 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3727 * calculated for this and the last passed beacon is greater than this 3728 * threshold. Zero value means that the temperature change is ignored for 3729 * beacon filtering; beacons will not be forced to be sent to driver 3730 * regardless of whether its temperature has been changed. 3731 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3732 * calculated for this and the last passed beacon is greater than this 3733 * threshold. Zero value means that the temperature change is ignored for 3734 * beacon filtering; beacons will not be forced to be sent to driver 3735 * regardless of whether its temperature has been changed. 3736 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3737 * @bf_filter_escape_timer: Send beacons to the driver if no beacons were passed 3738 * for a specific period of time. Units: Beacons. 3739 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3740 * for a longer period of time then this escape-timeout. Units: Beacons. 3741 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3742 */ 3743struct iwm_beacon_filter_cmd { 3744 uint32_t bf_energy_delta; 3745 uint32_t bf_roaming_energy_delta; 3746 uint32_t bf_roaming_state; 3747 uint32_t bf_temp_threshold; 3748 uint32_t bf_temp_fast_filter; 3749 uint32_t bf_temp_slow_filter; 3750 uint32_t bf_enable_beacon_filter; 3751 uint32_t bf_debug_flag; 3752 uint32_t bf_escape_timer; 3753 uint32_t ba_escape_timer; 3754 uint32_t ba_enable_beacon_abort; 3755} __packed; 3756 3757/* Beacon filtering and beacon abort */ 3758#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3759#define IWM_BF_ENERGY_DELTA_MAX 255 3760#define IWM_BF_ENERGY_DELTA_MIN 0 3761 3762#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3763#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3764#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3765 3766#define IWM_BF_ROAMING_STATE_DEFAULT 72 3767#define IWM_BF_ROAMING_STATE_MAX 255 3768#define IWM_BF_ROAMING_STATE_MIN 0 3769 3770#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3771#define IWM_BF_TEMP_THRESHOLD_MAX 255 3772#define IWM_BF_TEMP_THRESHOLD_MIN 0 3773 3774#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3775#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3776#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3777 3778#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3779#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3780#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3781 3782#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3783 3784#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3785 3786#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3787#define IWM_BF_ESCAPE_TIMER_MAX 1024 3788#define IWM_BF_ESCAPE_TIMER_MIN 0 3789 3790#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3791#define IWM_BA_ESCAPE_TIMER_D3 9 3792#define IWM_BA_ESCAPE_TIMER_MAX 1024 3793#define IWM_BA_ESCAPE_TIMER_MIN 0 3794 3795#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3796 3797#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3798 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3799 .bf_roaming_energy_delta = \ 3800 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3801 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3802 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3803 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3804 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3805 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3806 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3807 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3808 3809/* 3810 * END mvm/fw-api-power.h 3811 */ 3812 3813/* 3814 * BEGIN mvm/fw-api-rs.h 3815 */ 3816 3817/* 3818 * These serve as indexes into 3819 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3820 * TODO: avoid overlap between legacy and HT rates 3821 */ 3822enum { 3823 IWM_RATE_1M_INDEX = 0, 3824 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3825 IWM_RATE_2M_INDEX, 3826 IWM_RATE_5M_INDEX, 3827 IWM_RATE_11M_INDEX, 3828 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3829 IWM_RATE_6M_INDEX, 3830 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3831 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3832 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3833 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3834 IWM_RATE_9M_INDEX, 3835 IWM_RATE_12M_INDEX, 3836 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3837 IWM_RATE_18M_INDEX, 3838 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3839 IWM_RATE_24M_INDEX, 3840 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3841 IWM_RATE_36M_INDEX, 3842 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3843 IWM_RATE_48M_INDEX, 3844 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3845 IWM_RATE_54M_INDEX, 3846 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3847 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3848 IWM_RATE_60M_INDEX, 3849 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3850 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3851 IWM_RATE_MCS_8_INDEX, 3852 IWM_RATE_MCS_9_INDEX, 3853 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3854 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3855 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3856}; 3857 3858#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3859 3860/* fw API values for legacy bit rates, both OFDM and CCK */ 3861enum { 3862 IWM_RATE_6M_PLCP = 13, 3863 IWM_RATE_9M_PLCP = 15, 3864 IWM_RATE_12M_PLCP = 5, 3865 IWM_RATE_18M_PLCP = 7, 3866 IWM_RATE_24M_PLCP = 9, 3867 IWM_RATE_36M_PLCP = 11, 3868 IWM_RATE_48M_PLCP = 1, 3869 IWM_RATE_54M_PLCP = 3, 3870 IWM_RATE_1M_PLCP = 10, 3871 IWM_RATE_2M_PLCP = 20, 3872 IWM_RATE_5M_PLCP = 55, 3873 IWM_RATE_11M_PLCP = 110, 3874 IWM_RATE_INVM_PLCP = -1, 3875}; 3876 3877/* 3878 * rate_n_flags bit fields 3879 * 3880 * The 32-bit value has different layouts in the low 8 bites depending on the 3881 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3882 * for CCK and OFDM). 3883 * 3884 * High-throughput (HT) rate format 3885 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3886 * Very High-throughput (VHT) rate format 3887 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3888 * Legacy OFDM rate format for bits 7:0 3889 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3890 * Legacy CCK rate format for bits 7:0: 3891 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3892 */ 3893 3894/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3895#define IWM_RATE_MCS_HT_POS 8 3896#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3897 3898/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3899#define IWM_RATE_MCS_CCK_POS 9 3900#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3901 3902/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3903#define IWM_RATE_MCS_VHT_POS 26 3904#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3905 3906 3907/* 3908 * High-throughput (HT) rate format for bits 7:0 3909 * 3910 * 2-0: MCS rate base 3911 * 0) 6 Mbps 3912 * 1) 12 Mbps 3913 * 2) 18 Mbps 3914 * 3) 24 Mbps 3915 * 4) 36 Mbps 3916 * 5) 48 Mbps 3917 * 6) 54 Mbps 3918 * 7) 60 Mbps 3919 * 4-3: 0) Single stream (SISO) 3920 * 1) Dual stream (MIMO) 3921 * 2) Triple stream (MIMO) 3922 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3923 * (bits 7-6 are zero) 3924 * 3925 * Together the low 5 bits work out to the MCS index because we don't 3926 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3927 * streams and 16-23 have three streams. We could also support MCS 32 3928 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3929 */ 3930#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3931#define IWM_RATE_HT_MCS_NSS_POS 3 3932#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3933 3934/* Bit 10: (1) Use Green Field preamble */ 3935#define IWM_RATE_HT_MCS_GF_POS 10 3936#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3937 3938#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3939 3940/* 3941 * Very High-throughput (VHT) rate format for bits 7:0 3942 * 3943 * 3-0: VHT MCS (0-9) 3944 * 5-4: number of streams - 1: 3945 * 0) Single stream (SISO) 3946 * 1) Dual stream (MIMO) 3947 * 2) Triple stream (MIMO) 3948 */ 3949 3950/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3951#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3952#define IWM_RATE_VHT_MCS_NSS_POS 4 3953#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3954 3955/* 3956 * Legacy OFDM rate format for bits 7:0 3957 * 3958 * 3-0: 0xD) 6 Mbps 3959 * 0xF) 9 Mbps 3960 * 0x5) 12 Mbps 3961 * 0x7) 18 Mbps 3962 * 0x9) 24 Mbps 3963 * 0xB) 36 Mbps 3964 * 0x1) 48 Mbps 3965 * 0x3) 54 Mbps 3966 * (bits 7-4 are 0) 3967 * 3968 * Legacy CCK rate format for bits 7:0: 3969 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3970 * 3971 * 6-0: 10) 1 Mbps 3972 * 20) 2 Mbps 3973 * 55) 5.5 Mbps 3974 * 110) 11 Mbps 3975 * (bit 7 is 0) 3976 */ 3977#define IWM_RATE_LEGACY_RATE_MSK 0xff 3978 3979 3980/* 3981 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 3982 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 3983 */ 3984#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 3985#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3986#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3987#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3988#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3989#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3990 3991/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 3992#define IWM_RATE_MCS_SGI_POS 13 3993#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 3994 3995/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 3996#define IWM_RATE_MCS_ANT_POS 14 3997#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 3998#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 3999#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4000#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4001 IWM_RATE_MCS_ANT_B_MSK) 4002#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4003 IWM_RATE_MCS_ANT_C_MSK) 4004#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4005#define IWM_RATE_MCS_ANT_NUM 3 4006 4007/* Bit 17-18: (0) SS, (1) SS*2 */ 4008#define IWM_RATE_MCS_STBC_POS 17 4009#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4010 4011/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4012#define IWM_RATE_MCS_BF_POS 19 4013#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4014 4015/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4016#define IWM_RATE_MCS_ZLF_POS 20 4017#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4018 4019/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4020#define IWM_RATE_MCS_DUP_POS 24 4021#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4022 4023/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4024#define IWM_RATE_MCS_LDPC_POS 27 4025#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4026 4027 4028/* Link Quality definitions */ 4029 4030/* # entries in rate scale table to support Tx retries */ 4031#define IWM_LQ_MAX_RETRY_NUM 16 4032 4033/* Link quality command flags bit fields */ 4034 4035/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4036#define IWM_LQ_FLAG_USE_RTS_POS 0 4037#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4038 4039/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4040#define IWM_LQ_FLAG_COLOR_POS 1 4041#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4042 4043/* Bit 4-5: Tx RTS BW Signalling 4044 * (0) No RTS BW signalling 4045 * (1) Static BW signalling 4046 * (2) Dynamic BW signalling 4047 */ 4048#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4049#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4050#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4051#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4052 4053/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4054 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4055 */ 4056#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4057#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4058 4059/* Single Stream Tx Parameters (lq_cmd->ss_params) 4060 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 4061 * used for single stream Tx. 4062 */ 4063 4064/* Bit 0-1: Max STBC streams allowed. Can be 0-3. 4065 * (0) - No STBC allowed 4066 * (1) - 2x1 STBC allowed (HT/VHT) 4067 * (2) - 4x2 STBC allowed (HT/VHT) 4068 * (3) - 3x2 STBC allowed (HT only) 4069 * All our chips are at most 2 antennas so only (1) is valid for now. 4070 */ 4071#define IWM_LQ_SS_STBC_ALLOWED_POS 0 4072#define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK) 4073 4074/* 2x1 STBC is allowed */ 4075#define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS) 4076 4077/* Bit 2: Beamformer (VHT only) is allowed */ 4078#define IWM_LQ_SS_BFER_ALLOWED_POS 2 4079#define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS) 4080 4081/* Bit 3: Force BFER or STBC for testing 4082 * If this is set: 4083 * If BFER is allowed then force the ucode to choose BFER else 4084 * If STBC is allowed then force the ucode to choose STBC over SISO 4085 */ 4086#define IWM_LQ_SS_FORCE_POS 3 4087#define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS) 4088 4089/* Bit 31: ss_params field is valid. Used for FW backward compatibility 4090 * with other drivers which don't support the ss_params API yet 4091 */ 4092#define IWM_LQ_SS_PARAMS_VALID_POS 31 4093#define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS) 4094 4095/** 4096 * struct iwm_lq_cmd - link quality command 4097 * @sta_id: station to update 4098 * @control: not used 4099 * @flags: combination of IWM_LQ_FLAG_* 4100 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4101 * and SISO rates 4102 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4103 * Should be ANT_[ABC] 4104 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4105 * @initial_rate_index: first index from rs_table per AC category 4106 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4107 * value of 100 is one usec. Range is 100 to 8000 4108 * @agg_disable_start_th: try-count threshold for starting aggregation. 4109 * If a frame has higher try-count, it should not be selected for 4110 * starting an aggregation sequence. 4111 * @agg_frame_cnt_limit: max frame count in an aggregation. 4112 * 0: no limit 4113 * 1: no aggregation (one frame per aggregation) 4114 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4115 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4116 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4117 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 4118 */ 4119struct iwm_lq_cmd { 4120 uint8_t sta_id; 4121 uint8_t reduced_tpc; 4122 uint16_t control; 4123 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4124 uint8_t flags; 4125 uint8_t mimo_delim; 4126 uint8_t single_stream_ant_msk; 4127 uint8_t dual_stream_ant_msk; 4128 uint8_t initial_rate_index[IWM_AC_NUM]; 4129 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4130 uint16_t agg_time_limit; 4131 uint8_t agg_disable_start_th; 4132 uint8_t agg_frame_cnt_limit; 4133 uint32_t reserved2; 4134 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4135 uint32_t ss_params; 4136}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4137 4138/* 4139 * END mvm/fw-api-rs.h 4140 */ 4141 4142/* 4143 * BEGIN mvm/fw-api-tx.h 4144 */ 4145 4146/** 4147 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4148 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4149 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4150 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4151 * Otherwise, use rate_n_flags from the TX command 4152 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4153 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4154 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4155 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4156 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4157 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4158 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4159 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4160 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4161 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4162 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4163 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4164 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4165 * Should be set for beacons and probe responses 4166 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4167 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4168 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4169 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4170 * Should be set for 26/30 length MAC headers 4171 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4172 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4173 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4174 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4175 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4176 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4177 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4178 */ 4179enum iwm_tx_flags { 4180 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4181 IWM_TX_CMD_FLG_ACK = (1 << 3), 4182 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4183 IWM_TX_CMD_FLG_BA = (1 << 5), 4184 IWM_TX_CMD_FLG_BAR = (1 << 6), 4185 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4186 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4187 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4188 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4189 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4190 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4191 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4192 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4193 IWM_TX_CMD_FLG_TSF = (1 << 16), 4194 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4195 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4196 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4197 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4198 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4199 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4200 IWM_TX_CMD_FLG_DUR = (1 << 25), 4201 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4202 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4203 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4204 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4205}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4206 4207/** 4208 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4209 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4210 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4211 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4212 */ 4213enum iwm_tx_pm_timeouts { 4214 IWM_PM_FRAME_NONE = 0, 4215 IWM_PM_FRAME_MGMT = 2, 4216 IWM_PM_FRAME_ASSOC = 3, 4217}; 4218 4219/* 4220 * TX command security control 4221 */ 4222#define IWM_TX_CMD_SEC_WEP 0x01 4223#define IWM_TX_CMD_SEC_CCM 0x02 4224#define IWM_TX_CMD_SEC_TKIP 0x03 4225#define IWM_TX_CMD_SEC_EXT 0x04 4226#define IWM_TX_CMD_SEC_MSK 0x07 4227#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4228#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4229#define IWM_TX_CMD_SEC_KEY128 0x08 4230 4231/* TODO: how does these values are OK with only 16 bit variable??? */ 4232/* 4233 * TX command next frame info 4234 * 4235 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4236 * bit 3 - immediate ACK required 4237 * bit 4 - rate is taken from STA table 4238 * bit 5 - frame belongs to BA stream 4239 * bit 6 - immediate BA response expected 4240 * bit 7 - unused 4241 * bits 8:15 - Station ID 4242 * bits 16:31 - rate 4243 */ 4244#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4245#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4246#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4247#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4248#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4249#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4250#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4251#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4252#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4253 4254/* 4255 * TX command Frame life time in us - to be written in pm_frame_timeout 4256 */ 4257#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4258#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4259#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4260#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4261 4262/* 4263 * TID for non QoS frames - to be written in tid_tspec 4264 */ 4265#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4266 4267/* 4268 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4269 */ 4270#define IWM_DEFAULT_TX_RETRY 15 4271#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4272#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4273#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4274#define IWM_LOW_RETRY_LIMIT 7 4275 4276/* TODO: complete documentation for try_cnt and btkill_cnt */ 4277/** 4278 * struct iwm_tx_cmd - TX command struct to FW 4279 * ( IWM_TX_CMD = 0x1c ) 4280 * @len: in bytes of the payload, see below for details 4281 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4282 * Used for fragmentation and bursting, but not in 11n aggregation. 4283 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4284 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4285 * cleared. Combination of IWM_RATE_MCS_* 4286 * @sta_id: index of destination station in FW station table 4287 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4288 * @initial_rate_index: index into the rate table for initial TX attempt. 4289 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4290 * @key: security key 4291 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4292 * @life_time: frame life time (usecs??) 4293 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4294 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4295 * @dram_msb_ptr: upper bits of the scratch physical address 4296 * @rts_retry_limit: max attempts for RTS 4297 * @data_retry_limit: max attempts to send the data packet 4298 * @tid_spec: TID/tspec 4299 * @pm_frame_timeout: PM TX frame timeout 4300 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4301 * specified by HCCA protocol 4302 * 4303 * The byte count (both len and next_frame_len) includes MAC header 4304 * (24/26/30/32 bytes) 4305 * + 2 bytes pad if 26/30 header size 4306 * + 8 byte IV for CCM or TKIP (not used for WEP) 4307 * + Data payload 4308 * + 8-byte MIC (not used for CCM/WEP) 4309 * It does not include post-MAC padding, i.e., 4310 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4311 * Range of len: 14-2342 bytes. 4312 * 4313 * After the struct fields the MAC header is placed, plus any padding, 4314 * and then the actial payload. 4315 */ 4316struct iwm_tx_cmd { 4317 uint16_t len; 4318 uint16_t next_frame_len; 4319 uint32_t tx_flags; 4320 struct { 4321 uint8_t try_cnt; 4322 uint8_t btkill_cnt; 4323 uint16_t reserved; 4324 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4325 uint32_t rate_n_flags; 4326 uint8_t sta_id; 4327 uint8_t sec_ctl; 4328 uint8_t initial_rate_index; 4329 uint8_t reserved2; 4330 uint8_t key[16]; 4331 uint16_t next_frame_flags; 4332 uint16_t reserved3; 4333 uint32_t life_time; 4334 uint32_t dram_lsb_ptr; 4335 uint8_t dram_msb_ptr; 4336 uint8_t rts_retry_limit; 4337 uint8_t data_retry_limit; 4338 uint8_t tid_tspec; 4339 uint16_t pm_frame_timeout; 4340 uint16_t driver_txop; 4341 uint8_t payload[0]; 4342 struct ieee80211_frame hdr[0]; 4343} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4344 4345/* 4346 * TX response related data 4347 */ 4348 4349/* 4350 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4351 * @IWM_TX_STATUS_SUCCESS: 4352 * @IWM_TX_STATUS_DIRECT_DONE: 4353 * @IWM_TX_STATUS_POSTPONE_DELAY: 4354 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4355 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4356 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4357 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4358 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4359 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4360 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4361 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4362 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4363 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4364 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4365 * @IWM_TX_STATUS_FAIL_DEST_PS: 4366 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4367 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4368 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4369 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4370 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4371 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4372 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4373 * @IWM_TX_STATUS_FAIL_FW_DROP: 4374 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4375 * STA table 4376 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4377 * @IWM_TX_MODE_MSK: 4378 * @IWM_TX_MODE_NO_BURST: 4379 * @IWM_TX_MODE_IN_BURST_SEQ: 4380 * @IWM_TX_MODE_FIRST_IN_BURST: 4381 * @IWM_TX_QUEUE_NUM_MSK: 4382 * 4383 * Valid only if frame_count =1 4384 * TODO: complete documentation 4385 */ 4386enum iwm_tx_status { 4387 IWM_TX_STATUS_MSK = 0x000000ff, 4388 IWM_TX_STATUS_SUCCESS = 0x01, 4389 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4390 /* postpone TX */ 4391 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4392 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4393 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4394 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4395 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4396 /* abort TX */ 4397 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4398 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4399 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4400 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4401 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4402 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4403 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4404 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4405 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4406 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4407 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4408 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4409 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4410 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4411 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4412 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4413 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4414 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4415 IWM_TX_MODE_MSK = 0x00000f00, 4416 IWM_TX_MODE_NO_BURST = 0x00000000, 4417 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4418 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4419 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4420 IWM_TX_NARROW_BW_MSK = 0x00060000, 4421 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4422 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4423 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4424}; 4425 4426/* 4427 * enum iwm_tx_agg_status - TX aggregation status 4428 * @IWM_AGG_TX_STATE_STATUS_MSK: 4429 * @IWM_AGG_TX_STATE_TRANSMITTED: 4430 * @IWM_AGG_TX_STATE_UNDERRUN: 4431 * @IWM_AGG_TX_STATE_BT_PRIO: 4432 * @IWM_AGG_TX_STATE_FEW_BYTES: 4433 * @IWM_AGG_TX_STATE_ABORT: 4434 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4435 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4436 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4437 * @IWM_AGG_TX_STATE_SCD_QUERY: 4438 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4439 * @IWM_AGG_TX_STATE_RESPONSE: 4440 * @IWM_AGG_TX_STATE_DUMP_TX: 4441 * @IWM_AGG_TX_STATE_DELAY_TX: 4442 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4443 * occur if tx failed for this frame when it was a member of a previous 4444 * aggregation block). If rate scaling is used, retry count indicates the 4445 * rate table entry used for all frames in the new agg. 4446 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4447 * this frame 4448 * 4449 * TODO: complete documentation 4450 */ 4451enum iwm_tx_agg_status { 4452 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4453 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4454 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4455 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4456 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4457 IWM_AGG_TX_STATE_ABORT = 0x008, 4458 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4459 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4460 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4461 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4462 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4463 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4464 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4465 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4466 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4467 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4468}; 4469 4470#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4471 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4472 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4473 4474/* 4475 * The mask below describes a status where we are absolutely sure that the MPDU 4476 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4477 * written the bytes to the TXE, but we know nothing about what the DSP did. 4478 */ 4479#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4480 IWM_AGG_TX_STATE_ABORT | \ 4481 IWM_AGG_TX_STATE_SCD_QUERY) 4482 4483/* 4484 * IWM_REPLY_TX = 0x1c (response) 4485 * 4486 * This response may be in one of two slightly different formats, indicated 4487 * by the frame_count field: 4488 * 4489 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4490 * frame. Multiple attempts, at various bit rates, may have been made for 4491 * this frame. 4492 * 4493 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4494 * frames that used block-acknowledge. All frames were transmitted at 4495 * same rate. Rate scaling may have been used if first frame in this new 4496 * agg block failed in previous agg block(s). 4497 * 4498 * Note that, for aggregation, ACK (block-ack) status is not delivered 4499 * here; block-ack has not been received by the time the device records 4500 * this status. 4501 * This status relates to reasons the tx might have been blocked or aborted 4502 * within the device, rather than whether it was received successfully by 4503 * the destination station. 4504 */ 4505 4506/** 4507 * struct iwm_agg_tx_status - per packet TX aggregation status 4508 * @status: enum iwm_tx_agg_status 4509 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4510 */ 4511struct iwm_agg_tx_status { 4512 uint16_t status; 4513 uint16_t sequence; 4514} __packed; 4515 4516/* 4517 * definitions for initial rate index field 4518 * bits [3:0] initial rate index 4519 * bits [6:4] rate table color, used for the initial rate 4520 * bit-7 invalid rate indication 4521 */ 4522#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4523#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4524#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4525 4526#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4527#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4528 4529/** 4530 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4531 * ( IWM_REPLY_TX = 0x1c ) 4532 * @frame_count: 1 no aggregation, >1 aggregation 4533 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4534 * @failure_rts: num of failures due to unsuccessful RTS 4535 * @failure_frame: num failures due to no ACK (unused for agg) 4536 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4537 * Tx of all the batch. IWM_RATE_MCS_* 4538 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4539 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4540 * in usec. 4541 * @pa_status: tx power info 4542 * @pa_integ_res_a: tx power info 4543 * @pa_integ_res_b: tx power info 4544 * @pa_integ_res_c: tx power info 4545 * @measurement_req_id: tx power info 4546 * @tfd_info: TFD information set by the FH 4547 * @seq_ctl: sequence control from the Tx cmd 4548 * @byte_cnt: byte count from the Tx cmd 4549 * @tlc_info: TLC rate info 4550 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4551 * @frame_ctrl: frame control 4552 * @status: for non-agg: frame status IWM_TX_STATUS_* 4553 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4554 * follow this one, up to frame_count. 4555 * 4556 * After the array of statuses comes the SSN of the SCD. Look at 4557 * %iwm_mvm_get_scd_ssn for more details. 4558 */ 4559struct iwm_mvm_tx_resp { 4560 uint8_t frame_count; 4561 uint8_t bt_kill_count; 4562 uint8_t failure_rts; 4563 uint8_t failure_frame; 4564 uint32_t initial_rate; 4565 uint16_t wireless_media_time; 4566 4567 uint8_t pa_status; 4568 uint8_t pa_integ_res_a[3]; 4569 uint8_t pa_integ_res_b[3]; 4570 uint8_t pa_integ_res_c[3]; 4571 uint16_t measurement_req_id; 4572 uint8_t reduced_tpc; 4573 uint8_t reserved; 4574 4575 uint32_t tfd_info; 4576 uint16_t seq_ctl; 4577 uint16_t byte_cnt; 4578 uint8_t tlc_info; 4579 uint8_t ra_tid; 4580 uint16_t frame_ctrl; 4581 4582 struct iwm_agg_tx_status status; 4583} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4584 4585/** 4586 * struct iwm_mvm_ba_notif - notifies about reception of BA 4587 * ( IWM_BA_NOTIF = 0xc5 ) 4588 * @sta_addr_lo32: lower 32 bits of the MAC address 4589 * @sta_addr_hi16: upper 16 bits of the MAC address 4590 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4591 * @tid: tid of the session 4592 * @seq_ctl: 4593 * @bitmap: the bitmap of the BA notification as seen in the air 4594 * @scd_flow: the tx queue this BA relates to 4595 * @scd_ssn: the index of the last contiguously sent packet 4596 * @txed: number of Txed frames in this batch 4597 * @txed_2_done: number of Acked frames in this batch 4598 */ 4599struct iwm_mvm_ba_notif { 4600 uint32_t sta_addr_lo32; 4601 uint16_t sta_addr_hi16; 4602 uint16_t reserved; 4603 4604 uint8_t sta_id; 4605 uint8_t tid; 4606 uint16_t seq_ctl; 4607 uint64_t bitmap; 4608 uint16_t scd_flow; 4609 uint16_t scd_ssn; 4610 uint8_t txed; 4611 uint8_t txed_2_done; 4612 uint16_t reserved1; 4613} __packed; 4614 4615/* 4616 * struct iwm_mac_beacon_cmd - beacon template command 4617 * @tx: the tx commands associated with the beacon frame 4618 * @template_id: currently equal to the mac context id of the coresponding 4619 * mac. 4620 * @tim_idx: the offset of the tim IE in the beacon 4621 * @tim_size: the length of the tim IE 4622 * @frame: the template of the beacon frame 4623 */ 4624struct iwm_mac_beacon_cmd { 4625 struct iwm_tx_cmd tx; 4626 uint32_t template_id; 4627 uint32_t tim_idx; 4628 uint32_t tim_size; 4629 struct ieee80211_frame frame[0]; 4630} __packed; 4631 4632struct iwm_beacon_notif { 4633 struct iwm_mvm_tx_resp beacon_notify_hdr; 4634 uint64_t tsf; 4635 uint32_t ibss_mgr_status; 4636} __packed; 4637 4638/** 4639 * enum iwm_dump_control - dump (flush) control flags 4640 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4641 * and the TFD queues are empty. 4642 */ 4643enum iwm_dump_control { 4644 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4645}; 4646 4647/** 4648 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4649 * @queues_ctl: bitmap of queues to flush 4650 * @flush_ctl: control flags 4651 * @reserved: reserved 4652 */ 4653struct iwm_tx_path_flush_cmd { 4654 uint32_t queues_ctl; 4655 uint16_t flush_ctl; 4656 uint16_t reserved; 4657} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4658 4659/** 4660 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4661 * @tx_resp: the Tx response from the fw (agg or non-agg) 4662 * 4663 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4664 * it can't know that everything will go well until the end of the AMPDU, it 4665 * can't know in advance the number of MPDUs that will be sent in the current 4666 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4667 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4668 * of the batch. This is why the SSN of the SCD is written at the end of the 4669 * whole struct at a variable offset. This function knows how to cope with the 4670 * variable offset and returns the SSN of the SCD. 4671 */ 4672static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4673{ 4674 return le32_to_cpup((uint32_t *)&tx_resp->status + 4675 tx_resp->frame_count) & 0xfff; 4676} 4677 4678/* 4679 * END mvm/fw-api-tx.h 4680 */ 4681 4682/* 4683 * BEGIN mvm/fw-api-scan.h 4684 */ 4685 4686/** 4687 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4688 * @token: 4689 * @sta_id: station id 4690 * @tid: 4691 * @scd_queue: scheduler queue to confiug 4692 * @enable: 1 queue enable, 0 queue disable 4693 * @aggregate: 1 aggregated queue, 0 otherwise 4694 * @tx_fifo: %enum iwm_mvm_tx_fifo 4695 * @window: BA window size 4696 * @ssn: SSN for the BA agreement 4697 */ 4698struct iwm_scd_txq_cfg_cmd { 4699 uint8_t token; 4700 uint8_t sta_id; 4701 uint8_t tid; 4702 uint8_t scd_queue; 4703 uint8_t enable; 4704 uint8_t aggregate; 4705 uint8_t tx_fifo; 4706 uint8_t window; 4707 uint16_t ssn; 4708 uint16_t reserved; 4709} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4710 4711/** 4712 * struct iwm_scd_txq_cfg_rsp 4713 * @token: taken from the command 4714 * @sta_id: station id from the command 4715 * @tid: tid from the command 4716 * @scd_queue: scd_queue from the command 4717 */ 4718struct iwm_scd_txq_cfg_rsp { 4719 uint8_t token; 4720 uint8_t sta_id; 4721 uint8_t tid; 4722 uint8_t scd_queue; 4723} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4724 4725 4726/* Scan Commands, Responses, Notifications */ 4727 4728/* Masks for iwm_scan_channel.type flags */ 4729#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4730#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4731 4732/* Max number of IEs for direct SSID scans in a command */ 4733#define IWM_PROBE_OPTION_MAX 20 4734 4735/** 4736 * struct iwm_ssid_ie - directed scan network information element 4737 * 4738 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4739 * selected by "type" bit field in struct iwm_scan_channel; 4740 * each channel may select different ssids from among the 20 entries. 4741 * SSID IEs get transmitted in reverse order of entry. 4742 */ 4743struct iwm_ssid_ie { 4744 uint8_t id; 4745 uint8_t len; 4746 uint8_t ssid[IEEE80211_NWID_LEN]; 4747} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4748 4749/* scan offload */ 4750#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4751#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4752#define IWM_SCAN_MAX_PROFILES 11 4753#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4754 4755/* Default watchdog (in MS) for scheduled scan iteration */ 4756#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4757 4758#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4759#define IWM_CAN_ABORT_STATUS 1 4760 4761#define IWM_FULL_SCAN_MULTIPLIER 5 4762#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4763#define IWM_MAX_SCHED_SCAN_PLANS 2 4764 4765/** 4766 * iwm_scan_schedule_lmac - schedule of scan offload 4767 * @delay: delay between iterations, in seconds. 4768 * @iterations: num of scan iterations 4769 * @full_scan_mul: number of partial scans before each full scan 4770 */ 4771struct iwm_scan_schedule_lmac { 4772 uint16_t delay; 4773 uint8_t iterations; 4774 uint8_t full_scan_mul; 4775} __packed; /* SCAN_SCHEDULE_API_S */ 4776 4777/** 4778 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4779 * @tx_flags: combination of TX_CMD_FLG_* 4780 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4781 * cleared. Combination of RATE_MCS_* 4782 * @sta_id: index of destination station in FW station table 4783 * @reserved: for alignment and future use 4784 */ 4785struct iwm_scan_req_tx_cmd { 4786 uint32_t tx_flags; 4787 uint32_t rate_n_flags; 4788 uint8_t sta_id; 4789 uint8_t reserved[3]; 4790} __packed; 4791 4792enum iwm_scan_channel_flags_lmac { 4793 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4794 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4795}; 4796 4797/** 4798 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4799 * @flags: bits 1-20: directed scan to i'th ssid 4800 * other bits &enum iwm_scan_channel_flags_lmac 4801 * @channel_number: channel number 1-13 etc 4802 * @iter_count: scan iteration on this channel 4803 * @iter_interval: interval in seconds between iterations on one channel 4804 */ 4805struct iwm_scan_channel_cfg_lmac { 4806 uint32_t flags; 4807 uint16_t channel_num; 4808 uint16_t iter_count; 4809 uint32_t iter_interval; 4810} __packed; 4811 4812/* 4813 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4814 * @offset: offset in the data block 4815 * @len: length of the segment 4816 */ 4817struct iwm_scan_probe_segment { 4818 uint16_t offset; 4819 uint16_t len; 4820} __packed; 4821 4822/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4823 * @mac_header: first (and common) part of the probe 4824 * @band_data: band specific data 4825 * @common_data: last (and common) part of the probe 4826 * @buf: raw data block 4827 */ 4828struct iwm_scan_probe_req { 4829 struct iwm_scan_probe_segment mac_header; 4830 struct iwm_scan_probe_segment band_data[2]; 4831 struct iwm_scan_probe_segment common_data; 4832 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4833} __packed; 4834 4835enum iwm_scan_channel_flags { 4836 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4837 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4838 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4839}; 4840 4841/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4842 * @flags: enum iwm_scan_channel_flags 4843 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4844 * involved. 4845 * 1 - EBS is disabled. 4846 * 2 - every second scan will be full scan(and so on). 4847 */ 4848struct iwm_scan_channel_opt { 4849 uint16_t flags; 4850 uint16_t non_ebs_ratio; 4851} __packed; 4852 4853/** 4854 * iwm_mvm_lmac_scan_flags 4855 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4856 * without filtering. 4857 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4858 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4859 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4860 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4861 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4862 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4863 * and DS parameter set IEs into probe requests. 4864 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4865 * 1, 6 and 11. 4866 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4867 */ 4868enum iwm_mvm_lmac_scan_flags { 4869 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4870 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4871 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4872 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4873 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4874 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4875 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4876 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4877 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4878}; 4879 4880enum iwm_scan_priority { 4881 IWM_SCAN_PRIORITY_LOW, 4882 IWM_SCAN_PRIORITY_MEDIUM, 4883 IWM_SCAN_PRIORITY_HIGH, 4884}; 4885 4886/** 4887 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4888 * @reserved1: for alignment and future use 4889 * @channel_num: num of channels to scan 4890 * @active-dwell: dwell time for active channels 4891 * @passive-dwell: dwell time for passive channels 4892 * @fragmented-dwell: dwell time for fragmented passive scan 4893 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4894 * @reserved2: for alignment and future use 4895 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4896 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4897 * @max_out_time: max time (in TU) to be out of associated channel 4898 * @suspend_time: pause scan this long (TUs) when returning to service channel 4899 * @flags: RXON flags 4900 * @filter_flags: RXON filter 4901 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4902 * @direct_scan: list of SSIDs for directed active scan 4903 * @scan_prio: enum iwm_scan_priority 4904 * @iter_num: number of scan iterations 4905 * @delay: delay in seconds before first iteration 4906 * @schedule: two scheduling plans. The first one is finite, the second one can 4907 * be infinite. 4908 * @channel_opt: channel optimization options, for full and partial scan 4909 * @data: channel configuration and probe request packet. 4910 */ 4911struct iwm_scan_req_lmac { 4912 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4913 uint32_t reserved1; 4914 uint8_t n_channels; 4915 uint8_t active_dwell; 4916 uint8_t passive_dwell; 4917 uint8_t fragmented_dwell; 4918 uint8_t extended_dwell; 4919 uint8_t reserved2; 4920 uint16_t rx_chain_select; 4921 uint32_t scan_flags; 4922 uint32_t max_out_time; 4923 uint32_t suspend_time; 4924 /* RX_ON_FLAGS_API_S_VER_1 */ 4925 uint32_t flags; 4926 uint32_t filter_flags; 4927 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4928 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4929 uint32_t scan_prio; 4930 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4931 uint32_t iter_num; 4932 uint32_t delay; 4933 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4934 struct iwm_scan_channel_opt channel_opt[2]; 4935 uint8_t data[]; 4936} __packed; 4937 4938/** 4939 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4940 * @last_schedule_line: last schedule line executed (fast or regular) 4941 * @last_schedule_iteration: last scan iteration executed before scan abort 4942 * @status: enum iwm_scan_offload_complete_status 4943 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4944 * @time_after_last_iter; time in seconds elapsed after last iteration 4945 */ 4946struct iwm_periodic_scan_complete { 4947 uint8_t last_schedule_line; 4948 uint8_t last_schedule_iteration; 4949 uint8_t status; 4950 uint8_t ebs_status; 4951 uint32_t time_after_last_iter; 4952 uint32_t reserved; 4953} __packed; 4954 4955/* How many statistics are gathered for each channel */ 4956#define IWM_SCAN_RESULTS_STATISTICS 1 4957 4958/** 4959 * enum iwm_scan_complete_status - status codes for scan complete notifications 4960 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4961 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4962 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4963 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4964 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4965 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4966 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4967 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4968 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4969 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4970 * (not an error!) 4971 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4972 * asked for 4973 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4974*/ 4975enum iwm_scan_complete_status { 4976 IWM_SCAN_COMP_STATUS_OK = 0x1, 4977 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4978 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4979 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4980 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4981 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4982 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4983 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4984 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4985 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4986 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4987 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4988}; 4989 4990/** 4991 * struct iwm_scan_results_notif - scan results for one channel 4992 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4993 * @channel: which channel the results are from 4994 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4995 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4996 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4997 * @duration: duration spent in channel, in usecs 4998 * @statistics: statistics gathered for this channel 4999 */ 5000struct iwm_scan_results_notif { 5001 uint8_t channel; 5002 uint8_t band; 5003 uint8_t probe_status; 5004 uint8_t num_probe_not_sent; 5005 uint32_t duration; 5006 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5007} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5008 5009enum iwm_scan_framework_client { 5010 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5011 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5012 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5013}; 5014 5015/** 5016 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5017 * @ssid: MAC address to filter out 5018 * @reported_rssi: AP rssi reported to the host 5019 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5020 */ 5021struct iwm_scan_offload_blacklist { 5022 uint8_t ssid[IEEE80211_ADDR_LEN]; 5023 uint8_t reported_rssi; 5024 uint8_t client_bitmap; 5025} __packed; 5026 5027enum iwm_scan_offload_network_type { 5028 IWM_NETWORK_TYPE_BSS = 1, 5029 IWM_NETWORK_TYPE_IBSS = 2, 5030 IWM_NETWORK_TYPE_ANY = 3, 5031}; 5032 5033enum iwm_scan_offload_band_selection { 5034 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5035 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5036 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5037}; 5038 5039/** 5040 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5041 * @ssid_index: index to ssid list in fixed part 5042 * @unicast_cipher: encryption olgorithm to match - bitmap 5043 * @aut_alg: authentication olgorithm to match - bitmap 5044 * @network_type: enum iwm_scan_offload_network_type 5045 * @band_selection: enum iwm_scan_offload_band_selection 5046 * @client_bitmap: clients waiting for match - enum scan_framework_client 5047 */ 5048struct iwm_scan_offload_profile { 5049 uint8_t ssid_index; 5050 uint8_t unicast_cipher; 5051 uint8_t auth_alg; 5052 uint8_t network_type; 5053 uint8_t band_selection; 5054 uint8_t client_bitmap; 5055 uint8_t reserved[2]; 5056} __packed; 5057 5058/** 5059 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5060 * @blaclist: AP list to filter off from scan results 5061 * @profiles: profiles to search for match 5062 * @blacklist_len: length of blacklist 5063 * @num_profiles: num of profiles in the list 5064 * @match_notify: clients waiting for match found notification 5065 * @pass_match: clients waiting for the results 5066 * @active_clients: active clients bitmap - enum scan_framework_client 5067 * @any_beacon_notify: clients waiting for match notification without match 5068 */ 5069struct iwm_scan_offload_profile_cfg { 5070 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5071 uint8_t blacklist_len; 5072 uint8_t num_profiles; 5073 uint8_t match_notify; 5074 uint8_t pass_match; 5075 uint8_t active_clients; 5076 uint8_t any_beacon_notify; 5077 uint8_t reserved[2]; 5078} __packed; 5079 5080enum iwm_scan_offload_complete_status { 5081 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5082 IWM_SCAN_OFFLOAD_ABORTED = 2, 5083}; 5084 5085/** 5086 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5087 * SCAN_COMPLETE_NTF_API_S_VER_3 5088 * @scanned_channels: number of channels scanned (and number of valid results) 5089 * @status: one of SCAN_COMP_STATUS_* 5090 * @bt_status: BT on/off status 5091 * @last_channel: last channel that was scanned 5092 * @tsf_low: TSF timer (lower half) in usecs 5093 * @tsf_high: TSF timer (higher half) in usecs 5094 * @results: an array of scan results, only "scanned_channels" of them are valid 5095 */ 5096struct iwm_lmac_scan_complete_notif { 5097 uint8_t scanned_channels; 5098 uint8_t status; 5099 uint8_t bt_status; 5100 uint8_t last_channel; 5101 uint32_t tsf_low; 5102 uint32_t tsf_high; 5103 struct iwm_scan_results_notif results[]; 5104} __packed; 5105 5106 5107/* 5108 * END mvm/fw-api-scan.h 5109 */ 5110 5111/* 5112 * BEGIN mvm/fw-api-sta.h 5113 */ 5114 5115/* UMAC Scan API */ 5116 5117/* The maximum of either of these cannot exceed 8, because we use an 5118 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5119 */ 5120#define IWM_MVM_MAX_UMAC_SCANS 8 5121#define IWM_MVM_MAX_LMAC_SCANS 1 5122 5123enum iwm_scan_config_flags { 5124 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5125 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5126 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5127 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5128 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5129 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5130 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5131 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5132 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5133 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5134 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5135 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5136 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5137 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5138 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5139 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5140 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5141 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5142 5143 /* Bits 26-31 are for num of channels in channel_array */ 5144#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5145}; 5146 5147enum iwm_scan_config_rates { 5148 /* OFDM basic rates */ 5149 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5150 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5151 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5152 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5153 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5154 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5155 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5156 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5157 /* CCK basic rates */ 5158 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5159 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5160 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5161 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5162 5163 /* Bits 16-27 are for supported rates */ 5164#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5165}; 5166 5167enum iwm_channel_flags { 5168 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5169 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5170 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5171 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5172}; 5173 5174/** 5175 * struct iwm_scan_config 5176 * @flags: enum scan_config_flags 5177 * @tx_chains: valid_tx antenna - ANT_* definitions 5178 * @rx_chains: valid_rx antenna - ANT_* definitions 5179 * @legacy_rates: default legacy rates - enum scan_config_rates 5180 * @out_of_channel_time: default max out of serving channel time 5181 * @suspend_time: default max suspend time 5182 * @dwell_active: default dwell time for active scan 5183 * @dwell_passive: default dwell time for passive scan 5184 * @dwell_fragmented: default dwell time for fragmented scan 5185 * @dwell_extended: default dwell time for channels 1, 6 and 11 5186 * @mac_addr: default mac address to be used in probes 5187 * @bcast_sta_id: the index of the station in the fw 5188 * @channel_flags: default channel flags - enum iwm_channel_flags 5189 * scan_config_channel_flag 5190 * @channel_array: default supported channels 5191 */ 5192struct iwm_scan_config { 5193 uint32_t flags; 5194 uint32_t tx_chains; 5195 uint32_t rx_chains; 5196 uint32_t legacy_rates; 5197 uint32_t out_of_channel_time; 5198 uint32_t suspend_time; 5199 uint8_t dwell_active; 5200 uint8_t dwell_passive; 5201 uint8_t dwell_fragmented; 5202 uint8_t dwell_extended; 5203 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5204 uint8_t bcast_sta_id; 5205 uint8_t channel_flags; 5206 uint8_t channel_array[]; 5207} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5208 5209/** 5210 * iwm_umac_scan_flags 5211 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5212 * can be preempted by other scan requests with higher priority. 5213 * The low priority scan will be resumed when the higher proirity scan is 5214 * completed. 5215 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5216 * when scan starts. 5217 */ 5218enum iwm_umac_scan_flags { 5219 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5220 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5221}; 5222 5223enum iwm_umac_scan_uid_offsets { 5224 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5225 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5226}; 5227 5228enum iwm_umac_scan_general_flags { 5229 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5230 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5231 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5232 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5233 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5234 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5235 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5236 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5237 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5238 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5239 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5240}; 5241 5242/** 5243 * struct iwm_scan_channel_cfg_umac 5244 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5245 * @channel_num: channel number 1-13 etc. 5246 * @iter_count: repetition count for the channel. 5247 * @iter_interval: interval between two scan iterations on one channel. 5248 */ 5249struct iwm_scan_channel_cfg_umac { 5250 uint32_t flags; 5251#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5252 5253 uint8_t channel_num; 5254 uint8_t iter_count; 5255 uint16_t iter_interval; 5256} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5257 5258/** 5259 * struct iwm_scan_umac_schedule 5260 * @interval: interval in seconds between scan iterations 5261 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5262 * @reserved: for alignment and future use 5263 */ 5264struct iwm_scan_umac_schedule { 5265 uint16_t interval; 5266 uint8_t iter_count; 5267 uint8_t reserved; 5268} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5269 5270/** 5271 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5272 * parameters following channels configuration array. 5273 * @schedule: two scheduling plans. 5274 * @delay: delay in TUs before starting the first scan iteration 5275 * @reserved: for future use and alignment 5276 * @preq: probe request with IEs blocks 5277 * @direct_scan: list of SSIDs for directed active scan 5278 */ 5279struct iwm_scan_req_umac_tail { 5280 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5281 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5282 uint16_t delay; 5283 uint16_t reserved; 5284 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5285 struct iwm_scan_probe_req preq; 5286 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5287} __packed; 5288 5289/** 5290 * struct iwm_scan_req_umac 5291 * @flags: &enum iwm_umac_scan_flags 5292 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5293 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5294 * @general_flags: &enum iwm_umac_scan_general_flags 5295 * @extended_dwell: dwell time for channels 1, 6 and 11 5296 * @active_dwell: dwell time for active scan 5297 * @passive_dwell: dwell time for passive scan 5298 * @fragmented_dwell: dwell time for fragmented passive scan 5299 * @max_out_time: max out of serving channel time 5300 * @suspend_time: max suspend time 5301 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5302 * @channel_flags: &enum iwm_scan_channel_flags 5303 * @n_channels: num of channels in scan request 5304 * @reserved: for future use and alignment 5305 * @data: &struct iwm_scan_channel_cfg_umac and 5306 * &struct iwm_scan_req_umac_tail 5307 */ 5308struct iwm_scan_req_umac { 5309 uint32_t flags; 5310 uint32_t uid; 5311 uint32_t ooc_priority; 5312 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5313 uint32_t general_flags; 5314 uint8_t extended_dwell; 5315 uint8_t active_dwell; 5316 uint8_t passive_dwell; 5317 uint8_t fragmented_dwell; 5318 uint32_t max_out_time; 5319 uint32_t suspend_time; 5320 uint32_t scan_priority; 5321 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5322 uint8_t channel_flags; 5323 uint8_t n_channels; 5324 uint16_t reserved; 5325 uint8_t data[]; 5326} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5327 5328/** 5329 * struct iwm_umac_scan_abort 5330 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5331 * @flags: reserved 5332 */ 5333struct iwm_umac_scan_abort { 5334 uint32_t uid; 5335 uint32_t flags; 5336} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5337 5338/** 5339 * struct iwm_umac_scan_complete 5340 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5341 * @last_schedule: last scheduling line 5342 * @last_iter: last scan iteration number 5343 * @scan status: &enum iwm_scan_offload_complete_status 5344 * @ebs_status: &enum iwm_scan_ebs_status 5345 * @time_from_last_iter: time elapsed from last iteration 5346 * @reserved: for future use 5347 */ 5348struct iwm_umac_scan_complete { 5349 uint32_t uid; 5350 uint8_t last_schedule; 5351 uint8_t last_iter; 5352 uint8_t status; 5353 uint8_t ebs_status; 5354 uint32_t time_from_last_iter; 5355 uint32_t reserved; 5356} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5357 5358#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5359/** 5360 * struct iwm_scan_offload_profile_match - match information 5361 * @bssid: matched bssid 5362 * @channel: channel where the match occurred 5363 * @energy: 5364 * @matching_feature: 5365 * @matching_channels: bitmap of channels that matched, referencing 5366 * the channels passed in tue scan offload request 5367 */ 5368struct iwm_scan_offload_profile_match { 5369 uint8_t bssid[IEEE80211_ADDR_LEN]; 5370 uint16_t reserved; 5371 uint8_t channel; 5372 uint8_t energy; 5373 uint8_t matching_feature; 5374 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5375} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5376 5377/** 5378 * struct iwm_scan_offload_profiles_query - match results query response 5379 * @matched_profiles: bitmap of matched profiles, referencing the 5380 * matches passed in the scan offload request 5381 * @last_scan_age: age of the last offloaded scan 5382 * @n_scans_done: number of offloaded scans done 5383 * @gp2_d0u: GP2 when D0U occurred 5384 * @gp2_invoked: GP2 when scan offload was invoked 5385 * @resume_while_scanning: not used 5386 * @self_recovery: obsolete 5387 * @reserved: reserved 5388 * @matches: array of match information, one for each match 5389 */ 5390struct iwm_scan_offload_profiles_query { 5391 uint32_t matched_profiles; 5392 uint32_t last_scan_age; 5393 uint32_t n_scans_done; 5394 uint32_t gp2_d0u; 5395 uint32_t gp2_invoked; 5396 uint8_t resume_while_scanning; 5397 uint8_t self_recovery; 5398 uint16_t reserved; 5399 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5400} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5401 5402/** 5403 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5404 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5405 * @scanned_channels: number of channels scanned and number of valid elements in 5406 * results array 5407 * @status: one of SCAN_COMP_STATUS_* 5408 * @bt_status: BT on/off status 5409 * @last_channel: last channel that was scanned 5410 * @tsf_low: TSF timer (lower half) in usecs 5411 * @tsf_high: TSF timer (higher half) in usecs 5412 * @results: array of scan results, only "scanned_channels" of them are valid 5413 */ 5414struct iwm_umac_scan_iter_complete_notif { 5415 uint32_t uid; 5416 uint8_t scanned_channels; 5417 uint8_t status; 5418 uint8_t bt_status; 5419 uint8_t last_channel; 5420 uint32_t tsf_low; 5421 uint32_t tsf_high; 5422 struct iwm_scan_results_notif results[]; 5423} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5424 5425/* Please keep this enum *SORTED* by hex value. 5426 * Needed for binary search, otherwise a warning will be triggered. 5427 */ 5428enum iwm_scan_subcmd_ids { 5429 IWM_GSCAN_START_CMD = 0x0, 5430 IWM_GSCAN_STOP_CMD = 0x1, 5431 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5432 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5433 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5434 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5435 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5436 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5437 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5438}; 5439 5440/* STA API */ 5441 5442/** 5443 * enum iwm_sta_flags - flags for the ADD_STA host command 5444 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5445 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5446 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5447 * @IWM_STA_FLG_PS: set if STA is in Power Save 5448 * @IWM_STA_FLG_INVALID: set if STA is invalid 5449 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5450 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5451 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5452 * @IWM_STA_FLG_PAN: STA is for PAN interface 5453 * @IWM_STA_FLG_CLASS_AUTH: 5454 * @IWM_STA_FLG_CLASS_ASSOC: 5455 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5456 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5457 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5458 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5459 * initialised by driver and can be updated by fw upon reception of 5460 * action frames that can change the channel width. When cleared the fw 5461 * will send all the frames in 20MHz even when FAT channel is requested. 5462 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5463 * driver and can be updated by fw upon reception of action frames. 5464 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5465 */ 5466enum iwm_sta_flags { 5467 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5468 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5469 5470 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5471 5472 IWM_STA_FLG_PS = (1 << 8), 5473 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5474 IWM_STA_FLG_PAN = (1 << 13), 5475 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5476 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5477 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5478 5479 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5480 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5481 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5482 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5483 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5484 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5485 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5486 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5487 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5488 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5489 5490 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5491 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5492 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5493 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5494 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5495 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5496 5497 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5498 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5499 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5500 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5501 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5502 5503 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5504 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5505 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5506 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5507}; 5508 5509/** 5510 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5511 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5512 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5513 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5514 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5515 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5516 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5517 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5518 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5519 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5520 * station info array (1 - n 1X mode) 5521 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5522 * @IWM_STA_KEY_NOT_VALID: key is invalid 5523 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5524 * @IWM_STA_KEY_MULTICAST: set for multical key 5525 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5526 */ 5527enum iwm_sta_key_flag { 5528 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5529 IWM_STA_KEY_FLG_WEP = (1 << 0), 5530 IWM_STA_KEY_FLG_CCM = (2 << 0), 5531 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5532 IWM_STA_KEY_FLG_EXT = (4 << 0), 5533 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5534 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5535 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5536 5537 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5538 IWM_STA_KEY_FLG_KEYID_POS = 8, 5539 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5540 IWM_STA_KEY_NOT_VALID = (1 << 11), 5541 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5542 IWM_STA_KEY_MULTICAST = (1 << 14), 5543 IWM_STA_KEY_MFP = (1 << 15), 5544}; 5545 5546/** 5547 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5548 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5549 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5550 * @IWM_STA_MODIFY_TX_RATE: unused 5551 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5552 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5553 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5554 * @IWM_STA_MODIFY_PROT_TH: 5555 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5556 */ 5557enum iwm_sta_modify_flag { 5558 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5559 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5560 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5561 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5562 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5563 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5564 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5565 IWM_STA_MODIFY_QUEUES = (1 << 7), 5566}; 5567 5568#define IWM_STA_MODE_MODIFY 1 5569 5570/** 5571 * enum iwm_sta_sleep_flag - type of sleep of the station 5572 * @IWM_STA_SLEEP_STATE_AWAKE: 5573 * @IWM_STA_SLEEP_STATE_PS_POLL: 5574 * @IWM_STA_SLEEP_STATE_UAPSD: 5575 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5576 * (last) released frame 5577 */ 5578enum iwm_sta_sleep_flag { 5579 IWM_STA_SLEEP_STATE_AWAKE = 0, 5580 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5581 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5582 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5583}; 5584 5585/* STA ID and color bits definitions */ 5586#define IWM_STA_ID_SEED (0x0f) 5587#define IWM_STA_ID_POS (0) 5588#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5589 5590#define IWM_STA_COLOR_SEED (0x7) 5591#define IWM_STA_COLOR_POS (4) 5592#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5593 5594#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5595 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5596#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5597 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5598 5599#define IWM_STA_KEY_MAX_NUM (16) 5600#define IWM_STA_KEY_IDX_INVALID (0xff) 5601#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5602#define IWM_MAX_GLOBAL_KEYS (4) 5603#define IWM_STA_KEY_LEN_WEP40 (5) 5604#define IWM_STA_KEY_LEN_WEP104 (13) 5605 5606/** 5607 * struct iwm_mvm_keyinfo - key information 5608 * @key_flags: type %iwm_sta_key_flag 5609 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5610 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5611 * @key_offset: key offset in the fw's key table 5612 * @key: 16-byte unicast decryption key 5613 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5614 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5615 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5616 */ 5617struct iwm_mvm_keyinfo { 5618 uint16_t key_flags; 5619 uint8_t tkip_rx_tsc_byte2; 5620 uint8_t reserved1; 5621 uint16_t tkip_rx_ttak[5]; 5622 uint8_t key_offset; 5623 uint8_t reserved2; 5624 uint8_t key[16]; 5625 uint64_t tx_secur_seq_cnt; 5626 uint64_t hw_tkip_mic_rx_key; 5627 uint64_t hw_tkip_mic_tx_key; 5628} __packed; 5629 5630#define IWM_ADD_STA_STATUS_MASK 0xFF 5631#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5632#define IWM_ADD_STA_BAID_MASK 0x7F00 5633#define IWM_ADD_STA_BAID_SHIFT 8 5634 5635/** 5636 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5637 * ( REPLY_ADD_STA = 0x18 ) 5638 * @add_modify: 1: modify existing, 0: add new station 5639 * @awake_acs: 5640 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5641 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5642 * @mac_id_n_color: the Mac context this station belongs to 5643 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5644 * @sta_id: index of station in uCode's station table 5645 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5646 * alone. 1 - modify, 0 - don't change. 5647 * @station_flags: look at %iwm_sta_flags 5648 * @station_flags_msk: what of %station_flags have changed 5649 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5650 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5651 * add_immediate_ba_ssn. 5652 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5653 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5654 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5655 * add_immediate_ba_tid. 5656 * @sleep_tx_count: number of packets to transmit to station even though it is 5657 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5658 * keeps track of STA sleep state. 5659 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5660 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5661 * mac-addr. 5662 * @beamform_flags: beam forming controls 5663 * @tfd_queue_msk: tfd queues used by this station 5664 * 5665 * The device contains an internal table of per-station information, with info 5666 * on security keys, aggregation parameters, and Tx rates for initial Tx 5667 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5668 * 5669 * ADD_STA sets up the table entry for one station, either creating a new 5670 * entry, or modifying a pre-existing one. 5671 */ 5672struct iwm_mvm_add_sta_cmd { 5673 uint8_t add_modify; 5674 uint8_t awake_acs; 5675 uint16_t tid_disable_tx; 5676 uint32_t mac_id_n_color; 5677 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5678 uint16_t reserved2; 5679 uint8_t sta_id; 5680 uint8_t modify_mask; 5681 uint16_t reserved3; 5682 uint32_t station_flags; 5683 uint32_t station_flags_msk; 5684 uint8_t add_immediate_ba_tid; 5685 uint8_t remove_immediate_ba_tid; 5686 uint16_t add_immediate_ba_ssn; 5687 uint16_t sleep_tx_count; 5688 uint16_t sleep_state_flags; 5689 uint16_t assoc_id; 5690 uint16_t beamform_flags; 5691 uint32_t tfd_queue_msk; 5692} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5693 5694/** 5695 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5696 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5697 * @sta_id: index of station in uCode's station table 5698 * @key_offset: key offset in key storage 5699 * @key_flags: type %iwm_sta_key_flag 5700 * @key: key material data 5701 * @key2: key material data 5702 * @rx_secur_seq_cnt: RX security sequence counter for the key 5703 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5704 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5705 */ 5706struct iwm_mvm_add_sta_key_cmd { 5707 uint8_t sta_id; 5708 uint8_t key_offset; 5709 uint16_t key_flags; 5710 uint8_t key[16]; 5711 uint8_t key2[16]; 5712 uint8_t rx_secur_seq_cnt[16]; 5713 uint8_t tkip_rx_tsc_byte2; 5714 uint8_t reserved; 5715 uint16_t tkip_rx_ttak[5]; 5716} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5717 5718/** 5719 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5720 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5721 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5722 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5723 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5724 * that doesn't exist. 5725 */ 5726enum iwm_mvm_add_sta_rsp_status { 5727 IWM_ADD_STA_SUCCESS = 0x1, 5728 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5729 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5730 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5731}; 5732 5733/** 5734 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5735 * ( IWM_REMOVE_STA = 0x19 ) 5736 * @sta_id: the station id of the station to be removed 5737 */ 5738struct iwm_mvm_rm_sta_cmd { 5739 uint8_t sta_id; 5740 uint8_t reserved[3]; 5741} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5742 5743/** 5744 * struct iwm_mvm_mgmt_mcast_key_cmd 5745 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5746 * @ctrl_flags: %iwm_sta_key_flag 5747 * @IGTK: 5748 * @K1: IGTK master key 5749 * @K2: IGTK sub key 5750 * @sta_id: station ID that support IGTK 5751 * @key_id: 5752 * @receive_seq_cnt: initial RSC/PN needed for replay check 5753 */ 5754struct iwm_mvm_mgmt_mcast_key_cmd { 5755 uint32_t ctrl_flags; 5756 uint8_t IGTK[16]; 5757 uint8_t K1[16]; 5758 uint8_t K2[16]; 5759 uint32_t key_id; 5760 uint32_t sta_id; 5761 uint64_t receive_seq_cnt; 5762} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5763 5764struct iwm_mvm_wep_key { 5765 uint8_t key_index; 5766 uint8_t key_offset; 5767 uint16_t reserved1; 5768 uint8_t key_size; 5769 uint8_t reserved2[3]; 5770 uint8_t key[16]; 5771} __packed; 5772 5773struct iwm_mvm_wep_key_cmd { 5774 uint32_t mac_id_n_color; 5775 uint8_t num_keys; 5776 uint8_t decryption_type; 5777 uint8_t flags; 5778 uint8_t reserved; 5779 struct iwm_mvm_wep_key wep_key[0]; 5780} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5781 5782/* 5783 * END mvm/fw-api-sta.h 5784 */ 5785 5786/* 5787 * BT coex 5788 */ 5789 5790enum iwm_bt_coex_mode { 5791 IWM_BT_COEX_DISABLE = 0x0, 5792 IWM_BT_COEX_NW = 0x1, 5793 IWM_BT_COEX_BT = 0x2, 5794 IWM_BT_COEX_WIFI = 0x3, 5795}; /* BT_COEX_MODES_E */ 5796 5797enum iwm_bt_coex_enabled_modules { 5798 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5799 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5800 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5801 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5802 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5803}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5804 5805/** 5806 * struct iwm_bt_coex_cmd - bt coex configuration command 5807 * @mode: enum %iwm_bt_coex_mode 5808 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5809 * 5810 * The structure is used for the BT_COEX command. 5811 */ 5812struct iwm_bt_coex_cmd { 5813 uint32_t mode; 5814 uint32_t enabled_modules; 5815} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5816 5817 5818/* 5819 * Location Aware Regulatory (LAR) API - MCC updates 5820 */ 5821 5822/** 5823 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5824 * regulatory profile according to the given MCC (Mobile Country Code). 5825 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5826 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5827 * MCC in the cmd response will be the relevant MCC in the NVM. 5828 * @mcc: given mobile country code 5829 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5830 * @reserved: reserved for alignment 5831 */ 5832struct iwm_mcc_update_cmd_v1 { 5833 uint16_t mcc; 5834 uint8_t source_id; 5835 uint8_t reserved; 5836} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5837 5838/** 5839 * struct iwm_mcc_update_cmd - Request the device to update geographic 5840 * regulatory profile according to the given MCC (Mobile Country Code). 5841 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5842 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5843 * MCC in the cmd response will be the relevant MCC in the NVM. 5844 * @mcc: given mobile country code 5845 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5846 * @reserved: reserved for alignment 5847 * @key: integrity key for MCC API OEM testing 5848 * @reserved2: reserved 5849 */ 5850struct iwm_mcc_update_cmd { 5851 uint16_t mcc; 5852 uint8_t source_id; 5853 uint8_t reserved; 5854 uint32_t key; 5855 uint32_t reserved2[5]; 5856} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5857 5858/** 5859 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5860 * Contains the new channel control profile map, if changed, and the new MCC 5861 * (mobile country code). 5862 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5863 * @status: see &enum iwm_mcc_update_status 5864 * @mcc: the new applied MCC 5865 * @cap: capabilities for all channels which matches the MCC 5866 * @source_id: the MCC source, see iwm_mcc_source 5867 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5868 * channels, depending on platform) 5869 * @channels: channel control data map, DWORD for each channel. Only the first 5870 * 16bits are used. 5871 */ 5872struct iwm_mcc_update_resp_v1 { 5873 uint32_t status; 5874 uint16_t mcc; 5875 uint8_t cap; 5876 uint8_t source_id; 5877 uint32_t n_channels; 5878 uint32_t channels[0]; 5879} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5880 5881/** 5882 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5883 * Contains the new channel control profile map, if changed, and the new MCC 5884 * (mobile country code). 5885 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5886 * @status: see &enum iwm_mcc_update_status 5887 * @mcc: the new applied MCC 5888 * @cap: capabilities for all channels which matches the MCC 5889 * @source_id: the MCC source, see iwm_mcc_source 5890 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5891 * @reserved: reserved. 5892 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5893 * channels, depending on platform) 5894 * @channels: channel control data map, DWORD for each channel. Only the first 5895 * 16bits are used. 5896 */ 5897struct iwm_mcc_update_resp { 5898 uint32_t status; 5899 uint16_t mcc; 5900 uint8_t cap; 5901 uint8_t source_id; 5902 uint16_t time; 5903 uint16_t reserved; 5904 uint32_t n_channels; 5905 uint32_t channels[0]; 5906} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5907 5908/** 5909 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5910 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5911 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5912 * the cellular and connectivity cores that gets updates of the mcc, and 5913 * notifies the ucode directly of any mcc change. 5914 * The ucode requests the driver to request the device to update geographic 5915 * regulatory profile according to the given MCC (Mobile Country Code). 5916 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5917 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5918 * MCC in the cmd response will be the relevant MCC in the NVM. 5919 * @mcc: given mobile country code 5920 * @source_id: identity of the change originator, see iwm_mcc_source 5921 * @reserved1: reserved for alignment 5922 */ 5923struct iwm_mcc_chub_notif { 5924 uint16_t mcc; 5925 uint8_t source_id; 5926 uint8_t reserved1; 5927} __packed; /* LAR_MCC_NOTIFY_S */ 5928 5929enum iwm_mcc_update_status { 5930 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5931 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5932 IWM_MCC_RESP_INVALID, 5933 IWM_MCC_RESP_NVM_DISABLED, 5934 IWM_MCC_RESP_ILLEGAL, 5935 IWM_MCC_RESP_LOW_PRIORITY, 5936 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5937 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5938 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5939}; 5940 5941enum iwm_mcc_source { 5942 IWM_MCC_SOURCE_OLD_FW = 0, 5943 IWM_MCC_SOURCE_ME = 1, 5944 IWM_MCC_SOURCE_BIOS = 2, 5945 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5946 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5947 IWM_MCC_SOURCE_WIFI = 5, 5948 IWM_MCC_SOURCE_RESERVED = 6, 5949 IWM_MCC_SOURCE_DEFAULT = 7, 5950 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5951 IWM_MCC_SOURCE_MCC_API = 9, 5952 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5953 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5954}; 5955 5956/** 5957 * struct iwm_dts_measurement_notif_v1 - measurements notification 5958 * 5959 * @temp: the measured temperature 5960 * @voltage: the measured voltage 5961 */ 5962struct iwm_dts_measurement_notif_v1 { 5963 int32_t temp; 5964 int32_t voltage; 5965} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5966 5967/** 5968 * struct iwm_dts_measurement_notif_v2 - measurements notification 5969 * 5970 * @temp: the measured temperature 5971 * @voltage: the measured voltage 5972 * @threshold_idx: the trip index that was crossed 5973 */ 5974struct iwm_dts_measurement_notif_v2 { 5975 int32_t temp; 5976 int32_t voltage; 5977 int32_t threshold_idx; 5978} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5979 5980/* 5981 * Some cherry-picked definitions 5982 */ 5983 5984#define IWM_FRAME_LIMIT 64 5985 5986/* 5987 * These functions retrieve specific information from the id field in 5988 * the iwm_host_cmd struct which contains the command id, the group id, 5989 * and the version of the command and vice versa. 5990*/ 5991static inline uint8_t 5992iwm_cmd_opcode(uint32_t cmdid) 5993{ 5994 return cmdid & 0xff; 5995} 5996 5997static inline uint8_t 5998iwm_cmd_groupid(uint32_t cmdid) 5999{ 6000 return ((cmdid & 0xff00) >> 8); 6001} 6002 6003static inline uint8_t 6004iwm_cmd_version(uint32_t cmdid) 6005{ 6006 return ((cmdid & 0xff0000) >> 16); 6007} 6008 6009static inline uint32_t 6010iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6011{ 6012 return opcode + (groupid << 8) + (version << 16); 6013} 6014 6015/* make uint16_t wide id out of uint8_t group and opcode */ 6016#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6017 6018/* due to the conversion, this group is special */ 6019#define IWM_ALWAYS_LONG_GROUP 1 6020 6021struct iwm_cmd_header { 6022 uint8_t code; 6023 uint8_t flags; 6024 uint8_t idx; 6025 uint8_t qid; 6026} __packed; 6027 6028struct iwm_cmd_header_wide { 6029 uint8_t opcode; 6030 uint8_t group_id; 6031 uint8_t idx; 6032 uint8_t qid; 6033 uint16_t length; 6034 uint8_t reserved; 6035 uint8_t version; 6036} __packed; 6037 6038/** 6039 * enum iwm_power_scheme 6040 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6041 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6042 * @IWM_POWER_LEVEL_LP - Low Power 6043 */ 6044enum iwm_power_scheme { 6045 IWM_POWER_SCHEME_CAM = 1, 6046 IWM_POWER_SCHEME_BPS, 6047 IWM_POWER_SCHEME_LP 6048}; 6049 6050#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6051#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6052#define IWM_CMD_FAILED_MSK 0x40 6053 6054/** 6055 * struct iwm_device_cmd 6056 * 6057 * For allocation of the command and tx queues, this establishes the overall 6058 * size of the largest command we send to uCode, except for commands that 6059 * aren't fully copied and use other TFD space. 6060 */ 6061struct iwm_device_cmd { 6062 union { 6063 struct { 6064 struct iwm_cmd_header hdr; 6065 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6066 }; 6067 struct { 6068 struct iwm_cmd_header_wide hdr_wide; 6069 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6070 sizeof(struct iwm_cmd_header_wide) + 6071 sizeof(struct iwm_cmd_header)]; 6072 }; 6073 }; 6074} __packed; 6075 6076struct iwm_rx_packet { 6077 /* 6078 * The first 4 bytes of the RX frame header contain both the RX frame 6079 * size and some flags. 6080 * Bit fields: 6081 * 31: flag flush RB request 6082 * 30: flag ignore TC (terminal counter) request 6083 * 29: flag fast IRQ request 6084 * 28-14: Reserved 6085 * 13-00: RX frame size 6086 */ 6087 uint32_t len_n_flags; 6088 struct iwm_cmd_header hdr; 6089 uint8_t data[]; 6090} __packed; 6091 6092#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6093#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6094#define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6095 6096static inline uint32_t 6097iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6098{ 6099 6100 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6101} 6102 6103static inline uint32_t 6104iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6105{ 6106 6107 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6108} 6109 6110 6111#define IWM_MIN_DBM -100 6112#define IWM_MAX_DBM -33 /* realistic guess */ 6113 6114#define IWM_READ(sc, reg) \ 6115 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6116 6117#define IWM_WRITE(sc, reg, val) \ 6118 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6119 6120#define IWM_WRITE_1(sc, reg, val) \ 6121 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6122 6123#define IWM_SETBITS(sc, reg, mask) \ 6124 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6125 6126#define IWM_CLRBITS(sc, reg, mask) \ 6127 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6128 6129#define IWM_BARRIER_WRITE(sc) \ 6130 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6131 BUS_SPACE_BARRIER_WRITE) 6132 6133#define IWM_BARRIER_READ_WRITE(sc) \ 6134 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6135 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6136 6137#endif /* __IF_IWM_REG_H__ */ 6138