if_iwmreg.h revision 330183
1/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2/* $FreeBSD: stable/11/sys/dev/iwm/if_iwmreg.h 330183 2018-03-01 06:13:01Z eadler $ */ 3 4/****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66#ifndef __IF_IWM_REG_H__ 67#define __IF_IWM_REG_H__ 68 69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72/* 73 * BEGIN iwl-csr.h 74 */ 75 76/* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101#define IWM_CSR_GP_CNTRL (0x024) 102 103/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104#define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106/* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114#define IWM_CSR_HW_REV (0x028) 115 116/* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122#define IWM_CSR_EEPROM_REG (0x02c) 123#define IWM_CSR_EEPROM_GP (0x030) 124#define IWM_CSR_OTP_GP_REG (0x034) 125 126#define IWM_CSR_GIO_REG (0x03C) 127#define IWM_CSR_GP_UCODE_REG (0x048) 128#define IWM_CSR_GP_DRIVER_REG (0x050) 129 130/* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139#define IWM_CSR_MBOX_SET_REG (0x088) 140#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142#define IWM_CSR_LED_REG (0x094) 143#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147/* GIO Chicken Bits (PCI Express bus link power management) */ 148#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150/* Analog phase-lock-loop configuration */ 151#define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153/* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161#define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233/* GPIO */ 234#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238/* RESET */ 239#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246/* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296/* HW REV */ 297#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300/** 301 * hw_rev values 302 */ 303enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307}; 308 309 310#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329/* EEPROM REG */ 330#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335/* EEPROM GP */ 336#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343/* One-time-programmable memory general purpose reg */ 344#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349/* GP REG */ 350#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357/* CSR GIO */ 358#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360/* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394/* GP Driver */ 395#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404/* GIO Chicken Bits (PCI Express bus link power management) */ 405#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408/* LED */ 409#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410#define IWM_CSR_LED_REG_TURN_ON (0x60) 411#define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413/* ANA_PLL */ 414#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416/* HPET MEM debug */ 417#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419/* DRAM INT TABLE */ 420#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424/* SECURE boot registers */ 425#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429}; 430 431#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439}; 440 441#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442#define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 443enum iwm_secure_load_status_reg { 444 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 445 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 446 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 447 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 448 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 449}; 450#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 451 452#define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 453#define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 454#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 455#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 456 457#define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 458#define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 459#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 460#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 461 462#define IWM_CSR_SECURE_TIME_OUT (100) 463 464/* extended range in FW SRAM */ 465#define IWM_FW_MEM_EXTENDED_START 0x40000 466#define IWM_FW_MEM_EXTENDED_END 0x57FFF 467 468/* FW chicken bits */ 469#define IWM_LMPM_CHICK 0xa01ff8 470#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 471 472#define IWM_FH_TCSR_0_REG0 (0x1D00) 473 474/* 475 * HBUS (Host-side Bus) 476 * 477 * HBUS registers are mapped directly into PCI bus space, but are used 478 * to indirectly access device's internal memory or registers that 479 * may be powered-down. 480 * 481 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 482 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 483 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 484 * internal resources. 485 * 486 * Do not use iwl_write32()/iwl_read32() family to access these registers; 487 * these provide only simple PCI bus access, without waking up the MAC. 488 */ 489#define IWM_HBUS_BASE (0x400) 490 491/* 492 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 493 * structures, error log, event log, verifying uCode load). 494 * First write to address register, then read from or write to data register 495 * to complete the job. Once the address register is set up, accesses to 496 * data registers auto-increment the address by one dword. 497 * Bit usage for address registers (read or write): 498 * 0-31: memory address within device 499 */ 500#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 501#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 502#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 503#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 504 505/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 506#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 507#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 508 509/* 510 * Registers for accessing device's internal peripheral registers 511 * (e.g. SCD, BSM, etc.). First write to address register, 512 * then read from or write to data register to complete the job. 513 * Bit usage for address registers (read or write): 514 * 0-15: register address (offset) within device 515 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 516 */ 517#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 518#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 519#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 520#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 521 522/* enable the ID buf for read */ 523#define IWM_WFPM_PS_CTL_CLR 0xa0300c 524#define IWM_WFMP_MAC_ADDR_0 0xa03080 525#define IWM_WFMP_MAC_ADDR_1 0xa03084 526#define IWM_LMPM_PMG_EN 0xa01cec 527#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 528#define IWM_RFIC_REG_RD 0xad0470 529#define IWM_WFPM_CTRL_REG 0xa03030 530#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 531#define IWM_ENABLE_WFPM 0x80000000 532 533#define IWM_AUX_MISC_REG 0xa200b0 534#define IWM_HW_STEP_LOCATION_BITS 24 535 536#define IWM_AUX_MISC_MASTER1_EN 0xa20818 537#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 538#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 539#define IWM_RSA_ENABLE 0xa24b08 540#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 541#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 542#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 543#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 544#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 545#define IWM_SB_CPU_1_STATUS 0xa01e30 546#define IWM_SB_CPU_2_STATUS 0Xa01e34 547 548/* Used to enable DBGM */ 549#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 550 551/* 552 * Per-Tx-queue write pointer (index, really!) 553 * Indicates index to next TFD that driver will fill (1 past latest filled). 554 * Bit usage: 555 * 0-7: queue write index 556 * 11-8: queue selector 557 */ 558#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 559 560/********************************************************** 561 * CSR values 562 **********************************************************/ 563 /* 564 * host interrupt timeout value 565 * used with setting interrupt coalescing timer 566 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 567 * 568 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 569 */ 570#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 571#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 572#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 573#define IWM_HOST_INT_OPER_MODE (1 << 31) 574 575/***************************************************************************** 576 * 7000/3000 series SHR DTS addresses * 577 *****************************************************************************/ 578 579/* Diode Results Register Structure: */ 580enum iwm_dtd_diode_reg { 581 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 582 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 583 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 584 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 585 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 586 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 587/* Those are the masks INSIDE the flags bit-field: */ 588 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 589 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 590 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 591 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 592}; 593 594/* 595 * END iwl-csr.h 596 */ 597 598/* 599 * BEGIN iwl-fw.h 600 */ 601 602/** 603 * enum iwm_ucode_tlv_flag - ucode API flags 604 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 605 * was a separate TLV but moved here to save space. 606 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 607 * treats good CRC threshold as a boolean 608 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 609 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 610 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 611 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 612 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 613 * offload profile config command. 614 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 615 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 616 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 617 * (rather than two) IPv6 addresses 618 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 619 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 620 * from the probe request template. 621 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 622 * connection when going back to D0 623 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 624 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 625 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 626 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 627 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 628 * containing CAM (Continuous Active Mode) indication. 629 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 630 * single bound interface). 631 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 632 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 633 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 634 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 635 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 636 * 637 */ 638enum iwm_ucode_tlv_flag { 639 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 640 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 641 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 642 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 643 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 644 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 645 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 646 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 647 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 648 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 649 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 650 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 651 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 652 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 653 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 654 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 655 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 656 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 657 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 658 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 659 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 660 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 661 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 662 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 663 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 664 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 665 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 666 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 667}; 668 669#define IWM_UCODE_TLV_FLAG_BITS \ 670 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 671Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 672L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 673P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 674 675/** 676 * enum iwm_ucode_tlv_api - ucode api 677 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 678 * longer than the passive one, which is essential for fragmented scan. 679 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 680 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 681 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 682 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 683 * instead of 3. 684 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 685 * (command version 3) that supports per-chain limits 686 * 687 * @IWM_NUM_UCODE_TLV_API: number of bits used 688 */ 689enum iwm_ucode_tlv_api { 690 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 691 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 692 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 693 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 694 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 695 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 696 697 IWM_NUM_UCODE_TLV_API = 32 698}; 699 700#define IWM_UCODE_TLV_API_BITS \ 701 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 702 703/** 704 * enum iwm_ucode_tlv_capa - ucode capabilities 705 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 706 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 707 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 708 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 709 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 710 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 711 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 712 * tx power value into TPC Report action frame and Link Measurement Report 713 * action frame 714 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 715 * channel in DS parameter set element in probe requests. 716 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 717 * probe requests. 718 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 719 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 720 * which also implies support for the scheduler configuration command 721 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 722 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 723 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 724 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 725 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 726 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 727 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 728 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 729 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 730 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 731 * sources for the MCC. This TLV bit is a future replacement to 732 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 733 * is supported. 734 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 735 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 736 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 737 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 738 * 0=no support) 739 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 740 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 741 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 742 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 743 * antenna the beacon should be transmitted 744 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 745 * from AP and will send it upon d0i3 exit. 746 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 747 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 748 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 749 * thresholds reporting 750 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 751 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 752 * regular image. 753 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 754 * memory addresses from the firmware. 755 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 756 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 757 * 0=no support) 758 * 759 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 760 */ 761enum iwm_ucode_tlv_capa { 762 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 763 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 764 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 765 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 766 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 767 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 768 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 769 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 770 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 771 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 772 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 773 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 774 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 775 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 776 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 777 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 778 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 779 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 780 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 781 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 782 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 783 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 784 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 785 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 786 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 787 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 788 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 789 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 790 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 791 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 792 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 793 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 794 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 795 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 796 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 797 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 798 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 799 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 800 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 801 802 IWM_NUM_UCODE_TLV_CAPA = 128 803}; 804 805/* The default calibrate table size if not specified by firmware file */ 806#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 807#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 808#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 809 810/* The default max probe length if not specified by the firmware file */ 811#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 812 813/* 814 * enumeration of ucode section. 815 * This enumeration is used directly for older firmware (before 16.0). 816 * For new firmware, there can be up to 4 sections (see below) but the 817 * first one packaged into the firmware file is the DATA section and 818 * some debugging code accesses that. 819 */ 820enum iwm_ucode_sec { 821 IWM_UCODE_SECTION_DATA, 822 IWM_UCODE_SECTION_INST, 823}; 824/* 825 * For 16.0 uCode and above, there is no differentiation between sections, 826 * just an offset to the HW address. 827 */ 828#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 829#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 830 831/* uCode version contains 4 values: Major/Minor/API/Serial */ 832#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 833#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 834#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 835#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 836 837/* 838 * Calibration control struct. 839 * Sent as part of the phy configuration command. 840 * @flow_trigger: bitmap for which calibrations to perform according to 841 * flow triggers. 842 * @event_trigger: bitmap for which calibrations to perform according to 843 * event triggers. 844 */ 845struct iwm_tlv_calib_ctrl { 846 uint32_t flow_trigger; 847 uint32_t event_trigger; 848} __packed; 849 850enum iwm_fw_phy_cfg { 851 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 852 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 853 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 854 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 855 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 856 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 857 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 858 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 859 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 860 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 861}; 862 863#define IWM_UCODE_MAX_CS 1 864 865/** 866 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 867 * @cipher: a cipher suite selector 868 * @flags: cipher scheme flags (currently reserved for a future use) 869 * @hdr_len: a size of MPDU security header 870 * @pn_len: a size of PN 871 * @pn_off: an offset of pn from the beginning of the security header 872 * @key_idx_off: an offset of key index byte in the security header 873 * @key_idx_mask: a bit mask of key_idx bits 874 * @key_idx_shift: bit shift needed to get key_idx 875 * @mic_len: mic length in bytes 876 * @hw_cipher: a HW cipher index used in host commands 877 */ 878struct iwm_fw_cipher_scheme { 879 uint32_t cipher; 880 uint8_t flags; 881 uint8_t hdr_len; 882 uint8_t pn_len; 883 uint8_t pn_off; 884 uint8_t key_idx_off; 885 uint8_t key_idx_mask; 886 uint8_t key_idx_shift; 887 uint8_t mic_len; 888 uint8_t hw_cipher; 889} __packed; 890 891/* 892 * Block paging calculations 893 */ 894#define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */ 895#define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */ 896#define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3 897/* 8 pages per group */ 898#define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE) 899/* don't change, support only 32KB size */ 900#define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE) 901/* 32K == 2^15 */ 902#define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE) 903 904/* 905 * Image paging calculations 906 */ 907#define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5 908/* 2^5 == 32 blocks per image */ 909#define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE) 910/* maximum image size 1024KB */ 911#define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE) 912 913/** 914 * struct iwm_fw_cscheme_list - a cipher scheme list 915 * @size: a number of entries 916 * @cs: cipher scheme entries 917 */ 918struct iwm_fw_cscheme_list { 919 uint8_t size; 920 struct iwm_fw_cipher_scheme cs[]; 921} __packed; 922 923/* 924 * END iwl-fw.h 925 */ 926 927/* 928 * BEGIN iwl-fw-file.h 929 */ 930 931/* v1/v2 uCode file layout */ 932struct iwm_ucode_header { 933 uint32_t ver; /* major/minor/API/serial */ 934 union { 935 struct { 936 uint32_t inst_size; /* bytes of runtime code */ 937 uint32_t data_size; /* bytes of runtime data */ 938 uint32_t init_size; /* bytes of init code */ 939 uint32_t init_data_size; /* bytes of init data */ 940 uint32_t boot_size; /* bytes of bootstrap code */ 941 uint8_t data[0]; /* in same order as sizes */ 942 } v1; 943 struct { 944 uint32_t build; /* build number */ 945 uint32_t inst_size; /* bytes of runtime code */ 946 uint32_t data_size; /* bytes of runtime data */ 947 uint32_t init_size; /* bytes of init code */ 948 uint32_t init_data_size; /* bytes of init data */ 949 uint32_t boot_size; /* bytes of bootstrap code */ 950 uint8_t data[0]; /* in same order as sizes */ 951 } v2; 952 } u; 953}; 954 955/* 956 * new TLV uCode file layout 957 * 958 * The new TLV file format contains TLVs, that each specify 959 * some piece of data. 960 */ 961 962enum iwm_ucode_tlv_type { 963 IWM_UCODE_TLV_INVALID = 0, /* unused */ 964 IWM_UCODE_TLV_INST = 1, 965 IWM_UCODE_TLV_DATA = 2, 966 IWM_UCODE_TLV_INIT = 3, 967 IWM_UCODE_TLV_INIT_DATA = 4, 968 IWM_UCODE_TLV_BOOT = 5, 969 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 970 IWM_UCODE_TLV_PAN = 7, 971 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 972 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 973 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 974 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 975 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 976 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 977 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 978 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 979 IWM_UCODE_TLV_WOWLAN_INST = 16, 980 IWM_UCODE_TLV_WOWLAN_DATA = 17, 981 IWM_UCODE_TLV_FLAGS = 18, 982 IWM_UCODE_TLV_SEC_RT = 19, 983 IWM_UCODE_TLV_SEC_INIT = 20, 984 IWM_UCODE_TLV_SEC_WOWLAN = 21, 985 IWM_UCODE_TLV_DEF_CALIB = 22, 986 IWM_UCODE_TLV_PHY_SKU = 23, 987 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 988 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 989 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 990 IWM_UCODE_TLV_NUM_OF_CPU = 27, 991 IWM_UCODE_TLV_CSCHEME = 28, 992 993 /* 994 * Following two are not in our base tag, but allow 995 * handling ucode version 9. 996 */ 997 IWM_UCODE_TLV_API_CHANGES_SET = 29, 998 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 999 1000 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 1001 IWM_UCODE_TLV_PAGING = 32, 1002 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 1003 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 1004 IWM_UCODE_TLV_FW_VERSION = 36, 1005 IWM_UCODE_TLV_FW_DBG_DEST = 38, 1006 IWM_UCODE_TLV_FW_DBG_CONF = 39, 1007 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 1008 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 1009 IWM_UCODE_TLV_FW_MEM_SEG = 51, 1010}; 1011 1012struct iwm_ucode_tlv { 1013 uint32_t type; /* see above */ 1014 uint32_t length; /* not including type/length fields */ 1015 uint8_t data[0]; 1016}; 1017 1018struct iwm_ucode_api { 1019 uint32_t api_index; 1020 uint32_t api_flags; 1021} __packed; 1022 1023struct iwm_ucode_capa { 1024 uint32_t api_index; 1025 uint32_t api_capa; 1026} __packed; 1027 1028#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 1029 1030struct iwm_tlv_ucode_header { 1031 /* 1032 * The TLV style ucode header is distinguished from 1033 * the v1/v2 style header by first four bytes being 1034 * zero, as such is an invalid combination of 1035 * major/minor/API/serial versions. 1036 */ 1037 uint32_t zero; 1038 uint32_t magic; 1039 uint8_t human_readable[64]; 1040 uint32_t ver; /* major/minor/API/serial */ 1041 uint32_t build; 1042 uint64_t ignore; 1043 /* 1044 * The data contained herein has a TLV layout, 1045 * see above for the TLV header and types. 1046 * Note that each TLV is padded to a length 1047 * that is a multiple of 4 for alignment. 1048 */ 1049 uint8_t data[0]; 1050}; 1051 1052/* 1053 * END iwl-fw-file.h 1054 */ 1055 1056/* 1057 * BEGIN iwl-prph.h 1058 */ 1059 1060/* 1061 * Registers in this file are internal, not PCI bus memory mapped. 1062 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1063 */ 1064#define IWM_PRPH_BASE (0x00000) 1065#define IWM_PRPH_END (0xFFFFF) 1066 1067/* APMG (power management) constants */ 1068#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1069#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1070#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1071#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1072#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1073#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1074#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1075#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1076#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1077#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1078#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1079 1080#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1081#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1082#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1083 1084#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1085#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1086#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1087#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1088#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1089#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1090#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1091 1092#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1093 1094#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1095 1096/* Device system time */ 1097#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1098 1099/* Device NMI register */ 1100#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1101#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1102#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1103#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1104#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1105 1106/* 1107 * Device reset for family 8000 1108 * write to bit 24 in order to reset the CPU 1109 */ 1110#define IWM_RELEASE_CPU_RESET 0x300c 1111#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1112 1113 1114/***************************************************************************** 1115 * 7000/3000 series SHR DTS addresses * 1116 *****************************************************************************/ 1117 1118#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1119#define IWM_DTSC_CFG_MODE (0x00a10604) 1120#define IWM_DTSC_VREF_AVG (0x00a10648) 1121#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1122#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1123#define IWM_DTSC_PTAT_AVG (0x00a10650) 1124 1125 1126/** 1127 * Tx Scheduler 1128 * 1129 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1130 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1131 * host DRAM. It steers each frame's Tx command (which contains the frame 1132 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1133 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1134 * but one DMA channel may take input from several queues. 1135 * 1136 * Tx DMA FIFOs have dedicated purposes. 1137 * 1138 * For 5000 series and up, they are used differently 1139 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1140 * 1141 * 0 -- EDCA BK (background) frames, lowest priority 1142 * 1 -- EDCA BE (best effort) frames, normal priority 1143 * 2 -- EDCA VI (video) frames, higher priority 1144 * 3 -- EDCA VO (voice) and management frames, highest priority 1145 * 4 -- unused 1146 * 5 -- unused 1147 * 6 -- unused 1148 * 7 -- Commands 1149 * 1150 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1151 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1152 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1153 * 1154 * The driver sets up each queue to work in one of two modes: 1155 * 1156 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1157 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1158 * contains TFDs for a unique combination of Recipient Address (RA) 1159 * and Traffic Identifier (TID), that is, traffic of a given 1160 * Quality-Of-Service (QOS) priority, destined for a single station. 1161 * 1162 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1163 * each frame within the BA window, including whether it's been transmitted, 1164 * and whether it's been acknowledged by the receiving station. The device 1165 * automatically processes block-acks received from the receiving STA, 1166 * and reschedules un-acked frames to be retransmitted (successful 1167 * Tx completion may end up being out-of-order). 1168 * 1169 * The driver must maintain the queue's Byte Count table in host DRAM 1170 * for this mode. 1171 * This mode does not support fragmentation. 1172 * 1173 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1174 * The device may automatically retry Tx, but will retry only one frame 1175 * at a time, until receiving ACK from receiving station, or reaching 1176 * retry limit and giving up. 1177 * 1178 * The command queue (#4/#9) must use this mode! 1179 * This mode does not require use of the Byte Count table in host DRAM. 1180 * 1181 * Driver controls scheduler operation via 3 means: 1182 * 1) Scheduler registers 1183 * 2) Shared scheduler data base in internal SRAM 1184 * 3) Shared data in host DRAM 1185 * 1186 * Initialization: 1187 * 1188 * When loading, driver should allocate memory for: 1189 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1190 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1191 * (1024 bytes for each queue). 1192 * 1193 * After receiving "Alive" response from uCode, driver must initialize 1194 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1195 * the driver can't issue commands!): 1196 */ 1197#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1198 1199/** 1200 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1201 * can keep track of at one time when creating block-ack chains of frames. 1202 * Note that "64" matches the number of ack bits in a block-ack packet. 1203 */ 1204#define IWM_SCD_WIN_SIZE 64 1205#define IWM_SCD_FRAME_LIMIT 64 1206 1207#define IWM_SCD_TXFIFO_POS_TID (0) 1208#define IWM_SCD_TXFIFO_POS_RA (4) 1209#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1210 1211/* agn SCD */ 1212#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1213#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1214#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1215#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1216#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1217 1218#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1219#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1220#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1221#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1222#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1223#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1224#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1225#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1226#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1227#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1228 1229/* Context Data */ 1230#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1231#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1232 1233/* Tx status */ 1234#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1235#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1236 1237/* Translation Data */ 1238#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1239#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1240 1241#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1242 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1243 1244#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1245 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1246 1247#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1248 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1249 1250#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1251 1252#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1253#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1254#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1255#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1256#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1257#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1258#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1259#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1260#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1261#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1262#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1263 1264static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1265{ 1266 if (chnl < 20) 1267 return IWM_SCD_BASE + 0x18 + chnl * 4; 1268 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1269} 1270 1271static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1272{ 1273 if (chnl < 20) 1274 return IWM_SCD_BASE + 0x68 + chnl * 4; 1275 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1276} 1277 1278static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1279{ 1280 if (chnl < 20) 1281 return IWM_SCD_BASE + 0x10c + chnl * 4; 1282 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1283} 1284 1285/*********************** END TX SCHEDULER *************************************/ 1286 1287/* Oscillator clock */ 1288#define IWM_OSC_CLK (0xa04068) 1289#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1290 1291/* 1292 * END iwl-prph.h 1293 */ 1294 1295/* 1296 * BEGIN iwl-fh.h 1297 */ 1298 1299/****************************/ 1300/* Flow Handler Definitions */ 1301/****************************/ 1302 1303/** 1304 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1305 * Addresses are offsets from device's PCI hardware base address. 1306 */ 1307#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1308#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1309 1310/** 1311 * Keep-Warm (KW) buffer base address. 1312 * 1313 * Driver must allocate a 4KByte buffer that is for keeping the 1314 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1315 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1316 * from going into a power-savings mode that would cause higher DRAM latency, 1317 * and possible data over/under-runs, before all Tx/Rx is complete. 1318 * 1319 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1320 * of the buffer, which must be 4K aligned. Once this is set up, the device 1321 * automatically invokes keep-warm accesses when normal accesses might not 1322 * be sufficient to maintain fast DRAM response. 1323 * 1324 * Bit fields: 1325 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1326 */ 1327#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1328 1329 1330/** 1331 * TFD Circular Buffers Base (CBBC) addresses 1332 * 1333 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1334 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1335 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1336 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1337 * aligned (address bits 0-7 must be 0). 1338 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1339 * for them are in different places. 1340 * 1341 * Bit fields in each pointer register: 1342 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1343 */ 1344#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1345#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1346#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1347#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1348#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1349#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1350 1351/* Find TFD CB base pointer for given queue */ 1352static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1353{ 1354 if (chnl < 16) 1355 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1356 if (chnl < 20) 1357 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1358 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1359} 1360 1361 1362/** 1363 * Rx SRAM Control and Status Registers (RSCSR) 1364 * 1365 * These registers provide handshake between driver and device for the Rx queue 1366 * (this queue handles *all* command responses, notifications, Rx data, etc. 1367 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1368 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1369 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1370 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1371 * mapping between RBDs and RBs. 1372 * 1373 * Driver must allocate host DRAM memory for the following, and set the 1374 * physical address of each into device registers: 1375 * 1376 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1377 * entries (although any power of 2, up to 4096, is selectable by driver). 1378 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1379 * (typically 4K, although 8K or 16K are also selectable by driver). 1380 * Driver sets up RB size and number of RBDs in the CB via Rx config 1381 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1382 * 1383 * Bit fields within one RBD: 1384 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1385 * 1386 * Driver sets physical address [35:8] of base of RBD circular buffer 1387 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1388 * 1389 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1390 * (RBs) have been filled, via a "write pointer", actually the index of 1391 * the RB's corresponding RBD within the circular buffer. Driver sets 1392 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1393 * 1394 * Bit fields in lower dword of Rx status buffer (upper dword not used 1395 * by driver: 1396 * 31-12: Not used by driver 1397 * 11- 0: Index of last filled Rx buffer descriptor 1398 * (device writes, driver reads this value) 1399 * 1400 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1401 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1402 * and update the device's "write" index register, 1403 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1404 * 1405 * This "write" index corresponds to the *next* RBD that the driver will make 1406 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1407 * the circular buffer. This value should initially be 0 (before preparing any 1408 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1409 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1410 * "read" index has advanced past 1! See below). 1411 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1412 * 1413 * As the device fills RBs (referenced from contiguous RBDs within the circular 1414 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1415 * to tell the driver the index of the latest filled RBD. The driver must 1416 * read this "read" index from DRAM after receiving an Rx interrupt from device 1417 * 1418 * The driver must also internally keep track of a third index, which is the 1419 * next RBD to process. When receiving an Rx interrupt, driver should process 1420 * all filled but unprocessed RBs up to, but not including, the RB 1421 * corresponding to the "read" index. For example, if "read" index becomes "1", 1422 * driver may process the RB pointed to by RBD 0. Depending on volume of 1423 * traffic, there may be many RBs to process. 1424 * 1425 * If read index == write index, device thinks there is no room to put new data. 1426 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1427 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1428 * and "read" indexes; that is, make sure that there are no more than 254 1429 * buffers waiting to be filled. 1430 */ 1431#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1432#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1433#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1434 1435/** 1436 * Physical base address of 8-byte Rx Status buffer. 1437 * Bit fields: 1438 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1439 */ 1440#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1441 1442/** 1443 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1444 * Bit fields: 1445 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1446 */ 1447#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1448 1449/** 1450 * Rx write pointer (index, really!). 1451 * Bit fields: 1452 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1453 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1454 */ 1455#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1456#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1457 1458#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1459#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1460 1461/** 1462 * Rx Config/Status Registers (RCSR) 1463 * Rx Config Reg for channel 0 (only channel used) 1464 * 1465 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1466 * normal operation (see bit fields). 1467 * 1468 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1469 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1470 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1471 * 1472 * Bit fields: 1473 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1474 * '10' operate normally 1475 * 29-24: reserved 1476 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1477 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1478 * 19-18: reserved 1479 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1480 * '10' 12K, '11' 16K. 1481 * 15-14: reserved 1482 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1483 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1484 * typical value 0x10 (about 1/2 msec) 1485 * 3- 0: reserved 1486 */ 1487#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1488#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1489#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1490 1491#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1492#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1493#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1494 1495#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1496#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1497#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1498#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1499#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1500#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1501 1502#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1503#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1504#define IWM_RX_RB_TIMEOUT (0x11) 1505 1506#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1507#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1508#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1509 1510#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1511#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1512#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1513#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1514 1515#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1516#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1517#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1518 1519/** 1520 * Rx Shared Status Registers (RSSR) 1521 * 1522 * After stopping Rx DMA channel (writing 0 to 1523 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1524 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1525 * 1526 * Bit fields: 1527 * 24: 1 = Channel 0 is idle 1528 * 1529 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1530 * contain default values that should not be altered by the driver. 1531 */ 1532#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1533#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1534 1535#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1536#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1537#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1538 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1539 1540#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1541 1542#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1543 1544/* TFDB Area - TFDs buffer table */ 1545#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1546#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1547#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1548#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1549#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1550 1551/** 1552 * Transmit DMA Channel Control/Status Registers (TCSR) 1553 * 1554 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1555 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1556 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1557 * 1558 * To use a Tx DMA channel, driver must initialize its 1559 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1560 * 1561 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1562 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1563 * 1564 * All other bits should be 0. 1565 * 1566 * Bit fields: 1567 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1568 * '10' operate normally 1569 * 29- 4: Reserved, set to "0" 1570 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1571 * 2- 0: Reserved, set to "0" 1572 */ 1573#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1574#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1575 1576/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1577#define IWM_FH_TCSR_CHNL_NUM (8) 1578 1579/* TCSR: tx_config register values */ 1580#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1581 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1582#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1583 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1584#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1585 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1586 1587#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1588#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1589 1590#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1591#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1592 1593#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1594#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1595#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1596 1597#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1598#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1599#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1600 1601#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1602#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1603#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1604 1605#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1606#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1607#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1608 1609#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1610#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1611 1612/** 1613 * Tx Shared Status Registers (TSSR) 1614 * 1615 * After stopping Tx DMA channel (writing 0 to 1616 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1617 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1618 * (channel's buffers empty | no pending requests). 1619 * 1620 * Bit fields: 1621 * 31-24: 1 = Channel buffers empty (channel 7:0) 1622 * 23-16: 1 = No pending requests (channel 7:0) 1623 */ 1624#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1625#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1626 1627#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1628 1629/** 1630 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1631 * 31: Indicates an address error when accessed to internal memory 1632 * uCode/driver must write "1" in order to clear this flag 1633 * 30: Indicates that Host did not send the expected number of dwords to FH 1634 * uCode/driver must write "1" in order to clear this flag 1635 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1636 * command was received from the scheduler while the TRB was already full 1637 * with previous command 1638 * uCode/driver must write "1" in order to clear this flag 1639 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1640 * bit is set, it indicates that the FH has received a full indication 1641 * from the RTC TxFIFO and the current value of the TxCredit counter was 1642 * not equal to zero. This mean that the credit mechanism was not 1643 * synchronized to the TxFIFO status 1644 * uCode/driver must write "1" in order to clear this flag 1645 */ 1646#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1647#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1648 1649#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1650 1651/* Tx service channels */ 1652#define IWM_FH_SRVC_CHNL (9) 1653#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1654#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1655#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1656 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1657 1658#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1659#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1660 (_chan) * 4) 1661 1662/* Instruct FH to increment the retry count of a packet when 1663 * it is brought from the memory to TX-FIFO 1664 */ 1665#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1666 1667#define IWM_RX_QUEUE_SIZE 256 1668#define IWM_RX_QUEUE_MASK 255 1669#define IWM_RX_QUEUE_SIZE_LOG 8 1670 1671/* 1672 * RX related structures and functions 1673 */ 1674#define IWM_RX_FREE_BUFFERS 64 1675#define IWM_RX_LOW_WATERMARK 8 1676 1677/** 1678 * struct iwm_rb_status - reseve buffer status 1679 * host memory mapped FH registers 1680 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1681 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1682 * @finished_rb_num [0:11] - Indicates the index of the current RB 1683 * in which the last frame was written to 1684 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1685 * which was transferred 1686 */ 1687struct iwm_rb_status { 1688 uint16_t closed_rb_num; 1689 uint16_t closed_fr_num; 1690 uint16_t finished_rb_num; 1691 uint16_t finished_fr_nam; 1692 uint32_t unused; 1693} __packed; 1694 1695 1696#define IWM_TFD_QUEUE_SIZE_MAX (256) 1697#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1698#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1699 IWM_TFD_QUEUE_SIZE_BC_DUP) 1700#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1701#define IWM_NUM_OF_TBS 20 1702 1703static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1704{ 1705 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1706} 1707/** 1708 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1709 * 1710 * This structure contains dma address and length of transmission address 1711 * 1712 * @lo: low [31:0] portion of the dma address of TX buffer 1713 * every even is unaligned on 16 bit boundary 1714 * @hi_n_len 0-3 [35:32] portion of dma 1715 * 4-15 length of the tx buffer 1716 */ 1717struct iwm_tfd_tb { 1718 uint32_t lo; 1719 uint16_t hi_n_len; 1720} __packed; 1721 1722/** 1723 * struct iwm_tfd 1724 * 1725 * Transmit Frame Descriptor (TFD) 1726 * 1727 * @ __reserved1[3] reserved 1728 * @ num_tbs 0-4 number of active tbs 1729 * 5 reserved 1730 * 6-7 padding (not used) 1731 * @ tbs[20] transmit frame buffer descriptors 1732 * @ __pad padding 1733 * 1734 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1735 * Both driver and device share these circular buffers, each of which must be 1736 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1737 * 1738 * Driver must indicate the physical address of the base of each 1739 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1740 * 1741 * Each TFD contains pointer/size information for up to 20 data buffers 1742 * in host DRAM. These buffers collectively contain the (one) frame described 1743 * by the TFD. Each buffer must be a single contiguous block of memory within 1744 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1745 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1746 * Tx frame, up to 8 KBytes in size. 1747 * 1748 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1749 */ 1750struct iwm_tfd { 1751 uint8_t __reserved1[3]; 1752 uint8_t num_tbs; 1753 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1754 uint32_t __pad; 1755} __packed; 1756 1757/* Keep Warm Size */ 1758#define IWM_KW_SIZE 0x1000 /* 4k */ 1759 1760/* Fixed (non-configurable) rx data from phy */ 1761 1762/** 1763 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1764 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1765 * @tfd_offset 0-12 - tx command byte count 1766 * 12-16 - station index 1767 */ 1768struct iwm_agn_scd_bc_tbl { 1769 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1770} __packed; 1771 1772/* 1773 * END iwl-fh.h 1774 */ 1775 1776/* 1777 * BEGIN mvm/fw-api.h 1778 */ 1779 1780/* Maximum number of Tx queues. */ 1781#define IWM_MVM_MAX_QUEUES 31 1782 1783/* Tx queue numbers */ 1784enum { 1785 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1786 IWM_MVM_CMD_QUEUE = 9, 1787 IWM_MVM_AUX_QUEUE = 15, 1788}; 1789 1790enum iwm_mvm_tx_fifo { 1791 IWM_MVM_TX_FIFO_BK = 0, 1792 IWM_MVM_TX_FIFO_BE, 1793 IWM_MVM_TX_FIFO_VI, 1794 IWM_MVM_TX_FIFO_VO, 1795 IWM_MVM_TX_FIFO_MCAST = 5, 1796 IWM_MVM_TX_FIFO_CMD = 7, 1797}; 1798 1799#define IWM_MVM_STATION_COUNT 16 1800 1801/* commands */ 1802enum { 1803 IWM_MVM_ALIVE = 0x1, 1804 IWM_REPLY_ERROR = 0x2, 1805 1806 IWM_INIT_COMPLETE_NOTIF = 0x4, 1807 1808 /* PHY context commands */ 1809 IWM_PHY_CONTEXT_CMD = 0x8, 1810 IWM_DBG_CFG = 0x9, 1811 1812 /* UMAC scan commands */ 1813 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1814 IWM_SCAN_CFG_CMD = 0xc, 1815 IWM_SCAN_REQ_UMAC = 0xd, 1816 IWM_SCAN_ABORT_UMAC = 0xe, 1817 IWM_SCAN_COMPLETE_UMAC = 0xf, 1818 1819 /* station table */ 1820 IWM_ADD_STA_KEY = 0x17, 1821 IWM_ADD_STA = 0x18, 1822 IWM_REMOVE_STA = 0x19, 1823 1824 /* TX */ 1825 IWM_TX_CMD = 0x1c, 1826 IWM_TXPATH_FLUSH = 0x1e, 1827 IWM_MGMT_MCAST_KEY = 0x1f, 1828 1829 /* scheduler config */ 1830 IWM_SCD_QUEUE_CFG = 0x1d, 1831 1832 /* global key */ 1833 IWM_WEP_KEY = 0x20, 1834 1835 /* MAC and Binding commands */ 1836 IWM_MAC_CONTEXT_CMD = 0x28, 1837 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1838 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1839 IWM_BINDING_CONTEXT_CMD = 0x2b, 1840 IWM_TIME_QUOTA_CMD = 0x2c, 1841 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1842 1843 IWM_LQ_CMD = 0x4e, 1844 1845 /* Calibration */ 1846 IWM_TEMPERATURE_NOTIFICATION = 0x62, 1847 IWM_CALIBRATION_CFG_CMD = 0x65, 1848 IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1849 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1850 IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1851 1852 /* Scan offload */ 1853 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1854 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1855 IWM_HOT_SPOT_CMD = 0x53, 1856 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1857 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1858 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1859 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1860 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1861 1862 /* Phy */ 1863 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1864 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1865 /* IWM_PHY_DB_CMD = 0x6c, */ 1866 1867 /* Power - legacy power table command */ 1868 IWM_POWER_TABLE_CMD = 0x77, 1869 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1870 1871 /* Thermal Throttling*/ 1872 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1873 1874 /* Scanning */ 1875 IWM_SCAN_ABORT_CMD = 0x81, 1876 IWM_SCAN_START_NOTIFICATION = 0x82, 1877 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1878 1879 /* NVM */ 1880 IWM_NVM_ACCESS_CMD = 0x88, 1881 1882 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1883 1884 IWM_BEACON_NOTIFICATION = 0x90, 1885 IWM_BEACON_TEMPLATE_CMD = 0x91, 1886 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1887 IWM_BT_CONFIG = 0x9b, 1888 IWM_STATISTICS_NOTIFICATION = 0x9d, 1889 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1890 1891 /* RF-KILL commands and notifications */ 1892 IWM_CARD_STATE_CMD = 0xa0, 1893 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1894 1895 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1896 1897 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1898 1899 /* Power - new power table command */ 1900 IWM_MAC_PM_POWER_TABLE = 0xa9, 1901 1902 IWM_REPLY_RX_PHY_CMD = 0xc0, 1903 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1904 IWM_BA_NOTIF = 0xc5, 1905 1906 /* Location Aware Regulatory */ 1907 IWM_MCC_UPDATE_CMD = 0xc8, 1908 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1909 1910 /* BT Coex */ 1911 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1912 IWM_BT_COEX_PROT_ENV = 0xcd, 1913 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1914 IWM_BT_COEX_CI = 0x5d, 1915 1916 IWM_REPLY_SF_CFG_CMD = 0xd1, 1917 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1918 1919 /* DTS measurements */ 1920 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1921 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1922 1923 IWM_REPLY_DEBUG_CMD = 0xf0, 1924 IWM_DEBUG_LOG_MSG = 0xf7, 1925 1926 IWM_MCAST_FILTER_CMD = 0xd0, 1927 1928 /* D3 commands/notifications */ 1929 IWM_D3_CONFIG_CMD = 0xd3, 1930 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1931 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1932 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1933 1934 /* for WoWLAN in particular */ 1935 IWM_WOWLAN_PATTERNS = 0xe0, 1936 IWM_WOWLAN_CONFIGURATION = 0xe1, 1937 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1938 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1939 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1940 IWM_WOWLAN_GET_STATUSES = 0xe5, 1941 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1942 1943 /* and for NetDetect */ 1944 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1945 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1946 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1947 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1948 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1949 1950 IWM_REPLY_MAX = 0xff, 1951}; 1952 1953enum iwm_phy_ops_subcmd_ids { 1954 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1955 IWM_CTDP_CONFIG_CMD = 0x03, 1956 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1957 IWM_CT_KILL_NOTIFICATION = 0xFE, 1958 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1959}; 1960 1961/* command groups */ 1962enum { 1963 IWM_LEGACY_GROUP = 0x0, 1964 IWM_LONG_GROUP = 0x1, 1965 IWM_SYSTEM_GROUP = 0x2, 1966 IWM_MAC_CONF_GROUP = 0x3, 1967 IWM_PHY_OPS_GROUP = 0x4, 1968 IWM_DATA_PATH_GROUP = 0x5, 1969 IWM_PROT_OFFLOAD_GROUP = 0xb, 1970}; 1971 1972/** 1973 * struct iwm_cmd_response - generic response struct for most commands 1974 * @status: status of the command asked, changes for each one 1975 */ 1976struct iwm_cmd_response { 1977 uint32_t status; 1978}; 1979 1980/* 1981 * struct iwm_tx_ant_cfg_cmd 1982 * @valid: valid antenna configuration 1983 */ 1984struct iwm_tx_ant_cfg_cmd { 1985 uint32_t valid; 1986} __packed; 1987 1988/** 1989 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1990 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1991 * @flags: (reserved for future implementation) 1992 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1993 * @pwr_restriction: TX power restriction in dBms. 1994 */ 1995struct iwm_reduce_tx_power_cmd { 1996 uint8_t flags; 1997 uint8_t mac_context_id; 1998 uint16_t pwr_restriction; 1999} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 2000 2001/* 2002 * Calibration control struct. 2003 * Sent as part of the phy configuration command. 2004 * @flow_trigger: bitmap for which calibrations to perform according to 2005 * flow triggers. 2006 * @event_trigger: bitmap for which calibrations to perform according to 2007 * event triggers. 2008 */ 2009struct iwm_calib_ctrl { 2010 uint32_t flow_trigger; 2011 uint32_t event_trigger; 2012} __packed; 2013 2014/* This enum defines the bitmap of various calibrations to enable in both 2015 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 2016 */ 2017enum iwm_calib_cfg { 2018 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 2019 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 2020 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 2021 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 2022 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 2023 IWM_CALIB_CFG_DC_IDX = (1 << 5), 2024 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 2025 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 2026 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 2027 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 2028 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 2029 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 2030 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 2031 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 2032 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 2033 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 2034 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 2035 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 2036 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 2037}; 2038 2039/* 2040 * Phy configuration command. 2041 */ 2042struct iwm_phy_cfg_cmd { 2043 uint32_t phy_cfg; 2044 struct iwm_calib_ctrl calib_control; 2045} __packed; 2046 2047#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2048#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2049#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2050#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2051#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2052#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2053#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2054#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2055#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2056#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2057 2058 2059/* Target of the IWM_NVM_ACCESS_CMD */ 2060enum { 2061 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2062 IWM_NVM_ACCESS_TARGET_OTP = 1, 2063 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2064}; 2065 2066/* Section types for IWM_NVM_ACCESS_CMD */ 2067enum { 2068 IWM_NVM_SECTION_TYPE_SW = 1, 2069 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2070 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2071 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2072 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2073 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2074 IWM_NVM_MAX_NUM_SECTIONS = 13, 2075}; 2076 2077/** 2078 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2079 * @op_code: 0 - read, 1 - write 2080 * @target: IWM_NVM_ACCESS_TARGET_* 2081 * @type: IWM_NVM_SECTION_TYPE_* 2082 * @offset: offset in bytes into the section 2083 * @length: in bytes, to read/write 2084 * @data: if write operation, the data to write. On read its empty 2085 */ 2086struct iwm_nvm_access_cmd { 2087 uint8_t op_code; 2088 uint8_t target; 2089 uint16_t type; 2090 uint16_t offset; 2091 uint16_t length; 2092 uint8_t data[]; 2093} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2094 2095/** 2096 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2097 * @offset: offset in bytes into the section 2098 * @length: in bytes, either how much was written or read 2099 * @type: IWM_NVM_SECTION_TYPE_* 2100 * @status: 0 for success, fail otherwise 2101 * @data: if read operation, the data returned. Empty on write. 2102 */ 2103struct iwm_nvm_access_resp { 2104 uint16_t offset; 2105 uint16_t length; 2106 uint16_t type; 2107 uint16_t status; 2108 uint8_t data[]; 2109} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2110 2111/* IWM_MVM_ALIVE 0x1 */ 2112 2113/* alive response is_valid values */ 2114#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2115#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2116 2117/* alive response ver_type values */ 2118enum { 2119 IWM_FW_TYPE_HW = 0, 2120 IWM_FW_TYPE_PROT = 1, 2121 IWM_FW_TYPE_AP = 2, 2122 IWM_FW_TYPE_WOWLAN = 3, 2123 IWM_FW_TYPE_TIMING = 4, 2124 IWM_FW_TYPE_WIPAN = 5 2125}; 2126 2127/* alive response ver_subtype values */ 2128enum { 2129 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2130 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2131 IWM_FW_SUBTYPE_REDUCED = 2, 2132 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2133 IWM_FW_SUBTYPE_WOWLAN = 4, 2134 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2135 IWM_FW_SUBTYPE_WIPAN = 6, 2136 IWM_FW_SUBTYPE_INITIALIZE = 9 2137}; 2138 2139#define IWM_ALIVE_STATUS_ERR 0xDEAD 2140#define IWM_ALIVE_STATUS_OK 0xCAFE 2141 2142#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2143 2144struct iwm_mvm_alive_resp_ver1 { 2145 uint16_t status; 2146 uint16_t flags; 2147 uint8_t ucode_minor; 2148 uint8_t ucode_major; 2149 uint16_t id; 2150 uint8_t api_minor; 2151 uint8_t api_major; 2152 uint8_t ver_subtype; 2153 uint8_t ver_type; 2154 uint8_t mac; 2155 uint8_t opt; 2156 uint16_t reserved2; 2157 uint32_t timestamp; 2158 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2159 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2160 uint32_t cpu_register_ptr; 2161 uint32_t dbgm_config_ptr; 2162 uint32_t alive_counter_ptr; 2163 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2164} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2165 2166struct iwm_mvm_alive_resp_ver2 { 2167 uint16_t status; 2168 uint16_t flags; 2169 uint8_t ucode_minor; 2170 uint8_t ucode_major; 2171 uint16_t id; 2172 uint8_t api_minor; 2173 uint8_t api_major; 2174 uint8_t ver_subtype; 2175 uint8_t ver_type; 2176 uint8_t mac; 2177 uint8_t opt; 2178 uint16_t reserved2; 2179 uint32_t timestamp; 2180 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2181 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2182 uint32_t cpu_register_ptr; 2183 uint32_t dbgm_config_ptr; 2184 uint32_t alive_counter_ptr; 2185 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2186 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2187 uint32_t st_fwrd_size; 2188 uint8_t umac_minor; /* UMAC version: minor */ 2189 uint8_t umac_major; /* UMAC version: major */ 2190 uint16_t umac_id; /* UMAC version: id */ 2191 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2192 uint32_t dbg_print_buff_addr; 2193} __packed; /* ALIVE_RES_API_S_VER_2 */ 2194 2195struct iwm_mvm_alive_resp { 2196 uint16_t status; 2197 uint16_t flags; 2198 uint32_t ucode_minor; 2199 uint32_t ucode_major; 2200 uint8_t ver_subtype; 2201 uint8_t ver_type; 2202 uint8_t mac; 2203 uint8_t opt; 2204 uint32_t timestamp; 2205 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2206 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2207 uint32_t cpu_register_ptr; 2208 uint32_t dbgm_config_ptr; 2209 uint32_t alive_counter_ptr; 2210 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2211 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2212 uint32_t st_fwrd_size; 2213 uint32_t umac_minor; /* UMAC version: minor */ 2214 uint32_t umac_major; /* UMAC version: major */ 2215 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2216 uint32_t dbg_print_buff_addr; 2217} __packed; /* ALIVE_RES_API_S_VER_3 */ 2218 2219/* Error response/notification */ 2220enum { 2221 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2222 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2223 IWM_FW_ERR_SERVICE = 0x2, 2224 IWM_FW_ERR_ARC_MEMORY = 0x3, 2225 IWM_FW_ERR_ARC_CODE = 0x4, 2226 IWM_FW_ERR_WATCH_DOG = 0x5, 2227 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2228 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2229 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2230 IWM_FW_ERR_UNEXPECTED = 0xFE, 2231 IWM_FW_ERR_FATAL = 0xFF 2232}; 2233 2234/** 2235 * struct iwm_error_resp - FW error indication 2236 * ( IWM_REPLY_ERROR = 0x2 ) 2237 * @error_type: one of IWM_FW_ERR_* 2238 * @cmd_id: the command ID for which the error occurred 2239 * @bad_cmd_seq_num: sequence number of the erroneous command 2240 * @error_service: which service created the error, applicable only if 2241 * error_type = 2, otherwise 0 2242 * @timestamp: TSF in usecs. 2243 */ 2244struct iwm_error_resp { 2245 uint32_t error_type; 2246 uint8_t cmd_id; 2247 uint8_t reserved1; 2248 uint16_t bad_cmd_seq_num; 2249 uint32_t error_service; 2250 uint64_t timestamp; 2251} __packed; 2252 2253 2254/* Common PHY, MAC and Bindings definitions */ 2255 2256#define IWM_MAX_MACS_IN_BINDING (3) 2257#define IWM_MAX_BINDINGS (4) 2258#define IWM_AUX_BINDING_INDEX (3) 2259#define IWM_MAX_PHYS (4) 2260 2261/* Used to extract ID and color from the context dword */ 2262#define IWM_FW_CTXT_ID_POS (0) 2263#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2264#define IWM_FW_CTXT_COLOR_POS (8) 2265#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2266#define IWM_FW_CTXT_INVALID (0xffffffff) 2267 2268#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2269 (_color << IWM_FW_CTXT_COLOR_POS)) 2270 2271/* Possible actions on PHYs, MACs and Bindings */ 2272enum { 2273 IWM_FW_CTXT_ACTION_STUB = 0, 2274 IWM_FW_CTXT_ACTION_ADD, 2275 IWM_FW_CTXT_ACTION_MODIFY, 2276 IWM_FW_CTXT_ACTION_REMOVE, 2277 IWM_FW_CTXT_ACTION_NUM 2278}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2279 2280/* Time Events */ 2281 2282/* Time Event types, according to MAC type */ 2283enum iwm_time_event_type { 2284 /* BSS Station Events */ 2285 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2286 IWM_TE_BSS_STA_ASSOC, 2287 IWM_TE_BSS_EAP_DHCP_PROT, 2288 IWM_TE_BSS_QUIET_PERIOD, 2289 2290 /* P2P Device Events */ 2291 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2292 IWM_TE_P2P_DEVICE_LISTEN, 2293 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2294 IWM_TE_P2P_DEVICE_FULL_SCAN, 2295 2296 /* P2P Client Events */ 2297 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2298 IWM_TE_P2P_CLIENT_ASSOC, 2299 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2300 2301 /* P2P GO Events */ 2302 IWM_TE_P2P_GO_ASSOC_PROT, 2303 IWM_TE_P2P_GO_REPETITIVE_NOA, 2304 IWM_TE_P2P_GO_CT_WINDOW, 2305 2306 /* WiDi Sync Events */ 2307 IWM_TE_WIDI_TX_SYNC, 2308 2309 IWM_TE_MAX 2310}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2311 2312 2313 2314/* Time event - defines for command API v1 */ 2315 2316/* 2317 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2318 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2319 * the first fragment is scheduled. 2320 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2321 * the first 2 fragments are scheduled. 2322 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2323 * number of fragments are valid. 2324 * 2325 * Other than the constant defined above, specifying a fragmentation value 'x' 2326 * means that the event can be fragmented but only the first 'x' will be 2327 * scheduled. 2328 */ 2329enum { 2330 IWM_TE_V1_FRAG_NONE = 0, 2331 IWM_TE_V1_FRAG_SINGLE = 1, 2332 IWM_TE_V1_FRAG_DUAL = 2, 2333 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2334}; 2335 2336/* If a Time Event can be fragmented, this is the max number of fragments */ 2337#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2338/* Repeat the time event endlessly (until removed) */ 2339#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2340/* If a Time Event has bounded repetitions, this is the maximal value */ 2341#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2342 2343/* Time Event dependencies: none, on another TE, or in a specific time */ 2344enum { 2345 IWM_TE_V1_INDEPENDENT = 0, 2346 IWM_TE_V1_DEP_OTHER = (1 << 0), 2347 IWM_TE_V1_DEP_TSF = (1 << 1), 2348 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2349}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2350 2351/* 2352 * @IWM_TE_V1_NOTIF_NONE: no notifications 2353 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2354 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2355 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2356 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2357 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2358 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2359 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2360 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2361 * 2362 * Supported Time event notifications configuration. 2363 * A notification (both event and fragment) includes a status indicating weather 2364 * the FW was able to schedule the event or not. For fragment start/end 2365 * notification the status is always success. There is no start/end fragment 2366 * notification for monolithic events. 2367 */ 2368enum { 2369 IWM_TE_V1_NOTIF_NONE = 0, 2370 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2371 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2372 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2373 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2374 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2375 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2376 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2377 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2378 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2379}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2380 2381 2382/** 2383 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2384 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2385 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2386 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2387 * @id_and_color: ID and color of the relevant MAC 2388 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2389 * @id: this field has two meanings, depending on the action: 2390 * If the action is ADD, then it means the type of event to add. 2391 * For all other actions it is the unique event ID assigned when the 2392 * event was added by the FW. 2393 * @apply_time: When to start the Time Event (in GP2) 2394 * @max_delay: maximum delay to event's start (apply time), in TU 2395 * @depends_on: the unique ID of the event we depend on (if any) 2396 * @interval: interval between repetitions, in TU 2397 * @interval_reciprocal: 2^32 / interval 2398 * @duration: duration of event in TU 2399 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2400 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2401 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2402 * @is_present: 0 or 1, are we present or absent during the Time Event 2403 * @max_frags: maximal number of fragments the Time Event can be divided to 2404 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2405 */ 2406struct iwm_time_event_cmd_v1 { 2407 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2408 uint32_t id_and_color; 2409 uint32_t action; 2410 uint32_t id; 2411 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2412 uint32_t apply_time; 2413 uint32_t max_delay; 2414 uint32_t dep_policy; 2415 uint32_t depends_on; 2416 uint32_t is_present; 2417 uint32_t max_frags; 2418 uint32_t interval; 2419 uint32_t interval_reciprocal; 2420 uint32_t duration; 2421 uint32_t repeat; 2422 uint32_t notify; 2423} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2424 2425 2426/* Time event - defines for command API v2 */ 2427 2428/* 2429 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2430 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2431 * the first fragment is scheduled. 2432 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2433 * the first 2 fragments are scheduled. 2434 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2435 * number of fragments are valid. 2436 * 2437 * Other than the constant defined above, specifying a fragmentation value 'x' 2438 * means that the event can be fragmented but only the first 'x' will be 2439 * scheduled. 2440 */ 2441enum { 2442 IWM_TE_V2_FRAG_NONE = 0, 2443 IWM_TE_V2_FRAG_SINGLE = 1, 2444 IWM_TE_V2_FRAG_DUAL = 2, 2445 IWM_TE_V2_FRAG_MAX = 0xfe, 2446 IWM_TE_V2_FRAG_ENDLESS = 0xff 2447}; 2448 2449/* Repeat the time event endlessly (until removed) */ 2450#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2451/* If a Time Event has bounded repetitions, this is the maximal value */ 2452#define IWM_TE_V2_REPEAT_MAX 0xfe 2453 2454#define IWM_TE_V2_PLACEMENT_POS 12 2455#define IWM_TE_V2_ABSENCE_POS 15 2456 2457/* Time event policy values (for time event cmd api v2) 2458 * A notification (both event and fragment) includes a status indicating weather 2459 * the FW was able to schedule the event or not. For fragment start/end 2460 * notification the status is always success. There is no start/end fragment 2461 * notification for monolithic events. 2462 * 2463 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2464 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2465 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2466 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2467 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2468 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2469 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2470 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2471 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2472 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2473 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2474 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2475 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2476 */ 2477enum { 2478 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2479 2480 /* notifications (event start/stop, fragment start/stop) */ 2481 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2482 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2483 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2484 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2485 2486 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2487 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2488 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2489 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2490 2491 IWM_TE_V2_NOTIF_MSK = 0xff, 2492 2493 /* placement characteristics */ 2494 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2495 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2496 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2497 2498 /* are we present or absent during the Time Event. */ 2499 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2500}; 2501 2502/** 2503 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2504 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2505 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2506 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2507 * @id_and_color: ID and color of the relevant MAC 2508 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2509 * @id: this field has two meanings, depending on the action: 2510 * If the action is ADD, then it means the type of event to add. 2511 * For all other actions it is the unique event ID assigned when the 2512 * event was added by the FW. 2513 * @apply_time: When to start the Time Event (in GP2) 2514 * @max_delay: maximum delay to event's start (apply time), in TU 2515 * @depends_on: the unique ID of the event we depend on (if any) 2516 * @interval: interval between repetitions, in TU 2517 * @duration: duration of event in TU 2518 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2519 * @max_frags: maximal number of fragments the Time Event can be divided to 2520 * @policy: defines whether uCode shall notify the host or other uCode modules 2521 * on event and/or fragment start and/or end 2522 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2523 * IWM_TE_EVENT_SOCIOPATHIC 2524 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2525 */ 2526struct iwm_time_event_cmd_v2 { 2527 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2528 uint32_t id_and_color; 2529 uint32_t action; 2530 uint32_t id; 2531 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2532 uint32_t apply_time; 2533 uint32_t max_delay; 2534 uint32_t depends_on; 2535 uint32_t interval; 2536 uint32_t duration; 2537 uint8_t repeat; 2538 uint8_t max_frags; 2539 uint16_t policy; 2540} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2541 2542/** 2543 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2544 * @status: bit 0 indicates success, all others specify errors 2545 * @id: the Time Event type 2546 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2547 * @id_and_color: ID and color of the relevant MAC 2548 */ 2549struct iwm_time_event_resp { 2550 uint32_t status; 2551 uint32_t id; 2552 uint32_t unique_id; 2553 uint32_t id_and_color; 2554} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2555 2556/** 2557 * struct iwm_time_event_notif - notifications of time event start/stop 2558 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2559 * @timestamp: action timestamp in GP2 2560 * @session_id: session's unique id 2561 * @unique_id: unique id of the Time Event itself 2562 * @id_and_color: ID and color of the relevant MAC 2563 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2564 * @status: true if scheduled, false otherwise (not executed) 2565 */ 2566struct iwm_time_event_notif { 2567 uint32_t timestamp; 2568 uint32_t session_id; 2569 uint32_t unique_id; 2570 uint32_t id_and_color; 2571 uint32_t action; 2572 uint32_t status; 2573} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2574 2575 2576/* Bindings and Time Quota */ 2577 2578/** 2579 * struct iwm_binding_cmd - configuring bindings 2580 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2581 * @id_and_color: ID and color of the relevant Binding 2582 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2583 * @macs: array of MAC id and colors which belong to the binding 2584 * @phy: PHY id and color which belongs to the binding 2585 */ 2586struct iwm_binding_cmd { 2587 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2588 uint32_t id_and_color; 2589 uint32_t action; 2590 /* IWM_BINDING_DATA_API_S_VER_1 */ 2591 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2592 uint32_t phy; 2593} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2594 2595/* The maximal number of fragments in the FW's schedule session */ 2596#define IWM_MVM_MAX_QUOTA 128 2597 2598/** 2599 * struct iwm_time_quota_data - configuration of time quota per binding 2600 * @id_and_color: ID and color of the relevant Binding 2601 * @quota: absolute time quota in TU. The scheduler will try to divide the 2602 * remainig quota (after Time Events) according to this quota. 2603 * @max_duration: max uninterrupted context duration in TU 2604 */ 2605struct iwm_time_quota_data { 2606 uint32_t id_and_color; 2607 uint32_t quota; 2608 uint32_t max_duration; 2609} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2610 2611/** 2612 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2613 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2614 * @quotas: allocations per binding 2615 */ 2616struct iwm_time_quota_cmd { 2617 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2618} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2619 2620 2621/* PHY context */ 2622 2623/* Supported bands */ 2624#define IWM_PHY_BAND_5 (0) 2625#define IWM_PHY_BAND_24 (1) 2626 2627/* Supported channel width, vary if there is VHT support */ 2628#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2629#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2630#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2631#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2632 2633/* 2634 * Control channel position: 2635 * For legacy set bit means upper channel, otherwise lower. 2636 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2637 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2638 * center_freq 2639 * | 2640 * 40Mhz |_______|_______| 2641 * 80Mhz |_______|_______|_______|_______| 2642 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2643 * code 011 010 001 000 | 100 101 110 111 2644 */ 2645#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2646#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2647#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2648#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2649#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2650#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2651#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2652#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2653 2654/* 2655 * @band: IWM_PHY_BAND_* 2656 * @channel: channel number 2657 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2658 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2659 */ 2660struct iwm_fw_channel_info { 2661 uint8_t band; 2662 uint8_t channel; 2663 uint8_t width; 2664 uint8_t ctrl_pos; 2665} __packed; 2666 2667#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2668#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2669 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2670#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2671#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2672 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2673#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2674#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2675 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2676#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2677#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2678 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2679#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2680#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2681 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2682#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2683#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2684 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2685#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2686#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2687 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2688 2689/* TODO: fix the value, make it depend on firmware at runtime? */ 2690#define IWM_NUM_PHY_CTX 3 2691 2692/* TODO: complete missing documentation */ 2693/** 2694 * struct iwm_phy_context_cmd - config of the PHY context 2695 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2696 * @id_and_color: ID and color of the relevant Binding 2697 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2698 * @apply_time: 0 means immediate apply and context switch. 2699 * other value means apply new params after X usecs 2700 * @tx_param_color: ??? 2701 * @channel_info: 2702 * @txchain_info: ??? 2703 * @rxchain_info: ??? 2704 * @acquisition_data: ??? 2705 * @dsp_cfg_flags: set to 0 2706 */ 2707struct iwm_phy_context_cmd { 2708 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2709 uint32_t id_and_color; 2710 uint32_t action; 2711 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2712 uint32_t apply_time; 2713 uint32_t tx_param_color; 2714 struct iwm_fw_channel_info ci; 2715 uint32_t txchain_info; 2716 uint32_t rxchain_info; 2717 uint32_t acquisition_data; 2718 uint32_t dsp_cfg_flags; 2719} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2720 2721#define IWM_RX_INFO_PHY_CNT 8 2722#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2723#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2724#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2725#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2726#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2727#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2728#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2729 2730#define IWM_RX_INFO_AGC_IDX 1 2731#define IWM_RX_INFO_RSSI_AB_IDX 2 2732#define IWM_OFDM_AGC_A_MSK 0x0000007f 2733#define IWM_OFDM_AGC_A_POS 0 2734#define IWM_OFDM_AGC_B_MSK 0x00003f80 2735#define IWM_OFDM_AGC_B_POS 7 2736#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2737#define IWM_OFDM_AGC_CODE_POS 20 2738#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2739#define IWM_OFDM_RSSI_A_POS 0 2740#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2741#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2742#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2743#define IWM_OFDM_RSSI_B_POS 16 2744#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2745#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2746 2747/** 2748 * struct iwm_rx_phy_info - phy info 2749 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2750 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2751 * @cfg_phy_cnt: configurable DSP phy data byte count 2752 * @stat_id: configurable DSP phy data set ID 2753 * @reserved1: 2754 * @system_timestamp: GP2 at on air rise 2755 * @timestamp: TSF at on air rise 2756 * @beacon_time_stamp: beacon at on-air rise 2757 * @phy_flags: general phy flags: band, modulation, ... 2758 * @channel: channel number 2759 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2760 * @rate_n_flags: IWM_RATE_MCS_* 2761 * @byte_count: frame's byte-count 2762 * @frame_time: frame's time on the air, based on byte count and frame rate 2763 * calculation 2764 * @mac_active_msk: what MACs were active when the frame was received 2765 * 2766 * Before each Rx, the device sends this data. It contains PHY information 2767 * about the reception of the packet. 2768 */ 2769struct iwm_rx_phy_info { 2770 uint8_t non_cfg_phy_cnt; 2771 uint8_t cfg_phy_cnt; 2772 uint8_t stat_id; 2773 uint8_t reserved1; 2774 uint32_t system_timestamp; 2775 uint64_t timestamp; 2776 uint32_t beacon_time_stamp; 2777 uint16_t phy_flags; 2778#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2779 uint16_t channel; 2780 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2781 uint8_t rate; 2782 uint8_t rflags; 2783 uint16_t xrflags; 2784 uint32_t byte_count; 2785 uint16_t mac_active_msk; 2786 uint16_t frame_time; 2787} __packed; 2788 2789struct iwm_rx_mpdu_res_start { 2790 uint16_t byte_count; 2791 uint16_t reserved; 2792} __packed; 2793 2794/** 2795 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2796 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2797 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2798 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2799 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2800 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2801 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2802 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2803 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2804 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2805 */ 2806enum iwm_rx_phy_flags { 2807 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2808 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2809 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2810 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2811 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2812 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2813 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2814 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2815 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2816 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2817}; 2818 2819/** 2820 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2821 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2822 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2823 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2824 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2825 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2826 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2827 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2828 * in the driver. 2829 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2830 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2831 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2832 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2833 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2834 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2835 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2836 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2837 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2838 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2839 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2840 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2841 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2842 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2843 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2844 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2845 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2846 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2847 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2848 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2849 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2850 */ 2851enum iwm_mvm_rx_status { 2852 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2853 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2854 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2855 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2856 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2857 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2858 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2859 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2860 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2861 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2862 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2863 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2864 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2865 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2866 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2867 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2868 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2869 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2870 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2871 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2872 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2873 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2874 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2875 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2876 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2877 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2878 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2879}; 2880 2881/** 2882 * struct iwm_radio_version_notif - information on the radio version 2883 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2884 * @radio_flavor: 2885 * @radio_step: 2886 * @radio_dash: 2887 */ 2888struct iwm_radio_version_notif { 2889 uint32_t radio_flavor; 2890 uint32_t radio_step; 2891 uint32_t radio_dash; 2892} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2893 2894enum iwm_card_state_flags { 2895 IWM_CARD_ENABLED = 0x00, 2896 IWM_HW_CARD_DISABLED = 0x01, 2897 IWM_SW_CARD_DISABLED = 0x02, 2898 IWM_CT_KILL_CARD_DISABLED = 0x04, 2899 IWM_HALT_CARD_DISABLED = 0x08, 2900 IWM_CARD_DISABLED_MSK = 0x0f, 2901 IWM_CARD_IS_RX_ON = 0x10, 2902}; 2903 2904/** 2905 * struct iwm_radio_version_notif - information on the radio version 2906 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2907 * @flags: %iwm_card_state_flags 2908 */ 2909struct iwm_card_state_notif { 2910 uint32_t flags; 2911} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2912 2913/** 2914 * struct iwm_missed_beacons_notif - information on missed beacons 2915 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2916 * @mac_id: interface ID 2917 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2918 * beacons since last RX. 2919 * @consec_missed_beacons: number of consecutive missed beacons 2920 * @num_expected_beacons: 2921 * @num_recvd_beacons: 2922 */ 2923struct iwm_missed_beacons_notif { 2924 uint32_t mac_id; 2925 uint32_t consec_missed_beacons_since_last_rx; 2926 uint32_t consec_missed_beacons; 2927 uint32_t num_expected_beacons; 2928 uint32_t num_recvd_beacons; 2929} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2930 2931/** 2932 * struct iwm_mfuart_load_notif - mfuart image version & status 2933 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2934 * @installed_ver: installed image version 2935 * @external_ver: external image version 2936 * @status: MFUART loading status 2937 * @duration: MFUART loading time 2938*/ 2939struct iwm_mfuart_load_notif { 2940 uint32_t installed_ver; 2941 uint32_t external_ver; 2942 uint32_t status; 2943 uint32_t duration; 2944} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2945 2946/** 2947 * struct iwm_set_calib_default_cmd - set default value for calibration. 2948 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2949 * @calib_index: the calibration to set value for 2950 * @length: of data 2951 * @data: the value to set for the calibration result 2952 */ 2953struct iwm_set_calib_default_cmd { 2954 uint16_t calib_index; 2955 uint16_t length; 2956 uint8_t data[0]; 2957} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2958 2959#define IWM_MAX_PORT_ID_NUM 2 2960#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2961 2962/** 2963 * struct iwm_mcast_filter_cmd - configure multicast filter. 2964 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2965 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2966 * to identify network interface adopted in host-device IF. 2967 * It is used by FW as index in array of addresses. This array has 2968 * IWM_MAX_PORT_ID_NUM members. 2969 * @count: Number of MAC addresses in the array 2970 * @pass_all: Set 1 to pass all multicast packets. 2971 * @bssid: current association BSSID. 2972 * @addr_list: Place holder for array of MAC addresses. 2973 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2974 */ 2975struct iwm_mcast_filter_cmd { 2976 uint8_t filter_own; 2977 uint8_t port_id; 2978 uint8_t count; 2979 uint8_t pass_all; 2980 uint8_t bssid[6]; 2981 uint8_t reserved[2]; 2982 uint8_t addr_list[0]; 2983} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2984 2985struct iwm_mvm_statistics_dbg { 2986 uint32_t burst_check; 2987 uint32_t burst_count; 2988 uint32_t wait_for_silence_timeout_cnt; 2989 uint32_t reserved[3]; 2990} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2991 2992struct iwm_mvm_statistics_div { 2993 uint32_t tx_on_a; 2994 uint32_t tx_on_b; 2995 uint32_t exec_time; 2996 uint32_t probe_time; 2997 uint32_t rssi_ant; 2998 uint32_t reserved2; 2999} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3000 3001struct iwm_mvm_statistics_general_common { 3002 uint32_t temperature; /* radio temperature */ 3003 uint32_t temperature_m; /* radio voltage */ 3004 struct iwm_mvm_statistics_dbg dbg; 3005 uint32_t sleep_time; 3006 uint32_t slots_out; 3007 uint32_t slots_idle; 3008 uint32_t ttl_timestamp; 3009 struct iwm_mvm_statistics_div div; 3010 uint32_t rx_enable_counter; 3011 /* 3012 * num_of_sos_states: 3013 * count the number of times we have to re-tune 3014 * in order to get out of bad PHY status 3015 */ 3016 uint32_t num_of_sos_states; 3017} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3018 3019struct iwm_mvm_statistics_rx_non_phy { 3020 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3021 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3022 uint32_t non_bssid_frames; /* number of frames with BSSID that 3023 * doesn't belong to the STA BSSID */ 3024 uint32_t filtered_frames; /* count frames that were dumped in the 3025 * filtering process */ 3026 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3027 * our serving channel */ 3028 uint32_t channel_beacons; /* beacons with our bss id and in our 3029 * serving channel */ 3030 uint32_t num_missed_bcon; /* number of missed beacons */ 3031 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3032 * ADC was in saturation */ 3033 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3034 * for INA */ 3035 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3036 uint32_t interference_data_flag; /* flag for interference data 3037 * availability. 1 when data is 3038 * available. */ 3039 uint32_t channel_load; /* counts RX Enable time in uSec */ 3040 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3041 * and CCK) counter */ 3042 uint32_t beacon_rssi_a; 3043 uint32_t beacon_rssi_b; 3044 uint32_t beacon_rssi_c; 3045 uint32_t beacon_energy_a; 3046 uint32_t beacon_energy_b; 3047 uint32_t beacon_energy_c; 3048 uint32_t num_bt_kills; 3049 uint32_t mac_id; 3050 uint32_t directed_data_mpdu; 3051} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3052 3053struct iwm_mvm_statistics_rx_phy { 3054 uint32_t ina_cnt; 3055 uint32_t fina_cnt; 3056 uint32_t plcp_err; 3057 uint32_t crc32_err; 3058 uint32_t overrun_err; 3059 uint32_t early_overrun_err; 3060 uint32_t crc32_good; 3061 uint32_t false_alarm_cnt; 3062 uint32_t fina_sync_err_cnt; 3063 uint32_t sfd_timeout; 3064 uint32_t fina_timeout; 3065 uint32_t unresponded_rts; 3066 uint32_t rxe_frame_limit_overrun; 3067 uint32_t sent_ack_cnt; 3068 uint32_t sent_cts_cnt; 3069 uint32_t sent_ba_rsp_cnt; 3070 uint32_t dsp_self_kill; 3071 uint32_t mh_format_err; 3072 uint32_t re_acq_main_rssi_sum; 3073 uint32_t reserved; 3074} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3075 3076struct iwm_mvm_statistics_rx_ht_phy { 3077 uint32_t plcp_err; 3078 uint32_t overrun_err; 3079 uint32_t early_overrun_err; 3080 uint32_t crc32_good; 3081 uint32_t crc32_err; 3082 uint32_t mh_format_err; 3083 uint32_t agg_crc32_good; 3084 uint32_t agg_mpdu_cnt; 3085 uint32_t agg_cnt; 3086 uint32_t unsupport_mcs; 3087} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3088 3089#define IWM_MAX_CHAINS 3 3090 3091struct iwm_mvm_statistics_tx_non_phy_agg { 3092 uint32_t ba_timeout; 3093 uint32_t ba_reschedule_frames; 3094 uint32_t scd_query_agg_frame_cnt; 3095 uint32_t scd_query_no_agg; 3096 uint32_t scd_query_agg; 3097 uint32_t scd_query_mismatch; 3098 uint32_t frame_not_ready; 3099 uint32_t underrun; 3100 uint32_t bt_prio_kill; 3101 uint32_t rx_ba_rsp_cnt; 3102 int8_t txpower[IWM_MAX_CHAINS]; 3103 int8_t reserved; 3104 uint32_t reserved2; 3105} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3106 3107struct iwm_mvm_statistics_tx_channel_width { 3108 uint32_t ext_cca_narrow_ch20[1]; 3109 uint32_t ext_cca_narrow_ch40[2]; 3110 uint32_t ext_cca_narrow_ch80[3]; 3111 uint32_t ext_cca_narrow_ch160[4]; 3112 uint32_t last_tx_ch_width_indx; 3113 uint32_t rx_detected_per_ch_width[4]; 3114 uint32_t success_per_ch_width[4]; 3115 uint32_t fail_per_ch_width[4]; 3116}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3117 3118struct iwm_mvm_statistics_tx { 3119 uint32_t preamble_cnt; 3120 uint32_t rx_detected_cnt; 3121 uint32_t bt_prio_defer_cnt; 3122 uint32_t bt_prio_kill_cnt; 3123 uint32_t few_bytes_cnt; 3124 uint32_t cts_timeout; 3125 uint32_t ack_timeout; 3126 uint32_t expected_ack_cnt; 3127 uint32_t actual_ack_cnt; 3128 uint32_t dump_msdu_cnt; 3129 uint32_t burst_abort_next_frame_mismatch_cnt; 3130 uint32_t burst_abort_missing_next_frame_cnt; 3131 uint32_t cts_timeout_collision; 3132 uint32_t ack_or_ba_timeout_collision; 3133 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3134 struct iwm_mvm_statistics_tx_channel_width channel_width; 3135} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3136 3137 3138struct iwm_mvm_statistics_bt_activity { 3139 uint32_t hi_priority_tx_req_cnt; 3140 uint32_t hi_priority_tx_denied_cnt; 3141 uint32_t lo_priority_tx_req_cnt; 3142 uint32_t lo_priority_tx_denied_cnt; 3143 uint32_t hi_priority_rx_req_cnt; 3144 uint32_t hi_priority_rx_denied_cnt; 3145 uint32_t lo_priority_rx_req_cnt; 3146 uint32_t lo_priority_rx_denied_cnt; 3147} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3148 3149struct iwm_mvm_statistics_general { 3150 struct iwm_mvm_statistics_general_common common; 3151 uint32_t beacon_filtered; 3152 uint32_t missed_beacons; 3153 int8_t beacon_filter_average_energy; 3154 int8_t beacon_filter_reason; 3155 int8_t beacon_filter_current_energy; 3156 int8_t beacon_filter_reserved; 3157 uint32_t beacon_filter_delta_time; 3158 struct iwm_mvm_statistics_bt_activity bt_activity; 3159} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3160 3161struct iwm_mvm_statistics_rx { 3162 struct iwm_mvm_statistics_rx_phy ofdm; 3163 struct iwm_mvm_statistics_rx_phy cck; 3164 struct iwm_mvm_statistics_rx_non_phy general; 3165 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3166} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3167 3168/* 3169 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3170 * 3171 * By default, uCode issues this notification after receiving a beacon 3172 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3173 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3174 * 3175 * Statistics counters continue to increment beacon after beacon, but are 3176 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3177 * 0x9c with CLEAR_STATS bit set (see above). 3178 * 3179 * uCode also issues this notification during scans. uCode clears statistics 3180 * appropriately so that each notification contains statistics for only the 3181 * one channel that has just been scanned. 3182 */ 3183 3184struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3185 uint32_t flag; 3186 struct iwm_mvm_statistics_rx rx; 3187 struct iwm_mvm_statistics_tx tx; 3188 struct iwm_mvm_statistics_general general; 3189} __packed; 3190 3191/*********************************** 3192 * Smart Fifo API 3193 ***********************************/ 3194/* Smart Fifo state */ 3195enum iwm_sf_state { 3196 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3197 IWM_SF_FULL_ON, 3198 IWM_SF_UNINIT, 3199 IWM_SF_INIT_OFF, 3200 IWM_SF_HW_NUM_STATES 3201}; 3202 3203/* Smart Fifo possible scenario */ 3204enum iwm_sf_scenario { 3205 IWM_SF_SCENARIO_SINGLE_UNICAST, 3206 IWM_SF_SCENARIO_AGG_UNICAST, 3207 IWM_SF_SCENARIO_MULTICAST, 3208 IWM_SF_SCENARIO_BA_RESP, 3209 IWM_SF_SCENARIO_TX_RESP, 3210 IWM_SF_NUM_SCENARIO 3211}; 3212 3213#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3214#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3215 3216/* smart FIFO default values */ 3217#define IWM_SF_W_MARK_SISO 4096 3218#define IWM_SF_W_MARK_MIMO2 8192 3219#define IWM_SF_W_MARK_MIMO3 6144 3220#define IWM_SF_W_MARK_LEGACY 4096 3221#define IWM_SF_W_MARK_SCAN 4096 3222 3223/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3224#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3225#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3226#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3227#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3228#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3229#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3230#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3231#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3232#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3233#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3234 3235/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3236#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3237#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3238#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3239#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3240#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3241#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3242#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3243#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3244#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3245#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3246 3247#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3248 3249#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3250 3251/** 3252 * Smart Fifo configuration command. 3253 * @state: smart fifo state, types listed in iwm_sf_state. 3254 * @watermark: Minimum allowed available free space in RXF for transient state. 3255 * @long_delay_timeouts: aging and idle timer values for each scenario 3256 * in long delay state. 3257 * @full_on_timeouts: timer values for each scenario in full on state. 3258 */ 3259struct iwm_sf_cfg_cmd { 3260 uint32_t state; 3261 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3262 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3263 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3264} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3265 3266/* 3267 * END mvm/fw-api.h 3268 */ 3269 3270/* 3271 * BEGIN mvm/fw-api-mac.h 3272 */ 3273 3274/* 3275 * The first MAC indices (starting from 0) 3276 * are available to the driver, AUX follows 3277 */ 3278#define IWM_MAC_INDEX_AUX 4 3279#define IWM_MAC_INDEX_MIN_DRIVER 0 3280#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3281 3282enum iwm_ac { 3283 IWM_AC_BK, 3284 IWM_AC_BE, 3285 IWM_AC_VI, 3286 IWM_AC_VO, 3287 IWM_AC_NUM, 3288}; 3289 3290/** 3291 * enum iwm_mac_protection_flags - MAC context flags 3292 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3293 * this will require CCK RTS/CTS2self. 3294 * RTS/CTS will protect full burst time. 3295 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3296 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3297 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3298 */ 3299enum iwm_mac_protection_flags { 3300 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3301 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3302 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3303 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3304}; 3305 3306#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3307#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3308 3309/** 3310 * enum iwm_mac_types - Supported MAC types 3311 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3312 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3313 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3314 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3315 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3316 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3317 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3318 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3319 * @IWM_FW_MAC_TYPE_GO: P2P GO 3320 * @IWM_FW_MAC_TYPE_TEST: ? 3321 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3322 */ 3323enum iwm_mac_types { 3324 IWM_FW_MAC_TYPE_FIRST = 1, 3325 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3326 IWM_FW_MAC_TYPE_LISTENER, 3327 IWM_FW_MAC_TYPE_PIBSS, 3328 IWM_FW_MAC_TYPE_IBSS, 3329 IWM_FW_MAC_TYPE_BSS_STA, 3330 IWM_FW_MAC_TYPE_P2P_DEVICE, 3331 IWM_FW_MAC_TYPE_P2P_STA, 3332 IWM_FW_MAC_TYPE_GO, 3333 IWM_FW_MAC_TYPE_TEST, 3334 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3335}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3336 3337/** 3338 * enum iwm_tsf_id - TSF hw timer ID 3339 * @IWM_TSF_ID_A: use TSF A 3340 * @IWM_TSF_ID_B: use TSF B 3341 * @IWM_TSF_ID_C: use TSF C 3342 * @IWM_TSF_ID_D: use TSF D 3343 * @IWM_NUM_TSF_IDS: number of TSF timers available 3344 */ 3345enum iwm_tsf_id { 3346 IWM_TSF_ID_A = 0, 3347 IWM_TSF_ID_B = 1, 3348 IWM_TSF_ID_C = 2, 3349 IWM_TSF_ID_D = 3, 3350 IWM_NUM_TSF_IDS = 4, 3351}; /* IWM_TSF_ID_API_E_VER_1 */ 3352 3353/** 3354 * struct iwm_mac_data_ap - configuration data for AP MAC context 3355 * @beacon_time: beacon transmit time in system time 3356 * @beacon_tsf: beacon transmit time in TSF 3357 * @bi: beacon interval in TU 3358 * @bi_reciprocal: 2^32 / bi 3359 * @dtim_interval: dtim transmit time in TU 3360 * @dtim_reciprocal: 2^32 / dtim_interval 3361 * @mcast_qid: queue ID for multicast traffic 3362 * @beacon_template: beacon template ID 3363 */ 3364struct iwm_mac_data_ap { 3365 uint32_t beacon_time; 3366 uint64_t beacon_tsf; 3367 uint32_t bi; 3368 uint32_t bi_reciprocal; 3369 uint32_t dtim_interval; 3370 uint32_t dtim_reciprocal; 3371 uint32_t mcast_qid; 3372 uint32_t beacon_template; 3373} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3374 3375/** 3376 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3377 * @beacon_time: beacon transmit time in system time 3378 * @beacon_tsf: beacon transmit time in TSF 3379 * @bi: beacon interval in TU 3380 * @bi_reciprocal: 2^32 / bi 3381 * @beacon_template: beacon template ID 3382 */ 3383struct iwm_mac_data_ibss { 3384 uint32_t beacon_time; 3385 uint64_t beacon_tsf; 3386 uint32_t bi; 3387 uint32_t bi_reciprocal; 3388 uint32_t beacon_template; 3389} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3390 3391/** 3392 * struct iwm_mac_data_sta - configuration data for station MAC context 3393 * @is_assoc: 1 for associated state, 0 otherwise 3394 * @dtim_time: DTIM arrival time in system time 3395 * @dtim_tsf: DTIM arrival time in TSF 3396 * @bi: beacon interval in TU, applicable only when associated 3397 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3398 * @dtim_interval: DTIM interval in TU, applicable only when associated 3399 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3400 * @listen_interval: in beacon intervals, applicable only when associated 3401 * @assoc_id: unique ID assigned by the AP during association 3402 */ 3403struct iwm_mac_data_sta { 3404 uint32_t is_assoc; 3405 uint32_t dtim_time; 3406 uint64_t dtim_tsf; 3407 uint32_t bi; 3408 uint32_t bi_reciprocal; 3409 uint32_t dtim_interval; 3410 uint32_t dtim_reciprocal; 3411 uint32_t listen_interval; 3412 uint32_t assoc_id; 3413 uint32_t assoc_beacon_arrive_time; 3414} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3415 3416/** 3417 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3418 * @ap: iwm_mac_data_ap struct with most config data 3419 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3420 * 0 indicates that there is no CT window. 3421 * @opp_ps_enabled: indicate that opportunistic PS allowed 3422 */ 3423struct iwm_mac_data_go { 3424 struct iwm_mac_data_ap ap; 3425 uint32_t ctwin; 3426 uint32_t opp_ps_enabled; 3427} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3428 3429/** 3430 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3431 * @sta: iwm_mac_data_sta struct with most config data 3432 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3433 * 0 indicates that there is no CT window. 3434 */ 3435struct iwm_mac_data_p2p_sta { 3436 struct iwm_mac_data_sta sta; 3437 uint32_t ctwin; 3438} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3439 3440/** 3441 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3442 * @stats_interval: interval in TU between statistics notifications to host. 3443 */ 3444struct iwm_mac_data_pibss { 3445 uint32_t stats_interval; 3446} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3447 3448/* 3449 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3450 * context. 3451 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3452 * other channels as well. This should be to true only in case that the 3453 * device is discoverable and there is an active GO. Note that setting this 3454 * field when not needed, will increase the number of interrupts and have 3455 * effect on the platform power, as this setting opens the Rx filters on 3456 * all macs. 3457 */ 3458struct iwm_mac_data_p2p_dev { 3459 uint32_t is_disc_extended; 3460} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3461 3462/** 3463 * enum iwm_mac_filter_flags - MAC context filter flags 3464 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3465 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3466 * control frames to the host 3467 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3468 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3469 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3470 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3471 * (in station mode when associated) 3472 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3473 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3474 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3475 */ 3476enum iwm_mac_filter_flags { 3477 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3478 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3479 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3480 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3481 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3482 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3483 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3484 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3485 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3486}; 3487 3488/** 3489 * enum iwm_mac_qos_flags - QoS flags 3490 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3491 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3492 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3493 * 3494 */ 3495enum iwm_mac_qos_flags { 3496 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3497 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3498 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3499}; 3500 3501/** 3502 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3503 * @cw_min: Contention window, start value in numbers of slots. 3504 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3505 * @cw_max: Contention window, max value in numbers of slots. 3506 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3507 * @aifsn: Number of slots in Arbitration Interframe Space (before 3508 * performing random backoff timing prior to Tx). Device default 1. 3509 * @fifos_mask: FIFOs used by this MAC for this AC 3510 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3511 * 3512 * One instance of this config struct for each of 4 EDCA access categories 3513 * in struct iwm_qosparam_cmd. 3514 * 3515 * Device will automatically increase contention window by (2*CW) + 1 for each 3516 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3517 * value, to cap the CW value. 3518 */ 3519struct iwm_ac_qos { 3520 uint16_t cw_min; 3521 uint16_t cw_max; 3522 uint8_t aifsn; 3523 uint8_t fifos_mask; 3524 uint16_t edca_txop; 3525} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3526 3527/** 3528 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3529 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3530 * @id_and_color: ID and color of the MAC 3531 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3532 * @mac_type: one of IWM_FW_MAC_TYPE_* 3533 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3534 * @node_addr: MAC address 3535 * @bssid_addr: BSSID 3536 * @cck_rates: basic rates available for CCK 3537 * @ofdm_rates: basic rates available for OFDM 3538 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3539 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3540 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3541 * @filter_flags: combination of IWM_MAC_FILTER_* 3542 * @qos_flags: from IWM_MAC_QOS_FLG_* 3543 * @ac: one iwm_mac_qos configuration for each AC 3544 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3545 */ 3546struct iwm_mac_ctx_cmd { 3547 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3548 uint32_t id_and_color; 3549 uint32_t action; 3550 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3551 uint32_t mac_type; 3552 uint32_t tsf_id; 3553 uint8_t node_addr[6]; 3554 uint16_t reserved_for_node_addr; 3555 uint8_t bssid_addr[6]; 3556 uint16_t reserved_for_bssid_addr; 3557 uint32_t cck_rates; 3558 uint32_t ofdm_rates; 3559 uint32_t protection_flags; 3560 uint32_t cck_short_preamble; 3561 uint32_t short_slot; 3562 uint32_t filter_flags; 3563 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3564 uint32_t qos_flags; 3565 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3566 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3567 union { 3568 struct iwm_mac_data_ap ap; 3569 struct iwm_mac_data_go go; 3570 struct iwm_mac_data_sta sta; 3571 struct iwm_mac_data_p2p_sta p2p_sta; 3572 struct iwm_mac_data_p2p_dev p2p_dev; 3573 struct iwm_mac_data_pibss pibss; 3574 struct iwm_mac_data_ibss ibss; 3575 }; 3576} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3577 3578static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3579{ 3580 if (!v) 3581 return 0; 3582 return 0xFFFFFFFF / v; 3583} 3584 3585#define IWM_NONQOS_SEQ_GET 0x1 3586#define IWM_NONQOS_SEQ_SET 0x2 3587struct iwm_nonqos_seq_query_cmd { 3588 uint32_t get_set_flag; 3589 uint32_t mac_id_n_color; 3590 uint16_t value; 3591 uint16_t reserved; 3592} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3593 3594/* 3595 * END mvm/fw-api-mac.h 3596 */ 3597 3598/* 3599 * BEGIN mvm/fw-api-power.h 3600 */ 3601 3602/* Power Management Commands, Responses, Notifications */ 3603 3604/* Radio LP RX Energy Threshold measured in dBm */ 3605#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3606#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3607#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3608 3609/** 3610 * enum iwm_scan_flags - masks for power table command flags 3611 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3612 * receiver and transmitter. '0' - does not allow. 3613 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3614 * '1' Driver enables PM (use rest of parameters) 3615 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3616 * '1' PM could sleep over DTIM till listen Interval. 3617 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3618 * access categories are both delivery and trigger enabled. 3619 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3620 * PBW Snoozing enabled 3621 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3622 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3623 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3624 * detection enablement 3625*/ 3626enum iwm_power_flags { 3627 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3628 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3629 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3630 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3631 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3632 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3633 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3634 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3635}; 3636 3637#define IWM_POWER_VEC_SIZE 5 3638 3639/** 3640 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3641 * is used also with a new power API for device wide power settings. 3642 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3643 * 3644 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3645 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3646 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3647 * set regardless of power scheme or current power state. 3648 * FW use this value also when PM is disabled. 3649 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3650 * PSM transition - legacy PM 3651 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3652 * PSM transition - legacy PM 3653 * @sleep_interval: not in use 3654 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3655 * is set. For example, if it is required to skip over 3656 * one DTIM, this value need to be set to 2 (DTIM periods). 3657 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3658 * Default: 80dbm 3659 */ 3660struct iwm_powertable_cmd { 3661 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3662 uint16_t flags; 3663 uint8_t keep_alive_seconds; 3664 uint8_t debug_flags; 3665 uint32_t rx_data_timeout; 3666 uint32_t tx_data_timeout; 3667 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3668 uint32_t skip_dtim_periods; 3669 uint32_t lprx_rssi_threshold; 3670} __packed; 3671 3672/** 3673 * enum iwm_device_power_flags - masks for device power command flags 3674 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3675 * receiver and transmitter. '0' - does not allow. This flag should be 3676 * always set to '1' unless one need to disable actual power down for debug 3677 * purposes. 3678 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3679 * that power management is disabled. '0' Power management is enabled, one 3680 * of power schemes is applied. 3681*/ 3682enum iwm_device_power_flags { 3683 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3684 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3685}; 3686 3687/** 3688 * struct iwm_device_power_cmd - device wide power command. 3689 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3690 * 3691 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3692 */ 3693struct iwm_device_power_cmd { 3694 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3695 uint16_t flags; 3696 uint16_t reserved; 3697} __packed; 3698 3699/** 3700 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3701 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3702 * @id_and_color: MAC contex identifier 3703 * @flags: Power table command flags from POWER_FLAGS_* 3704 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3705 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3706 * set regardless of power scheme or current power state. 3707 * FW use this value also when PM is disabled. 3708 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3709 * PSM transition - legacy PM 3710 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3711 * PSM transition - legacy PM 3712 * @sleep_interval: not in use 3713 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3714 * is set. For example, if it is required to skip over 3715 * one DTIM, this value need to be set to 2 (DTIM periods). 3716 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3717 * PSM transition - uAPSD 3718 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3719 * PSM transition - uAPSD 3720 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3721 * Default: 80dbm 3722 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3723 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3724 * from the AP [msec] 3725 * @snooze_window: A window of time in which PBW snoozing insures that all 3726 * packets received. It is also the minimum time from last 3727 * received unicast RX packet, before client stops snoozing 3728 * for data. [msec] 3729 * @snooze_step: TBD 3730 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3731 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3732 * each corresponding AC. 3733 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3734 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3735 * values. 3736 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3737 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3738 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3739 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3740 * @limited_ps_threshold: 3741*/ 3742struct iwm_mac_power_cmd { 3743 /* CONTEXT_DESC_API_T_VER_1 */ 3744 uint32_t id_and_color; 3745 3746 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3747 uint16_t flags; 3748 uint16_t keep_alive_seconds; 3749 uint32_t rx_data_timeout; 3750 uint32_t tx_data_timeout; 3751 uint32_t rx_data_timeout_uapsd; 3752 uint32_t tx_data_timeout_uapsd; 3753 uint8_t lprx_rssi_threshold; 3754 uint8_t skip_dtim_periods; 3755 uint16_t snooze_interval; 3756 uint16_t snooze_window; 3757 uint8_t snooze_step; 3758 uint8_t qndp_tid; 3759 uint8_t uapsd_ac_flags; 3760 uint8_t uapsd_max_sp; 3761 uint8_t heavy_tx_thld_packets; 3762 uint8_t heavy_rx_thld_packets; 3763 uint8_t heavy_tx_thld_percentage; 3764 uint8_t heavy_rx_thld_percentage; 3765 uint8_t limited_ps_threshold; 3766 uint8_t reserved; 3767} __packed; 3768 3769/* 3770 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3771 * associated AP is identified as improperly implementing uAPSD protocol. 3772 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3773 * @sta_id: index of station in uCode's station table - associated AP ID in 3774 * this context. 3775 */ 3776struct iwm_uapsd_misbehaving_ap_notif { 3777 uint32_t sta_id; 3778 uint8_t mac_id; 3779 uint8_t reserved[3]; 3780} __packed; 3781 3782/** 3783 * struct iwm_beacon_filter_cmd 3784 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3785 * @id_and_color: MAC contex identifier 3786 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3787 * to driver if delta in Energy values calculated for this and last 3788 * passed beacon is greater than this threshold. Zero value means that 3789 * the Energy change is ignored for beacon filtering, and beacon will 3790 * not be forced to be sent to driver regardless of this delta. Typical 3791 * energy delta 5dB. 3792 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3793 * Send beacon to driver if delta in Energy values calculated for this 3794 * and last passed beacon is greater than this threshold. Zero value 3795 * means that the Energy change is ignored for beacon filtering while in 3796 * Roaming state, typical energy delta 1dB. 3797 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3798 * calculated for current beacon is less than the threshold, use 3799 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3800 * Threshold. Typical energy threshold is -72dBm. 3801 * @bf_temp_threshold: This threshold determines the type of temperature 3802 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3803 * If the current temperature is above this threshold - Fast filter 3804 * will be used, If the current temperature is below this threshold - 3805 * Slow filter will be used. 3806 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3807 * calculated for this and the last passed beacon is greater than this 3808 * threshold. Zero value means that the temperature change is ignored for 3809 * beacon filtering; beacons will not be forced to be sent to driver 3810 * regardless of whether its temperature has been changed. 3811 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3812 * calculated for this and the last passed beacon is greater than this 3813 * threshold. Zero value means that the temperature change is ignored for 3814 * beacon filtering; beacons will not be forced to be sent to driver 3815 * regardless of whether its temperature has been changed. 3816 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3817 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3818 * for a specific period of time. Units: Beacons. 3819 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3820 * for a longer period of time then this escape-timeout. Units: Beacons. 3821 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3822 */ 3823struct iwm_beacon_filter_cmd { 3824 uint32_t bf_energy_delta; 3825 uint32_t bf_roaming_energy_delta; 3826 uint32_t bf_roaming_state; 3827 uint32_t bf_temp_threshold; 3828 uint32_t bf_temp_fast_filter; 3829 uint32_t bf_temp_slow_filter; 3830 uint32_t bf_enable_beacon_filter; 3831 uint32_t bf_debug_flag; 3832 uint32_t bf_escape_timer; 3833 uint32_t ba_escape_timer; 3834 uint32_t ba_enable_beacon_abort; 3835} __packed; 3836 3837/* Beacon filtering and beacon abort */ 3838#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3839#define IWM_BF_ENERGY_DELTA_MAX 255 3840#define IWM_BF_ENERGY_DELTA_MIN 0 3841 3842#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3843#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3844#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3845 3846#define IWM_BF_ROAMING_STATE_DEFAULT 72 3847#define IWM_BF_ROAMING_STATE_MAX 255 3848#define IWM_BF_ROAMING_STATE_MIN 0 3849 3850#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3851#define IWM_BF_TEMP_THRESHOLD_MAX 255 3852#define IWM_BF_TEMP_THRESHOLD_MIN 0 3853 3854#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3855#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3856#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3857 3858#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3859#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3860#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3861 3862#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3863 3864#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3865 3866#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3867#define IWM_BF_ESCAPE_TIMER_MAX 1024 3868#define IWM_BF_ESCAPE_TIMER_MIN 0 3869 3870#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3871#define IWM_BA_ESCAPE_TIMER_D3 9 3872#define IWM_BA_ESCAPE_TIMER_MAX 1024 3873#define IWM_BA_ESCAPE_TIMER_MIN 0 3874 3875#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3876 3877#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3878 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3879 .bf_roaming_energy_delta = \ 3880 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3881 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3882 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3883 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3884 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3885 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3886 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3887 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3888 3889/* 3890 * END mvm/fw-api-power.h 3891 */ 3892 3893/* 3894 * BEGIN mvm/fw-api-rs.h 3895 */ 3896 3897/* 3898 * These serve as indexes into 3899 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3900 * TODO: avoid overlap between legacy and HT rates 3901 */ 3902enum { 3903 IWM_RATE_1M_INDEX = 0, 3904 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3905 IWM_RATE_2M_INDEX, 3906 IWM_RATE_5M_INDEX, 3907 IWM_RATE_11M_INDEX, 3908 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3909 IWM_RATE_6M_INDEX, 3910 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3911 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3912 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3913 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3914 IWM_RATE_9M_INDEX, 3915 IWM_RATE_12M_INDEX, 3916 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3917 IWM_RATE_18M_INDEX, 3918 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3919 IWM_RATE_24M_INDEX, 3920 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3921 IWM_RATE_36M_INDEX, 3922 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3923 IWM_RATE_48M_INDEX, 3924 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3925 IWM_RATE_54M_INDEX, 3926 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3927 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3928 IWM_RATE_60M_INDEX, 3929 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3930 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3931 IWM_RATE_MCS_8_INDEX, 3932 IWM_RATE_MCS_9_INDEX, 3933 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3934 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3935 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3936}; 3937 3938#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3939 3940/* fw API values for legacy bit rates, both OFDM and CCK */ 3941enum { 3942 IWM_RATE_6M_PLCP = 13, 3943 IWM_RATE_9M_PLCP = 15, 3944 IWM_RATE_12M_PLCP = 5, 3945 IWM_RATE_18M_PLCP = 7, 3946 IWM_RATE_24M_PLCP = 9, 3947 IWM_RATE_36M_PLCP = 11, 3948 IWM_RATE_48M_PLCP = 1, 3949 IWM_RATE_54M_PLCP = 3, 3950 IWM_RATE_1M_PLCP = 10, 3951 IWM_RATE_2M_PLCP = 20, 3952 IWM_RATE_5M_PLCP = 55, 3953 IWM_RATE_11M_PLCP = 110, 3954 IWM_RATE_INVM_PLCP = -1, 3955}; 3956 3957/* 3958 * rate_n_flags bit fields 3959 * 3960 * The 32-bit value has different layouts in the low 8 bites depending on the 3961 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3962 * for CCK and OFDM). 3963 * 3964 * High-throughput (HT) rate format 3965 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3966 * Very High-throughput (VHT) rate format 3967 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3968 * Legacy OFDM rate format for bits 7:0 3969 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3970 * Legacy CCK rate format for bits 7:0: 3971 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3972 */ 3973 3974/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3975#define IWM_RATE_MCS_HT_POS 8 3976#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3977 3978/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3979#define IWM_RATE_MCS_CCK_POS 9 3980#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3981 3982/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3983#define IWM_RATE_MCS_VHT_POS 26 3984#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3985 3986 3987/* 3988 * High-throughput (HT) rate format for bits 7:0 3989 * 3990 * 2-0: MCS rate base 3991 * 0) 6 Mbps 3992 * 1) 12 Mbps 3993 * 2) 18 Mbps 3994 * 3) 24 Mbps 3995 * 4) 36 Mbps 3996 * 5) 48 Mbps 3997 * 6) 54 Mbps 3998 * 7) 60 Mbps 3999 * 4-3: 0) Single stream (SISO) 4000 * 1) Dual stream (MIMO) 4001 * 2) Triple stream (MIMO) 4002 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4003 * (bits 7-6 are zero) 4004 * 4005 * Together the low 5 bits work out to the MCS index because we don't 4006 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4007 * streams and 16-23 have three streams. We could also support MCS 32 4008 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4009 */ 4010#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4011#define IWM_RATE_HT_MCS_NSS_POS 3 4012#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4013 4014/* Bit 10: (1) Use Green Field preamble */ 4015#define IWM_RATE_HT_MCS_GF_POS 10 4016#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4017 4018#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4019 4020/* 4021 * Very High-throughput (VHT) rate format for bits 7:0 4022 * 4023 * 3-0: VHT MCS (0-9) 4024 * 5-4: number of streams - 1: 4025 * 0) Single stream (SISO) 4026 * 1) Dual stream (MIMO) 4027 * 2) Triple stream (MIMO) 4028 */ 4029 4030/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4031#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4032#define IWM_RATE_VHT_MCS_NSS_POS 4 4033#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4034 4035/* 4036 * Legacy OFDM rate format for bits 7:0 4037 * 4038 * 3-0: 0xD) 6 Mbps 4039 * 0xF) 9 Mbps 4040 * 0x5) 12 Mbps 4041 * 0x7) 18 Mbps 4042 * 0x9) 24 Mbps 4043 * 0xB) 36 Mbps 4044 * 0x1) 48 Mbps 4045 * 0x3) 54 Mbps 4046 * (bits 7-4 are 0) 4047 * 4048 * Legacy CCK rate format for bits 7:0: 4049 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4050 * 4051 * 6-0: 10) 1 Mbps 4052 * 20) 2 Mbps 4053 * 55) 5.5 Mbps 4054 * 110) 11 Mbps 4055 * (bit 7 is 0) 4056 */ 4057#define IWM_RATE_LEGACY_RATE_MSK 0xff 4058 4059 4060/* 4061 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4062 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4063 */ 4064#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4065#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4066#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4067#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4068#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4069#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4070 4071/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4072#define IWM_RATE_MCS_SGI_POS 13 4073#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4074 4075/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4076#define IWM_RATE_MCS_ANT_POS 14 4077#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4078#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4079#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4080#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4081 IWM_RATE_MCS_ANT_B_MSK) 4082#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4083 IWM_RATE_MCS_ANT_C_MSK) 4084#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4085#define IWM_RATE_MCS_ANT_NUM 3 4086 4087/* Bit 17-18: (0) SS, (1) SS*2 */ 4088#define IWM_RATE_MCS_STBC_POS 17 4089#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4090 4091/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4092#define IWM_RATE_MCS_BF_POS 19 4093#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4094 4095/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4096#define IWM_RATE_MCS_ZLF_POS 20 4097#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4098 4099/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4100#define IWM_RATE_MCS_DUP_POS 24 4101#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4102 4103/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4104#define IWM_RATE_MCS_LDPC_POS 27 4105#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4106 4107 4108/* Link Quality definitions */ 4109 4110/* # entries in rate scale table to support Tx retries */ 4111#define IWM_LQ_MAX_RETRY_NUM 16 4112 4113/* Link quality command flags bit fields */ 4114 4115/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4116#define IWM_LQ_FLAG_USE_RTS_POS 0 4117#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4118 4119/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4120#define IWM_LQ_FLAG_COLOR_POS 1 4121#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4122 4123/* Bit 4-5: Tx RTS BW Signalling 4124 * (0) No RTS BW signalling 4125 * (1) Static BW signalling 4126 * (2) Dynamic BW signalling 4127 */ 4128#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4129#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4130#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4131#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4132 4133/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4134 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4135 */ 4136#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4137#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4138 4139/** 4140 * struct iwm_lq_cmd - link quality command 4141 * @sta_id: station to update 4142 * @control: not used 4143 * @flags: combination of IWM_LQ_FLAG_* 4144 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4145 * and SISO rates 4146 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4147 * Should be ANT_[ABC] 4148 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4149 * @initial_rate_index: first index from rs_table per AC category 4150 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4151 * value of 100 is one usec. Range is 100 to 8000 4152 * @agg_disable_start_th: try-count threshold for starting aggregation. 4153 * If a frame has higher try-count, it should not be selected for 4154 * starting an aggregation sequence. 4155 * @agg_frame_cnt_limit: max frame count in an aggregation. 4156 * 0: no limit 4157 * 1: no aggregation (one frame per aggregation) 4158 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4159 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4160 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4161 * @bf_params: beam forming params, currently not used 4162 */ 4163struct iwm_lq_cmd { 4164 uint8_t sta_id; 4165 uint8_t reserved1; 4166 uint16_t control; 4167 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4168 uint8_t flags; 4169 uint8_t mimo_delim; 4170 uint8_t single_stream_ant_msk; 4171 uint8_t dual_stream_ant_msk; 4172 uint8_t initial_rate_index[IWM_AC_NUM]; 4173 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4174 uint16_t agg_time_limit; 4175 uint8_t agg_disable_start_th; 4176 uint8_t agg_frame_cnt_limit; 4177 uint32_t reserved2; 4178 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4179 uint32_t bf_params; 4180}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4181 4182/* 4183 * END mvm/fw-api-rs.h 4184 */ 4185 4186/* 4187 * BEGIN mvm/fw-api-tx.h 4188 */ 4189 4190/** 4191 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4192 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4193 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4194 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4195 * Otherwise, use rate_n_flags from the TX command 4196 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4197 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4198 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4199 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4200 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4201 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4202 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4203 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4204 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4205 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4206 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4207 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4208 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4209 * Should be set for beacons and probe responses 4210 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4211 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4212 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4213 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4214 * Should be set for 26/30 length MAC headers 4215 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4216 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4217 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4218 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4219 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4220 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4221 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4222 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4223 */ 4224enum iwm_tx_flags { 4225 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4226 IWM_TX_CMD_FLG_ACK = (1 << 3), 4227 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4228 IWM_TX_CMD_FLG_BA = (1 << 5), 4229 IWM_TX_CMD_FLG_BAR = (1 << 6), 4230 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4231 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4232 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4233 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4234 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4235 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4236 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4237 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4238 IWM_TX_CMD_FLG_TSF = (1 << 16), 4239 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4240 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4241 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4242 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4243 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4244 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4245 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4246 IWM_TX_CMD_FLG_DUR = (1 << 25), 4247 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4248 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4249 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4250 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4251}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4252 4253/** 4254 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4255 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4256 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4257 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4258 */ 4259enum iwm_tx_pm_timeouts { 4260 IWM_PM_FRAME_NONE = 0, 4261 IWM_PM_FRAME_MGMT = 2, 4262 IWM_PM_FRAME_ASSOC = 3, 4263}; 4264 4265/* 4266 * TX command security control 4267 */ 4268#define IWM_TX_CMD_SEC_WEP 0x01 4269#define IWM_TX_CMD_SEC_CCM 0x02 4270#define IWM_TX_CMD_SEC_TKIP 0x03 4271#define IWM_TX_CMD_SEC_EXT 0x04 4272#define IWM_TX_CMD_SEC_MSK 0x07 4273#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4274#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4275#define IWM_TX_CMD_SEC_KEY128 0x08 4276 4277/* TODO: how does these values are OK with only 16 bit variable??? */ 4278/* 4279 * TX command next frame info 4280 * 4281 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4282 * bit 3 - immediate ACK required 4283 * bit 4 - rate is taken from STA table 4284 * bit 5 - frame belongs to BA stream 4285 * bit 6 - immediate BA response expected 4286 * bit 7 - unused 4287 * bits 8:15 - Station ID 4288 * bits 16:31 - rate 4289 */ 4290#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4291#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4292#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4293#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4294#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4295#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4296#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4297#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4298#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4299 4300/* 4301 * TX command Frame life time in us - to be written in pm_frame_timeout 4302 */ 4303#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4304#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4305#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4306#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4307 4308/* 4309 * TID for non QoS frames - to be written in tid_tspec 4310 */ 4311#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4312 4313/* 4314 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4315 */ 4316#define IWM_DEFAULT_TX_RETRY 15 4317#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4318#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4319#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4320#define IWM_LOW_RETRY_LIMIT 7 4321 4322/* TODO: complete documentation for try_cnt and btkill_cnt */ 4323/** 4324 * struct iwm_tx_cmd - TX command struct to FW 4325 * ( IWM_TX_CMD = 0x1c ) 4326 * @len: in bytes of the payload, see below for details 4327 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4328 * Used for fragmentation and bursting, but not in 11n aggregation. 4329 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4330 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4331 * cleared. Combination of IWM_RATE_MCS_* 4332 * @sta_id: index of destination station in FW station table 4333 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4334 * @initial_rate_index: index into the rate table for initial TX attempt. 4335 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4336 * @key: security key 4337 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4338 * @life_time: frame life time (usecs??) 4339 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4340 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4341 * @dram_msb_ptr: upper bits of the scratch physical address 4342 * @rts_retry_limit: max attempts for RTS 4343 * @data_retry_limit: max attempts to send the data packet 4344 * @tid_spec: TID/tspec 4345 * @pm_frame_timeout: PM TX frame timeout 4346 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4347 * specified by HCCA protocol 4348 * 4349 * The byte count (both len and next_frame_len) includes MAC header 4350 * (24/26/30/32 bytes) 4351 * + 2 bytes pad if 26/30 header size 4352 * + 8 byte IV for CCM or TKIP (not used for WEP) 4353 * + Data payload 4354 * + 8-byte MIC (not used for CCM/WEP) 4355 * It does not include post-MAC padding, i.e., 4356 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4357 * Range of len: 14-2342 bytes. 4358 * 4359 * After the struct fields the MAC header is placed, plus any padding, 4360 * and then the actial payload. 4361 */ 4362struct iwm_tx_cmd { 4363 uint16_t len; 4364 uint16_t next_frame_len; 4365 uint32_t tx_flags; 4366 struct { 4367 uint8_t try_cnt; 4368 uint8_t btkill_cnt; 4369 uint16_t reserved; 4370 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4371 uint32_t rate_n_flags; 4372 uint8_t sta_id; 4373 uint8_t sec_ctl; 4374 uint8_t initial_rate_index; 4375 uint8_t reserved2; 4376 uint8_t key[16]; 4377 uint16_t next_frame_flags; 4378 uint16_t reserved3; 4379 uint32_t life_time; 4380 uint32_t dram_lsb_ptr; 4381 uint8_t dram_msb_ptr; 4382 uint8_t rts_retry_limit; 4383 uint8_t data_retry_limit; 4384 uint8_t tid_tspec; 4385 uint16_t pm_frame_timeout; 4386 uint16_t driver_txop; 4387 uint8_t payload[0]; 4388 struct ieee80211_frame hdr[0]; 4389} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4390 4391/* 4392 * TX response related data 4393 */ 4394 4395/* 4396 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4397 * @IWM_TX_STATUS_SUCCESS: 4398 * @IWM_TX_STATUS_DIRECT_DONE: 4399 * @IWM_TX_STATUS_POSTPONE_DELAY: 4400 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4401 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4402 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4403 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4404 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4405 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4406 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4407 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4408 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4409 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4410 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4411 * @IWM_TX_STATUS_FAIL_DEST_PS: 4412 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4413 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4414 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4415 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4416 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4417 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4418 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4419 * @IWM_TX_STATUS_FAIL_FW_DROP: 4420 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4421 * STA table 4422 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4423 * @IWM_TX_MODE_MSK: 4424 * @IWM_TX_MODE_NO_BURST: 4425 * @IWM_TX_MODE_IN_BURST_SEQ: 4426 * @IWM_TX_MODE_FIRST_IN_BURST: 4427 * @IWM_TX_QUEUE_NUM_MSK: 4428 * 4429 * Valid only if frame_count =1 4430 * TODO: complete documentation 4431 */ 4432enum iwm_tx_status { 4433 IWM_TX_STATUS_MSK = 0x000000ff, 4434 IWM_TX_STATUS_SUCCESS = 0x01, 4435 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4436 /* postpone TX */ 4437 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4438 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4439 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4440 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4441 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4442 /* abort TX */ 4443 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4444 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4445 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4446 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4447 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4448 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4449 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4450 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4451 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4452 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4453 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4454 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4455 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4456 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4457 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4458 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4459 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4460 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4461 IWM_TX_MODE_MSK = 0x00000f00, 4462 IWM_TX_MODE_NO_BURST = 0x00000000, 4463 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4464 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4465 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4466 IWM_TX_NARROW_BW_MSK = 0x00060000, 4467 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4468 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4469 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4470}; 4471 4472/* 4473 * enum iwm_tx_agg_status - TX aggregation status 4474 * @IWM_AGG_TX_STATE_STATUS_MSK: 4475 * @IWM_AGG_TX_STATE_TRANSMITTED: 4476 * @IWM_AGG_TX_STATE_UNDERRUN: 4477 * @IWM_AGG_TX_STATE_BT_PRIO: 4478 * @IWM_AGG_TX_STATE_FEW_BYTES: 4479 * @IWM_AGG_TX_STATE_ABORT: 4480 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4481 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4482 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4483 * @IWM_AGG_TX_STATE_SCD_QUERY: 4484 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4485 * @IWM_AGG_TX_STATE_RESPONSE: 4486 * @IWM_AGG_TX_STATE_DUMP_TX: 4487 * @IWM_AGG_TX_STATE_DELAY_TX: 4488 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4489 * occur if tx failed for this frame when it was a member of a previous 4490 * aggregation block). If rate scaling is used, retry count indicates the 4491 * rate table entry used for all frames in the new agg. 4492 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4493 * this frame 4494 * 4495 * TODO: complete documentation 4496 */ 4497enum iwm_tx_agg_status { 4498 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4499 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4500 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4501 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4502 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4503 IWM_AGG_TX_STATE_ABORT = 0x008, 4504 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4505 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4506 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4507 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4508 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4509 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4510 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4511 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4512 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4513 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4514}; 4515 4516#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4517 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4518 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4519 4520/* 4521 * The mask below describes a status where we are absolutely sure that the MPDU 4522 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4523 * written the bytes to the TXE, but we know nothing about what the DSP did. 4524 */ 4525#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4526 IWM_AGG_TX_STATE_ABORT | \ 4527 IWM_AGG_TX_STATE_SCD_QUERY) 4528 4529/* 4530 * IWM_REPLY_TX = 0x1c (response) 4531 * 4532 * This response may be in one of two slightly different formats, indicated 4533 * by the frame_count field: 4534 * 4535 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4536 * frame. Multiple attempts, at various bit rates, may have been made for 4537 * this frame. 4538 * 4539 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4540 * frames that used block-acknowledge. All frames were transmitted at 4541 * same rate. Rate scaling may have been used if first frame in this new 4542 * agg block failed in previous agg block(s). 4543 * 4544 * Note that, for aggregation, ACK (block-ack) status is not delivered 4545 * here; block-ack has not been received by the time the device records 4546 * this status. 4547 * This status relates to reasons the tx might have been blocked or aborted 4548 * within the device, rather than whether it was received successfully by 4549 * the destination station. 4550 */ 4551 4552/** 4553 * struct iwm_agg_tx_status - per packet TX aggregation status 4554 * @status: enum iwm_tx_agg_status 4555 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4556 */ 4557struct iwm_agg_tx_status { 4558 uint16_t status; 4559 uint16_t sequence; 4560} __packed; 4561 4562/* 4563 * definitions for initial rate index field 4564 * bits [3:0] initial rate index 4565 * bits [6:4] rate table color, used for the initial rate 4566 * bit-7 invalid rate indication 4567 */ 4568#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4569#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4570#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4571 4572#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4573#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4574 4575/** 4576 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4577 * ( IWM_REPLY_TX = 0x1c ) 4578 * @frame_count: 1 no aggregation, >1 aggregation 4579 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4580 * @failure_rts: num of failures due to unsuccessful RTS 4581 * @failure_frame: num failures due to no ACK (unused for agg) 4582 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4583 * Tx of all the batch. IWM_RATE_MCS_* 4584 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4585 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4586 * in usec. 4587 * @pa_status: tx power info 4588 * @pa_integ_res_a: tx power info 4589 * @pa_integ_res_b: tx power info 4590 * @pa_integ_res_c: tx power info 4591 * @measurement_req_id: tx power info 4592 * @tfd_info: TFD information set by the FH 4593 * @seq_ctl: sequence control from the Tx cmd 4594 * @byte_cnt: byte count from the Tx cmd 4595 * @tlc_info: TLC rate info 4596 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4597 * @frame_ctrl: frame control 4598 * @status: for non-agg: frame status IWM_TX_STATUS_* 4599 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4600 * follow this one, up to frame_count. 4601 * 4602 * After the array of statuses comes the SSN of the SCD. Look at 4603 * %iwm_mvm_get_scd_ssn for more details. 4604 */ 4605struct iwm_mvm_tx_resp { 4606 uint8_t frame_count; 4607 uint8_t bt_kill_count; 4608 uint8_t failure_rts; 4609 uint8_t failure_frame; 4610 uint32_t initial_rate; 4611 uint16_t wireless_media_time; 4612 4613 uint8_t pa_status; 4614 uint8_t pa_integ_res_a[3]; 4615 uint8_t pa_integ_res_b[3]; 4616 uint8_t pa_integ_res_c[3]; 4617 uint16_t measurement_req_id; 4618 uint16_t reserved; 4619 4620 uint32_t tfd_info; 4621 uint16_t seq_ctl; 4622 uint16_t byte_cnt; 4623 uint8_t tlc_info; 4624 uint8_t ra_tid; 4625 uint16_t frame_ctrl; 4626 4627 struct iwm_agg_tx_status status; 4628} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4629 4630/** 4631 * struct iwm_mvm_ba_notif - notifies about reception of BA 4632 * ( IWM_BA_NOTIF = 0xc5 ) 4633 * @sta_addr_lo32: lower 32 bits of the MAC address 4634 * @sta_addr_hi16: upper 16 bits of the MAC address 4635 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4636 * @tid: tid of the session 4637 * @seq_ctl: 4638 * @bitmap: the bitmap of the BA notification as seen in the air 4639 * @scd_flow: the tx queue this BA relates to 4640 * @scd_ssn: the index of the last contiguously sent packet 4641 * @txed: number of Txed frames in this batch 4642 * @txed_2_done: number of Acked frames in this batch 4643 */ 4644struct iwm_mvm_ba_notif { 4645 uint32_t sta_addr_lo32; 4646 uint16_t sta_addr_hi16; 4647 uint16_t reserved; 4648 4649 uint8_t sta_id; 4650 uint8_t tid; 4651 uint16_t seq_ctl; 4652 uint64_t bitmap; 4653 uint16_t scd_flow; 4654 uint16_t scd_ssn; 4655 uint8_t txed; 4656 uint8_t txed_2_done; 4657 uint16_t reserved1; 4658} __packed; 4659 4660/* 4661 * struct iwm_mac_beacon_cmd - beacon template command 4662 * @tx: the tx commands associated with the beacon frame 4663 * @template_id: currently equal to the mac context id of the coresponding 4664 * mac. 4665 * @tim_idx: the offset of the tim IE in the beacon 4666 * @tim_size: the length of the tim IE 4667 * @frame: the template of the beacon frame 4668 */ 4669struct iwm_mac_beacon_cmd { 4670 struct iwm_tx_cmd tx; 4671 uint32_t template_id; 4672 uint32_t tim_idx; 4673 uint32_t tim_size; 4674 struct ieee80211_frame frame[0]; 4675} __packed; 4676 4677struct iwm_beacon_notif { 4678 struct iwm_mvm_tx_resp beacon_notify_hdr; 4679 uint64_t tsf; 4680 uint32_t ibss_mgr_status; 4681} __packed; 4682 4683/** 4684 * enum iwm_dump_control - dump (flush) control flags 4685 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4686 * and the TFD queues are empty. 4687 */ 4688enum iwm_dump_control { 4689 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4690}; 4691 4692/** 4693 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4694 * @queues_ctl: bitmap of queues to flush 4695 * @flush_ctl: control flags 4696 * @reserved: reserved 4697 */ 4698struct iwm_tx_path_flush_cmd { 4699 uint32_t queues_ctl; 4700 uint16_t flush_ctl; 4701 uint16_t reserved; 4702} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4703 4704/** 4705 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4706 * @tx_resp: the Tx response from the fw (agg or non-agg) 4707 * 4708 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4709 * it can't know that everything will go well until the end of the AMPDU, it 4710 * can't know in advance the number of MPDUs that will be sent in the current 4711 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4712 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4713 * of the batch. This is why the SSN of the SCD is written at the end of the 4714 * whole struct at a variable offset. This function knows how to cope with the 4715 * variable offset and returns the SSN of the SCD. 4716 */ 4717static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4718{ 4719 return le32_to_cpup((uint32_t *)&tx_resp->status + 4720 tx_resp->frame_count) & 0xfff; 4721} 4722 4723/* 4724 * END mvm/fw-api-tx.h 4725 */ 4726 4727/* 4728 * BEGIN mvm/fw-api-scan.h 4729 */ 4730 4731/** 4732 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4733 * @token: 4734 * @sta_id: station id 4735 * @tid: 4736 * @scd_queue: scheduler queue to confiug 4737 * @enable: 1 queue enable, 0 queue disable 4738 * @aggregate: 1 aggregated queue, 0 otherwise 4739 * @tx_fifo: %enum iwm_mvm_tx_fifo 4740 * @window: BA window size 4741 * @ssn: SSN for the BA agreement 4742 */ 4743struct iwm_scd_txq_cfg_cmd { 4744 uint8_t token; 4745 uint8_t sta_id; 4746 uint8_t tid; 4747 uint8_t scd_queue; 4748 uint8_t enable; 4749 uint8_t aggregate; 4750 uint8_t tx_fifo; 4751 uint8_t window; 4752 uint16_t ssn; 4753 uint16_t reserved; 4754} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4755 4756/** 4757 * struct iwm_scd_txq_cfg_rsp 4758 * @token: taken from the command 4759 * @sta_id: station id from the command 4760 * @tid: tid from the command 4761 * @scd_queue: scd_queue from the command 4762 */ 4763struct iwm_scd_txq_cfg_rsp { 4764 uint8_t token; 4765 uint8_t sta_id; 4766 uint8_t tid; 4767 uint8_t scd_queue; 4768} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4769 4770 4771/* Scan Commands, Responses, Notifications */ 4772 4773/* Masks for iwm_scan_channel.type flags */ 4774#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4775#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4776 4777/* Max number of IEs for direct SSID scans in a command */ 4778#define IWM_PROBE_OPTION_MAX 20 4779 4780/** 4781 * struct iwm_ssid_ie - directed scan network information element 4782 * 4783 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4784 * selected by "type" bit field in struct iwm_scan_channel; 4785 * each channel may select different ssids from among the 20 entries. 4786 * SSID IEs get transmitted in reverse order of entry. 4787 */ 4788struct iwm_ssid_ie { 4789 uint8_t id; 4790 uint8_t len; 4791 uint8_t ssid[IEEE80211_NWID_LEN]; 4792} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4793 4794/* scan offload */ 4795#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4796#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4797#define IWM_SCAN_MAX_PROFILES 11 4798#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4799 4800/* Default watchdog (in MS) for scheduled scan iteration */ 4801#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4802 4803#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4804#define IWM_CAN_ABORT_STATUS 1 4805 4806#define IWM_FULL_SCAN_MULTIPLIER 5 4807#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4808#define IWM_MAX_SCHED_SCAN_PLANS 2 4809 4810/** 4811 * iwm_scan_schedule_lmac - schedule of scan offload 4812 * @delay: delay between iterations, in seconds. 4813 * @iterations: num of scan iterations 4814 * @full_scan_mul: number of partial scans before each full scan 4815 */ 4816struct iwm_scan_schedule_lmac { 4817 uint16_t delay; 4818 uint8_t iterations; 4819 uint8_t full_scan_mul; 4820} __packed; /* SCAN_SCHEDULE_API_S */ 4821 4822/** 4823 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4824 * @tx_flags: combination of TX_CMD_FLG_* 4825 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4826 * cleared. Combination of RATE_MCS_* 4827 * @sta_id: index of destination station in FW station table 4828 * @reserved: for alignment and future use 4829 */ 4830struct iwm_scan_req_tx_cmd { 4831 uint32_t tx_flags; 4832 uint32_t rate_n_flags; 4833 uint8_t sta_id; 4834 uint8_t reserved[3]; 4835} __packed; 4836 4837enum iwm_scan_channel_flags_lmac { 4838 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4839 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4840}; 4841 4842/** 4843 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4844 * @flags: bits 1-20: directed scan to i'th ssid 4845 * other bits &enum iwm_scan_channel_flags_lmac 4846 * @channel_number: channel number 1-13 etc 4847 * @iter_count: scan iteration on this channel 4848 * @iter_interval: interval in seconds between iterations on one channel 4849 */ 4850struct iwm_scan_channel_cfg_lmac { 4851 uint32_t flags; 4852 uint16_t channel_num; 4853 uint16_t iter_count; 4854 uint32_t iter_interval; 4855} __packed; 4856 4857/* 4858 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4859 * @offset: offset in the data block 4860 * @len: length of the segment 4861 */ 4862struct iwm_scan_probe_segment { 4863 uint16_t offset; 4864 uint16_t len; 4865} __packed; 4866 4867/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4868 * @mac_header: first (and common) part of the probe 4869 * @band_data: band specific data 4870 * @common_data: last (and common) part of the probe 4871 * @buf: raw data block 4872 */ 4873struct iwm_scan_probe_req { 4874 struct iwm_scan_probe_segment mac_header; 4875 struct iwm_scan_probe_segment band_data[2]; 4876 struct iwm_scan_probe_segment common_data; 4877 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4878} __packed; 4879 4880enum iwm_scan_channel_flags { 4881 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4882 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4883 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4884}; 4885 4886/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4887 * @flags: enum iwm_scan_channel_flags 4888 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4889 * involved. 4890 * 1 - EBS is disabled. 4891 * 2 - every second scan will be full scan(and so on). 4892 */ 4893struct iwm_scan_channel_opt { 4894 uint16_t flags; 4895 uint16_t non_ebs_ratio; 4896} __packed; 4897 4898/** 4899 * iwm_mvm_lmac_scan_flags 4900 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4901 * without filtering. 4902 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4903 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4904 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4905 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4906 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4907 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4908 * and DS parameter set IEs into probe requests. 4909 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4910 * 1, 6 and 11. 4911 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4912 */ 4913enum iwm_mvm_lmac_scan_flags { 4914 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4915 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4916 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4917 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4918 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4919 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4920 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4921 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4922 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4923}; 4924 4925enum iwm_scan_priority { 4926 IWM_SCAN_PRIORITY_LOW, 4927 IWM_SCAN_PRIORITY_MEDIUM, 4928 IWM_SCAN_PRIORITY_HIGH, 4929}; 4930 4931/** 4932 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4933 * @reserved1: for alignment and future use 4934 * @channel_num: num of channels to scan 4935 * @active-dwell: dwell time for active channels 4936 * @passive-dwell: dwell time for passive channels 4937 * @fragmented-dwell: dwell time for fragmented passive scan 4938 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4939 * @reserved2: for alignment and future use 4940 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4941 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4942 * @max_out_time: max time (in TU) to be out of associated channel 4943 * @suspend_time: pause scan this long (TUs) when returning to service channel 4944 * @flags: RXON flags 4945 * @filter_flags: RXON filter 4946 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4947 * @direct_scan: list of SSIDs for directed active scan 4948 * @scan_prio: enum iwm_scan_priority 4949 * @iter_num: number of scan iterations 4950 * @delay: delay in seconds before first iteration 4951 * @schedule: two scheduling plans. The first one is finite, the second one can 4952 * be infinite. 4953 * @channel_opt: channel optimization options, for full and partial scan 4954 * @data: channel configuration and probe request packet. 4955 */ 4956struct iwm_scan_req_lmac { 4957 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4958 uint32_t reserved1; 4959 uint8_t n_channels; 4960 uint8_t active_dwell; 4961 uint8_t passive_dwell; 4962 uint8_t fragmented_dwell; 4963 uint8_t extended_dwell; 4964 uint8_t reserved2; 4965 uint16_t rx_chain_select; 4966 uint32_t scan_flags; 4967 uint32_t max_out_time; 4968 uint32_t suspend_time; 4969 /* RX_ON_FLAGS_API_S_VER_1 */ 4970 uint32_t flags; 4971 uint32_t filter_flags; 4972 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4973 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4974 uint32_t scan_prio; 4975 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4976 uint32_t iter_num; 4977 uint32_t delay; 4978 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4979 struct iwm_scan_channel_opt channel_opt[2]; 4980 uint8_t data[]; 4981} __packed; 4982 4983/** 4984 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4985 * @last_schedule_line: last schedule line executed (fast or regular) 4986 * @last_schedule_iteration: last scan iteration executed before scan abort 4987 * @status: enum iwm_scan_offload_complete_status 4988 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4989 * @time_after_last_iter; time in seconds elapsed after last iteration 4990 */ 4991struct iwm_periodic_scan_complete { 4992 uint8_t last_schedule_line; 4993 uint8_t last_schedule_iteration; 4994 uint8_t status; 4995 uint8_t ebs_status; 4996 uint32_t time_after_last_iter; 4997 uint32_t reserved; 4998} __packed; 4999 5000/* How many statistics are gathered for each channel */ 5001#define IWM_SCAN_RESULTS_STATISTICS 1 5002 5003/** 5004 * enum iwm_scan_complete_status - status codes for scan complete notifications 5005 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5006 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5007 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5008 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5009 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5010 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5011 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5012 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5013 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5014 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5015 * (not an error!) 5016 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5017 * asked for 5018 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5019*/ 5020enum iwm_scan_complete_status { 5021 IWM_SCAN_COMP_STATUS_OK = 0x1, 5022 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5023 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5024 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5025 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5026 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5027 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5028 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5029 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5030 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5031 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5032 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5033}; 5034 5035/** 5036 * struct iwm_scan_results_notif - scan results for one channel 5037 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5038 * @channel: which channel the results are from 5039 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5040 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5041 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5042 * @duration: duration spent in channel, in usecs 5043 * @statistics: statistics gathered for this channel 5044 */ 5045struct iwm_scan_results_notif { 5046 uint8_t channel; 5047 uint8_t band; 5048 uint8_t probe_status; 5049 uint8_t num_probe_not_sent; 5050 uint32_t duration; 5051 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5052} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5053 5054enum iwm_scan_framework_client { 5055 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5056 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5057 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5058}; 5059 5060/** 5061 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5062 * @ssid: MAC address to filter out 5063 * @reported_rssi: AP rssi reported to the host 5064 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5065 */ 5066struct iwm_scan_offload_blacklist { 5067 uint8_t ssid[IEEE80211_ADDR_LEN]; 5068 uint8_t reported_rssi; 5069 uint8_t client_bitmap; 5070} __packed; 5071 5072enum iwm_scan_offload_network_type { 5073 IWM_NETWORK_TYPE_BSS = 1, 5074 IWM_NETWORK_TYPE_IBSS = 2, 5075 IWM_NETWORK_TYPE_ANY = 3, 5076}; 5077 5078enum iwm_scan_offload_band_selection { 5079 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5080 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5081 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5082}; 5083 5084/** 5085 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5086 * @ssid_index: index to ssid list in fixed part 5087 * @unicast_cipher: encryption olgorithm to match - bitmap 5088 * @aut_alg: authentication olgorithm to match - bitmap 5089 * @network_type: enum iwm_scan_offload_network_type 5090 * @band_selection: enum iwm_scan_offload_band_selection 5091 * @client_bitmap: clients waiting for match - enum scan_framework_client 5092 */ 5093struct iwm_scan_offload_profile { 5094 uint8_t ssid_index; 5095 uint8_t unicast_cipher; 5096 uint8_t auth_alg; 5097 uint8_t network_type; 5098 uint8_t band_selection; 5099 uint8_t client_bitmap; 5100 uint8_t reserved[2]; 5101} __packed; 5102 5103/** 5104 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5105 * @blaclist: AP list to filter off from scan results 5106 * @profiles: profiles to search for match 5107 * @blacklist_len: length of blacklist 5108 * @num_profiles: num of profiles in the list 5109 * @match_notify: clients waiting for match found notification 5110 * @pass_match: clients waiting for the results 5111 * @active_clients: active clients bitmap - enum scan_framework_client 5112 * @any_beacon_notify: clients waiting for match notification without match 5113 */ 5114struct iwm_scan_offload_profile_cfg { 5115 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5116 uint8_t blacklist_len; 5117 uint8_t num_profiles; 5118 uint8_t match_notify; 5119 uint8_t pass_match; 5120 uint8_t active_clients; 5121 uint8_t any_beacon_notify; 5122 uint8_t reserved[2]; 5123} __packed; 5124 5125enum iwm_scan_offload_complete_status { 5126 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5127 IWM_SCAN_OFFLOAD_ABORTED = 2, 5128}; 5129 5130/** 5131 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5132 * SCAN_COMPLETE_NTF_API_S_VER_3 5133 * @scanned_channels: number of channels scanned (and number of valid results) 5134 * @status: one of SCAN_COMP_STATUS_* 5135 * @bt_status: BT on/off status 5136 * @last_channel: last channel that was scanned 5137 * @tsf_low: TSF timer (lower half) in usecs 5138 * @tsf_high: TSF timer (higher half) in usecs 5139 * @results: an array of scan results, only "scanned_channels" of them are valid 5140 */ 5141struct iwm_lmac_scan_complete_notif { 5142 uint8_t scanned_channels; 5143 uint8_t status; 5144 uint8_t bt_status; 5145 uint8_t last_channel; 5146 uint32_t tsf_low; 5147 uint32_t tsf_high; 5148 struct iwm_scan_results_notif results[]; 5149} __packed; 5150 5151 5152/* 5153 * END mvm/fw-api-scan.h 5154 */ 5155 5156/* 5157 * BEGIN mvm/fw-api-sta.h 5158 */ 5159 5160/* UMAC Scan API */ 5161 5162/* The maximum of either of these cannot exceed 8, because we use an 5163 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5164 */ 5165#define IWM_MVM_MAX_UMAC_SCANS 8 5166#define IWM_MVM_MAX_LMAC_SCANS 1 5167 5168enum iwm_scan_config_flags { 5169 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5170 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5171 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5172 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5173 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5174 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5175 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5176 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5177 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5178 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5179 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5180 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5181 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5182 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5183 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5184 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5185 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5186 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5187 5188 /* Bits 26-31 are for num of channels in channel_array */ 5189#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5190}; 5191 5192enum iwm_scan_config_rates { 5193 /* OFDM basic rates */ 5194 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5195 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5196 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5197 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5198 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5199 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5200 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5201 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5202 /* CCK basic rates */ 5203 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5204 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5205 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5206 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5207 5208 /* Bits 16-27 are for supported rates */ 5209#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5210}; 5211 5212enum iwm_channel_flags { 5213 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5214 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5215 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5216 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5217}; 5218 5219/** 5220 * struct iwm_scan_config 5221 * @flags: enum scan_config_flags 5222 * @tx_chains: valid_tx antenna - ANT_* definitions 5223 * @rx_chains: valid_rx antenna - ANT_* definitions 5224 * @legacy_rates: default legacy rates - enum scan_config_rates 5225 * @out_of_channel_time: default max out of serving channel time 5226 * @suspend_time: default max suspend time 5227 * @dwell_active: default dwell time for active scan 5228 * @dwell_passive: default dwell time for passive scan 5229 * @dwell_fragmented: default dwell time for fragmented scan 5230 * @dwell_extended: default dwell time for channels 1, 6 and 11 5231 * @mac_addr: default mac address to be used in probes 5232 * @bcast_sta_id: the index of the station in the fw 5233 * @channel_flags: default channel flags - enum iwm_channel_flags 5234 * scan_config_channel_flag 5235 * @channel_array: default supported channels 5236 */ 5237struct iwm_scan_config { 5238 uint32_t flags; 5239 uint32_t tx_chains; 5240 uint32_t rx_chains; 5241 uint32_t legacy_rates; 5242 uint32_t out_of_channel_time; 5243 uint32_t suspend_time; 5244 uint8_t dwell_active; 5245 uint8_t dwell_passive; 5246 uint8_t dwell_fragmented; 5247 uint8_t dwell_extended; 5248 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5249 uint8_t bcast_sta_id; 5250 uint8_t channel_flags; 5251 uint8_t channel_array[]; 5252} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5253 5254/** 5255 * iwm_umac_scan_flags 5256 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5257 * can be preempted by other scan requests with higher priority. 5258 * The low priority scan will be resumed when the higher proirity scan is 5259 * completed. 5260 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5261 * when scan starts. 5262 */ 5263enum iwm_umac_scan_flags { 5264 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5265 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5266}; 5267 5268enum iwm_umac_scan_uid_offsets { 5269 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5270 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5271}; 5272 5273enum iwm_umac_scan_general_flags { 5274 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5275 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5276 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5277 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5278 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5279 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5280 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5281 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5282 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5283 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5284 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5285}; 5286 5287/** 5288 * struct iwm_scan_channel_cfg_umac 5289 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5290 * @channel_num: channel number 1-13 etc. 5291 * @iter_count: repetition count for the channel. 5292 * @iter_interval: interval between two scan iterations on one channel. 5293 */ 5294struct iwm_scan_channel_cfg_umac { 5295 uint32_t flags; 5296#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5297 5298 uint8_t channel_num; 5299 uint8_t iter_count; 5300 uint16_t iter_interval; 5301} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5302 5303/** 5304 * struct iwm_scan_umac_schedule 5305 * @interval: interval in seconds between scan iterations 5306 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5307 * @reserved: for alignment and future use 5308 */ 5309struct iwm_scan_umac_schedule { 5310 uint16_t interval; 5311 uint8_t iter_count; 5312 uint8_t reserved; 5313} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5314 5315/** 5316 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5317 * parameters following channels configuration array. 5318 * @schedule: two scheduling plans. 5319 * @delay: delay in TUs before starting the first scan iteration 5320 * @reserved: for future use and alignment 5321 * @preq: probe request with IEs blocks 5322 * @direct_scan: list of SSIDs for directed active scan 5323 */ 5324struct iwm_scan_req_umac_tail { 5325 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5326 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5327 uint16_t delay; 5328 uint16_t reserved; 5329 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5330 struct iwm_scan_probe_req preq; 5331 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5332} __packed; 5333 5334/** 5335 * struct iwm_scan_req_umac 5336 * @flags: &enum iwm_umac_scan_flags 5337 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5338 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5339 * @general_flags: &enum iwm_umac_scan_general_flags 5340 * @extended_dwell: dwell time for channels 1, 6 and 11 5341 * @active_dwell: dwell time for active scan 5342 * @passive_dwell: dwell time for passive scan 5343 * @fragmented_dwell: dwell time for fragmented passive scan 5344 * @max_out_time: max out of serving channel time 5345 * @suspend_time: max suspend time 5346 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5347 * @channel_flags: &enum iwm_scan_channel_flags 5348 * @n_channels: num of channels in scan request 5349 * @reserved: for future use and alignment 5350 * @data: &struct iwm_scan_channel_cfg_umac and 5351 * &struct iwm_scan_req_umac_tail 5352 */ 5353struct iwm_scan_req_umac { 5354 uint32_t flags; 5355 uint32_t uid; 5356 uint32_t ooc_priority; 5357 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5358 uint32_t general_flags; 5359 uint8_t extended_dwell; 5360 uint8_t active_dwell; 5361 uint8_t passive_dwell; 5362 uint8_t fragmented_dwell; 5363 uint32_t max_out_time; 5364 uint32_t suspend_time; 5365 uint32_t scan_priority; 5366 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5367 uint8_t channel_flags; 5368 uint8_t n_channels; 5369 uint16_t reserved; 5370 uint8_t data[]; 5371} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5372 5373/** 5374 * struct iwm_umac_scan_abort 5375 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5376 * @flags: reserved 5377 */ 5378struct iwm_umac_scan_abort { 5379 uint32_t uid; 5380 uint32_t flags; 5381} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5382 5383/** 5384 * struct iwm_umac_scan_complete 5385 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5386 * @last_schedule: last scheduling line 5387 * @last_iter: last scan iteration number 5388 * @scan status: &enum iwm_scan_offload_complete_status 5389 * @ebs_status: &enum iwm_scan_ebs_status 5390 * @time_from_last_iter: time elapsed from last iteration 5391 * @reserved: for future use 5392 */ 5393struct iwm_umac_scan_complete { 5394 uint32_t uid; 5395 uint8_t last_schedule; 5396 uint8_t last_iter; 5397 uint8_t status; 5398 uint8_t ebs_status; 5399 uint32_t time_from_last_iter; 5400 uint32_t reserved; 5401} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5402 5403#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5404/** 5405 * struct iwm_scan_offload_profile_match - match information 5406 * @bssid: matched bssid 5407 * @channel: channel where the match occurred 5408 * @energy: 5409 * @matching_feature: 5410 * @matching_channels: bitmap of channels that matched, referencing 5411 * the channels passed in tue scan offload request 5412 */ 5413struct iwm_scan_offload_profile_match { 5414 uint8_t bssid[IEEE80211_ADDR_LEN]; 5415 uint16_t reserved; 5416 uint8_t channel; 5417 uint8_t energy; 5418 uint8_t matching_feature; 5419 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5420} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5421 5422/** 5423 * struct iwm_scan_offload_profiles_query - match results query response 5424 * @matched_profiles: bitmap of matched profiles, referencing the 5425 * matches passed in the scan offload request 5426 * @last_scan_age: age of the last offloaded scan 5427 * @n_scans_done: number of offloaded scans done 5428 * @gp2_d0u: GP2 when D0U occurred 5429 * @gp2_invoked: GP2 when scan offload was invoked 5430 * @resume_while_scanning: not used 5431 * @self_recovery: obsolete 5432 * @reserved: reserved 5433 * @matches: array of match information, one for each match 5434 */ 5435struct iwm_scan_offload_profiles_query { 5436 uint32_t matched_profiles; 5437 uint32_t last_scan_age; 5438 uint32_t n_scans_done; 5439 uint32_t gp2_d0u; 5440 uint32_t gp2_invoked; 5441 uint8_t resume_while_scanning; 5442 uint8_t self_recovery; 5443 uint16_t reserved; 5444 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5445} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5446 5447/** 5448 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5449 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5450 * @scanned_channels: number of channels scanned and number of valid elements in 5451 * results array 5452 * @status: one of SCAN_COMP_STATUS_* 5453 * @bt_status: BT on/off status 5454 * @last_channel: last channel that was scanned 5455 * @tsf_low: TSF timer (lower half) in usecs 5456 * @tsf_high: TSF timer (higher half) in usecs 5457 * @results: array of scan results, only "scanned_channels" of them are valid 5458 */ 5459struct iwm_umac_scan_iter_complete_notif { 5460 uint32_t uid; 5461 uint8_t scanned_channels; 5462 uint8_t status; 5463 uint8_t bt_status; 5464 uint8_t last_channel; 5465 uint32_t tsf_low; 5466 uint32_t tsf_high; 5467 struct iwm_scan_results_notif results[]; 5468} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5469 5470/* Please keep this enum *SORTED* by hex value. 5471 * Needed for binary search, otherwise a warning will be triggered. 5472 */ 5473enum iwm_scan_subcmd_ids { 5474 IWM_GSCAN_START_CMD = 0x0, 5475 IWM_GSCAN_STOP_CMD = 0x1, 5476 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5477 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5478 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5479 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5480 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5481 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5482 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5483}; 5484 5485/* STA API */ 5486 5487/** 5488 * enum iwm_sta_flags - flags for the ADD_STA host command 5489 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5490 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5491 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5492 * @IWM_STA_FLG_PS: set if STA is in Power Save 5493 * @IWM_STA_FLG_INVALID: set if STA is invalid 5494 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5495 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5496 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5497 * @IWM_STA_FLG_PAN: STA is for PAN interface 5498 * @IWM_STA_FLG_CLASS_AUTH: 5499 * @IWM_STA_FLG_CLASS_ASSOC: 5500 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5501 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5502 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5503 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5504 * initialised by driver and can be updated by fw upon reception of 5505 * action frames that can change the channel width. When cleared the fw 5506 * will send all the frames in 20MHz even when FAT channel is requested. 5507 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5508 * driver and can be updated by fw upon reception of action frames. 5509 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5510 */ 5511enum iwm_sta_flags { 5512 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5513 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5514 5515 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5516 5517 IWM_STA_FLG_PS = (1 << 8), 5518 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5519 IWM_STA_FLG_PAN = (1 << 13), 5520 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5521 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5522 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5523 5524 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5525 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5526 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5527 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5528 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5529 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5530 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5531 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5532 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5533 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5534 5535 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5536 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5537 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5538 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5539 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5540 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5541 5542 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5543 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5544 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5545 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5546 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5547 5548 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5549 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5550 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5551 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5552}; 5553 5554/** 5555 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5556 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5557 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5558 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5559 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5560 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5561 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5562 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5563 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5564 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5565 * station info array (1 - n 1X mode) 5566 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5567 * @IWM_STA_KEY_NOT_VALID: key is invalid 5568 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5569 * @IWM_STA_KEY_MULTICAST: set for multical key 5570 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5571 */ 5572enum iwm_sta_key_flag { 5573 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5574 IWM_STA_KEY_FLG_WEP = (1 << 0), 5575 IWM_STA_KEY_FLG_CCM = (2 << 0), 5576 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5577 IWM_STA_KEY_FLG_EXT = (4 << 0), 5578 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5579 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5580 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5581 5582 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5583 IWM_STA_KEY_FLG_KEYID_POS = 8, 5584 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5585 IWM_STA_KEY_NOT_VALID = (1 << 11), 5586 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5587 IWM_STA_KEY_MULTICAST = (1 << 14), 5588 IWM_STA_KEY_MFP = (1 << 15), 5589}; 5590 5591/** 5592 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5593 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5594 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5595 * @IWM_STA_MODIFY_TX_RATE: unused 5596 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5597 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5598 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5599 * @IWM_STA_MODIFY_PROT_TH: 5600 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5601 */ 5602enum iwm_sta_modify_flag { 5603 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5604 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5605 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5606 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5607 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5608 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5609 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5610 IWM_STA_MODIFY_QUEUES = (1 << 7), 5611}; 5612 5613#define IWM_STA_MODE_MODIFY 1 5614 5615/** 5616 * enum iwm_sta_sleep_flag - type of sleep of the station 5617 * @IWM_STA_SLEEP_STATE_AWAKE: 5618 * @IWM_STA_SLEEP_STATE_PS_POLL: 5619 * @IWM_STA_SLEEP_STATE_UAPSD: 5620 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5621 * (last) released frame 5622 */ 5623enum iwm_sta_sleep_flag { 5624 IWM_STA_SLEEP_STATE_AWAKE = 0, 5625 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5626 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5627 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5628}; 5629 5630/* STA ID and color bits definitions */ 5631#define IWM_STA_ID_SEED (0x0f) 5632#define IWM_STA_ID_POS (0) 5633#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5634 5635#define IWM_STA_COLOR_SEED (0x7) 5636#define IWM_STA_COLOR_POS (4) 5637#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5638 5639#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5640 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5641#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5642 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5643 5644#define IWM_STA_KEY_MAX_NUM (16) 5645#define IWM_STA_KEY_IDX_INVALID (0xff) 5646#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5647#define IWM_MAX_GLOBAL_KEYS (4) 5648#define IWM_STA_KEY_LEN_WEP40 (5) 5649#define IWM_STA_KEY_LEN_WEP104 (13) 5650 5651/** 5652 * struct iwm_mvm_keyinfo - key information 5653 * @key_flags: type %iwm_sta_key_flag 5654 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5655 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5656 * @key_offset: key offset in the fw's key table 5657 * @key: 16-byte unicast decryption key 5658 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5659 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5660 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5661 */ 5662struct iwm_mvm_keyinfo { 5663 uint16_t key_flags; 5664 uint8_t tkip_rx_tsc_byte2; 5665 uint8_t reserved1; 5666 uint16_t tkip_rx_ttak[5]; 5667 uint8_t key_offset; 5668 uint8_t reserved2; 5669 uint8_t key[16]; 5670 uint64_t tx_secur_seq_cnt; 5671 uint64_t hw_tkip_mic_rx_key; 5672 uint64_t hw_tkip_mic_tx_key; 5673} __packed; 5674 5675#define IWM_ADD_STA_STATUS_MASK 0xFF 5676#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5677#define IWM_ADD_STA_BAID_MASK 0x7F00 5678#define IWM_ADD_STA_BAID_SHIFT 8 5679 5680/** 5681 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5682 * ( REPLY_ADD_STA = 0x18 ) 5683 * @add_modify: 1: modify existing, 0: add new station 5684 * @awake_acs: 5685 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5686 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5687 * @mac_id_n_color: the Mac context this station belongs to 5688 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5689 * @sta_id: index of station in uCode's station table 5690 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5691 * alone. 1 - modify, 0 - don't change. 5692 * @station_flags: look at %iwm_sta_flags 5693 * @station_flags_msk: what of %station_flags have changed 5694 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5695 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5696 * add_immediate_ba_ssn. 5697 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5698 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5699 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5700 * add_immediate_ba_tid. 5701 * @sleep_tx_count: number of packets to transmit to station even though it is 5702 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5703 * keeps track of STA sleep state. 5704 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5705 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5706 * mac-addr. 5707 * @beamform_flags: beam forming controls 5708 * @tfd_queue_msk: tfd queues used by this station 5709 * 5710 * The device contains an internal table of per-station information, with info 5711 * on security keys, aggregation parameters, and Tx rates for initial Tx 5712 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5713 * 5714 * ADD_STA sets up the table entry for one station, either creating a new 5715 * entry, or modifying a pre-existing one. 5716 */ 5717struct iwm_mvm_add_sta_cmd_v7 { 5718 uint8_t add_modify; 5719 uint8_t awake_acs; 5720 uint16_t tid_disable_tx; 5721 uint32_t mac_id_n_color; 5722 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5723 uint16_t reserved2; 5724 uint8_t sta_id; 5725 uint8_t modify_mask; 5726 uint16_t reserved3; 5727 uint32_t station_flags; 5728 uint32_t station_flags_msk; 5729 uint8_t add_immediate_ba_tid; 5730 uint8_t remove_immediate_ba_tid; 5731 uint16_t add_immediate_ba_ssn; 5732 uint16_t sleep_tx_count; 5733 uint16_t sleep_state_flags; 5734 uint16_t assoc_id; 5735 uint16_t beamform_flags; 5736 uint32_t tfd_queue_msk; 5737} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5738 5739/** 5740 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5741 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5742 * @sta_id: index of station in uCode's station table 5743 * @key_offset: key offset in key storage 5744 * @key_flags: type %iwm_sta_key_flag 5745 * @key: key material data 5746 * @key2: key material data 5747 * @rx_secur_seq_cnt: RX security sequence counter for the key 5748 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5749 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5750 */ 5751struct iwm_mvm_add_sta_key_cmd { 5752 uint8_t sta_id; 5753 uint8_t key_offset; 5754 uint16_t key_flags; 5755 uint8_t key[16]; 5756 uint8_t key2[16]; 5757 uint8_t rx_secur_seq_cnt[16]; 5758 uint8_t tkip_rx_tsc_byte2; 5759 uint8_t reserved; 5760 uint16_t tkip_rx_ttak[5]; 5761} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5762 5763/** 5764 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5765 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5766 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5767 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5768 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5769 * that doesn't exist. 5770 */ 5771enum iwm_mvm_add_sta_rsp_status { 5772 IWM_ADD_STA_SUCCESS = 0x1, 5773 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5774 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5775 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5776}; 5777 5778/** 5779 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5780 * ( IWM_REMOVE_STA = 0x19 ) 5781 * @sta_id: the station id of the station to be removed 5782 */ 5783struct iwm_mvm_rm_sta_cmd { 5784 uint8_t sta_id; 5785 uint8_t reserved[3]; 5786} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5787 5788/** 5789 * struct iwm_mvm_mgmt_mcast_key_cmd 5790 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5791 * @ctrl_flags: %iwm_sta_key_flag 5792 * @IGTK: 5793 * @K1: IGTK master key 5794 * @K2: IGTK sub key 5795 * @sta_id: station ID that support IGTK 5796 * @key_id: 5797 * @receive_seq_cnt: initial RSC/PN needed for replay check 5798 */ 5799struct iwm_mvm_mgmt_mcast_key_cmd { 5800 uint32_t ctrl_flags; 5801 uint8_t IGTK[16]; 5802 uint8_t K1[16]; 5803 uint8_t K2[16]; 5804 uint32_t key_id; 5805 uint32_t sta_id; 5806 uint64_t receive_seq_cnt; 5807} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5808 5809struct iwm_mvm_wep_key { 5810 uint8_t key_index; 5811 uint8_t key_offset; 5812 uint16_t reserved1; 5813 uint8_t key_size; 5814 uint8_t reserved2[3]; 5815 uint8_t key[16]; 5816} __packed; 5817 5818struct iwm_mvm_wep_key_cmd { 5819 uint32_t mac_id_n_color; 5820 uint8_t num_keys; 5821 uint8_t decryption_type; 5822 uint8_t flags; 5823 uint8_t reserved; 5824 struct iwm_mvm_wep_key wep_key[0]; 5825} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5826 5827/* 5828 * END mvm/fw-api-sta.h 5829 */ 5830 5831/* 5832 * BT coex 5833 */ 5834 5835enum iwm_bt_coex_mode { 5836 IWM_BT_COEX_DISABLE = 0x0, 5837 IWM_BT_COEX_NW = 0x1, 5838 IWM_BT_COEX_BT = 0x2, 5839 IWM_BT_COEX_WIFI = 0x3, 5840}; /* BT_COEX_MODES_E */ 5841 5842enum iwm_bt_coex_enabled_modules { 5843 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5844 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5845 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5846 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5847 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5848}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5849 5850/** 5851 * struct iwm_bt_coex_cmd - bt coex configuration command 5852 * @mode: enum %iwm_bt_coex_mode 5853 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5854 * 5855 * The structure is used for the BT_COEX command. 5856 */ 5857struct iwm_bt_coex_cmd { 5858 uint32_t mode; 5859 uint32_t enabled_modules; 5860} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5861 5862 5863/* 5864 * Location Aware Regulatory (LAR) API - MCC updates 5865 */ 5866 5867/** 5868 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5869 * regulatory profile according to the given MCC (Mobile Country Code). 5870 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5871 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5872 * MCC in the cmd response will be the relevant MCC in the NVM. 5873 * @mcc: given mobile country code 5874 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5875 * @reserved: reserved for alignment 5876 */ 5877struct iwm_mcc_update_cmd_v1 { 5878 uint16_t mcc; 5879 uint8_t source_id; 5880 uint8_t reserved; 5881} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5882 5883/** 5884 * struct iwm_mcc_update_cmd - Request the device to update geographic 5885 * regulatory profile according to the given MCC (Mobile Country Code). 5886 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5887 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5888 * MCC in the cmd response will be the relevant MCC in the NVM. 5889 * @mcc: given mobile country code 5890 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5891 * @reserved: reserved for alignment 5892 * @key: integrity key for MCC API OEM testing 5893 * @reserved2: reserved 5894 */ 5895struct iwm_mcc_update_cmd { 5896 uint16_t mcc; 5897 uint8_t source_id; 5898 uint8_t reserved; 5899 uint32_t key; 5900 uint32_t reserved2[5]; 5901} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5902 5903/** 5904 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5905 * Contains the new channel control profile map, if changed, and the new MCC 5906 * (mobile country code). 5907 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5908 * @status: see &enum iwm_mcc_update_status 5909 * @mcc: the new applied MCC 5910 * @cap: capabilities for all channels which matches the MCC 5911 * @source_id: the MCC source, see iwm_mcc_source 5912 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5913 * channels, depending on platform) 5914 * @channels: channel control data map, DWORD for each channel. Only the first 5915 * 16bits are used. 5916 */ 5917struct iwm_mcc_update_resp_v1 { 5918 uint32_t status; 5919 uint16_t mcc; 5920 uint8_t cap; 5921 uint8_t source_id; 5922 uint32_t n_channels; 5923 uint32_t channels[0]; 5924} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5925 5926/** 5927 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5928 * Contains the new channel control profile map, if changed, and the new MCC 5929 * (mobile country code). 5930 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5931 * @status: see &enum iwm_mcc_update_status 5932 * @mcc: the new applied MCC 5933 * @cap: capabilities for all channels which matches the MCC 5934 * @source_id: the MCC source, see iwm_mcc_source 5935 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5936 * @reserved: reserved. 5937 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5938 * channels, depending on platform) 5939 * @channels: channel control data map, DWORD for each channel. Only the first 5940 * 16bits are used. 5941 */ 5942struct iwm_mcc_update_resp { 5943 uint32_t status; 5944 uint16_t mcc; 5945 uint8_t cap; 5946 uint8_t source_id; 5947 uint16_t time; 5948 uint16_t reserved; 5949 uint32_t n_channels; 5950 uint32_t channels[0]; 5951} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5952 5953/** 5954 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5955 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5956 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5957 * the cellular and connectivity cores that gets updates of the mcc, and 5958 * notifies the ucode directly of any mcc change. 5959 * The ucode requests the driver to request the device to update geographic 5960 * regulatory profile according to the given MCC (Mobile Country Code). 5961 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5962 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5963 * MCC in the cmd response will be the relevant MCC in the NVM. 5964 * @mcc: given mobile country code 5965 * @source_id: identity of the change originator, see iwm_mcc_source 5966 * @reserved1: reserved for alignment 5967 */ 5968struct iwm_mcc_chub_notif { 5969 uint16_t mcc; 5970 uint8_t source_id; 5971 uint8_t reserved1; 5972} __packed; /* LAR_MCC_NOTIFY_S */ 5973 5974enum iwm_mcc_update_status { 5975 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5976 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5977 IWM_MCC_RESP_INVALID, 5978 IWM_MCC_RESP_NVM_DISABLED, 5979 IWM_MCC_RESP_ILLEGAL, 5980 IWM_MCC_RESP_LOW_PRIORITY, 5981 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5982 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5983 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5984}; 5985 5986enum iwm_mcc_source { 5987 IWM_MCC_SOURCE_OLD_FW = 0, 5988 IWM_MCC_SOURCE_ME = 1, 5989 IWM_MCC_SOURCE_BIOS = 2, 5990 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5991 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5992 IWM_MCC_SOURCE_WIFI = 5, 5993 IWM_MCC_SOURCE_RESERVED = 6, 5994 IWM_MCC_SOURCE_DEFAULT = 7, 5995 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5996 IWM_MCC_SOURCE_MCC_API = 9, 5997 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5998 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5999}; 6000 6001/** 6002 * struct iwm_dts_measurement_notif_v1 - measurements notification 6003 * 6004 * @temp: the measured temperature 6005 * @voltage: the measured voltage 6006 */ 6007struct iwm_dts_measurement_notif_v1 { 6008 int32_t temp; 6009 int32_t voltage; 6010} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 6011 6012/** 6013 * struct iwm_dts_measurement_notif_v2 - measurements notification 6014 * 6015 * @temp: the measured temperature 6016 * @voltage: the measured voltage 6017 * @threshold_idx: the trip index that was crossed 6018 */ 6019struct iwm_dts_measurement_notif_v2 { 6020 int32_t temp; 6021 int32_t voltage; 6022 int32_t threshold_idx; 6023} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 6024 6025/* 6026 * Some cherry-picked definitions 6027 */ 6028 6029#define IWM_FRAME_LIMIT 64 6030 6031/* 6032 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6033 * As the firmware is slowly running out of command IDs and grouping of 6034 * commands is desirable anyway, the firmware is extending the command 6035 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6036 * former flags field, since that's always 0 on commands and thus can 6037 * be easily used to distinguish between the two). 6038 * 6039 * These functions retrieve specific information from the id field in 6040 * the iwm_host_cmd struct which contains the command id, the group id, 6041 * and the version of the command. 6042*/ 6043static inline uint8_t 6044iwm_cmd_opcode(uint32_t cmdid) 6045{ 6046 return cmdid & 0xff; 6047} 6048 6049static inline uint8_t 6050iwm_cmd_groupid(uint32_t cmdid) 6051{ 6052 return ((cmdid & 0Xff00) >> 8); 6053} 6054 6055static inline uint8_t 6056iwm_cmd_version(uint32_t cmdid) 6057{ 6058 return ((cmdid & 0xff0000) >> 16); 6059} 6060 6061static inline uint32_t 6062iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6063{ 6064 return opcode + (groupid << 8) + (version << 16); 6065} 6066 6067/* make uint16_t wide id out of uint8_t group and opcode */ 6068#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6069 6070/* due to the conversion, this group is special */ 6071#define IWM_ALWAYS_LONG_GROUP 1 6072 6073struct iwm_cmd_header { 6074 uint8_t code; 6075 uint8_t flags; 6076 uint8_t idx; 6077 uint8_t qid; 6078} __packed; 6079 6080struct iwm_cmd_header_wide { 6081 uint8_t opcode; 6082 uint8_t group_id; 6083 uint8_t idx; 6084 uint8_t qid; 6085 uint16_t length; 6086 uint8_t reserved; 6087 uint8_t version; 6088} __packed; 6089 6090enum iwm_power_scheme { 6091 IWM_POWER_SCHEME_CAM = 1, 6092 IWM_POWER_SCHEME_BPS, 6093 IWM_POWER_SCHEME_LP 6094}; 6095 6096#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6097#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6098#define IWM_CMD_FAILED_MSK 0x40 6099 6100/** 6101 * struct iwm_device_cmd 6102 * 6103 * For allocation of the command and tx queues, this establishes the overall 6104 * size of the largest command we send to uCode, except for commands that 6105 * aren't fully copied and use other TFD space. 6106 */ 6107struct iwm_device_cmd { 6108 union { 6109 struct { 6110 struct iwm_cmd_header hdr; 6111 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6112 }; 6113 struct { 6114 struct iwm_cmd_header_wide hdr_wide; 6115 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6116 sizeof(struct iwm_cmd_header_wide) + 6117 sizeof(struct iwm_cmd_header)]; 6118 }; 6119 }; 6120} __packed; 6121 6122struct iwm_rx_packet { 6123 /* 6124 * The first 4 bytes of the RX frame header contain both the RX frame 6125 * size and some flags. 6126 * Bit fields: 6127 * 31: flag flush RB request 6128 * 30: flag ignore TC (terminal counter) request 6129 * 29: flag fast IRQ request 6130 * 28-14: Reserved 6131 * 13-00: RX frame size 6132 */ 6133 uint32_t len_n_flags; 6134 struct iwm_cmd_header hdr; 6135 uint8_t data[]; 6136} __packed; 6137 6138#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6139 6140static inline uint32_t 6141iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6142{ 6143 6144 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6145} 6146 6147static inline uint32_t 6148iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6149{ 6150 6151 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6152} 6153 6154 6155#define IWM_MIN_DBM -100 6156#define IWM_MAX_DBM -33 /* realistic guess */ 6157 6158#define IWM_READ(sc, reg) \ 6159 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6160 6161#define IWM_WRITE(sc, reg, val) \ 6162 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6163 6164#define IWM_WRITE_1(sc, reg, val) \ 6165 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6166 6167#define IWM_SETBITS(sc, reg, mask) \ 6168 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6169 6170#define IWM_CLRBITS(sc, reg, mask) \ 6171 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6172 6173#define IWM_BARRIER_WRITE(sc) \ 6174 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6175 BUS_SPACE_BARRIER_WRITE) 6176 6177#define IWM_BARRIER_READ_WRITE(sc) \ 6178 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6179 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6180 6181#endif /* __IF_IWM_REG_H__ */ 6182