if_iwmreg.h revision 330162
1/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2/* $FreeBSD: stable/11/sys/dev/iwm/if_iwmreg.h 330162 2018-03-01 05:09:08Z eadler $ */ 3 4/****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66#ifndef __IF_IWM_REG_H__ 67#define __IF_IWM_REG_H__ 68 69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72/* 73 * BEGIN iwl-csr.h 74 */ 75 76/* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101#define IWM_CSR_GP_CNTRL (0x024) 102 103/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104#define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106/* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114#define IWM_CSR_HW_REV (0x028) 115 116/* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122#define IWM_CSR_EEPROM_REG (0x02c) 123#define IWM_CSR_EEPROM_GP (0x030) 124#define IWM_CSR_OTP_GP_REG (0x034) 125 126#define IWM_CSR_GIO_REG (0x03C) 127#define IWM_CSR_GP_UCODE_REG (0x048) 128#define IWM_CSR_GP_DRIVER_REG (0x050) 129 130/* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139#define IWM_CSR_MBOX_SET_REG (0x088) 140#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142#define IWM_CSR_LED_REG (0x094) 143#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147/* GIO Chicken Bits (PCI Express bus link power management) */ 148#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150/* Analog phase-lock-loop configuration */ 151#define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153/* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161#define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233/* GPIO */ 234#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238/* RESET */ 239#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246/* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296/* HW REV */ 297#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300/** 301 * hw_rev values 302 */ 303enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307}; 308 309 310#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329/* EEPROM REG */ 330#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335/* EEPROM GP */ 336#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343/* One-time-programmable memory general purpose reg */ 344#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349/* GP REG */ 350#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357/* CSR GIO */ 358#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360/* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394/* GP Driver */ 395#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404/* GIO Chicken Bits (PCI Express bus link power management) */ 405#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408/* LED */ 409#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410#define IWM_CSR_LED_REG_TURN_ON (0x60) 411#define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413/* ANA_PLL */ 414#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416/* HPET MEM debug */ 417#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419/* DRAM INT TABLE */ 420#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424/* SECURE boot registers */ 425#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429}; 430 431#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439}; 440 441#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442#define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 443enum iwm_secure_load_status_reg { 444 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 445 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 446 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 447 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 448 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 449}; 450#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 451 452#define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 453#define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 454#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 455#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 456 457#define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 458#define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 459#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 460#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 461 462#define IWM_CSR_SECURE_TIME_OUT (100) 463 464/* extended range in FW SRAM */ 465#define IWM_FW_MEM_EXTENDED_START 0x40000 466#define IWM_FW_MEM_EXTENDED_END 0x57FFF 467 468/* FW chicken bits */ 469#define IWM_LMPM_CHICK 0xa01ff8 470#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 471 472#define IWM_FH_TCSR_0_REG0 (0x1D00) 473 474/* 475 * HBUS (Host-side Bus) 476 * 477 * HBUS registers are mapped directly into PCI bus space, but are used 478 * to indirectly access device's internal memory or registers that 479 * may be powered-down. 480 * 481 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 482 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 483 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 484 * internal resources. 485 * 486 * Do not use iwl_write32()/iwl_read32() family to access these registers; 487 * these provide only simple PCI bus access, without waking up the MAC. 488 */ 489#define IWM_HBUS_BASE (0x400) 490 491/* 492 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 493 * structures, error log, event log, verifying uCode load). 494 * First write to address register, then read from or write to data register 495 * to complete the job. Once the address register is set up, accesses to 496 * data registers auto-increment the address by one dword. 497 * Bit usage for address registers (read or write): 498 * 0-31: memory address within device 499 */ 500#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 501#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 502#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 503#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 504 505/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 506#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 507#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 508 509/* 510 * Registers for accessing device's internal peripheral registers 511 * (e.g. SCD, BSM, etc.). First write to address register, 512 * then read from or write to data register to complete the job. 513 * Bit usage for address registers (read or write): 514 * 0-15: register address (offset) within device 515 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 516 */ 517#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 518#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 519#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 520#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 521 522/* enable the ID buf for read */ 523#define IWM_WFPM_PS_CTL_CLR 0xa0300c 524#define IWM_WFMP_MAC_ADDR_0 0xa03080 525#define IWM_WFMP_MAC_ADDR_1 0xa03084 526#define IWM_LMPM_PMG_EN 0xa01cec 527#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 528#define IWM_RFIC_REG_RD 0xad0470 529#define IWM_WFPM_CTRL_REG 0xa03030 530#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 531#define IWM_ENABLE_WFPM 0x80000000 532 533#define IWM_AUX_MISC_REG 0xa200b0 534#define IWM_HW_STEP_LOCATION_BITS 24 535 536#define IWM_AUX_MISC_MASTER1_EN 0xa20818 537#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 538#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 539#define IWM_RSA_ENABLE 0xa24b08 540#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 541#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 542#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 543#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 544#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 545#define IWM_SB_CPU_1_STATUS 0xa01e30 546#define IWM_SB_CPU_2_STATUS 0Xa01e34 547 548/* Used to enable DBGM */ 549#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 550 551/* 552 * Per-Tx-queue write pointer (index, really!) 553 * Indicates index to next TFD that driver will fill (1 past latest filled). 554 * Bit usage: 555 * 0-7: queue write index 556 * 11-8: queue selector 557 */ 558#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 559 560/********************************************************** 561 * CSR values 562 **********************************************************/ 563 /* 564 * host interrupt timeout value 565 * used with setting interrupt coalescing timer 566 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 567 * 568 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 569 */ 570#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 571#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 572#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 573#define IWM_HOST_INT_OPER_MODE (1 << 31) 574 575/***************************************************************************** 576 * 7000/3000 series SHR DTS addresses * 577 *****************************************************************************/ 578 579/* Diode Results Register Structure: */ 580enum iwm_dtd_diode_reg { 581 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 582 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 583 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 584 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 585 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 586 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 587/* Those are the masks INSIDE the flags bit-field: */ 588 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 589 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 590 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 591 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 592}; 593 594/* 595 * END iwl-csr.h 596 */ 597 598/* 599 * BEGIN iwl-fw.h 600 */ 601 602/** 603 * enum iwm_ucode_tlv_flag - ucode API flags 604 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 605 * was a separate TLV but moved here to save space. 606 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 607 * treats good CRC threshold as a boolean 608 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 609 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 610 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 611 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 612 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 613 * offload profile config command. 614 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 615 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 616 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 617 * (rather than two) IPv6 addresses 618 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 619 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 620 * from the probe request template. 621 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 622 * connection when going back to D0 623 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 624 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 625 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 626 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 627 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 628 * containing CAM (Continuous Active Mode) indication. 629 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 630 * single bound interface). 631 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 632 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 633 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 634 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 635 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 636 * 637 */ 638enum iwm_ucode_tlv_flag { 639 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 640 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 641 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 642 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 643 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 644 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 645 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 646 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 647 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 648 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 649 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 650 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 651 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 652 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 653 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 654 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 655 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 656 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 657 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 658 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 659 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 660 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 661 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 662 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 663 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 664 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 665 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 666 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 667}; 668 669#define IWM_UCODE_TLV_FLAG_BITS \ 670 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 671Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 672L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 673P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 674 675/** 676 * enum iwm_ucode_tlv_api - ucode api 677 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 678 * longer than the passive one, which is essential for fragmented scan. 679 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 680 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 681 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 682 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 683 * instead of 3. 684 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 685 * (command version 3) that supports per-chain limits 686 * 687 * @IWM_NUM_UCODE_TLV_API: number of bits used 688 */ 689enum iwm_ucode_tlv_api { 690 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 691 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 692 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 693 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 694 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 695 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 696 697 IWM_NUM_UCODE_TLV_API = 32 698}; 699 700#define IWM_UCODE_TLV_API_BITS \ 701 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 702 703/** 704 * enum iwm_ucode_tlv_capa - ucode capabilities 705 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 706 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 707 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 708 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 709 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 710 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 711 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 712 * tx power value into TPC Report action frame and Link Measurement Report 713 * action frame 714 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 715 * channel in DS parameter set element in probe requests. 716 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 717 * probe requests. 718 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 719 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 720 * which also implies support for the scheduler configuration command 721 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 722 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 723 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 724 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 725 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 726 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 727 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 728 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 729 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 730 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 731 * sources for the MCC. This TLV bit is a future replacement to 732 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 733 * is supported. 734 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 735 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 736 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 737 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 738 * 0=no support) 739 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 740 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 741 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 742 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 743 * antenna the beacon should be transmitted 744 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 745 * from AP and will send it upon d0i3 exit. 746 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 747 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 748 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 749 * thresholds reporting 750 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 751 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 752 * regular image. 753 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 754 * memory addresses from the firmware. 755 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 756 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 757 * 0=no support) 758 * 759 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 760 */ 761enum iwm_ucode_tlv_capa { 762 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 763 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 764 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 765 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 766 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 767 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 768 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 769 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 770 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 771 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 772 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 773 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 774 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 775 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 776 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 777 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 778 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 779 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 780 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 781 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 782 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 783 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 784 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 785 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 786 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 787 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 788 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 789 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 790 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 791 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 792 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 793 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 794 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 795 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 796 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 797 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 798 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 799 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 800 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 801 802 IWM_NUM_UCODE_TLV_CAPA = 128 803}; 804 805/* The default calibrate table size if not specified by firmware file */ 806#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 807#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 808#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 809 810/* The default max probe length if not specified by the firmware file */ 811#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 812 813/* 814 * enumeration of ucode section. 815 * This enumeration is used directly for older firmware (before 16.0). 816 * For new firmware, there can be up to 4 sections (see below) but the 817 * first one packaged into the firmware file is the DATA section and 818 * some debugging code accesses that. 819 */ 820enum iwm_ucode_sec { 821 IWM_UCODE_SECTION_DATA, 822 IWM_UCODE_SECTION_INST, 823}; 824/* 825 * For 16.0 uCode and above, there is no differentiation between sections, 826 * just an offset to the HW address. 827 */ 828#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 829#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 830 831/* uCode version contains 4 values: Major/Minor/API/Serial */ 832#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 833#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 834#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 835#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 836 837/* 838 * Calibration control struct. 839 * Sent as part of the phy configuration command. 840 * @flow_trigger: bitmap for which calibrations to perform according to 841 * flow triggers. 842 * @event_trigger: bitmap for which calibrations to perform according to 843 * event triggers. 844 */ 845struct iwm_tlv_calib_ctrl { 846 uint32_t flow_trigger; 847 uint32_t event_trigger; 848} __packed; 849 850enum iwm_fw_phy_cfg { 851 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 852 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 853 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 854 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 855 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 856 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 857 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 858 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 859 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 860 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 861}; 862 863#define IWM_UCODE_MAX_CS 1 864 865/** 866 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 867 * @cipher: a cipher suite selector 868 * @flags: cipher scheme flags (currently reserved for a future use) 869 * @hdr_len: a size of MPDU security header 870 * @pn_len: a size of PN 871 * @pn_off: an offset of pn from the beginning of the security header 872 * @key_idx_off: an offset of key index byte in the security header 873 * @key_idx_mask: a bit mask of key_idx bits 874 * @key_idx_shift: bit shift needed to get key_idx 875 * @mic_len: mic length in bytes 876 * @hw_cipher: a HW cipher index used in host commands 877 */ 878struct iwm_fw_cipher_scheme { 879 uint32_t cipher; 880 uint8_t flags; 881 uint8_t hdr_len; 882 uint8_t pn_len; 883 uint8_t pn_off; 884 uint8_t key_idx_off; 885 uint8_t key_idx_mask; 886 uint8_t key_idx_shift; 887 uint8_t mic_len; 888 uint8_t hw_cipher; 889} __packed; 890 891/** 892 * struct iwm_fw_cscheme_list - a cipher scheme list 893 * @size: a number of entries 894 * @cs: cipher scheme entries 895 */ 896struct iwm_fw_cscheme_list { 897 uint8_t size; 898 struct iwm_fw_cipher_scheme cs[]; 899} __packed; 900 901/* 902 * END iwl-fw.h 903 */ 904 905/* 906 * BEGIN iwl-fw-file.h 907 */ 908 909/* v1/v2 uCode file layout */ 910struct iwm_ucode_header { 911 uint32_t ver; /* major/minor/API/serial */ 912 union { 913 struct { 914 uint32_t inst_size; /* bytes of runtime code */ 915 uint32_t data_size; /* bytes of runtime data */ 916 uint32_t init_size; /* bytes of init code */ 917 uint32_t init_data_size; /* bytes of init data */ 918 uint32_t boot_size; /* bytes of bootstrap code */ 919 uint8_t data[0]; /* in same order as sizes */ 920 } v1; 921 struct { 922 uint32_t build; /* build number */ 923 uint32_t inst_size; /* bytes of runtime code */ 924 uint32_t data_size; /* bytes of runtime data */ 925 uint32_t init_size; /* bytes of init code */ 926 uint32_t init_data_size; /* bytes of init data */ 927 uint32_t boot_size; /* bytes of bootstrap code */ 928 uint8_t data[0]; /* in same order as sizes */ 929 } v2; 930 } u; 931}; 932 933/* 934 * new TLV uCode file layout 935 * 936 * The new TLV file format contains TLVs, that each specify 937 * some piece of data. 938 */ 939 940enum iwm_ucode_tlv_type { 941 IWM_UCODE_TLV_INVALID = 0, /* unused */ 942 IWM_UCODE_TLV_INST = 1, 943 IWM_UCODE_TLV_DATA = 2, 944 IWM_UCODE_TLV_INIT = 3, 945 IWM_UCODE_TLV_INIT_DATA = 4, 946 IWM_UCODE_TLV_BOOT = 5, 947 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 948 IWM_UCODE_TLV_PAN = 7, 949 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 950 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 951 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 952 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 953 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 954 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 955 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 956 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 957 IWM_UCODE_TLV_WOWLAN_INST = 16, 958 IWM_UCODE_TLV_WOWLAN_DATA = 17, 959 IWM_UCODE_TLV_FLAGS = 18, 960 IWM_UCODE_TLV_SEC_RT = 19, 961 IWM_UCODE_TLV_SEC_INIT = 20, 962 IWM_UCODE_TLV_SEC_WOWLAN = 21, 963 IWM_UCODE_TLV_DEF_CALIB = 22, 964 IWM_UCODE_TLV_PHY_SKU = 23, 965 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 966 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 967 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 968 IWM_UCODE_TLV_NUM_OF_CPU = 27, 969 IWM_UCODE_TLV_CSCHEME = 28, 970 971 /* 972 * Following two are not in our base tag, but allow 973 * handling ucode version 9. 974 */ 975 IWM_UCODE_TLV_API_CHANGES_SET = 29, 976 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 977 978 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 979 IWM_UCODE_TLV_PAGING = 32, 980 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 981 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 982 IWM_UCODE_TLV_FW_VERSION = 36, 983 IWM_UCODE_TLV_FW_DBG_DEST = 38, 984 IWM_UCODE_TLV_FW_DBG_CONF = 39, 985 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 986 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 987}; 988 989struct iwm_ucode_tlv { 990 uint32_t type; /* see above */ 991 uint32_t length; /* not including type/length fields */ 992 uint8_t data[0]; 993}; 994 995struct iwm_ucode_api { 996 uint32_t api_index; 997 uint32_t api_flags; 998} __packed; 999 1000struct iwm_ucode_capa { 1001 uint32_t api_index; 1002 uint32_t api_capa; 1003} __packed; 1004 1005#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 1006 1007struct iwm_tlv_ucode_header { 1008 /* 1009 * The TLV style ucode header is distinguished from 1010 * the v1/v2 style header by first four bytes being 1011 * zero, as such is an invalid combination of 1012 * major/minor/API/serial versions. 1013 */ 1014 uint32_t zero; 1015 uint32_t magic; 1016 uint8_t human_readable[64]; 1017 uint32_t ver; /* major/minor/API/serial */ 1018 uint32_t build; 1019 uint64_t ignore; 1020 /* 1021 * The data contained herein has a TLV layout, 1022 * see above for the TLV header and types. 1023 * Note that each TLV is padded to a length 1024 * that is a multiple of 4 for alignment. 1025 */ 1026 uint8_t data[0]; 1027}; 1028 1029/* 1030 * END iwl-fw-file.h 1031 */ 1032 1033/* 1034 * BEGIN iwl-prph.h 1035 */ 1036 1037/* 1038 * Registers in this file are internal, not PCI bus memory mapped. 1039 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1040 */ 1041#define IWM_PRPH_BASE (0x00000) 1042#define IWM_PRPH_END (0xFFFFF) 1043 1044/* APMG (power management) constants */ 1045#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1046#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1047#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1048#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1049#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1050#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1051#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1052#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1053#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1054#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1055#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1056 1057#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1058#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1059#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1060 1061#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1062#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1063#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1064#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1065#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1066#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1067#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1068 1069#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1070 1071#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1072 1073/* Device system time */ 1074#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1075 1076/* Device NMI register */ 1077#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1078#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1079#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1080#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1081#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1082 1083/* 1084 * Device reset for family 8000 1085 * write to bit 24 in order to reset the CPU 1086 */ 1087#define IWM_RELEASE_CPU_RESET 0x300c 1088#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1089 1090 1091/***************************************************************************** 1092 * 7000/3000 series SHR DTS addresses * 1093 *****************************************************************************/ 1094 1095#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1096#define IWM_DTSC_CFG_MODE (0x00a10604) 1097#define IWM_DTSC_VREF_AVG (0x00a10648) 1098#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1099#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1100#define IWM_DTSC_PTAT_AVG (0x00a10650) 1101 1102 1103/** 1104 * Tx Scheduler 1105 * 1106 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1107 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1108 * host DRAM. It steers each frame's Tx command (which contains the frame 1109 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1110 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1111 * but one DMA channel may take input from several queues. 1112 * 1113 * Tx DMA FIFOs have dedicated purposes. 1114 * 1115 * For 5000 series and up, they are used differently 1116 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1117 * 1118 * 0 -- EDCA BK (background) frames, lowest priority 1119 * 1 -- EDCA BE (best effort) frames, normal priority 1120 * 2 -- EDCA VI (video) frames, higher priority 1121 * 3 -- EDCA VO (voice) and management frames, highest priority 1122 * 4 -- unused 1123 * 5 -- unused 1124 * 6 -- unused 1125 * 7 -- Commands 1126 * 1127 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1128 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1129 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1130 * 1131 * The driver sets up each queue to work in one of two modes: 1132 * 1133 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1134 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1135 * contains TFDs for a unique combination of Recipient Address (RA) 1136 * and Traffic Identifier (TID), that is, traffic of a given 1137 * Quality-Of-Service (QOS) priority, destined for a single station. 1138 * 1139 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1140 * each frame within the BA window, including whether it's been transmitted, 1141 * and whether it's been acknowledged by the receiving station. The device 1142 * automatically processes block-acks received from the receiving STA, 1143 * and reschedules un-acked frames to be retransmitted (successful 1144 * Tx completion may end up being out-of-order). 1145 * 1146 * The driver must maintain the queue's Byte Count table in host DRAM 1147 * for this mode. 1148 * This mode does not support fragmentation. 1149 * 1150 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1151 * The device may automatically retry Tx, but will retry only one frame 1152 * at a time, until receiving ACK from receiving station, or reaching 1153 * retry limit and giving up. 1154 * 1155 * The command queue (#4/#9) must use this mode! 1156 * This mode does not require use of the Byte Count table in host DRAM. 1157 * 1158 * Driver controls scheduler operation via 3 means: 1159 * 1) Scheduler registers 1160 * 2) Shared scheduler data base in internal SRAM 1161 * 3) Shared data in host DRAM 1162 * 1163 * Initialization: 1164 * 1165 * When loading, driver should allocate memory for: 1166 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1167 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1168 * (1024 bytes for each queue). 1169 * 1170 * After receiving "Alive" response from uCode, driver must initialize 1171 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1172 * the driver can't issue commands!): 1173 */ 1174#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1175 1176/** 1177 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1178 * can keep track of at one time when creating block-ack chains of frames. 1179 * Note that "64" matches the number of ack bits in a block-ack packet. 1180 */ 1181#define IWM_SCD_WIN_SIZE 64 1182#define IWM_SCD_FRAME_LIMIT 64 1183 1184#define IWM_SCD_TXFIFO_POS_TID (0) 1185#define IWM_SCD_TXFIFO_POS_RA (4) 1186#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1187 1188/* agn SCD */ 1189#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1190#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1191#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1192#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1193#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1194 1195#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1196#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1197#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1198#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1199#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1200#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1201#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1202#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1203#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1204#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1205 1206/* Context Data */ 1207#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1208#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1209 1210/* Tx status */ 1211#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1212#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1213 1214/* Translation Data */ 1215#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1216#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1217 1218#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1219 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1220 1221#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1222 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1223 1224#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1225 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1226 1227#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1228 1229#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1230#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1231#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1232#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1233#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1234#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1235#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1236#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1237#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1238#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1239#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1240 1241static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1242{ 1243 if (chnl < 20) 1244 return IWM_SCD_BASE + 0x18 + chnl * 4; 1245 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1246} 1247 1248static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1249{ 1250 if (chnl < 20) 1251 return IWM_SCD_BASE + 0x68 + chnl * 4; 1252 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1253} 1254 1255static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1256{ 1257 if (chnl < 20) 1258 return IWM_SCD_BASE + 0x10c + chnl * 4; 1259 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1260} 1261 1262/*********************** END TX SCHEDULER *************************************/ 1263 1264/* Oscillator clock */ 1265#define IWM_OSC_CLK (0xa04068) 1266#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1267 1268/* 1269 * END iwl-prph.h 1270 */ 1271 1272/* 1273 * BEGIN iwl-fh.h 1274 */ 1275 1276/****************************/ 1277/* Flow Handler Definitions */ 1278/****************************/ 1279 1280/** 1281 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1282 * Addresses are offsets from device's PCI hardware base address. 1283 */ 1284#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1285#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1286 1287/** 1288 * Keep-Warm (KW) buffer base address. 1289 * 1290 * Driver must allocate a 4KByte buffer that is for keeping the 1291 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1292 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1293 * from going into a power-savings mode that would cause higher DRAM latency, 1294 * and possible data over/under-runs, before all Tx/Rx is complete. 1295 * 1296 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1297 * of the buffer, which must be 4K aligned. Once this is set up, the device 1298 * automatically invokes keep-warm accesses when normal accesses might not 1299 * be sufficient to maintain fast DRAM response. 1300 * 1301 * Bit fields: 1302 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1303 */ 1304#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1305 1306 1307/** 1308 * TFD Circular Buffers Base (CBBC) addresses 1309 * 1310 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1311 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1312 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1313 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1314 * aligned (address bits 0-7 must be 0). 1315 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1316 * for them are in different places. 1317 * 1318 * Bit fields in each pointer register: 1319 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1320 */ 1321#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1322#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1323#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1324#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1325#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1326#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1327 1328/* Find TFD CB base pointer for given queue */ 1329static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1330{ 1331 if (chnl < 16) 1332 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1333 if (chnl < 20) 1334 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1335 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1336} 1337 1338 1339/** 1340 * Rx SRAM Control and Status Registers (RSCSR) 1341 * 1342 * These registers provide handshake between driver and device for the Rx queue 1343 * (this queue handles *all* command responses, notifications, Rx data, etc. 1344 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1345 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1346 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1347 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1348 * mapping between RBDs and RBs. 1349 * 1350 * Driver must allocate host DRAM memory for the following, and set the 1351 * physical address of each into device registers: 1352 * 1353 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1354 * entries (although any power of 2, up to 4096, is selectable by driver). 1355 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1356 * (typically 4K, although 8K or 16K are also selectable by driver). 1357 * Driver sets up RB size and number of RBDs in the CB via Rx config 1358 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1359 * 1360 * Bit fields within one RBD: 1361 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1362 * 1363 * Driver sets physical address [35:8] of base of RBD circular buffer 1364 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1365 * 1366 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1367 * (RBs) have been filled, via a "write pointer", actually the index of 1368 * the RB's corresponding RBD within the circular buffer. Driver sets 1369 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1370 * 1371 * Bit fields in lower dword of Rx status buffer (upper dword not used 1372 * by driver: 1373 * 31-12: Not used by driver 1374 * 11- 0: Index of last filled Rx buffer descriptor 1375 * (device writes, driver reads this value) 1376 * 1377 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1378 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1379 * and update the device's "write" index register, 1380 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1381 * 1382 * This "write" index corresponds to the *next* RBD that the driver will make 1383 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1384 * the circular buffer. This value should initially be 0 (before preparing any 1385 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1386 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1387 * "read" index has advanced past 1! See below). 1388 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1389 * 1390 * As the device fills RBs (referenced from contiguous RBDs within the circular 1391 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1392 * to tell the driver the index of the latest filled RBD. The driver must 1393 * read this "read" index from DRAM after receiving an Rx interrupt from device 1394 * 1395 * The driver must also internally keep track of a third index, which is the 1396 * next RBD to process. When receiving an Rx interrupt, driver should process 1397 * all filled but unprocessed RBs up to, but not including, the RB 1398 * corresponding to the "read" index. For example, if "read" index becomes "1", 1399 * driver may process the RB pointed to by RBD 0. Depending on volume of 1400 * traffic, there may be many RBs to process. 1401 * 1402 * If read index == write index, device thinks there is no room to put new data. 1403 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1404 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1405 * and "read" indexes; that is, make sure that there are no more than 254 1406 * buffers waiting to be filled. 1407 */ 1408#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1409#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1410#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1411 1412/** 1413 * Physical base address of 8-byte Rx Status buffer. 1414 * Bit fields: 1415 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1416 */ 1417#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1418 1419/** 1420 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1421 * Bit fields: 1422 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1423 */ 1424#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1425 1426/** 1427 * Rx write pointer (index, really!). 1428 * Bit fields: 1429 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1430 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1431 */ 1432#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1433#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1434 1435#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1436#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1437 1438/** 1439 * Rx Config/Status Registers (RCSR) 1440 * Rx Config Reg for channel 0 (only channel used) 1441 * 1442 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1443 * normal operation (see bit fields). 1444 * 1445 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1446 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1447 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1448 * 1449 * Bit fields: 1450 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1451 * '10' operate normally 1452 * 29-24: reserved 1453 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1454 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1455 * 19-18: reserved 1456 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1457 * '10' 12K, '11' 16K. 1458 * 15-14: reserved 1459 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1460 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1461 * typical value 0x10 (about 1/2 msec) 1462 * 3- 0: reserved 1463 */ 1464#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1465#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1466#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1467 1468#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1469#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1470#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1471 1472#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1473#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1474#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1475#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1476#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1477#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1478 1479#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1480#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1481#define IWM_RX_RB_TIMEOUT (0x11) 1482 1483#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1484#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1485#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1486 1487#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1488#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1489#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1490#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1491 1492#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1493#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1494#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1495 1496/** 1497 * Rx Shared Status Registers (RSSR) 1498 * 1499 * After stopping Rx DMA channel (writing 0 to 1500 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1501 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1502 * 1503 * Bit fields: 1504 * 24: 1 = Channel 0 is idle 1505 * 1506 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1507 * contain default values that should not be altered by the driver. 1508 */ 1509#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1510#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1511 1512#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1513#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1514#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1515 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1516 1517#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1518 1519#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1520 1521/* TFDB Area - TFDs buffer table */ 1522#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1523#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1524#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1525#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1526#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1527 1528/** 1529 * Transmit DMA Channel Control/Status Registers (TCSR) 1530 * 1531 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1532 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1533 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1534 * 1535 * To use a Tx DMA channel, driver must initialize its 1536 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1537 * 1538 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1539 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1540 * 1541 * All other bits should be 0. 1542 * 1543 * Bit fields: 1544 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1545 * '10' operate normally 1546 * 29- 4: Reserved, set to "0" 1547 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1548 * 2- 0: Reserved, set to "0" 1549 */ 1550#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1551#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1552 1553/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1554#define IWM_FH_TCSR_CHNL_NUM (8) 1555 1556/* TCSR: tx_config register values */ 1557#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1558 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1559#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1560 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1561#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1562 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1563 1564#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1565#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1566 1567#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1568#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1569 1570#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1571#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1572#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1573 1574#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1575#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1576#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1577 1578#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1579#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1580#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1581 1582#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1583#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1584#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1585 1586#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1587#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1588 1589/** 1590 * Tx Shared Status Registers (TSSR) 1591 * 1592 * After stopping Tx DMA channel (writing 0 to 1593 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1594 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1595 * (channel's buffers empty | no pending requests). 1596 * 1597 * Bit fields: 1598 * 31-24: 1 = Channel buffers empty (channel 7:0) 1599 * 23-16: 1 = No pending requests (channel 7:0) 1600 */ 1601#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1602#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1603 1604#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1605 1606/** 1607 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1608 * 31: Indicates an address error when accessed to internal memory 1609 * uCode/driver must write "1" in order to clear this flag 1610 * 30: Indicates that Host did not send the expected number of dwords to FH 1611 * uCode/driver must write "1" in order to clear this flag 1612 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1613 * command was received from the scheduler while the TRB was already full 1614 * with previous command 1615 * uCode/driver must write "1" in order to clear this flag 1616 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1617 * bit is set, it indicates that the FH has received a full indication 1618 * from the RTC TxFIFO and the current value of the TxCredit counter was 1619 * not equal to zero. This mean that the credit mechanism was not 1620 * synchronized to the TxFIFO status 1621 * uCode/driver must write "1" in order to clear this flag 1622 */ 1623#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1624#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1625 1626#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1627 1628/* Tx service channels */ 1629#define IWM_FH_SRVC_CHNL (9) 1630#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1631#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1632#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1633 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1634 1635#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1636#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1637 (_chan) * 4) 1638 1639/* Instruct FH to increment the retry count of a packet when 1640 * it is brought from the memory to TX-FIFO 1641 */ 1642#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1643 1644#define IWM_RX_QUEUE_SIZE 256 1645#define IWM_RX_QUEUE_MASK 255 1646#define IWM_RX_QUEUE_SIZE_LOG 8 1647 1648/* 1649 * RX related structures and functions 1650 */ 1651#define IWM_RX_FREE_BUFFERS 64 1652#define IWM_RX_LOW_WATERMARK 8 1653 1654/** 1655 * struct iwm_rb_status - reseve buffer status 1656 * host memory mapped FH registers 1657 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1658 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1659 * @finished_rb_num [0:11] - Indicates the index of the current RB 1660 * in which the last frame was written to 1661 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1662 * which was transferred 1663 */ 1664struct iwm_rb_status { 1665 uint16_t closed_rb_num; 1666 uint16_t closed_fr_num; 1667 uint16_t finished_rb_num; 1668 uint16_t finished_fr_nam; 1669 uint32_t unused; 1670} __packed; 1671 1672 1673#define IWM_TFD_QUEUE_SIZE_MAX (256) 1674#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1675#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1676 IWM_TFD_QUEUE_SIZE_BC_DUP) 1677#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1678#define IWM_NUM_OF_TBS 20 1679 1680static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1681{ 1682 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1683} 1684/** 1685 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1686 * 1687 * This structure contains dma address and length of transmission address 1688 * 1689 * @lo: low [31:0] portion of the dma address of TX buffer 1690 * every even is unaligned on 16 bit boundary 1691 * @hi_n_len 0-3 [35:32] portion of dma 1692 * 4-15 length of the tx buffer 1693 */ 1694struct iwm_tfd_tb { 1695 uint32_t lo; 1696 uint16_t hi_n_len; 1697} __packed; 1698 1699/** 1700 * struct iwm_tfd 1701 * 1702 * Transmit Frame Descriptor (TFD) 1703 * 1704 * @ __reserved1[3] reserved 1705 * @ num_tbs 0-4 number of active tbs 1706 * 5 reserved 1707 * 6-7 padding (not used) 1708 * @ tbs[20] transmit frame buffer descriptors 1709 * @ __pad padding 1710 * 1711 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1712 * Both driver and device share these circular buffers, each of which must be 1713 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1714 * 1715 * Driver must indicate the physical address of the base of each 1716 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1717 * 1718 * Each TFD contains pointer/size information for up to 20 data buffers 1719 * in host DRAM. These buffers collectively contain the (one) frame described 1720 * by the TFD. Each buffer must be a single contiguous block of memory within 1721 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1722 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1723 * Tx frame, up to 8 KBytes in size. 1724 * 1725 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1726 */ 1727struct iwm_tfd { 1728 uint8_t __reserved1[3]; 1729 uint8_t num_tbs; 1730 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1731 uint32_t __pad; 1732} __packed; 1733 1734/* Keep Warm Size */ 1735#define IWM_KW_SIZE 0x1000 /* 4k */ 1736 1737/* Fixed (non-configurable) rx data from phy */ 1738 1739/** 1740 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1741 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1742 * @tfd_offset 0-12 - tx command byte count 1743 * 12-16 - station index 1744 */ 1745struct iwm_agn_scd_bc_tbl { 1746 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1747} __packed; 1748 1749/* 1750 * END iwl-fh.h 1751 */ 1752 1753/* 1754 * BEGIN mvm/fw-api.h 1755 */ 1756 1757/* Maximum number of Tx queues. */ 1758#define IWM_MVM_MAX_QUEUES 31 1759 1760/* Tx queue numbers */ 1761enum { 1762 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1763 IWM_MVM_CMD_QUEUE = 9, 1764 IWM_MVM_AUX_QUEUE = 15, 1765}; 1766 1767enum iwm_mvm_tx_fifo { 1768 IWM_MVM_TX_FIFO_BK = 0, 1769 IWM_MVM_TX_FIFO_BE, 1770 IWM_MVM_TX_FIFO_VI, 1771 IWM_MVM_TX_FIFO_VO, 1772 IWM_MVM_TX_FIFO_MCAST = 5, 1773 IWM_MVM_TX_FIFO_CMD = 7, 1774}; 1775 1776#define IWM_MVM_STATION_COUNT 16 1777 1778/* commands */ 1779enum { 1780 IWM_MVM_ALIVE = 0x1, 1781 IWM_REPLY_ERROR = 0x2, 1782 1783 IWM_INIT_COMPLETE_NOTIF = 0x4, 1784 1785 /* PHY context commands */ 1786 IWM_PHY_CONTEXT_CMD = 0x8, 1787 IWM_DBG_CFG = 0x9, 1788 1789 /* UMAC scan commands */ 1790 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1791 IWM_SCAN_CFG_CMD = 0xc, 1792 IWM_SCAN_REQ_UMAC = 0xd, 1793 IWM_SCAN_ABORT_UMAC = 0xe, 1794 IWM_SCAN_COMPLETE_UMAC = 0xf, 1795 1796 /* station table */ 1797 IWM_ADD_STA_KEY = 0x17, 1798 IWM_ADD_STA = 0x18, 1799 IWM_REMOVE_STA = 0x19, 1800 1801 /* TX */ 1802 IWM_TX_CMD = 0x1c, 1803 IWM_TXPATH_FLUSH = 0x1e, 1804 IWM_MGMT_MCAST_KEY = 0x1f, 1805 1806 /* scheduler config */ 1807 IWM_SCD_QUEUE_CFG = 0x1d, 1808 1809 /* global key */ 1810 IWM_WEP_KEY = 0x20, 1811 1812 /* MAC and Binding commands */ 1813 IWM_MAC_CONTEXT_CMD = 0x28, 1814 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1815 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1816 IWM_BINDING_CONTEXT_CMD = 0x2b, 1817 IWM_TIME_QUOTA_CMD = 0x2c, 1818 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1819 1820 IWM_LQ_CMD = 0x4e, 1821 1822 /* Calibration */ 1823 IWM_TEMPERATURE_NOTIFICATION = 0x62, 1824 IWM_CALIBRATION_CFG_CMD = 0x65, 1825 IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1826 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1827 IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1828 1829 /* Scan offload */ 1830 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1831 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1832 IWM_HOT_SPOT_CMD = 0x53, 1833 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1834 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1835 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1836 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1837 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1838 1839 /* Phy */ 1840 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1841 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1842 /* IWM_PHY_DB_CMD = 0x6c, */ 1843 1844 /* Power - legacy power table command */ 1845 IWM_POWER_TABLE_CMD = 0x77, 1846 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1847 1848 /* Thermal Throttling*/ 1849 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1850 1851 /* Scanning */ 1852 IWM_SCAN_ABORT_CMD = 0x81, 1853 IWM_SCAN_START_NOTIFICATION = 0x82, 1854 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1855 1856 /* NVM */ 1857 IWM_NVM_ACCESS_CMD = 0x88, 1858 1859 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1860 1861 IWM_BEACON_NOTIFICATION = 0x90, 1862 IWM_BEACON_TEMPLATE_CMD = 0x91, 1863 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1864 IWM_BT_CONFIG = 0x9b, 1865 IWM_STATISTICS_NOTIFICATION = 0x9d, 1866 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1867 1868 /* RF-KILL commands and notifications */ 1869 IWM_CARD_STATE_CMD = 0xa0, 1870 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1871 1872 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1873 1874 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1875 1876 /* Power - new power table command */ 1877 IWM_MAC_PM_POWER_TABLE = 0xa9, 1878 1879 IWM_REPLY_RX_PHY_CMD = 0xc0, 1880 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1881 IWM_BA_NOTIF = 0xc5, 1882 1883 /* Location Aware Regulatory */ 1884 IWM_MCC_UPDATE_CMD = 0xc8, 1885 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1886 1887 /* BT Coex */ 1888 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1889 IWM_BT_COEX_PROT_ENV = 0xcd, 1890 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1891 IWM_BT_COEX_CI = 0x5d, 1892 1893 IWM_REPLY_SF_CFG_CMD = 0xd1, 1894 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1895 1896 /* DTS measurements */ 1897 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1898 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1899 1900 IWM_REPLY_DEBUG_CMD = 0xf0, 1901 IWM_DEBUG_LOG_MSG = 0xf7, 1902 1903 IWM_MCAST_FILTER_CMD = 0xd0, 1904 1905 /* D3 commands/notifications */ 1906 IWM_D3_CONFIG_CMD = 0xd3, 1907 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1908 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1909 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1910 1911 /* for WoWLAN in particular */ 1912 IWM_WOWLAN_PATTERNS = 0xe0, 1913 IWM_WOWLAN_CONFIGURATION = 0xe1, 1914 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1915 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1916 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1917 IWM_WOWLAN_GET_STATUSES = 0xe5, 1918 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1919 1920 /* and for NetDetect */ 1921 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1922 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1923 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1924 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1925 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1926 1927 IWM_REPLY_MAX = 0xff, 1928}; 1929 1930/** 1931 * struct iwm_cmd_response - generic response struct for most commands 1932 * @status: status of the command asked, changes for each one 1933 */ 1934struct iwm_cmd_response { 1935 uint32_t status; 1936}; 1937 1938/* 1939 * struct iwm_tx_ant_cfg_cmd 1940 * @valid: valid antenna configuration 1941 */ 1942struct iwm_tx_ant_cfg_cmd { 1943 uint32_t valid; 1944} __packed; 1945 1946/** 1947 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1948 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1949 * @flags: (reserved for future implementation) 1950 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1951 * @pwr_restriction: TX power restriction in dBms. 1952 */ 1953struct iwm_reduce_tx_power_cmd { 1954 uint8_t flags; 1955 uint8_t mac_context_id; 1956 uint16_t pwr_restriction; 1957} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1958 1959/* 1960 * Calibration control struct. 1961 * Sent as part of the phy configuration command. 1962 * @flow_trigger: bitmap for which calibrations to perform according to 1963 * flow triggers. 1964 * @event_trigger: bitmap for which calibrations to perform according to 1965 * event triggers. 1966 */ 1967struct iwm_calib_ctrl { 1968 uint32_t flow_trigger; 1969 uint32_t event_trigger; 1970} __packed; 1971 1972/* This enum defines the bitmap of various calibrations to enable in both 1973 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1974 */ 1975enum iwm_calib_cfg { 1976 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1977 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1978 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1979 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1980 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1981 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1982 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1983 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1984 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1985 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1986 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1987 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1988 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1989 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1990 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1991 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1992 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1993 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1994 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1995}; 1996 1997/* 1998 * Phy configuration command. 1999 */ 2000struct iwm_phy_cfg_cmd { 2001 uint32_t phy_cfg; 2002 struct iwm_calib_ctrl calib_control; 2003} __packed; 2004 2005#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2006#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2007#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2008#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2009#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2010#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2011#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2012#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2013#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2014#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2015 2016/* 2017 * PHY db 2018 */ 2019 2020enum iwm_phy_db_section_type { 2021 IWM_PHY_DB_CFG = 1, 2022 IWM_PHY_DB_CALIB_NCH, 2023 IWM_PHY_DB_UNUSED, 2024 IWM_PHY_DB_CALIB_CHG_PAPD, 2025 IWM_PHY_DB_CALIB_CHG_TXP, 2026 IWM_PHY_DB_MAX 2027}; 2028 2029#define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */ 2030 2031/* 2032 * phy db - configure operational ucode 2033 */ 2034struct iwm_phy_db_cmd { 2035 uint16_t type; 2036 uint16_t length; 2037 uint8_t data[]; 2038} __packed; 2039 2040/* for parsing of tx power channel group data that comes from the firmware */ 2041struct iwm_phy_db_chg_txp { 2042 uint32_t space; 2043 uint16_t max_channel_idx; 2044} __packed; 2045 2046/* 2047 * phy db - Receive phy db chunk after calibrations 2048 */ 2049struct iwm_calib_res_notif_phy_db { 2050 uint16_t type; 2051 uint16_t length; 2052 uint8_t data[]; 2053} __packed; 2054 2055 2056/* Target of the IWM_NVM_ACCESS_CMD */ 2057enum { 2058 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2059 IWM_NVM_ACCESS_TARGET_OTP = 1, 2060 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2061}; 2062 2063/* Section types for IWM_NVM_ACCESS_CMD */ 2064enum { 2065 IWM_NVM_SECTION_TYPE_HW = 0, 2066 IWM_NVM_SECTION_TYPE_SW, 2067 IWM_NVM_SECTION_TYPE_PAPD, 2068 IWM_NVM_SECTION_TYPE_REGULATORY, 2069 IWM_NVM_SECTION_TYPE_CALIBRATION, 2070 IWM_NVM_SECTION_TYPE_PRODUCTION, 2071 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 2072 /* 7, 8, 9 unknown */ 2073 IWM_NVM_SECTION_TYPE_HW_8000 = 10, 2074 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2075 IWM_NVM_SECTION_TYPE_PHY_SKU, 2076 IWM_NVM_NUM_OF_SECTIONS, 2077}; 2078 2079/** 2080 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2081 * @op_code: 0 - read, 1 - write 2082 * @target: IWM_NVM_ACCESS_TARGET_* 2083 * @type: IWM_NVM_SECTION_TYPE_* 2084 * @offset: offset in bytes into the section 2085 * @length: in bytes, to read/write 2086 * @data: if write operation, the data to write. On read its empty 2087 */ 2088struct iwm_nvm_access_cmd { 2089 uint8_t op_code; 2090 uint8_t target; 2091 uint16_t type; 2092 uint16_t offset; 2093 uint16_t length; 2094 uint8_t data[]; 2095} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2096 2097/** 2098 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2099 * @offset: offset in bytes into the section 2100 * @length: in bytes, either how much was written or read 2101 * @type: IWM_NVM_SECTION_TYPE_* 2102 * @status: 0 for success, fail otherwise 2103 * @data: if read operation, the data returned. Empty on write. 2104 */ 2105struct iwm_nvm_access_resp { 2106 uint16_t offset; 2107 uint16_t length; 2108 uint16_t type; 2109 uint16_t status; 2110 uint8_t data[]; 2111} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2112 2113/* IWM_MVM_ALIVE 0x1 */ 2114 2115/* alive response is_valid values */ 2116#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2117#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2118 2119/* alive response ver_type values */ 2120enum { 2121 IWM_FW_TYPE_HW = 0, 2122 IWM_FW_TYPE_PROT = 1, 2123 IWM_FW_TYPE_AP = 2, 2124 IWM_FW_TYPE_WOWLAN = 3, 2125 IWM_FW_TYPE_TIMING = 4, 2126 IWM_FW_TYPE_WIPAN = 5 2127}; 2128 2129/* alive response ver_subtype values */ 2130enum { 2131 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2132 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2133 IWM_FW_SUBTYPE_REDUCED = 2, 2134 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2135 IWM_FW_SUBTYPE_WOWLAN = 4, 2136 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2137 IWM_FW_SUBTYPE_WIPAN = 6, 2138 IWM_FW_SUBTYPE_INITIALIZE = 9 2139}; 2140 2141#define IWM_ALIVE_STATUS_ERR 0xDEAD 2142#define IWM_ALIVE_STATUS_OK 0xCAFE 2143 2144#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2145 2146struct iwm_mvm_alive_resp_v1 { 2147 uint16_t status; 2148 uint16_t flags; 2149 uint8_t ucode_minor; 2150 uint8_t ucode_major; 2151 uint16_t id; 2152 uint8_t api_minor; 2153 uint8_t api_major; 2154 uint8_t ver_subtype; 2155 uint8_t ver_type; 2156 uint8_t mac; 2157 uint8_t opt; 2158 uint16_t reserved2; 2159 uint32_t timestamp; 2160 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2161 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2162 uint32_t cpu_register_ptr; 2163 uint32_t dbgm_config_ptr; 2164 uint32_t alive_counter_ptr; 2165 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2166} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2167 2168struct iwm_mvm_alive_resp_v2 { 2169 uint16_t status; 2170 uint16_t flags; 2171 uint8_t ucode_minor; 2172 uint8_t ucode_major; 2173 uint16_t id; 2174 uint8_t api_minor; 2175 uint8_t api_major; 2176 uint8_t ver_subtype; 2177 uint8_t ver_type; 2178 uint8_t mac; 2179 uint8_t opt; 2180 uint16_t reserved2; 2181 uint32_t timestamp; 2182 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2183 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2184 uint32_t cpu_register_ptr; 2185 uint32_t dbgm_config_ptr; 2186 uint32_t alive_counter_ptr; 2187 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2188 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2189 uint32_t st_fwrd_size; 2190 uint8_t umac_minor; /* UMAC version: minor */ 2191 uint8_t umac_major; /* UMAC version: major */ 2192 uint16_t umac_id; /* UMAC version: id */ 2193 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2194 uint32_t dbg_print_buff_addr; 2195} __packed; /* ALIVE_RES_API_S_VER_2 */ 2196 2197struct iwm_mvm_alive_resp_v3 { 2198 uint16_t status; 2199 uint16_t flags; 2200 uint32_t ucode_minor; 2201 uint32_t ucode_major; 2202 uint8_t ver_subtype; 2203 uint8_t ver_type; 2204 uint8_t mac; 2205 uint8_t opt; 2206 uint32_t timestamp; 2207 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2208 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2209 uint32_t cpu_register_ptr; 2210 uint32_t dbgm_config_ptr; 2211 uint32_t alive_counter_ptr; 2212 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2213 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2214 uint32_t st_fwrd_size; 2215 uint32_t umac_minor; /* UMAC version: minor */ 2216 uint32_t umac_major; /* UMAC version: major */ 2217 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2218 uint32_t dbg_print_buff_addr; 2219} __packed; /* ALIVE_RES_API_S_VER_3 */ 2220 2221/* Error response/notification */ 2222enum { 2223 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2224 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2225 IWM_FW_ERR_SERVICE = 0x2, 2226 IWM_FW_ERR_ARC_MEMORY = 0x3, 2227 IWM_FW_ERR_ARC_CODE = 0x4, 2228 IWM_FW_ERR_WATCH_DOG = 0x5, 2229 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2230 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2231 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2232 IWM_FW_ERR_UNEXPECTED = 0xFE, 2233 IWM_FW_ERR_FATAL = 0xFF 2234}; 2235 2236/** 2237 * struct iwm_error_resp - FW error indication 2238 * ( IWM_REPLY_ERROR = 0x2 ) 2239 * @error_type: one of IWM_FW_ERR_* 2240 * @cmd_id: the command ID for which the error occurred 2241 * @bad_cmd_seq_num: sequence number of the erroneous command 2242 * @error_service: which service created the error, applicable only if 2243 * error_type = 2, otherwise 0 2244 * @timestamp: TSF in usecs. 2245 */ 2246struct iwm_error_resp { 2247 uint32_t error_type; 2248 uint8_t cmd_id; 2249 uint8_t reserved1; 2250 uint16_t bad_cmd_seq_num; 2251 uint32_t error_service; 2252 uint64_t timestamp; 2253} __packed; 2254 2255 2256/* Common PHY, MAC and Bindings definitions */ 2257 2258#define IWM_MAX_MACS_IN_BINDING (3) 2259#define IWM_MAX_BINDINGS (4) 2260#define IWM_AUX_BINDING_INDEX (3) 2261#define IWM_MAX_PHYS (4) 2262 2263/* Used to extract ID and color from the context dword */ 2264#define IWM_FW_CTXT_ID_POS (0) 2265#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2266#define IWM_FW_CTXT_COLOR_POS (8) 2267#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2268#define IWM_FW_CTXT_INVALID (0xffffffff) 2269 2270#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2271 (_color << IWM_FW_CTXT_COLOR_POS)) 2272 2273/* Possible actions on PHYs, MACs and Bindings */ 2274enum { 2275 IWM_FW_CTXT_ACTION_STUB = 0, 2276 IWM_FW_CTXT_ACTION_ADD, 2277 IWM_FW_CTXT_ACTION_MODIFY, 2278 IWM_FW_CTXT_ACTION_REMOVE, 2279 IWM_FW_CTXT_ACTION_NUM 2280}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2281 2282/* Time Events */ 2283 2284/* Time Event types, according to MAC type */ 2285enum iwm_time_event_type { 2286 /* BSS Station Events */ 2287 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2288 IWM_TE_BSS_STA_ASSOC, 2289 IWM_TE_BSS_EAP_DHCP_PROT, 2290 IWM_TE_BSS_QUIET_PERIOD, 2291 2292 /* P2P Device Events */ 2293 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2294 IWM_TE_P2P_DEVICE_LISTEN, 2295 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2296 IWM_TE_P2P_DEVICE_FULL_SCAN, 2297 2298 /* P2P Client Events */ 2299 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2300 IWM_TE_P2P_CLIENT_ASSOC, 2301 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2302 2303 /* P2P GO Events */ 2304 IWM_TE_P2P_GO_ASSOC_PROT, 2305 IWM_TE_P2P_GO_REPETITIVE_NOA, 2306 IWM_TE_P2P_GO_CT_WINDOW, 2307 2308 /* WiDi Sync Events */ 2309 IWM_TE_WIDI_TX_SYNC, 2310 2311 IWM_TE_MAX 2312}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2313 2314 2315 2316/* Time event - defines for command API v1 */ 2317 2318/* 2319 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2320 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2321 * the first fragment is scheduled. 2322 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2323 * the first 2 fragments are scheduled. 2324 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2325 * number of fragments are valid. 2326 * 2327 * Other than the constant defined above, specifying a fragmentation value 'x' 2328 * means that the event can be fragmented but only the first 'x' will be 2329 * scheduled. 2330 */ 2331enum { 2332 IWM_TE_V1_FRAG_NONE = 0, 2333 IWM_TE_V1_FRAG_SINGLE = 1, 2334 IWM_TE_V1_FRAG_DUAL = 2, 2335 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2336}; 2337 2338/* If a Time Event can be fragmented, this is the max number of fragments */ 2339#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2340/* Repeat the time event endlessly (until removed) */ 2341#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2342/* If a Time Event has bounded repetitions, this is the maximal value */ 2343#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2344 2345/* Time Event dependencies: none, on another TE, or in a specific time */ 2346enum { 2347 IWM_TE_V1_INDEPENDENT = 0, 2348 IWM_TE_V1_DEP_OTHER = (1 << 0), 2349 IWM_TE_V1_DEP_TSF = (1 << 1), 2350 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2351}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2352 2353/* 2354 * @IWM_TE_V1_NOTIF_NONE: no notifications 2355 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2356 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2357 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2358 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2359 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2360 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2361 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2362 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2363 * 2364 * Supported Time event notifications configuration. 2365 * A notification (both event and fragment) includes a status indicating weather 2366 * the FW was able to schedule the event or not. For fragment start/end 2367 * notification the status is always success. There is no start/end fragment 2368 * notification for monolithic events. 2369 */ 2370enum { 2371 IWM_TE_V1_NOTIF_NONE = 0, 2372 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2373 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2374 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2375 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2376 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2377 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2378 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2379 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2380 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2381}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2382 2383 2384/** 2385 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2386 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2387 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2388 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2389 * @id_and_color: ID and color of the relevant MAC 2390 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2391 * @id: this field has two meanings, depending on the action: 2392 * If the action is ADD, then it means the type of event to add. 2393 * For all other actions it is the unique event ID assigned when the 2394 * event was added by the FW. 2395 * @apply_time: When to start the Time Event (in GP2) 2396 * @max_delay: maximum delay to event's start (apply time), in TU 2397 * @depends_on: the unique ID of the event we depend on (if any) 2398 * @interval: interval between repetitions, in TU 2399 * @interval_reciprocal: 2^32 / interval 2400 * @duration: duration of event in TU 2401 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2402 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2403 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2404 * @is_present: 0 or 1, are we present or absent during the Time Event 2405 * @max_frags: maximal number of fragments the Time Event can be divided to 2406 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2407 */ 2408struct iwm_time_event_cmd_v1 { 2409 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2410 uint32_t id_and_color; 2411 uint32_t action; 2412 uint32_t id; 2413 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2414 uint32_t apply_time; 2415 uint32_t max_delay; 2416 uint32_t dep_policy; 2417 uint32_t depends_on; 2418 uint32_t is_present; 2419 uint32_t max_frags; 2420 uint32_t interval; 2421 uint32_t interval_reciprocal; 2422 uint32_t duration; 2423 uint32_t repeat; 2424 uint32_t notify; 2425} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2426 2427 2428/* Time event - defines for command API v2 */ 2429 2430/* 2431 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2432 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2433 * the first fragment is scheduled. 2434 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2435 * the first 2 fragments are scheduled. 2436 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2437 * number of fragments are valid. 2438 * 2439 * Other than the constant defined above, specifying a fragmentation value 'x' 2440 * means that the event can be fragmented but only the first 'x' will be 2441 * scheduled. 2442 */ 2443enum { 2444 IWM_TE_V2_FRAG_NONE = 0, 2445 IWM_TE_V2_FRAG_SINGLE = 1, 2446 IWM_TE_V2_FRAG_DUAL = 2, 2447 IWM_TE_V2_FRAG_MAX = 0xfe, 2448 IWM_TE_V2_FRAG_ENDLESS = 0xff 2449}; 2450 2451/* Repeat the time event endlessly (until removed) */ 2452#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2453/* If a Time Event has bounded repetitions, this is the maximal value */ 2454#define IWM_TE_V2_REPEAT_MAX 0xfe 2455 2456#define IWM_TE_V2_PLACEMENT_POS 12 2457#define IWM_TE_V2_ABSENCE_POS 15 2458 2459/* Time event policy values (for time event cmd api v2) 2460 * A notification (both event and fragment) includes a status indicating weather 2461 * the FW was able to schedule the event or not. For fragment start/end 2462 * notification the status is always success. There is no start/end fragment 2463 * notification for monolithic events. 2464 * 2465 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2466 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2467 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2468 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2469 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2470 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2471 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2472 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2473 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2474 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2475 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2476 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2477 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2478 */ 2479enum { 2480 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2481 2482 /* notifications (event start/stop, fragment start/stop) */ 2483 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2484 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2485 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2486 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2487 2488 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2489 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2490 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2491 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2492 2493 IWM_TE_V2_NOTIF_MSK = 0xff, 2494 2495 /* placement characteristics */ 2496 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2497 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2498 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2499 2500 /* are we present or absent during the Time Event. */ 2501 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2502}; 2503 2504/** 2505 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2506 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2507 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2508 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2509 * @id_and_color: ID and color of the relevant MAC 2510 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2511 * @id: this field has two meanings, depending on the action: 2512 * If the action is ADD, then it means the type of event to add. 2513 * For all other actions it is the unique event ID assigned when the 2514 * event was added by the FW. 2515 * @apply_time: When to start the Time Event (in GP2) 2516 * @max_delay: maximum delay to event's start (apply time), in TU 2517 * @depends_on: the unique ID of the event we depend on (if any) 2518 * @interval: interval between repetitions, in TU 2519 * @duration: duration of event in TU 2520 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2521 * @max_frags: maximal number of fragments the Time Event can be divided to 2522 * @policy: defines whether uCode shall notify the host or other uCode modules 2523 * on event and/or fragment start and/or end 2524 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2525 * IWM_TE_EVENT_SOCIOPATHIC 2526 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2527 */ 2528struct iwm_time_event_cmd_v2 { 2529 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2530 uint32_t id_and_color; 2531 uint32_t action; 2532 uint32_t id; 2533 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2534 uint32_t apply_time; 2535 uint32_t max_delay; 2536 uint32_t depends_on; 2537 uint32_t interval; 2538 uint32_t duration; 2539 uint8_t repeat; 2540 uint8_t max_frags; 2541 uint16_t policy; 2542} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2543 2544/** 2545 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2546 * @status: bit 0 indicates success, all others specify errors 2547 * @id: the Time Event type 2548 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2549 * @id_and_color: ID and color of the relevant MAC 2550 */ 2551struct iwm_time_event_resp { 2552 uint32_t status; 2553 uint32_t id; 2554 uint32_t unique_id; 2555 uint32_t id_and_color; 2556} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2557 2558/** 2559 * struct iwm_time_event_notif - notifications of time event start/stop 2560 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2561 * @timestamp: action timestamp in GP2 2562 * @session_id: session's unique id 2563 * @unique_id: unique id of the Time Event itself 2564 * @id_and_color: ID and color of the relevant MAC 2565 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2566 * @status: true if scheduled, false otherwise (not executed) 2567 */ 2568struct iwm_time_event_notif { 2569 uint32_t timestamp; 2570 uint32_t session_id; 2571 uint32_t unique_id; 2572 uint32_t id_and_color; 2573 uint32_t action; 2574 uint32_t status; 2575} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2576 2577 2578/* Bindings and Time Quota */ 2579 2580/** 2581 * struct iwm_binding_cmd - configuring bindings 2582 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2583 * @id_and_color: ID and color of the relevant Binding 2584 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2585 * @macs: array of MAC id and colors which belong to the binding 2586 * @phy: PHY id and color which belongs to the binding 2587 */ 2588struct iwm_binding_cmd { 2589 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2590 uint32_t id_and_color; 2591 uint32_t action; 2592 /* IWM_BINDING_DATA_API_S_VER_1 */ 2593 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2594 uint32_t phy; 2595} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2596 2597/* The maximal number of fragments in the FW's schedule session */ 2598#define IWM_MVM_MAX_QUOTA 128 2599 2600/** 2601 * struct iwm_time_quota_data - configuration of time quota per binding 2602 * @id_and_color: ID and color of the relevant Binding 2603 * @quota: absolute time quota in TU. The scheduler will try to divide the 2604 * remainig quota (after Time Events) according to this quota. 2605 * @max_duration: max uninterrupted context duration in TU 2606 */ 2607struct iwm_time_quota_data { 2608 uint32_t id_and_color; 2609 uint32_t quota; 2610 uint32_t max_duration; 2611} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2612 2613/** 2614 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2615 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2616 * @quotas: allocations per binding 2617 */ 2618struct iwm_time_quota_cmd { 2619 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2620} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2621 2622 2623/* PHY context */ 2624 2625/* Supported bands */ 2626#define IWM_PHY_BAND_5 (0) 2627#define IWM_PHY_BAND_24 (1) 2628 2629/* Supported channel width, vary if there is VHT support */ 2630#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2631#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2632#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2633#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2634 2635/* 2636 * Control channel position: 2637 * For legacy set bit means upper channel, otherwise lower. 2638 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2639 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2640 * center_freq 2641 * | 2642 * 40Mhz |_______|_______| 2643 * 80Mhz |_______|_______|_______|_______| 2644 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2645 * code 011 010 001 000 | 100 101 110 111 2646 */ 2647#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2648#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2649#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2650#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2651#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2652#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2653#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2654#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2655 2656/* 2657 * @band: IWM_PHY_BAND_* 2658 * @channel: channel number 2659 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2660 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2661 */ 2662struct iwm_fw_channel_info { 2663 uint8_t band; 2664 uint8_t channel; 2665 uint8_t width; 2666 uint8_t ctrl_pos; 2667} __packed; 2668 2669#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2670#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2671 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2672#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2673#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2674 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2675#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2676#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2677 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2678#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2679#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2680 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2681#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2682#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2683 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2684#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2685#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2686 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2687#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2688#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2689 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2690 2691/* TODO: fix the value, make it depend on firmware at runtime? */ 2692#define IWM_NUM_PHY_CTX 3 2693 2694/* TODO: complete missing documentation */ 2695/** 2696 * struct iwm_phy_context_cmd - config of the PHY context 2697 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2698 * @id_and_color: ID and color of the relevant Binding 2699 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2700 * @apply_time: 0 means immediate apply and context switch. 2701 * other value means apply new params after X usecs 2702 * @tx_param_color: ??? 2703 * @channel_info: 2704 * @txchain_info: ??? 2705 * @rxchain_info: ??? 2706 * @acquisition_data: ??? 2707 * @dsp_cfg_flags: set to 0 2708 */ 2709struct iwm_phy_context_cmd { 2710 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2711 uint32_t id_and_color; 2712 uint32_t action; 2713 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2714 uint32_t apply_time; 2715 uint32_t tx_param_color; 2716 struct iwm_fw_channel_info ci; 2717 uint32_t txchain_info; 2718 uint32_t rxchain_info; 2719 uint32_t acquisition_data; 2720 uint32_t dsp_cfg_flags; 2721} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2722 2723#define IWM_RX_INFO_PHY_CNT 8 2724#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2725#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2726#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2727#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2728#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2729#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2730#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2731 2732#define IWM_RX_INFO_AGC_IDX 1 2733#define IWM_RX_INFO_RSSI_AB_IDX 2 2734#define IWM_OFDM_AGC_A_MSK 0x0000007f 2735#define IWM_OFDM_AGC_A_POS 0 2736#define IWM_OFDM_AGC_B_MSK 0x00003f80 2737#define IWM_OFDM_AGC_B_POS 7 2738#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2739#define IWM_OFDM_AGC_CODE_POS 20 2740#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2741#define IWM_OFDM_RSSI_A_POS 0 2742#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2743#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2744#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2745#define IWM_OFDM_RSSI_B_POS 16 2746#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2747#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2748 2749/** 2750 * struct iwm_rx_phy_info - phy info 2751 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2752 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2753 * @cfg_phy_cnt: configurable DSP phy data byte count 2754 * @stat_id: configurable DSP phy data set ID 2755 * @reserved1: 2756 * @system_timestamp: GP2 at on air rise 2757 * @timestamp: TSF at on air rise 2758 * @beacon_time_stamp: beacon at on-air rise 2759 * @phy_flags: general phy flags: band, modulation, ... 2760 * @channel: channel number 2761 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2762 * @rate_n_flags: IWM_RATE_MCS_* 2763 * @byte_count: frame's byte-count 2764 * @frame_time: frame's time on the air, based on byte count and frame rate 2765 * calculation 2766 * @mac_active_msk: what MACs were active when the frame was received 2767 * 2768 * Before each Rx, the device sends this data. It contains PHY information 2769 * about the reception of the packet. 2770 */ 2771struct iwm_rx_phy_info { 2772 uint8_t non_cfg_phy_cnt; 2773 uint8_t cfg_phy_cnt; 2774 uint8_t stat_id; 2775 uint8_t reserved1; 2776 uint32_t system_timestamp; 2777 uint64_t timestamp; 2778 uint32_t beacon_time_stamp; 2779 uint16_t phy_flags; 2780#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2781 uint16_t channel; 2782 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2783 uint8_t rate; 2784 uint8_t rflags; 2785 uint16_t xrflags; 2786 uint32_t byte_count; 2787 uint16_t mac_active_msk; 2788 uint16_t frame_time; 2789} __packed; 2790 2791struct iwm_rx_mpdu_res_start { 2792 uint16_t byte_count; 2793 uint16_t reserved; 2794} __packed; 2795 2796/** 2797 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2798 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2799 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2800 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2801 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2802 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2803 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2804 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2805 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2806 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2807 */ 2808enum iwm_rx_phy_flags { 2809 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2810 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2811 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2812 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2813 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2814 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2815 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2816 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2817 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2818 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2819}; 2820 2821/** 2822 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2823 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2824 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2825 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2826 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2827 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2828 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2829 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2830 * in the driver. 2831 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2832 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2833 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2834 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2835 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2836 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2837 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2838 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2839 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2840 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2841 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2842 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2843 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2844 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2845 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2846 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2847 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2848 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2849 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2850 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2851 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2852 */ 2853enum iwm_mvm_rx_status { 2854 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2855 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2856 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2857 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2858 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2859 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2860 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2861 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2862 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2863 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2864 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2865 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2866 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2867 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2868 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2869 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2870 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2871 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2872 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2873 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2874 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2875 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2876 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2877 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2878 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2879 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2880 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2881}; 2882 2883/** 2884 * struct iwm_radio_version_notif - information on the radio version 2885 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2886 * @radio_flavor: 2887 * @radio_step: 2888 * @radio_dash: 2889 */ 2890struct iwm_radio_version_notif { 2891 uint32_t radio_flavor; 2892 uint32_t radio_step; 2893 uint32_t radio_dash; 2894} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2895 2896enum iwm_card_state_flags { 2897 IWM_CARD_ENABLED = 0x00, 2898 IWM_HW_CARD_DISABLED = 0x01, 2899 IWM_SW_CARD_DISABLED = 0x02, 2900 IWM_CT_KILL_CARD_DISABLED = 0x04, 2901 IWM_HALT_CARD_DISABLED = 0x08, 2902 IWM_CARD_DISABLED_MSK = 0x0f, 2903 IWM_CARD_IS_RX_ON = 0x10, 2904}; 2905 2906/** 2907 * struct iwm_radio_version_notif - information on the radio version 2908 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2909 * @flags: %iwm_card_state_flags 2910 */ 2911struct iwm_card_state_notif { 2912 uint32_t flags; 2913} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2914 2915/** 2916 * struct iwm_missed_beacons_notif - information on missed beacons 2917 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2918 * @mac_id: interface ID 2919 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2920 * beacons since last RX. 2921 * @consec_missed_beacons: number of consecutive missed beacons 2922 * @num_expected_beacons: 2923 * @num_recvd_beacons: 2924 */ 2925struct iwm_missed_beacons_notif { 2926 uint32_t mac_id; 2927 uint32_t consec_missed_beacons_since_last_rx; 2928 uint32_t consec_missed_beacons; 2929 uint32_t num_expected_beacons; 2930 uint32_t num_recvd_beacons; 2931} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2932 2933/** 2934 * struct iwm_mfuart_load_notif - mfuart image version & status 2935 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2936 * @installed_ver: installed image version 2937 * @external_ver: external image version 2938 * @status: MFUART loading status 2939 * @duration: MFUART loading time 2940*/ 2941struct iwm_mfuart_load_notif { 2942 uint32_t installed_ver; 2943 uint32_t external_ver; 2944 uint32_t status; 2945 uint32_t duration; 2946} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2947 2948/** 2949 * struct iwm_set_calib_default_cmd - set default value for calibration. 2950 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2951 * @calib_index: the calibration to set value for 2952 * @length: of data 2953 * @data: the value to set for the calibration result 2954 */ 2955struct iwm_set_calib_default_cmd { 2956 uint16_t calib_index; 2957 uint16_t length; 2958 uint8_t data[0]; 2959} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2960 2961#define IWM_MAX_PORT_ID_NUM 2 2962#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2963 2964/** 2965 * struct iwm_mcast_filter_cmd - configure multicast filter. 2966 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2967 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2968 * to identify network interface adopted in host-device IF. 2969 * It is used by FW as index in array of addresses. This array has 2970 * IWM_MAX_PORT_ID_NUM members. 2971 * @count: Number of MAC addresses in the array 2972 * @pass_all: Set 1 to pass all multicast packets. 2973 * @bssid: current association BSSID. 2974 * @addr_list: Place holder for array of MAC addresses. 2975 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2976 */ 2977struct iwm_mcast_filter_cmd { 2978 uint8_t filter_own; 2979 uint8_t port_id; 2980 uint8_t count; 2981 uint8_t pass_all; 2982 uint8_t bssid[6]; 2983 uint8_t reserved[2]; 2984 uint8_t addr_list[0]; 2985} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2986 2987struct iwm_mvm_statistics_dbg { 2988 uint32_t burst_check; 2989 uint32_t burst_count; 2990 uint32_t wait_for_silence_timeout_cnt; 2991 uint32_t reserved[3]; 2992} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2993 2994struct iwm_mvm_statistics_div { 2995 uint32_t tx_on_a; 2996 uint32_t tx_on_b; 2997 uint32_t exec_time; 2998 uint32_t probe_time; 2999 uint32_t rssi_ant; 3000 uint32_t reserved2; 3001} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3002 3003struct iwm_mvm_statistics_general_common { 3004 uint32_t temperature; /* radio temperature */ 3005 uint32_t temperature_m; /* radio voltage */ 3006 struct iwm_mvm_statistics_dbg dbg; 3007 uint32_t sleep_time; 3008 uint32_t slots_out; 3009 uint32_t slots_idle; 3010 uint32_t ttl_timestamp; 3011 struct iwm_mvm_statistics_div div; 3012 uint32_t rx_enable_counter; 3013 /* 3014 * num_of_sos_states: 3015 * count the number of times we have to re-tune 3016 * in order to get out of bad PHY status 3017 */ 3018 uint32_t num_of_sos_states; 3019} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3020 3021struct iwm_mvm_statistics_rx_non_phy { 3022 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3023 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3024 uint32_t non_bssid_frames; /* number of frames with BSSID that 3025 * doesn't belong to the STA BSSID */ 3026 uint32_t filtered_frames; /* count frames that were dumped in the 3027 * filtering process */ 3028 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3029 * our serving channel */ 3030 uint32_t channel_beacons; /* beacons with our bss id and in our 3031 * serving channel */ 3032 uint32_t num_missed_bcon; /* number of missed beacons */ 3033 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3034 * ADC was in saturation */ 3035 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3036 * for INA */ 3037 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3038 uint32_t interference_data_flag; /* flag for interference data 3039 * availability. 1 when data is 3040 * available. */ 3041 uint32_t channel_load; /* counts RX Enable time in uSec */ 3042 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3043 * and CCK) counter */ 3044 uint32_t beacon_rssi_a; 3045 uint32_t beacon_rssi_b; 3046 uint32_t beacon_rssi_c; 3047 uint32_t beacon_energy_a; 3048 uint32_t beacon_energy_b; 3049 uint32_t beacon_energy_c; 3050 uint32_t num_bt_kills; 3051 uint32_t mac_id; 3052 uint32_t directed_data_mpdu; 3053} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3054 3055struct iwm_mvm_statistics_rx_phy { 3056 uint32_t ina_cnt; 3057 uint32_t fina_cnt; 3058 uint32_t plcp_err; 3059 uint32_t crc32_err; 3060 uint32_t overrun_err; 3061 uint32_t early_overrun_err; 3062 uint32_t crc32_good; 3063 uint32_t false_alarm_cnt; 3064 uint32_t fina_sync_err_cnt; 3065 uint32_t sfd_timeout; 3066 uint32_t fina_timeout; 3067 uint32_t unresponded_rts; 3068 uint32_t rxe_frame_limit_overrun; 3069 uint32_t sent_ack_cnt; 3070 uint32_t sent_cts_cnt; 3071 uint32_t sent_ba_rsp_cnt; 3072 uint32_t dsp_self_kill; 3073 uint32_t mh_format_err; 3074 uint32_t re_acq_main_rssi_sum; 3075 uint32_t reserved; 3076} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3077 3078struct iwm_mvm_statistics_rx_ht_phy { 3079 uint32_t plcp_err; 3080 uint32_t overrun_err; 3081 uint32_t early_overrun_err; 3082 uint32_t crc32_good; 3083 uint32_t crc32_err; 3084 uint32_t mh_format_err; 3085 uint32_t agg_crc32_good; 3086 uint32_t agg_mpdu_cnt; 3087 uint32_t agg_cnt; 3088 uint32_t unsupport_mcs; 3089} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3090 3091#define IWM_MAX_CHAINS 3 3092 3093struct iwm_mvm_statistics_tx_non_phy_agg { 3094 uint32_t ba_timeout; 3095 uint32_t ba_reschedule_frames; 3096 uint32_t scd_query_agg_frame_cnt; 3097 uint32_t scd_query_no_agg; 3098 uint32_t scd_query_agg; 3099 uint32_t scd_query_mismatch; 3100 uint32_t frame_not_ready; 3101 uint32_t underrun; 3102 uint32_t bt_prio_kill; 3103 uint32_t rx_ba_rsp_cnt; 3104 int8_t txpower[IWM_MAX_CHAINS]; 3105 int8_t reserved; 3106 uint32_t reserved2; 3107} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3108 3109struct iwm_mvm_statistics_tx_channel_width { 3110 uint32_t ext_cca_narrow_ch20[1]; 3111 uint32_t ext_cca_narrow_ch40[2]; 3112 uint32_t ext_cca_narrow_ch80[3]; 3113 uint32_t ext_cca_narrow_ch160[4]; 3114 uint32_t last_tx_ch_width_indx; 3115 uint32_t rx_detected_per_ch_width[4]; 3116 uint32_t success_per_ch_width[4]; 3117 uint32_t fail_per_ch_width[4]; 3118}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3119 3120struct iwm_mvm_statistics_tx { 3121 uint32_t preamble_cnt; 3122 uint32_t rx_detected_cnt; 3123 uint32_t bt_prio_defer_cnt; 3124 uint32_t bt_prio_kill_cnt; 3125 uint32_t few_bytes_cnt; 3126 uint32_t cts_timeout; 3127 uint32_t ack_timeout; 3128 uint32_t expected_ack_cnt; 3129 uint32_t actual_ack_cnt; 3130 uint32_t dump_msdu_cnt; 3131 uint32_t burst_abort_next_frame_mismatch_cnt; 3132 uint32_t burst_abort_missing_next_frame_cnt; 3133 uint32_t cts_timeout_collision; 3134 uint32_t ack_or_ba_timeout_collision; 3135 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3136 struct iwm_mvm_statistics_tx_channel_width channel_width; 3137} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3138 3139 3140struct iwm_mvm_statistics_bt_activity { 3141 uint32_t hi_priority_tx_req_cnt; 3142 uint32_t hi_priority_tx_denied_cnt; 3143 uint32_t lo_priority_tx_req_cnt; 3144 uint32_t lo_priority_tx_denied_cnt; 3145 uint32_t hi_priority_rx_req_cnt; 3146 uint32_t hi_priority_rx_denied_cnt; 3147 uint32_t lo_priority_rx_req_cnt; 3148 uint32_t lo_priority_rx_denied_cnt; 3149} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3150 3151struct iwm_mvm_statistics_general { 3152 struct iwm_mvm_statistics_general_common common; 3153 uint32_t beacon_filtered; 3154 uint32_t missed_beacons; 3155 int8_t beacon_filter_average_energy; 3156 int8_t beacon_filter_reason; 3157 int8_t beacon_filter_current_energy; 3158 int8_t beacon_filter_reserved; 3159 uint32_t beacon_filter_delta_time; 3160 struct iwm_mvm_statistics_bt_activity bt_activity; 3161} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3162 3163struct iwm_mvm_statistics_rx { 3164 struct iwm_mvm_statistics_rx_phy ofdm; 3165 struct iwm_mvm_statistics_rx_phy cck; 3166 struct iwm_mvm_statistics_rx_non_phy general; 3167 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3168} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3169 3170/* 3171 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3172 * 3173 * By default, uCode issues this notification after receiving a beacon 3174 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3175 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3176 * 3177 * Statistics counters continue to increment beacon after beacon, but are 3178 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3179 * 0x9c with CLEAR_STATS bit set (see above). 3180 * 3181 * uCode also issues this notification during scans. uCode clears statistics 3182 * appropriately so that each notification contains statistics for only the 3183 * one channel that has just been scanned. 3184 */ 3185 3186struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3187 uint32_t flag; 3188 struct iwm_mvm_statistics_rx rx; 3189 struct iwm_mvm_statistics_tx tx; 3190 struct iwm_mvm_statistics_general general; 3191} __packed; 3192 3193/*********************************** 3194 * Smart Fifo API 3195 ***********************************/ 3196/* Smart Fifo state */ 3197enum iwm_sf_state { 3198 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3199 IWM_SF_FULL_ON, 3200 IWM_SF_UNINIT, 3201 IWM_SF_INIT_OFF, 3202 IWM_SF_HW_NUM_STATES 3203}; 3204 3205/* Smart Fifo possible scenario */ 3206enum iwm_sf_scenario { 3207 IWM_SF_SCENARIO_SINGLE_UNICAST, 3208 IWM_SF_SCENARIO_AGG_UNICAST, 3209 IWM_SF_SCENARIO_MULTICAST, 3210 IWM_SF_SCENARIO_BA_RESP, 3211 IWM_SF_SCENARIO_TX_RESP, 3212 IWM_SF_NUM_SCENARIO 3213}; 3214 3215#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3216#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3217 3218/* smart FIFO default values */ 3219#define IWM_SF_W_MARK_SISO 4096 3220#define IWM_SF_W_MARK_MIMO2 8192 3221#define IWM_SF_W_MARK_MIMO3 6144 3222#define IWM_SF_W_MARK_LEGACY 4096 3223#define IWM_SF_W_MARK_SCAN 4096 3224 3225/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3226#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3227#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3228#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3229#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3230#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3231#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3232#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3233#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3234#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3235#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3236 3237/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3238#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3239#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3240#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3241#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3242#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3243#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3244#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3245#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3246#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3247#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3248 3249#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3250 3251#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3252 3253/** 3254 * Smart Fifo configuration command. 3255 * @state: smart fifo state, types listed in iwm_sf_state. 3256 * @watermark: Minimum allowed available free space in RXF for transient state. 3257 * @long_delay_timeouts: aging and idle timer values for each scenario 3258 * in long delay state. 3259 * @full_on_timeouts: timer values for each scenario in full on state. 3260 */ 3261struct iwm_sf_cfg_cmd { 3262 uint32_t state; 3263 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3264 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3265 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3266} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3267 3268/* 3269 * END mvm/fw-api.h 3270 */ 3271 3272/* 3273 * BEGIN mvm/fw-api-mac.h 3274 */ 3275 3276/* 3277 * The first MAC indices (starting from 0) 3278 * are available to the driver, AUX follows 3279 */ 3280#define IWM_MAC_INDEX_AUX 4 3281#define IWM_MAC_INDEX_MIN_DRIVER 0 3282#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3283 3284enum iwm_ac { 3285 IWM_AC_BK, 3286 IWM_AC_BE, 3287 IWM_AC_VI, 3288 IWM_AC_VO, 3289 IWM_AC_NUM, 3290}; 3291 3292/** 3293 * enum iwm_mac_protection_flags - MAC context flags 3294 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3295 * this will require CCK RTS/CTS2self. 3296 * RTS/CTS will protect full burst time. 3297 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3298 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3299 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3300 */ 3301enum iwm_mac_protection_flags { 3302 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3303 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3304 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3305 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3306}; 3307 3308#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3309#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3310 3311/** 3312 * enum iwm_mac_types - Supported MAC types 3313 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3314 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3315 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3316 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3317 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3318 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3319 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3320 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3321 * @IWM_FW_MAC_TYPE_GO: P2P GO 3322 * @IWM_FW_MAC_TYPE_TEST: ? 3323 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3324 */ 3325enum iwm_mac_types { 3326 IWM_FW_MAC_TYPE_FIRST = 1, 3327 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3328 IWM_FW_MAC_TYPE_LISTENER, 3329 IWM_FW_MAC_TYPE_PIBSS, 3330 IWM_FW_MAC_TYPE_IBSS, 3331 IWM_FW_MAC_TYPE_BSS_STA, 3332 IWM_FW_MAC_TYPE_P2P_DEVICE, 3333 IWM_FW_MAC_TYPE_P2P_STA, 3334 IWM_FW_MAC_TYPE_GO, 3335 IWM_FW_MAC_TYPE_TEST, 3336 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3337}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3338 3339/** 3340 * enum iwm_tsf_id - TSF hw timer ID 3341 * @IWM_TSF_ID_A: use TSF A 3342 * @IWM_TSF_ID_B: use TSF B 3343 * @IWM_TSF_ID_C: use TSF C 3344 * @IWM_TSF_ID_D: use TSF D 3345 * @IWM_NUM_TSF_IDS: number of TSF timers available 3346 */ 3347enum iwm_tsf_id { 3348 IWM_TSF_ID_A = 0, 3349 IWM_TSF_ID_B = 1, 3350 IWM_TSF_ID_C = 2, 3351 IWM_TSF_ID_D = 3, 3352 IWM_NUM_TSF_IDS = 4, 3353}; /* IWM_TSF_ID_API_E_VER_1 */ 3354 3355/** 3356 * struct iwm_mac_data_ap - configuration data for AP MAC context 3357 * @beacon_time: beacon transmit time in system time 3358 * @beacon_tsf: beacon transmit time in TSF 3359 * @bi: beacon interval in TU 3360 * @bi_reciprocal: 2^32 / bi 3361 * @dtim_interval: dtim transmit time in TU 3362 * @dtim_reciprocal: 2^32 / dtim_interval 3363 * @mcast_qid: queue ID for multicast traffic 3364 * @beacon_template: beacon template ID 3365 */ 3366struct iwm_mac_data_ap { 3367 uint32_t beacon_time; 3368 uint64_t beacon_tsf; 3369 uint32_t bi; 3370 uint32_t bi_reciprocal; 3371 uint32_t dtim_interval; 3372 uint32_t dtim_reciprocal; 3373 uint32_t mcast_qid; 3374 uint32_t beacon_template; 3375} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3376 3377/** 3378 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3379 * @beacon_time: beacon transmit time in system time 3380 * @beacon_tsf: beacon transmit time in TSF 3381 * @bi: beacon interval in TU 3382 * @bi_reciprocal: 2^32 / bi 3383 * @beacon_template: beacon template ID 3384 */ 3385struct iwm_mac_data_ibss { 3386 uint32_t beacon_time; 3387 uint64_t beacon_tsf; 3388 uint32_t bi; 3389 uint32_t bi_reciprocal; 3390 uint32_t beacon_template; 3391} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3392 3393/** 3394 * struct iwm_mac_data_sta - configuration data for station MAC context 3395 * @is_assoc: 1 for associated state, 0 otherwise 3396 * @dtim_time: DTIM arrival time in system time 3397 * @dtim_tsf: DTIM arrival time in TSF 3398 * @bi: beacon interval in TU, applicable only when associated 3399 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3400 * @dtim_interval: DTIM interval in TU, applicable only when associated 3401 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3402 * @listen_interval: in beacon intervals, applicable only when associated 3403 * @assoc_id: unique ID assigned by the AP during association 3404 */ 3405struct iwm_mac_data_sta { 3406 uint32_t is_assoc; 3407 uint32_t dtim_time; 3408 uint64_t dtim_tsf; 3409 uint32_t bi; 3410 uint32_t bi_reciprocal; 3411 uint32_t dtim_interval; 3412 uint32_t dtim_reciprocal; 3413 uint32_t listen_interval; 3414 uint32_t assoc_id; 3415 uint32_t assoc_beacon_arrive_time; 3416} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3417 3418/** 3419 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3420 * @ap: iwm_mac_data_ap struct with most config data 3421 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3422 * 0 indicates that there is no CT window. 3423 * @opp_ps_enabled: indicate that opportunistic PS allowed 3424 */ 3425struct iwm_mac_data_go { 3426 struct iwm_mac_data_ap ap; 3427 uint32_t ctwin; 3428 uint32_t opp_ps_enabled; 3429} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3430 3431/** 3432 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3433 * @sta: iwm_mac_data_sta struct with most config data 3434 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3435 * 0 indicates that there is no CT window. 3436 */ 3437struct iwm_mac_data_p2p_sta { 3438 struct iwm_mac_data_sta sta; 3439 uint32_t ctwin; 3440} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3441 3442/** 3443 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3444 * @stats_interval: interval in TU between statistics notifications to host. 3445 */ 3446struct iwm_mac_data_pibss { 3447 uint32_t stats_interval; 3448} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3449 3450/* 3451 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3452 * context. 3453 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3454 * other channels as well. This should be to true only in case that the 3455 * device is discoverable and there is an active GO. Note that setting this 3456 * field when not needed, will increase the number of interrupts and have 3457 * effect on the platform power, as this setting opens the Rx filters on 3458 * all macs. 3459 */ 3460struct iwm_mac_data_p2p_dev { 3461 uint32_t is_disc_extended; 3462} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3463 3464/** 3465 * enum iwm_mac_filter_flags - MAC context filter flags 3466 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3467 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3468 * control frames to the host 3469 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3470 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3471 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3472 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3473 * (in station mode when associated) 3474 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3475 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3476 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3477 */ 3478enum iwm_mac_filter_flags { 3479 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3480 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3481 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3482 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3483 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3484 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3485 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3486 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3487 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3488}; 3489 3490/** 3491 * enum iwm_mac_qos_flags - QoS flags 3492 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3493 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3494 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3495 * 3496 */ 3497enum iwm_mac_qos_flags { 3498 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3499 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3500 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3501}; 3502 3503/** 3504 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3505 * @cw_min: Contention window, start value in numbers of slots. 3506 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3507 * @cw_max: Contention window, max value in numbers of slots. 3508 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3509 * @aifsn: Number of slots in Arbitration Interframe Space (before 3510 * performing random backoff timing prior to Tx). Device default 1. 3511 * @fifos_mask: FIFOs used by this MAC for this AC 3512 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3513 * 3514 * One instance of this config struct for each of 4 EDCA access categories 3515 * in struct iwm_qosparam_cmd. 3516 * 3517 * Device will automatically increase contention window by (2*CW) + 1 for each 3518 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3519 * value, to cap the CW value. 3520 */ 3521struct iwm_ac_qos { 3522 uint16_t cw_min; 3523 uint16_t cw_max; 3524 uint8_t aifsn; 3525 uint8_t fifos_mask; 3526 uint16_t edca_txop; 3527} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3528 3529/** 3530 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3531 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3532 * @id_and_color: ID and color of the MAC 3533 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3534 * @mac_type: one of IWM_FW_MAC_TYPE_* 3535 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3536 * @node_addr: MAC address 3537 * @bssid_addr: BSSID 3538 * @cck_rates: basic rates available for CCK 3539 * @ofdm_rates: basic rates available for OFDM 3540 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3541 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3542 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3543 * @filter_flags: combination of IWM_MAC_FILTER_* 3544 * @qos_flags: from IWM_MAC_QOS_FLG_* 3545 * @ac: one iwm_mac_qos configuration for each AC 3546 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3547 */ 3548struct iwm_mac_ctx_cmd { 3549 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3550 uint32_t id_and_color; 3551 uint32_t action; 3552 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3553 uint32_t mac_type; 3554 uint32_t tsf_id; 3555 uint8_t node_addr[6]; 3556 uint16_t reserved_for_node_addr; 3557 uint8_t bssid_addr[6]; 3558 uint16_t reserved_for_bssid_addr; 3559 uint32_t cck_rates; 3560 uint32_t ofdm_rates; 3561 uint32_t protection_flags; 3562 uint32_t cck_short_preamble; 3563 uint32_t short_slot; 3564 uint32_t filter_flags; 3565 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3566 uint32_t qos_flags; 3567 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3568 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3569 union { 3570 struct iwm_mac_data_ap ap; 3571 struct iwm_mac_data_go go; 3572 struct iwm_mac_data_sta sta; 3573 struct iwm_mac_data_p2p_sta p2p_sta; 3574 struct iwm_mac_data_p2p_dev p2p_dev; 3575 struct iwm_mac_data_pibss pibss; 3576 struct iwm_mac_data_ibss ibss; 3577 }; 3578} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3579 3580static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3581{ 3582 if (!v) 3583 return 0; 3584 return 0xFFFFFFFF / v; 3585} 3586 3587#define IWM_NONQOS_SEQ_GET 0x1 3588#define IWM_NONQOS_SEQ_SET 0x2 3589struct iwm_nonqos_seq_query_cmd { 3590 uint32_t get_set_flag; 3591 uint32_t mac_id_n_color; 3592 uint16_t value; 3593 uint16_t reserved; 3594} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3595 3596/* 3597 * END mvm/fw-api-mac.h 3598 */ 3599 3600/* 3601 * BEGIN mvm/fw-api-power.h 3602 */ 3603 3604/* Power Management Commands, Responses, Notifications */ 3605 3606/* Radio LP RX Energy Threshold measured in dBm */ 3607#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3608#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3609#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3610 3611/** 3612 * enum iwm_scan_flags - masks for power table command flags 3613 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3614 * receiver and transmitter. '0' - does not allow. 3615 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3616 * '1' Driver enables PM (use rest of parameters) 3617 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3618 * '1' PM could sleep over DTIM till listen Interval. 3619 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3620 * access categories are both delivery and trigger enabled. 3621 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3622 * PBW Snoozing enabled 3623 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3624 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3625 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3626 * detection enablement 3627*/ 3628enum iwm_power_flags { 3629 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3630 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3631 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3632 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3633 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3634 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3635 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3636 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3637}; 3638 3639#define IWM_POWER_VEC_SIZE 5 3640 3641/** 3642 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3643 * is used also with a new power API for device wide power settings. 3644 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3645 * 3646 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3647 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3648 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3649 * set regardless of power scheme or current power state. 3650 * FW use this value also when PM is disabled. 3651 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3652 * PSM transition - legacy PM 3653 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3654 * PSM transition - legacy PM 3655 * @sleep_interval: not in use 3656 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3657 * is set. For example, if it is required to skip over 3658 * one DTIM, this value need to be set to 2 (DTIM periods). 3659 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3660 * Default: 80dbm 3661 */ 3662struct iwm_powertable_cmd { 3663 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3664 uint16_t flags; 3665 uint8_t keep_alive_seconds; 3666 uint8_t debug_flags; 3667 uint32_t rx_data_timeout; 3668 uint32_t tx_data_timeout; 3669 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3670 uint32_t skip_dtim_periods; 3671 uint32_t lprx_rssi_threshold; 3672} __packed; 3673 3674/** 3675 * enum iwm_device_power_flags - masks for device power command flags 3676 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3677 * receiver and transmitter. '0' - does not allow. This flag should be 3678 * always set to '1' unless one need to disable actual power down for debug 3679 * purposes. 3680 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3681 * that power management is disabled. '0' Power management is enabled, one 3682 * of power schemes is applied. 3683*/ 3684enum iwm_device_power_flags { 3685 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3686 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3687}; 3688 3689/** 3690 * struct iwm_device_power_cmd - device wide power command. 3691 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3692 * 3693 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3694 */ 3695struct iwm_device_power_cmd { 3696 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3697 uint16_t flags; 3698 uint16_t reserved; 3699} __packed; 3700 3701/** 3702 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3703 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3704 * @id_and_color: MAC contex identifier 3705 * @flags: Power table command flags from POWER_FLAGS_* 3706 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3707 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3708 * set regardless of power scheme or current power state. 3709 * FW use this value also when PM is disabled. 3710 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3711 * PSM transition - legacy PM 3712 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3713 * PSM transition - legacy PM 3714 * @sleep_interval: not in use 3715 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3716 * is set. For example, if it is required to skip over 3717 * one DTIM, this value need to be set to 2 (DTIM periods). 3718 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3719 * PSM transition - uAPSD 3720 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3721 * PSM transition - uAPSD 3722 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3723 * Default: 80dbm 3724 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3725 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3726 * from the AP [msec] 3727 * @snooze_window: A window of time in which PBW snoozing insures that all 3728 * packets received. It is also the minimum time from last 3729 * received unicast RX packet, before client stops snoozing 3730 * for data. [msec] 3731 * @snooze_step: TBD 3732 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3733 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3734 * each corresponding AC. 3735 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3736 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3737 * values. 3738 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3739 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3740 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3741 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3742 * @limited_ps_threshold: 3743*/ 3744struct iwm_mac_power_cmd { 3745 /* CONTEXT_DESC_API_T_VER_1 */ 3746 uint32_t id_and_color; 3747 3748 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3749 uint16_t flags; 3750 uint16_t keep_alive_seconds; 3751 uint32_t rx_data_timeout; 3752 uint32_t tx_data_timeout; 3753 uint32_t rx_data_timeout_uapsd; 3754 uint32_t tx_data_timeout_uapsd; 3755 uint8_t lprx_rssi_threshold; 3756 uint8_t skip_dtim_periods; 3757 uint16_t snooze_interval; 3758 uint16_t snooze_window; 3759 uint8_t snooze_step; 3760 uint8_t qndp_tid; 3761 uint8_t uapsd_ac_flags; 3762 uint8_t uapsd_max_sp; 3763 uint8_t heavy_tx_thld_packets; 3764 uint8_t heavy_rx_thld_packets; 3765 uint8_t heavy_tx_thld_percentage; 3766 uint8_t heavy_rx_thld_percentage; 3767 uint8_t limited_ps_threshold; 3768 uint8_t reserved; 3769} __packed; 3770 3771/* 3772 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3773 * associated AP is identified as improperly implementing uAPSD protocol. 3774 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3775 * @sta_id: index of station in uCode's station table - associated AP ID in 3776 * this context. 3777 */ 3778struct iwm_uapsd_misbehaving_ap_notif { 3779 uint32_t sta_id; 3780 uint8_t mac_id; 3781 uint8_t reserved[3]; 3782} __packed; 3783 3784/** 3785 * struct iwm_beacon_filter_cmd 3786 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3787 * @id_and_color: MAC contex identifier 3788 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3789 * to driver if delta in Energy values calculated for this and last 3790 * passed beacon is greater than this threshold. Zero value means that 3791 * the Energy change is ignored for beacon filtering, and beacon will 3792 * not be forced to be sent to driver regardless of this delta. Typical 3793 * energy delta 5dB. 3794 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3795 * Send beacon to driver if delta in Energy values calculated for this 3796 * and last passed beacon is greater than this threshold. Zero value 3797 * means that the Energy change is ignored for beacon filtering while in 3798 * Roaming state, typical energy delta 1dB. 3799 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3800 * calculated for current beacon is less than the threshold, use 3801 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3802 * Threshold. Typical energy threshold is -72dBm. 3803 * @bf_temp_threshold: This threshold determines the type of temperature 3804 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3805 * If the current temperature is above this threshold - Fast filter 3806 * will be used, If the current temperature is below this threshold - 3807 * Slow filter will be used. 3808 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3809 * calculated for this and the last passed beacon is greater than this 3810 * threshold. Zero value means that the temperature change is ignored for 3811 * beacon filtering; beacons will not be forced to be sent to driver 3812 * regardless of whether its temperature has been changed. 3813 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3814 * calculated for this and the last passed beacon is greater than this 3815 * threshold. Zero value means that the temperature change is ignored for 3816 * beacon filtering; beacons will not be forced to be sent to driver 3817 * regardless of whether its temperature has been changed. 3818 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3819 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3820 * for a specific period of time. Units: Beacons. 3821 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3822 * for a longer period of time then this escape-timeout. Units: Beacons. 3823 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3824 */ 3825struct iwm_beacon_filter_cmd { 3826 uint32_t bf_energy_delta; 3827 uint32_t bf_roaming_energy_delta; 3828 uint32_t bf_roaming_state; 3829 uint32_t bf_temp_threshold; 3830 uint32_t bf_temp_fast_filter; 3831 uint32_t bf_temp_slow_filter; 3832 uint32_t bf_enable_beacon_filter; 3833 uint32_t bf_debug_flag; 3834 uint32_t bf_escape_timer; 3835 uint32_t ba_escape_timer; 3836 uint32_t ba_enable_beacon_abort; 3837} __packed; 3838 3839/* Beacon filtering and beacon abort */ 3840#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3841#define IWM_BF_ENERGY_DELTA_MAX 255 3842#define IWM_BF_ENERGY_DELTA_MIN 0 3843 3844#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3845#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3846#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3847 3848#define IWM_BF_ROAMING_STATE_DEFAULT 72 3849#define IWM_BF_ROAMING_STATE_MAX 255 3850#define IWM_BF_ROAMING_STATE_MIN 0 3851 3852#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3853#define IWM_BF_TEMP_THRESHOLD_MAX 255 3854#define IWM_BF_TEMP_THRESHOLD_MIN 0 3855 3856#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3857#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3858#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3859 3860#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3861#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3862#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3863 3864#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3865 3866#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3867 3868#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3869#define IWM_BF_ESCAPE_TIMER_MAX 1024 3870#define IWM_BF_ESCAPE_TIMER_MIN 0 3871 3872#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3873#define IWM_BA_ESCAPE_TIMER_D3 9 3874#define IWM_BA_ESCAPE_TIMER_MAX 1024 3875#define IWM_BA_ESCAPE_TIMER_MIN 0 3876 3877#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3878 3879#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3880 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3881 .bf_roaming_energy_delta = \ 3882 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3883 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3884 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3885 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3886 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3887 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3888 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3889 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3890 3891/* 3892 * END mvm/fw-api-power.h 3893 */ 3894 3895/* 3896 * BEGIN mvm/fw-api-rs.h 3897 */ 3898 3899/* 3900 * These serve as indexes into 3901 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3902 * TODO: avoid overlap between legacy and HT rates 3903 */ 3904enum { 3905 IWM_RATE_1M_INDEX = 0, 3906 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3907 IWM_RATE_2M_INDEX, 3908 IWM_RATE_5M_INDEX, 3909 IWM_RATE_11M_INDEX, 3910 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3911 IWM_RATE_6M_INDEX, 3912 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3913 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3914 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3915 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3916 IWM_RATE_9M_INDEX, 3917 IWM_RATE_12M_INDEX, 3918 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3919 IWM_RATE_18M_INDEX, 3920 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3921 IWM_RATE_24M_INDEX, 3922 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3923 IWM_RATE_36M_INDEX, 3924 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3925 IWM_RATE_48M_INDEX, 3926 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3927 IWM_RATE_54M_INDEX, 3928 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3929 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3930 IWM_RATE_60M_INDEX, 3931 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3932 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3933 IWM_RATE_MCS_8_INDEX, 3934 IWM_RATE_MCS_9_INDEX, 3935 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3936 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3937 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3938}; 3939 3940#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3941 3942/* fw API values for legacy bit rates, both OFDM and CCK */ 3943enum { 3944 IWM_RATE_6M_PLCP = 13, 3945 IWM_RATE_9M_PLCP = 15, 3946 IWM_RATE_12M_PLCP = 5, 3947 IWM_RATE_18M_PLCP = 7, 3948 IWM_RATE_24M_PLCP = 9, 3949 IWM_RATE_36M_PLCP = 11, 3950 IWM_RATE_48M_PLCP = 1, 3951 IWM_RATE_54M_PLCP = 3, 3952 IWM_RATE_1M_PLCP = 10, 3953 IWM_RATE_2M_PLCP = 20, 3954 IWM_RATE_5M_PLCP = 55, 3955 IWM_RATE_11M_PLCP = 110, 3956 IWM_RATE_INVM_PLCP = -1, 3957}; 3958 3959/* 3960 * rate_n_flags bit fields 3961 * 3962 * The 32-bit value has different layouts in the low 8 bites depending on the 3963 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3964 * for CCK and OFDM). 3965 * 3966 * High-throughput (HT) rate format 3967 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3968 * Very High-throughput (VHT) rate format 3969 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3970 * Legacy OFDM rate format for bits 7:0 3971 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3972 * Legacy CCK rate format for bits 7:0: 3973 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3974 */ 3975 3976/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3977#define IWM_RATE_MCS_HT_POS 8 3978#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3979 3980/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3981#define IWM_RATE_MCS_CCK_POS 9 3982#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3983 3984/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3985#define IWM_RATE_MCS_VHT_POS 26 3986#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3987 3988 3989/* 3990 * High-throughput (HT) rate format for bits 7:0 3991 * 3992 * 2-0: MCS rate base 3993 * 0) 6 Mbps 3994 * 1) 12 Mbps 3995 * 2) 18 Mbps 3996 * 3) 24 Mbps 3997 * 4) 36 Mbps 3998 * 5) 48 Mbps 3999 * 6) 54 Mbps 4000 * 7) 60 Mbps 4001 * 4-3: 0) Single stream (SISO) 4002 * 1) Dual stream (MIMO) 4003 * 2) Triple stream (MIMO) 4004 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4005 * (bits 7-6 are zero) 4006 * 4007 * Together the low 5 bits work out to the MCS index because we don't 4008 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4009 * streams and 16-23 have three streams. We could also support MCS 32 4010 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4011 */ 4012#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4013#define IWM_RATE_HT_MCS_NSS_POS 3 4014#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4015 4016/* Bit 10: (1) Use Green Field preamble */ 4017#define IWM_RATE_HT_MCS_GF_POS 10 4018#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4019 4020#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4021 4022/* 4023 * Very High-throughput (VHT) rate format for bits 7:0 4024 * 4025 * 3-0: VHT MCS (0-9) 4026 * 5-4: number of streams - 1: 4027 * 0) Single stream (SISO) 4028 * 1) Dual stream (MIMO) 4029 * 2) Triple stream (MIMO) 4030 */ 4031 4032/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4033#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4034#define IWM_RATE_VHT_MCS_NSS_POS 4 4035#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4036 4037/* 4038 * Legacy OFDM rate format for bits 7:0 4039 * 4040 * 3-0: 0xD) 6 Mbps 4041 * 0xF) 9 Mbps 4042 * 0x5) 12 Mbps 4043 * 0x7) 18 Mbps 4044 * 0x9) 24 Mbps 4045 * 0xB) 36 Mbps 4046 * 0x1) 48 Mbps 4047 * 0x3) 54 Mbps 4048 * (bits 7-4 are 0) 4049 * 4050 * Legacy CCK rate format for bits 7:0: 4051 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4052 * 4053 * 6-0: 10) 1 Mbps 4054 * 20) 2 Mbps 4055 * 55) 5.5 Mbps 4056 * 110) 11 Mbps 4057 * (bit 7 is 0) 4058 */ 4059#define IWM_RATE_LEGACY_RATE_MSK 0xff 4060 4061 4062/* 4063 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4064 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4065 */ 4066#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4067#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4068#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4069#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4070#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4071#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4072 4073/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4074#define IWM_RATE_MCS_SGI_POS 13 4075#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4076 4077/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4078#define IWM_RATE_MCS_ANT_POS 14 4079#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4080#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4081#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4082#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4083 IWM_RATE_MCS_ANT_B_MSK) 4084#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4085 IWM_RATE_MCS_ANT_C_MSK) 4086#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4087#define IWM_RATE_MCS_ANT_NUM 3 4088 4089/* Bit 17-18: (0) SS, (1) SS*2 */ 4090#define IWM_RATE_MCS_STBC_POS 17 4091#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4092 4093/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4094#define IWM_RATE_MCS_BF_POS 19 4095#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4096 4097/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4098#define IWM_RATE_MCS_ZLF_POS 20 4099#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4100 4101/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4102#define IWM_RATE_MCS_DUP_POS 24 4103#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4104 4105/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4106#define IWM_RATE_MCS_LDPC_POS 27 4107#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4108 4109 4110/* Link Quality definitions */ 4111 4112/* # entries in rate scale table to support Tx retries */ 4113#define IWM_LQ_MAX_RETRY_NUM 16 4114 4115/* Link quality command flags bit fields */ 4116 4117/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4118#define IWM_LQ_FLAG_USE_RTS_POS 0 4119#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4120 4121/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4122#define IWM_LQ_FLAG_COLOR_POS 1 4123#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4124 4125/* Bit 4-5: Tx RTS BW Signalling 4126 * (0) No RTS BW signalling 4127 * (1) Static BW signalling 4128 * (2) Dynamic BW signalling 4129 */ 4130#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4131#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4132#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4133#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4134 4135/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4136 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4137 */ 4138#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4139#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4140 4141/** 4142 * struct iwm_lq_cmd - link quality command 4143 * @sta_id: station to update 4144 * @control: not used 4145 * @flags: combination of IWM_LQ_FLAG_* 4146 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4147 * and SISO rates 4148 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4149 * Should be ANT_[ABC] 4150 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4151 * @initial_rate_index: first index from rs_table per AC category 4152 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4153 * value of 100 is one usec. Range is 100 to 8000 4154 * @agg_disable_start_th: try-count threshold for starting aggregation. 4155 * If a frame has higher try-count, it should not be selected for 4156 * starting an aggregation sequence. 4157 * @agg_frame_cnt_limit: max frame count in an aggregation. 4158 * 0: no limit 4159 * 1: no aggregation (one frame per aggregation) 4160 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4161 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4162 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4163 * @bf_params: beam forming params, currently not used 4164 */ 4165struct iwm_lq_cmd { 4166 uint8_t sta_id; 4167 uint8_t reserved1; 4168 uint16_t control; 4169 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4170 uint8_t flags; 4171 uint8_t mimo_delim; 4172 uint8_t single_stream_ant_msk; 4173 uint8_t dual_stream_ant_msk; 4174 uint8_t initial_rate_index[IWM_AC_NUM]; 4175 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4176 uint16_t agg_time_limit; 4177 uint8_t agg_disable_start_th; 4178 uint8_t agg_frame_cnt_limit; 4179 uint32_t reserved2; 4180 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4181 uint32_t bf_params; 4182}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4183 4184/* 4185 * END mvm/fw-api-rs.h 4186 */ 4187 4188/* 4189 * BEGIN mvm/fw-api-tx.h 4190 */ 4191 4192/** 4193 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4194 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4195 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4196 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4197 * Otherwise, use rate_n_flags from the TX command 4198 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4199 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4200 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4201 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4202 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4203 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4204 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4205 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4206 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4207 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4208 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4209 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4210 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4211 * Should be set for beacons and probe responses 4212 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4213 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4214 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4215 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4216 * Should be set for 26/30 length MAC headers 4217 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4218 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4219 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4220 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4221 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4222 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4223 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4224 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4225 */ 4226enum iwm_tx_flags { 4227 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4228 IWM_TX_CMD_FLG_ACK = (1 << 3), 4229 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4230 IWM_TX_CMD_FLG_BA = (1 << 5), 4231 IWM_TX_CMD_FLG_BAR = (1 << 6), 4232 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4233 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4234 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4235 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4236 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4237 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4238 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4239 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4240 IWM_TX_CMD_FLG_TSF = (1 << 16), 4241 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4242 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4243 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4244 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4245 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4246 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4247 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4248 IWM_TX_CMD_FLG_DUR = (1 << 25), 4249 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4250 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4251 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4252 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4253}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4254 4255/** 4256 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4257 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4258 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4259 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4260 */ 4261enum iwm_tx_pm_timeouts { 4262 IWM_PM_FRAME_NONE = 0, 4263 IWM_PM_FRAME_MGMT = 2, 4264 IWM_PM_FRAME_ASSOC = 3, 4265}; 4266 4267/* 4268 * TX command security control 4269 */ 4270#define IWM_TX_CMD_SEC_WEP 0x01 4271#define IWM_TX_CMD_SEC_CCM 0x02 4272#define IWM_TX_CMD_SEC_TKIP 0x03 4273#define IWM_TX_CMD_SEC_EXT 0x04 4274#define IWM_TX_CMD_SEC_MSK 0x07 4275#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4276#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4277#define IWM_TX_CMD_SEC_KEY128 0x08 4278 4279/* TODO: how does these values are OK with only 16 bit variable??? */ 4280/* 4281 * TX command next frame info 4282 * 4283 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4284 * bit 3 - immediate ACK required 4285 * bit 4 - rate is taken from STA table 4286 * bit 5 - frame belongs to BA stream 4287 * bit 6 - immediate BA response expected 4288 * bit 7 - unused 4289 * bits 8:15 - Station ID 4290 * bits 16:31 - rate 4291 */ 4292#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4293#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4294#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4295#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4296#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4297#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4298#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4299#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4300#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4301 4302/* 4303 * TX command Frame life time in us - to be written in pm_frame_timeout 4304 */ 4305#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4306#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4307#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4308#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4309 4310/* 4311 * TID for non QoS frames - to be written in tid_tspec 4312 */ 4313#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4314 4315/* 4316 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4317 */ 4318#define IWM_DEFAULT_TX_RETRY 15 4319#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4320#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4321#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4322#define IWM_LOW_RETRY_LIMIT 7 4323 4324/* TODO: complete documentation for try_cnt and btkill_cnt */ 4325/** 4326 * struct iwm_tx_cmd - TX command struct to FW 4327 * ( IWM_TX_CMD = 0x1c ) 4328 * @len: in bytes of the payload, see below for details 4329 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4330 * Used for fragmentation and bursting, but not in 11n aggregation. 4331 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4332 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4333 * cleared. Combination of IWM_RATE_MCS_* 4334 * @sta_id: index of destination station in FW station table 4335 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4336 * @initial_rate_index: index into the rate table for initial TX attempt. 4337 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4338 * @key: security key 4339 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4340 * @life_time: frame life time (usecs??) 4341 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4342 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4343 * @dram_msb_ptr: upper bits of the scratch physical address 4344 * @rts_retry_limit: max attempts for RTS 4345 * @data_retry_limit: max attempts to send the data packet 4346 * @tid_spec: TID/tspec 4347 * @pm_frame_timeout: PM TX frame timeout 4348 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4349 * specified by HCCA protocol 4350 * 4351 * The byte count (both len and next_frame_len) includes MAC header 4352 * (24/26/30/32 bytes) 4353 * + 2 bytes pad if 26/30 header size 4354 * + 8 byte IV for CCM or TKIP (not used for WEP) 4355 * + Data payload 4356 * + 8-byte MIC (not used for CCM/WEP) 4357 * It does not include post-MAC padding, i.e., 4358 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4359 * Range of len: 14-2342 bytes. 4360 * 4361 * After the struct fields the MAC header is placed, plus any padding, 4362 * and then the actial payload. 4363 */ 4364struct iwm_tx_cmd { 4365 uint16_t len; 4366 uint16_t next_frame_len; 4367 uint32_t tx_flags; 4368 struct { 4369 uint8_t try_cnt; 4370 uint8_t btkill_cnt; 4371 uint16_t reserved; 4372 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4373 uint32_t rate_n_flags; 4374 uint8_t sta_id; 4375 uint8_t sec_ctl; 4376 uint8_t initial_rate_index; 4377 uint8_t reserved2; 4378 uint8_t key[16]; 4379 uint16_t next_frame_flags; 4380 uint16_t reserved3; 4381 uint32_t life_time; 4382 uint32_t dram_lsb_ptr; 4383 uint8_t dram_msb_ptr; 4384 uint8_t rts_retry_limit; 4385 uint8_t data_retry_limit; 4386 uint8_t tid_tspec; 4387 uint16_t pm_frame_timeout; 4388 uint16_t driver_txop; 4389 uint8_t payload[0]; 4390 struct ieee80211_frame hdr[0]; 4391} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4392 4393/* 4394 * TX response related data 4395 */ 4396 4397/* 4398 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4399 * @IWM_TX_STATUS_SUCCESS: 4400 * @IWM_TX_STATUS_DIRECT_DONE: 4401 * @IWM_TX_STATUS_POSTPONE_DELAY: 4402 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4403 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4404 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4405 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4406 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4407 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4408 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4409 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4410 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4411 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4412 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4413 * @IWM_TX_STATUS_FAIL_DEST_PS: 4414 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4415 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4416 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4417 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4418 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4419 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4420 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4421 * @IWM_TX_STATUS_FAIL_FW_DROP: 4422 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4423 * STA table 4424 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4425 * @IWM_TX_MODE_MSK: 4426 * @IWM_TX_MODE_NO_BURST: 4427 * @IWM_TX_MODE_IN_BURST_SEQ: 4428 * @IWM_TX_MODE_FIRST_IN_BURST: 4429 * @IWM_TX_QUEUE_NUM_MSK: 4430 * 4431 * Valid only if frame_count =1 4432 * TODO: complete documentation 4433 */ 4434enum iwm_tx_status { 4435 IWM_TX_STATUS_MSK = 0x000000ff, 4436 IWM_TX_STATUS_SUCCESS = 0x01, 4437 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4438 /* postpone TX */ 4439 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4440 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4441 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4442 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4443 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4444 /* abort TX */ 4445 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4446 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4447 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4448 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4449 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4450 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4451 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4452 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4453 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4454 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4455 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4456 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4457 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4458 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4459 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4460 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4461 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4462 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4463 IWM_TX_MODE_MSK = 0x00000f00, 4464 IWM_TX_MODE_NO_BURST = 0x00000000, 4465 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4466 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4467 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4468 IWM_TX_NARROW_BW_MSK = 0x00060000, 4469 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4470 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4471 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4472}; 4473 4474/* 4475 * enum iwm_tx_agg_status - TX aggregation status 4476 * @IWM_AGG_TX_STATE_STATUS_MSK: 4477 * @IWM_AGG_TX_STATE_TRANSMITTED: 4478 * @IWM_AGG_TX_STATE_UNDERRUN: 4479 * @IWM_AGG_TX_STATE_BT_PRIO: 4480 * @IWM_AGG_TX_STATE_FEW_BYTES: 4481 * @IWM_AGG_TX_STATE_ABORT: 4482 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4483 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4484 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4485 * @IWM_AGG_TX_STATE_SCD_QUERY: 4486 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4487 * @IWM_AGG_TX_STATE_RESPONSE: 4488 * @IWM_AGG_TX_STATE_DUMP_TX: 4489 * @IWM_AGG_TX_STATE_DELAY_TX: 4490 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4491 * occur if tx failed for this frame when it was a member of a previous 4492 * aggregation block). If rate scaling is used, retry count indicates the 4493 * rate table entry used for all frames in the new agg. 4494 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4495 * this frame 4496 * 4497 * TODO: complete documentation 4498 */ 4499enum iwm_tx_agg_status { 4500 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4501 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4502 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4503 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4504 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4505 IWM_AGG_TX_STATE_ABORT = 0x008, 4506 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4507 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4508 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4509 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4510 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4511 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4512 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4513 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4514 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4515 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4516}; 4517 4518#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4519 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4520 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4521 4522/* 4523 * The mask below describes a status where we are absolutely sure that the MPDU 4524 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4525 * written the bytes to the TXE, but we know nothing about what the DSP did. 4526 */ 4527#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4528 IWM_AGG_TX_STATE_ABORT | \ 4529 IWM_AGG_TX_STATE_SCD_QUERY) 4530 4531/* 4532 * IWM_REPLY_TX = 0x1c (response) 4533 * 4534 * This response may be in one of two slightly different formats, indicated 4535 * by the frame_count field: 4536 * 4537 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4538 * frame. Multiple attempts, at various bit rates, may have been made for 4539 * this frame. 4540 * 4541 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4542 * frames that used block-acknowledge. All frames were transmitted at 4543 * same rate. Rate scaling may have been used if first frame in this new 4544 * agg block failed in previous agg block(s). 4545 * 4546 * Note that, for aggregation, ACK (block-ack) status is not delivered 4547 * here; block-ack has not been received by the time the device records 4548 * this status. 4549 * This status relates to reasons the tx might have been blocked or aborted 4550 * within the device, rather than whether it was received successfully by 4551 * the destination station. 4552 */ 4553 4554/** 4555 * struct iwm_agg_tx_status - per packet TX aggregation status 4556 * @status: enum iwm_tx_agg_status 4557 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4558 */ 4559struct iwm_agg_tx_status { 4560 uint16_t status; 4561 uint16_t sequence; 4562} __packed; 4563 4564/* 4565 * definitions for initial rate index field 4566 * bits [3:0] initial rate index 4567 * bits [6:4] rate table color, used for the initial rate 4568 * bit-7 invalid rate indication 4569 */ 4570#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4571#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4572#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4573 4574#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4575#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4576 4577/** 4578 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4579 * ( IWM_REPLY_TX = 0x1c ) 4580 * @frame_count: 1 no aggregation, >1 aggregation 4581 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4582 * @failure_rts: num of failures due to unsuccessful RTS 4583 * @failure_frame: num failures due to no ACK (unused for agg) 4584 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4585 * Tx of all the batch. IWM_RATE_MCS_* 4586 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4587 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4588 * in usec. 4589 * @pa_status: tx power info 4590 * @pa_integ_res_a: tx power info 4591 * @pa_integ_res_b: tx power info 4592 * @pa_integ_res_c: tx power info 4593 * @measurement_req_id: tx power info 4594 * @tfd_info: TFD information set by the FH 4595 * @seq_ctl: sequence control from the Tx cmd 4596 * @byte_cnt: byte count from the Tx cmd 4597 * @tlc_info: TLC rate info 4598 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4599 * @frame_ctrl: frame control 4600 * @status: for non-agg: frame status IWM_TX_STATUS_* 4601 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4602 * follow this one, up to frame_count. 4603 * 4604 * After the array of statuses comes the SSN of the SCD. Look at 4605 * %iwm_mvm_get_scd_ssn for more details. 4606 */ 4607struct iwm_mvm_tx_resp { 4608 uint8_t frame_count; 4609 uint8_t bt_kill_count; 4610 uint8_t failure_rts; 4611 uint8_t failure_frame; 4612 uint32_t initial_rate; 4613 uint16_t wireless_media_time; 4614 4615 uint8_t pa_status; 4616 uint8_t pa_integ_res_a[3]; 4617 uint8_t pa_integ_res_b[3]; 4618 uint8_t pa_integ_res_c[3]; 4619 uint16_t measurement_req_id; 4620 uint16_t reserved; 4621 4622 uint32_t tfd_info; 4623 uint16_t seq_ctl; 4624 uint16_t byte_cnt; 4625 uint8_t tlc_info; 4626 uint8_t ra_tid; 4627 uint16_t frame_ctrl; 4628 4629 struct iwm_agg_tx_status status; 4630} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4631 4632/** 4633 * struct iwm_mvm_ba_notif - notifies about reception of BA 4634 * ( IWM_BA_NOTIF = 0xc5 ) 4635 * @sta_addr_lo32: lower 32 bits of the MAC address 4636 * @sta_addr_hi16: upper 16 bits of the MAC address 4637 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4638 * @tid: tid of the session 4639 * @seq_ctl: 4640 * @bitmap: the bitmap of the BA notification as seen in the air 4641 * @scd_flow: the tx queue this BA relates to 4642 * @scd_ssn: the index of the last contiguously sent packet 4643 * @txed: number of Txed frames in this batch 4644 * @txed_2_done: number of Acked frames in this batch 4645 */ 4646struct iwm_mvm_ba_notif { 4647 uint32_t sta_addr_lo32; 4648 uint16_t sta_addr_hi16; 4649 uint16_t reserved; 4650 4651 uint8_t sta_id; 4652 uint8_t tid; 4653 uint16_t seq_ctl; 4654 uint64_t bitmap; 4655 uint16_t scd_flow; 4656 uint16_t scd_ssn; 4657 uint8_t txed; 4658 uint8_t txed_2_done; 4659 uint16_t reserved1; 4660} __packed; 4661 4662/* 4663 * struct iwm_mac_beacon_cmd - beacon template command 4664 * @tx: the tx commands associated with the beacon frame 4665 * @template_id: currently equal to the mac context id of the coresponding 4666 * mac. 4667 * @tim_idx: the offset of the tim IE in the beacon 4668 * @tim_size: the length of the tim IE 4669 * @frame: the template of the beacon frame 4670 */ 4671struct iwm_mac_beacon_cmd { 4672 struct iwm_tx_cmd tx; 4673 uint32_t template_id; 4674 uint32_t tim_idx; 4675 uint32_t tim_size; 4676 struct ieee80211_frame frame[0]; 4677} __packed; 4678 4679struct iwm_beacon_notif { 4680 struct iwm_mvm_tx_resp beacon_notify_hdr; 4681 uint64_t tsf; 4682 uint32_t ibss_mgr_status; 4683} __packed; 4684 4685/** 4686 * enum iwm_dump_control - dump (flush) control flags 4687 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4688 * and the TFD queues are empty. 4689 */ 4690enum iwm_dump_control { 4691 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4692}; 4693 4694/** 4695 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4696 * @queues_ctl: bitmap of queues to flush 4697 * @flush_ctl: control flags 4698 * @reserved: reserved 4699 */ 4700struct iwm_tx_path_flush_cmd { 4701 uint32_t queues_ctl; 4702 uint16_t flush_ctl; 4703 uint16_t reserved; 4704} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4705 4706/** 4707 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4708 * @tx_resp: the Tx response from the fw (agg or non-agg) 4709 * 4710 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4711 * it can't know that everything will go well until the end of the AMPDU, it 4712 * can't know in advance the number of MPDUs that will be sent in the current 4713 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4714 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4715 * of the batch. This is why the SSN of the SCD is written at the end of the 4716 * whole struct at a variable offset. This function knows how to cope with the 4717 * variable offset and returns the SSN of the SCD. 4718 */ 4719static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4720{ 4721 return le32_to_cpup((uint32_t *)&tx_resp->status + 4722 tx_resp->frame_count) & 0xfff; 4723} 4724 4725/* 4726 * END mvm/fw-api-tx.h 4727 */ 4728 4729/* 4730 * BEGIN mvm/fw-api-scan.h 4731 */ 4732 4733/** 4734 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4735 * @token: 4736 * @sta_id: station id 4737 * @tid: 4738 * @scd_queue: scheduler queue to confiug 4739 * @enable: 1 queue enable, 0 queue disable 4740 * @aggregate: 1 aggregated queue, 0 otherwise 4741 * @tx_fifo: %enum iwm_mvm_tx_fifo 4742 * @window: BA window size 4743 * @ssn: SSN for the BA agreement 4744 */ 4745struct iwm_scd_txq_cfg_cmd { 4746 uint8_t token; 4747 uint8_t sta_id; 4748 uint8_t tid; 4749 uint8_t scd_queue; 4750 uint8_t enable; 4751 uint8_t aggregate; 4752 uint8_t tx_fifo; 4753 uint8_t window; 4754 uint16_t ssn; 4755 uint16_t reserved; 4756} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4757 4758/** 4759 * struct iwm_scd_txq_cfg_rsp 4760 * @token: taken from the command 4761 * @sta_id: station id from the command 4762 * @tid: tid from the command 4763 * @scd_queue: scd_queue from the command 4764 */ 4765struct iwm_scd_txq_cfg_rsp { 4766 uint8_t token; 4767 uint8_t sta_id; 4768 uint8_t tid; 4769 uint8_t scd_queue; 4770} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4771 4772 4773/* Scan Commands, Responses, Notifications */ 4774 4775/* Masks for iwm_scan_channel.type flags */ 4776#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4777#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4778 4779/* Max number of IEs for direct SSID scans in a command */ 4780#define IWM_PROBE_OPTION_MAX 20 4781 4782/** 4783 * struct iwm_ssid_ie - directed scan network information element 4784 * 4785 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4786 * selected by "type" bit field in struct iwm_scan_channel; 4787 * each channel may select different ssids from among the 20 entries. 4788 * SSID IEs get transmitted in reverse order of entry. 4789 */ 4790struct iwm_ssid_ie { 4791 uint8_t id; 4792 uint8_t len; 4793 uint8_t ssid[IEEE80211_NWID_LEN]; 4794} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4795 4796/* scan offload */ 4797#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4798#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4799#define IWM_SCAN_MAX_PROFILES 11 4800#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4801 4802/* Default watchdog (in MS) for scheduled scan iteration */ 4803#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4804 4805#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4806#define IWM_CAN_ABORT_STATUS 1 4807 4808#define IWM_FULL_SCAN_MULTIPLIER 5 4809#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4810#define IWM_MAX_SCHED_SCAN_PLANS 2 4811 4812/** 4813 * iwm_scan_schedule_lmac - schedule of scan offload 4814 * @delay: delay between iterations, in seconds. 4815 * @iterations: num of scan iterations 4816 * @full_scan_mul: number of partial scans before each full scan 4817 */ 4818struct iwm_scan_schedule_lmac { 4819 uint16_t delay; 4820 uint8_t iterations; 4821 uint8_t full_scan_mul; 4822} __packed; /* SCAN_SCHEDULE_API_S */ 4823 4824/** 4825 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4826 * @tx_flags: combination of TX_CMD_FLG_* 4827 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4828 * cleared. Combination of RATE_MCS_* 4829 * @sta_id: index of destination station in FW station table 4830 * @reserved: for alignment and future use 4831 */ 4832struct iwm_scan_req_tx_cmd { 4833 uint32_t tx_flags; 4834 uint32_t rate_n_flags; 4835 uint8_t sta_id; 4836 uint8_t reserved[3]; 4837} __packed; 4838 4839enum iwm_scan_channel_flags_lmac { 4840 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4841 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4842}; 4843 4844/** 4845 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4846 * @flags: bits 1-20: directed scan to i'th ssid 4847 * other bits &enum iwm_scan_channel_flags_lmac 4848 * @channel_number: channel number 1-13 etc 4849 * @iter_count: scan iteration on this channel 4850 * @iter_interval: interval in seconds between iterations on one channel 4851 */ 4852struct iwm_scan_channel_cfg_lmac { 4853 uint32_t flags; 4854 uint16_t channel_num; 4855 uint16_t iter_count; 4856 uint32_t iter_interval; 4857} __packed; 4858 4859/* 4860 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4861 * @offset: offset in the data block 4862 * @len: length of the segment 4863 */ 4864struct iwm_scan_probe_segment { 4865 uint16_t offset; 4866 uint16_t len; 4867} __packed; 4868 4869/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4870 * @mac_header: first (and common) part of the probe 4871 * @band_data: band specific data 4872 * @common_data: last (and common) part of the probe 4873 * @buf: raw data block 4874 */ 4875struct iwm_scan_probe_req { 4876 struct iwm_scan_probe_segment mac_header; 4877 struct iwm_scan_probe_segment band_data[2]; 4878 struct iwm_scan_probe_segment common_data; 4879 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4880} __packed; 4881 4882enum iwm_scan_channel_flags { 4883 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4884 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4885 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4886}; 4887 4888/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4889 * @flags: enum iwm_scan_channel_flags 4890 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4891 * involved. 4892 * 1 - EBS is disabled. 4893 * 2 - every second scan will be full scan(and so on). 4894 */ 4895struct iwm_scan_channel_opt { 4896 uint16_t flags; 4897 uint16_t non_ebs_ratio; 4898} __packed; 4899 4900/** 4901 * iwm_mvm_lmac_scan_flags 4902 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4903 * without filtering. 4904 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4905 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4906 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4907 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4908 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4909 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4910 * and DS parameter set IEs into probe requests. 4911 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4912 * 1, 6 and 11. 4913 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4914 */ 4915enum iwm_mvm_lmac_scan_flags { 4916 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4917 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4918 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4919 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4920 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4921 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4922 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4923 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4924 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4925}; 4926 4927enum iwm_scan_priority { 4928 IWM_SCAN_PRIORITY_LOW, 4929 IWM_SCAN_PRIORITY_MEDIUM, 4930 IWM_SCAN_PRIORITY_HIGH, 4931}; 4932 4933/** 4934 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4935 * @reserved1: for alignment and future use 4936 * @channel_num: num of channels to scan 4937 * @active-dwell: dwell time for active channels 4938 * @passive-dwell: dwell time for passive channels 4939 * @fragmented-dwell: dwell time for fragmented passive scan 4940 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4941 * @reserved2: for alignment and future use 4942 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4943 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4944 * @max_out_time: max time (in TU) to be out of associated channel 4945 * @suspend_time: pause scan this long (TUs) when returning to service channel 4946 * @flags: RXON flags 4947 * @filter_flags: RXON filter 4948 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4949 * @direct_scan: list of SSIDs for directed active scan 4950 * @scan_prio: enum iwm_scan_priority 4951 * @iter_num: number of scan iterations 4952 * @delay: delay in seconds before first iteration 4953 * @schedule: two scheduling plans. The first one is finite, the second one can 4954 * be infinite. 4955 * @channel_opt: channel optimization options, for full and partial scan 4956 * @data: channel configuration and probe request packet. 4957 */ 4958struct iwm_scan_req_lmac { 4959 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4960 uint32_t reserved1; 4961 uint8_t n_channels; 4962 uint8_t active_dwell; 4963 uint8_t passive_dwell; 4964 uint8_t fragmented_dwell; 4965 uint8_t extended_dwell; 4966 uint8_t reserved2; 4967 uint16_t rx_chain_select; 4968 uint32_t scan_flags; 4969 uint32_t max_out_time; 4970 uint32_t suspend_time; 4971 /* RX_ON_FLAGS_API_S_VER_1 */ 4972 uint32_t flags; 4973 uint32_t filter_flags; 4974 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4975 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4976 uint32_t scan_prio; 4977 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4978 uint32_t iter_num; 4979 uint32_t delay; 4980 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4981 struct iwm_scan_channel_opt channel_opt[2]; 4982 uint8_t data[]; 4983} __packed; 4984 4985/** 4986 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4987 * @last_schedule_line: last schedule line executed (fast or regular) 4988 * @last_schedule_iteration: last scan iteration executed before scan abort 4989 * @status: enum iwm_scan_offload_complete_status 4990 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4991 * @time_after_last_iter; time in seconds elapsed after last iteration 4992 */ 4993struct iwm_periodic_scan_complete { 4994 uint8_t last_schedule_line; 4995 uint8_t last_schedule_iteration; 4996 uint8_t status; 4997 uint8_t ebs_status; 4998 uint32_t time_after_last_iter; 4999 uint32_t reserved; 5000} __packed; 5001 5002/* How many statistics are gathered for each channel */ 5003#define IWM_SCAN_RESULTS_STATISTICS 1 5004 5005/** 5006 * enum iwm_scan_complete_status - status codes for scan complete notifications 5007 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5008 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5009 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5010 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5011 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5012 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5013 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5014 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5015 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5016 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5017 * (not an error!) 5018 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5019 * asked for 5020 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5021*/ 5022enum iwm_scan_complete_status { 5023 IWM_SCAN_COMP_STATUS_OK = 0x1, 5024 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5025 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5026 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5027 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5028 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5029 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5030 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5031 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5032 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5033 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5034 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5035}; 5036 5037/** 5038 * struct iwm_scan_results_notif - scan results for one channel 5039 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5040 * @channel: which channel the results are from 5041 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5042 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5043 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5044 * @duration: duration spent in channel, in usecs 5045 * @statistics: statistics gathered for this channel 5046 */ 5047struct iwm_scan_results_notif { 5048 uint8_t channel; 5049 uint8_t band; 5050 uint8_t probe_status; 5051 uint8_t num_probe_not_sent; 5052 uint32_t duration; 5053 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5054} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5055 5056enum iwm_scan_framework_client { 5057 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5058 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5059 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5060}; 5061 5062/** 5063 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5064 * @ssid: MAC address to filter out 5065 * @reported_rssi: AP rssi reported to the host 5066 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5067 */ 5068struct iwm_scan_offload_blacklist { 5069 uint8_t ssid[IEEE80211_ADDR_LEN]; 5070 uint8_t reported_rssi; 5071 uint8_t client_bitmap; 5072} __packed; 5073 5074enum iwm_scan_offload_network_type { 5075 IWM_NETWORK_TYPE_BSS = 1, 5076 IWM_NETWORK_TYPE_IBSS = 2, 5077 IWM_NETWORK_TYPE_ANY = 3, 5078}; 5079 5080enum iwm_scan_offload_band_selection { 5081 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5082 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5083 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5084}; 5085 5086/** 5087 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5088 * @ssid_index: index to ssid list in fixed part 5089 * @unicast_cipher: encryption olgorithm to match - bitmap 5090 * @aut_alg: authentication olgorithm to match - bitmap 5091 * @network_type: enum iwm_scan_offload_network_type 5092 * @band_selection: enum iwm_scan_offload_band_selection 5093 * @client_bitmap: clients waiting for match - enum scan_framework_client 5094 */ 5095struct iwm_scan_offload_profile { 5096 uint8_t ssid_index; 5097 uint8_t unicast_cipher; 5098 uint8_t auth_alg; 5099 uint8_t network_type; 5100 uint8_t band_selection; 5101 uint8_t client_bitmap; 5102 uint8_t reserved[2]; 5103} __packed; 5104 5105/** 5106 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5107 * @blaclist: AP list to filter off from scan results 5108 * @profiles: profiles to search for match 5109 * @blacklist_len: length of blacklist 5110 * @num_profiles: num of profiles in the list 5111 * @match_notify: clients waiting for match found notification 5112 * @pass_match: clients waiting for the results 5113 * @active_clients: active clients bitmap - enum scan_framework_client 5114 * @any_beacon_notify: clients waiting for match notification without match 5115 */ 5116struct iwm_scan_offload_profile_cfg { 5117 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5118 uint8_t blacklist_len; 5119 uint8_t num_profiles; 5120 uint8_t match_notify; 5121 uint8_t pass_match; 5122 uint8_t active_clients; 5123 uint8_t any_beacon_notify; 5124 uint8_t reserved[2]; 5125} __packed; 5126 5127enum iwm_scan_offload_complete_status { 5128 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5129 IWM_SCAN_OFFLOAD_ABORTED = 2, 5130}; 5131 5132/** 5133 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5134 * SCAN_COMPLETE_NTF_API_S_VER_3 5135 * @scanned_channels: number of channels scanned (and number of valid results) 5136 * @status: one of SCAN_COMP_STATUS_* 5137 * @bt_status: BT on/off status 5138 * @last_channel: last channel that was scanned 5139 * @tsf_low: TSF timer (lower half) in usecs 5140 * @tsf_high: TSF timer (higher half) in usecs 5141 * @results: an array of scan results, only "scanned_channels" of them are valid 5142 */ 5143struct iwm_lmac_scan_complete_notif { 5144 uint8_t scanned_channels; 5145 uint8_t status; 5146 uint8_t bt_status; 5147 uint8_t last_channel; 5148 uint32_t tsf_low; 5149 uint32_t tsf_high; 5150 struct iwm_scan_results_notif results[]; 5151} __packed; 5152 5153 5154/* 5155 * END mvm/fw-api-scan.h 5156 */ 5157 5158/* 5159 * BEGIN mvm/fw-api-sta.h 5160 */ 5161 5162/* UMAC Scan API */ 5163 5164/* The maximum of either of these cannot exceed 8, because we use an 5165 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5166 */ 5167#define IWM_MVM_MAX_UMAC_SCANS 8 5168#define IWM_MVM_MAX_LMAC_SCANS 1 5169 5170enum iwm_scan_config_flags { 5171 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5172 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5173 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5174 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5175 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5176 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5177 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5178 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5179 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5180 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5181 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5182 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5183 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5184 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5185 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5186 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5187 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5188 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5189 5190 /* Bits 26-31 are for num of channels in channel_array */ 5191#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5192}; 5193 5194enum iwm_scan_config_rates { 5195 /* OFDM basic rates */ 5196 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5197 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5198 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5199 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5200 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5201 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5202 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5203 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5204 /* CCK basic rates */ 5205 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5206 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5207 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5208 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5209 5210 /* Bits 16-27 are for supported rates */ 5211#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5212}; 5213 5214enum iwm_channel_flags { 5215 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5216 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5217 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5218 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5219}; 5220 5221/** 5222 * struct iwm_scan_config 5223 * @flags: enum scan_config_flags 5224 * @tx_chains: valid_tx antenna - ANT_* definitions 5225 * @rx_chains: valid_rx antenna - ANT_* definitions 5226 * @legacy_rates: default legacy rates - enum scan_config_rates 5227 * @out_of_channel_time: default max out of serving channel time 5228 * @suspend_time: default max suspend time 5229 * @dwell_active: default dwell time for active scan 5230 * @dwell_passive: default dwell time for passive scan 5231 * @dwell_fragmented: default dwell time for fragmented scan 5232 * @dwell_extended: default dwell time for channels 1, 6 and 11 5233 * @mac_addr: default mac address to be used in probes 5234 * @bcast_sta_id: the index of the station in the fw 5235 * @channel_flags: default channel flags - enum iwm_channel_flags 5236 * scan_config_channel_flag 5237 * @channel_array: default supported channels 5238 */ 5239struct iwm_scan_config { 5240 uint32_t flags; 5241 uint32_t tx_chains; 5242 uint32_t rx_chains; 5243 uint32_t legacy_rates; 5244 uint32_t out_of_channel_time; 5245 uint32_t suspend_time; 5246 uint8_t dwell_active; 5247 uint8_t dwell_passive; 5248 uint8_t dwell_fragmented; 5249 uint8_t dwell_extended; 5250 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5251 uint8_t bcast_sta_id; 5252 uint8_t channel_flags; 5253 uint8_t channel_array[]; 5254} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5255 5256/** 5257 * iwm_umac_scan_flags 5258 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5259 * can be preempted by other scan requests with higher priority. 5260 * The low priority scan will be resumed when the higher proirity scan is 5261 * completed. 5262 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5263 * when scan starts. 5264 */ 5265enum iwm_umac_scan_flags { 5266 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5267 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5268}; 5269 5270enum iwm_umac_scan_uid_offsets { 5271 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5272 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5273}; 5274 5275enum iwm_umac_scan_general_flags { 5276 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5277 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5278 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5279 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5280 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5281 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5282 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5283 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5284 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5285 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5286 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5287}; 5288 5289/** 5290 * struct iwm_scan_channel_cfg_umac 5291 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5292 * @channel_num: channel number 1-13 etc. 5293 * @iter_count: repetition count for the channel. 5294 * @iter_interval: interval between two scan iterations on one channel. 5295 */ 5296struct iwm_scan_channel_cfg_umac { 5297 uint32_t flags; 5298#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5299 5300 uint8_t channel_num; 5301 uint8_t iter_count; 5302 uint16_t iter_interval; 5303} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5304 5305/** 5306 * struct iwm_scan_umac_schedule 5307 * @interval: interval in seconds between scan iterations 5308 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5309 * @reserved: for alignment and future use 5310 */ 5311struct iwm_scan_umac_schedule { 5312 uint16_t interval; 5313 uint8_t iter_count; 5314 uint8_t reserved; 5315} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5316 5317/** 5318 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5319 * parameters following channels configuration array. 5320 * @schedule: two scheduling plans. 5321 * @delay: delay in TUs before starting the first scan iteration 5322 * @reserved: for future use and alignment 5323 * @preq: probe request with IEs blocks 5324 * @direct_scan: list of SSIDs for directed active scan 5325 */ 5326struct iwm_scan_req_umac_tail { 5327 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5328 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5329 uint16_t delay; 5330 uint16_t reserved; 5331 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5332 struct iwm_scan_probe_req preq; 5333 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5334} __packed; 5335 5336/** 5337 * struct iwm_scan_req_umac 5338 * @flags: &enum iwm_umac_scan_flags 5339 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5340 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5341 * @general_flags: &enum iwm_umac_scan_general_flags 5342 * @extended_dwell: dwell time for channels 1, 6 and 11 5343 * @active_dwell: dwell time for active scan 5344 * @passive_dwell: dwell time for passive scan 5345 * @fragmented_dwell: dwell time for fragmented passive scan 5346 * @max_out_time: max out of serving channel time 5347 * @suspend_time: max suspend time 5348 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5349 * @channel_flags: &enum iwm_scan_channel_flags 5350 * @n_channels: num of channels in scan request 5351 * @reserved: for future use and alignment 5352 * @data: &struct iwm_scan_channel_cfg_umac and 5353 * &struct iwm_scan_req_umac_tail 5354 */ 5355struct iwm_scan_req_umac { 5356 uint32_t flags; 5357 uint32_t uid; 5358 uint32_t ooc_priority; 5359 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5360 uint32_t general_flags; 5361 uint8_t extended_dwell; 5362 uint8_t active_dwell; 5363 uint8_t passive_dwell; 5364 uint8_t fragmented_dwell; 5365 uint32_t max_out_time; 5366 uint32_t suspend_time; 5367 uint32_t scan_priority; 5368 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5369 uint8_t channel_flags; 5370 uint8_t n_channels; 5371 uint16_t reserved; 5372 uint8_t data[]; 5373} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5374 5375/** 5376 * struct iwm_umac_scan_abort 5377 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5378 * @flags: reserved 5379 */ 5380struct iwm_umac_scan_abort { 5381 uint32_t uid; 5382 uint32_t flags; 5383} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5384 5385/** 5386 * struct iwm_umac_scan_complete 5387 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5388 * @last_schedule: last scheduling line 5389 * @last_iter: last scan iteration number 5390 * @scan status: &enum iwm_scan_offload_complete_status 5391 * @ebs_status: &enum iwm_scan_ebs_status 5392 * @time_from_last_iter: time elapsed from last iteration 5393 * @reserved: for future use 5394 */ 5395struct iwm_umac_scan_complete { 5396 uint32_t uid; 5397 uint8_t last_schedule; 5398 uint8_t last_iter; 5399 uint8_t status; 5400 uint8_t ebs_status; 5401 uint32_t time_from_last_iter; 5402 uint32_t reserved; 5403} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5404 5405#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5406/** 5407 * struct iwm_scan_offload_profile_match - match information 5408 * @bssid: matched bssid 5409 * @channel: channel where the match occurred 5410 * @energy: 5411 * @matching_feature: 5412 * @matching_channels: bitmap of channels that matched, referencing 5413 * the channels passed in tue scan offload request 5414 */ 5415struct iwm_scan_offload_profile_match { 5416 uint8_t bssid[IEEE80211_ADDR_LEN]; 5417 uint16_t reserved; 5418 uint8_t channel; 5419 uint8_t energy; 5420 uint8_t matching_feature; 5421 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5422} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5423 5424/** 5425 * struct iwm_scan_offload_profiles_query - match results query response 5426 * @matched_profiles: bitmap of matched profiles, referencing the 5427 * matches passed in the scan offload request 5428 * @last_scan_age: age of the last offloaded scan 5429 * @n_scans_done: number of offloaded scans done 5430 * @gp2_d0u: GP2 when D0U occurred 5431 * @gp2_invoked: GP2 when scan offload was invoked 5432 * @resume_while_scanning: not used 5433 * @self_recovery: obsolete 5434 * @reserved: reserved 5435 * @matches: array of match information, one for each match 5436 */ 5437struct iwm_scan_offload_profiles_query { 5438 uint32_t matched_profiles; 5439 uint32_t last_scan_age; 5440 uint32_t n_scans_done; 5441 uint32_t gp2_d0u; 5442 uint32_t gp2_invoked; 5443 uint8_t resume_while_scanning; 5444 uint8_t self_recovery; 5445 uint16_t reserved; 5446 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5447} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5448 5449/** 5450 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5451 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5452 * @scanned_channels: number of channels scanned and number of valid elements in 5453 * results array 5454 * @status: one of SCAN_COMP_STATUS_* 5455 * @bt_status: BT on/off status 5456 * @last_channel: last channel that was scanned 5457 * @tsf_low: TSF timer (lower half) in usecs 5458 * @tsf_high: TSF timer (higher half) in usecs 5459 * @results: array of scan results, only "scanned_channels" of them are valid 5460 */ 5461struct iwm_umac_scan_iter_complete_notif { 5462 uint32_t uid; 5463 uint8_t scanned_channels; 5464 uint8_t status; 5465 uint8_t bt_status; 5466 uint8_t last_channel; 5467 uint32_t tsf_low; 5468 uint32_t tsf_high; 5469 struct iwm_scan_results_notif results[]; 5470} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5471 5472/* Please keep this enum *SORTED* by hex value. 5473 * Needed for binary search, otherwise a warning will be triggered. 5474 */ 5475enum iwm_scan_subcmd_ids { 5476 IWM_GSCAN_START_CMD = 0x0, 5477 IWM_GSCAN_STOP_CMD = 0x1, 5478 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5479 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5480 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5481 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5482 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5483 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5484 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5485}; 5486 5487/* STA API */ 5488 5489/** 5490 * enum iwm_sta_flags - flags for the ADD_STA host command 5491 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5492 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5493 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5494 * @IWM_STA_FLG_PS: set if STA is in Power Save 5495 * @IWM_STA_FLG_INVALID: set if STA is invalid 5496 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5497 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5498 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5499 * @IWM_STA_FLG_PAN: STA is for PAN interface 5500 * @IWM_STA_FLG_CLASS_AUTH: 5501 * @IWM_STA_FLG_CLASS_ASSOC: 5502 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5503 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5504 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5505 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5506 * initialised by driver and can be updated by fw upon reception of 5507 * action frames that can change the channel width. When cleared the fw 5508 * will send all the frames in 20MHz even when FAT channel is requested. 5509 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5510 * driver and can be updated by fw upon reception of action frames. 5511 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5512 */ 5513enum iwm_sta_flags { 5514 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5515 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5516 5517 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5518 5519 IWM_STA_FLG_PS = (1 << 8), 5520 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5521 IWM_STA_FLG_PAN = (1 << 13), 5522 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5523 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5524 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5525 5526 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5527 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5528 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5529 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5530 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5531 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5532 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5533 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5534 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5535 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5536 5537 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5538 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5539 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5540 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5541 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5542 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5543 5544 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5545 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5546 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5547 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5548 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5549 5550 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5551 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5552 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5553 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5554}; 5555 5556/** 5557 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5558 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5559 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5560 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5561 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5562 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5563 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5564 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5565 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5566 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5567 * station info array (1 - n 1X mode) 5568 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5569 * @IWM_STA_KEY_NOT_VALID: key is invalid 5570 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5571 * @IWM_STA_KEY_MULTICAST: set for multical key 5572 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5573 */ 5574enum iwm_sta_key_flag { 5575 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5576 IWM_STA_KEY_FLG_WEP = (1 << 0), 5577 IWM_STA_KEY_FLG_CCM = (2 << 0), 5578 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5579 IWM_STA_KEY_FLG_EXT = (4 << 0), 5580 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5581 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5582 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5583 5584 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5585 IWM_STA_KEY_FLG_KEYID_POS = 8, 5586 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5587 IWM_STA_KEY_NOT_VALID = (1 << 11), 5588 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5589 IWM_STA_KEY_MULTICAST = (1 << 14), 5590 IWM_STA_KEY_MFP = (1 << 15), 5591}; 5592 5593/** 5594 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5595 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5596 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5597 * @IWM_STA_MODIFY_TX_RATE: unused 5598 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5599 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5600 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5601 * @IWM_STA_MODIFY_PROT_TH: 5602 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5603 */ 5604enum iwm_sta_modify_flag { 5605 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5606 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5607 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5608 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5609 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5610 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5611 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5612 IWM_STA_MODIFY_QUEUES = (1 << 7), 5613}; 5614 5615#define IWM_STA_MODE_MODIFY 1 5616 5617/** 5618 * enum iwm_sta_sleep_flag - type of sleep of the station 5619 * @IWM_STA_SLEEP_STATE_AWAKE: 5620 * @IWM_STA_SLEEP_STATE_PS_POLL: 5621 * @IWM_STA_SLEEP_STATE_UAPSD: 5622 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5623 * (last) released frame 5624 */ 5625enum iwm_sta_sleep_flag { 5626 IWM_STA_SLEEP_STATE_AWAKE = 0, 5627 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5628 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5629 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5630}; 5631 5632/* STA ID and color bits definitions */ 5633#define IWM_STA_ID_SEED (0x0f) 5634#define IWM_STA_ID_POS (0) 5635#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5636 5637#define IWM_STA_COLOR_SEED (0x7) 5638#define IWM_STA_COLOR_POS (4) 5639#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5640 5641#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5642 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5643#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5644 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5645 5646#define IWM_STA_KEY_MAX_NUM (16) 5647#define IWM_STA_KEY_IDX_INVALID (0xff) 5648#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5649#define IWM_MAX_GLOBAL_KEYS (4) 5650#define IWM_STA_KEY_LEN_WEP40 (5) 5651#define IWM_STA_KEY_LEN_WEP104 (13) 5652 5653/** 5654 * struct iwm_mvm_keyinfo - key information 5655 * @key_flags: type %iwm_sta_key_flag 5656 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5657 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5658 * @key_offset: key offset in the fw's key table 5659 * @key: 16-byte unicast decryption key 5660 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5661 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5662 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5663 */ 5664struct iwm_mvm_keyinfo { 5665 uint16_t key_flags; 5666 uint8_t tkip_rx_tsc_byte2; 5667 uint8_t reserved1; 5668 uint16_t tkip_rx_ttak[5]; 5669 uint8_t key_offset; 5670 uint8_t reserved2; 5671 uint8_t key[16]; 5672 uint64_t tx_secur_seq_cnt; 5673 uint64_t hw_tkip_mic_rx_key; 5674 uint64_t hw_tkip_mic_tx_key; 5675} __packed; 5676 5677#define IWM_ADD_STA_STATUS_MASK 0xFF 5678#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5679#define IWM_ADD_STA_BAID_MASK 0x7F00 5680#define IWM_ADD_STA_BAID_SHIFT 8 5681 5682/** 5683 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5684 * ( REPLY_ADD_STA = 0x18 ) 5685 * @add_modify: 1: modify existing, 0: add new station 5686 * @awake_acs: 5687 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5688 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5689 * @mac_id_n_color: the Mac context this station belongs to 5690 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5691 * @sta_id: index of station in uCode's station table 5692 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5693 * alone. 1 - modify, 0 - don't change. 5694 * @station_flags: look at %iwm_sta_flags 5695 * @station_flags_msk: what of %station_flags have changed 5696 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5697 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5698 * add_immediate_ba_ssn. 5699 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5700 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5701 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5702 * add_immediate_ba_tid. 5703 * @sleep_tx_count: number of packets to transmit to station even though it is 5704 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5705 * keeps track of STA sleep state. 5706 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5707 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5708 * mac-addr. 5709 * @beamform_flags: beam forming controls 5710 * @tfd_queue_msk: tfd queues used by this station 5711 * 5712 * The device contains an internal table of per-station information, with info 5713 * on security keys, aggregation parameters, and Tx rates for initial Tx 5714 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5715 * 5716 * ADD_STA sets up the table entry for one station, either creating a new 5717 * entry, or modifying a pre-existing one. 5718 */ 5719struct iwm_mvm_add_sta_cmd_v7 { 5720 uint8_t add_modify; 5721 uint8_t awake_acs; 5722 uint16_t tid_disable_tx; 5723 uint32_t mac_id_n_color; 5724 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5725 uint16_t reserved2; 5726 uint8_t sta_id; 5727 uint8_t modify_mask; 5728 uint16_t reserved3; 5729 uint32_t station_flags; 5730 uint32_t station_flags_msk; 5731 uint8_t add_immediate_ba_tid; 5732 uint8_t remove_immediate_ba_tid; 5733 uint16_t add_immediate_ba_ssn; 5734 uint16_t sleep_tx_count; 5735 uint16_t sleep_state_flags; 5736 uint16_t assoc_id; 5737 uint16_t beamform_flags; 5738 uint32_t tfd_queue_msk; 5739} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5740 5741/** 5742 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5743 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5744 * @sta_id: index of station in uCode's station table 5745 * @key_offset: key offset in key storage 5746 * @key_flags: type %iwm_sta_key_flag 5747 * @key: key material data 5748 * @key2: key material data 5749 * @rx_secur_seq_cnt: RX security sequence counter for the key 5750 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5751 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5752 */ 5753struct iwm_mvm_add_sta_key_cmd { 5754 uint8_t sta_id; 5755 uint8_t key_offset; 5756 uint16_t key_flags; 5757 uint8_t key[16]; 5758 uint8_t key2[16]; 5759 uint8_t rx_secur_seq_cnt[16]; 5760 uint8_t tkip_rx_tsc_byte2; 5761 uint8_t reserved; 5762 uint16_t tkip_rx_ttak[5]; 5763} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5764 5765/** 5766 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5767 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5768 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5769 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5770 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5771 * that doesn't exist. 5772 */ 5773enum iwm_mvm_add_sta_rsp_status { 5774 IWM_ADD_STA_SUCCESS = 0x1, 5775 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5776 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5777 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5778}; 5779 5780/** 5781 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5782 * ( IWM_REMOVE_STA = 0x19 ) 5783 * @sta_id: the station id of the station to be removed 5784 */ 5785struct iwm_mvm_rm_sta_cmd { 5786 uint8_t sta_id; 5787 uint8_t reserved[3]; 5788} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5789 5790/** 5791 * struct iwm_mvm_mgmt_mcast_key_cmd 5792 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5793 * @ctrl_flags: %iwm_sta_key_flag 5794 * @IGTK: 5795 * @K1: IGTK master key 5796 * @K2: IGTK sub key 5797 * @sta_id: station ID that support IGTK 5798 * @key_id: 5799 * @receive_seq_cnt: initial RSC/PN needed for replay check 5800 */ 5801struct iwm_mvm_mgmt_mcast_key_cmd { 5802 uint32_t ctrl_flags; 5803 uint8_t IGTK[16]; 5804 uint8_t K1[16]; 5805 uint8_t K2[16]; 5806 uint32_t key_id; 5807 uint32_t sta_id; 5808 uint64_t receive_seq_cnt; 5809} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5810 5811struct iwm_mvm_wep_key { 5812 uint8_t key_index; 5813 uint8_t key_offset; 5814 uint16_t reserved1; 5815 uint8_t key_size; 5816 uint8_t reserved2[3]; 5817 uint8_t key[16]; 5818} __packed; 5819 5820struct iwm_mvm_wep_key_cmd { 5821 uint32_t mac_id_n_color; 5822 uint8_t num_keys; 5823 uint8_t decryption_type; 5824 uint8_t flags; 5825 uint8_t reserved; 5826 struct iwm_mvm_wep_key wep_key[0]; 5827} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5828 5829/* 5830 * END mvm/fw-api-sta.h 5831 */ 5832 5833/* 5834 * BT coex 5835 */ 5836 5837enum iwm_bt_coex_mode { 5838 IWM_BT_COEX_DISABLE = 0x0, 5839 IWM_BT_COEX_NW = 0x1, 5840 IWM_BT_COEX_BT = 0x2, 5841 IWM_BT_COEX_WIFI = 0x3, 5842}; /* BT_COEX_MODES_E */ 5843 5844enum iwm_bt_coex_enabled_modules { 5845 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5846 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5847 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5848 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5849 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5850}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5851 5852/** 5853 * struct iwm_bt_coex_cmd - bt coex configuration command 5854 * @mode: enum %iwm_bt_coex_mode 5855 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5856 * 5857 * The structure is used for the BT_COEX command. 5858 */ 5859struct iwm_bt_coex_cmd { 5860 uint32_t mode; 5861 uint32_t enabled_modules; 5862} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5863 5864 5865/* 5866 * Location Aware Regulatory (LAR) API - MCC updates 5867 */ 5868 5869/** 5870 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5871 * regulatory profile according to the given MCC (Mobile Country Code). 5872 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5873 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5874 * MCC in the cmd response will be the relevant MCC in the NVM. 5875 * @mcc: given mobile country code 5876 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5877 * @reserved: reserved for alignment 5878 */ 5879struct iwm_mcc_update_cmd_v1 { 5880 uint16_t mcc; 5881 uint8_t source_id; 5882 uint8_t reserved; 5883} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5884 5885/** 5886 * struct iwm_mcc_update_cmd - Request the device to update geographic 5887 * regulatory profile according to the given MCC (Mobile Country Code). 5888 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5889 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5890 * MCC in the cmd response will be the relevant MCC in the NVM. 5891 * @mcc: given mobile country code 5892 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5893 * @reserved: reserved for alignment 5894 * @key: integrity key for MCC API OEM testing 5895 * @reserved2: reserved 5896 */ 5897struct iwm_mcc_update_cmd { 5898 uint16_t mcc; 5899 uint8_t source_id; 5900 uint8_t reserved; 5901 uint32_t key; 5902 uint32_t reserved2[5]; 5903} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5904 5905/** 5906 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5907 * Contains the new channel control profile map, if changed, and the new MCC 5908 * (mobile country code). 5909 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5910 * @status: see &enum iwm_mcc_update_status 5911 * @mcc: the new applied MCC 5912 * @cap: capabilities for all channels which matches the MCC 5913 * @source_id: the MCC source, see iwm_mcc_source 5914 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5915 * channels, depending on platform) 5916 * @channels: channel control data map, DWORD for each channel. Only the first 5917 * 16bits are used. 5918 */ 5919struct iwm_mcc_update_resp_v1 { 5920 uint32_t status; 5921 uint16_t mcc; 5922 uint8_t cap; 5923 uint8_t source_id; 5924 uint32_t n_channels; 5925 uint32_t channels[0]; 5926} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5927 5928/** 5929 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5930 * Contains the new channel control profile map, if changed, and the new MCC 5931 * (mobile country code). 5932 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5933 * @status: see &enum iwm_mcc_update_status 5934 * @mcc: the new applied MCC 5935 * @cap: capabilities for all channels which matches the MCC 5936 * @source_id: the MCC source, see iwm_mcc_source 5937 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5938 * @reserved: reserved. 5939 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5940 * channels, depending on platform) 5941 * @channels: channel control data map, DWORD for each channel. Only the first 5942 * 16bits are used. 5943 */ 5944struct iwm_mcc_update_resp { 5945 uint32_t status; 5946 uint16_t mcc; 5947 uint8_t cap; 5948 uint8_t source_id; 5949 uint16_t time; 5950 uint16_t reserved; 5951 uint32_t n_channels; 5952 uint32_t channels[0]; 5953} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5954 5955/** 5956 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5957 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5958 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5959 * the cellular and connectivity cores that gets updates of the mcc, and 5960 * notifies the ucode directly of any mcc change. 5961 * The ucode requests the driver to request the device to update geographic 5962 * regulatory profile according to the given MCC (Mobile Country Code). 5963 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5964 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5965 * MCC in the cmd response will be the relevant MCC in the NVM. 5966 * @mcc: given mobile country code 5967 * @source_id: identity of the change originator, see iwm_mcc_source 5968 * @reserved1: reserved for alignment 5969 */ 5970struct iwm_mcc_chub_notif { 5971 uint16_t mcc; 5972 uint8_t source_id; 5973 uint8_t reserved1; 5974} __packed; /* LAR_MCC_NOTIFY_S */ 5975 5976enum iwm_mcc_update_status { 5977 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5978 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5979 IWM_MCC_RESP_INVALID, 5980 IWM_MCC_RESP_NVM_DISABLED, 5981 IWM_MCC_RESP_ILLEGAL, 5982 IWM_MCC_RESP_LOW_PRIORITY, 5983 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5984 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5985 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5986}; 5987 5988enum iwm_mcc_source { 5989 IWM_MCC_SOURCE_OLD_FW = 0, 5990 IWM_MCC_SOURCE_ME = 1, 5991 IWM_MCC_SOURCE_BIOS = 2, 5992 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5993 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5994 IWM_MCC_SOURCE_WIFI = 5, 5995 IWM_MCC_SOURCE_RESERVED = 6, 5996 IWM_MCC_SOURCE_DEFAULT = 7, 5997 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5998 IWM_MCC_SOURCE_MCC_API = 9, 5999 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6000 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6001}; 6002 6003/* 6004 * Some cherry-picked definitions 6005 */ 6006 6007#define IWM_FRAME_LIMIT 64 6008 6009/* 6010 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6011 * As the firmware is slowly running out of command IDs and grouping of 6012 * commands is desirable anyway, the firmware is extending the command 6013 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6014 * former flags field, since that's always 0 on commands and thus can 6015 * be easily used to distinguish between the two). 6016 * 6017 * These functions retrieve specific information from the id field in 6018 * the iwm_host_cmd struct which contains the command id, the group id, 6019 * and the version of the command. 6020*/ 6021static inline uint8_t 6022iwm_cmd_opcode(uint32_t cmdid) 6023{ 6024 return cmdid & 0xff; 6025} 6026 6027static inline uint8_t 6028iwm_cmd_groupid(uint32_t cmdid) 6029{ 6030 return ((cmdid & 0Xff00) >> 8); 6031} 6032 6033static inline uint8_t 6034iwm_cmd_version(uint32_t cmdid) 6035{ 6036 return ((cmdid & 0xff0000) >> 16); 6037} 6038 6039static inline uint32_t 6040iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6041{ 6042 return opcode + (groupid << 8) + (version << 16); 6043} 6044 6045/* make uint16_t wide id out of uint8_t group and opcode */ 6046#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6047 6048/* due to the conversion, this group is special */ 6049#define IWM_ALWAYS_LONG_GROUP 1 6050 6051struct iwm_cmd_header { 6052 uint8_t code; 6053 uint8_t flags; 6054 uint8_t idx; 6055 uint8_t qid; 6056} __packed; 6057 6058struct iwm_cmd_header_wide { 6059 uint8_t opcode; 6060 uint8_t group_id; 6061 uint8_t idx; 6062 uint8_t qid; 6063 uint16_t length; 6064 uint8_t reserved; 6065 uint8_t version; 6066} __packed; 6067 6068enum iwm_power_scheme { 6069 IWM_POWER_SCHEME_CAM = 1, 6070 IWM_POWER_SCHEME_BPS, 6071 IWM_POWER_SCHEME_LP 6072}; 6073 6074#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6075#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6076#define IWM_CMD_FAILED_MSK 0x40 6077 6078/** 6079 * struct iwm_device_cmd 6080 * 6081 * For allocation of the command and tx queues, this establishes the overall 6082 * size of the largest command we send to uCode, except for commands that 6083 * aren't fully copied and use other TFD space. 6084 */ 6085struct iwm_device_cmd { 6086 union { 6087 struct { 6088 struct iwm_cmd_header hdr; 6089 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6090 }; 6091 struct { 6092 struct iwm_cmd_header_wide hdr_wide; 6093 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6094 sizeof(struct iwm_cmd_header_wide) + 6095 sizeof(struct iwm_cmd_header)]; 6096 }; 6097 }; 6098} __packed; 6099 6100struct iwm_rx_packet { 6101 /* 6102 * The first 4 bytes of the RX frame header contain both the RX frame 6103 * size and some flags. 6104 * Bit fields: 6105 * 31: flag flush RB request 6106 * 30: flag ignore TC (terminal counter) request 6107 * 29: flag fast IRQ request 6108 * 28-14: Reserved 6109 * 13-00: RX frame size 6110 */ 6111 uint32_t len_n_flags; 6112 struct iwm_cmd_header hdr; 6113 uint8_t data[]; 6114} __packed; 6115 6116#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6117 6118static inline uint32_t 6119iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6120{ 6121 6122 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6123} 6124 6125static inline uint32_t 6126iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6127{ 6128 6129 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6130} 6131 6132 6133#define IWM_MIN_DBM -100 6134#define IWM_MAX_DBM -33 /* realistic guess */ 6135 6136#define IWM_READ(sc, reg) \ 6137 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6138 6139#define IWM_WRITE(sc, reg, val) \ 6140 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6141 6142#define IWM_WRITE_1(sc, reg, val) \ 6143 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6144 6145#define IWM_SETBITS(sc, reg, mask) \ 6146 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6147 6148#define IWM_CLRBITS(sc, reg, mask) \ 6149 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6150 6151#define IWM_BARRIER_WRITE(sc) \ 6152 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6153 BUS_SPACE_BARRIER_WRITE) 6154 6155#define IWM_BARRIER_READ_WRITE(sc) \ 6156 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6157 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6158 6159#endif /* __IF_IWM_REG_H__ */ 6160