if_iwmreg.h revision 330201
1303628Ssbruno/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2286441Srpaulo/* $FreeBSD: stable/11/sys/dev/iwm/if_iwmreg.h 330201 2018-03-01 06:34:21Z eadler $ */ 3286441Srpaulo 4286441Srpaulo/****************************************************************************** 5286441Srpaulo * 6286441Srpaulo * This file is provided under a dual BSD/GPLv2 license. When using or 7286441Srpaulo * redistributing this file, you may do so under either license. 8286441Srpaulo * 9286441Srpaulo * GPL LICENSE SUMMARY 10286441Srpaulo * 11286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12286441Srpaulo * 13286441Srpaulo * This program is free software; you can redistribute it and/or modify 14286441Srpaulo * it under the terms of version 2 of the GNU General Public License as 15286441Srpaulo * published by the Free Software Foundation. 16286441Srpaulo * 17286441Srpaulo * This program is distributed in the hope that it will be useful, but 18286441Srpaulo * WITHOUT ANY WARRANTY; without even the implied warranty of 19286441Srpaulo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20286441Srpaulo * General Public License for more details. 21286441Srpaulo * 22286441Srpaulo * You should have received a copy of the GNU General Public License 23286441Srpaulo * along with this program; if not, write to the Free Software 24286441Srpaulo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25286441Srpaulo * USA 26286441Srpaulo * 27286441Srpaulo * The full GNU General Public License is included in this distribution 28286441Srpaulo * in the file called COPYING. 29286441Srpaulo * 30286441Srpaulo * Contact Information: 31286441Srpaulo * Intel Linux Wireless <ilw@linux.intel.com> 32286441Srpaulo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33286441Srpaulo * 34286441Srpaulo * BSD LICENSE 35286441Srpaulo * 36286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37286441Srpaulo * All rights reserved. 38286441Srpaulo * 39286441Srpaulo * Redistribution and use in source and binary forms, with or without 40286441Srpaulo * modification, are permitted provided that the following conditions 41286441Srpaulo * are met: 42286441Srpaulo * 43286441Srpaulo * * Redistributions of source code must retain the above copyright 44286441Srpaulo * notice, this list of conditions and the following disclaimer. 45286441Srpaulo * * Redistributions in binary form must reproduce the above copyright 46286441Srpaulo * notice, this list of conditions and the following disclaimer in 47286441Srpaulo * the documentation and/or other materials provided with the 48286441Srpaulo * distribution. 49286441Srpaulo * * Neither the name Intel Corporation nor the names of its 50286441Srpaulo * contributors may be used to endorse or promote products derived 51286441Srpaulo * from this software without specific prior written permission. 52286441Srpaulo * 53286441Srpaulo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54286441Srpaulo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55286441Srpaulo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56286441Srpaulo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57286441Srpaulo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58286441Srpaulo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59286441Srpaulo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60286441Srpaulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61286441Srpaulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62286441Srpaulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63286441Srpaulo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64286441Srpaulo * 65286441Srpaulo *****************************************************************************/ 66286441Srpaulo#ifndef __IF_IWM_REG_H__ 67286441Srpaulo#define __IF_IWM_REG_H__ 68286441Srpaulo 69286441Srpaulo#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70286441Srpaulo#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71286441Srpaulo 72286441Srpaulo/* 73286441Srpaulo * BEGIN iwl-csr.h 74286441Srpaulo */ 75286441Srpaulo 76286441Srpaulo/* 77286441Srpaulo * CSR (control and status registers) 78286441Srpaulo * 79286441Srpaulo * CSR registers are mapped directly into PCI bus space, and are accessible 80286441Srpaulo * whenever platform supplies power to device, even when device is in 81286441Srpaulo * low power states due to driver-invoked device resets 82286441Srpaulo * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83286441Srpaulo * 84286441Srpaulo * Use iwl_write32() and iwl_read32() family to access these registers; 85286441Srpaulo * these provide simple PCI bus access, without waking up the MAC. 86286441Srpaulo * Do not use iwl_write_direct32() family for these registers; 87286441Srpaulo * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88286441Srpaulo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89286441Srpaulo * the CSR registers. 90286441Srpaulo * 91286441Srpaulo * NOTE: Device does need to be awake in order to read this memory 92286441Srpaulo * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93286441Srpaulo */ 94286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95286441Srpaulo#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96286441Srpaulo#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97286441Srpaulo#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98286441Srpaulo#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99286441Srpaulo#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100286441Srpaulo#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101286441Srpaulo#define IWM_CSR_GP_CNTRL (0x024) 102286441Srpaulo 103286441Srpaulo/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104286441Srpaulo#define IWM_CSR_INT_PERIODIC_REG (0x005) 105286441Srpaulo 106286441Srpaulo/* 107286441Srpaulo * Hardware revision info 108286441Srpaulo * Bit fields: 109286441Srpaulo * 31-16: Reserved 110286441Srpaulo * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111286441Srpaulo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112286441Srpaulo * 1-0: "Dash" (-) value, as in A-1, etc. 113286441Srpaulo */ 114286441Srpaulo#define IWM_CSR_HW_REV (0x028) 115286441Srpaulo 116286441Srpaulo/* 117286441Srpaulo * EEPROM and OTP (one-time-programmable) memory reads 118286441Srpaulo * 119286441Srpaulo * NOTE: Device must be awake, initialized via apm_ops.init(), 120286441Srpaulo * in order to read. 121286441Srpaulo */ 122286441Srpaulo#define IWM_CSR_EEPROM_REG (0x02c) 123286441Srpaulo#define IWM_CSR_EEPROM_GP (0x030) 124286441Srpaulo#define IWM_CSR_OTP_GP_REG (0x034) 125286441Srpaulo 126286441Srpaulo#define IWM_CSR_GIO_REG (0x03C) 127286441Srpaulo#define IWM_CSR_GP_UCODE_REG (0x048) 128286441Srpaulo#define IWM_CSR_GP_DRIVER_REG (0x050) 129286441Srpaulo 130286441Srpaulo/* 131286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox registers. 132286441Srpaulo * SET/CLR registers set/clear bit(s) if "1" is written. 133286441Srpaulo */ 134286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137286441Srpaulo#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138286441Srpaulo 139303628Ssbruno#define IWM_CSR_MBOX_SET_REG (0x088) 140303628Ssbruno#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141303628Ssbruno 142286441Srpaulo#define IWM_CSR_LED_REG (0x094) 143286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144286441Srpaulo#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145286441Srpaulo 146286441Srpaulo 147286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 148286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149286441Srpaulo 150286441Srpaulo/* Analog phase-lock-loop configuration */ 151286441Srpaulo#define IWM_CSR_ANA_PLL_CFG (0x20c) 152286441Srpaulo 153286441Srpaulo/* 154286441Srpaulo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155286441Srpaulo * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156286441Srpaulo * See also IWM_CSR_HW_REV register. 157286441Srpaulo * Bit fields: 158286441Srpaulo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159286441Srpaulo * 1-0: "Dash" (-) value, as in C-1, etc. 160286441Srpaulo */ 161286441Srpaulo#define IWM_CSR_HW_REV_WA_REG (0x22C) 162286441Srpaulo 163286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164286441Srpaulo#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165286441Srpaulo 166286441Srpaulo/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175286441Srpaulo 176286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182286441Srpaulo 183286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188303628Ssbruno#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189303628Ssbruno#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190286441Srpaulo 191286441Srpaulo#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192286441Srpaulo#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193286441Srpaulo 194286441Srpaulo/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195286441Srpaulo * acknowledged (reset) by host writing "1" to flagged bits. */ 196286441Srpaulo#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197286441Srpaulo#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198286441Srpaulo#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199286441Srpaulo#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200286441Srpaulo#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201286441Srpaulo#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202286441Srpaulo#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203286441Srpaulo#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204286441Srpaulo#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205286441Srpaulo#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206286441Srpaulo#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207286441Srpaulo 208286441Srpaulo#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209286441Srpaulo IWM_CSR_INT_BIT_HW_ERR | \ 210286441Srpaulo IWM_CSR_INT_BIT_FH_TX | \ 211286441Srpaulo IWM_CSR_INT_BIT_SW_ERR | \ 212286441Srpaulo IWM_CSR_INT_BIT_RF_KILL | \ 213286441Srpaulo IWM_CSR_INT_BIT_SW_RX | \ 214286441Srpaulo IWM_CSR_INT_BIT_WAKEUP | \ 215286441Srpaulo IWM_CSR_INT_BIT_ALIVE | \ 216286441Srpaulo IWM_CSR_INT_BIT_RX_PERIODIC) 217286441Srpaulo 218286441Srpaulo/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219286441Srpaulo#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220286441Srpaulo#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225286441Srpaulo 226286441Srpaulo#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL0) 229286441Srpaulo 230286441Srpaulo#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231286441Srpaulo IWM_CSR_FH_INT_BIT_TX_CHNL0) 232286441Srpaulo 233286441Srpaulo/* GPIO */ 234286441Srpaulo#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237286441Srpaulo 238286441Srpaulo/* RESET */ 239286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244286441Srpaulo#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245286441Srpaulo 246286441Srpaulo/* 247286441Srpaulo * GP (general purpose) CONTROL REGISTER 248286441Srpaulo * Bit fields: 249286441Srpaulo * 27: HW_RF_KILL_SW 250286441Srpaulo * Indicates state of (platform's) hardware RF-Kill switch 251286441Srpaulo * 26-24: POWER_SAVE_TYPE 252286441Srpaulo * Indicates current power-saving mode: 253286441Srpaulo * 000 -- No power saving 254286441Srpaulo * 001 -- MAC power-down 255286441Srpaulo * 010 -- PHY (radio) power-down 256286441Srpaulo * 011 -- Error 257286441Srpaulo * 9-6: SYS_CONFIG 258286441Srpaulo * Indicates current system configuration, reflecting pins on chip 259286441Srpaulo * as forced high/low by device circuit board. 260286441Srpaulo * 4: GOING_TO_SLEEP 261286441Srpaulo * Indicates MAC is entering a power-saving sleep power-down. 262286441Srpaulo * Not a good time to access device-internal resources. 263286441Srpaulo * 3: MAC_ACCESS_REQ 264286441Srpaulo * Host sets this to request and maintain MAC wakeup, to allow host 265286441Srpaulo * access to device-internal resources. Host must wait for 266286441Srpaulo * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267286441Srpaulo * device registers. 268286441Srpaulo * 2: INIT_DONE 269286441Srpaulo * Host sets this to put device into fully operational D0 power mode. 270286441Srpaulo * Host resets this after SW_RESET to put device into low power mode. 271286441Srpaulo * 0: MAC_CLOCK_READY 272286441Srpaulo * Indicates MAC (ucode processor, etc.) is powered up and can run. 273286441Srpaulo * Internal resources are accessible. 274286441Srpaulo * NOTE: This does not indicate that the processor is actually running. 275286441Srpaulo * NOTE: This does not indicate that device has completed 276286441Srpaulo * init or post-power-down restore of internal SRAM memory. 277286441Srpaulo * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278286441Srpaulo * SRAM is restored and uCode is in normal operation mode. 279286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280286441Srpaulo * do not need to save/restore it. 281286441Srpaulo * NOTE: After device reset, this bit remains "0" until host sets 282286441Srpaulo * INIT_DONE 283286441Srpaulo */ 284286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288286441Srpaulo 289286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290286441Srpaulo 291286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294286441Srpaulo 295286441Srpaulo 296286441Srpaulo/* HW REV */ 297286441Srpaulo#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298286441Srpaulo#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299286441Srpaulo 300330162Seadler/** 301330162Seadler * hw_rev values 302330162Seadler */ 303330162Seadlerenum { 304330162Seadler IWM_SILICON_A_STEP = 0, 305330162Seadler IWM_SILICON_B_STEP, 306330162Seadler IWM_SILICON_C_STEP, 307330162Seadler}; 308330162Seadler 309330162Seadler 310286441Srpaulo#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315286441Srpaulo#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324286441Srpaulo#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325286441Srpaulo#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326303628Ssbruno#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327286441Srpaulo#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328286441Srpaulo 329286441Srpaulo/* EEPROM REG */ 330286441Srpaulo#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331286441Srpaulo#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334286441Srpaulo 335286441Srpaulo/* EEPROM GP */ 336286441Srpaulo#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337286441Srpaulo#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342286441Srpaulo 343286441Srpaulo/* One-time-programmable memory general purpose reg */ 344286441Srpaulo#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345286441Srpaulo#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348286441Srpaulo 349286441Srpaulo/* GP REG */ 350286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351286441Srpaulo#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352286441Srpaulo#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353286441Srpaulo#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355286441Srpaulo 356286441Srpaulo 357286441Srpaulo/* CSR GIO */ 358286441Srpaulo#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359286441Srpaulo 360286441Srpaulo/* 361286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox register 1 362286441Srpaulo * Host driver and uCode write and/or read this register to communicate with 363286441Srpaulo * each other. 364286441Srpaulo * Bit fields: 365286441Srpaulo * 4: UCODE_DISABLE 366286441Srpaulo * Host sets this to request permanent halt of uCode, same as 367286441Srpaulo * sending CARD_STATE command with "halt" bit set. 368286441Srpaulo * 3: CT_KILL_EXIT 369286441Srpaulo * Host sets this to request exit from CT_KILL state, i.e. host thinks 370286441Srpaulo * device temperature is low enough to continue normal operation. 371286441Srpaulo * 2: CMD_BLOCKED 372286441Srpaulo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373286441Srpaulo * to release uCode to clear all Tx and command queues, enter 374286441Srpaulo * unassociated mode, and power down. 375286441Srpaulo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376286441Srpaulo * 1: SW_BIT_RFKILL 377286441Srpaulo * Host sets this when issuing CARD_STATE command to request 378286441Srpaulo * device sleep. 379286441Srpaulo * 0: MAC_SLEEP 380286441Srpaulo * uCode sets this when preparing a power-saving power-down. 381286441Srpaulo * uCode resets this when power-up is complete and SRAM is sane. 382286441Srpaulo * NOTE: device saves internal SRAM data to host when powering down, 383286441Srpaulo * and must restore this data after powering back up. 384286441Srpaulo * MAC_SLEEP is the best indication that restore is complete. 385286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386286441Srpaulo * do not need to save/restore it. 387286441Srpaulo */ 388286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389286441Srpaulo#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393286441Srpaulo 394286441Srpaulo/* GP Driver */ 395286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401286441Srpaulo 402286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403286441Srpaulo 404286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 405286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407286441Srpaulo 408286441Srpaulo/* LED */ 409286441Srpaulo#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410286441Srpaulo#define IWM_CSR_LED_REG_TURN_ON (0x60) 411286441Srpaulo#define IWM_CSR_LED_REG_TURN_OFF (0x20) 412286441Srpaulo 413286441Srpaulo/* ANA_PLL */ 414286441Srpaulo#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415286441Srpaulo 416286441Srpaulo/* HPET MEM debug */ 417286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418286441Srpaulo 419286441Srpaulo/* DRAM INT TABLE */ 420286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421303628Ssbruno#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422286441Srpaulo#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423286441Srpaulo 424286441Srpaulo/* SECURE boot registers */ 425286441Srpaulo#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426286441Srpauloenum iwm_secure_boot_config_reg { 427286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429286441Srpaulo}; 430286441Srpaulo 431286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433286441Srpauloenum iwm_secure_boot_status_reg { 434286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439286441Srpaulo}; 440286441Srpaulo 441303628Ssbruno#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442303628Ssbruno#define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 443286441Srpauloenum iwm_secure_load_status_reg { 444303628Ssbruno IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 445303628Ssbruno IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 446303628Ssbruno IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 447303628Ssbruno IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 448303628Ssbruno IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 449286441Srpaulo}; 450303628Ssbruno#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 451286441Srpaulo 452303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 453303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 454303628Ssbruno#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 455303628Ssbruno#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 456286441Srpaulo 457303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 458303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 459303628Ssbruno#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 460303628Ssbruno#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 461303628Ssbruno 462286441Srpaulo#define IWM_CSR_SECURE_TIME_OUT (100) 463286441Srpaulo 464303628Ssbruno/* extended range in FW SRAM */ 465303628Ssbruno#define IWM_FW_MEM_EXTENDED_START 0x40000 466303628Ssbruno#define IWM_FW_MEM_EXTENDED_END 0x57FFF 467303628Ssbruno 468303628Ssbruno/* FW chicken bits */ 469303628Ssbruno#define IWM_LMPM_CHICK 0xa01ff8 470303628Ssbruno#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 471303628Ssbruno 472286441Srpaulo#define IWM_FH_TCSR_0_REG0 (0x1D00) 473286441Srpaulo 474286441Srpaulo/* 475286441Srpaulo * HBUS (Host-side Bus) 476286441Srpaulo * 477286441Srpaulo * HBUS registers are mapped directly into PCI bus space, but are used 478286441Srpaulo * to indirectly access device's internal memory or registers that 479286441Srpaulo * may be powered-down. 480286441Srpaulo * 481286441Srpaulo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 482286441Srpaulo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 483286441Srpaulo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 484286441Srpaulo * internal resources. 485286441Srpaulo * 486286441Srpaulo * Do not use iwl_write32()/iwl_read32() family to access these registers; 487286441Srpaulo * these provide only simple PCI bus access, without waking up the MAC. 488286441Srpaulo */ 489286441Srpaulo#define IWM_HBUS_BASE (0x400) 490286441Srpaulo 491286441Srpaulo/* 492286441Srpaulo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 493286441Srpaulo * structures, error log, event log, verifying uCode load). 494286441Srpaulo * First write to address register, then read from or write to data register 495286441Srpaulo * to complete the job. Once the address register is set up, accesses to 496286441Srpaulo * data registers auto-increment the address by one dword. 497286441Srpaulo * Bit usage for address registers (read or write): 498286441Srpaulo * 0-31: memory address within device 499286441Srpaulo */ 500286441Srpaulo#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 501286441Srpaulo#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 502286441Srpaulo#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 503286441Srpaulo#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 504286441Srpaulo 505286441Srpaulo/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 506286441Srpaulo#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 507286441Srpaulo#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 508286441Srpaulo 509286441Srpaulo/* 510286441Srpaulo * Registers for accessing device's internal peripheral registers 511286441Srpaulo * (e.g. SCD, BSM, etc.). First write to address register, 512286441Srpaulo * then read from or write to data register to complete the job. 513286441Srpaulo * Bit usage for address registers (read or write): 514286441Srpaulo * 0-15: register address (offset) within device 515286441Srpaulo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 516286441Srpaulo */ 517286441Srpaulo#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 518286441Srpaulo#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 519286441Srpaulo#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 520286441Srpaulo#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 521286441Srpaulo 522303628Ssbruno/* enable the ID buf for read */ 523303628Ssbruno#define IWM_WFPM_PS_CTL_CLR 0xa0300c 524303628Ssbruno#define IWM_WFMP_MAC_ADDR_0 0xa03080 525303628Ssbruno#define IWM_WFMP_MAC_ADDR_1 0xa03084 526303628Ssbruno#define IWM_LMPM_PMG_EN 0xa01cec 527303628Ssbruno#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 528303628Ssbruno#define IWM_RFIC_REG_RD 0xad0470 529303628Ssbruno#define IWM_WFPM_CTRL_REG 0xa03030 530303628Ssbruno#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 531303628Ssbruno#define IWM_ENABLE_WFPM 0x80000000 532303628Ssbruno 533303628Ssbruno#define IWM_AUX_MISC_REG 0xa200b0 534303628Ssbruno#define IWM_HW_STEP_LOCATION_BITS 24 535303628Ssbruno 536303628Ssbruno#define IWM_AUX_MISC_MASTER1_EN 0xa20818 537303628Ssbruno#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 538303628Ssbruno#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 539303628Ssbruno#define IWM_RSA_ENABLE 0xa24b08 540303628Ssbruno#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 541303628Ssbruno#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 542303628Ssbruno#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 543303628Ssbruno#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 544303628Ssbruno#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 545303628Ssbruno#define IWM_SB_CPU_1_STATUS 0xa01e30 546303628Ssbruno#define IWM_SB_CPU_2_STATUS 0Xa01e34 547303628Ssbruno 548286441Srpaulo/* Used to enable DBGM */ 549286441Srpaulo#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 550286441Srpaulo 551286441Srpaulo/* 552286441Srpaulo * Per-Tx-queue write pointer (index, really!) 553286441Srpaulo * Indicates index to next TFD that driver will fill (1 past latest filled). 554286441Srpaulo * Bit usage: 555286441Srpaulo * 0-7: queue write index 556286441Srpaulo * 11-8: queue selector 557286441Srpaulo */ 558286441Srpaulo#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 559286441Srpaulo 560286441Srpaulo/********************************************************** 561286441Srpaulo * CSR values 562286441Srpaulo **********************************************************/ 563286441Srpaulo /* 564286441Srpaulo * host interrupt timeout value 565286441Srpaulo * used with setting interrupt coalescing timer 566286441Srpaulo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 567286441Srpaulo * 568286441Srpaulo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 569286441Srpaulo */ 570286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 571286441Srpaulo#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 572286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 573286441Srpaulo#define IWM_HOST_INT_OPER_MODE (1 << 31) 574286441Srpaulo 575286441Srpaulo/***************************************************************************** 576286441Srpaulo * 7000/3000 series SHR DTS addresses * 577286441Srpaulo *****************************************************************************/ 578286441Srpaulo 579286441Srpaulo/* Diode Results Register Structure: */ 580286441Srpauloenum iwm_dtd_diode_reg { 581286441Srpaulo IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 582286441Srpaulo IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 583286441Srpaulo IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 584286441Srpaulo IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 585286441Srpaulo IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 586286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 587286441Srpaulo/* Those are the masks INSIDE the flags bit-field: */ 588286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 589286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 590286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 591286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 592286441Srpaulo}; 593286441Srpaulo 594286441Srpaulo/* 595286441Srpaulo * END iwl-csr.h 596286441Srpaulo */ 597286441Srpaulo 598286441Srpaulo/* 599286441Srpaulo * BEGIN iwl-fw.h 600286441Srpaulo */ 601286441Srpaulo 602286441Srpaulo/** 603301192Sadrian * enum iwm_ucode_tlv_flag - ucode API flags 604286441Srpaulo * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 605286441Srpaulo * was a separate TLV but moved here to save space. 606286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 607286441Srpaulo * treats good CRC threshold as a boolean 608286441Srpaulo * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 609286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 610286441Srpaulo * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 611286441Srpaulo * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 612286441Srpaulo * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 613286441Srpaulo * offload profile config command. 614286441Srpaulo * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 615286441Srpaulo * (rather than two) IPv6 addresses 616286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 617286441Srpaulo * from the probe request template. 618286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 619286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 620286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 621286441Srpaulo * single bound interface). 622303628Ssbruno * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 623303628Ssbruno * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 624286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 625303628Ssbruno * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 626303628Ssbruno * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 627303628Ssbruno * 628286441Srpaulo */ 629286441Srpauloenum iwm_ucode_tlv_flag { 630286441Srpaulo IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 631286441Srpaulo IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 632286441Srpaulo IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 633286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 634286441Srpaulo IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 635286441Srpaulo IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 636286441Srpaulo IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 637286441Srpaulo IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 638286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 639286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 640286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 641303628Ssbruno IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 642303628Ssbruno IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 643286441Srpaulo IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 644303628Ssbruno IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 645286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 646303628Ssbruno IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 647303628Ssbruno IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 648303628Ssbruno IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 649286441Srpaulo}; 650286441Srpaulo 651303628Ssbruno#define IWM_UCODE_TLV_FLAG_BITS \ 652303628Ssbruno "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 653303628SsbrunoY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 654303628SsbrunoL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 655303628SsbrunoP2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 656303628Ssbruno 657303628Ssbruno/** 658303628Ssbruno * enum iwm_ucode_tlv_api - ucode api 659303628Ssbruno * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 660303628Ssbruno * longer than the passive one, which is essential for fragmented scan. 661303628Ssbruno * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 662303628Ssbruno * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 663303628Ssbruno * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 664303628Ssbruno * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 665303628Ssbruno * instead of 3. 666303628Ssbruno * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 667303628Ssbruno * (command version 3) that supports per-chain limits 668303628Ssbruno * 669303628Ssbruno * @IWM_NUM_UCODE_TLV_API: number of bits used 670303628Ssbruno */ 671303628Ssbrunoenum iwm_ucode_tlv_api { 672303628Ssbruno IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 673303628Ssbruno IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 674303628Ssbruno IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 675303628Ssbruno IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 676303628Ssbruno IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 677303628Ssbruno IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 678303628Ssbruno 679303628Ssbruno IWM_NUM_UCODE_TLV_API = 32 680303628Ssbruno}; 681303628Ssbruno 682303628Ssbruno#define IWM_UCODE_TLV_API_BITS \ 683303628Ssbruno "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 684303628Ssbruno 685303628Ssbruno/** 686303628Ssbruno * enum iwm_ucode_tlv_capa - ucode capabilities 687303628Ssbruno * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 688303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 689303628Ssbruno * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 690303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 691303628Ssbruno * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 692303628Ssbruno * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 693303628Ssbruno * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 694303628Ssbruno * tx power value into TPC Report action frame and Link Measurement Report 695303628Ssbruno * action frame 696303628Ssbruno * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 697303628Ssbruno * channel in DS parameter set element in probe requests. 698303628Ssbruno * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 699303628Ssbruno * probe requests. 700303628Ssbruno * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 701303628Ssbruno * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 702303628Ssbruno * which also implies support for the scheduler configuration command 703303628Ssbruno * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 704303628Ssbruno * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 705303628Ssbruno * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 706303628Ssbruno * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 707303628Ssbruno * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 708303628Ssbruno * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 709303628Ssbruno * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 710303628Ssbruno * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 711303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 712303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 713303628Ssbruno * sources for the MCC. This TLV bit is a future replacement to 714303628Ssbruno * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 715303628Ssbruno * is supported. 716303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 717303628Ssbruno * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 718303628Ssbruno * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 719303628Ssbruno * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 720303628Ssbruno * 0=no support) 721303628Ssbruno * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 722303628Ssbruno * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 723303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 724303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 725303628Ssbruno * antenna the beacon should be transmitted 726303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 727303628Ssbruno * from AP and will send it upon d0i3 exit. 728303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 729303628Ssbruno * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 730303628Ssbruno * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 731303628Ssbruno * thresholds reporting 732303628Ssbruno * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 733303628Ssbruno * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 734303628Ssbruno * regular image. 735303628Ssbruno * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 736303628Ssbruno * memory addresses from the firmware. 737303628Ssbruno * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 738303628Ssbruno * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 739303628Ssbruno * 0=no support) 740303628Ssbruno * 741303628Ssbruno * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 742303628Ssbruno */ 743303628Ssbrunoenum iwm_ucode_tlv_capa { 744303628Ssbruno IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 745303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 746303628Ssbruno IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 747303628Ssbruno IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 748303628Ssbruno IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 749303628Ssbruno IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 750303628Ssbruno IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 751303628Ssbruno IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 752303628Ssbruno IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 753303628Ssbruno IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 754303628Ssbruno IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 755303628Ssbruno IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 756303628Ssbruno IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 757303628Ssbruno IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 758303628Ssbruno IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 759303628Ssbruno IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 760303628Ssbruno IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 761303628Ssbruno IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 762303628Ssbruno IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 763303628Ssbruno IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 764303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 765303628Ssbruno IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 766303628Ssbruno IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 767303628Ssbruno IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 768303628Ssbruno IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 769303628Ssbruno IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 770303628Ssbruno IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 771303628Ssbruno IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 772303628Ssbruno IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 773303628Ssbruno IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 774303628Ssbruno IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 775303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 776303628Ssbruno IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 777303628Ssbruno IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 778303628Ssbruno IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 779303628Ssbruno IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 780303628Ssbruno IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 781303628Ssbruno IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 782303628Ssbruno IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 783303628Ssbruno 784303628Ssbruno IWM_NUM_UCODE_TLV_CAPA = 128 785303628Ssbruno}; 786303628Ssbruno 787286441Srpaulo/* The default calibrate table size if not specified by firmware file */ 788286441Srpaulo#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 789286441Srpaulo#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 790286441Srpaulo#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 791286441Srpaulo 792286441Srpaulo/* The default max probe length if not specified by the firmware file */ 793286441Srpaulo#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 794286441Srpaulo 795286441Srpaulo/* 796286441Srpaulo * enumeration of ucode section. 797286441Srpaulo * This enumeration is used directly for older firmware (before 16.0). 798286441Srpaulo * For new firmware, there can be up to 4 sections (see below) but the 799286441Srpaulo * first one packaged into the firmware file is the DATA section and 800286441Srpaulo * some debugging code accesses that. 801286441Srpaulo */ 802286441Srpauloenum iwm_ucode_sec { 803286441Srpaulo IWM_UCODE_SECTION_DATA, 804286441Srpaulo IWM_UCODE_SECTION_INST, 805286441Srpaulo}; 806286441Srpaulo/* 807286441Srpaulo * For 16.0 uCode and above, there is no differentiation between sections, 808286441Srpaulo * just an offset to the HW address. 809286441Srpaulo */ 810303628Ssbruno#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 811303628Ssbruno#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 812286441Srpaulo 813286441Srpaulo/* uCode version contains 4 values: Major/Minor/API/Serial */ 814286441Srpaulo#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 815286441Srpaulo#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 816286441Srpaulo#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 817286441Srpaulo#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 818286441Srpaulo 819286441Srpaulo/* 820286441Srpaulo * Calibration control struct. 821286441Srpaulo * Sent as part of the phy configuration command. 822286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 823286441Srpaulo * flow triggers. 824286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 825286441Srpaulo * event triggers. 826286441Srpaulo */ 827286441Srpaulostruct iwm_tlv_calib_ctrl { 828286441Srpaulo uint32_t flow_trigger; 829286441Srpaulo uint32_t event_trigger; 830286441Srpaulo} __packed; 831286441Srpaulo 832286441Srpauloenum iwm_fw_phy_cfg { 833286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 834286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 835286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 836286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 837286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 838286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 839286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 840286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 841286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 842286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 843286441Srpaulo}; 844286441Srpaulo 845286441Srpaulo#define IWM_UCODE_MAX_CS 1 846286441Srpaulo 847286441Srpaulo/** 848286441Srpaulo * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 849286441Srpaulo * @cipher: a cipher suite selector 850286441Srpaulo * @flags: cipher scheme flags (currently reserved for a future use) 851286441Srpaulo * @hdr_len: a size of MPDU security header 852286441Srpaulo * @pn_len: a size of PN 853286441Srpaulo * @pn_off: an offset of pn from the beginning of the security header 854286441Srpaulo * @key_idx_off: an offset of key index byte in the security header 855286441Srpaulo * @key_idx_mask: a bit mask of key_idx bits 856286441Srpaulo * @key_idx_shift: bit shift needed to get key_idx 857286441Srpaulo * @mic_len: mic length in bytes 858286441Srpaulo * @hw_cipher: a HW cipher index used in host commands 859286441Srpaulo */ 860286441Srpaulostruct iwm_fw_cipher_scheme { 861286441Srpaulo uint32_t cipher; 862286441Srpaulo uint8_t flags; 863286441Srpaulo uint8_t hdr_len; 864286441Srpaulo uint8_t pn_len; 865286441Srpaulo uint8_t pn_off; 866286441Srpaulo uint8_t key_idx_off; 867286441Srpaulo uint8_t key_idx_mask; 868286441Srpaulo uint8_t key_idx_shift; 869286441Srpaulo uint8_t mic_len; 870286441Srpaulo uint8_t hw_cipher; 871286441Srpaulo} __packed; 872286441Srpaulo 873286441Srpaulo/** 874286441Srpaulo * struct iwm_fw_cscheme_list - a cipher scheme list 875286441Srpaulo * @size: a number of entries 876286441Srpaulo * @cs: cipher scheme entries 877286441Srpaulo */ 878286441Srpaulostruct iwm_fw_cscheme_list { 879286441Srpaulo uint8_t size; 880286441Srpaulo struct iwm_fw_cipher_scheme cs[]; 881286441Srpaulo} __packed; 882286441Srpaulo 883286441Srpaulo/* 884286441Srpaulo * END iwl-fw.h 885286441Srpaulo */ 886286441Srpaulo 887286441Srpaulo/* 888286441Srpaulo * BEGIN iwl-fw-file.h 889286441Srpaulo */ 890286441Srpaulo 891286441Srpaulo/* v1/v2 uCode file layout */ 892286441Srpaulostruct iwm_ucode_header { 893286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 894286441Srpaulo union { 895286441Srpaulo struct { 896286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 897286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 898286441Srpaulo uint32_t init_size; /* bytes of init code */ 899286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 900286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 901286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 902286441Srpaulo } v1; 903286441Srpaulo struct { 904286441Srpaulo uint32_t build; /* build number */ 905286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 906286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 907286441Srpaulo uint32_t init_size; /* bytes of init code */ 908286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 909286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 910286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 911286441Srpaulo } v2; 912286441Srpaulo } u; 913286441Srpaulo}; 914286441Srpaulo 915286441Srpaulo/* 916286441Srpaulo * new TLV uCode file layout 917286441Srpaulo * 918286441Srpaulo * The new TLV file format contains TLVs, that each specify 919286441Srpaulo * some piece of data. 920286441Srpaulo */ 921286441Srpaulo 922286441Srpauloenum iwm_ucode_tlv_type { 923286441Srpaulo IWM_UCODE_TLV_INVALID = 0, /* unused */ 924286441Srpaulo IWM_UCODE_TLV_INST = 1, 925286441Srpaulo IWM_UCODE_TLV_DATA = 2, 926286441Srpaulo IWM_UCODE_TLV_INIT = 3, 927286441Srpaulo IWM_UCODE_TLV_INIT_DATA = 4, 928286441Srpaulo IWM_UCODE_TLV_BOOT = 5, 929286441Srpaulo IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 930286441Srpaulo IWM_UCODE_TLV_PAN = 7, 931286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 932286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 933286441Srpaulo IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 934286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 935286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 936286441Srpaulo IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 937286441Srpaulo IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 938286441Srpaulo IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 939286441Srpaulo IWM_UCODE_TLV_WOWLAN_INST = 16, 940286441Srpaulo IWM_UCODE_TLV_WOWLAN_DATA = 17, 941286441Srpaulo IWM_UCODE_TLV_FLAGS = 18, 942286441Srpaulo IWM_UCODE_TLV_SEC_RT = 19, 943286441Srpaulo IWM_UCODE_TLV_SEC_INIT = 20, 944286441Srpaulo IWM_UCODE_TLV_SEC_WOWLAN = 21, 945286441Srpaulo IWM_UCODE_TLV_DEF_CALIB = 22, 946286441Srpaulo IWM_UCODE_TLV_PHY_SKU = 23, 947286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_RT = 24, 948286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 949286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 950286441Srpaulo IWM_UCODE_TLV_NUM_OF_CPU = 27, 951286441Srpaulo IWM_UCODE_TLV_CSCHEME = 28, 952286441Srpaulo 953286441Srpaulo /* 954286441Srpaulo * Following two are not in our base tag, but allow 955286441Srpaulo * handling ucode version 9. 956286441Srpaulo */ 957286441Srpaulo IWM_UCODE_TLV_API_CHANGES_SET = 29, 958303628Ssbruno IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 959303628Ssbruno 960303628Ssbruno IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 961303628Ssbruno IWM_UCODE_TLV_PAGING = 32, 962303628Ssbruno IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 963303628Ssbruno IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 964303628Ssbruno IWM_UCODE_TLV_FW_VERSION = 36, 965303628Ssbruno IWM_UCODE_TLV_FW_DBG_DEST = 38, 966303628Ssbruno IWM_UCODE_TLV_FW_DBG_CONF = 39, 967303628Ssbruno IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 968303628Ssbruno IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 969330179Seadler IWM_UCODE_TLV_FW_MEM_SEG = 51, 970286441Srpaulo}; 971286441Srpaulo 972286441Srpaulostruct iwm_ucode_tlv { 973286441Srpaulo uint32_t type; /* see above */ 974286441Srpaulo uint32_t length; /* not including type/length fields */ 975286441Srpaulo uint8_t data[0]; 976286441Srpaulo}; 977286441Srpaulo 978303628Ssbrunostruct iwm_ucode_api { 979303628Ssbruno uint32_t api_index; 980303628Ssbruno uint32_t api_flags; 981303628Ssbruno} __packed; 982303628Ssbruno 983303628Ssbrunostruct iwm_ucode_capa { 984303628Ssbruno uint32_t api_index; 985303628Ssbruno uint32_t api_capa; 986303628Ssbruno} __packed; 987303628Ssbruno 988286441Srpaulo#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 989286441Srpaulo 990286441Srpaulostruct iwm_tlv_ucode_header { 991286441Srpaulo /* 992286441Srpaulo * The TLV style ucode header is distinguished from 993286441Srpaulo * the v1/v2 style header by first four bytes being 994286441Srpaulo * zero, as such is an invalid combination of 995286441Srpaulo * major/minor/API/serial versions. 996286441Srpaulo */ 997286441Srpaulo uint32_t zero; 998286441Srpaulo uint32_t magic; 999286441Srpaulo uint8_t human_readable[64]; 1000286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 1001286441Srpaulo uint32_t build; 1002286441Srpaulo uint64_t ignore; 1003286441Srpaulo /* 1004286441Srpaulo * The data contained herein has a TLV layout, 1005286441Srpaulo * see above for the TLV header and types. 1006286441Srpaulo * Note that each TLV is padded to a length 1007286441Srpaulo * that is a multiple of 4 for alignment. 1008286441Srpaulo */ 1009286441Srpaulo uint8_t data[0]; 1010286441Srpaulo}; 1011286441Srpaulo 1012286441Srpaulo/* 1013286441Srpaulo * END iwl-fw-file.h 1014286441Srpaulo */ 1015286441Srpaulo 1016286441Srpaulo/* 1017286441Srpaulo * BEGIN iwl-prph.h 1018286441Srpaulo */ 1019286441Srpaulo 1020286441Srpaulo/* 1021286441Srpaulo * Registers in this file are internal, not PCI bus memory mapped. 1022286441Srpaulo * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1023286441Srpaulo */ 1024286441Srpaulo#define IWM_PRPH_BASE (0x00000) 1025286441Srpaulo#define IWM_PRPH_END (0xFFFFF) 1026286441Srpaulo 1027286441Srpaulo/* APMG (power management) constants */ 1028286441Srpaulo#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1029286441Srpaulo#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1030286441Srpaulo#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1031286441Srpaulo#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1032286441Srpaulo#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1033286441Srpaulo#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1034286441Srpaulo#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1035286441Srpaulo#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1036286441Srpaulo#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1037286441Srpaulo#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1038286441Srpaulo#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1039286441Srpaulo 1040286441Srpaulo#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1041286441Srpaulo#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1042286441Srpaulo#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1043286441Srpaulo 1044286441Srpaulo#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1045286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1046286441Srpaulo#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1047286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1048286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1049286441Srpaulo#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1050286441Srpaulo#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1051286441Srpaulo 1052286441Srpaulo#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1053286441Srpaulo 1054286441Srpaulo#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1055286441Srpaulo 1056286441Srpaulo/* Device system time */ 1057286441Srpaulo#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1058286441Srpaulo 1059286441Srpaulo/* Device NMI register */ 1060303628Ssbruno#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1061303628Ssbruno#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1062303628Ssbruno#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1063303628Ssbruno#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1064303628Ssbruno#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1065286441Srpaulo 1066303628Ssbruno/* 1067303628Ssbruno * Device reset for family 8000 1068303628Ssbruno * write to bit 24 in order to reset the CPU 1069303628Ssbruno */ 1070303628Ssbruno#define IWM_RELEASE_CPU_RESET 0x300c 1071303628Ssbruno#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1072303628Ssbruno 1073303628Ssbruno 1074286441Srpaulo/***************************************************************************** 1075286441Srpaulo * 7000/3000 series SHR DTS addresses * 1076286441Srpaulo *****************************************************************************/ 1077286441Srpaulo 1078286441Srpaulo#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1079286441Srpaulo#define IWM_DTSC_CFG_MODE (0x00a10604) 1080286441Srpaulo#define IWM_DTSC_VREF_AVG (0x00a10648) 1081286441Srpaulo#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1082286441Srpaulo#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1083286441Srpaulo#define IWM_DTSC_PTAT_AVG (0x00a10650) 1084286441Srpaulo 1085286441Srpaulo 1086286441Srpaulo/** 1087286441Srpaulo * Tx Scheduler 1088286441Srpaulo * 1089286441Srpaulo * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1090286441Srpaulo * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1091286441Srpaulo * host DRAM. It steers each frame's Tx command (which contains the frame 1092286441Srpaulo * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1093286441Srpaulo * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1094286441Srpaulo * but one DMA channel may take input from several queues. 1095286441Srpaulo * 1096286441Srpaulo * Tx DMA FIFOs have dedicated purposes. 1097286441Srpaulo * 1098286441Srpaulo * For 5000 series and up, they are used differently 1099286441Srpaulo * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1100286441Srpaulo * 1101286441Srpaulo * 0 -- EDCA BK (background) frames, lowest priority 1102286441Srpaulo * 1 -- EDCA BE (best effort) frames, normal priority 1103286441Srpaulo * 2 -- EDCA VI (video) frames, higher priority 1104286441Srpaulo * 3 -- EDCA VO (voice) and management frames, highest priority 1105286441Srpaulo * 4 -- unused 1106286441Srpaulo * 5 -- unused 1107286441Srpaulo * 6 -- unused 1108286441Srpaulo * 7 -- Commands 1109286441Srpaulo * 1110286441Srpaulo * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1111286441Srpaulo * In addition, driver can map the remaining queues to Tx DMA/FIFO 1112286441Srpaulo * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1113286441Srpaulo * 1114286441Srpaulo * The driver sets up each queue to work in one of two modes: 1115286441Srpaulo * 1116286441Srpaulo * 1) Scheduler-Ack, in which the scheduler automatically supports a 1117286441Srpaulo * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1118286441Srpaulo * contains TFDs for a unique combination of Recipient Address (RA) 1119286441Srpaulo * and Traffic Identifier (TID), that is, traffic of a given 1120286441Srpaulo * Quality-Of-Service (QOS) priority, destined for a single station. 1121286441Srpaulo * 1122286441Srpaulo * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1123286441Srpaulo * each frame within the BA window, including whether it's been transmitted, 1124286441Srpaulo * and whether it's been acknowledged by the receiving station. The device 1125286441Srpaulo * automatically processes block-acks received from the receiving STA, 1126286441Srpaulo * and reschedules un-acked frames to be retransmitted (successful 1127286441Srpaulo * Tx completion may end up being out-of-order). 1128286441Srpaulo * 1129286441Srpaulo * The driver must maintain the queue's Byte Count table in host DRAM 1130286441Srpaulo * for this mode. 1131286441Srpaulo * This mode does not support fragmentation. 1132286441Srpaulo * 1133286441Srpaulo * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1134286441Srpaulo * The device may automatically retry Tx, but will retry only one frame 1135286441Srpaulo * at a time, until receiving ACK from receiving station, or reaching 1136286441Srpaulo * retry limit and giving up. 1137286441Srpaulo * 1138286441Srpaulo * The command queue (#4/#9) must use this mode! 1139286441Srpaulo * This mode does not require use of the Byte Count table in host DRAM. 1140286441Srpaulo * 1141286441Srpaulo * Driver controls scheduler operation via 3 means: 1142286441Srpaulo * 1) Scheduler registers 1143286441Srpaulo * 2) Shared scheduler data base in internal SRAM 1144286441Srpaulo * 3) Shared data in host DRAM 1145286441Srpaulo * 1146286441Srpaulo * Initialization: 1147286441Srpaulo * 1148286441Srpaulo * When loading, driver should allocate memory for: 1149286441Srpaulo * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1150286441Srpaulo * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1151286441Srpaulo * (1024 bytes for each queue). 1152286441Srpaulo * 1153286441Srpaulo * After receiving "Alive" response from uCode, driver must initialize 1154286441Srpaulo * the scheduler (especially for queue #4/#9, the command queue, otherwise 1155286441Srpaulo * the driver can't issue commands!): 1156286441Srpaulo */ 1157286441Srpaulo#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1158286441Srpaulo 1159286441Srpaulo/** 1160286441Srpaulo * Max Tx window size is the max number of contiguous TFDs that the scheduler 1161286441Srpaulo * can keep track of at one time when creating block-ack chains of frames. 1162286441Srpaulo * Note that "64" matches the number of ack bits in a block-ack packet. 1163286441Srpaulo */ 1164286441Srpaulo#define IWM_SCD_WIN_SIZE 64 1165286441Srpaulo#define IWM_SCD_FRAME_LIMIT 64 1166286441Srpaulo 1167286441Srpaulo#define IWM_SCD_TXFIFO_POS_TID (0) 1168286441Srpaulo#define IWM_SCD_TXFIFO_POS_RA (4) 1169286441Srpaulo#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1170286441Srpaulo 1171286441Srpaulo/* agn SCD */ 1172286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1173286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1174286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1175286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1176286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1177286441Srpaulo 1178286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1179286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1180286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1181286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1182286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1183286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1184286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1185286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1186303628Ssbruno#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1187303628Ssbruno#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1188286441Srpaulo 1189286441Srpaulo/* Context Data */ 1190286441Srpaulo#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1191286441Srpaulo#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1192286441Srpaulo 1193286441Srpaulo/* Tx status */ 1194286441Srpaulo#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1195286441Srpaulo#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1196286441Srpaulo 1197286441Srpaulo/* Translation Data */ 1198286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1199286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1200286441Srpaulo 1201286441Srpaulo#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1202286441Srpaulo (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1203286441Srpaulo 1204286441Srpaulo#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1205286441Srpaulo (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1206286441Srpaulo 1207286441Srpaulo#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1208286441Srpaulo ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1209286441Srpaulo 1210286441Srpaulo#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1211286441Srpaulo 1212286441Srpaulo#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1213286441Srpaulo#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1214286441Srpaulo#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1215286441Srpaulo#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1216286441Srpaulo#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1217286441Srpaulo#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1218286441Srpaulo#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1219286441Srpaulo#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1220286441Srpaulo#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1221303628Ssbruno#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1222303628Ssbruno#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1223286441Srpaulo 1224286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1225286441Srpaulo{ 1226286441Srpaulo if (chnl < 20) 1227286441Srpaulo return IWM_SCD_BASE + 0x18 + chnl * 4; 1228286441Srpaulo return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1229286441Srpaulo} 1230286441Srpaulo 1231286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1232286441Srpaulo{ 1233286441Srpaulo if (chnl < 20) 1234286441Srpaulo return IWM_SCD_BASE + 0x68 + chnl * 4; 1235286441Srpaulo return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1236286441Srpaulo} 1237286441Srpaulo 1238286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1239286441Srpaulo{ 1240286441Srpaulo if (chnl < 20) 1241286441Srpaulo return IWM_SCD_BASE + 0x10c + chnl * 4; 1242286441Srpaulo return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1243286441Srpaulo} 1244286441Srpaulo 1245286441Srpaulo/*********************** END TX SCHEDULER *************************************/ 1246286441Srpaulo 1247286441Srpaulo/* Oscillator clock */ 1248286441Srpaulo#define IWM_OSC_CLK (0xa04068) 1249286441Srpaulo#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1250286441Srpaulo 1251286441Srpaulo/* 1252286441Srpaulo * END iwl-prph.h 1253286441Srpaulo */ 1254286441Srpaulo 1255286441Srpaulo/* 1256286441Srpaulo * BEGIN iwl-fh.h 1257286441Srpaulo */ 1258286441Srpaulo 1259286441Srpaulo/****************************/ 1260286441Srpaulo/* Flow Handler Definitions */ 1261286441Srpaulo/****************************/ 1262286441Srpaulo 1263286441Srpaulo/** 1264286441Srpaulo * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1265286441Srpaulo * Addresses are offsets from device's PCI hardware base address. 1266286441Srpaulo */ 1267286441Srpaulo#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1268286441Srpaulo#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1269286441Srpaulo 1270286441Srpaulo/** 1271286441Srpaulo * Keep-Warm (KW) buffer base address. 1272286441Srpaulo * 1273286441Srpaulo * Driver must allocate a 4KByte buffer that is for keeping the 1274286441Srpaulo * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1275286441Srpaulo * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1276286441Srpaulo * from going into a power-savings mode that would cause higher DRAM latency, 1277286441Srpaulo * and possible data over/under-runs, before all Tx/Rx is complete. 1278286441Srpaulo * 1279286441Srpaulo * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1280286441Srpaulo * of the buffer, which must be 4K aligned. Once this is set up, the device 1281286441Srpaulo * automatically invokes keep-warm accesses when normal accesses might not 1282286441Srpaulo * be sufficient to maintain fast DRAM response. 1283286441Srpaulo * 1284286441Srpaulo * Bit fields: 1285286441Srpaulo * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1286286441Srpaulo */ 1287286441Srpaulo#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1288286441Srpaulo 1289286441Srpaulo 1290286441Srpaulo/** 1291286441Srpaulo * TFD Circular Buffers Base (CBBC) addresses 1292286441Srpaulo * 1293286441Srpaulo * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1294286441Srpaulo * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1295286441Srpaulo * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1296286441Srpaulo * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1297286441Srpaulo * aligned (address bits 0-7 must be 0). 1298286441Srpaulo * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1299286441Srpaulo * for them are in different places. 1300286441Srpaulo * 1301286441Srpaulo * Bit fields in each pointer register: 1302286441Srpaulo * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1303286441Srpaulo */ 1304286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1305286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1306286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1307286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1308286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1309286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1310286441Srpaulo 1311286441Srpaulo/* Find TFD CB base pointer for given queue */ 1312286441Srpaulostatic inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1313286441Srpaulo{ 1314286441Srpaulo if (chnl < 16) 1315286441Srpaulo return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1316286441Srpaulo if (chnl < 20) 1317286441Srpaulo return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1318286441Srpaulo return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1319286441Srpaulo} 1320286441Srpaulo 1321286441Srpaulo 1322286441Srpaulo/** 1323286441Srpaulo * Rx SRAM Control and Status Registers (RSCSR) 1324286441Srpaulo * 1325286441Srpaulo * These registers provide handshake between driver and device for the Rx queue 1326286441Srpaulo * (this queue handles *all* command responses, notifications, Rx data, etc. 1327286441Srpaulo * sent from uCode to host driver). Unlike Tx, there is only one Rx 1328286441Srpaulo * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1329286441Srpaulo * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1330286441Srpaulo * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1331286441Srpaulo * mapping between RBDs and RBs. 1332286441Srpaulo * 1333286441Srpaulo * Driver must allocate host DRAM memory for the following, and set the 1334286441Srpaulo * physical address of each into device registers: 1335286441Srpaulo * 1336286441Srpaulo * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1337286441Srpaulo * entries (although any power of 2, up to 4096, is selectable by driver). 1338286441Srpaulo * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1339286441Srpaulo * (typically 4K, although 8K or 16K are also selectable by driver). 1340286441Srpaulo * Driver sets up RB size and number of RBDs in the CB via Rx config 1341286441Srpaulo * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1342286441Srpaulo * 1343286441Srpaulo * Bit fields within one RBD: 1344286441Srpaulo * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1345286441Srpaulo * 1346286441Srpaulo * Driver sets physical address [35:8] of base of RBD circular buffer 1347286441Srpaulo * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1348286441Srpaulo * 1349286441Srpaulo * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1350286441Srpaulo * (RBs) have been filled, via a "write pointer", actually the index of 1351286441Srpaulo * the RB's corresponding RBD within the circular buffer. Driver sets 1352286441Srpaulo * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1353286441Srpaulo * 1354286441Srpaulo * Bit fields in lower dword of Rx status buffer (upper dword not used 1355286441Srpaulo * by driver: 1356286441Srpaulo * 31-12: Not used by driver 1357286441Srpaulo * 11- 0: Index of last filled Rx buffer descriptor 1358286441Srpaulo * (device writes, driver reads this value) 1359286441Srpaulo * 1360286441Srpaulo * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1361286441Srpaulo * enter pointers to these RBs into contiguous RBD circular buffer entries, 1362286441Srpaulo * and update the device's "write" index register, 1363286441Srpaulo * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1364286441Srpaulo * 1365286441Srpaulo * This "write" index corresponds to the *next* RBD that the driver will make 1366286441Srpaulo * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1367286441Srpaulo * the circular buffer. This value should initially be 0 (before preparing any 1368286441Srpaulo * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1369286441Srpaulo * wrap back to 0 at the end of the circular buffer (but don't wrap before 1370286441Srpaulo * "read" index has advanced past 1! See below). 1371286441Srpaulo * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1372286441Srpaulo * 1373286441Srpaulo * As the device fills RBs (referenced from contiguous RBDs within the circular 1374286441Srpaulo * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1375286441Srpaulo * to tell the driver the index of the latest filled RBD. The driver must 1376286441Srpaulo * read this "read" index from DRAM after receiving an Rx interrupt from device 1377286441Srpaulo * 1378286441Srpaulo * The driver must also internally keep track of a third index, which is the 1379286441Srpaulo * next RBD to process. When receiving an Rx interrupt, driver should process 1380286441Srpaulo * all filled but unprocessed RBs up to, but not including, the RB 1381286441Srpaulo * corresponding to the "read" index. For example, if "read" index becomes "1", 1382286441Srpaulo * driver may process the RB pointed to by RBD 0. Depending on volume of 1383286441Srpaulo * traffic, there may be many RBs to process. 1384286441Srpaulo * 1385286441Srpaulo * If read index == write index, device thinks there is no room to put new data. 1386286441Srpaulo * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1387286441Srpaulo * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1388286441Srpaulo * and "read" indexes; that is, make sure that there are no more than 254 1389286441Srpaulo * buffers waiting to be filled. 1390286441Srpaulo */ 1391286441Srpaulo#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1392286441Srpaulo#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1393286441Srpaulo#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1394286441Srpaulo 1395286441Srpaulo/** 1396286441Srpaulo * Physical base address of 8-byte Rx Status buffer. 1397286441Srpaulo * Bit fields: 1398286441Srpaulo * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1399286441Srpaulo */ 1400286441Srpaulo#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1401286441Srpaulo 1402286441Srpaulo/** 1403286441Srpaulo * Physical base address of Rx Buffer Descriptor Circular Buffer. 1404286441Srpaulo * Bit fields: 1405286441Srpaulo * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1406286441Srpaulo */ 1407286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1408286441Srpaulo 1409286441Srpaulo/** 1410286441Srpaulo * Rx write pointer (index, really!). 1411286441Srpaulo * Bit fields: 1412286441Srpaulo * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1413286441Srpaulo * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1414286441Srpaulo */ 1415286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1416286441Srpaulo#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1417286441Srpaulo 1418286441Srpaulo#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1419286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1420286441Srpaulo 1421286441Srpaulo/** 1422286441Srpaulo * Rx Config/Status Registers (RCSR) 1423286441Srpaulo * Rx Config Reg for channel 0 (only channel used) 1424286441Srpaulo * 1425286441Srpaulo * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1426286441Srpaulo * normal operation (see bit fields). 1427286441Srpaulo * 1428286441Srpaulo * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1429286441Srpaulo * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1430286441Srpaulo * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1431286441Srpaulo * 1432286441Srpaulo * Bit fields: 1433286441Srpaulo * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1434286441Srpaulo * '10' operate normally 1435286441Srpaulo * 29-24: reserved 1436286441Srpaulo * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1437286441Srpaulo * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1438286441Srpaulo * 19-18: reserved 1439286441Srpaulo * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1440286441Srpaulo * '10' 12K, '11' 16K. 1441286441Srpaulo * 15-14: reserved 1442286441Srpaulo * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1443286441Srpaulo * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1444286441Srpaulo * typical value 0x10 (about 1/2 msec) 1445286441Srpaulo * 3- 0: reserved 1446286441Srpaulo */ 1447286441Srpaulo#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1448286441Srpaulo#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1449286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1450286441Srpaulo 1451286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1452286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1453286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1454286441Srpaulo 1455286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1456286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1457286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1458286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1459286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1460286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1461286441Srpaulo 1462286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1463286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1464286441Srpaulo#define IWM_RX_RB_TIMEOUT (0x11) 1465286441Srpaulo 1466286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1467286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1468286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1469286441Srpaulo 1470286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1471286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1472286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1473286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1474286441Srpaulo 1475286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1476286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1477286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1478286441Srpaulo 1479286441Srpaulo/** 1480286441Srpaulo * Rx Shared Status Registers (RSSR) 1481286441Srpaulo * 1482286441Srpaulo * After stopping Rx DMA channel (writing 0 to 1483286441Srpaulo * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1484286441Srpaulo * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1485286441Srpaulo * 1486286441Srpaulo * Bit fields: 1487286441Srpaulo * 24: 1 = Channel 0 is idle 1488286441Srpaulo * 1489286441Srpaulo * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1490286441Srpaulo * contain default values that should not be altered by the driver. 1491286441Srpaulo */ 1492286441Srpaulo#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1493286441Srpaulo#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1494286441Srpaulo 1495286441Srpaulo#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1496286441Srpaulo#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1497286441Srpaulo#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1498286441Srpaulo (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1499286441Srpaulo 1500286441Srpaulo#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1501286441Srpaulo 1502286441Srpaulo#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1503286441Srpaulo 1504286441Srpaulo/* TFDB Area - TFDs buffer table */ 1505286441Srpaulo#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1506286441Srpaulo#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1507286441Srpaulo#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1508286441Srpaulo#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1509286441Srpaulo#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1510286441Srpaulo 1511286441Srpaulo/** 1512286441Srpaulo * Transmit DMA Channel Control/Status Registers (TCSR) 1513286441Srpaulo * 1514286441Srpaulo * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1515286441Srpaulo * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1516286441Srpaulo * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1517286441Srpaulo * 1518286441Srpaulo * To use a Tx DMA channel, driver must initialize its 1519286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1520286441Srpaulo * 1521286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1522286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1523286441Srpaulo * 1524286441Srpaulo * All other bits should be 0. 1525286441Srpaulo * 1526286441Srpaulo * Bit fields: 1527286441Srpaulo * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1528286441Srpaulo * '10' operate normally 1529286441Srpaulo * 29- 4: Reserved, set to "0" 1530286441Srpaulo * 3: Enable internal DMA requests (1, normal operation), disable (0) 1531286441Srpaulo * 2- 0: Reserved, set to "0" 1532286441Srpaulo */ 1533286441Srpaulo#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1534286441Srpaulo#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1535286441Srpaulo 1536286441Srpaulo/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1537286441Srpaulo#define IWM_FH_TCSR_CHNL_NUM (8) 1538286441Srpaulo 1539286441Srpaulo/* TCSR: tx_config register values */ 1540286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1541286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1542286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1543286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1544286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1545286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1546286441Srpaulo 1547286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1548286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1549286441Srpaulo 1550286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1551286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1552286441Srpaulo 1553286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1554286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1555286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1556286441Srpaulo 1557286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1558286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1559286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1560286441Srpaulo 1561286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1562286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1563286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1564286441Srpaulo 1565286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1566286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1567286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1568286441Srpaulo 1569286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1570286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1571286441Srpaulo 1572286441Srpaulo/** 1573286441Srpaulo * Tx Shared Status Registers (TSSR) 1574286441Srpaulo * 1575286441Srpaulo * After stopping Tx DMA channel (writing 0 to 1576286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1577286441Srpaulo * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1578286441Srpaulo * (channel's buffers empty | no pending requests). 1579286441Srpaulo * 1580286441Srpaulo * Bit fields: 1581286441Srpaulo * 31-24: 1 = Channel buffers empty (channel 7:0) 1582286441Srpaulo * 23-16: 1 = No pending requests (channel 7:0) 1583286441Srpaulo */ 1584286441Srpaulo#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1585286441Srpaulo#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1586286441Srpaulo 1587286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1588286441Srpaulo 1589286441Srpaulo/** 1590286441Srpaulo * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1591286441Srpaulo * 31: Indicates an address error when accessed to internal memory 1592286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1593286441Srpaulo * 30: Indicates that Host did not send the expected number of dwords to FH 1594286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1595286441Srpaulo * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1596286441Srpaulo * command was received from the scheduler while the TRB was already full 1597286441Srpaulo * with previous command 1598286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1599286441Srpaulo * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1600286441Srpaulo * bit is set, it indicates that the FH has received a full indication 1601286441Srpaulo * from the RTC TxFIFO and the current value of the TxCredit counter was 1602286441Srpaulo * not equal to zero. This mean that the credit mechanism was not 1603286441Srpaulo * synchronized to the TxFIFO status 1604286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1605286441Srpaulo */ 1606286441Srpaulo#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1607286441Srpaulo#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1608286441Srpaulo 1609286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1610286441Srpaulo 1611286441Srpaulo/* Tx service channels */ 1612286441Srpaulo#define IWM_FH_SRVC_CHNL (9) 1613286441Srpaulo#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1614286441Srpaulo#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1615286441Srpaulo#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1616286441Srpaulo (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1617286441Srpaulo 1618286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1619286441Srpaulo#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1620286441Srpaulo (_chan) * 4) 1621286441Srpaulo 1622286441Srpaulo/* Instruct FH to increment the retry count of a packet when 1623286441Srpaulo * it is brought from the memory to TX-FIFO 1624286441Srpaulo */ 1625286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1626286441Srpaulo 1627286441Srpaulo#define IWM_RX_QUEUE_SIZE 256 1628286441Srpaulo#define IWM_RX_QUEUE_MASK 255 1629286441Srpaulo#define IWM_RX_QUEUE_SIZE_LOG 8 1630286441Srpaulo 1631286441Srpaulo/* 1632286441Srpaulo * RX related structures and functions 1633286441Srpaulo */ 1634286441Srpaulo#define IWM_RX_FREE_BUFFERS 64 1635286441Srpaulo#define IWM_RX_LOW_WATERMARK 8 1636286441Srpaulo 1637286441Srpaulo/** 1638286441Srpaulo * struct iwm_rb_status - reseve buffer status 1639286441Srpaulo * host memory mapped FH registers 1640286441Srpaulo * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1641286441Srpaulo * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1642286441Srpaulo * @finished_rb_num [0:11] - Indicates the index of the current RB 1643286441Srpaulo * in which the last frame was written to 1644286441Srpaulo * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1645286441Srpaulo * which was transferred 1646286441Srpaulo */ 1647286441Srpaulostruct iwm_rb_status { 1648286441Srpaulo uint16_t closed_rb_num; 1649286441Srpaulo uint16_t closed_fr_num; 1650286441Srpaulo uint16_t finished_rb_num; 1651286441Srpaulo uint16_t finished_fr_nam; 1652286441Srpaulo uint32_t unused; 1653286441Srpaulo} __packed; 1654286441Srpaulo 1655286441Srpaulo 1656286441Srpaulo#define IWM_TFD_QUEUE_SIZE_MAX (256) 1657286441Srpaulo#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1658286441Srpaulo#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1659286441Srpaulo IWM_TFD_QUEUE_SIZE_BC_DUP) 1660286441Srpaulo#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1661286441Srpaulo#define IWM_NUM_OF_TBS 20 1662286441Srpaulo 1663286441Srpaulostatic inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1664286441Srpaulo{ 1665286441Srpaulo return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1666286441Srpaulo} 1667286441Srpaulo/** 1668286441Srpaulo * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1669286441Srpaulo * 1670286441Srpaulo * This structure contains dma address and length of transmission address 1671286441Srpaulo * 1672286441Srpaulo * @lo: low [31:0] portion of the dma address of TX buffer 1673286441Srpaulo * every even is unaligned on 16 bit boundary 1674286441Srpaulo * @hi_n_len 0-3 [35:32] portion of dma 1675286441Srpaulo * 4-15 length of the tx buffer 1676286441Srpaulo */ 1677286441Srpaulostruct iwm_tfd_tb { 1678286441Srpaulo uint32_t lo; 1679286441Srpaulo uint16_t hi_n_len; 1680286441Srpaulo} __packed; 1681286441Srpaulo 1682286441Srpaulo/** 1683286441Srpaulo * struct iwm_tfd 1684286441Srpaulo * 1685286441Srpaulo * Transmit Frame Descriptor (TFD) 1686286441Srpaulo * 1687286441Srpaulo * @ __reserved1[3] reserved 1688286441Srpaulo * @ num_tbs 0-4 number of active tbs 1689286441Srpaulo * 5 reserved 1690286441Srpaulo * 6-7 padding (not used) 1691286441Srpaulo * @ tbs[20] transmit frame buffer descriptors 1692286441Srpaulo * @ __pad padding 1693286441Srpaulo * 1694286441Srpaulo * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1695286441Srpaulo * Both driver and device share these circular buffers, each of which must be 1696286441Srpaulo * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1697286441Srpaulo * 1698286441Srpaulo * Driver must indicate the physical address of the base of each 1699286441Srpaulo * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1700286441Srpaulo * 1701286441Srpaulo * Each TFD contains pointer/size information for up to 20 data buffers 1702286441Srpaulo * in host DRAM. These buffers collectively contain the (one) frame described 1703286441Srpaulo * by the TFD. Each buffer must be a single contiguous block of memory within 1704286441Srpaulo * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1705286441Srpaulo * of (4K - 4). The concatenates all of a TFD's buffers into a single 1706286441Srpaulo * Tx frame, up to 8 KBytes in size. 1707286441Srpaulo * 1708286441Srpaulo * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1709286441Srpaulo */ 1710286441Srpaulostruct iwm_tfd { 1711286441Srpaulo uint8_t __reserved1[3]; 1712286441Srpaulo uint8_t num_tbs; 1713286441Srpaulo struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1714286441Srpaulo uint32_t __pad; 1715286441Srpaulo} __packed; 1716286441Srpaulo 1717286441Srpaulo/* Keep Warm Size */ 1718286441Srpaulo#define IWM_KW_SIZE 0x1000 /* 4k */ 1719286441Srpaulo 1720286441Srpaulo/* Fixed (non-configurable) rx data from phy */ 1721286441Srpaulo 1722286441Srpaulo/** 1723286441Srpaulo * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1724286441Srpaulo * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1725286441Srpaulo * @tfd_offset 0-12 - tx command byte count 1726286441Srpaulo * 12-16 - station index 1727286441Srpaulo */ 1728286441Srpaulostruct iwm_agn_scd_bc_tbl { 1729286441Srpaulo uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1730286441Srpaulo} __packed; 1731286441Srpaulo 1732286441Srpaulo/* 1733286441Srpaulo * END iwl-fh.h 1734286441Srpaulo */ 1735286441Srpaulo 1736286441Srpaulo/* 1737286441Srpaulo * BEGIN mvm/fw-api.h 1738286441Srpaulo */ 1739286441Srpaulo 1740303628Ssbruno/* Maximum number of Tx queues. */ 1741303628Ssbruno#define IWM_MVM_MAX_QUEUES 31 1742286441Srpaulo 1743286441Srpaulo/* Tx queue numbers */ 1744286441Srpauloenum { 1745286441Srpaulo IWM_MVM_OFFCHANNEL_QUEUE = 8, 1746286441Srpaulo IWM_MVM_CMD_QUEUE = 9, 1747303628Ssbruno IWM_MVM_AUX_QUEUE = 15, 1748286441Srpaulo}; 1749286441Srpaulo 1750301192Sadrianenum iwm_mvm_tx_fifo { 1751301192Sadrian IWM_MVM_TX_FIFO_BK = 0, 1752301192Sadrian IWM_MVM_TX_FIFO_BE, 1753301192Sadrian IWM_MVM_TX_FIFO_VI, 1754301192Sadrian IWM_MVM_TX_FIFO_VO, 1755301192Sadrian IWM_MVM_TX_FIFO_MCAST = 5, 1756301192Sadrian IWM_MVM_TX_FIFO_CMD = 7, 1757301192Sadrian}; 1758286441Srpaulo 1759286441Srpaulo#define IWM_MVM_STATION_COUNT 16 1760286441Srpaulo 1761286441Srpaulo/* commands */ 1762286441Srpauloenum { 1763286441Srpaulo IWM_MVM_ALIVE = 0x1, 1764286441Srpaulo IWM_REPLY_ERROR = 0x2, 1765286441Srpaulo 1766286441Srpaulo IWM_INIT_COMPLETE_NOTIF = 0x4, 1767286441Srpaulo 1768286441Srpaulo /* PHY context commands */ 1769286441Srpaulo IWM_PHY_CONTEXT_CMD = 0x8, 1770286441Srpaulo IWM_DBG_CFG = 0x9, 1771286441Srpaulo 1772303628Ssbruno /* UMAC scan commands */ 1773303628Ssbruno IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1774303628Ssbruno IWM_SCAN_CFG_CMD = 0xc, 1775303628Ssbruno IWM_SCAN_REQ_UMAC = 0xd, 1776303628Ssbruno IWM_SCAN_ABORT_UMAC = 0xe, 1777303628Ssbruno IWM_SCAN_COMPLETE_UMAC = 0xf, 1778303628Ssbruno 1779286441Srpaulo /* station table */ 1780286441Srpaulo IWM_ADD_STA_KEY = 0x17, 1781286441Srpaulo IWM_ADD_STA = 0x18, 1782286441Srpaulo IWM_REMOVE_STA = 0x19, 1783286441Srpaulo 1784286441Srpaulo /* TX */ 1785286441Srpaulo IWM_TX_CMD = 0x1c, 1786286441Srpaulo IWM_TXPATH_FLUSH = 0x1e, 1787286441Srpaulo IWM_MGMT_MCAST_KEY = 0x1f, 1788286441Srpaulo 1789303628Ssbruno /* scheduler config */ 1790303628Ssbruno IWM_SCD_QUEUE_CFG = 0x1d, 1791303628Ssbruno 1792286441Srpaulo /* global key */ 1793286441Srpaulo IWM_WEP_KEY = 0x20, 1794286441Srpaulo 1795286441Srpaulo /* MAC and Binding commands */ 1796286441Srpaulo IWM_MAC_CONTEXT_CMD = 0x28, 1797286441Srpaulo IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1798286441Srpaulo IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1799286441Srpaulo IWM_BINDING_CONTEXT_CMD = 0x2b, 1800286441Srpaulo IWM_TIME_QUOTA_CMD = 0x2c, 1801286441Srpaulo IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1802286441Srpaulo 1803286441Srpaulo IWM_LQ_CMD = 0x4e, 1804286441Srpaulo 1805330192Seadler /* paging block to FW cpu2 */ 1806330192Seadler IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1807286441Srpaulo 1808286441Srpaulo /* Scan offload */ 1809286441Srpaulo IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1810286441Srpaulo IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1811303628Ssbruno IWM_HOT_SPOT_CMD = 0x53, 1812303628Ssbruno IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1813303628Ssbruno IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1814286441Srpaulo IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1815286441Srpaulo IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1816303628Ssbruno IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1817286441Srpaulo 1818286441Srpaulo /* Phy */ 1819286441Srpaulo IWM_PHY_CONFIGURATION_CMD = 0x6a, 1820286441Srpaulo IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1821286441Srpaulo /* IWM_PHY_DB_CMD = 0x6c, */ 1822286441Srpaulo 1823286441Srpaulo /* Power - legacy power table command */ 1824286441Srpaulo IWM_POWER_TABLE_CMD = 0x77, 1825286441Srpaulo IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1826286441Srpaulo 1827286441Srpaulo /* Thermal Throttling*/ 1828286441Srpaulo IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1829286441Srpaulo 1830286441Srpaulo /* Scanning */ 1831286441Srpaulo IWM_SCAN_ABORT_CMD = 0x81, 1832286441Srpaulo IWM_SCAN_START_NOTIFICATION = 0x82, 1833286441Srpaulo IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1834286441Srpaulo 1835286441Srpaulo /* NVM */ 1836286441Srpaulo IWM_NVM_ACCESS_CMD = 0x88, 1837286441Srpaulo 1838286441Srpaulo IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1839286441Srpaulo 1840286441Srpaulo IWM_BEACON_NOTIFICATION = 0x90, 1841286441Srpaulo IWM_BEACON_TEMPLATE_CMD = 0x91, 1842286441Srpaulo IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1843286441Srpaulo IWM_BT_CONFIG = 0x9b, 1844286441Srpaulo IWM_STATISTICS_NOTIFICATION = 0x9d, 1845286441Srpaulo IWM_REDUCE_TX_POWER_CMD = 0x9f, 1846286441Srpaulo 1847286441Srpaulo /* RF-KILL commands and notifications */ 1848286441Srpaulo IWM_CARD_STATE_CMD = 0xa0, 1849286441Srpaulo IWM_CARD_STATE_NOTIFICATION = 0xa1, 1850286441Srpaulo 1851286441Srpaulo IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1852286441Srpaulo 1853303628Ssbruno IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1854303628Ssbruno 1855286441Srpaulo /* Power - new power table command */ 1856286441Srpaulo IWM_MAC_PM_POWER_TABLE = 0xa9, 1857286441Srpaulo 1858286441Srpaulo IWM_REPLY_RX_PHY_CMD = 0xc0, 1859286441Srpaulo IWM_REPLY_RX_MPDU_CMD = 0xc1, 1860286441Srpaulo IWM_BA_NOTIF = 0xc5, 1861286441Srpaulo 1862303628Ssbruno /* Location Aware Regulatory */ 1863303628Ssbruno IWM_MCC_UPDATE_CMD = 0xc8, 1864303628Ssbruno IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1865303628Ssbruno 1866286441Srpaulo /* BT Coex */ 1867286441Srpaulo IWM_BT_COEX_PRIO_TABLE = 0xcc, 1868286441Srpaulo IWM_BT_COEX_PROT_ENV = 0xcd, 1869286441Srpaulo IWM_BT_PROFILE_NOTIFICATION = 0xce, 1870286441Srpaulo IWM_BT_COEX_CI = 0x5d, 1871286441Srpaulo 1872286441Srpaulo IWM_REPLY_SF_CFG_CMD = 0xd1, 1873286441Srpaulo IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1874286441Srpaulo 1875303628Ssbruno /* DTS measurements */ 1876303628Ssbruno IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1877303628Ssbruno IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1878303628Ssbruno 1879286441Srpaulo IWM_REPLY_DEBUG_CMD = 0xf0, 1880286441Srpaulo IWM_DEBUG_LOG_MSG = 0xf7, 1881286441Srpaulo 1882286441Srpaulo IWM_MCAST_FILTER_CMD = 0xd0, 1883286441Srpaulo 1884286441Srpaulo /* D3 commands/notifications */ 1885286441Srpaulo IWM_D3_CONFIG_CMD = 0xd3, 1886286441Srpaulo IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1887286441Srpaulo IWM_OFFLOADS_QUERY_CMD = 0xd5, 1888286441Srpaulo IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1889286441Srpaulo 1890286441Srpaulo /* for WoWLAN in particular */ 1891286441Srpaulo IWM_WOWLAN_PATTERNS = 0xe0, 1892286441Srpaulo IWM_WOWLAN_CONFIGURATION = 0xe1, 1893286441Srpaulo IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1894286441Srpaulo IWM_WOWLAN_TKIP_PARAM = 0xe3, 1895286441Srpaulo IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1896286441Srpaulo IWM_WOWLAN_GET_STATUSES = 0xe5, 1897286441Srpaulo IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1898286441Srpaulo 1899286441Srpaulo /* and for NetDetect */ 1900286441Srpaulo IWM_NET_DETECT_CONFIG_CMD = 0x54, 1901286441Srpaulo IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1902286441Srpaulo IWM_NET_DETECT_PROFILES_CMD = 0x57, 1903286441Srpaulo IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1904286441Srpaulo IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1905286441Srpaulo 1906286441Srpaulo IWM_REPLY_MAX = 0xff, 1907286441Srpaulo}; 1908286441Srpaulo 1909330178Seadlerenum iwm_phy_ops_subcmd_ids { 1910330178Seadler IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1911330178Seadler IWM_CTDP_CONFIG_CMD = 0x03, 1912330178Seadler IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1913330178Seadler IWM_CT_KILL_NOTIFICATION = 0xFE, 1914330178Seadler IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1915330178Seadler}; 1916330178Seadler 1917330178Seadler/* command groups */ 1918330178Seadlerenum { 1919330178Seadler IWM_LEGACY_GROUP = 0x0, 1920330178Seadler IWM_LONG_GROUP = 0x1, 1921330178Seadler IWM_SYSTEM_GROUP = 0x2, 1922330178Seadler IWM_MAC_CONF_GROUP = 0x3, 1923330178Seadler IWM_PHY_OPS_GROUP = 0x4, 1924330178Seadler IWM_DATA_PATH_GROUP = 0x5, 1925330178Seadler IWM_PROT_OFFLOAD_GROUP = 0xb, 1926330178Seadler}; 1927330178Seadler 1928286441Srpaulo/** 1929286441Srpaulo * struct iwm_cmd_response - generic response struct for most commands 1930286441Srpaulo * @status: status of the command asked, changes for each one 1931286441Srpaulo */ 1932286441Srpaulostruct iwm_cmd_response { 1933286441Srpaulo uint32_t status; 1934286441Srpaulo}; 1935286441Srpaulo 1936286441Srpaulo/* 1937286441Srpaulo * struct iwm_tx_ant_cfg_cmd 1938286441Srpaulo * @valid: valid antenna configuration 1939286441Srpaulo */ 1940286441Srpaulostruct iwm_tx_ant_cfg_cmd { 1941286441Srpaulo uint32_t valid; 1942286441Srpaulo} __packed; 1943286441Srpaulo 1944286441Srpaulo/** 1945286441Srpaulo * struct iwm_reduce_tx_power_cmd - TX power reduction command 1946286441Srpaulo * IWM_REDUCE_TX_POWER_CMD = 0x9f 1947286441Srpaulo * @flags: (reserved for future implementation) 1948286441Srpaulo * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1949286441Srpaulo * @pwr_restriction: TX power restriction in dBms. 1950286441Srpaulo */ 1951286441Srpaulostruct iwm_reduce_tx_power_cmd { 1952286441Srpaulo uint8_t flags; 1953286441Srpaulo uint8_t mac_context_id; 1954286441Srpaulo uint16_t pwr_restriction; 1955286441Srpaulo} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1956286441Srpaulo 1957286441Srpaulo/* 1958286441Srpaulo * Calibration control struct. 1959286441Srpaulo * Sent as part of the phy configuration command. 1960286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 1961286441Srpaulo * flow triggers. 1962286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 1963286441Srpaulo * event triggers. 1964286441Srpaulo */ 1965286441Srpaulostruct iwm_calib_ctrl { 1966286441Srpaulo uint32_t flow_trigger; 1967286441Srpaulo uint32_t event_trigger; 1968286441Srpaulo} __packed; 1969286441Srpaulo 1970286441Srpaulo/* This enum defines the bitmap of various calibrations to enable in both 1971286441Srpaulo * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1972286441Srpaulo */ 1973286441Srpauloenum iwm_calib_cfg { 1974286441Srpaulo IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1975286441Srpaulo IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1976286441Srpaulo IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1977286441Srpaulo IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1978286441Srpaulo IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1979286441Srpaulo IWM_CALIB_CFG_DC_IDX = (1 << 5), 1980286441Srpaulo IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1981286441Srpaulo IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1982286441Srpaulo IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1983286441Srpaulo IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1984286441Srpaulo IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1985286441Srpaulo IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1986286441Srpaulo IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1987286441Srpaulo IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1988286441Srpaulo IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1989286441Srpaulo IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1990286441Srpaulo IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1991286441Srpaulo IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1992286441Srpaulo IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1993286441Srpaulo}; 1994286441Srpaulo 1995286441Srpaulo/* 1996286441Srpaulo * Phy configuration command. 1997286441Srpaulo */ 1998286441Srpaulostruct iwm_phy_cfg_cmd { 1999286441Srpaulo uint32_t phy_cfg; 2000286441Srpaulo struct iwm_calib_ctrl calib_control; 2001286441Srpaulo} __packed; 2002286441Srpaulo 2003286441Srpaulo#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2004286441Srpaulo#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2005286441Srpaulo#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2006286441Srpaulo#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2007286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2008286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2009286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2010286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2011286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2012286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2013286441Srpaulo 2014286441Srpaulo 2015286441Srpaulo/* Target of the IWM_NVM_ACCESS_CMD */ 2016286441Srpauloenum { 2017286441Srpaulo IWM_NVM_ACCESS_TARGET_CACHE = 0, 2018286441Srpaulo IWM_NVM_ACCESS_TARGET_OTP = 1, 2019286441Srpaulo IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2020286441Srpaulo}; 2021286441Srpaulo 2022286441Srpaulo/* Section types for IWM_NVM_ACCESS_CMD */ 2023286441Srpauloenum { 2024330165Seadler IWM_NVM_SECTION_TYPE_SW = 1, 2025330165Seadler IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2026330165Seadler IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2027330165Seadler IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2028330165Seadler IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2029330165Seadler IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2030330165Seadler IWM_NVM_MAX_NUM_SECTIONS = 13, 2031286441Srpaulo}; 2032286441Srpaulo 2033286441Srpaulo/** 2034286441Srpaulo * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2035286441Srpaulo * @op_code: 0 - read, 1 - write 2036286441Srpaulo * @target: IWM_NVM_ACCESS_TARGET_* 2037286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 2038286441Srpaulo * @offset: offset in bytes into the section 2039286441Srpaulo * @length: in bytes, to read/write 2040286441Srpaulo * @data: if write operation, the data to write. On read its empty 2041286441Srpaulo */ 2042286441Srpaulostruct iwm_nvm_access_cmd { 2043286441Srpaulo uint8_t op_code; 2044286441Srpaulo uint8_t target; 2045286441Srpaulo uint16_t type; 2046286441Srpaulo uint16_t offset; 2047286441Srpaulo uint16_t length; 2048286441Srpaulo uint8_t data[]; 2049286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2050286441Srpaulo 2051330192Seadler#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2052330192Seadler 2053330192Seadler/* 2054330192Seadler * struct iwm_fw_paging_cmd - paging layout 2055330192Seadler * 2056330192Seadler * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2057330192Seadler * 2058330192Seadler * Send to FW the paging layout in the driver. 2059330192Seadler * 2060330192Seadler * @flags: various flags for the command 2061330192Seadler * @block_size: the block size in powers of 2 2062330192Seadler * @block_num: number of blocks specified in the command. 2063330192Seadler * @device_phy_addr: virtual addresses from device side 2064330192Seadler*/ 2065330192Seadlerstruct iwm_fw_paging_cmd { 2066330192Seadler uint32_t flags; 2067330192Seadler uint32_t block_size; 2068330192Seadler uint32_t block_num; 2069330192Seadler uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2070330192Seadler} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2071330192Seadler 2072330192Seadler/* 2073330192Seadler * Fw items ID's 2074330192Seadler * 2075330192Seadler * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2076330192Seadler * download 2077330192Seadler */ 2078330192Seadlerenum iwm_fw_item_id { 2079330192Seadler IWM_FW_ITEM_ID_PAGING = 3, 2080330192Seadler}; 2081330192Seadler 2082330192Seadler/* 2083330192Seadler * struct iwm_fw_get_item_cmd - get an item from the fw 2084330192Seadler */ 2085330192Seadlerstruct iwm_fw_get_item_cmd { 2086330192Seadler uint32_t item_id; 2087330192Seadler} __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2088330192Seadler 2089286441Srpaulo/** 2090286441Srpaulo * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2091286441Srpaulo * @offset: offset in bytes into the section 2092286441Srpaulo * @length: in bytes, either how much was written or read 2093286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 2094286441Srpaulo * @status: 0 for success, fail otherwise 2095286441Srpaulo * @data: if read operation, the data returned. Empty on write. 2096286441Srpaulo */ 2097286441Srpaulostruct iwm_nvm_access_resp { 2098286441Srpaulo uint16_t offset; 2099286441Srpaulo uint16_t length; 2100286441Srpaulo uint16_t type; 2101286441Srpaulo uint16_t status; 2102286441Srpaulo uint8_t data[]; 2103286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2104286441Srpaulo 2105286441Srpaulo/* IWM_MVM_ALIVE 0x1 */ 2106286441Srpaulo 2107286441Srpaulo/* alive response is_valid values */ 2108286441Srpaulo#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2109286441Srpaulo#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2110286441Srpaulo 2111286441Srpaulo/* alive response ver_type values */ 2112286441Srpauloenum { 2113286441Srpaulo IWM_FW_TYPE_HW = 0, 2114286441Srpaulo IWM_FW_TYPE_PROT = 1, 2115286441Srpaulo IWM_FW_TYPE_AP = 2, 2116286441Srpaulo IWM_FW_TYPE_WOWLAN = 3, 2117286441Srpaulo IWM_FW_TYPE_TIMING = 4, 2118286441Srpaulo IWM_FW_TYPE_WIPAN = 5 2119286441Srpaulo}; 2120286441Srpaulo 2121286441Srpaulo/* alive response ver_subtype values */ 2122286441Srpauloenum { 2123286441Srpaulo IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2124286441Srpaulo IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2125286441Srpaulo IWM_FW_SUBTYPE_REDUCED = 2, 2126286441Srpaulo IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2127286441Srpaulo IWM_FW_SUBTYPE_WOWLAN = 4, 2128286441Srpaulo IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2129286441Srpaulo IWM_FW_SUBTYPE_WIPAN = 6, 2130286441Srpaulo IWM_FW_SUBTYPE_INITIALIZE = 9 2131286441Srpaulo}; 2132286441Srpaulo 2133286441Srpaulo#define IWM_ALIVE_STATUS_ERR 0xDEAD 2134286441Srpaulo#define IWM_ALIVE_STATUS_OK 0xCAFE 2135286441Srpaulo 2136286441Srpaulo#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2137286441Srpaulo 2138330183Seadlerstruct iwm_mvm_alive_resp_ver1 { 2139286441Srpaulo uint16_t status; 2140286441Srpaulo uint16_t flags; 2141286441Srpaulo uint8_t ucode_minor; 2142286441Srpaulo uint8_t ucode_major; 2143286441Srpaulo uint16_t id; 2144286441Srpaulo uint8_t api_minor; 2145286441Srpaulo uint8_t api_major; 2146286441Srpaulo uint8_t ver_subtype; 2147286441Srpaulo uint8_t ver_type; 2148286441Srpaulo uint8_t mac; 2149286441Srpaulo uint8_t opt; 2150286441Srpaulo uint16_t reserved2; 2151286441Srpaulo uint32_t timestamp; 2152286441Srpaulo uint32_t error_event_table_ptr; /* SRAM address for error log */ 2153286441Srpaulo uint32_t log_event_table_ptr; /* SRAM address for event log */ 2154286441Srpaulo uint32_t cpu_register_ptr; 2155286441Srpaulo uint32_t dbgm_config_ptr; 2156286441Srpaulo uint32_t alive_counter_ptr; 2157286441Srpaulo uint32_t scd_base_ptr; /* SRAM address for SCD */ 2158286441Srpaulo} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2159286441Srpaulo 2160330183Seadlerstruct iwm_mvm_alive_resp_ver2 { 2161303628Ssbruno uint16_t status; 2162303628Ssbruno uint16_t flags; 2163303628Ssbruno uint8_t ucode_minor; 2164303628Ssbruno uint8_t ucode_major; 2165303628Ssbruno uint16_t id; 2166303628Ssbruno uint8_t api_minor; 2167303628Ssbruno uint8_t api_major; 2168303628Ssbruno uint8_t ver_subtype; 2169303628Ssbruno uint8_t ver_type; 2170303628Ssbruno uint8_t mac; 2171303628Ssbruno uint8_t opt; 2172303628Ssbruno uint16_t reserved2; 2173303628Ssbruno uint32_t timestamp; 2174303628Ssbruno uint32_t error_event_table_ptr; /* SRAM address for error log */ 2175303628Ssbruno uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2176303628Ssbruno uint32_t cpu_register_ptr; 2177303628Ssbruno uint32_t dbgm_config_ptr; 2178303628Ssbruno uint32_t alive_counter_ptr; 2179303628Ssbruno uint32_t scd_base_ptr; /* SRAM address for SCD */ 2180303628Ssbruno uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2181303628Ssbruno uint32_t st_fwrd_size; 2182330183Seadler uint8_t umac_minor; /* UMAC version: minor */ 2183330183Seadler uint8_t umac_major; /* UMAC version: major */ 2184330183Seadler uint16_t umac_id; /* UMAC version: id */ 2185330183Seadler uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2186303628Ssbruno uint32_t dbg_print_buff_addr; 2187303628Ssbruno} __packed; /* ALIVE_RES_API_S_VER_2 */ 2188303628Ssbruno 2189330183Seadlerstruct iwm_mvm_alive_resp { 2190303628Ssbruno uint16_t status; 2191303628Ssbruno uint16_t flags; 2192303628Ssbruno uint32_t ucode_minor; 2193303628Ssbruno uint32_t ucode_major; 2194303628Ssbruno uint8_t ver_subtype; 2195303628Ssbruno uint8_t ver_type; 2196303628Ssbruno uint8_t mac; 2197303628Ssbruno uint8_t opt; 2198303628Ssbruno uint32_t timestamp; 2199303628Ssbruno uint32_t error_event_table_ptr; /* SRAM address for error log */ 2200303628Ssbruno uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2201303628Ssbruno uint32_t cpu_register_ptr; 2202303628Ssbruno uint32_t dbgm_config_ptr; 2203303628Ssbruno uint32_t alive_counter_ptr; 2204303628Ssbruno uint32_t scd_base_ptr; /* SRAM address for SCD */ 2205303628Ssbruno uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2206303628Ssbruno uint32_t st_fwrd_size; 2207303628Ssbruno uint32_t umac_minor; /* UMAC version: minor */ 2208303628Ssbruno uint32_t umac_major; /* UMAC version: major */ 2209330183Seadler uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2210303628Ssbruno uint32_t dbg_print_buff_addr; 2211303628Ssbruno} __packed; /* ALIVE_RES_API_S_VER_3 */ 2212303628Ssbruno 2213286441Srpaulo/* Error response/notification */ 2214286441Srpauloenum { 2215286441Srpaulo IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2216286441Srpaulo IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2217286441Srpaulo IWM_FW_ERR_SERVICE = 0x2, 2218286441Srpaulo IWM_FW_ERR_ARC_MEMORY = 0x3, 2219286441Srpaulo IWM_FW_ERR_ARC_CODE = 0x4, 2220286441Srpaulo IWM_FW_ERR_WATCH_DOG = 0x5, 2221286441Srpaulo IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2222286441Srpaulo IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2223286441Srpaulo IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2224286441Srpaulo IWM_FW_ERR_UNEXPECTED = 0xFE, 2225286441Srpaulo IWM_FW_ERR_FATAL = 0xFF 2226286441Srpaulo}; 2227286441Srpaulo 2228286441Srpaulo/** 2229286441Srpaulo * struct iwm_error_resp - FW error indication 2230286441Srpaulo * ( IWM_REPLY_ERROR = 0x2 ) 2231286441Srpaulo * @error_type: one of IWM_FW_ERR_* 2232298955Spfg * @cmd_id: the command ID for which the error occurred 2233286441Srpaulo * @bad_cmd_seq_num: sequence number of the erroneous command 2234286441Srpaulo * @error_service: which service created the error, applicable only if 2235286441Srpaulo * error_type = 2, otherwise 0 2236286441Srpaulo * @timestamp: TSF in usecs. 2237286441Srpaulo */ 2238286441Srpaulostruct iwm_error_resp { 2239286441Srpaulo uint32_t error_type; 2240286441Srpaulo uint8_t cmd_id; 2241286441Srpaulo uint8_t reserved1; 2242286441Srpaulo uint16_t bad_cmd_seq_num; 2243286441Srpaulo uint32_t error_service; 2244286441Srpaulo uint64_t timestamp; 2245286441Srpaulo} __packed; 2246286441Srpaulo 2247286441Srpaulo 2248286441Srpaulo/* Common PHY, MAC and Bindings definitions */ 2249286441Srpaulo 2250286441Srpaulo#define IWM_MAX_MACS_IN_BINDING (3) 2251286441Srpaulo#define IWM_MAX_BINDINGS (4) 2252286441Srpaulo#define IWM_AUX_BINDING_INDEX (3) 2253286441Srpaulo#define IWM_MAX_PHYS (4) 2254286441Srpaulo 2255286441Srpaulo/* Used to extract ID and color from the context dword */ 2256286441Srpaulo#define IWM_FW_CTXT_ID_POS (0) 2257286441Srpaulo#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2258286441Srpaulo#define IWM_FW_CTXT_COLOR_POS (8) 2259286441Srpaulo#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2260286441Srpaulo#define IWM_FW_CTXT_INVALID (0xffffffff) 2261286441Srpaulo 2262286441Srpaulo#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2263286441Srpaulo (_color << IWM_FW_CTXT_COLOR_POS)) 2264286441Srpaulo 2265286441Srpaulo/* Possible actions on PHYs, MACs and Bindings */ 2266286441Srpauloenum { 2267286441Srpaulo IWM_FW_CTXT_ACTION_STUB = 0, 2268286441Srpaulo IWM_FW_CTXT_ACTION_ADD, 2269286441Srpaulo IWM_FW_CTXT_ACTION_MODIFY, 2270286441Srpaulo IWM_FW_CTXT_ACTION_REMOVE, 2271286441Srpaulo IWM_FW_CTXT_ACTION_NUM 2272286441Srpaulo}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2273286441Srpaulo 2274286441Srpaulo/* Time Events */ 2275286441Srpaulo 2276286441Srpaulo/* Time Event types, according to MAC type */ 2277286441Srpauloenum iwm_time_event_type { 2278286441Srpaulo /* BSS Station Events */ 2279286441Srpaulo IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2280286441Srpaulo IWM_TE_BSS_STA_ASSOC, 2281286441Srpaulo IWM_TE_BSS_EAP_DHCP_PROT, 2282286441Srpaulo IWM_TE_BSS_QUIET_PERIOD, 2283286441Srpaulo 2284286441Srpaulo /* P2P Device Events */ 2285286441Srpaulo IWM_TE_P2P_DEVICE_DISCOVERABLE, 2286286441Srpaulo IWM_TE_P2P_DEVICE_LISTEN, 2287286441Srpaulo IWM_TE_P2P_DEVICE_ACTION_SCAN, 2288286441Srpaulo IWM_TE_P2P_DEVICE_FULL_SCAN, 2289286441Srpaulo 2290286441Srpaulo /* P2P Client Events */ 2291286441Srpaulo IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2292286441Srpaulo IWM_TE_P2P_CLIENT_ASSOC, 2293286441Srpaulo IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2294286441Srpaulo 2295286441Srpaulo /* P2P GO Events */ 2296286441Srpaulo IWM_TE_P2P_GO_ASSOC_PROT, 2297286441Srpaulo IWM_TE_P2P_GO_REPETITIVE_NOA, 2298286441Srpaulo IWM_TE_P2P_GO_CT_WINDOW, 2299286441Srpaulo 2300286441Srpaulo /* WiDi Sync Events */ 2301286441Srpaulo IWM_TE_WIDI_TX_SYNC, 2302286441Srpaulo 2303286441Srpaulo IWM_TE_MAX 2304286441Srpaulo}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2305286441Srpaulo 2306286441Srpaulo 2307286441Srpaulo 2308286441Srpaulo/* Time event - defines for command API v1 */ 2309286441Srpaulo 2310286441Srpaulo/* 2311286441Srpaulo * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2312286441Srpaulo * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2313286441Srpaulo * the first fragment is scheduled. 2314286441Srpaulo * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2315286441Srpaulo * the first 2 fragments are scheduled. 2316286441Srpaulo * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2317286441Srpaulo * number of fragments are valid. 2318286441Srpaulo * 2319286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2320286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2321286441Srpaulo * scheduled. 2322286441Srpaulo */ 2323286441Srpauloenum { 2324286441Srpaulo IWM_TE_V1_FRAG_NONE = 0, 2325286441Srpaulo IWM_TE_V1_FRAG_SINGLE = 1, 2326286441Srpaulo IWM_TE_V1_FRAG_DUAL = 2, 2327286441Srpaulo IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2328286441Srpaulo}; 2329286441Srpaulo 2330286441Srpaulo/* If a Time Event can be fragmented, this is the max number of fragments */ 2331286441Srpaulo#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2332286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2333286441Srpaulo#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2334286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2335286441Srpaulo#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2336286441Srpaulo 2337286441Srpaulo/* Time Event dependencies: none, on another TE, or in a specific time */ 2338286441Srpauloenum { 2339286441Srpaulo IWM_TE_V1_INDEPENDENT = 0, 2340286441Srpaulo IWM_TE_V1_DEP_OTHER = (1 << 0), 2341286441Srpaulo IWM_TE_V1_DEP_TSF = (1 << 1), 2342286441Srpaulo IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2343286441Srpaulo}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2344286441Srpaulo 2345286441Srpaulo/* 2346286441Srpaulo * @IWM_TE_V1_NOTIF_NONE: no notifications 2347286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2348286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2349286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2350286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2351286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2352286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2353286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2354286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2355286441Srpaulo * 2356286441Srpaulo * Supported Time event notifications configuration. 2357286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2358286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2359286441Srpaulo * notification the status is always success. There is no start/end fragment 2360286441Srpaulo * notification for monolithic events. 2361286441Srpaulo */ 2362286441Srpauloenum { 2363286441Srpaulo IWM_TE_V1_NOTIF_NONE = 0, 2364286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2365286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2366286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2367286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2368286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2369286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2370286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2371286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2372303628Ssbruno IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2373286441Srpaulo}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2374286441Srpaulo 2375330195Seadler/* Time event - defines for command API */ 2376286441Srpaulo 2377286441Srpaulo/* 2378286441Srpaulo * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2379286441Srpaulo * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2380286441Srpaulo * the first fragment is scheduled. 2381286441Srpaulo * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2382286441Srpaulo * the first 2 fragments are scheduled. 2383286441Srpaulo * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2384286441Srpaulo * number of fragments are valid. 2385286441Srpaulo * 2386286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2387286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2388286441Srpaulo * scheduled. 2389286441Srpaulo */ 2390286441Srpauloenum { 2391286441Srpaulo IWM_TE_V2_FRAG_NONE = 0, 2392286441Srpaulo IWM_TE_V2_FRAG_SINGLE = 1, 2393286441Srpaulo IWM_TE_V2_FRAG_DUAL = 2, 2394286441Srpaulo IWM_TE_V2_FRAG_MAX = 0xfe, 2395286441Srpaulo IWM_TE_V2_FRAG_ENDLESS = 0xff 2396286441Srpaulo}; 2397286441Srpaulo 2398286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2399286441Srpaulo#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2400286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2401286441Srpaulo#define IWM_TE_V2_REPEAT_MAX 0xfe 2402286441Srpaulo 2403286441Srpaulo#define IWM_TE_V2_PLACEMENT_POS 12 2404286441Srpaulo#define IWM_TE_V2_ABSENCE_POS 15 2405286441Srpaulo 2406330195Seadler/* Time event policy values 2407286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2408286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2409286441Srpaulo * notification the status is always success. There is no start/end fragment 2410286441Srpaulo * notification for monolithic events. 2411286441Srpaulo * 2412286441Srpaulo * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2413286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2414286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2415286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2416286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2417286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2418286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2419286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2420286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2421286441Srpaulo * @IWM_TE_V2_DEP_OTHER: depends on another time event 2422286441Srpaulo * @IWM_TE_V2_DEP_TSF: depends on a specific time 2423286441Srpaulo * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2424286441Srpaulo * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2425286441Srpaulo */ 2426286441Srpauloenum { 2427286441Srpaulo IWM_TE_V2_DEFAULT_POLICY = 0x0, 2428286441Srpaulo 2429286441Srpaulo /* notifications (event start/stop, fragment start/stop) */ 2430286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2431286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2432286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2433286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2434286441Srpaulo 2435286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2436286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2437286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2438286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2439286441Srpaulo 2440286441Srpaulo IWM_TE_V2_NOTIF_MSK = 0xff, 2441286441Srpaulo 2442286441Srpaulo /* placement characteristics */ 2443286441Srpaulo IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2444286441Srpaulo IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2445286441Srpaulo IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2446286441Srpaulo 2447286441Srpaulo /* are we present or absent during the Time Event. */ 2448286441Srpaulo IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2449286441Srpaulo}; 2450286441Srpaulo 2451286441Srpaulo/** 2452330195Seadler * struct iwm_time_event_cmd_api - configuring Time Events 2453286441Srpaulo * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2454286441Srpaulo * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2455286441Srpaulo * ( IWM_TIME_EVENT_CMD = 0x29 ) 2456286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2457286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2458286441Srpaulo * @id: this field has two meanings, depending on the action: 2459286441Srpaulo * If the action is ADD, then it means the type of event to add. 2460286441Srpaulo * For all other actions it is the unique event ID assigned when the 2461286441Srpaulo * event was added by the FW. 2462286441Srpaulo * @apply_time: When to start the Time Event (in GP2) 2463286441Srpaulo * @max_delay: maximum delay to event's start (apply time), in TU 2464286441Srpaulo * @depends_on: the unique ID of the event we depend on (if any) 2465286441Srpaulo * @interval: interval between repetitions, in TU 2466286441Srpaulo * @duration: duration of event in TU 2467286441Srpaulo * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2468286441Srpaulo * @max_frags: maximal number of fragments the Time Event can be divided to 2469286441Srpaulo * @policy: defines whether uCode shall notify the host or other uCode modules 2470286441Srpaulo * on event and/or fragment start and/or end 2471286441Srpaulo * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2472286441Srpaulo * IWM_TE_EVENT_SOCIOPATHIC 2473286441Srpaulo * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2474286441Srpaulo */ 2475330195Seadlerstruct iwm_time_event_cmd { 2476286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2477286441Srpaulo uint32_t id_and_color; 2478286441Srpaulo uint32_t action; 2479286441Srpaulo uint32_t id; 2480286441Srpaulo /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2481286441Srpaulo uint32_t apply_time; 2482286441Srpaulo uint32_t max_delay; 2483286441Srpaulo uint32_t depends_on; 2484286441Srpaulo uint32_t interval; 2485286441Srpaulo uint32_t duration; 2486286441Srpaulo uint8_t repeat; 2487286441Srpaulo uint8_t max_frags; 2488286441Srpaulo uint16_t policy; 2489286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2490286441Srpaulo 2491286441Srpaulo/** 2492286441Srpaulo * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2493286441Srpaulo * @status: bit 0 indicates success, all others specify errors 2494286441Srpaulo * @id: the Time Event type 2495286441Srpaulo * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2496286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2497286441Srpaulo */ 2498286441Srpaulostruct iwm_time_event_resp { 2499286441Srpaulo uint32_t status; 2500286441Srpaulo uint32_t id; 2501286441Srpaulo uint32_t unique_id; 2502286441Srpaulo uint32_t id_and_color; 2503286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2504286441Srpaulo 2505286441Srpaulo/** 2506286441Srpaulo * struct iwm_time_event_notif - notifications of time event start/stop 2507286441Srpaulo * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2508286441Srpaulo * @timestamp: action timestamp in GP2 2509286441Srpaulo * @session_id: session's unique id 2510286441Srpaulo * @unique_id: unique id of the Time Event itself 2511286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2512286441Srpaulo * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2513286441Srpaulo * @status: true if scheduled, false otherwise (not executed) 2514286441Srpaulo */ 2515286441Srpaulostruct iwm_time_event_notif { 2516286441Srpaulo uint32_t timestamp; 2517286441Srpaulo uint32_t session_id; 2518286441Srpaulo uint32_t unique_id; 2519286441Srpaulo uint32_t id_and_color; 2520286441Srpaulo uint32_t action; 2521286441Srpaulo uint32_t status; 2522286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2523286441Srpaulo 2524286441Srpaulo 2525286441Srpaulo/* Bindings and Time Quota */ 2526286441Srpaulo 2527286441Srpaulo/** 2528286441Srpaulo * struct iwm_binding_cmd - configuring bindings 2529286441Srpaulo * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2530286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2531286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2532286441Srpaulo * @macs: array of MAC id and colors which belong to the binding 2533286441Srpaulo * @phy: PHY id and color which belongs to the binding 2534286441Srpaulo */ 2535286441Srpaulostruct iwm_binding_cmd { 2536286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2537286441Srpaulo uint32_t id_and_color; 2538286441Srpaulo uint32_t action; 2539286441Srpaulo /* IWM_BINDING_DATA_API_S_VER_1 */ 2540286441Srpaulo uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2541286441Srpaulo uint32_t phy; 2542286441Srpaulo} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2543286441Srpaulo 2544286441Srpaulo/* The maximal number of fragments in the FW's schedule session */ 2545286441Srpaulo#define IWM_MVM_MAX_QUOTA 128 2546286441Srpaulo 2547286441Srpaulo/** 2548286441Srpaulo * struct iwm_time_quota_data - configuration of time quota per binding 2549286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2550286441Srpaulo * @quota: absolute time quota in TU. The scheduler will try to divide the 2551286441Srpaulo * remainig quota (after Time Events) according to this quota. 2552286441Srpaulo * @max_duration: max uninterrupted context duration in TU 2553286441Srpaulo */ 2554286441Srpaulostruct iwm_time_quota_data { 2555286441Srpaulo uint32_t id_and_color; 2556286441Srpaulo uint32_t quota; 2557286441Srpaulo uint32_t max_duration; 2558286441Srpaulo} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2559286441Srpaulo 2560286441Srpaulo/** 2561286441Srpaulo * struct iwm_time_quota_cmd - configuration of time quota between bindings 2562286441Srpaulo * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2563286441Srpaulo * @quotas: allocations per binding 2564286441Srpaulo */ 2565286441Srpaulostruct iwm_time_quota_cmd { 2566286441Srpaulo struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2567286441Srpaulo} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2568286441Srpaulo 2569286441Srpaulo 2570286441Srpaulo/* PHY context */ 2571286441Srpaulo 2572286441Srpaulo/* Supported bands */ 2573286441Srpaulo#define IWM_PHY_BAND_5 (0) 2574286441Srpaulo#define IWM_PHY_BAND_24 (1) 2575286441Srpaulo 2576286441Srpaulo/* Supported channel width, vary if there is VHT support */ 2577286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2578286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2579286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2580286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2581286441Srpaulo 2582286441Srpaulo/* 2583286441Srpaulo * Control channel position: 2584286441Srpaulo * For legacy set bit means upper channel, otherwise lower. 2585286441Srpaulo * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2586286441Srpaulo * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2587286441Srpaulo * center_freq 2588286441Srpaulo * | 2589286441Srpaulo * 40Mhz |_______|_______| 2590286441Srpaulo * 80Mhz |_______|_______|_______|_______| 2591286441Srpaulo * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2592286441Srpaulo * code 011 010 001 000 | 100 101 110 111 2593286441Srpaulo */ 2594286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2595286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2596286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2597286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2598286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2599286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2600286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2601286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2602286441Srpaulo 2603286441Srpaulo/* 2604286441Srpaulo * @band: IWM_PHY_BAND_* 2605286441Srpaulo * @channel: channel number 2606286441Srpaulo * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2607286441Srpaulo * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2608286441Srpaulo */ 2609286441Srpaulostruct iwm_fw_channel_info { 2610286441Srpaulo uint8_t band; 2611286441Srpaulo uint8_t channel; 2612286441Srpaulo uint8_t width; 2613286441Srpaulo uint8_t ctrl_pos; 2614286441Srpaulo} __packed; 2615286441Srpaulo 2616286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2617286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2618286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2619286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2620286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2621286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2622286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2623286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2624286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2625286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2626286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2627286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2628286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2629286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2630286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2631286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2632286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2633286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2634286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2635286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2636286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2637286441Srpaulo 2638286441Srpaulo/* TODO: fix the value, make it depend on firmware at runtime? */ 2639286441Srpaulo#define IWM_NUM_PHY_CTX 3 2640286441Srpaulo 2641286441Srpaulo/* TODO: complete missing documentation */ 2642286441Srpaulo/** 2643286441Srpaulo * struct iwm_phy_context_cmd - config of the PHY context 2644286441Srpaulo * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2645286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2646286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2647286441Srpaulo * @apply_time: 0 means immediate apply and context switch. 2648286441Srpaulo * other value means apply new params after X usecs 2649286441Srpaulo * @tx_param_color: ??? 2650286441Srpaulo * @channel_info: 2651286441Srpaulo * @txchain_info: ??? 2652286441Srpaulo * @rxchain_info: ??? 2653286441Srpaulo * @acquisition_data: ??? 2654286441Srpaulo * @dsp_cfg_flags: set to 0 2655286441Srpaulo */ 2656286441Srpaulostruct iwm_phy_context_cmd { 2657286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2658286441Srpaulo uint32_t id_and_color; 2659286441Srpaulo uint32_t action; 2660286441Srpaulo /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2661286441Srpaulo uint32_t apply_time; 2662286441Srpaulo uint32_t tx_param_color; 2663286441Srpaulo struct iwm_fw_channel_info ci; 2664286441Srpaulo uint32_t txchain_info; 2665286441Srpaulo uint32_t rxchain_info; 2666286441Srpaulo uint32_t acquisition_data; 2667286441Srpaulo uint32_t dsp_cfg_flags; 2668286441Srpaulo} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2669286441Srpaulo 2670286441Srpaulo#define IWM_RX_INFO_PHY_CNT 8 2671286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2672286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2673286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2674286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2675286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2676286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2677286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2678286441Srpaulo 2679286441Srpaulo#define IWM_RX_INFO_AGC_IDX 1 2680286441Srpaulo#define IWM_RX_INFO_RSSI_AB_IDX 2 2681286441Srpaulo#define IWM_OFDM_AGC_A_MSK 0x0000007f 2682286441Srpaulo#define IWM_OFDM_AGC_A_POS 0 2683286441Srpaulo#define IWM_OFDM_AGC_B_MSK 0x00003f80 2684286441Srpaulo#define IWM_OFDM_AGC_B_POS 7 2685286441Srpaulo#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2686286441Srpaulo#define IWM_OFDM_AGC_CODE_POS 20 2687286441Srpaulo#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2688286441Srpaulo#define IWM_OFDM_RSSI_A_POS 0 2689286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2690286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2691286441Srpaulo#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2692286441Srpaulo#define IWM_OFDM_RSSI_B_POS 16 2693286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2694286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2695286441Srpaulo 2696286441Srpaulo/** 2697286441Srpaulo * struct iwm_rx_phy_info - phy info 2698286441Srpaulo * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2699286441Srpaulo * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2700286441Srpaulo * @cfg_phy_cnt: configurable DSP phy data byte count 2701286441Srpaulo * @stat_id: configurable DSP phy data set ID 2702286441Srpaulo * @reserved1: 2703286441Srpaulo * @system_timestamp: GP2 at on air rise 2704286441Srpaulo * @timestamp: TSF at on air rise 2705286441Srpaulo * @beacon_time_stamp: beacon at on-air rise 2706286441Srpaulo * @phy_flags: general phy flags: band, modulation, ... 2707286441Srpaulo * @channel: channel number 2708286441Srpaulo * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2709286441Srpaulo * @rate_n_flags: IWM_RATE_MCS_* 2710286441Srpaulo * @byte_count: frame's byte-count 2711286441Srpaulo * @frame_time: frame's time on the air, based on byte count and frame rate 2712286441Srpaulo * calculation 2713286441Srpaulo * @mac_active_msk: what MACs were active when the frame was received 2714286441Srpaulo * 2715286441Srpaulo * Before each Rx, the device sends this data. It contains PHY information 2716286441Srpaulo * about the reception of the packet. 2717286441Srpaulo */ 2718286441Srpaulostruct iwm_rx_phy_info { 2719286441Srpaulo uint8_t non_cfg_phy_cnt; 2720286441Srpaulo uint8_t cfg_phy_cnt; 2721286441Srpaulo uint8_t stat_id; 2722286441Srpaulo uint8_t reserved1; 2723286441Srpaulo uint32_t system_timestamp; 2724286441Srpaulo uint64_t timestamp; 2725286441Srpaulo uint32_t beacon_time_stamp; 2726286441Srpaulo uint16_t phy_flags; 2727286441Srpaulo#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2728286441Srpaulo uint16_t channel; 2729286441Srpaulo uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2730286441Srpaulo uint8_t rate; 2731286441Srpaulo uint8_t rflags; 2732286441Srpaulo uint16_t xrflags; 2733286441Srpaulo uint32_t byte_count; 2734286441Srpaulo uint16_t mac_active_msk; 2735286441Srpaulo uint16_t frame_time; 2736286441Srpaulo} __packed; 2737286441Srpaulo 2738286441Srpaulostruct iwm_rx_mpdu_res_start { 2739286441Srpaulo uint16_t byte_count; 2740286441Srpaulo uint16_t reserved; 2741286441Srpaulo} __packed; 2742286441Srpaulo 2743286441Srpaulo/** 2744286441Srpaulo * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2745286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2746286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2747286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2748286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2749286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2750286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2751286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2752286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2753286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2754286441Srpaulo */ 2755286441Srpauloenum iwm_rx_phy_flags { 2756286441Srpaulo IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2757286441Srpaulo IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2758286441Srpaulo IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2759286441Srpaulo IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2760286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2761286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2762286441Srpaulo IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2763286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2764286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2765286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2766286441Srpaulo}; 2767286441Srpaulo 2768286441Srpaulo/** 2769286441Srpaulo * enum iwm_mvm_rx_status - written by fw for each Rx packet 2770286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2771286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2772286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2773286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2774286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2775286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2776286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2777286441Srpaulo * in the driver. 2778286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2779286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2780286441Srpaulo * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2781286441Srpaulo * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2782286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2783286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2784286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2785286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2786286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2787286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2788286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2789286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2790286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2791286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2792286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2793286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2794286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2795286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2796286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2797286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2798286441Srpaulo * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2799286441Srpaulo */ 2800286441Srpauloenum iwm_mvm_rx_status { 2801286441Srpaulo IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2802286441Srpaulo IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2803286441Srpaulo IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2804286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2805286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2806286441Srpaulo IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2807286441Srpaulo IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2808286441Srpaulo IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2809286441Srpaulo IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2810286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2811286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2812286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2813286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2814286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2815286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2816286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2817286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2818286441Srpaulo IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2819286441Srpaulo IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2820286441Srpaulo IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2821286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2822286441Srpaulo IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2823286441Srpaulo IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2824286441Srpaulo IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2825286441Srpaulo IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2826286441Srpaulo IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2827286441Srpaulo IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2828286441Srpaulo}; 2829286441Srpaulo 2830286441Srpaulo/** 2831286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2832286441Srpaulo * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2833286441Srpaulo * @radio_flavor: 2834286441Srpaulo * @radio_step: 2835286441Srpaulo * @radio_dash: 2836286441Srpaulo */ 2837286441Srpaulostruct iwm_radio_version_notif { 2838286441Srpaulo uint32_t radio_flavor; 2839286441Srpaulo uint32_t radio_step; 2840286441Srpaulo uint32_t radio_dash; 2841286441Srpaulo} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2842286441Srpaulo 2843286441Srpauloenum iwm_card_state_flags { 2844286441Srpaulo IWM_CARD_ENABLED = 0x00, 2845286441Srpaulo IWM_HW_CARD_DISABLED = 0x01, 2846286441Srpaulo IWM_SW_CARD_DISABLED = 0x02, 2847286441Srpaulo IWM_CT_KILL_CARD_DISABLED = 0x04, 2848286441Srpaulo IWM_HALT_CARD_DISABLED = 0x08, 2849286441Srpaulo IWM_CARD_DISABLED_MSK = 0x0f, 2850286441Srpaulo IWM_CARD_IS_RX_ON = 0x10, 2851286441Srpaulo}; 2852286441Srpaulo 2853286441Srpaulo/** 2854286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2855286441Srpaulo * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2856286441Srpaulo * @flags: %iwm_card_state_flags 2857286441Srpaulo */ 2858286441Srpaulostruct iwm_card_state_notif { 2859286441Srpaulo uint32_t flags; 2860286441Srpaulo} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2861286441Srpaulo 2862286441Srpaulo/** 2863286441Srpaulo * struct iwm_missed_beacons_notif - information on missed beacons 2864286441Srpaulo * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2865286441Srpaulo * @mac_id: interface ID 2866286441Srpaulo * @consec_missed_beacons_since_last_rx: number of consecutive missed 2867286441Srpaulo * beacons since last RX. 2868286441Srpaulo * @consec_missed_beacons: number of consecutive missed beacons 2869286441Srpaulo * @num_expected_beacons: 2870286441Srpaulo * @num_recvd_beacons: 2871286441Srpaulo */ 2872286441Srpaulostruct iwm_missed_beacons_notif { 2873286441Srpaulo uint32_t mac_id; 2874286441Srpaulo uint32_t consec_missed_beacons_since_last_rx; 2875286441Srpaulo uint32_t consec_missed_beacons; 2876286441Srpaulo uint32_t num_expected_beacons; 2877286441Srpaulo uint32_t num_recvd_beacons; 2878286441Srpaulo} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2879286441Srpaulo 2880286441Srpaulo/** 2881303628Ssbruno * struct iwm_mfuart_load_notif - mfuart image version & status 2882303628Ssbruno * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2883303628Ssbruno * @installed_ver: installed image version 2884303628Ssbruno * @external_ver: external image version 2885303628Ssbruno * @status: MFUART loading status 2886303628Ssbruno * @duration: MFUART loading time 2887303628Ssbruno*/ 2888303628Ssbrunostruct iwm_mfuart_load_notif { 2889303628Ssbruno uint32_t installed_ver; 2890303628Ssbruno uint32_t external_ver; 2891303628Ssbruno uint32_t status; 2892303628Ssbruno uint32_t duration; 2893303628Ssbruno} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2894303628Ssbruno 2895303628Ssbruno/** 2896286441Srpaulo * struct iwm_set_calib_default_cmd - set default value for calibration. 2897286441Srpaulo * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2898286441Srpaulo * @calib_index: the calibration to set value for 2899286441Srpaulo * @length: of data 2900286441Srpaulo * @data: the value to set for the calibration result 2901286441Srpaulo */ 2902286441Srpaulostruct iwm_set_calib_default_cmd { 2903286441Srpaulo uint16_t calib_index; 2904286441Srpaulo uint16_t length; 2905286441Srpaulo uint8_t data[0]; 2906286441Srpaulo} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2907286441Srpaulo 2908286441Srpaulo#define IWM_MAX_PORT_ID_NUM 2 2909286441Srpaulo#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2910286441Srpaulo 2911286441Srpaulo/** 2912286441Srpaulo * struct iwm_mcast_filter_cmd - configure multicast filter. 2913286441Srpaulo * @filter_own: Set 1 to filter out multicast packets sent by station itself 2914286441Srpaulo * @port_id: Multicast MAC addresses array specifier. This is a strange way 2915286441Srpaulo * to identify network interface adopted in host-device IF. 2916286441Srpaulo * It is used by FW as index in array of addresses. This array has 2917286441Srpaulo * IWM_MAX_PORT_ID_NUM members. 2918286441Srpaulo * @count: Number of MAC addresses in the array 2919286441Srpaulo * @pass_all: Set 1 to pass all multicast packets. 2920286441Srpaulo * @bssid: current association BSSID. 2921286441Srpaulo * @addr_list: Place holder for array of MAC addresses. 2922286441Srpaulo * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2923286441Srpaulo */ 2924286441Srpaulostruct iwm_mcast_filter_cmd { 2925286441Srpaulo uint8_t filter_own; 2926286441Srpaulo uint8_t port_id; 2927286441Srpaulo uint8_t count; 2928286441Srpaulo uint8_t pass_all; 2929286441Srpaulo uint8_t bssid[6]; 2930286441Srpaulo uint8_t reserved[2]; 2931286441Srpaulo uint8_t addr_list[0]; 2932286441Srpaulo} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2933286441Srpaulo 2934286441Srpaulostruct iwm_mvm_statistics_dbg { 2935286441Srpaulo uint32_t burst_check; 2936286441Srpaulo uint32_t burst_count; 2937286441Srpaulo uint32_t wait_for_silence_timeout_cnt; 2938286441Srpaulo uint32_t reserved[3]; 2939286441Srpaulo} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2940286441Srpaulo 2941286441Srpaulostruct iwm_mvm_statistics_div { 2942286441Srpaulo uint32_t tx_on_a; 2943286441Srpaulo uint32_t tx_on_b; 2944286441Srpaulo uint32_t exec_time; 2945286441Srpaulo uint32_t probe_time; 2946286441Srpaulo uint32_t rssi_ant; 2947286441Srpaulo uint32_t reserved2; 2948286441Srpaulo} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2949286441Srpaulo 2950286441Srpaulostruct iwm_mvm_statistics_general_common { 2951286441Srpaulo uint32_t temperature; /* radio temperature */ 2952286441Srpaulo uint32_t temperature_m; /* radio voltage */ 2953286441Srpaulo struct iwm_mvm_statistics_dbg dbg; 2954286441Srpaulo uint32_t sleep_time; 2955286441Srpaulo uint32_t slots_out; 2956286441Srpaulo uint32_t slots_idle; 2957286441Srpaulo uint32_t ttl_timestamp; 2958286441Srpaulo struct iwm_mvm_statistics_div div; 2959286441Srpaulo uint32_t rx_enable_counter; 2960286441Srpaulo /* 2961286441Srpaulo * num_of_sos_states: 2962286441Srpaulo * count the number of times we have to re-tune 2963286441Srpaulo * in order to get out of bad PHY status 2964286441Srpaulo */ 2965286441Srpaulo uint32_t num_of_sos_states; 2966286441Srpaulo} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 2967286441Srpaulo 2968286441Srpaulostruct iwm_mvm_statistics_rx_non_phy { 2969286441Srpaulo uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2970286441Srpaulo uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2971286441Srpaulo uint32_t non_bssid_frames; /* number of frames with BSSID that 2972286441Srpaulo * doesn't belong to the STA BSSID */ 2973286441Srpaulo uint32_t filtered_frames; /* count frames that were dumped in the 2974286441Srpaulo * filtering process */ 2975286441Srpaulo uint32_t non_channel_beacons; /* beacons with our bss id but not on 2976286441Srpaulo * our serving channel */ 2977286441Srpaulo uint32_t channel_beacons; /* beacons with our bss id and in our 2978286441Srpaulo * serving channel */ 2979286441Srpaulo uint32_t num_missed_bcon; /* number of missed beacons */ 2980286441Srpaulo uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2981286441Srpaulo * ADC was in saturation */ 2982286441Srpaulo uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2983286441Srpaulo * for INA */ 2984286441Srpaulo uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2985286441Srpaulo uint32_t interference_data_flag; /* flag for interference data 2986286441Srpaulo * availability. 1 when data is 2987286441Srpaulo * available. */ 2988286441Srpaulo uint32_t channel_load; /* counts RX Enable time in uSec */ 2989286441Srpaulo uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2990286441Srpaulo * and CCK) counter */ 2991286441Srpaulo uint32_t beacon_rssi_a; 2992286441Srpaulo uint32_t beacon_rssi_b; 2993286441Srpaulo uint32_t beacon_rssi_c; 2994286441Srpaulo uint32_t beacon_energy_a; 2995286441Srpaulo uint32_t beacon_energy_b; 2996286441Srpaulo uint32_t beacon_energy_c; 2997286441Srpaulo uint32_t num_bt_kills; 2998286441Srpaulo uint32_t mac_id; 2999286441Srpaulo uint32_t directed_data_mpdu; 3000286441Srpaulo} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3001286441Srpaulo 3002286441Srpaulostruct iwm_mvm_statistics_rx_phy { 3003286441Srpaulo uint32_t ina_cnt; 3004286441Srpaulo uint32_t fina_cnt; 3005286441Srpaulo uint32_t plcp_err; 3006286441Srpaulo uint32_t crc32_err; 3007286441Srpaulo uint32_t overrun_err; 3008286441Srpaulo uint32_t early_overrun_err; 3009286441Srpaulo uint32_t crc32_good; 3010286441Srpaulo uint32_t false_alarm_cnt; 3011286441Srpaulo uint32_t fina_sync_err_cnt; 3012286441Srpaulo uint32_t sfd_timeout; 3013286441Srpaulo uint32_t fina_timeout; 3014286441Srpaulo uint32_t unresponded_rts; 3015286441Srpaulo uint32_t rxe_frame_limit_overrun; 3016286441Srpaulo uint32_t sent_ack_cnt; 3017286441Srpaulo uint32_t sent_cts_cnt; 3018286441Srpaulo uint32_t sent_ba_rsp_cnt; 3019286441Srpaulo uint32_t dsp_self_kill; 3020286441Srpaulo uint32_t mh_format_err; 3021286441Srpaulo uint32_t re_acq_main_rssi_sum; 3022286441Srpaulo uint32_t reserved; 3023286441Srpaulo} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3024286441Srpaulo 3025286441Srpaulostruct iwm_mvm_statistics_rx_ht_phy { 3026286441Srpaulo uint32_t plcp_err; 3027286441Srpaulo uint32_t overrun_err; 3028286441Srpaulo uint32_t early_overrun_err; 3029286441Srpaulo uint32_t crc32_good; 3030286441Srpaulo uint32_t crc32_err; 3031286441Srpaulo uint32_t mh_format_err; 3032286441Srpaulo uint32_t agg_crc32_good; 3033286441Srpaulo uint32_t agg_mpdu_cnt; 3034286441Srpaulo uint32_t agg_cnt; 3035286441Srpaulo uint32_t unsupport_mcs; 3036286441Srpaulo} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3037286441Srpaulo 3038286441Srpaulo#define IWM_MAX_CHAINS 3 3039286441Srpaulo 3040286441Srpaulostruct iwm_mvm_statistics_tx_non_phy_agg { 3041286441Srpaulo uint32_t ba_timeout; 3042286441Srpaulo uint32_t ba_reschedule_frames; 3043286441Srpaulo uint32_t scd_query_agg_frame_cnt; 3044286441Srpaulo uint32_t scd_query_no_agg; 3045286441Srpaulo uint32_t scd_query_agg; 3046286441Srpaulo uint32_t scd_query_mismatch; 3047286441Srpaulo uint32_t frame_not_ready; 3048286441Srpaulo uint32_t underrun; 3049286441Srpaulo uint32_t bt_prio_kill; 3050286441Srpaulo uint32_t rx_ba_rsp_cnt; 3051286441Srpaulo int8_t txpower[IWM_MAX_CHAINS]; 3052286441Srpaulo int8_t reserved; 3053286441Srpaulo uint32_t reserved2; 3054286441Srpaulo} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3055286441Srpaulo 3056286441Srpaulostruct iwm_mvm_statistics_tx_channel_width { 3057286441Srpaulo uint32_t ext_cca_narrow_ch20[1]; 3058286441Srpaulo uint32_t ext_cca_narrow_ch40[2]; 3059286441Srpaulo uint32_t ext_cca_narrow_ch80[3]; 3060286441Srpaulo uint32_t ext_cca_narrow_ch160[4]; 3061286441Srpaulo uint32_t last_tx_ch_width_indx; 3062286441Srpaulo uint32_t rx_detected_per_ch_width[4]; 3063286441Srpaulo uint32_t success_per_ch_width[4]; 3064286441Srpaulo uint32_t fail_per_ch_width[4]; 3065286441Srpaulo}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3066286441Srpaulo 3067286441Srpaulostruct iwm_mvm_statistics_tx { 3068286441Srpaulo uint32_t preamble_cnt; 3069286441Srpaulo uint32_t rx_detected_cnt; 3070286441Srpaulo uint32_t bt_prio_defer_cnt; 3071286441Srpaulo uint32_t bt_prio_kill_cnt; 3072286441Srpaulo uint32_t few_bytes_cnt; 3073286441Srpaulo uint32_t cts_timeout; 3074286441Srpaulo uint32_t ack_timeout; 3075286441Srpaulo uint32_t expected_ack_cnt; 3076286441Srpaulo uint32_t actual_ack_cnt; 3077286441Srpaulo uint32_t dump_msdu_cnt; 3078286441Srpaulo uint32_t burst_abort_next_frame_mismatch_cnt; 3079286441Srpaulo uint32_t burst_abort_missing_next_frame_cnt; 3080286441Srpaulo uint32_t cts_timeout_collision; 3081286441Srpaulo uint32_t ack_or_ba_timeout_collision; 3082286441Srpaulo struct iwm_mvm_statistics_tx_non_phy_agg agg; 3083286441Srpaulo struct iwm_mvm_statistics_tx_channel_width channel_width; 3084286441Srpaulo} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3085286441Srpaulo 3086286441Srpaulo 3087286441Srpaulostruct iwm_mvm_statistics_bt_activity { 3088286441Srpaulo uint32_t hi_priority_tx_req_cnt; 3089286441Srpaulo uint32_t hi_priority_tx_denied_cnt; 3090286441Srpaulo uint32_t lo_priority_tx_req_cnt; 3091286441Srpaulo uint32_t lo_priority_tx_denied_cnt; 3092286441Srpaulo uint32_t hi_priority_rx_req_cnt; 3093286441Srpaulo uint32_t hi_priority_rx_denied_cnt; 3094286441Srpaulo uint32_t lo_priority_rx_req_cnt; 3095286441Srpaulo uint32_t lo_priority_rx_denied_cnt; 3096286441Srpaulo} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3097286441Srpaulo 3098286441Srpaulostruct iwm_mvm_statistics_general { 3099286441Srpaulo struct iwm_mvm_statistics_general_common common; 3100286441Srpaulo uint32_t beacon_filtered; 3101286441Srpaulo uint32_t missed_beacons; 3102286441Srpaulo int8_t beacon_filter_average_energy; 3103286441Srpaulo int8_t beacon_filter_reason; 3104286441Srpaulo int8_t beacon_filter_current_energy; 3105286441Srpaulo int8_t beacon_filter_reserved; 3106286441Srpaulo uint32_t beacon_filter_delta_time; 3107286441Srpaulo struct iwm_mvm_statistics_bt_activity bt_activity; 3108286441Srpaulo} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3109286441Srpaulo 3110286441Srpaulostruct iwm_mvm_statistics_rx { 3111286441Srpaulo struct iwm_mvm_statistics_rx_phy ofdm; 3112286441Srpaulo struct iwm_mvm_statistics_rx_phy cck; 3113286441Srpaulo struct iwm_mvm_statistics_rx_non_phy general; 3114286441Srpaulo struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3115286441Srpaulo} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3116286441Srpaulo 3117286441Srpaulo/* 3118286441Srpaulo * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3119286441Srpaulo * 3120286441Srpaulo * By default, uCode issues this notification after receiving a beacon 3121286441Srpaulo * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3122286441Srpaulo * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3123286441Srpaulo * 3124286441Srpaulo * Statistics counters continue to increment beacon after beacon, but are 3125286441Srpaulo * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3126286441Srpaulo * 0x9c with CLEAR_STATS bit set (see above). 3127286441Srpaulo * 3128286441Srpaulo * uCode also issues this notification during scans. uCode clears statistics 3129286441Srpaulo * appropriately so that each notification contains statistics for only the 3130286441Srpaulo * one channel that has just been scanned. 3131286441Srpaulo */ 3132286441Srpaulo 3133286441Srpaulostruct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3134286441Srpaulo uint32_t flag; 3135286441Srpaulo struct iwm_mvm_statistics_rx rx; 3136286441Srpaulo struct iwm_mvm_statistics_tx tx; 3137286441Srpaulo struct iwm_mvm_statistics_general general; 3138286441Srpaulo} __packed; 3139286441Srpaulo 3140286441Srpaulo/*********************************** 3141286441Srpaulo * Smart Fifo API 3142286441Srpaulo ***********************************/ 3143286441Srpaulo/* Smart Fifo state */ 3144286441Srpauloenum iwm_sf_state { 3145286441Srpaulo IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3146286441Srpaulo IWM_SF_FULL_ON, 3147286441Srpaulo IWM_SF_UNINIT, 3148286441Srpaulo IWM_SF_INIT_OFF, 3149286441Srpaulo IWM_SF_HW_NUM_STATES 3150286441Srpaulo}; 3151286441Srpaulo 3152286441Srpaulo/* Smart Fifo possible scenario */ 3153286441Srpauloenum iwm_sf_scenario { 3154286441Srpaulo IWM_SF_SCENARIO_SINGLE_UNICAST, 3155286441Srpaulo IWM_SF_SCENARIO_AGG_UNICAST, 3156286441Srpaulo IWM_SF_SCENARIO_MULTICAST, 3157286441Srpaulo IWM_SF_SCENARIO_BA_RESP, 3158286441Srpaulo IWM_SF_SCENARIO_TX_RESP, 3159286441Srpaulo IWM_SF_NUM_SCENARIO 3160286441Srpaulo}; 3161286441Srpaulo 3162286441Srpaulo#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3163286441Srpaulo#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3164286441Srpaulo 3165286441Srpaulo/* smart FIFO default values */ 3166286441Srpaulo#define IWM_SF_W_MARK_SISO 4096 3167286441Srpaulo#define IWM_SF_W_MARK_MIMO2 8192 3168286441Srpaulo#define IWM_SF_W_MARK_MIMO3 6144 3169286441Srpaulo#define IWM_SF_W_MARK_LEGACY 4096 3170286441Srpaulo#define IWM_SF_W_MARK_SCAN 4096 3171286441Srpaulo 3172303628Ssbruno/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3173303628Ssbruno#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3174303628Ssbruno#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3175303628Ssbruno#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3176303628Ssbruno#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3177330143Seadler#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3178303628Ssbruno#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3179303628Ssbruno#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3180303628Ssbruno#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3181303628Ssbruno#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3182303628Ssbruno#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3183303628Ssbruno 3184286441Srpaulo/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3185286441Srpaulo#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3186286441Srpaulo#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3187286441Srpaulo#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3188286441Srpaulo#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3189286441Srpaulo#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3190286441Srpaulo#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3191286441Srpaulo#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3192286441Srpaulo#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3193286441Srpaulo#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3194286441Srpaulo#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3195286441Srpaulo 3196286441Srpaulo#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3197286441Srpaulo 3198303628Ssbruno#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3199303628Ssbruno 3200286441Srpaulo/** 3201286441Srpaulo * Smart Fifo configuration command. 3202330143Seadler * @state: smart fifo state, types listed in iwm_sf_state. 3203298955Spfg * @watermark: Minimum allowed available free space in RXF for transient state. 3204286441Srpaulo * @long_delay_timeouts: aging and idle timer values for each scenario 3205286441Srpaulo * in long delay state. 3206286441Srpaulo * @full_on_timeouts: timer values for each scenario in full on state. 3207286441Srpaulo */ 3208286441Srpaulostruct iwm_sf_cfg_cmd { 3209330146Seadler uint32_t state; 3210286441Srpaulo uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3211286441Srpaulo uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3212286441Srpaulo uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3213286441Srpaulo} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3214286441Srpaulo 3215286441Srpaulo/* 3216286441Srpaulo * END mvm/fw-api.h 3217286441Srpaulo */ 3218286441Srpaulo 3219286441Srpaulo/* 3220286441Srpaulo * BEGIN mvm/fw-api-mac.h 3221286441Srpaulo */ 3222286441Srpaulo 3223286441Srpaulo/* 3224286441Srpaulo * The first MAC indices (starting from 0) 3225286441Srpaulo * are available to the driver, AUX follows 3226286441Srpaulo */ 3227286441Srpaulo#define IWM_MAC_INDEX_AUX 4 3228286441Srpaulo#define IWM_MAC_INDEX_MIN_DRIVER 0 3229286441Srpaulo#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3230286441Srpaulo 3231286441Srpauloenum iwm_ac { 3232286441Srpaulo IWM_AC_BK, 3233286441Srpaulo IWM_AC_BE, 3234286441Srpaulo IWM_AC_VI, 3235286441Srpaulo IWM_AC_VO, 3236286441Srpaulo IWM_AC_NUM, 3237286441Srpaulo}; 3238286441Srpaulo 3239286441Srpaulo/** 3240286441Srpaulo * enum iwm_mac_protection_flags - MAC context flags 3241286441Srpaulo * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3242286441Srpaulo * this will require CCK RTS/CTS2self. 3243286441Srpaulo * RTS/CTS will protect full burst time. 3244286441Srpaulo * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3245286441Srpaulo * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3246286441Srpaulo * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3247286441Srpaulo */ 3248286441Srpauloenum iwm_mac_protection_flags { 3249286441Srpaulo IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3250286441Srpaulo IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3251286441Srpaulo IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3252286441Srpaulo IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3253286441Srpaulo}; 3254286441Srpaulo 3255286441Srpaulo#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3256286441Srpaulo#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3257286441Srpaulo 3258286441Srpaulo/** 3259286441Srpaulo * enum iwm_mac_types - Supported MAC types 3260286441Srpaulo * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3261286441Srpaulo * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3262286441Srpaulo * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3263286441Srpaulo * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3264286441Srpaulo * @IWM_FW_MAC_TYPE_IBSS: IBSS 3265286441Srpaulo * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3266286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3267286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3268286441Srpaulo * @IWM_FW_MAC_TYPE_GO: P2P GO 3269286441Srpaulo * @IWM_FW_MAC_TYPE_TEST: ? 3270286441Srpaulo * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3271286441Srpaulo */ 3272286441Srpauloenum iwm_mac_types { 3273286441Srpaulo IWM_FW_MAC_TYPE_FIRST = 1, 3274286441Srpaulo IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3275286441Srpaulo IWM_FW_MAC_TYPE_LISTENER, 3276286441Srpaulo IWM_FW_MAC_TYPE_PIBSS, 3277286441Srpaulo IWM_FW_MAC_TYPE_IBSS, 3278286441Srpaulo IWM_FW_MAC_TYPE_BSS_STA, 3279286441Srpaulo IWM_FW_MAC_TYPE_P2P_DEVICE, 3280286441Srpaulo IWM_FW_MAC_TYPE_P2P_STA, 3281286441Srpaulo IWM_FW_MAC_TYPE_GO, 3282286441Srpaulo IWM_FW_MAC_TYPE_TEST, 3283286441Srpaulo IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3284286441Srpaulo}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3285286441Srpaulo 3286286441Srpaulo/** 3287286441Srpaulo * enum iwm_tsf_id - TSF hw timer ID 3288286441Srpaulo * @IWM_TSF_ID_A: use TSF A 3289286441Srpaulo * @IWM_TSF_ID_B: use TSF B 3290286441Srpaulo * @IWM_TSF_ID_C: use TSF C 3291286441Srpaulo * @IWM_TSF_ID_D: use TSF D 3292286441Srpaulo * @IWM_NUM_TSF_IDS: number of TSF timers available 3293286441Srpaulo */ 3294286441Srpauloenum iwm_tsf_id { 3295286441Srpaulo IWM_TSF_ID_A = 0, 3296286441Srpaulo IWM_TSF_ID_B = 1, 3297286441Srpaulo IWM_TSF_ID_C = 2, 3298286441Srpaulo IWM_TSF_ID_D = 3, 3299286441Srpaulo IWM_NUM_TSF_IDS = 4, 3300286441Srpaulo}; /* IWM_TSF_ID_API_E_VER_1 */ 3301286441Srpaulo 3302286441Srpaulo/** 3303286441Srpaulo * struct iwm_mac_data_ap - configuration data for AP MAC context 3304286441Srpaulo * @beacon_time: beacon transmit time in system time 3305286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 3306286441Srpaulo * @bi: beacon interval in TU 3307286441Srpaulo * @bi_reciprocal: 2^32 / bi 3308286441Srpaulo * @dtim_interval: dtim transmit time in TU 3309286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval 3310286441Srpaulo * @mcast_qid: queue ID for multicast traffic 3311286441Srpaulo * @beacon_template: beacon template ID 3312286441Srpaulo */ 3313286441Srpaulostruct iwm_mac_data_ap { 3314286441Srpaulo uint32_t beacon_time; 3315286441Srpaulo uint64_t beacon_tsf; 3316286441Srpaulo uint32_t bi; 3317286441Srpaulo uint32_t bi_reciprocal; 3318286441Srpaulo uint32_t dtim_interval; 3319286441Srpaulo uint32_t dtim_reciprocal; 3320286441Srpaulo uint32_t mcast_qid; 3321286441Srpaulo uint32_t beacon_template; 3322286441Srpaulo} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3323286441Srpaulo 3324286441Srpaulo/** 3325286441Srpaulo * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3326286441Srpaulo * @beacon_time: beacon transmit time in system time 3327286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 3328286441Srpaulo * @bi: beacon interval in TU 3329286441Srpaulo * @bi_reciprocal: 2^32 / bi 3330286441Srpaulo * @beacon_template: beacon template ID 3331286441Srpaulo */ 3332286441Srpaulostruct iwm_mac_data_ibss { 3333286441Srpaulo uint32_t beacon_time; 3334286441Srpaulo uint64_t beacon_tsf; 3335286441Srpaulo uint32_t bi; 3336286441Srpaulo uint32_t bi_reciprocal; 3337286441Srpaulo uint32_t beacon_template; 3338286441Srpaulo} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3339286441Srpaulo 3340286441Srpaulo/** 3341286441Srpaulo * struct iwm_mac_data_sta - configuration data for station MAC context 3342286441Srpaulo * @is_assoc: 1 for associated state, 0 otherwise 3343286441Srpaulo * @dtim_time: DTIM arrival time in system time 3344286441Srpaulo * @dtim_tsf: DTIM arrival time in TSF 3345286441Srpaulo * @bi: beacon interval in TU, applicable only when associated 3346286441Srpaulo * @bi_reciprocal: 2^32 / bi , applicable only when associated 3347286441Srpaulo * @dtim_interval: DTIM interval in TU, applicable only when associated 3348286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3349286441Srpaulo * @listen_interval: in beacon intervals, applicable only when associated 3350286441Srpaulo * @assoc_id: unique ID assigned by the AP during association 3351286441Srpaulo */ 3352286441Srpaulostruct iwm_mac_data_sta { 3353286441Srpaulo uint32_t is_assoc; 3354286441Srpaulo uint32_t dtim_time; 3355286441Srpaulo uint64_t dtim_tsf; 3356286441Srpaulo uint32_t bi; 3357286441Srpaulo uint32_t bi_reciprocal; 3358286441Srpaulo uint32_t dtim_interval; 3359286441Srpaulo uint32_t dtim_reciprocal; 3360286441Srpaulo uint32_t listen_interval; 3361286441Srpaulo uint32_t assoc_id; 3362286441Srpaulo uint32_t assoc_beacon_arrive_time; 3363286441Srpaulo} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3364286441Srpaulo 3365286441Srpaulo/** 3366286441Srpaulo * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3367286441Srpaulo * @ap: iwm_mac_data_ap struct with most config data 3368286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3369286441Srpaulo * 0 indicates that there is no CT window. 3370286441Srpaulo * @opp_ps_enabled: indicate that opportunistic PS allowed 3371286441Srpaulo */ 3372286441Srpaulostruct iwm_mac_data_go { 3373286441Srpaulo struct iwm_mac_data_ap ap; 3374286441Srpaulo uint32_t ctwin; 3375286441Srpaulo uint32_t opp_ps_enabled; 3376286441Srpaulo} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3377286441Srpaulo 3378286441Srpaulo/** 3379286441Srpaulo * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3380286441Srpaulo * @sta: iwm_mac_data_sta struct with most config data 3381286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3382286441Srpaulo * 0 indicates that there is no CT window. 3383286441Srpaulo */ 3384286441Srpaulostruct iwm_mac_data_p2p_sta { 3385286441Srpaulo struct iwm_mac_data_sta sta; 3386286441Srpaulo uint32_t ctwin; 3387286441Srpaulo} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3388286441Srpaulo 3389286441Srpaulo/** 3390286441Srpaulo * struct iwm_mac_data_pibss - Pseudo IBSS config data 3391286441Srpaulo * @stats_interval: interval in TU between statistics notifications to host. 3392286441Srpaulo */ 3393286441Srpaulostruct iwm_mac_data_pibss { 3394286441Srpaulo uint32_t stats_interval; 3395286441Srpaulo} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3396286441Srpaulo 3397286441Srpaulo/* 3398286441Srpaulo * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3399286441Srpaulo * context. 3400286441Srpaulo * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3401286441Srpaulo * other channels as well. This should be to true only in case that the 3402286441Srpaulo * device is discoverable and there is an active GO. Note that setting this 3403286441Srpaulo * field when not needed, will increase the number of interrupts and have 3404286441Srpaulo * effect on the platform power, as this setting opens the Rx filters on 3405286441Srpaulo * all macs. 3406286441Srpaulo */ 3407286441Srpaulostruct iwm_mac_data_p2p_dev { 3408286441Srpaulo uint32_t is_disc_extended; 3409286441Srpaulo} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3410286441Srpaulo 3411286441Srpaulo/** 3412286441Srpaulo * enum iwm_mac_filter_flags - MAC context filter flags 3413286441Srpaulo * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3414286441Srpaulo * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3415286441Srpaulo * control frames to the host 3416286441Srpaulo * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3417286441Srpaulo * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3418286441Srpaulo * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3419286441Srpaulo * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3420286441Srpaulo * (in station mode when associated) 3421286441Srpaulo * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3422286441Srpaulo * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3423286441Srpaulo * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3424286441Srpaulo */ 3425286441Srpauloenum iwm_mac_filter_flags { 3426286441Srpaulo IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3427286441Srpaulo IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3428286441Srpaulo IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3429286441Srpaulo IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3430286441Srpaulo IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3431286441Srpaulo IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3432286441Srpaulo IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3433286441Srpaulo IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3434286441Srpaulo IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3435286441Srpaulo}; 3436286441Srpaulo 3437286441Srpaulo/** 3438286441Srpaulo * enum iwm_mac_qos_flags - QoS flags 3439286441Srpaulo * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3440286441Srpaulo * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3441286441Srpaulo * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3442286441Srpaulo * 3443286441Srpaulo */ 3444286441Srpauloenum iwm_mac_qos_flags { 3445286441Srpaulo IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3446286441Srpaulo IWM_MAC_QOS_FLG_TGN = (1 << 1), 3447286441Srpaulo IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3448286441Srpaulo}; 3449286441Srpaulo 3450286441Srpaulo/** 3451286441Srpaulo * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3452286441Srpaulo * @cw_min: Contention window, start value in numbers of slots. 3453286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x0f. 3454286441Srpaulo * @cw_max: Contention window, max value in numbers of slots. 3455286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x3f. 3456286441Srpaulo * @aifsn: Number of slots in Arbitration Interframe Space (before 3457286441Srpaulo * performing random backoff timing prior to Tx). Device default 1. 3458286441Srpaulo * @fifos_mask: FIFOs used by this MAC for this AC 3459286441Srpaulo * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3460286441Srpaulo * 3461286441Srpaulo * One instance of this config struct for each of 4 EDCA access categories 3462286441Srpaulo * in struct iwm_qosparam_cmd. 3463286441Srpaulo * 3464286441Srpaulo * Device will automatically increase contention window by (2*CW) + 1 for each 3465286441Srpaulo * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3466286441Srpaulo * value, to cap the CW value. 3467286441Srpaulo */ 3468286441Srpaulostruct iwm_ac_qos { 3469286441Srpaulo uint16_t cw_min; 3470286441Srpaulo uint16_t cw_max; 3471286441Srpaulo uint8_t aifsn; 3472286441Srpaulo uint8_t fifos_mask; 3473286441Srpaulo uint16_t edca_txop; 3474286441Srpaulo} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3475286441Srpaulo 3476286441Srpaulo/** 3477286441Srpaulo * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3478286441Srpaulo * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3479286441Srpaulo * @id_and_color: ID and color of the MAC 3480286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3481286441Srpaulo * @mac_type: one of IWM_FW_MAC_TYPE_* 3482286441Srpaulo * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3483286441Srpaulo * @node_addr: MAC address 3484286441Srpaulo * @bssid_addr: BSSID 3485286441Srpaulo * @cck_rates: basic rates available for CCK 3486286441Srpaulo * @ofdm_rates: basic rates available for OFDM 3487286441Srpaulo * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3488286441Srpaulo * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3489286441Srpaulo * @short_slot: 0x10 for enabling short slots, 0 otherwise 3490286441Srpaulo * @filter_flags: combination of IWM_MAC_FILTER_* 3491286441Srpaulo * @qos_flags: from IWM_MAC_QOS_FLG_* 3492286441Srpaulo * @ac: one iwm_mac_qos configuration for each AC 3493286441Srpaulo * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3494286441Srpaulo */ 3495286441Srpaulostruct iwm_mac_ctx_cmd { 3496286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 3497286441Srpaulo uint32_t id_and_color; 3498286441Srpaulo uint32_t action; 3499286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3500286441Srpaulo uint32_t mac_type; 3501286441Srpaulo uint32_t tsf_id; 3502286441Srpaulo uint8_t node_addr[6]; 3503286441Srpaulo uint16_t reserved_for_node_addr; 3504286441Srpaulo uint8_t bssid_addr[6]; 3505286441Srpaulo uint16_t reserved_for_bssid_addr; 3506286441Srpaulo uint32_t cck_rates; 3507286441Srpaulo uint32_t ofdm_rates; 3508286441Srpaulo uint32_t protection_flags; 3509286441Srpaulo uint32_t cck_short_preamble; 3510286441Srpaulo uint32_t short_slot; 3511286441Srpaulo uint32_t filter_flags; 3512286441Srpaulo /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3513286441Srpaulo uint32_t qos_flags; 3514286441Srpaulo struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3515286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3516286441Srpaulo union { 3517286441Srpaulo struct iwm_mac_data_ap ap; 3518286441Srpaulo struct iwm_mac_data_go go; 3519286441Srpaulo struct iwm_mac_data_sta sta; 3520286441Srpaulo struct iwm_mac_data_p2p_sta p2p_sta; 3521286441Srpaulo struct iwm_mac_data_p2p_dev p2p_dev; 3522286441Srpaulo struct iwm_mac_data_pibss pibss; 3523286441Srpaulo struct iwm_mac_data_ibss ibss; 3524286441Srpaulo }; 3525286441Srpaulo} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3526286441Srpaulo 3527286441Srpaulostatic inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3528286441Srpaulo{ 3529286441Srpaulo if (!v) 3530286441Srpaulo return 0; 3531286441Srpaulo return 0xFFFFFFFF / v; 3532286441Srpaulo} 3533286441Srpaulo 3534286441Srpaulo#define IWM_NONQOS_SEQ_GET 0x1 3535286441Srpaulo#define IWM_NONQOS_SEQ_SET 0x2 3536286441Srpaulostruct iwm_nonqos_seq_query_cmd { 3537286441Srpaulo uint32_t get_set_flag; 3538286441Srpaulo uint32_t mac_id_n_color; 3539286441Srpaulo uint16_t value; 3540286441Srpaulo uint16_t reserved; 3541286441Srpaulo} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3542286441Srpaulo 3543286441Srpaulo/* 3544286441Srpaulo * END mvm/fw-api-mac.h 3545286441Srpaulo */ 3546286441Srpaulo 3547286441Srpaulo/* 3548286441Srpaulo * BEGIN mvm/fw-api-power.h 3549286441Srpaulo */ 3550286441Srpaulo 3551286441Srpaulo/* Power Management Commands, Responses, Notifications */ 3552286441Srpaulo 3553286441Srpaulo/* Radio LP RX Energy Threshold measured in dBm */ 3554286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3555286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3556286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3557286441Srpaulo 3558286441Srpaulo/** 3559286441Srpaulo * enum iwm_scan_flags - masks for power table command flags 3560286441Srpaulo * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3561286441Srpaulo * receiver and transmitter. '0' - does not allow. 3562286441Srpaulo * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3563286441Srpaulo * '1' Driver enables PM (use rest of parameters) 3564286441Srpaulo * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3565286441Srpaulo * '1' PM could sleep over DTIM till listen Interval. 3566286441Srpaulo * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3567286441Srpaulo * access categories are both delivery and trigger enabled. 3568286441Srpaulo * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3569286441Srpaulo * PBW Snoozing enabled 3570286441Srpaulo * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3571286441Srpaulo * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3572286441Srpaulo * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3573286441Srpaulo * detection enablement 3574286441Srpaulo*/ 3575286441Srpauloenum iwm_power_flags { 3576286441Srpaulo IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3577286441Srpaulo IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3578286441Srpaulo IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3579286441Srpaulo IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3580286441Srpaulo IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3581286441Srpaulo IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3582286441Srpaulo IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3583286441Srpaulo IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3584286441Srpaulo}; 3585286441Srpaulo 3586286441Srpaulo#define IWM_POWER_VEC_SIZE 5 3587286441Srpaulo 3588286441Srpaulo/** 3589286441Srpaulo * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3590286441Srpaulo * is used also with a new power API for device wide power settings. 3591286441Srpaulo * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3592286441Srpaulo * 3593286441Srpaulo * @flags: Power table command flags from IWM_POWER_FLAGS_* 3594286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3595286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3596286441Srpaulo * set regardless of power scheme or current power state. 3597286441Srpaulo * FW use this value also when PM is disabled. 3598286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3599286441Srpaulo * PSM transition - legacy PM 3600286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3601286441Srpaulo * PSM transition - legacy PM 3602286441Srpaulo * @sleep_interval: not in use 3603286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3604286441Srpaulo * is set. For example, if it is required to skip over 3605286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3606286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3607286441Srpaulo * Default: 80dbm 3608286441Srpaulo */ 3609286441Srpaulostruct iwm_powertable_cmd { 3610286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3611286441Srpaulo uint16_t flags; 3612286441Srpaulo uint8_t keep_alive_seconds; 3613286441Srpaulo uint8_t debug_flags; 3614286441Srpaulo uint32_t rx_data_timeout; 3615286441Srpaulo uint32_t tx_data_timeout; 3616286441Srpaulo uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3617286441Srpaulo uint32_t skip_dtim_periods; 3618286441Srpaulo uint32_t lprx_rssi_threshold; 3619286441Srpaulo} __packed; 3620286441Srpaulo 3621286441Srpaulo/** 3622286441Srpaulo * enum iwm_device_power_flags - masks for device power command flags 3623330201Seadler * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3624330201Seadler * receiver and transmitter. '0' - does not allow. 3625330201Seadler */ 3626286441Srpauloenum iwm_device_power_flags { 3627286441Srpaulo IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3628286441Srpaulo}; 3629286441Srpaulo 3630286441Srpaulo/** 3631286441Srpaulo * struct iwm_device_power_cmd - device wide power command. 3632286441Srpaulo * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3633286441Srpaulo * 3634286441Srpaulo * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3635286441Srpaulo */ 3636286441Srpaulostruct iwm_device_power_cmd { 3637286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3638286441Srpaulo uint16_t flags; 3639286441Srpaulo uint16_t reserved; 3640286441Srpaulo} __packed; 3641286441Srpaulo 3642286441Srpaulo/** 3643286441Srpaulo * struct iwm_mac_power_cmd - New power command containing uAPSD support 3644286441Srpaulo * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3645286441Srpaulo * @id_and_color: MAC contex identifier 3646286441Srpaulo * @flags: Power table command flags from POWER_FLAGS_* 3647286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3648286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3649286441Srpaulo * set regardless of power scheme or current power state. 3650286441Srpaulo * FW use this value also when PM is disabled. 3651286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3652286441Srpaulo * PSM transition - legacy PM 3653286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3654286441Srpaulo * PSM transition - legacy PM 3655286441Srpaulo * @sleep_interval: not in use 3656286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3657286441Srpaulo * is set. For example, if it is required to skip over 3658286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3659286441Srpaulo * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3660286441Srpaulo * PSM transition - uAPSD 3661286441Srpaulo * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3662286441Srpaulo * PSM transition - uAPSD 3663286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3664286441Srpaulo * Default: 80dbm 3665286441Srpaulo * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3666286441Srpaulo * @snooze_interval: Maximum time between attempts to retrieve buffered data 3667286441Srpaulo * from the AP [msec] 3668286441Srpaulo * @snooze_window: A window of time in which PBW snoozing insures that all 3669286441Srpaulo * packets received. It is also the minimum time from last 3670286441Srpaulo * received unicast RX packet, before client stops snoozing 3671286441Srpaulo * for data. [msec] 3672286441Srpaulo * @snooze_step: TBD 3673286441Srpaulo * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3674286441Srpaulo * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3675286441Srpaulo * each corresponding AC. 3676286441Srpaulo * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3677286441Srpaulo * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3678286441Srpaulo * values. 3679286441Srpaulo * @heavy_tx_thld_packets: TX threshold measured in number of packets 3680286441Srpaulo * @heavy_rx_thld_packets: RX threshold measured in number of packets 3681286441Srpaulo * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3682286441Srpaulo * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3683286441Srpaulo * @limited_ps_threshold: 3684286441Srpaulo*/ 3685286441Srpaulostruct iwm_mac_power_cmd { 3686286441Srpaulo /* CONTEXT_DESC_API_T_VER_1 */ 3687286441Srpaulo uint32_t id_and_color; 3688286441Srpaulo 3689286441Srpaulo /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3690286441Srpaulo uint16_t flags; 3691286441Srpaulo uint16_t keep_alive_seconds; 3692286441Srpaulo uint32_t rx_data_timeout; 3693286441Srpaulo uint32_t tx_data_timeout; 3694286441Srpaulo uint32_t rx_data_timeout_uapsd; 3695286441Srpaulo uint32_t tx_data_timeout_uapsd; 3696286441Srpaulo uint8_t lprx_rssi_threshold; 3697286441Srpaulo uint8_t skip_dtim_periods; 3698286441Srpaulo uint16_t snooze_interval; 3699286441Srpaulo uint16_t snooze_window; 3700286441Srpaulo uint8_t snooze_step; 3701286441Srpaulo uint8_t qndp_tid; 3702286441Srpaulo uint8_t uapsd_ac_flags; 3703286441Srpaulo uint8_t uapsd_max_sp; 3704286441Srpaulo uint8_t heavy_tx_thld_packets; 3705286441Srpaulo uint8_t heavy_rx_thld_packets; 3706286441Srpaulo uint8_t heavy_tx_thld_percentage; 3707286441Srpaulo uint8_t heavy_rx_thld_percentage; 3708286441Srpaulo uint8_t limited_ps_threshold; 3709286441Srpaulo uint8_t reserved; 3710286441Srpaulo} __packed; 3711286441Srpaulo 3712286441Srpaulo/* 3713286441Srpaulo * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3714286441Srpaulo * associated AP is identified as improperly implementing uAPSD protocol. 3715286441Srpaulo * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3716286441Srpaulo * @sta_id: index of station in uCode's station table - associated AP ID in 3717286441Srpaulo * this context. 3718286441Srpaulo */ 3719286441Srpaulostruct iwm_uapsd_misbehaving_ap_notif { 3720286441Srpaulo uint32_t sta_id; 3721286441Srpaulo uint8_t mac_id; 3722286441Srpaulo uint8_t reserved[3]; 3723286441Srpaulo} __packed; 3724286441Srpaulo 3725286441Srpaulo/** 3726286441Srpaulo * struct iwm_beacon_filter_cmd 3727286441Srpaulo * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3728286441Srpaulo * @id_and_color: MAC contex identifier 3729286441Srpaulo * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3730286441Srpaulo * to driver if delta in Energy values calculated for this and last 3731286441Srpaulo * passed beacon is greater than this threshold. Zero value means that 3732286441Srpaulo * the Energy change is ignored for beacon filtering, and beacon will 3733286441Srpaulo * not be forced to be sent to driver regardless of this delta. Typical 3734286441Srpaulo * energy delta 5dB. 3735286441Srpaulo * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3736286441Srpaulo * Send beacon to driver if delta in Energy values calculated for this 3737286441Srpaulo * and last passed beacon is greater than this threshold. Zero value 3738286441Srpaulo * means that the Energy change is ignored for beacon filtering while in 3739286441Srpaulo * Roaming state, typical energy delta 1dB. 3740286441Srpaulo * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3741286441Srpaulo * calculated for current beacon is less than the threshold, use 3742286441Srpaulo * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3743286441Srpaulo * Threshold. Typical energy threshold is -72dBm. 3744286441Srpaulo * @bf_temp_threshold: This threshold determines the type of temperature 3745286441Srpaulo * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3746286441Srpaulo * If the current temperature is above this threshold - Fast filter 3747286441Srpaulo * will be used, If the current temperature is below this threshold - 3748286441Srpaulo * Slow filter will be used. 3749286441Srpaulo * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3750286441Srpaulo * calculated for this and the last passed beacon is greater than this 3751286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3752286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3753298955Spfg * regardless of whether its temperature has been changed. 3754286441Srpaulo * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3755286441Srpaulo * calculated for this and the last passed beacon is greater than this 3756286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3757286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3758298955Spfg * regardless of whether its temperature has been changed. 3759286441Srpaulo * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3760286441Srpaulo * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3761286441Srpaulo * for a specific period of time. Units: Beacons. 3762286441Srpaulo * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3763286441Srpaulo * for a longer period of time then this escape-timeout. Units: Beacons. 3764286441Srpaulo * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3765286441Srpaulo */ 3766286441Srpaulostruct iwm_beacon_filter_cmd { 3767286441Srpaulo uint32_t bf_energy_delta; 3768286441Srpaulo uint32_t bf_roaming_energy_delta; 3769286441Srpaulo uint32_t bf_roaming_state; 3770286441Srpaulo uint32_t bf_temp_threshold; 3771286441Srpaulo uint32_t bf_temp_fast_filter; 3772286441Srpaulo uint32_t bf_temp_slow_filter; 3773286441Srpaulo uint32_t bf_enable_beacon_filter; 3774286441Srpaulo uint32_t bf_debug_flag; 3775286441Srpaulo uint32_t bf_escape_timer; 3776286441Srpaulo uint32_t ba_escape_timer; 3777286441Srpaulo uint32_t ba_enable_beacon_abort; 3778286441Srpaulo} __packed; 3779286441Srpaulo 3780286441Srpaulo/* Beacon filtering and beacon abort */ 3781286441Srpaulo#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3782286441Srpaulo#define IWM_BF_ENERGY_DELTA_MAX 255 3783286441Srpaulo#define IWM_BF_ENERGY_DELTA_MIN 0 3784286441Srpaulo 3785286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3786286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3787286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3788286441Srpaulo 3789286441Srpaulo#define IWM_BF_ROAMING_STATE_DEFAULT 72 3790286441Srpaulo#define IWM_BF_ROAMING_STATE_MAX 255 3791286441Srpaulo#define IWM_BF_ROAMING_STATE_MIN 0 3792286441Srpaulo 3793286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3794286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MAX 255 3795286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MIN 0 3796286441Srpaulo 3797286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3798286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3799286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3800286441Srpaulo 3801286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3802286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3803286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3804286441Srpaulo 3805286441Srpaulo#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3806286441Srpaulo 3807286441Srpaulo#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3808286441Srpaulo 3809286441Srpaulo#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3810286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MAX 1024 3811286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MIN 0 3812286441Srpaulo 3813286441Srpaulo#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3814286441Srpaulo#define IWM_BA_ESCAPE_TIMER_D3 9 3815286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MAX 1024 3816286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MIN 0 3817286441Srpaulo 3818286441Srpaulo#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3819286441Srpaulo 3820286441Srpaulo#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3821286441Srpaulo .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3822286441Srpaulo .bf_roaming_energy_delta = \ 3823286441Srpaulo htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3824286441Srpaulo .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3825286441Srpaulo .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3826286441Srpaulo .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3827286441Srpaulo .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3828286441Srpaulo .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3829286441Srpaulo .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3830286441Srpaulo .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3831286441Srpaulo 3832286441Srpaulo/* 3833286441Srpaulo * END mvm/fw-api-power.h 3834286441Srpaulo */ 3835286441Srpaulo 3836286441Srpaulo/* 3837286441Srpaulo * BEGIN mvm/fw-api-rs.h 3838286441Srpaulo */ 3839286441Srpaulo 3840286441Srpaulo/* 3841286441Srpaulo * These serve as indexes into 3842286441Srpaulo * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3843286441Srpaulo * TODO: avoid overlap between legacy and HT rates 3844286441Srpaulo */ 3845286441Srpauloenum { 3846286441Srpaulo IWM_RATE_1M_INDEX = 0, 3847286441Srpaulo IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3848286441Srpaulo IWM_RATE_2M_INDEX, 3849286441Srpaulo IWM_RATE_5M_INDEX, 3850286441Srpaulo IWM_RATE_11M_INDEX, 3851286441Srpaulo IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3852286441Srpaulo IWM_RATE_6M_INDEX, 3853286441Srpaulo IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3854286441Srpaulo IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3855286441Srpaulo IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3856286441Srpaulo IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3857286441Srpaulo IWM_RATE_9M_INDEX, 3858286441Srpaulo IWM_RATE_12M_INDEX, 3859286441Srpaulo IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3860286441Srpaulo IWM_RATE_18M_INDEX, 3861286441Srpaulo IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3862286441Srpaulo IWM_RATE_24M_INDEX, 3863286441Srpaulo IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3864286441Srpaulo IWM_RATE_36M_INDEX, 3865286441Srpaulo IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3866286441Srpaulo IWM_RATE_48M_INDEX, 3867286441Srpaulo IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3868286441Srpaulo IWM_RATE_54M_INDEX, 3869286441Srpaulo IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3870286441Srpaulo IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3871286441Srpaulo IWM_RATE_60M_INDEX, 3872286441Srpaulo IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3873286441Srpaulo IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3874286441Srpaulo IWM_RATE_MCS_8_INDEX, 3875286441Srpaulo IWM_RATE_MCS_9_INDEX, 3876286441Srpaulo IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3877286441Srpaulo IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3878286441Srpaulo IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3879286441Srpaulo}; 3880286441Srpaulo 3881286441Srpaulo#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3882286441Srpaulo 3883286441Srpaulo/* fw API values for legacy bit rates, both OFDM and CCK */ 3884286441Srpauloenum { 3885286441Srpaulo IWM_RATE_6M_PLCP = 13, 3886286441Srpaulo IWM_RATE_9M_PLCP = 15, 3887286441Srpaulo IWM_RATE_12M_PLCP = 5, 3888286441Srpaulo IWM_RATE_18M_PLCP = 7, 3889286441Srpaulo IWM_RATE_24M_PLCP = 9, 3890286441Srpaulo IWM_RATE_36M_PLCP = 11, 3891286441Srpaulo IWM_RATE_48M_PLCP = 1, 3892286441Srpaulo IWM_RATE_54M_PLCP = 3, 3893286441Srpaulo IWM_RATE_1M_PLCP = 10, 3894286441Srpaulo IWM_RATE_2M_PLCP = 20, 3895286441Srpaulo IWM_RATE_5M_PLCP = 55, 3896286441Srpaulo IWM_RATE_11M_PLCP = 110, 3897286441Srpaulo IWM_RATE_INVM_PLCP = -1, 3898286441Srpaulo}; 3899286441Srpaulo 3900286441Srpaulo/* 3901286441Srpaulo * rate_n_flags bit fields 3902286441Srpaulo * 3903286441Srpaulo * The 32-bit value has different layouts in the low 8 bites depending on the 3904286441Srpaulo * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3905286441Srpaulo * for CCK and OFDM). 3906286441Srpaulo * 3907286441Srpaulo * High-throughput (HT) rate format 3908286441Srpaulo * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3909286441Srpaulo * Very High-throughput (VHT) rate format 3910286441Srpaulo * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3911286441Srpaulo * Legacy OFDM rate format for bits 7:0 3912286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3913286441Srpaulo * Legacy CCK rate format for bits 7:0: 3914286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3915286441Srpaulo */ 3916286441Srpaulo 3917286441Srpaulo/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3918286441Srpaulo#define IWM_RATE_MCS_HT_POS 8 3919286441Srpaulo#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3920286441Srpaulo 3921286441Srpaulo/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3922286441Srpaulo#define IWM_RATE_MCS_CCK_POS 9 3923286441Srpaulo#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3924286441Srpaulo 3925286441Srpaulo/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3926286441Srpaulo#define IWM_RATE_MCS_VHT_POS 26 3927286441Srpaulo#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3928286441Srpaulo 3929286441Srpaulo 3930286441Srpaulo/* 3931286441Srpaulo * High-throughput (HT) rate format for bits 7:0 3932286441Srpaulo * 3933286441Srpaulo * 2-0: MCS rate base 3934286441Srpaulo * 0) 6 Mbps 3935286441Srpaulo * 1) 12 Mbps 3936286441Srpaulo * 2) 18 Mbps 3937286441Srpaulo * 3) 24 Mbps 3938286441Srpaulo * 4) 36 Mbps 3939286441Srpaulo * 5) 48 Mbps 3940286441Srpaulo * 6) 54 Mbps 3941286441Srpaulo * 7) 60 Mbps 3942286441Srpaulo * 4-3: 0) Single stream (SISO) 3943286441Srpaulo * 1) Dual stream (MIMO) 3944286441Srpaulo * 2) Triple stream (MIMO) 3945286441Srpaulo * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3946286441Srpaulo * (bits 7-6 are zero) 3947286441Srpaulo * 3948286441Srpaulo * Together the low 5 bits work out to the MCS index because we don't 3949286441Srpaulo * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3950286441Srpaulo * streams and 16-23 have three streams. We could also support MCS 32 3951286441Srpaulo * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3952286441Srpaulo */ 3953286441Srpaulo#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3954286441Srpaulo#define IWM_RATE_HT_MCS_NSS_POS 3 3955286441Srpaulo#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3956286441Srpaulo 3957286441Srpaulo/* Bit 10: (1) Use Green Field preamble */ 3958286441Srpaulo#define IWM_RATE_HT_MCS_GF_POS 10 3959286441Srpaulo#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3960286441Srpaulo 3961286441Srpaulo#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3962286441Srpaulo 3963286441Srpaulo/* 3964286441Srpaulo * Very High-throughput (VHT) rate format for bits 7:0 3965286441Srpaulo * 3966286441Srpaulo * 3-0: VHT MCS (0-9) 3967286441Srpaulo * 5-4: number of streams - 1: 3968286441Srpaulo * 0) Single stream (SISO) 3969286441Srpaulo * 1) Dual stream (MIMO) 3970286441Srpaulo * 2) Triple stream (MIMO) 3971286441Srpaulo */ 3972286441Srpaulo 3973286441Srpaulo/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3974286441Srpaulo#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3975286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_POS 4 3976286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3977286441Srpaulo 3978286441Srpaulo/* 3979286441Srpaulo * Legacy OFDM rate format for bits 7:0 3980286441Srpaulo * 3981286441Srpaulo * 3-0: 0xD) 6 Mbps 3982286441Srpaulo * 0xF) 9 Mbps 3983286441Srpaulo * 0x5) 12 Mbps 3984286441Srpaulo * 0x7) 18 Mbps 3985286441Srpaulo * 0x9) 24 Mbps 3986286441Srpaulo * 0xB) 36 Mbps 3987286441Srpaulo * 0x1) 48 Mbps 3988286441Srpaulo * 0x3) 54 Mbps 3989286441Srpaulo * (bits 7-4 are 0) 3990286441Srpaulo * 3991286441Srpaulo * Legacy CCK rate format for bits 7:0: 3992286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3993286441Srpaulo * 3994286441Srpaulo * 6-0: 10) 1 Mbps 3995286441Srpaulo * 20) 2 Mbps 3996286441Srpaulo * 55) 5.5 Mbps 3997286441Srpaulo * 110) 11 Mbps 3998286441Srpaulo * (bit 7 is 0) 3999286441Srpaulo */ 4000286441Srpaulo#define IWM_RATE_LEGACY_RATE_MSK 0xff 4001286441Srpaulo 4002286441Srpaulo 4003286441Srpaulo/* 4004286441Srpaulo * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4005286441Srpaulo * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4006286441Srpaulo */ 4007286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4008286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4009286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4010286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4011286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4012286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4013286441Srpaulo 4014286441Srpaulo/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4015286441Srpaulo#define IWM_RATE_MCS_SGI_POS 13 4016286441Srpaulo#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4017286441Srpaulo 4018286441Srpaulo/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4019286441Srpaulo#define IWM_RATE_MCS_ANT_POS 14 4020286441Srpaulo#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4021286441Srpaulo#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4022286441Srpaulo#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4023286441Srpaulo#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4024286441Srpaulo IWM_RATE_MCS_ANT_B_MSK) 4025286441Srpaulo#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4026286441Srpaulo IWM_RATE_MCS_ANT_C_MSK) 4027286441Srpaulo#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4028286441Srpaulo#define IWM_RATE_MCS_ANT_NUM 3 4029286441Srpaulo 4030286441Srpaulo/* Bit 17-18: (0) SS, (1) SS*2 */ 4031286441Srpaulo#define IWM_RATE_MCS_STBC_POS 17 4032286441Srpaulo#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4033286441Srpaulo 4034286441Srpaulo/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4035286441Srpaulo#define IWM_RATE_MCS_BF_POS 19 4036286441Srpaulo#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4037286441Srpaulo 4038286441Srpaulo/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4039286441Srpaulo#define IWM_RATE_MCS_ZLF_POS 20 4040286441Srpaulo#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4041286441Srpaulo 4042286441Srpaulo/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4043286441Srpaulo#define IWM_RATE_MCS_DUP_POS 24 4044286441Srpaulo#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4045286441Srpaulo 4046286441Srpaulo/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4047286441Srpaulo#define IWM_RATE_MCS_LDPC_POS 27 4048286441Srpaulo#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4049286441Srpaulo 4050286441Srpaulo 4051286441Srpaulo/* Link Quality definitions */ 4052286441Srpaulo 4053286441Srpaulo/* # entries in rate scale table to support Tx retries */ 4054286441Srpaulo#define IWM_LQ_MAX_RETRY_NUM 16 4055286441Srpaulo 4056286441Srpaulo/* Link quality command flags bit fields */ 4057286441Srpaulo 4058286441Srpaulo/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4059286441Srpaulo#define IWM_LQ_FLAG_USE_RTS_POS 0 4060286441Srpaulo#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4061286441Srpaulo 4062286441Srpaulo/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4063286441Srpaulo#define IWM_LQ_FLAG_COLOR_POS 1 4064286441Srpaulo#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4065286441Srpaulo 4066286441Srpaulo/* Bit 4-5: Tx RTS BW Signalling 4067286441Srpaulo * (0) No RTS BW signalling 4068286441Srpaulo * (1) Static BW signalling 4069286441Srpaulo * (2) Dynamic BW signalling 4070286441Srpaulo */ 4071286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4072286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4073286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4074286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4075286441Srpaulo 4076286441Srpaulo/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4077286441Srpaulo * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4078286441Srpaulo */ 4079286441Srpaulo#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4080286441Srpaulo#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4081286441Srpaulo 4082286441Srpaulo/** 4083286441Srpaulo * struct iwm_lq_cmd - link quality command 4084286441Srpaulo * @sta_id: station to update 4085286441Srpaulo * @control: not used 4086286441Srpaulo * @flags: combination of IWM_LQ_FLAG_* 4087286441Srpaulo * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4088286441Srpaulo * and SISO rates 4089286441Srpaulo * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4090286441Srpaulo * Should be ANT_[ABC] 4091286441Srpaulo * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4092286441Srpaulo * @initial_rate_index: first index from rs_table per AC category 4093286441Srpaulo * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4094286441Srpaulo * value of 100 is one usec. Range is 100 to 8000 4095286441Srpaulo * @agg_disable_start_th: try-count threshold for starting aggregation. 4096286441Srpaulo * If a frame has higher try-count, it should not be selected for 4097286441Srpaulo * starting an aggregation sequence. 4098286441Srpaulo * @agg_frame_cnt_limit: max frame count in an aggregation. 4099286441Srpaulo * 0: no limit 4100286441Srpaulo * 1: no aggregation (one frame per aggregation) 4101286441Srpaulo * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4102286441Srpaulo * @rs_table: array of rates for each TX try, each is rate_n_flags, 4103286441Srpaulo * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4104286441Srpaulo * @bf_params: beam forming params, currently not used 4105286441Srpaulo */ 4106286441Srpaulostruct iwm_lq_cmd { 4107286441Srpaulo uint8_t sta_id; 4108286441Srpaulo uint8_t reserved1; 4109286441Srpaulo uint16_t control; 4110286441Srpaulo /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4111286441Srpaulo uint8_t flags; 4112286441Srpaulo uint8_t mimo_delim; 4113286441Srpaulo uint8_t single_stream_ant_msk; 4114286441Srpaulo uint8_t dual_stream_ant_msk; 4115286441Srpaulo uint8_t initial_rate_index[IWM_AC_NUM]; 4116286441Srpaulo /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4117286441Srpaulo uint16_t agg_time_limit; 4118286441Srpaulo uint8_t agg_disable_start_th; 4119286441Srpaulo uint8_t agg_frame_cnt_limit; 4120286441Srpaulo uint32_t reserved2; 4121286441Srpaulo uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4122286441Srpaulo uint32_t bf_params; 4123286441Srpaulo}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4124286441Srpaulo 4125286441Srpaulo/* 4126286441Srpaulo * END mvm/fw-api-rs.h 4127286441Srpaulo */ 4128286441Srpaulo 4129286441Srpaulo/* 4130286441Srpaulo * BEGIN mvm/fw-api-tx.h 4131286441Srpaulo */ 4132286441Srpaulo 4133286441Srpaulo/** 4134286441Srpaulo * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4135286441Srpaulo * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4136286441Srpaulo * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4137286441Srpaulo * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4138286441Srpaulo * Otherwise, use rate_n_flags from the TX command 4139286441Srpaulo * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4140286441Srpaulo * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4141286441Srpaulo * Must set IWM_TX_CMD_FLG_ACK with this flag. 4142286441Srpaulo * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4143286441Srpaulo * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4144286441Srpaulo * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4145286441Srpaulo * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4146286441Srpaulo * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4147286441Srpaulo * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4148286441Srpaulo * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4149286441Srpaulo * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4150286441Srpaulo * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4151286441Srpaulo * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4152286441Srpaulo * Should be set for beacons and probe responses 4153286441Srpaulo * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4154286441Srpaulo * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4155286441Srpaulo * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4156286441Srpaulo * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4157286441Srpaulo * Should be set for 26/30 length MAC headers 4158286441Srpaulo * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4159286441Srpaulo * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4160286441Srpaulo * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4161286441Srpaulo * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4162286441Srpaulo * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4163286441Srpaulo * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4164286441Srpaulo * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4165286441Srpaulo * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4166286441Srpaulo */ 4167286441Srpauloenum iwm_tx_flags { 4168286441Srpaulo IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4169286441Srpaulo IWM_TX_CMD_FLG_ACK = (1 << 3), 4170286441Srpaulo IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4171286441Srpaulo IWM_TX_CMD_FLG_BA = (1 << 5), 4172286441Srpaulo IWM_TX_CMD_FLG_BAR = (1 << 6), 4173286441Srpaulo IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4174286441Srpaulo IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4175286441Srpaulo IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4176286441Srpaulo IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4177286441Srpaulo IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4178286441Srpaulo IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4179286441Srpaulo IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4180286441Srpaulo IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4181286441Srpaulo IWM_TX_CMD_FLG_TSF = (1 << 16), 4182286441Srpaulo IWM_TX_CMD_FLG_CALIB = (1 << 17), 4183286441Srpaulo IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4184286441Srpaulo IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4185286441Srpaulo IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4186286441Srpaulo IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4187286441Srpaulo IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4188286441Srpaulo IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4189286441Srpaulo IWM_TX_CMD_FLG_DUR = (1 << 25), 4190286441Srpaulo IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4191286441Srpaulo IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4192286441Srpaulo IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4193286441Srpaulo IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4194286441Srpaulo}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4195286441Srpaulo 4196303628Ssbruno/** 4197303628Ssbruno * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4198303628Ssbruno * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4199303628Ssbruno * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4200303628Ssbruno * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4201303628Ssbruno */ 4202303628Ssbrunoenum iwm_tx_pm_timeouts { 4203303628Ssbruno IWM_PM_FRAME_NONE = 0, 4204303628Ssbruno IWM_PM_FRAME_MGMT = 2, 4205303628Ssbruno IWM_PM_FRAME_ASSOC = 3, 4206303628Ssbruno}; 4207303628Ssbruno 4208286441Srpaulo/* 4209286441Srpaulo * TX command security control 4210286441Srpaulo */ 4211286441Srpaulo#define IWM_TX_CMD_SEC_WEP 0x01 4212286441Srpaulo#define IWM_TX_CMD_SEC_CCM 0x02 4213286441Srpaulo#define IWM_TX_CMD_SEC_TKIP 0x03 4214286441Srpaulo#define IWM_TX_CMD_SEC_EXT 0x04 4215286441Srpaulo#define IWM_TX_CMD_SEC_MSK 0x07 4216286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4217286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4218286441Srpaulo#define IWM_TX_CMD_SEC_KEY128 0x08 4219286441Srpaulo 4220286441Srpaulo/* TODO: how does these values are OK with only 16 bit variable??? */ 4221286441Srpaulo/* 4222286441Srpaulo * TX command next frame info 4223286441Srpaulo * 4224286441Srpaulo * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4225286441Srpaulo * bit 3 - immediate ACK required 4226286441Srpaulo * bit 4 - rate is taken from STA table 4227286441Srpaulo * bit 5 - frame belongs to BA stream 4228286441Srpaulo * bit 6 - immediate BA response expected 4229286441Srpaulo * bit 7 - unused 4230286441Srpaulo * bits 8:15 - Station ID 4231286441Srpaulo * bits 16:31 - rate 4232286441Srpaulo */ 4233286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4234286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4235286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4236286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4237286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4238286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4239286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4240286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4241286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4242286441Srpaulo 4243286441Srpaulo/* 4244286441Srpaulo * TX command Frame life time in us - to be written in pm_frame_timeout 4245286441Srpaulo */ 4246286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4247286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4248286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4249286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4250286441Srpaulo 4251286441Srpaulo/* 4252286441Srpaulo * TID for non QoS frames - to be written in tid_tspec 4253286441Srpaulo */ 4254286441Srpaulo#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4255286441Srpaulo 4256286441Srpaulo/* 4257286441Srpaulo * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4258286441Srpaulo */ 4259286441Srpaulo#define IWM_DEFAULT_TX_RETRY 15 4260286441Srpaulo#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4261286441Srpaulo#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4262286441Srpaulo#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4263286441Srpaulo#define IWM_LOW_RETRY_LIMIT 7 4264286441Srpaulo 4265286441Srpaulo/* TODO: complete documentation for try_cnt and btkill_cnt */ 4266286441Srpaulo/** 4267286441Srpaulo * struct iwm_tx_cmd - TX command struct to FW 4268286441Srpaulo * ( IWM_TX_CMD = 0x1c ) 4269286441Srpaulo * @len: in bytes of the payload, see below for details 4270286441Srpaulo * @next_frame_len: same as len, but for next frame (0 if not applicable) 4271286441Srpaulo * Used for fragmentation and bursting, but not in 11n aggregation. 4272286441Srpaulo * @tx_flags: combination of IWM_TX_CMD_FLG_* 4273286441Srpaulo * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4274286441Srpaulo * cleared. Combination of IWM_RATE_MCS_* 4275286441Srpaulo * @sta_id: index of destination station in FW station table 4276286441Srpaulo * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4277300050Seadler * @initial_rate_index: index into the rate table for initial TX attempt. 4278286441Srpaulo * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4279286441Srpaulo * @key: security key 4280286441Srpaulo * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4281286441Srpaulo * @life_time: frame life time (usecs??) 4282286441Srpaulo * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4283286441Srpaulo * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4284286441Srpaulo * @dram_msb_ptr: upper bits of the scratch physical address 4285286441Srpaulo * @rts_retry_limit: max attempts for RTS 4286286441Srpaulo * @data_retry_limit: max attempts to send the data packet 4287286441Srpaulo * @tid_spec: TID/tspec 4288286441Srpaulo * @pm_frame_timeout: PM TX frame timeout 4289286441Srpaulo * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4290286441Srpaulo * specified by HCCA protocol 4291286441Srpaulo * 4292286441Srpaulo * The byte count (both len and next_frame_len) includes MAC header 4293286441Srpaulo * (24/26/30/32 bytes) 4294286441Srpaulo * + 2 bytes pad if 26/30 header size 4295286441Srpaulo * + 8 byte IV for CCM or TKIP (not used for WEP) 4296286441Srpaulo * + Data payload 4297286441Srpaulo * + 8-byte MIC (not used for CCM/WEP) 4298286441Srpaulo * It does not include post-MAC padding, i.e., 4299286441Srpaulo * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4300286441Srpaulo * Range of len: 14-2342 bytes. 4301286441Srpaulo * 4302286441Srpaulo * After the struct fields the MAC header is placed, plus any padding, 4303286441Srpaulo * and then the actial payload. 4304286441Srpaulo */ 4305286441Srpaulostruct iwm_tx_cmd { 4306286441Srpaulo uint16_t len; 4307286441Srpaulo uint16_t next_frame_len; 4308286441Srpaulo uint32_t tx_flags; 4309286441Srpaulo struct { 4310286441Srpaulo uint8_t try_cnt; 4311286441Srpaulo uint8_t btkill_cnt; 4312286441Srpaulo uint16_t reserved; 4313286441Srpaulo } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4314286441Srpaulo uint32_t rate_n_flags; 4315286441Srpaulo uint8_t sta_id; 4316286441Srpaulo uint8_t sec_ctl; 4317286441Srpaulo uint8_t initial_rate_index; 4318286441Srpaulo uint8_t reserved2; 4319286441Srpaulo uint8_t key[16]; 4320286441Srpaulo uint16_t next_frame_flags; 4321286441Srpaulo uint16_t reserved3; 4322286441Srpaulo uint32_t life_time; 4323286441Srpaulo uint32_t dram_lsb_ptr; 4324286441Srpaulo uint8_t dram_msb_ptr; 4325286441Srpaulo uint8_t rts_retry_limit; 4326286441Srpaulo uint8_t data_retry_limit; 4327286441Srpaulo uint8_t tid_tspec; 4328286441Srpaulo uint16_t pm_frame_timeout; 4329286441Srpaulo uint16_t driver_txop; 4330286441Srpaulo uint8_t payload[0]; 4331286441Srpaulo struct ieee80211_frame hdr[0]; 4332286441Srpaulo} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4333286441Srpaulo 4334286441Srpaulo/* 4335286441Srpaulo * TX response related data 4336286441Srpaulo */ 4337286441Srpaulo 4338286441Srpaulo/* 4339286441Srpaulo * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4340286441Srpaulo * @IWM_TX_STATUS_SUCCESS: 4341286441Srpaulo * @IWM_TX_STATUS_DIRECT_DONE: 4342286441Srpaulo * @IWM_TX_STATUS_POSTPONE_DELAY: 4343286441Srpaulo * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4344286441Srpaulo * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4345286441Srpaulo * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4346286441Srpaulo * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4347286441Srpaulo * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4348286441Srpaulo * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4349286441Srpaulo * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4350286441Srpaulo * @IWM_TX_STATUS_FAIL_UNDERRUN: 4351286441Srpaulo * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4352286441Srpaulo * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4353286441Srpaulo * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4354286441Srpaulo * @IWM_TX_STATUS_FAIL_DEST_PS: 4355286441Srpaulo * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4356286441Srpaulo * @IWM_TX_STATUS_FAIL_BT_RETRY: 4357286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_INVALID: 4358286441Srpaulo * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4359286441Srpaulo * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4360286441Srpaulo * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4361286441Srpaulo * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4362286441Srpaulo * @IWM_TX_STATUS_FAIL_FW_DROP: 4363286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4364286441Srpaulo * STA table 4365286441Srpaulo * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4366286441Srpaulo * @IWM_TX_MODE_MSK: 4367286441Srpaulo * @IWM_TX_MODE_NO_BURST: 4368286441Srpaulo * @IWM_TX_MODE_IN_BURST_SEQ: 4369286441Srpaulo * @IWM_TX_MODE_FIRST_IN_BURST: 4370286441Srpaulo * @IWM_TX_QUEUE_NUM_MSK: 4371286441Srpaulo * 4372286441Srpaulo * Valid only if frame_count =1 4373286441Srpaulo * TODO: complete documentation 4374286441Srpaulo */ 4375286441Srpauloenum iwm_tx_status { 4376286441Srpaulo IWM_TX_STATUS_MSK = 0x000000ff, 4377286441Srpaulo IWM_TX_STATUS_SUCCESS = 0x01, 4378286441Srpaulo IWM_TX_STATUS_DIRECT_DONE = 0x02, 4379286441Srpaulo /* postpone TX */ 4380286441Srpaulo IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4381286441Srpaulo IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4382286441Srpaulo IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4383286441Srpaulo IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4384286441Srpaulo IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4385286441Srpaulo /* abort TX */ 4386286441Srpaulo IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4387286441Srpaulo IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4388286441Srpaulo IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4389286441Srpaulo IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4390286441Srpaulo IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4391286441Srpaulo IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4392286441Srpaulo IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4393286441Srpaulo IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4394286441Srpaulo IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4395286441Srpaulo IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4396286441Srpaulo IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4397286441Srpaulo IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4398286441Srpaulo IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4399286441Srpaulo IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4400286441Srpaulo IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4401286441Srpaulo IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4402286441Srpaulo IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4403286441Srpaulo IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4404286441Srpaulo IWM_TX_MODE_MSK = 0x00000f00, 4405286441Srpaulo IWM_TX_MODE_NO_BURST = 0x00000000, 4406286441Srpaulo IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4407286441Srpaulo IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4408286441Srpaulo IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4409286441Srpaulo IWM_TX_NARROW_BW_MSK = 0x00060000, 4410286441Srpaulo IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4411286441Srpaulo IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4412286441Srpaulo IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4413286441Srpaulo}; 4414286441Srpaulo 4415286441Srpaulo/* 4416286441Srpaulo * enum iwm_tx_agg_status - TX aggregation status 4417286441Srpaulo * @IWM_AGG_TX_STATE_STATUS_MSK: 4418286441Srpaulo * @IWM_AGG_TX_STATE_TRANSMITTED: 4419286441Srpaulo * @IWM_AGG_TX_STATE_UNDERRUN: 4420286441Srpaulo * @IWM_AGG_TX_STATE_BT_PRIO: 4421286441Srpaulo * @IWM_AGG_TX_STATE_FEW_BYTES: 4422286441Srpaulo * @IWM_AGG_TX_STATE_ABORT: 4423286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4424286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4425286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4426286441Srpaulo * @IWM_AGG_TX_STATE_SCD_QUERY: 4427286441Srpaulo * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4428286441Srpaulo * @IWM_AGG_TX_STATE_RESPONSE: 4429286441Srpaulo * @IWM_AGG_TX_STATE_DUMP_TX: 4430286441Srpaulo * @IWM_AGG_TX_STATE_DELAY_TX: 4431286441Srpaulo * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4432286441Srpaulo * occur if tx failed for this frame when it was a member of a previous 4433286441Srpaulo * aggregation block). If rate scaling is used, retry count indicates the 4434286441Srpaulo * rate table entry used for all frames in the new agg. 4435286441Srpaulo *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4436286441Srpaulo * this frame 4437286441Srpaulo * 4438286441Srpaulo * TODO: complete documentation 4439286441Srpaulo */ 4440286441Srpauloenum iwm_tx_agg_status { 4441286441Srpaulo IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4442286441Srpaulo IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4443286441Srpaulo IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4444286441Srpaulo IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4445286441Srpaulo IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4446286441Srpaulo IWM_AGG_TX_STATE_ABORT = 0x008, 4447286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4448286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4449286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4450286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4451286441Srpaulo IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4452286441Srpaulo IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4453286441Srpaulo IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4454286441Srpaulo IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4455286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4456286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4457286441Srpaulo}; 4458286441Srpaulo 4459286441Srpaulo#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4460286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4461286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4462286441Srpaulo 4463286441Srpaulo/* 4464286441Srpaulo * The mask below describes a status where we are absolutely sure that the MPDU 4465286441Srpaulo * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4466286441Srpaulo * written the bytes to the TXE, but we know nothing about what the DSP did. 4467286441Srpaulo */ 4468286441Srpaulo#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4469286441Srpaulo IWM_AGG_TX_STATE_ABORT | \ 4470286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY) 4471286441Srpaulo 4472286441Srpaulo/* 4473286441Srpaulo * IWM_REPLY_TX = 0x1c (response) 4474286441Srpaulo * 4475286441Srpaulo * This response may be in one of two slightly different formats, indicated 4476286441Srpaulo * by the frame_count field: 4477286441Srpaulo * 4478286441Srpaulo * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4479286441Srpaulo * frame. Multiple attempts, at various bit rates, may have been made for 4480286441Srpaulo * this frame. 4481286441Srpaulo * 4482286441Srpaulo * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4483286441Srpaulo * frames that used block-acknowledge. All frames were transmitted at 4484286441Srpaulo * same rate. Rate scaling may have been used if first frame in this new 4485286441Srpaulo * agg block failed in previous agg block(s). 4486286441Srpaulo * 4487286441Srpaulo * Note that, for aggregation, ACK (block-ack) status is not delivered 4488286441Srpaulo * here; block-ack has not been received by the time the device records 4489286441Srpaulo * this status. 4490286441Srpaulo * This status relates to reasons the tx might have been blocked or aborted 4491286441Srpaulo * within the device, rather than whether it was received successfully by 4492286441Srpaulo * the destination station. 4493286441Srpaulo */ 4494286441Srpaulo 4495286441Srpaulo/** 4496286441Srpaulo * struct iwm_agg_tx_status - per packet TX aggregation status 4497286441Srpaulo * @status: enum iwm_tx_agg_status 4498286441Srpaulo * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4499286441Srpaulo */ 4500286441Srpaulostruct iwm_agg_tx_status { 4501286441Srpaulo uint16_t status; 4502286441Srpaulo uint16_t sequence; 4503286441Srpaulo} __packed; 4504286441Srpaulo 4505286441Srpaulo/* 4506286441Srpaulo * definitions for initial rate index field 4507286441Srpaulo * bits [3:0] initial rate index 4508286441Srpaulo * bits [6:4] rate table color, used for the initial rate 4509286441Srpaulo * bit-7 invalid rate indication 4510286441Srpaulo */ 4511286441Srpaulo#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4512286441Srpaulo#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4513286441Srpaulo#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4514286441Srpaulo 4515286441Srpaulo#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4516286441Srpaulo#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4517286441Srpaulo 4518286441Srpaulo/** 4519286441Srpaulo * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4520286441Srpaulo * ( IWM_REPLY_TX = 0x1c ) 4521286441Srpaulo * @frame_count: 1 no aggregation, >1 aggregation 4522286441Srpaulo * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4523286441Srpaulo * @failure_rts: num of failures due to unsuccessful RTS 4524286441Srpaulo * @failure_frame: num failures due to no ACK (unused for agg) 4525286441Srpaulo * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4526286441Srpaulo * Tx of all the batch. IWM_RATE_MCS_* 4527286441Srpaulo * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4528286441Srpaulo * for agg: RTS + CTS + aggregation tx time + block-ack time. 4529286441Srpaulo * in usec. 4530286441Srpaulo * @pa_status: tx power info 4531286441Srpaulo * @pa_integ_res_a: tx power info 4532286441Srpaulo * @pa_integ_res_b: tx power info 4533286441Srpaulo * @pa_integ_res_c: tx power info 4534286441Srpaulo * @measurement_req_id: tx power info 4535286441Srpaulo * @tfd_info: TFD information set by the FH 4536286441Srpaulo * @seq_ctl: sequence control from the Tx cmd 4537286441Srpaulo * @byte_cnt: byte count from the Tx cmd 4538286441Srpaulo * @tlc_info: TLC rate info 4539286441Srpaulo * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4540286441Srpaulo * @frame_ctrl: frame control 4541286441Srpaulo * @status: for non-agg: frame status IWM_TX_STATUS_* 4542286441Srpaulo * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4543286441Srpaulo * follow this one, up to frame_count. 4544286441Srpaulo * 4545286441Srpaulo * After the array of statuses comes the SSN of the SCD. Look at 4546286441Srpaulo * %iwm_mvm_get_scd_ssn for more details. 4547286441Srpaulo */ 4548286441Srpaulostruct iwm_mvm_tx_resp { 4549286441Srpaulo uint8_t frame_count; 4550286441Srpaulo uint8_t bt_kill_count; 4551286441Srpaulo uint8_t failure_rts; 4552286441Srpaulo uint8_t failure_frame; 4553286441Srpaulo uint32_t initial_rate; 4554286441Srpaulo uint16_t wireless_media_time; 4555286441Srpaulo 4556286441Srpaulo uint8_t pa_status; 4557286441Srpaulo uint8_t pa_integ_res_a[3]; 4558286441Srpaulo uint8_t pa_integ_res_b[3]; 4559286441Srpaulo uint8_t pa_integ_res_c[3]; 4560286441Srpaulo uint16_t measurement_req_id; 4561286441Srpaulo uint16_t reserved; 4562286441Srpaulo 4563286441Srpaulo uint32_t tfd_info; 4564286441Srpaulo uint16_t seq_ctl; 4565286441Srpaulo uint16_t byte_cnt; 4566286441Srpaulo uint8_t tlc_info; 4567286441Srpaulo uint8_t ra_tid; 4568286441Srpaulo uint16_t frame_ctrl; 4569286441Srpaulo 4570286441Srpaulo struct iwm_agg_tx_status status; 4571286441Srpaulo} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4572286441Srpaulo 4573286441Srpaulo/** 4574286441Srpaulo * struct iwm_mvm_ba_notif - notifies about reception of BA 4575286441Srpaulo * ( IWM_BA_NOTIF = 0xc5 ) 4576286441Srpaulo * @sta_addr_lo32: lower 32 bits of the MAC address 4577286441Srpaulo * @sta_addr_hi16: upper 16 bits of the MAC address 4578286441Srpaulo * @sta_id: Index of recipient (BA-sending) station in fw's station table 4579286441Srpaulo * @tid: tid of the session 4580286441Srpaulo * @seq_ctl: 4581286441Srpaulo * @bitmap: the bitmap of the BA notification as seen in the air 4582286441Srpaulo * @scd_flow: the tx queue this BA relates to 4583286441Srpaulo * @scd_ssn: the index of the last contiguously sent packet 4584286441Srpaulo * @txed: number of Txed frames in this batch 4585286441Srpaulo * @txed_2_done: number of Acked frames in this batch 4586286441Srpaulo */ 4587286441Srpaulostruct iwm_mvm_ba_notif { 4588286441Srpaulo uint32_t sta_addr_lo32; 4589286441Srpaulo uint16_t sta_addr_hi16; 4590286441Srpaulo uint16_t reserved; 4591286441Srpaulo 4592286441Srpaulo uint8_t sta_id; 4593286441Srpaulo uint8_t tid; 4594286441Srpaulo uint16_t seq_ctl; 4595286441Srpaulo uint64_t bitmap; 4596286441Srpaulo uint16_t scd_flow; 4597286441Srpaulo uint16_t scd_ssn; 4598286441Srpaulo uint8_t txed; 4599286441Srpaulo uint8_t txed_2_done; 4600286441Srpaulo uint16_t reserved1; 4601286441Srpaulo} __packed; 4602286441Srpaulo 4603286441Srpaulo/* 4604286441Srpaulo * struct iwm_mac_beacon_cmd - beacon template command 4605286441Srpaulo * @tx: the tx commands associated with the beacon frame 4606286441Srpaulo * @template_id: currently equal to the mac context id of the coresponding 4607286441Srpaulo * mac. 4608286441Srpaulo * @tim_idx: the offset of the tim IE in the beacon 4609286441Srpaulo * @tim_size: the length of the tim IE 4610286441Srpaulo * @frame: the template of the beacon frame 4611286441Srpaulo */ 4612286441Srpaulostruct iwm_mac_beacon_cmd { 4613286441Srpaulo struct iwm_tx_cmd tx; 4614286441Srpaulo uint32_t template_id; 4615286441Srpaulo uint32_t tim_idx; 4616286441Srpaulo uint32_t tim_size; 4617286441Srpaulo struct ieee80211_frame frame[0]; 4618286441Srpaulo} __packed; 4619286441Srpaulo 4620286441Srpaulostruct iwm_beacon_notif { 4621286441Srpaulo struct iwm_mvm_tx_resp beacon_notify_hdr; 4622286441Srpaulo uint64_t tsf; 4623286441Srpaulo uint32_t ibss_mgr_status; 4624286441Srpaulo} __packed; 4625286441Srpaulo 4626286441Srpaulo/** 4627286441Srpaulo * enum iwm_dump_control - dump (flush) control flags 4628300050Seadler * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4629286441Srpaulo * and the TFD queues are empty. 4630286441Srpaulo */ 4631286441Srpauloenum iwm_dump_control { 4632286441Srpaulo IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4633286441Srpaulo}; 4634286441Srpaulo 4635286441Srpaulo/** 4636286441Srpaulo * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4637286441Srpaulo * @queues_ctl: bitmap of queues to flush 4638286441Srpaulo * @flush_ctl: control flags 4639286441Srpaulo * @reserved: reserved 4640286441Srpaulo */ 4641286441Srpaulostruct iwm_tx_path_flush_cmd { 4642286441Srpaulo uint32_t queues_ctl; 4643286441Srpaulo uint16_t flush_ctl; 4644286441Srpaulo uint16_t reserved; 4645286441Srpaulo} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4646286441Srpaulo 4647286441Srpaulo/** 4648286441Srpaulo * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4649286441Srpaulo * @tx_resp: the Tx response from the fw (agg or non-agg) 4650286441Srpaulo * 4651286441Srpaulo * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4652286441Srpaulo * it can't know that everything will go well until the end of the AMPDU, it 4653286441Srpaulo * can't know in advance the number of MPDUs that will be sent in the current 4654286441Srpaulo * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4655286441Srpaulo * Hence, it can't know in advance what the SSN of the SCD will be at the end 4656286441Srpaulo * of the batch. This is why the SSN of the SCD is written at the end of the 4657286441Srpaulo * whole struct at a variable offset. This function knows how to cope with the 4658286441Srpaulo * variable offset and returns the SSN of the SCD. 4659286441Srpaulo */ 4660286441Srpaulostatic inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4661286441Srpaulo{ 4662286441Srpaulo return le32_to_cpup((uint32_t *)&tx_resp->status + 4663286441Srpaulo tx_resp->frame_count) & 0xfff; 4664286441Srpaulo} 4665286441Srpaulo 4666286441Srpaulo/* 4667286441Srpaulo * END mvm/fw-api-tx.h 4668286441Srpaulo */ 4669286441Srpaulo 4670286441Srpaulo/* 4671286441Srpaulo * BEGIN mvm/fw-api-scan.h 4672286441Srpaulo */ 4673286441Srpaulo 4674303628Ssbruno/** 4675303628Ssbruno * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4676303628Ssbruno * @token: 4677303628Ssbruno * @sta_id: station id 4678303628Ssbruno * @tid: 4679303628Ssbruno * @scd_queue: scheduler queue to confiug 4680303628Ssbruno * @enable: 1 queue enable, 0 queue disable 4681303628Ssbruno * @aggregate: 1 aggregated queue, 0 otherwise 4682303628Ssbruno * @tx_fifo: %enum iwm_mvm_tx_fifo 4683303628Ssbruno * @window: BA window size 4684303628Ssbruno * @ssn: SSN for the BA agreement 4685303628Ssbruno */ 4686303628Ssbrunostruct iwm_scd_txq_cfg_cmd { 4687303628Ssbruno uint8_t token; 4688303628Ssbruno uint8_t sta_id; 4689303628Ssbruno uint8_t tid; 4690303628Ssbruno uint8_t scd_queue; 4691303628Ssbruno uint8_t enable; 4692303628Ssbruno uint8_t aggregate; 4693303628Ssbruno uint8_t tx_fifo; 4694303628Ssbruno uint8_t window; 4695303628Ssbruno uint16_t ssn; 4696303628Ssbruno uint16_t reserved; 4697303628Ssbruno} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4698303628Ssbruno 4699303628Ssbruno/** 4700303628Ssbruno * struct iwm_scd_txq_cfg_rsp 4701303628Ssbruno * @token: taken from the command 4702303628Ssbruno * @sta_id: station id from the command 4703303628Ssbruno * @tid: tid from the command 4704303628Ssbruno * @scd_queue: scd_queue from the command 4705303628Ssbruno */ 4706303628Ssbrunostruct iwm_scd_txq_cfg_rsp { 4707303628Ssbruno uint8_t token; 4708303628Ssbruno uint8_t sta_id; 4709303628Ssbruno uint8_t tid; 4710303628Ssbruno uint8_t scd_queue; 4711303628Ssbruno} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4712303628Ssbruno 4713303628Ssbruno 4714286441Srpaulo/* Scan Commands, Responses, Notifications */ 4715286441Srpaulo 4716286441Srpaulo/* Masks for iwm_scan_channel.type flags */ 4717286441Srpaulo#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4718305762Savos#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4719286441Srpaulo 4720286441Srpaulo/* Max number of IEs for direct SSID scans in a command */ 4721286441Srpaulo#define IWM_PROBE_OPTION_MAX 20 4722286441Srpaulo 4723286441Srpaulo/** 4724286441Srpaulo * struct iwm_ssid_ie - directed scan network information element 4725286441Srpaulo * 4726286441Srpaulo * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4727286441Srpaulo * selected by "type" bit field in struct iwm_scan_channel; 4728286441Srpaulo * each channel may select different ssids from among the 20 entries. 4729286441Srpaulo * SSID IEs get transmitted in reverse order of entry. 4730286441Srpaulo */ 4731286441Srpaulostruct iwm_ssid_ie { 4732286441Srpaulo uint8_t id; 4733286441Srpaulo uint8_t len; 4734286441Srpaulo uint8_t ssid[IEEE80211_NWID_LEN]; 4735286441Srpaulo} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4736286441Srpaulo 4737303628Ssbruno/* scan offload */ 4738303628Ssbruno#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4739303628Ssbruno#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4740303628Ssbruno#define IWM_SCAN_MAX_PROFILES 11 4741303628Ssbruno#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4742303628Ssbruno 4743303628Ssbruno/* Default watchdog (in MS) for scheduled scan iteration */ 4744303628Ssbruno#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4745303628Ssbruno 4746303628Ssbruno#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4747303628Ssbruno#define IWM_CAN_ABORT_STATUS 1 4748303628Ssbruno 4749303628Ssbruno#define IWM_FULL_SCAN_MULTIPLIER 5 4750303628Ssbruno#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4751303628Ssbruno#define IWM_MAX_SCHED_SCAN_PLANS 2 4752303628Ssbruno 4753286441Srpaulo/** 4754303628Ssbruno * iwm_scan_schedule_lmac - schedule of scan offload 4755303628Ssbruno * @delay: delay between iterations, in seconds. 4756303628Ssbruno * @iterations: num of scan iterations 4757303628Ssbruno * @full_scan_mul: number of partial scans before each full scan 4758286441Srpaulo */ 4759303628Ssbrunostruct iwm_scan_schedule_lmac { 4760303628Ssbruno uint16_t delay; 4761303628Ssbruno uint8_t iterations; 4762303628Ssbruno uint8_t full_scan_mul; 4763303628Ssbruno} __packed; /* SCAN_SCHEDULE_API_S */ 4764303628Ssbruno 4765303628Ssbruno/** 4766303628Ssbruno * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4767303628Ssbruno * @tx_flags: combination of TX_CMD_FLG_* 4768303628Ssbruno * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4769303628Ssbruno * cleared. Combination of RATE_MCS_* 4770303628Ssbruno * @sta_id: index of destination station in FW station table 4771303628Ssbruno * @reserved: for alignment and future use 4772303628Ssbruno */ 4773303628Ssbrunostruct iwm_scan_req_tx_cmd { 4774303628Ssbruno uint32_t tx_flags; 4775303628Ssbruno uint32_t rate_n_flags; 4776303628Ssbruno uint8_t sta_id; 4777303628Ssbruno uint8_t reserved[3]; 4778303628Ssbruno} __packed; 4779303628Ssbruno 4780303628Ssbrunoenum iwm_scan_channel_flags_lmac { 4781303628Ssbruno IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4782303628Ssbruno IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4783303628Ssbruno}; 4784303628Ssbruno 4785303628Ssbruno/** 4786303628Ssbruno * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4787303628Ssbruno * @flags: bits 1-20: directed scan to i'th ssid 4788303628Ssbruno * other bits &enum iwm_scan_channel_flags_lmac 4789303628Ssbruno * @channel_number: channel number 1-13 etc 4790303628Ssbruno * @iter_count: scan iteration on this channel 4791303628Ssbruno * @iter_interval: interval in seconds between iterations on one channel 4792303628Ssbruno */ 4793303628Ssbrunostruct iwm_scan_channel_cfg_lmac { 4794303628Ssbruno uint32_t flags; 4795303628Ssbruno uint16_t channel_num; 4796303628Ssbruno uint16_t iter_count; 4797303628Ssbruno uint32_t iter_interval; 4798303628Ssbruno} __packed; 4799303628Ssbruno 4800303628Ssbruno/* 4801303628Ssbruno * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4802303628Ssbruno * @offset: offset in the data block 4803303628Ssbruno * @len: length of the segment 4804303628Ssbruno */ 4805303628Ssbrunostruct iwm_scan_probe_segment { 4806303628Ssbruno uint16_t offset; 4807286441Srpaulo uint16_t len; 4808303628Ssbruno} __packed; 4809303628Ssbruno 4810303628Ssbruno/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4811303628Ssbruno * @mac_header: first (and common) part of the probe 4812303628Ssbruno * @band_data: band specific data 4813303628Ssbruno * @common_data: last (and common) part of the probe 4814303628Ssbruno * @buf: raw data block 4815303628Ssbruno */ 4816303628Ssbrunostruct iwm_scan_probe_req { 4817303628Ssbruno struct iwm_scan_probe_segment mac_header; 4818303628Ssbruno struct iwm_scan_probe_segment band_data[2]; 4819303628Ssbruno struct iwm_scan_probe_segment common_data; 4820303628Ssbruno uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4821303628Ssbruno} __packed; 4822303628Ssbruno 4823303628Ssbrunoenum iwm_scan_channel_flags { 4824303628Ssbruno IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4825303628Ssbruno IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4826303628Ssbruno IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4827303628Ssbruno}; 4828303628Ssbruno 4829303628Ssbruno/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4830303628Ssbruno * @flags: enum iwm_scan_channel_flags 4831303628Ssbruno * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4832303628Ssbruno * involved. 4833303628Ssbruno * 1 - EBS is disabled. 4834303628Ssbruno * 2 - every second scan will be full scan(and so on). 4835303628Ssbruno */ 4836303628Ssbrunostruct iwm_scan_channel_opt { 4837303628Ssbruno uint16_t flags; 4838303628Ssbruno uint16_t non_ebs_ratio; 4839303628Ssbruno} __packed; 4840303628Ssbruno 4841303628Ssbruno/** 4842303628Ssbruno * iwm_mvm_lmac_scan_flags 4843303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4844303628Ssbruno * without filtering. 4845303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4846303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4847303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4848303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4849303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4850303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4851303628Ssbruno * and DS parameter set IEs into probe requests. 4852303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4853303628Ssbruno * 1, 6 and 11. 4854303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4855303628Ssbruno */ 4856303628Ssbrunoenum iwm_mvm_lmac_scan_flags { 4857303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4858303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4859303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4860303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4861303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4862303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4863303628Ssbruno IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4864303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4865303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4866303628Ssbruno}; 4867303628Ssbruno 4868303628Ssbrunoenum iwm_scan_priority { 4869303628Ssbruno IWM_SCAN_PRIORITY_LOW, 4870303628Ssbruno IWM_SCAN_PRIORITY_MEDIUM, 4871303628Ssbruno IWM_SCAN_PRIORITY_HIGH, 4872303628Ssbruno}; 4873303628Ssbruno 4874303628Ssbruno/** 4875303628Ssbruno * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4876303628Ssbruno * @reserved1: for alignment and future use 4877303628Ssbruno * @channel_num: num of channels to scan 4878303628Ssbruno * @active-dwell: dwell time for active channels 4879303628Ssbruno * @passive-dwell: dwell time for passive channels 4880303628Ssbruno * @fragmented-dwell: dwell time for fragmented passive scan 4881303628Ssbruno * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4882303628Ssbruno * @reserved2: for alignment and future use 4883303628Ssbruno * @rx_chain_selct: PHY_RX_CHAIN_* flags 4884303628Ssbruno * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4885303628Ssbruno * @max_out_time: max time (in TU) to be out of associated channel 4886303628Ssbruno * @suspend_time: pause scan this long (TUs) when returning to service channel 4887303628Ssbruno * @flags: RXON flags 4888303628Ssbruno * @filter_flags: RXON filter 4889303628Ssbruno * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4890303628Ssbruno * @direct_scan: list of SSIDs for directed active scan 4891303628Ssbruno * @scan_prio: enum iwm_scan_priority 4892303628Ssbruno * @iter_num: number of scan iterations 4893303628Ssbruno * @delay: delay in seconds before first iteration 4894303628Ssbruno * @schedule: two scheduling plans. The first one is finite, the second one can 4895303628Ssbruno * be infinite. 4896303628Ssbruno * @channel_opt: channel optimization options, for full and partial scan 4897303628Ssbruno * @data: channel configuration and probe request packet. 4898303628Ssbruno */ 4899303628Ssbrunostruct iwm_scan_req_lmac { 4900303628Ssbruno /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4901303628Ssbruno uint32_t reserved1; 4902303628Ssbruno uint8_t n_channels; 4903303628Ssbruno uint8_t active_dwell; 4904303628Ssbruno uint8_t passive_dwell; 4905303628Ssbruno uint8_t fragmented_dwell; 4906303628Ssbruno uint8_t extended_dwell; 4907303628Ssbruno uint8_t reserved2; 4908303628Ssbruno uint16_t rx_chain_select; 4909303628Ssbruno uint32_t scan_flags; 4910286441Srpaulo uint32_t max_out_time; 4911286441Srpaulo uint32_t suspend_time; 4912303628Ssbruno /* RX_ON_FLAGS_API_S_VER_1 */ 4913303628Ssbruno uint32_t flags; 4914286441Srpaulo uint32_t filter_flags; 4915303628Ssbruno struct iwm_scan_req_tx_cmd tx_cmd[2]; 4916286441Srpaulo struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4917303628Ssbruno uint32_t scan_prio; 4918303628Ssbruno /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4919303628Ssbruno uint32_t iter_num; 4920303628Ssbruno uint32_t delay; 4921303628Ssbruno struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4922303628Ssbruno struct iwm_scan_channel_opt channel_opt[2]; 4923303628Ssbruno uint8_t data[]; 4924303628Ssbruno} __packed; 4925286441Srpaulo 4926303628Ssbruno/** 4927303628Ssbruno * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4928303628Ssbruno * @last_schedule_line: last schedule line executed (fast or regular) 4929303628Ssbruno * @last_schedule_iteration: last scan iteration executed before scan abort 4930303628Ssbruno * @status: enum iwm_scan_offload_complete_status 4931303628Ssbruno * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4932303628Ssbruno * @time_after_last_iter; time in seconds elapsed after last iteration 4933303628Ssbruno */ 4934303628Ssbrunostruct iwm_periodic_scan_complete { 4935303628Ssbruno uint8_t last_schedule_line; 4936303628Ssbruno uint8_t last_schedule_iteration; 4937303628Ssbruno uint8_t status; 4938303628Ssbruno uint8_t ebs_status; 4939303628Ssbruno uint32_t time_after_last_iter; 4940303628Ssbruno uint32_t reserved; 4941303628Ssbruno} __packed; 4942286441Srpaulo 4943286441Srpaulo/* How many statistics are gathered for each channel */ 4944286441Srpaulo#define IWM_SCAN_RESULTS_STATISTICS 1 4945286441Srpaulo 4946286441Srpaulo/** 4947286441Srpaulo * enum iwm_scan_complete_status - status codes for scan complete notifications 4948286441Srpaulo * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4949286441Srpaulo * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4950286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4951286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4952286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4953286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4954286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4955286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4956286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4957286441Srpaulo * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4958286441Srpaulo * (not an error!) 4959286441Srpaulo * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4960286441Srpaulo * asked for 4961286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4962286441Srpaulo*/ 4963286441Srpauloenum iwm_scan_complete_status { 4964286441Srpaulo IWM_SCAN_COMP_STATUS_OK = 0x1, 4965286441Srpaulo IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4966286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4967286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4968286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4969286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4970286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4971286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4972286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4973286441Srpaulo IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4974286441Srpaulo IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4975286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4976286441Srpaulo}; 4977286441Srpaulo 4978286441Srpaulo/** 4979286441Srpaulo * struct iwm_scan_results_notif - scan results for one channel 4980286441Srpaulo * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4981286441Srpaulo * @channel: which channel the results are from 4982286441Srpaulo * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4983286441Srpaulo * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4984286441Srpaulo * @num_probe_not_sent: # of request that weren't sent due to not enough time 4985286441Srpaulo * @duration: duration spent in channel, in usecs 4986286441Srpaulo * @statistics: statistics gathered for this channel 4987286441Srpaulo */ 4988286441Srpaulostruct iwm_scan_results_notif { 4989286441Srpaulo uint8_t channel; 4990286441Srpaulo uint8_t band; 4991286441Srpaulo uint8_t probe_status; 4992286441Srpaulo uint8_t num_probe_not_sent; 4993286441Srpaulo uint32_t duration; 4994286441Srpaulo uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 4995286441Srpaulo} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 4996286441Srpaulo 4997286441Srpauloenum iwm_scan_framework_client { 4998286441Srpaulo IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4999286441Srpaulo IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5000286441Srpaulo IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5001286441Srpaulo}; 5002286441Srpaulo 5003286441Srpaulo/** 5004286441Srpaulo * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5005286441Srpaulo * @ssid: MAC address to filter out 5006286441Srpaulo * @reported_rssi: AP rssi reported to the host 5007286441Srpaulo * @client_bitmap: clients ignore this entry - enum scan_framework_client 5008286441Srpaulo */ 5009286441Srpaulostruct iwm_scan_offload_blacklist { 5010286441Srpaulo uint8_t ssid[IEEE80211_ADDR_LEN]; 5011286441Srpaulo uint8_t reported_rssi; 5012286441Srpaulo uint8_t client_bitmap; 5013286441Srpaulo} __packed; 5014286441Srpaulo 5015286441Srpauloenum iwm_scan_offload_network_type { 5016286441Srpaulo IWM_NETWORK_TYPE_BSS = 1, 5017286441Srpaulo IWM_NETWORK_TYPE_IBSS = 2, 5018286441Srpaulo IWM_NETWORK_TYPE_ANY = 3, 5019286441Srpaulo}; 5020286441Srpaulo 5021286441Srpauloenum iwm_scan_offload_band_selection { 5022286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5023286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5024286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5025286441Srpaulo}; 5026286441Srpaulo 5027286441Srpaulo/** 5028286441Srpaulo * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5029286441Srpaulo * @ssid_index: index to ssid list in fixed part 5030286441Srpaulo * @unicast_cipher: encryption olgorithm to match - bitmap 5031286441Srpaulo * @aut_alg: authentication olgorithm to match - bitmap 5032286441Srpaulo * @network_type: enum iwm_scan_offload_network_type 5033286441Srpaulo * @band_selection: enum iwm_scan_offload_band_selection 5034286441Srpaulo * @client_bitmap: clients waiting for match - enum scan_framework_client 5035286441Srpaulo */ 5036286441Srpaulostruct iwm_scan_offload_profile { 5037286441Srpaulo uint8_t ssid_index; 5038286441Srpaulo uint8_t unicast_cipher; 5039286441Srpaulo uint8_t auth_alg; 5040286441Srpaulo uint8_t network_type; 5041286441Srpaulo uint8_t band_selection; 5042286441Srpaulo uint8_t client_bitmap; 5043286441Srpaulo uint8_t reserved[2]; 5044286441Srpaulo} __packed; 5045286441Srpaulo 5046286441Srpaulo/** 5047286441Srpaulo * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5048286441Srpaulo * @blaclist: AP list to filter off from scan results 5049286441Srpaulo * @profiles: profiles to search for match 5050286441Srpaulo * @blacklist_len: length of blacklist 5051286441Srpaulo * @num_profiles: num of profiles in the list 5052286441Srpaulo * @match_notify: clients waiting for match found notification 5053286441Srpaulo * @pass_match: clients waiting for the results 5054286441Srpaulo * @active_clients: active clients bitmap - enum scan_framework_client 5055286441Srpaulo * @any_beacon_notify: clients waiting for match notification without match 5056286441Srpaulo */ 5057286441Srpaulostruct iwm_scan_offload_profile_cfg { 5058286441Srpaulo struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5059286441Srpaulo uint8_t blacklist_len; 5060286441Srpaulo uint8_t num_profiles; 5061286441Srpaulo uint8_t match_notify; 5062286441Srpaulo uint8_t pass_match; 5063286441Srpaulo uint8_t active_clients; 5064286441Srpaulo uint8_t any_beacon_notify; 5065286441Srpaulo uint8_t reserved[2]; 5066286441Srpaulo} __packed; 5067286441Srpaulo 5068330151Seadlerenum iwm_scan_offload_complete_status { 5069286441Srpaulo IWM_SCAN_OFFLOAD_COMPLETED = 1, 5070286441Srpaulo IWM_SCAN_OFFLOAD_ABORTED = 2, 5071286441Srpaulo}; 5072286441Srpaulo 5073286441Srpaulo/** 5074303628Ssbruno * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5075303628Ssbruno * SCAN_COMPLETE_NTF_API_S_VER_3 5076303628Ssbruno * @scanned_channels: number of channels scanned (and number of valid results) 5077303628Ssbruno * @status: one of SCAN_COMP_STATUS_* 5078303628Ssbruno * @bt_status: BT on/off status 5079303628Ssbruno * @last_channel: last channel that was scanned 5080303628Ssbruno * @tsf_low: TSF timer (lower half) in usecs 5081303628Ssbruno * @tsf_high: TSF timer (higher half) in usecs 5082303628Ssbruno * @results: an array of scan results, only "scanned_channels" of them are valid 5083303628Ssbruno */ 5084303628Ssbrunostruct iwm_lmac_scan_complete_notif { 5085303628Ssbruno uint8_t scanned_channels; 5086303628Ssbruno uint8_t status; 5087303628Ssbruno uint8_t bt_status; 5088303628Ssbruno uint8_t last_channel; 5089303628Ssbruno uint32_t tsf_low; 5090303628Ssbruno uint32_t tsf_high; 5091303628Ssbruno struct iwm_scan_results_notif results[]; 5092303628Ssbruno} __packed; 5093303628Ssbruno 5094303628Ssbruno 5095286441Srpaulo/* 5096286441Srpaulo * END mvm/fw-api-scan.h 5097286441Srpaulo */ 5098286441Srpaulo 5099286441Srpaulo/* 5100286441Srpaulo * BEGIN mvm/fw-api-sta.h 5101286441Srpaulo */ 5102286441Srpaulo 5103303628Ssbruno/* UMAC Scan API */ 5104303628Ssbruno 5105303628Ssbruno/* The maximum of either of these cannot exceed 8, because we use an 5106303628Ssbruno * 8-bit mask (see IWM_MVM_SCAN_MASK). 5107303628Ssbruno */ 5108303628Ssbruno#define IWM_MVM_MAX_UMAC_SCANS 8 5109303628Ssbruno#define IWM_MVM_MAX_LMAC_SCANS 1 5110303628Ssbruno 5111303628Ssbrunoenum iwm_scan_config_flags { 5112303628Ssbruno IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5113303628Ssbruno IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5114303628Ssbruno IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5115303628Ssbruno IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5116303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5117303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5118303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5119303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5120303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5121303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5122303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5123303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5124303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5125303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5126303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5127303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5128303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5129303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5130303628Ssbruno 5131303628Ssbruno /* Bits 26-31 are for num of channels in channel_array */ 5132303628Ssbruno#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5133303628Ssbruno}; 5134303628Ssbruno 5135303628Ssbrunoenum iwm_scan_config_rates { 5136303628Ssbruno /* OFDM basic rates */ 5137303628Ssbruno IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5138303628Ssbruno IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5139303628Ssbruno IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5140303628Ssbruno IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5141303628Ssbruno IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5142303628Ssbruno IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5143303628Ssbruno IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5144303628Ssbruno IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5145303628Ssbruno /* CCK basic rates */ 5146303628Ssbruno IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5147303628Ssbruno IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5148303628Ssbruno IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5149303628Ssbruno IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5150303628Ssbruno 5151303628Ssbruno /* Bits 16-27 are for supported rates */ 5152303628Ssbruno#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5153303628Ssbruno}; 5154303628Ssbruno 5155303628Ssbrunoenum iwm_channel_flags { 5156303628Ssbruno IWM_CHANNEL_FLAG_EBS = (1 << 0), 5157303628Ssbruno IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5158303628Ssbruno IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5159303628Ssbruno IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5160303628Ssbruno}; 5161303628Ssbruno 5162286441Srpaulo/** 5163303628Ssbruno * struct iwm_scan_config 5164303628Ssbruno * @flags: enum scan_config_flags 5165303628Ssbruno * @tx_chains: valid_tx antenna - ANT_* definitions 5166303628Ssbruno * @rx_chains: valid_rx antenna - ANT_* definitions 5167303628Ssbruno * @legacy_rates: default legacy rates - enum scan_config_rates 5168303628Ssbruno * @out_of_channel_time: default max out of serving channel time 5169303628Ssbruno * @suspend_time: default max suspend time 5170303628Ssbruno * @dwell_active: default dwell time for active scan 5171303628Ssbruno * @dwell_passive: default dwell time for passive scan 5172303628Ssbruno * @dwell_fragmented: default dwell time for fragmented scan 5173303628Ssbruno * @dwell_extended: default dwell time for channels 1, 6 and 11 5174303628Ssbruno * @mac_addr: default mac address to be used in probes 5175303628Ssbruno * @bcast_sta_id: the index of the station in the fw 5176303628Ssbruno * @channel_flags: default channel flags - enum iwm_channel_flags 5177303628Ssbruno * scan_config_channel_flag 5178303628Ssbruno * @channel_array: default supported channels 5179303628Ssbruno */ 5180303628Ssbrunostruct iwm_scan_config { 5181303628Ssbruno uint32_t flags; 5182303628Ssbruno uint32_t tx_chains; 5183303628Ssbruno uint32_t rx_chains; 5184303628Ssbruno uint32_t legacy_rates; 5185303628Ssbruno uint32_t out_of_channel_time; 5186303628Ssbruno uint32_t suspend_time; 5187303628Ssbruno uint8_t dwell_active; 5188303628Ssbruno uint8_t dwell_passive; 5189303628Ssbruno uint8_t dwell_fragmented; 5190303628Ssbruno uint8_t dwell_extended; 5191303628Ssbruno uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5192303628Ssbruno uint8_t bcast_sta_id; 5193303628Ssbruno uint8_t channel_flags; 5194303628Ssbruno uint8_t channel_array[]; 5195303628Ssbruno} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5196303628Ssbruno 5197303628Ssbruno/** 5198303628Ssbruno * iwm_umac_scan_flags 5199303628Ssbruno *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5200303628Ssbruno * can be preempted by other scan requests with higher priority. 5201303628Ssbruno * The low priority scan will be resumed when the higher proirity scan is 5202303628Ssbruno * completed. 5203303628Ssbruno *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5204303628Ssbruno * when scan starts. 5205303628Ssbruno */ 5206303628Ssbrunoenum iwm_umac_scan_flags { 5207303628Ssbruno IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5208303628Ssbruno IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5209303628Ssbruno}; 5210303628Ssbruno 5211303628Ssbrunoenum iwm_umac_scan_uid_offsets { 5212303628Ssbruno IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5213303628Ssbruno IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5214303628Ssbruno}; 5215303628Ssbruno 5216303628Ssbrunoenum iwm_umac_scan_general_flags { 5217303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5218303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5219303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5220303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5221303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5222303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5223303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5224303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5225303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5226303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5227303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5228303628Ssbruno}; 5229303628Ssbruno 5230303628Ssbruno/** 5231303628Ssbruno * struct iwm_scan_channel_cfg_umac 5232303628Ssbruno * @flags: bitmap - 0-19: directed scan to i'th ssid. 5233303628Ssbruno * @channel_num: channel number 1-13 etc. 5234303628Ssbruno * @iter_count: repetition count for the channel. 5235303628Ssbruno * @iter_interval: interval between two scan iterations on one channel. 5236303628Ssbruno */ 5237303628Ssbrunostruct iwm_scan_channel_cfg_umac { 5238303628Ssbruno uint32_t flags; 5239305762Savos#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5240305762Savos 5241303628Ssbruno uint8_t channel_num; 5242303628Ssbruno uint8_t iter_count; 5243303628Ssbruno uint16_t iter_interval; 5244303628Ssbruno} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5245303628Ssbruno 5246303628Ssbruno/** 5247303628Ssbruno * struct iwm_scan_umac_schedule 5248303628Ssbruno * @interval: interval in seconds between scan iterations 5249303628Ssbruno * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5250303628Ssbruno * @reserved: for alignment and future use 5251303628Ssbruno */ 5252303628Ssbrunostruct iwm_scan_umac_schedule { 5253303628Ssbruno uint16_t interval; 5254303628Ssbruno uint8_t iter_count; 5255303628Ssbruno uint8_t reserved; 5256303628Ssbruno} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5257303628Ssbruno 5258303628Ssbruno/** 5259303628Ssbruno * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5260303628Ssbruno * parameters following channels configuration array. 5261303628Ssbruno * @schedule: two scheduling plans. 5262303628Ssbruno * @delay: delay in TUs before starting the first scan iteration 5263303628Ssbruno * @reserved: for future use and alignment 5264303628Ssbruno * @preq: probe request with IEs blocks 5265303628Ssbruno * @direct_scan: list of SSIDs for directed active scan 5266303628Ssbruno */ 5267303628Ssbrunostruct iwm_scan_req_umac_tail { 5268303628Ssbruno /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5269303628Ssbruno struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5270303628Ssbruno uint16_t delay; 5271303628Ssbruno uint16_t reserved; 5272303628Ssbruno /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5273303628Ssbruno struct iwm_scan_probe_req preq; 5274303628Ssbruno struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5275303628Ssbruno} __packed; 5276303628Ssbruno 5277303628Ssbruno/** 5278303628Ssbruno * struct iwm_scan_req_umac 5279303628Ssbruno * @flags: &enum iwm_umac_scan_flags 5280303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5281303628Ssbruno * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5282303628Ssbruno * @general_flags: &enum iwm_umac_scan_general_flags 5283303628Ssbruno * @extended_dwell: dwell time for channels 1, 6 and 11 5284303628Ssbruno * @active_dwell: dwell time for active scan 5285303628Ssbruno * @passive_dwell: dwell time for passive scan 5286303628Ssbruno * @fragmented_dwell: dwell time for fragmented passive scan 5287303628Ssbruno * @max_out_time: max out of serving channel time 5288303628Ssbruno * @suspend_time: max suspend time 5289303628Ssbruno * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5290303628Ssbruno * @channel_flags: &enum iwm_scan_channel_flags 5291303628Ssbruno * @n_channels: num of channels in scan request 5292303628Ssbruno * @reserved: for future use and alignment 5293303628Ssbruno * @data: &struct iwm_scan_channel_cfg_umac and 5294303628Ssbruno * &struct iwm_scan_req_umac_tail 5295303628Ssbruno */ 5296303628Ssbrunostruct iwm_scan_req_umac { 5297303628Ssbruno uint32_t flags; 5298303628Ssbruno uint32_t uid; 5299303628Ssbruno uint32_t ooc_priority; 5300303628Ssbruno /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5301303628Ssbruno uint32_t general_flags; 5302303628Ssbruno uint8_t extended_dwell; 5303303628Ssbruno uint8_t active_dwell; 5304303628Ssbruno uint8_t passive_dwell; 5305303628Ssbruno uint8_t fragmented_dwell; 5306303628Ssbruno uint32_t max_out_time; 5307303628Ssbruno uint32_t suspend_time; 5308303628Ssbruno uint32_t scan_priority; 5309303628Ssbruno /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5310303628Ssbruno uint8_t channel_flags; 5311303628Ssbruno uint8_t n_channels; 5312303628Ssbruno uint16_t reserved; 5313303628Ssbruno uint8_t data[]; 5314303628Ssbruno} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5315303628Ssbruno 5316303628Ssbruno/** 5317303628Ssbruno * struct iwm_umac_scan_abort 5318303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5319303628Ssbruno * @flags: reserved 5320303628Ssbruno */ 5321303628Ssbrunostruct iwm_umac_scan_abort { 5322303628Ssbruno uint32_t uid; 5323303628Ssbruno uint32_t flags; 5324303628Ssbruno} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5325303628Ssbruno 5326303628Ssbruno/** 5327303628Ssbruno * struct iwm_umac_scan_complete 5328303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5329303628Ssbruno * @last_schedule: last scheduling line 5330303628Ssbruno * @last_iter: last scan iteration number 5331303628Ssbruno * @scan status: &enum iwm_scan_offload_complete_status 5332303628Ssbruno * @ebs_status: &enum iwm_scan_ebs_status 5333303628Ssbruno * @time_from_last_iter: time elapsed from last iteration 5334303628Ssbruno * @reserved: for future use 5335303628Ssbruno */ 5336303628Ssbrunostruct iwm_umac_scan_complete { 5337303628Ssbruno uint32_t uid; 5338303628Ssbruno uint8_t last_schedule; 5339303628Ssbruno uint8_t last_iter; 5340303628Ssbruno uint8_t status; 5341303628Ssbruno uint8_t ebs_status; 5342303628Ssbruno uint32_t time_from_last_iter; 5343303628Ssbruno uint32_t reserved; 5344303628Ssbruno} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5345303628Ssbruno 5346303628Ssbruno#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5347303628Ssbruno/** 5348303628Ssbruno * struct iwm_scan_offload_profile_match - match information 5349303628Ssbruno * @bssid: matched bssid 5350303628Ssbruno * @channel: channel where the match occurred 5351303628Ssbruno * @energy: 5352303628Ssbruno * @matching_feature: 5353303628Ssbruno * @matching_channels: bitmap of channels that matched, referencing 5354303628Ssbruno * the channels passed in tue scan offload request 5355303628Ssbruno */ 5356303628Ssbrunostruct iwm_scan_offload_profile_match { 5357303628Ssbruno uint8_t bssid[IEEE80211_ADDR_LEN]; 5358303628Ssbruno uint16_t reserved; 5359303628Ssbruno uint8_t channel; 5360303628Ssbruno uint8_t energy; 5361303628Ssbruno uint8_t matching_feature; 5362303628Ssbruno uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5363303628Ssbruno} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5364303628Ssbruno 5365303628Ssbruno/** 5366303628Ssbruno * struct iwm_scan_offload_profiles_query - match results query response 5367303628Ssbruno * @matched_profiles: bitmap of matched profiles, referencing the 5368303628Ssbruno * matches passed in the scan offload request 5369303628Ssbruno * @last_scan_age: age of the last offloaded scan 5370303628Ssbruno * @n_scans_done: number of offloaded scans done 5371303628Ssbruno * @gp2_d0u: GP2 when D0U occurred 5372303628Ssbruno * @gp2_invoked: GP2 when scan offload was invoked 5373303628Ssbruno * @resume_while_scanning: not used 5374303628Ssbruno * @self_recovery: obsolete 5375303628Ssbruno * @reserved: reserved 5376303628Ssbruno * @matches: array of match information, one for each match 5377303628Ssbruno */ 5378303628Ssbrunostruct iwm_scan_offload_profiles_query { 5379303628Ssbruno uint32_t matched_profiles; 5380303628Ssbruno uint32_t last_scan_age; 5381303628Ssbruno uint32_t n_scans_done; 5382303628Ssbruno uint32_t gp2_d0u; 5383303628Ssbruno uint32_t gp2_invoked; 5384303628Ssbruno uint8_t resume_while_scanning; 5385303628Ssbruno uint8_t self_recovery; 5386303628Ssbruno uint16_t reserved; 5387303628Ssbruno struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5388303628Ssbruno} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5389303628Ssbruno 5390303628Ssbruno/** 5391303628Ssbruno * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5392303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5393303628Ssbruno * @scanned_channels: number of channels scanned and number of valid elements in 5394303628Ssbruno * results array 5395303628Ssbruno * @status: one of SCAN_COMP_STATUS_* 5396303628Ssbruno * @bt_status: BT on/off status 5397303628Ssbruno * @last_channel: last channel that was scanned 5398303628Ssbruno * @tsf_low: TSF timer (lower half) in usecs 5399303628Ssbruno * @tsf_high: TSF timer (higher half) in usecs 5400303628Ssbruno * @results: array of scan results, only "scanned_channels" of them are valid 5401303628Ssbruno */ 5402303628Ssbrunostruct iwm_umac_scan_iter_complete_notif { 5403303628Ssbruno uint32_t uid; 5404303628Ssbruno uint8_t scanned_channels; 5405303628Ssbruno uint8_t status; 5406303628Ssbruno uint8_t bt_status; 5407303628Ssbruno uint8_t last_channel; 5408303628Ssbruno uint32_t tsf_low; 5409303628Ssbruno uint32_t tsf_high; 5410303628Ssbruno struct iwm_scan_results_notif results[]; 5411303628Ssbruno} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5412303628Ssbruno 5413303628Ssbruno/* Please keep this enum *SORTED* by hex value. 5414303628Ssbruno * Needed for binary search, otherwise a warning will be triggered. 5415303628Ssbruno */ 5416303628Ssbrunoenum iwm_scan_subcmd_ids { 5417303628Ssbruno IWM_GSCAN_START_CMD = 0x0, 5418303628Ssbruno IWM_GSCAN_STOP_CMD = 0x1, 5419303628Ssbruno IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5420303628Ssbruno IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5421303628Ssbruno IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5422303628Ssbruno IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5423303628Ssbruno IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5424303628Ssbruno IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5425303628Ssbruno IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5426303628Ssbruno}; 5427303628Ssbruno 5428303628Ssbruno/* STA API */ 5429303628Ssbruno 5430303628Ssbruno/** 5431286441Srpaulo * enum iwm_sta_flags - flags for the ADD_STA host command 5432286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5433286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5434303628Ssbruno * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5435286441Srpaulo * @IWM_STA_FLG_PS: set if STA is in Power Save 5436286441Srpaulo * @IWM_STA_FLG_INVALID: set if STA is invalid 5437286441Srpaulo * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5438286441Srpaulo * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5439286441Srpaulo * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5440286441Srpaulo * @IWM_STA_FLG_PAN: STA is for PAN interface 5441286441Srpaulo * @IWM_STA_FLG_CLASS_AUTH: 5442286441Srpaulo * @IWM_STA_FLG_CLASS_ASSOC: 5443286441Srpaulo * @IWM_STA_FLG_CLASS_MIMO_PROT: 5444286441Srpaulo * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5445286441Srpaulo * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5446286441Srpaulo * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5447286441Srpaulo * initialised by driver and can be updated by fw upon reception of 5448286441Srpaulo * action frames that can change the channel width. When cleared the fw 5449286441Srpaulo * will send all the frames in 20MHz even when FAT channel is requested. 5450286441Srpaulo * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5451286441Srpaulo * driver and can be updated by fw upon reception of action frames. 5452286441Srpaulo * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5453286441Srpaulo */ 5454286441Srpauloenum iwm_sta_flags { 5455286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5456286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5457286441Srpaulo 5458303628Ssbruno IWM_STA_FLG_DISABLE_TX = (1 << 4), 5459286441Srpaulo 5460286441Srpaulo IWM_STA_FLG_PS = (1 << 8), 5461286441Srpaulo IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5462286441Srpaulo IWM_STA_FLG_PAN = (1 << 13), 5463286441Srpaulo IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5464286441Srpaulo IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5465286441Srpaulo IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5466286441Srpaulo 5467286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5468286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5469286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5470286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5471286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5472286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5473286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5474286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5475286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5476286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5477286441Srpaulo 5478286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5479286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5480286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5481286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5482286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5483286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5484286441Srpaulo 5485286441Srpaulo IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5486286441Srpaulo IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5487286441Srpaulo IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5488286441Srpaulo IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5489286441Srpaulo IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5490286441Srpaulo 5491286441Srpaulo IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5492286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5493286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5494286441Srpaulo IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5495286441Srpaulo}; 5496286441Srpaulo 5497286441Srpaulo/** 5498286441Srpaulo * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5499286441Srpaulo * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5500286441Srpaulo * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5501286441Srpaulo * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5502286441Srpaulo * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5503286441Srpaulo * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5504286441Srpaulo * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5505286441Srpaulo * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5506286441Srpaulo * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5507286441Srpaulo * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5508286441Srpaulo * station info array (1 - n 1X mode) 5509286441Srpaulo * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5510286441Srpaulo * @IWM_STA_KEY_NOT_VALID: key is invalid 5511286441Srpaulo * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5512286441Srpaulo * @IWM_STA_KEY_MULTICAST: set for multical key 5513286441Srpaulo * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5514286441Srpaulo */ 5515286441Srpauloenum iwm_sta_key_flag { 5516286441Srpaulo IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5517286441Srpaulo IWM_STA_KEY_FLG_WEP = (1 << 0), 5518286441Srpaulo IWM_STA_KEY_FLG_CCM = (2 << 0), 5519286441Srpaulo IWM_STA_KEY_FLG_TKIP = (3 << 0), 5520286441Srpaulo IWM_STA_KEY_FLG_EXT = (4 << 0), 5521286441Srpaulo IWM_STA_KEY_FLG_CMAC = (6 << 0), 5522286441Srpaulo IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5523286441Srpaulo IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5524286441Srpaulo 5525286441Srpaulo IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5526286441Srpaulo IWM_STA_KEY_FLG_KEYID_POS = 8, 5527286441Srpaulo IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5528286441Srpaulo IWM_STA_KEY_NOT_VALID = (1 << 11), 5529286441Srpaulo IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5530286441Srpaulo IWM_STA_KEY_MULTICAST = (1 << 14), 5531286441Srpaulo IWM_STA_KEY_MFP = (1 << 15), 5532286441Srpaulo}; 5533286441Srpaulo 5534286441Srpaulo/** 5535286441Srpaulo * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5536303628Ssbruno * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5537286441Srpaulo * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5538286441Srpaulo * @IWM_STA_MODIFY_TX_RATE: unused 5539286441Srpaulo * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5540286441Srpaulo * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5541286441Srpaulo * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5542286441Srpaulo * @IWM_STA_MODIFY_PROT_TH: 5543286441Srpaulo * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5544286441Srpaulo */ 5545286441Srpauloenum iwm_sta_modify_flag { 5546303628Ssbruno IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5547286441Srpaulo IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5548286441Srpaulo IWM_STA_MODIFY_TX_RATE = (1 << 2), 5549286441Srpaulo IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5550286441Srpaulo IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5551286441Srpaulo IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5552286441Srpaulo IWM_STA_MODIFY_PROT_TH = (1 << 6), 5553286441Srpaulo IWM_STA_MODIFY_QUEUES = (1 << 7), 5554286441Srpaulo}; 5555286441Srpaulo 5556286441Srpaulo#define IWM_STA_MODE_MODIFY 1 5557286441Srpaulo 5558286441Srpaulo/** 5559286441Srpaulo * enum iwm_sta_sleep_flag - type of sleep of the station 5560286441Srpaulo * @IWM_STA_SLEEP_STATE_AWAKE: 5561286441Srpaulo * @IWM_STA_SLEEP_STATE_PS_POLL: 5562286441Srpaulo * @IWM_STA_SLEEP_STATE_UAPSD: 5563303628Ssbruno * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5564303628Ssbruno * (last) released frame 5565286441Srpaulo */ 5566286441Srpauloenum iwm_sta_sleep_flag { 5567286441Srpaulo IWM_STA_SLEEP_STATE_AWAKE = 0, 5568286441Srpaulo IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5569286441Srpaulo IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5570303628Ssbruno IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5571286441Srpaulo}; 5572286441Srpaulo 5573286441Srpaulo/* STA ID and color bits definitions */ 5574286441Srpaulo#define IWM_STA_ID_SEED (0x0f) 5575286441Srpaulo#define IWM_STA_ID_POS (0) 5576286441Srpaulo#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5577286441Srpaulo 5578286441Srpaulo#define IWM_STA_COLOR_SEED (0x7) 5579286441Srpaulo#define IWM_STA_COLOR_POS (4) 5580286441Srpaulo#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5581286441Srpaulo 5582286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5583286441Srpaulo (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5584286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5585286441Srpaulo (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5586286441Srpaulo 5587286441Srpaulo#define IWM_STA_KEY_MAX_NUM (16) 5588286441Srpaulo#define IWM_STA_KEY_IDX_INVALID (0xff) 5589286441Srpaulo#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5590286441Srpaulo#define IWM_MAX_GLOBAL_KEYS (4) 5591286441Srpaulo#define IWM_STA_KEY_LEN_WEP40 (5) 5592286441Srpaulo#define IWM_STA_KEY_LEN_WEP104 (13) 5593286441Srpaulo 5594286441Srpaulo/** 5595286441Srpaulo * struct iwm_mvm_keyinfo - key information 5596286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5597286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5598286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5599286441Srpaulo * @key_offset: key offset in the fw's key table 5600286441Srpaulo * @key: 16-byte unicast decryption key 5601286441Srpaulo * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5602286441Srpaulo * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5603286441Srpaulo * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5604286441Srpaulo */ 5605286441Srpaulostruct iwm_mvm_keyinfo { 5606286441Srpaulo uint16_t key_flags; 5607286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5608286441Srpaulo uint8_t reserved1; 5609286441Srpaulo uint16_t tkip_rx_ttak[5]; 5610286441Srpaulo uint8_t key_offset; 5611286441Srpaulo uint8_t reserved2; 5612286441Srpaulo uint8_t key[16]; 5613286441Srpaulo uint64_t tx_secur_seq_cnt; 5614286441Srpaulo uint64_t hw_tkip_mic_rx_key; 5615286441Srpaulo uint64_t hw_tkip_mic_tx_key; 5616286441Srpaulo} __packed; 5617286441Srpaulo 5618303628Ssbruno#define IWM_ADD_STA_STATUS_MASK 0xFF 5619303628Ssbruno#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5620303628Ssbruno#define IWM_ADD_STA_BAID_MASK 0x7F00 5621303628Ssbruno#define IWM_ADD_STA_BAID_SHIFT 8 5622303628Ssbruno 5623286441Srpaulo/** 5624330195Seadler * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5625303628Ssbruno * ( REPLY_ADD_STA = 0x18 ) 5626286441Srpaulo * @add_modify: 1: modify existing, 0: add new station 5627303628Ssbruno * @awake_acs: 5628303628Ssbruno * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5629303628Ssbruno * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5630286441Srpaulo * @mac_id_n_color: the Mac context this station belongs to 5631286441Srpaulo * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5632286441Srpaulo * @sta_id: index of station in uCode's station table 5633286441Srpaulo * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5634286441Srpaulo * alone. 1 - modify, 0 - don't change. 5635286441Srpaulo * @station_flags: look at %iwm_sta_flags 5636286441Srpaulo * @station_flags_msk: what of %station_flags have changed 5637286441Srpaulo * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5638286441Srpaulo * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5639286441Srpaulo * add_immediate_ba_ssn. 5640286441Srpaulo * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5641286441Srpaulo * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5642286441Srpaulo * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5643286441Srpaulo * add_immediate_ba_tid. 5644286441Srpaulo * @sleep_tx_count: number of packets to transmit to station even though it is 5645286441Srpaulo * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5646286441Srpaulo * keeps track of STA sleep state. 5647286441Srpaulo * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5648286441Srpaulo * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5649286441Srpaulo * mac-addr. 5650286441Srpaulo * @beamform_flags: beam forming controls 5651286441Srpaulo * @tfd_queue_msk: tfd queues used by this station 5652286441Srpaulo * 5653286441Srpaulo * The device contains an internal table of per-station information, with info 5654286441Srpaulo * on security keys, aggregation parameters, and Tx rates for initial Tx 5655286441Srpaulo * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5656286441Srpaulo * 5657286441Srpaulo * ADD_STA sets up the table entry for one station, either creating a new 5658286441Srpaulo * entry, or modifying a pre-existing one. 5659286441Srpaulo */ 5660330195Seadlerstruct iwm_mvm_add_sta_cmd { 5661286441Srpaulo uint8_t add_modify; 5662303628Ssbruno uint8_t awake_acs; 5663286441Srpaulo uint16_t tid_disable_tx; 5664286441Srpaulo uint32_t mac_id_n_color; 5665286441Srpaulo uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5666286441Srpaulo uint16_t reserved2; 5667286441Srpaulo uint8_t sta_id; 5668286441Srpaulo uint8_t modify_mask; 5669286441Srpaulo uint16_t reserved3; 5670286441Srpaulo uint32_t station_flags; 5671286441Srpaulo uint32_t station_flags_msk; 5672286441Srpaulo uint8_t add_immediate_ba_tid; 5673286441Srpaulo uint8_t remove_immediate_ba_tid; 5674286441Srpaulo uint16_t add_immediate_ba_ssn; 5675286441Srpaulo uint16_t sleep_tx_count; 5676286441Srpaulo uint16_t sleep_state_flags; 5677286441Srpaulo uint16_t assoc_id; 5678286441Srpaulo uint16_t beamform_flags; 5679286441Srpaulo uint32_t tfd_queue_msk; 5680303628Ssbruno} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5681286441Srpaulo 5682286441Srpaulo/** 5683286441Srpaulo * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5684286441Srpaulo * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5685286441Srpaulo * @sta_id: index of station in uCode's station table 5686286441Srpaulo * @key_offset: key offset in key storage 5687286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5688286441Srpaulo * @key: key material data 5689286441Srpaulo * @key2: key material data 5690286441Srpaulo * @rx_secur_seq_cnt: RX security sequence counter for the key 5691286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5692286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5693286441Srpaulo */ 5694286441Srpaulostruct iwm_mvm_add_sta_key_cmd { 5695286441Srpaulo uint8_t sta_id; 5696286441Srpaulo uint8_t key_offset; 5697286441Srpaulo uint16_t key_flags; 5698286441Srpaulo uint8_t key[16]; 5699286441Srpaulo uint8_t key2[16]; 5700286441Srpaulo uint8_t rx_secur_seq_cnt[16]; 5701286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5702286441Srpaulo uint8_t reserved; 5703286441Srpaulo uint16_t tkip_rx_ttak[5]; 5704286441Srpaulo} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5705286441Srpaulo 5706286441Srpaulo/** 5707286441Srpaulo * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5708286441Srpaulo * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5709286441Srpaulo * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5710286441Srpaulo * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5711286441Srpaulo * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5712286441Srpaulo * that doesn't exist. 5713286441Srpaulo */ 5714286441Srpauloenum iwm_mvm_add_sta_rsp_status { 5715286441Srpaulo IWM_ADD_STA_SUCCESS = 0x1, 5716286441Srpaulo IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5717286441Srpaulo IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5718286441Srpaulo IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5719286441Srpaulo}; 5720286441Srpaulo 5721286441Srpaulo/** 5722286441Srpaulo * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5723286441Srpaulo * ( IWM_REMOVE_STA = 0x19 ) 5724286441Srpaulo * @sta_id: the station id of the station to be removed 5725286441Srpaulo */ 5726286441Srpaulostruct iwm_mvm_rm_sta_cmd { 5727286441Srpaulo uint8_t sta_id; 5728286441Srpaulo uint8_t reserved[3]; 5729286441Srpaulo} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5730286441Srpaulo 5731286441Srpaulo/** 5732286441Srpaulo * struct iwm_mvm_mgmt_mcast_key_cmd 5733286441Srpaulo * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5734286441Srpaulo * @ctrl_flags: %iwm_sta_key_flag 5735286441Srpaulo * @IGTK: 5736286441Srpaulo * @K1: IGTK master key 5737286441Srpaulo * @K2: IGTK sub key 5738286441Srpaulo * @sta_id: station ID that support IGTK 5739286441Srpaulo * @key_id: 5740286441Srpaulo * @receive_seq_cnt: initial RSC/PN needed for replay check 5741286441Srpaulo */ 5742286441Srpaulostruct iwm_mvm_mgmt_mcast_key_cmd { 5743286441Srpaulo uint32_t ctrl_flags; 5744286441Srpaulo uint8_t IGTK[16]; 5745286441Srpaulo uint8_t K1[16]; 5746286441Srpaulo uint8_t K2[16]; 5747286441Srpaulo uint32_t key_id; 5748286441Srpaulo uint32_t sta_id; 5749286441Srpaulo uint64_t receive_seq_cnt; 5750286441Srpaulo} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5751286441Srpaulo 5752286441Srpaulostruct iwm_mvm_wep_key { 5753286441Srpaulo uint8_t key_index; 5754286441Srpaulo uint8_t key_offset; 5755286441Srpaulo uint16_t reserved1; 5756286441Srpaulo uint8_t key_size; 5757286441Srpaulo uint8_t reserved2[3]; 5758286441Srpaulo uint8_t key[16]; 5759286441Srpaulo} __packed; 5760286441Srpaulo 5761286441Srpaulostruct iwm_mvm_wep_key_cmd { 5762286441Srpaulo uint32_t mac_id_n_color; 5763286441Srpaulo uint8_t num_keys; 5764286441Srpaulo uint8_t decryption_type; 5765286441Srpaulo uint8_t flags; 5766286441Srpaulo uint8_t reserved; 5767286441Srpaulo struct iwm_mvm_wep_key wep_key[0]; 5768286441Srpaulo} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5769286441Srpaulo 5770286441Srpaulo/* 5771286441Srpaulo * END mvm/fw-api-sta.h 5772286441Srpaulo */ 5773286441Srpaulo 5774286441Srpaulo/* 5775303628Ssbruno * BT coex 5776303628Ssbruno */ 5777303628Ssbruno 5778303628Ssbrunoenum iwm_bt_coex_mode { 5779303628Ssbruno IWM_BT_COEX_DISABLE = 0x0, 5780303628Ssbruno IWM_BT_COEX_NW = 0x1, 5781303628Ssbruno IWM_BT_COEX_BT = 0x2, 5782303628Ssbruno IWM_BT_COEX_WIFI = 0x3, 5783303628Ssbruno}; /* BT_COEX_MODES_E */ 5784303628Ssbruno 5785303628Ssbrunoenum iwm_bt_coex_enabled_modules { 5786303628Ssbruno IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5787303628Ssbruno IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5788303628Ssbruno IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5789303628Ssbruno IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5790303628Ssbruno IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5791303628Ssbruno}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5792303628Ssbruno 5793303628Ssbruno/** 5794303628Ssbruno * struct iwm_bt_coex_cmd - bt coex configuration command 5795303628Ssbruno * @mode: enum %iwm_bt_coex_mode 5796303628Ssbruno * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5797303628Ssbruno * 5798303628Ssbruno * The structure is used for the BT_COEX command. 5799303628Ssbruno */ 5800303628Ssbrunostruct iwm_bt_coex_cmd { 5801303628Ssbruno uint32_t mode; 5802303628Ssbruno uint32_t enabled_modules; 5803303628Ssbruno} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5804303628Ssbruno 5805303628Ssbruno 5806303628Ssbruno/* 5807303628Ssbruno * Location Aware Regulatory (LAR) API - MCC updates 5808303628Ssbruno */ 5809303628Ssbruno 5810303628Ssbruno/** 5811303628Ssbruno * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5812303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 5813303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5814303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5815303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 5816303628Ssbruno * @mcc: given mobile country code 5817303628Ssbruno * @source_id: the source from where we got the MCC, see iwm_mcc_source 5818303628Ssbruno * @reserved: reserved for alignment 5819303628Ssbruno */ 5820303628Ssbrunostruct iwm_mcc_update_cmd_v1 { 5821303628Ssbruno uint16_t mcc; 5822303628Ssbruno uint8_t source_id; 5823303628Ssbruno uint8_t reserved; 5824303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5825303628Ssbruno 5826303628Ssbruno/** 5827303628Ssbruno * struct iwm_mcc_update_cmd - Request the device to update geographic 5828303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 5829303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5830303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5831303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 5832303628Ssbruno * @mcc: given mobile country code 5833303628Ssbruno * @source_id: the source from where we got the MCC, see iwm_mcc_source 5834303628Ssbruno * @reserved: reserved for alignment 5835303628Ssbruno * @key: integrity key for MCC API OEM testing 5836303628Ssbruno * @reserved2: reserved 5837303628Ssbruno */ 5838303628Ssbrunostruct iwm_mcc_update_cmd { 5839303628Ssbruno uint16_t mcc; 5840303628Ssbruno uint8_t source_id; 5841303628Ssbruno uint8_t reserved; 5842303628Ssbruno uint32_t key; 5843303628Ssbruno uint32_t reserved2[5]; 5844303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5845303628Ssbruno 5846303628Ssbruno/** 5847303628Ssbruno * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5848303628Ssbruno * Contains the new channel control profile map, if changed, and the new MCC 5849303628Ssbruno * (mobile country code). 5850303628Ssbruno * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5851303628Ssbruno * @status: see &enum iwm_mcc_update_status 5852303628Ssbruno * @mcc: the new applied MCC 5853303628Ssbruno * @cap: capabilities for all channels which matches the MCC 5854303628Ssbruno * @source_id: the MCC source, see iwm_mcc_source 5855303628Ssbruno * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5856303628Ssbruno * channels, depending on platform) 5857303628Ssbruno * @channels: channel control data map, DWORD for each channel. Only the first 5858303628Ssbruno * 16bits are used. 5859303628Ssbruno */ 5860303628Ssbrunostruct iwm_mcc_update_resp_v1 { 5861303628Ssbruno uint32_t status; 5862303628Ssbruno uint16_t mcc; 5863303628Ssbruno uint8_t cap; 5864303628Ssbruno uint8_t source_id; 5865303628Ssbruno uint32_t n_channels; 5866303628Ssbruno uint32_t channels[0]; 5867303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5868303628Ssbruno 5869303628Ssbruno/** 5870303628Ssbruno * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5871303628Ssbruno * Contains the new channel control profile map, if changed, and the new MCC 5872303628Ssbruno * (mobile country code). 5873303628Ssbruno * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5874303628Ssbruno * @status: see &enum iwm_mcc_update_status 5875303628Ssbruno * @mcc: the new applied MCC 5876303628Ssbruno * @cap: capabilities for all channels which matches the MCC 5877303628Ssbruno * @source_id: the MCC source, see iwm_mcc_source 5878303628Ssbruno * @time: time elapsed from the MCC test start (in 30 seconds TU) 5879303628Ssbruno * @reserved: reserved. 5880303628Ssbruno * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5881303628Ssbruno * channels, depending on platform) 5882303628Ssbruno * @channels: channel control data map, DWORD for each channel. Only the first 5883303628Ssbruno * 16bits are used. 5884303628Ssbruno */ 5885303628Ssbrunostruct iwm_mcc_update_resp { 5886303628Ssbruno uint32_t status; 5887303628Ssbruno uint16_t mcc; 5888303628Ssbruno uint8_t cap; 5889303628Ssbruno uint8_t source_id; 5890303628Ssbruno uint16_t time; 5891303628Ssbruno uint16_t reserved; 5892303628Ssbruno uint32_t n_channels; 5893303628Ssbruno uint32_t channels[0]; 5894303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5895303628Ssbruno 5896303628Ssbruno/** 5897303628Ssbruno * struct iwm_mcc_chub_notif - chub notifies of mcc change 5898303628Ssbruno * (MCC_CHUB_UPDATE_CMD = 0xc9) 5899303628Ssbruno * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5900303628Ssbruno * the cellular and connectivity cores that gets updates of the mcc, and 5901303628Ssbruno * notifies the ucode directly of any mcc change. 5902303628Ssbruno * The ucode requests the driver to request the device to update geographic 5903303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 5904303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5905303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5906303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 5907303628Ssbruno * @mcc: given mobile country code 5908303628Ssbruno * @source_id: identity of the change originator, see iwm_mcc_source 5909303628Ssbruno * @reserved1: reserved for alignment 5910303628Ssbruno */ 5911303628Ssbrunostruct iwm_mcc_chub_notif { 5912303628Ssbruno uint16_t mcc; 5913303628Ssbruno uint8_t source_id; 5914303628Ssbruno uint8_t reserved1; 5915303628Ssbruno} __packed; /* LAR_MCC_NOTIFY_S */ 5916303628Ssbruno 5917303628Ssbrunoenum iwm_mcc_update_status { 5918303628Ssbruno IWM_MCC_RESP_NEW_CHAN_PROFILE, 5919303628Ssbruno IWM_MCC_RESP_SAME_CHAN_PROFILE, 5920303628Ssbruno IWM_MCC_RESP_INVALID, 5921303628Ssbruno IWM_MCC_RESP_NVM_DISABLED, 5922303628Ssbruno IWM_MCC_RESP_ILLEGAL, 5923303628Ssbruno IWM_MCC_RESP_LOW_PRIORITY, 5924303628Ssbruno IWM_MCC_RESP_TEST_MODE_ACTIVE, 5925303628Ssbruno IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5926303628Ssbruno IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5927303628Ssbruno}; 5928303628Ssbruno 5929303628Ssbrunoenum iwm_mcc_source { 5930303628Ssbruno IWM_MCC_SOURCE_OLD_FW = 0, 5931303628Ssbruno IWM_MCC_SOURCE_ME = 1, 5932303628Ssbruno IWM_MCC_SOURCE_BIOS = 2, 5933303628Ssbruno IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5934303628Ssbruno IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5935303628Ssbruno IWM_MCC_SOURCE_WIFI = 5, 5936303628Ssbruno IWM_MCC_SOURCE_RESERVED = 6, 5937303628Ssbruno IWM_MCC_SOURCE_DEFAULT = 7, 5938303628Ssbruno IWM_MCC_SOURCE_UNINITIALIZED = 8, 5939303628Ssbruno IWM_MCC_SOURCE_MCC_API = 9, 5940303628Ssbruno IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5941303628Ssbruno IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5942303628Ssbruno}; 5943303628Ssbruno 5944330177Seadler/** 5945330177Seadler * struct iwm_dts_measurement_notif_v1 - measurements notification 5946330177Seadler * 5947330177Seadler * @temp: the measured temperature 5948330177Seadler * @voltage: the measured voltage 5949330177Seadler */ 5950330177Seadlerstruct iwm_dts_measurement_notif_v1 { 5951330177Seadler int32_t temp; 5952330177Seadler int32_t voltage; 5953330177Seadler} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5954330177Seadler 5955330177Seadler/** 5956330177Seadler * struct iwm_dts_measurement_notif_v2 - measurements notification 5957330177Seadler * 5958330177Seadler * @temp: the measured temperature 5959330177Seadler * @voltage: the measured voltage 5960330177Seadler * @threshold_idx: the trip index that was crossed 5961330177Seadler */ 5962330177Seadlerstruct iwm_dts_measurement_notif_v2 { 5963330177Seadler int32_t temp; 5964330177Seadler int32_t voltage; 5965330177Seadler int32_t threshold_idx; 5966330177Seadler} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5967330177Seadler 5968303628Ssbruno/* 5969286441Srpaulo * Some cherry-picked definitions 5970286441Srpaulo */ 5971286441Srpaulo 5972286441Srpaulo#define IWM_FRAME_LIMIT 64 5973286441Srpaulo 5974303628Ssbruno/* 5975303628Ssbruno * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 5976303628Ssbruno * As the firmware is slowly running out of command IDs and grouping of 5977303628Ssbruno * commands is desirable anyway, the firmware is extending the command 5978303628Ssbruno * header from 4 bytes to 8 bytes to introduce a group (in place of the 5979303628Ssbruno * former flags field, since that's always 0 on commands and thus can 5980303628Ssbruno * be easily used to distinguish between the two). 5981303628Ssbruno * 5982303628Ssbruno * These functions retrieve specific information from the id field in 5983303628Ssbruno * the iwm_host_cmd struct which contains the command id, the group id, 5984303628Ssbruno * and the version of the command. 5985303628Ssbruno*/ 5986303628Ssbrunostatic inline uint8_t 5987303628Ssbrunoiwm_cmd_opcode(uint32_t cmdid) 5988303628Ssbruno{ 5989303628Ssbruno return cmdid & 0xff; 5990303628Ssbruno} 5991303628Ssbruno 5992303628Ssbrunostatic inline uint8_t 5993303628Ssbrunoiwm_cmd_groupid(uint32_t cmdid) 5994303628Ssbruno{ 5995303628Ssbruno return ((cmdid & 0Xff00) >> 8); 5996303628Ssbruno} 5997303628Ssbruno 5998303628Ssbrunostatic inline uint8_t 5999303628Ssbrunoiwm_cmd_version(uint32_t cmdid) 6000303628Ssbruno{ 6001303628Ssbruno return ((cmdid & 0xff0000) >> 16); 6002303628Ssbruno} 6003303628Ssbruno 6004303628Ssbrunostatic inline uint32_t 6005303628Ssbrunoiwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6006303628Ssbruno{ 6007303628Ssbruno return opcode + (groupid << 8) + (version << 16); 6008303628Ssbruno} 6009303628Ssbruno 6010303628Ssbruno/* make uint16_t wide id out of uint8_t group and opcode */ 6011303628Ssbruno#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6012303628Ssbruno 6013303628Ssbruno/* due to the conversion, this group is special */ 6014303628Ssbruno#define IWM_ALWAYS_LONG_GROUP 1 6015303628Ssbruno 6016286441Srpaulostruct iwm_cmd_header { 6017286441Srpaulo uint8_t code; 6018286441Srpaulo uint8_t flags; 6019286441Srpaulo uint8_t idx; 6020286441Srpaulo uint8_t qid; 6021286441Srpaulo} __packed; 6022286441Srpaulo 6023303628Ssbrunostruct iwm_cmd_header_wide { 6024303628Ssbruno uint8_t opcode; 6025303628Ssbruno uint8_t group_id; 6026303628Ssbruno uint8_t idx; 6027303628Ssbruno uint8_t qid; 6028303628Ssbruno uint16_t length; 6029303628Ssbruno uint8_t reserved; 6030303628Ssbruno uint8_t version; 6031303628Ssbruno} __packed; 6032303628Ssbruno 6033330201Seadler/** 6034330201Seadler * enum iwm_power_scheme 6035330201Seadler * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6036330201Seadler * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6037330201Seadler * @IWM_POWER_LEVEL_LP - Low Power 6038330201Seadler */ 6039286441Srpauloenum iwm_power_scheme { 6040286441Srpaulo IWM_POWER_SCHEME_CAM = 1, 6041286441Srpaulo IWM_POWER_SCHEME_BPS, 6042286441Srpaulo IWM_POWER_SCHEME_LP 6043286441Srpaulo}; 6044286441Srpaulo 6045286441Srpaulo#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6046301189Sadrian#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6047286441Srpaulo#define IWM_CMD_FAILED_MSK 0x40 6048286441Srpaulo 6049303628Ssbruno/** 6050303628Ssbruno * struct iwm_device_cmd 6051303628Ssbruno * 6052303628Ssbruno * For allocation of the command and tx queues, this establishes the overall 6053303628Ssbruno * size of the largest command we send to uCode, except for commands that 6054303628Ssbruno * aren't fully copied and use other TFD space. 6055303628Ssbruno */ 6056286441Srpaulostruct iwm_device_cmd { 6057303628Ssbruno union { 6058303628Ssbruno struct { 6059303628Ssbruno struct iwm_cmd_header hdr; 6060303628Ssbruno uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6061303628Ssbruno }; 6062303628Ssbruno struct { 6063303628Ssbruno struct iwm_cmd_header_wide hdr_wide; 6064303628Ssbruno uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6065303628Ssbruno sizeof(struct iwm_cmd_header_wide) + 6066303628Ssbruno sizeof(struct iwm_cmd_header)]; 6067303628Ssbruno }; 6068303628Ssbruno }; 6069286441Srpaulo} __packed; 6070286441Srpaulo 6071286441Srpaulostruct iwm_rx_packet { 6072286441Srpaulo /* 6073286441Srpaulo * The first 4 bytes of the RX frame header contain both the RX frame 6074286441Srpaulo * size and some flags. 6075286441Srpaulo * Bit fields: 6076286441Srpaulo * 31: flag flush RB request 6077286441Srpaulo * 30: flag ignore TC (terminal counter) request 6078286441Srpaulo * 29: flag fast IRQ request 6079286441Srpaulo * 28-14: Reserved 6080286441Srpaulo * 13-00: RX frame size 6081286441Srpaulo */ 6082286441Srpaulo uint32_t len_n_flags; 6083286441Srpaulo struct iwm_cmd_header hdr; 6084286441Srpaulo uint8_t data[]; 6085286441Srpaulo} __packed; 6086286441Srpaulo 6087286441Srpaulo#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6088286441Srpaulo 6089286441Srpaulostatic inline uint32_t 6090286441Srpauloiwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6091286441Srpaulo{ 6092286441Srpaulo 6093286441Srpaulo return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6094286441Srpaulo} 6095286441Srpaulo 6096286441Srpaulostatic inline uint32_t 6097286441Srpauloiwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6098286441Srpaulo{ 6099286441Srpaulo 6100286441Srpaulo return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6101286441Srpaulo} 6102286441Srpaulo 6103286441Srpaulo 6104286441Srpaulo#define IWM_MIN_DBM -100 6105286441Srpaulo#define IWM_MAX_DBM -33 /* realistic guess */ 6106286441Srpaulo 6107286441Srpaulo#define IWM_READ(sc, reg) \ 6108286441Srpaulo bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6109286441Srpaulo 6110286441Srpaulo#define IWM_WRITE(sc, reg, val) \ 6111286441Srpaulo bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6112286441Srpaulo 6113286441Srpaulo#define IWM_WRITE_1(sc, reg, val) \ 6114286441Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6115286441Srpaulo 6116286441Srpaulo#define IWM_SETBITS(sc, reg, mask) \ 6117286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6118286441Srpaulo 6119286441Srpaulo#define IWM_CLRBITS(sc, reg, mask) \ 6120286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6121286441Srpaulo 6122286441Srpaulo#define IWM_BARRIER_WRITE(sc) \ 6123286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6124286441Srpaulo BUS_SPACE_BARRIER_WRITE) 6125286441Srpaulo 6126286441Srpaulo#define IWM_BARRIER_READ_WRITE(sc) \ 6127286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6128286441Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6129286441Srpaulo 6130286441Srpaulo#endif /* __IF_IWM_REG_H__ */ 6131