if_iwmreg.h revision 301189
1286441Srpaulo/* $OpenBSD: if_iwmreg.h,v 1.3 2015/02/23 10:25:20 stsp Exp $ */ 2286441Srpaulo/* $FreeBSD: head/sys/dev/iwm/if_iwmreg.h 301189 2016-06-02 04:53:28Z adrian $ */ 3286441Srpaulo 4286441Srpaulo/****************************************************************************** 5286441Srpaulo * 6286441Srpaulo * This file is provided under a dual BSD/GPLv2 license. When using or 7286441Srpaulo * redistributing this file, you may do so under either license. 8286441Srpaulo * 9286441Srpaulo * GPL LICENSE SUMMARY 10286441Srpaulo * 11286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12286441Srpaulo * 13286441Srpaulo * This program is free software; you can redistribute it and/or modify 14286441Srpaulo * it under the terms of version 2 of the GNU General Public License as 15286441Srpaulo * published by the Free Software Foundation. 16286441Srpaulo * 17286441Srpaulo * This program is distributed in the hope that it will be useful, but 18286441Srpaulo * WITHOUT ANY WARRANTY; without even the implied warranty of 19286441Srpaulo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20286441Srpaulo * General Public License for more details. 21286441Srpaulo * 22286441Srpaulo * You should have received a copy of the GNU General Public License 23286441Srpaulo * along with this program; if not, write to the Free Software 24286441Srpaulo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25286441Srpaulo * USA 26286441Srpaulo * 27286441Srpaulo * The full GNU General Public License is included in this distribution 28286441Srpaulo * in the file called COPYING. 29286441Srpaulo * 30286441Srpaulo * Contact Information: 31286441Srpaulo * Intel Linux Wireless <ilw@linux.intel.com> 32286441Srpaulo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33286441Srpaulo * 34286441Srpaulo * BSD LICENSE 35286441Srpaulo * 36286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37286441Srpaulo * All rights reserved. 38286441Srpaulo * 39286441Srpaulo * Redistribution and use in source and binary forms, with or without 40286441Srpaulo * modification, are permitted provided that the following conditions 41286441Srpaulo * are met: 42286441Srpaulo * 43286441Srpaulo * * Redistributions of source code must retain the above copyright 44286441Srpaulo * notice, this list of conditions and the following disclaimer. 45286441Srpaulo * * Redistributions in binary form must reproduce the above copyright 46286441Srpaulo * notice, this list of conditions and the following disclaimer in 47286441Srpaulo * the documentation and/or other materials provided with the 48286441Srpaulo * distribution. 49286441Srpaulo * * Neither the name Intel Corporation nor the names of its 50286441Srpaulo * contributors may be used to endorse or promote products derived 51286441Srpaulo * from this software without specific prior written permission. 52286441Srpaulo * 53286441Srpaulo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54286441Srpaulo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55286441Srpaulo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56286441Srpaulo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57286441Srpaulo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58286441Srpaulo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59286441Srpaulo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60286441Srpaulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61286441Srpaulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62286441Srpaulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63286441Srpaulo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64286441Srpaulo * 65286441Srpaulo *****************************************************************************/ 66286441Srpaulo#ifndef __IF_IWM_REG_H__ 67286441Srpaulo#define __IF_IWM_REG_H__ 68286441Srpaulo 69286441Srpaulo#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70286441Srpaulo#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71286441Srpaulo 72286441Srpaulo/* 73286441Srpaulo * BEGIN iwl-csr.h 74286441Srpaulo */ 75286441Srpaulo 76286441Srpaulo/* 77286441Srpaulo * CSR (control and status registers) 78286441Srpaulo * 79286441Srpaulo * CSR registers are mapped directly into PCI bus space, and are accessible 80286441Srpaulo * whenever platform supplies power to device, even when device is in 81286441Srpaulo * low power states due to driver-invoked device resets 82286441Srpaulo * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83286441Srpaulo * 84286441Srpaulo * Use iwl_write32() and iwl_read32() family to access these registers; 85286441Srpaulo * these provide simple PCI bus access, without waking up the MAC. 86286441Srpaulo * Do not use iwl_write_direct32() family for these registers; 87286441Srpaulo * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88286441Srpaulo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89286441Srpaulo * the CSR registers. 90286441Srpaulo * 91286441Srpaulo * NOTE: Device does need to be awake in order to read this memory 92286441Srpaulo * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93286441Srpaulo */ 94286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95286441Srpaulo#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96286441Srpaulo#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97286441Srpaulo#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98286441Srpaulo#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99286441Srpaulo#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100286441Srpaulo#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101286441Srpaulo#define IWM_CSR_GP_CNTRL (0x024) 102286441Srpaulo 103286441Srpaulo/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104286441Srpaulo#define IWM_CSR_INT_PERIODIC_REG (0x005) 105286441Srpaulo 106286441Srpaulo/* 107286441Srpaulo * Hardware revision info 108286441Srpaulo * Bit fields: 109286441Srpaulo * 31-16: Reserved 110286441Srpaulo * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111286441Srpaulo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112286441Srpaulo * 1-0: "Dash" (-) value, as in A-1, etc. 113286441Srpaulo */ 114286441Srpaulo#define IWM_CSR_HW_REV (0x028) 115286441Srpaulo 116286441Srpaulo/* 117286441Srpaulo * EEPROM and OTP (one-time-programmable) memory reads 118286441Srpaulo * 119286441Srpaulo * NOTE: Device must be awake, initialized via apm_ops.init(), 120286441Srpaulo * in order to read. 121286441Srpaulo */ 122286441Srpaulo#define IWM_CSR_EEPROM_REG (0x02c) 123286441Srpaulo#define IWM_CSR_EEPROM_GP (0x030) 124286441Srpaulo#define IWM_CSR_OTP_GP_REG (0x034) 125286441Srpaulo 126286441Srpaulo#define IWM_CSR_GIO_REG (0x03C) 127286441Srpaulo#define IWM_CSR_GP_UCODE_REG (0x048) 128286441Srpaulo#define IWM_CSR_GP_DRIVER_REG (0x050) 129286441Srpaulo 130286441Srpaulo/* 131286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox registers. 132286441Srpaulo * SET/CLR registers set/clear bit(s) if "1" is written. 133286441Srpaulo */ 134286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137286441Srpaulo#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138286441Srpaulo 139286441Srpaulo#define IWM_CSR_LED_REG (0x094) 140286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 141286441Srpaulo#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 142286441Srpaulo 143286441Srpaulo 144286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 145286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 146286441Srpaulo 147286441Srpaulo/* Analog phase-lock-loop configuration */ 148286441Srpaulo#define IWM_CSR_ANA_PLL_CFG (0x20c) 149286441Srpaulo 150286441Srpaulo/* 151286441Srpaulo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 152286441Srpaulo * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 153286441Srpaulo * See also IWM_CSR_HW_REV register. 154286441Srpaulo * Bit fields: 155286441Srpaulo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 156286441Srpaulo * 1-0: "Dash" (-) value, as in C-1, etc. 157286441Srpaulo */ 158286441Srpaulo#define IWM_CSR_HW_REV_WA_REG (0x22C) 159286441Srpaulo 160286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 161286441Srpaulo#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 162286441Srpaulo 163286441Srpaulo/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 164286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 165286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 166286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 167286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 168286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 169286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 170286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 171286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 172286441Srpaulo 173286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 174286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 175286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 176286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 177286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 178286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 179286441Srpaulo 180286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 181286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 182286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 183286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 184286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 185286441Srpaulo 186286441Srpaulo#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 187286441Srpaulo#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 188286441Srpaulo 189286441Srpaulo/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 190286441Srpaulo * acknowledged (reset) by host writing "1" to flagged bits. */ 191286441Srpaulo#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 192286441Srpaulo#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 193286441Srpaulo#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 194286441Srpaulo#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 195286441Srpaulo#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 196286441Srpaulo#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 197286441Srpaulo#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 198286441Srpaulo#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 199286441Srpaulo#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 200286441Srpaulo#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 201286441Srpaulo#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 202286441Srpaulo 203286441Srpaulo#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 204286441Srpaulo IWM_CSR_INT_BIT_HW_ERR | \ 205286441Srpaulo IWM_CSR_INT_BIT_FH_TX | \ 206286441Srpaulo IWM_CSR_INT_BIT_SW_ERR | \ 207286441Srpaulo IWM_CSR_INT_BIT_RF_KILL | \ 208286441Srpaulo IWM_CSR_INT_BIT_SW_RX | \ 209286441Srpaulo IWM_CSR_INT_BIT_WAKEUP | \ 210286441Srpaulo IWM_CSR_INT_BIT_ALIVE | \ 211286441Srpaulo IWM_CSR_INT_BIT_RX_PERIODIC) 212286441Srpaulo 213286441Srpaulo/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 214286441Srpaulo#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 215286441Srpaulo#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 216286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 217286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 218286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 219286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 220286441Srpaulo 221286441Srpaulo#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 222286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 223286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL0) 224286441Srpaulo 225286441Srpaulo#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 226286441Srpaulo IWM_CSR_FH_INT_BIT_TX_CHNL0) 227286441Srpaulo 228286441Srpaulo/* GPIO */ 229286441Srpaulo#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 230286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 231286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 232286441Srpaulo 233286441Srpaulo/* RESET */ 234286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 235286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 236286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 237286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 238286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 239286441Srpaulo#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 240286441Srpaulo 241286441Srpaulo/* 242286441Srpaulo * GP (general purpose) CONTROL REGISTER 243286441Srpaulo * Bit fields: 244286441Srpaulo * 27: HW_RF_KILL_SW 245286441Srpaulo * Indicates state of (platform's) hardware RF-Kill switch 246286441Srpaulo * 26-24: POWER_SAVE_TYPE 247286441Srpaulo * Indicates current power-saving mode: 248286441Srpaulo * 000 -- No power saving 249286441Srpaulo * 001 -- MAC power-down 250286441Srpaulo * 010 -- PHY (radio) power-down 251286441Srpaulo * 011 -- Error 252286441Srpaulo * 9-6: SYS_CONFIG 253286441Srpaulo * Indicates current system configuration, reflecting pins on chip 254286441Srpaulo * as forced high/low by device circuit board. 255286441Srpaulo * 4: GOING_TO_SLEEP 256286441Srpaulo * Indicates MAC is entering a power-saving sleep power-down. 257286441Srpaulo * Not a good time to access device-internal resources. 258286441Srpaulo * 3: MAC_ACCESS_REQ 259286441Srpaulo * Host sets this to request and maintain MAC wakeup, to allow host 260286441Srpaulo * access to device-internal resources. Host must wait for 261286441Srpaulo * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 262286441Srpaulo * device registers. 263286441Srpaulo * 2: INIT_DONE 264286441Srpaulo * Host sets this to put device into fully operational D0 power mode. 265286441Srpaulo * Host resets this after SW_RESET to put device into low power mode. 266286441Srpaulo * 0: MAC_CLOCK_READY 267286441Srpaulo * Indicates MAC (ucode processor, etc.) is powered up and can run. 268286441Srpaulo * Internal resources are accessible. 269286441Srpaulo * NOTE: This does not indicate that the processor is actually running. 270286441Srpaulo * NOTE: This does not indicate that device has completed 271286441Srpaulo * init or post-power-down restore of internal SRAM memory. 272286441Srpaulo * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 273286441Srpaulo * SRAM is restored and uCode is in normal operation mode. 274286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 275286441Srpaulo * do not need to save/restore it. 276286441Srpaulo * NOTE: After device reset, this bit remains "0" until host sets 277286441Srpaulo * INIT_DONE 278286441Srpaulo */ 279286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 280286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 281286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 282286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 283286441Srpaulo 284286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 285286441Srpaulo 286286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 287286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 288286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 289286441Srpaulo 290286441Srpaulo 291286441Srpaulo/* HW REV */ 292286441Srpaulo#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 293286441Srpaulo#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 294286441Srpaulo 295286441Srpaulo#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 296286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 297286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 298286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 299286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 300286441Srpaulo#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 301286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 302286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 303286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 304286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 305286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 306286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 307286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 308286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 309286441Srpaulo#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 310286441Srpaulo#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 311286441Srpaulo#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 312286441Srpaulo 313286441Srpaulo/* EEPROM REG */ 314286441Srpaulo#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 315286441Srpaulo#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 316286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 317286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 318286441Srpaulo 319286441Srpaulo/* EEPROM GP */ 320286441Srpaulo#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 321286441Srpaulo#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 322286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 323286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 324286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 325286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 326286441Srpaulo 327286441Srpaulo/* One-time-programmable memory general purpose reg */ 328286441Srpaulo#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 329286441Srpaulo#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 330286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 331286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 332286441Srpaulo 333286441Srpaulo/* GP REG */ 334286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 335286441Srpaulo#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 336286441Srpaulo#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 337286441Srpaulo#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 338286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 339286441Srpaulo 340286441Srpaulo 341286441Srpaulo/* CSR GIO */ 342286441Srpaulo#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 343286441Srpaulo 344286441Srpaulo/* 345286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox register 1 346286441Srpaulo * Host driver and uCode write and/or read this register to communicate with 347286441Srpaulo * each other. 348286441Srpaulo * Bit fields: 349286441Srpaulo * 4: UCODE_DISABLE 350286441Srpaulo * Host sets this to request permanent halt of uCode, same as 351286441Srpaulo * sending CARD_STATE command with "halt" bit set. 352286441Srpaulo * 3: CT_KILL_EXIT 353286441Srpaulo * Host sets this to request exit from CT_KILL state, i.e. host thinks 354286441Srpaulo * device temperature is low enough to continue normal operation. 355286441Srpaulo * 2: CMD_BLOCKED 356286441Srpaulo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 357286441Srpaulo * to release uCode to clear all Tx and command queues, enter 358286441Srpaulo * unassociated mode, and power down. 359286441Srpaulo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 360286441Srpaulo * 1: SW_BIT_RFKILL 361286441Srpaulo * Host sets this when issuing CARD_STATE command to request 362286441Srpaulo * device sleep. 363286441Srpaulo * 0: MAC_SLEEP 364286441Srpaulo * uCode sets this when preparing a power-saving power-down. 365286441Srpaulo * uCode resets this when power-up is complete and SRAM is sane. 366286441Srpaulo * NOTE: device saves internal SRAM data to host when powering down, 367286441Srpaulo * and must restore this data after powering back up. 368286441Srpaulo * MAC_SLEEP is the best indication that restore is complete. 369286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 370286441Srpaulo * do not need to save/restore it. 371286441Srpaulo */ 372286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 373286441Srpaulo#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 374286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 375286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 376286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 377286441Srpaulo 378286441Srpaulo/* GP Driver */ 379286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 380286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 381286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 382286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 383286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 384286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 385286441Srpaulo 386286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 387286441Srpaulo 388286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 389286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 390286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 391286441Srpaulo 392286441Srpaulo/* LED */ 393286441Srpaulo#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 394286441Srpaulo#define IWM_CSR_LED_REG_TURN_ON (0x60) 395286441Srpaulo#define IWM_CSR_LED_REG_TURN_OFF (0x20) 396286441Srpaulo 397286441Srpaulo/* ANA_PLL */ 398286441Srpaulo#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 399286441Srpaulo 400286441Srpaulo/* HPET MEM debug */ 401286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 402286441Srpaulo 403286441Srpaulo/* DRAM INT TABLE */ 404286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 405286441Srpaulo#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 406286441Srpaulo 407286441Srpaulo/* SECURE boot registers */ 408286441Srpaulo#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 409286441Srpauloenum iwm_secure_boot_config_reg { 410286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 411286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 412286441Srpaulo}; 413286441Srpaulo 414286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 415286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 416286441Srpauloenum iwm_secure_boot_status_reg { 417286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 418286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 419286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 420286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 421286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 422286441Srpaulo}; 423286441Srpaulo 424286441Srpaulo#define IWM_CSR_UCODE_LOAD_STATUS_ADDR (0x100) 425286441Srpauloenum iwm_secure_load_status_reg { 426286441Srpaulo IWM_CSR_CPU_STATUS_LOADING_STARTED = 0x00000001, 427286441Srpaulo IWM_CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002, 428286441Srpaulo IWM_CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 429286441Srpaulo IWM_CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 430286441Srpaulo}; 431286441Srpaulo 432286441Srpaulo#define IWM_CSR_SECURE_INSPECTOR_CODE_ADDR (0x100) 433286441Srpaulo#define IWM_CSR_SECURE_INSPECTOR_DATA_ADDR (0x100) 434286441Srpaulo 435286441Srpaulo#define IWM_CSR_SECURE_TIME_OUT (100) 436286441Srpaulo 437286441Srpaulo#define IWM_FH_TCSR_0_REG0 (0x1D00) 438286441Srpaulo 439286441Srpaulo/* 440286441Srpaulo * HBUS (Host-side Bus) 441286441Srpaulo * 442286441Srpaulo * HBUS registers are mapped directly into PCI bus space, but are used 443286441Srpaulo * to indirectly access device's internal memory or registers that 444286441Srpaulo * may be powered-down. 445286441Srpaulo * 446286441Srpaulo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 447286441Srpaulo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 448286441Srpaulo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 449286441Srpaulo * internal resources. 450286441Srpaulo * 451286441Srpaulo * Do not use iwl_write32()/iwl_read32() family to access these registers; 452286441Srpaulo * these provide only simple PCI bus access, without waking up the MAC. 453286441Srpaulo */ 454286441Srpaulo#define IWM_HBUS_BASE (0x400) 455286441Srpaulo 456286441Srpaulo/* 457286441Srpaulo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 458286441Srpaulo * structures, error log, event log, verifying uCode load). 459286441Srpaulo * First write to address register, then read from or write to data register 460286441Srpaulo * to complete the job. Once the address register is set up, accesses to 461286441Srpaulo * data registers auto-increment the address by one dword. 462286441Srpaulo * Bit usage for address registers (read or write): 463286441Srpaulo * 0-31: memory address within device 464286441Srpaulo */ 465286441Srpaulo#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 466286441Srpaulo#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 467286441Srpaulo#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 468286441Srpaulo#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 469286441Srpaulo 470286441Srpaulo/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 471286441Srpaulo#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 472286441Srpaulo#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 473286441Srpaulo 474286441Srpaulo/* 475286441Srpaulo * Registers for accessing device's internal peripheral registers 476286441Srpaulo * (e.g. SCD, BSM, etc.). First write to address register, 477286441Srpaulo * then read from or write to data register to complete the job. 478286441Srpaulo * Bit usage for address registers (read or write): 479286441Srpaulo * 0-15: register address (offset) within device 480286441Srpaulo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 481286441Srpaulo */ 482286441Srpaulo#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 483286441Srpaulo#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 484286441Srpaulo#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 485286441Srpaulo#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 486286441Srpaulo 487286441Srpaulo/* Used to enable DBGM */ 488286441Srpaulo#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 489286441Srpaulo 490286441Srpaulo/* 491286441Srpaulo * Per-Tx-queue write pointer (index, really!) 492286441Srpaulo * Indicates index to next TFD that driver will fill (1 past latest filled). 493286441Srpaulo * Bit usage: 494286441Srpaulo * 0-7: queue write index 495286441Srpaulo * 11-8: queue selector 496286441Srpaulo */ 497286441Srpaulo#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 498286441Srpaulo 499286441Srpaulo/********************************************************** 500286441Srpaulo * CSR values 501286441Srpaulo **********************************************************/ 502286441Srpaulo /* 503286441Srpaulo * host interrupt timeout value 504286441Srpaulo * used with setting interrupt coalescing timer 505286441Srpaulo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 506286441Srpaulo * 507286441Srpaulo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 508286441Srpaulo */ 509286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 510286441Srpaulo#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 511286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 512286441Srpaulo#define IWM_HOST_INT_OPER_MODE (1 << 31) 513286441Srpaulo 514286441Srpaulo/***************************************************************************** 515286441Srpaulo * 7000/3000 series SHR DTS addresses * 516286441Srpaulo *****************************************************************************/ 517286441Srpaulo 518286441Srpaulo/* Diode Results Register Structure: */ 519286441Srpauloenum iwm_dtd_diode_reg { 520286441Srpaulo IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 521286441Srpaulo IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 522286441Srpaulo IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 523286441Srpaulo IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 524286441Srpaulo IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 525286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 526286441Srpaulo/* Those are the masks INSIDE the flags bit-field: */ 527286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 528286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 529286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 530286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 531286441Srpaulo}; 532286441Srpaulo 533286441Srpaulo/* 534286441Srpaulo * END iwl-csr.h 535286441Srpaulo */ 536286441Srpaulo 537286441Srpaulo/* 538286441Srpaulo * BEGIN iwl-fw.h 539286441Srpaulo */ 540286441Srpaulo 541286441Srpaulo/** 542286441Srpaulo * enum iwl_ucode_tlv_flag - ucode API flags 543286441Srpaulo * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 544286441Srpaulo * was a separate TLV but moved here to save space. 545286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 546286441Srpaulo * treats good CRC threshold as a boolean 547286441Srpaulo * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 548286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 549286441Srpaulo * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 550286441Srpaulo * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 551286441Srpaulo * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 552286441Srpaulo * offload profile config command. 553286441Srpaulo * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 554286441Srpaulo * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 555286441Srpaulo * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 556286441Srpaulo * (rather than two) IPv6 addresses 557286441Srpaulo * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 558286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 559286441Srpaulo * from the probe request template. 560286441Srpaulo * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 561286441Srpaulo * connection when going back to D0 562286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 563286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 564286441Srpaulo * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 565286441Srpaulo * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 566286441Srpaulo * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 567286441Srpaulo * containing CAM (Continuous Active Mode) indication. 568286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 569286441Srpaulo * single bound interface). 570286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 571286441Srpaulo */ 572286441Srpauloenum iwm_ucode_tlv_flag { 573286441Srpaulo IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 574286441Srpaulo IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 575286441Srpaulo IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 576286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 577286441Srpaulo IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 578286441Srpaulo IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 579286441Srpaulo IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 580286441Srpaulo IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 581286441Srpaulo IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 582286441Srpaulo IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 583286441Srpaulo IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 584286441Srpaulo IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 585286441Srpaulo IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 586286441Srpaulo IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 587286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 588286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 589286441Srpaulo IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 590286441Srpaulo IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 591286441Srpaulo IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 592286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 593286441Srpaulo IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 594286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 595286441Srpaulo}; 596286441Srpaulo 597286441Srpaulo/* The default calibrate table size if not specified by firmware file */ 598286441Srpaulo#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 599286441Srpaulo#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 600286441Srpaulo#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 601286441Srpaulo 602286441Srpaulo/* The default max probe length if not specified by the firmware file */ 603286441Srpaulo#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 604286441Srpaulo 605286441Srpaulo/* 606286441Srpaulo * enumeration of ucode section. 607286441Srpaulo * This enumeration is used directly for older firmware (before 16.0). 608286441Srpaulo * For new firmware, there can be up to 4 sections (see below) but the 609286441Srpaulo * first one packaged into the firmware file is the DATA section and 610286441Srpaulo * some debugging code accesses that. 611286441Srpaulo */ 612286441Srpauloenum iwm_ucode_sec { 613286441Srpaulo IWM_UCODE_SECTION_DATA, 614286441Srpaulo IWM_UCODE_SECTION_INST, 615286441Srpaulo}; 616286441Srpaulo/* 617286441Srpaulo * For 16.0 uCode and above, there is no differentiation between sections, 618286441Srpaulo * just an offset to the HW address. 619286441Srpaulo */ 620286441Srpaulo#define IWM_UCODE_SECTION_MAX 6 621286441Srpaulo#define IWM_UCODE_FIRST_SECTION_OF_SECOND_CPU (IWM_UCODE_SECTION_MAX/2) 622286441Srpaulo 623286441Srpaulo/* uCode version contains 4 values: Major/Minor/API/Serial */ 624286441Srpaulo#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 625286441Srpaulo#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 626286441Srpaulo#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 627286441Srpaulo#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 628286441Srpaulo 629286441Srpaulo/* 630286441Srpaulo * Calibration control struct. 631286441Srpaulo * Sent as part of the phy configuration command. 632286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 633286441Srpaulo * flow triggers. 634286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 635286441Srpaulo * event triggers. 636286441Srpaulo */ 637286441Srpaulostruct iwm_tlv_calib_ctrl { 638286441Srpaulo uint32_t flow_trigger; 639286441Srpaulo uint32_t event_trigger; 640286441Srpaulo} __packed; 641286441Srpaulo 642286441Srpauloenum iwm_fw_phy_cfg { 643286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 644286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 645286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 646286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 647286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 648286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 649286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 650286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 651286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 652286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 653286441Srpaulo}; 654286441Srpaulo 655286441Srpaulo#define IWM_UCODE_MAX_CS 1 656286441Srpaulo 657286441Srpaulo/** 658286441Srpaulo * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 659286441Srpaulo * @cipher: a cipher suite selector 660286441Srpaulo * @flags: cipher scheme flags (currently reserved for a future use) 661286441Srpaulo * @hdr_len: a size of MPDU security header 662286441Srpaulo * @pn_len: a size of PN 663286441Srpaulo * @pn_off: an offset of pn from the beginning of the security header 664286441Srpaulo * @key_idx_off: an offset of key index byte in the security header 665286441Srpaulo * @key_idx_mask: a bit mask of key_idx bits 666286441Srpaulo * @key_idx_shift: bit shift needed to get key_idx 667286441Srpaulo * @mic_len: mic length in bytes 668286441Srpaulo * @hw_cipher: a HW cipher index used in host commands 669286441Srpaulo */ 670286441Srpaulostruct iwm_fw_cipher_scheme { 671286441Srpaulo uint32_t cipher; 672286441Srpaulo uint8_t flags; 673286441Srpaulo uint8_t hdr_len; 674286441Srpaulo uint8_t pn_len; 675286441Srpaulo uint8_t pn_off; 676286441Srpaulo uint8_t key_idx_off; 677286441Srpaulo uint8_t key_idx_mask; 678286441Srpaulo uint8_t key_idx_shift; 679286441Srpaulo uint8_t mic_len; 680286441Srpaulo uint8_t hw_cipher; 681286441Srpaulo} __packed; 682286441Srpaulo 683286441Srpaulo/** 684286441Srpaulo * struct iwm_fw_cscheme_list - a cipher scheme list 685286441Srpaulo * @size: a number of entries 686286441Srpaulo * @cs: cipher scheme entries 687286441Srpaulo */ 688286441Srpaulostruct iwm_fw_cscheme_list { 689286441Srpaulo uint8_t size; 690286441Srpaulo struct iwm_fw_cipher_scheme cs[]; 691286441Srpaulo} __packed; 692286441Srpaulo 693286441Srpaulo/* 694286441Srpaulo * END iwl-fw.h 695286441Srpaulo */ 696286441Srpaulo 697286441Srpaulo/* 698286441Srpaulo * BEGIN iwl-fw-file.h 699286441Srpaulo */ 700286441Srpaulo 701286441Srpaulo/* v1/v2 uCode file layout */ 702286441Srpaulostruct iwm_ucode_header { 703286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 704286441Srpaulo union { 705286441Srpaulo struct { 706286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 707286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 708286441Srpaulo uint32_t init_size; /* bytes of init code */ 709286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 710286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 711286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 712286441Srpaulo } v1; 713286441Srpaulo struct { 714286441Srpaulo uint32_t build; /* build number */ 715286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 716286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 717286441Srpaulo uint32_t init_size; /* bytes of init code */ 718286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 719286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 720286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 721286441Srpaulo } v2; 722286441Srpaulo } u; 723286441Srpaulo}; 724286441Srpaulo 725286441Srpaulo/* 726286441Srpaulo * new TLV uCode file layout 727286441Srpaulo * 728286441Srpaulo * The new TLV file format contains TLVs, that each specify 729286441Srpaulo * some piece of data. 730286441Srpaulo */ 731286441Srpaulo 732286441Srpauloenum iwm_ucode_tlv_type { 733286441Srpaulo IWM_UCODE_TLV_INVALID = 0, /* unused */ 734286441Srpaulo IWM_UCODE_TLV_INST = 1, 735286441Srpaulo IWM_UCODE_TLV_DATA = 2, 736286441Srpaulo IWM_UCODE_TLV_INIT = 3, 737286441Srpaulo IWM_UCODE_TLV_INIT_DATA = 4, 738286441Srpaulo IWM_UCODE_TLV_BOOT = 5, 739286441Srpaulo IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 740286441Srpaulo IWM_UCODE_TLV_PAN = 7, 741286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 742286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 743286441Srpaulo IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 744286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 745286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 746286441Srpaulo IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 747286441Srpaulo IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 748286441Srpaulo IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 749286441Srpaulo IWM_UCODE_TLV_WOWLAN_INST = 16, 750286441Srpaulo IWM_UCODE_TLV_WOWLAN_DATA = 17, 751286441Srpaulo IWM_UCODE_TLV_FLAGS = 18, 752286441Srpaulo IWM_UCODE_TLV_SEC_RT = 19, 753286441Srpaulo IWM_UCODE_TLV_SEC_INIT = 20, 754286441Srpaulo IWM_UCODE_TLV_SEC_WOWLAN = 21, 755286441Srpaulo IWM_UCODE_TLV_DEF_CALIB = 22, 756286441Srpaulo IWM_UCODE_TLV_PHY_SKU = 23, 757286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_RT = 24, 758286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 759286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 760286441Srpaulo IWM_UCODE_TLV_NUM_OF_CPU = 27, 761286441Srpaulo IWM_UCODE_TLV_CSCHEME = 28, 762286441Srpaulo 763286441Srpaulo /* 764286441Srpaulo * Following two are not in our base tag, but allow 765286441Srpaulo * handling ucode version 9. 766286441Srpaulo */ 767286441Srpaulo IWM_UCODE_TLV_API_CHANGES_SET = 29, 768286441Srpaulo IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30 769286441Srpaulo}; 770286441Srpaulo 771286441Srpaulostruct iwm_ucode_tlv { 772286441Srpaulo uint32_t type; /* see above */ 773286441Srpaulo uint32_t length; /* not including type/length fields */ 774286441Srpaulo uint8_t data[0]; 775286441Srpaulo}; 776286441Srpaulo 777286441Srpaulo#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 778286441Srpaulo 779286441Srpaulostruct iwm_tlv_ucode_header { 780286441Srpaulo /* 781286441Srpaulo * The TLV style ucode header is distinguished from 782286441Srpaulo * the v1/v2 style header by first four bytes being 783286441Srpaulo * zero, as such is an invalid combination of 784286441Srpaulo * major/minor/API/serial versions. 785286441Srpaulo */ 786286441Srpaulo uint32_t zero; 787286441Srpaulo uint32_t magic; 788286441Srpaulo uint8_t human_readable[64]; 789286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 790286441Srpaulo uint32_t build; 791286441Srpaulo uint64_t ignore; 792286441Srpaulo /* 793286441Srpaulo * The data contained herein has a TLV layout, 794286441Srpaulo * see above for the TLV header and types. 795286441Srpaulo * Note that each TLV is padded to a length 796286441Srpaulo * that is a multiple of 4 for alignment. 797286441Srpaulo */ 798286441Srpaulo uint8_t data[0]; 799286441Srpaulo}; 800286441Srpaulo 801286441Srpaulo/* 802286441Srpaulo * END iwl-fw-file.h 803286441Srpaulo */ 804286441Srpaulo 805286441Srpaulo/* 806286441Srpaulo * BEGIN iwl-prph.h 807286441Srpaulo */ 808286441Srpaulo 809286441Srpaulo/* 810286441Srpaulo * Registers in this file are internal, not PCI bus memory mapped. 811286441Srpaulo * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 812286441Srpaulo */ 813286441Srpaulo#define IWM_PRPH_BASE (0x00000) 814286441Srpaulo#define IWM_PRPH_END (0xFFFFF) 815286441Srpaulo 816286441Srpaulo/* APMG (power management) constants */ 817286441Srpaulo#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 818286441Srpaulo#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 819286441Srpaulo#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 820286441Srpaulo#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 821286441Srpaulo#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 822286441Srpaulo#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 823286441Srpaulo#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 824286441Srpaulo#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 825286441Srpaulo#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 826286441Srpaulo#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 827286441Srpaulo#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 828286441Srpaulo 829286441Srpaulo#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 830286441Srpaulo#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 831286441Srpaulo#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 832286441Srpaulo 833286441Srpaulo#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 834286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 835286441Srpaulo#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 836286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 837286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 838286441Srpaulo#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 839286441Srpaulo#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 840286441Srpaulo 841286441Srpaulo#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 842286441Srpaulo 843286441Srpaulo#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 844286441Srpaulo 845286441Srpaulo/* Device system time */ 846286441Srpaulo#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 847286441Srpaulo 848286441Srpaulo/* Device NMI register */ 849286441Srpaulo#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 850286441Srpaulo 851286441Srpaulo/***************************************************************************** 852286441Srpaulo * 7000/3000 series SHR DTS addresses * 853286441Srpaulo *****************************************************************************/ 854286441Srpaulo 855286441Srpaulo#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 856286441Srpaulo#define IWM_DTSC_CFG_MODE (0x00a10604) 857286441Srpaulo#define IWM_DTSC_VREF_AVG (0x00a10648) 858286441Srpaulo#define IWM_DTSC_VREF5_AVG (0x00a1064c) 859286441Srpaulo#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 860286441Srpaulo#define IWM_DTSC_PTAT_AVG (0x00a10650) 861286441Srpaulo 862286441Srpaulo 863286441Srpaulo/** 864286441Srpaulo * Tx Scheduler 865286441Srpaulo * 866286441Srpaulo * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 867286441Srpaulo * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 868286441Srpaulo * host DRAM. It steers each frame's Tx command (which contains the frame 869286441Srpaulo * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 870286441Srpaulo * device. A queue maps to only one (selectable by driver) Tx DMA channel, 871286441Srpaulo * but one DMA channel may take input from several queues. 872286441Srpaulo * 873286441Srpaulo * Tx DMA FIFOs have dedicated purposes. 874286441Srpaulo * 875286441Srpaulo * For 5000 series and up, they are used differently 876286441Srpaulo * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 877286441Srpaulo * 878286441Srpaulo * 0 -- EDCA BK (background) frames, lowest priority 879286441Srpaulo * 1 -- EDCA BE (best effort) frames, normal priority 880286441Srpaulo * 2 -- EDCA VI (video) frames, higher priority 881286441Srpaulo * 3 -- EDCA VO (voice) and management frames, highest priority 882286441Srpaulo * 4 -- unused 883286441Srpaulo * 5 -- unused 884286441Srpaulo * 6 -- unused 885286441Srpaulo * 7 -- Commands 886286441Srpaulo * 887286441Srpaulo * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 888286441Srpaulo * In addition, driver can map the remaining queues to Tx DMA/FIFO 889286441Srpaulo * channels 0-3 to support 11n aggregation via EDCA DMA channels. 890286441Srpaulo * 891286441Srpaulo * The driver sets up each queue to work in one of two modes: 892286441Srpaulo * 893286441Srpaulo * 1) Scheduler-Ack, in which the scheduler automatically supports a 894286441Srpaulo * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 895286441Srpaulo * contains TFDs for a unique combination of Recipient Address (RA) 896286441Srpaulo * and Traffic Identifier (TID), that is, traffic of a given 897286441Srpaulo * Quality-Of-Service (QOS) priority, destined for a single station. 898286441Srpaulo * 899286441Srpaulo * In scheduler-ack mode, the scheduler keeps track of the Tx status of 900286441Srpaulo * each frame within the BA window, including whether it's been transmitted, 901286441Srpaulo * and whether it's been acknowledged by the receiving station. The device 902286441Srpaulo * automatically processes block-acks received from the receiving STA, 903286441Srpaulo * and reschedules un-acked frames to be retransmitted (successful 904286441Srpaulo * Tx completion may end up being out-of-order). 905286441Srpaulo * 906286441Srpaulo * The driver must maintain the queue's Byte Count table in host DRAM 907286441Srpaulo * for this mode. 908286441Srpaulo * This mode does not support fragmentation. 909286441Srpaulo * 910286441Srpaulo * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 911286441Srpaulo * The device may automatically retry Tx, but will retry only one frame 912286441Srpaulo * at a time, until receiving ACK from receiving station, or reaching 913286441Srpaulo * retry limit and giving up. 914286441Srpaulo * 915286441Srpaulo * The command queue (#4/#9) must use this mode! 916286441Srpaulo * This mode does not require use of the Byte Count table in host DRAM. 917286441Srpaulo * 918286441Srpaulo * Driver controls scheduler operation via 3 means: 919286441Srpaulo * 1) Scheduler registers 920286441Srpaulo * 2) Shared scheduler data base in internal SRAM 921286441Srpaulo * 3) Shared data in host DRAM 922286441Srpaulo * 923286441Srpaulo * Initialization: 924286441Srpaulo * 925286441Srpaulo * When loading, driver should allocate memory for: 926286441Srpaulo * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 927286441Srpaulo * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 928286441Srpaulo * (1024 bytes for each queue). 929286441Srpaulo * 930286441Srpaulo * After receiving "Alive" response from uCode, driver must initialize 931286441Srpaulo * the scheduler (especially for queue #4/#9, the command queue, otherwise 932286441Srpaulo * the driver can't issue commands!): 933286441Srpaulo */ 934286441Srpaulo#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 935286441Srpaulo 936286441Srpaulo/** 937286441Srpaulo * Max Tx window size is the max number of contiguous TFDs that the scheduler 938286441Srpaulo * can keep track of at one time when creating block-ack chains of frames. 939286441Srpaulo * Note that "64" matches the number of ack bits in a block-ack packet. 940286441Srpaulo */ 941286441Srpaulo#define IWM_SCD_WIN_SIZE 64 942286441Srpaulo#define IWM_SCD_FRAME_LIMIT 64 943286441Srpaulo 944286441Srpaulo#define IWM_SCD_TXFIFO_POS_TID (0) 945286441Srpaulo#define IWM_SCD_TXFIFO_POS_RA (4) 946286441Srpaulo#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 947286441Srpaulo 948286441Srpaulo/* agn SCD */ 949286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 950286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 951286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 952286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 953286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 954286441Srpaulo 955286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 956286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 957286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 958286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 959286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 960286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 961286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 962286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 963286441Srpaulo 964286441Srpaulo/* Context Data */ 965286441Srpaulo#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 966286441Srpaulo#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 967286441Srpaulo 968286441Srpaulo/* Tx status */ 969286441Srpaulo#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 970286441Srpaulo#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 971286441Srpaulo 972286441Srpaulo/* Translation Data */ 973286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 974286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 975286441Srpaulo 976286441Srpaulo#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 977286441Srpaulo (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 978286441Srpaulo 979286441Srpaulo#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 980286441Srpaulo (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 981286441Srpaulo 982286441Srpaulo#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 983286441Srpaulo ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 984286441Srpaulo 985286441Srpaulo#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 986286441Srpaulo 987286441Srpaulo#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 988286441Srpaulo#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 989286441Srpaulo#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 990286441Srpaulo#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 991286441Srpaulo#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 992286441Srpaulo#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 993286441Srpaulo#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 994286441Srpaulo#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 995286441Srpaulo#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 996286441Srpaulo 997286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 998286441Srpaulo{ 999286441Srpaulo if (chnl < 20) 1000286441Srpaulo return IWM_SCD_BASE + 0x18 + chnl * 4; 1001286441Srpaulo return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1002286441Srpaulo} 1003286441Srpaulo 1004286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1005286441Srpaulo{ 1006286441Srpaulo if (chnl < 20) 1007286441Srpaulo return IWM_SCD_BASE + 0x68 + chnl * 4; 1008286441Srpaulo return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1009286441Srpaulo} 1010286441Srpaulo 1011286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1012286441Srpaulo{ 1013286441Srpaulo if (chnl < 20) 1014286441Srpaulo return IWM_SCD_BASE + 0x10c + chnl * 4; 1015286441Srpaulo return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1016286441Srpaulo} 1017286441Srpaulo 1018286441Srpaulo/*********************** END TX SCHEDULER *************************************/ 1019286441Srpaulo 1020286441Srpaulo/* Oscillator clock */ 1021286441Srpaulo#define IWM_OSC_CLK (0xa04068) 1022286441Srpaulo#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1023286441Srpaulo 1024286441Srpaulo/* 1025286441Srpaulo * END iwl-prph.h 1026286441Srpaulo */ 1027286441Srpaulo 1028286441Srpaulo/* 1029286441Srpaulo * BEGIN iwl-fh.h 1030286441Srpaulo */ 1031286441Srpaulo 1032286441Srpaulo/****************************/ 1033286441Srpaulo/* Flow Handler Definitions */ 1034286441Srpaulo/****************************/ 1035286441Srpaulo 1036286441Srpaulo/** 1037286441Srpaulo * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1038286441Srpaulo * Addresses are offsets from device's PCI hardware base address. 1039286441Srpaulo */ 1040286441Srpaulo#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1041286441Srpaulo#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1042286441Srpaulo 1043286441Srpaulo/** 1044286441Srpaulo * Keep-Warm (KW) buffer base address. 1045286441Srpaulo * 1046286441Srpaulo * Driver must allocate a 4KByte buffer that is for keeping the 1047286441Srpaulo * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1048286441Srpaulo * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1049286441Srpaulo * from going into a power-savings mode that would cause higher DRAM latency, 1050286441Srpaulo * and possible data over/under-runs, before all Tx/Rx is complete. 1051286441Srpaulo * 1052286441Srpaulo * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1053286441Srpaulo * of the buffer, which must be 4K aligned. Once this is set up, the device 1054286441Srpaulo * automatically invokes keep-warm accesses when normal accesses might not 1055286441Srpaulo * be sufficient to maintain fast DRAM response. 1056286441Srpaulo * 1057286441Srpaulo * Bit fields: 1058286441Srpaulo * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1059286441Srpaulo */ 1060286441Srpaulo#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1061286441Srpaulo 1062286441Srpaulo 1063286441Srpaulo/** 1064286441Srpaulo * TFD Circular Buffers Base (CBBC) addresses 1065286441Srpaulo * 1066286441Srpaulo * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1067286441Srpaulo * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1068286441Srpaulo * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1069286441Srpaulo * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1070286441Srpaulo * aligned (address bits 0-7 must be 0). 1071286441Srpaulo * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1072286441Srpaulo * for them are in different places. 1073286441Srpaulo * 1074286441Srpaulo * Bit fields in each pointer register: 1075286441Srpaulo * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1076286441Srpaulo */ 1077286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1078286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1079286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1080286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1081286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1082286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1083286441Srpaulo 1084286441Srpaulo/* Find TFD CB base pointer for given queue */ 1085286441Srpaulostatic inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1086286441Srpaulo{ 1087286441Srpaulo if (chnl < 16) 1088286441Srpaulo return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1089286441Srpaulo if (chnl < 20) 1090286441Srpaulo return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1091286441Srpaulo return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1092286441Srpaulo} 1093286441Srpaulo 1094286441Srpaulo 1095286441Srpaulo/** 1096286441Srpaulo * Rx SRAM Control and Status Registers (RSCSR) 1097286441Srpaulo * 1098286441Srpaulo * These registers provide handshake between driver and device for the Rx queue 1099286441Srpaulo * (this queue handles *all* command responses, notifications, Rx data, etc. 1100286441Srpaulo * sent from uCode to host driver). Unlike Tx, there is only one Rx 1101286441Srpaulo * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1102286441Srpaulo * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1103286441Srpaulo * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1104286441Srpaulo * mapping between RBDs and RBs. 1105286441Srpaulo * 1106286441Srpaulo * Driver must allocate host DRAM memory for the following, and set the 1107286441Srpaulo * physical address of each into device registers: 1108286441Srpaulo * 1109286441Srpaulo * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1110286441Srpaulo * entries (although any power of 2, up to 4096, is selectable by driver). 1111286441Srpaulo * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1112286441Srpaulo * (typically 4K, although 8K or 16K are also selectable by driver). 1113286441Srpaulo * Driver sets up RB size and number of RBDs in the CB via Rx config 1114286441Srpaulo * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1115286441Srpaulo * 1116286441Srpaulo * Bit fields within one RBD: 1117286441Srpaulo * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1118286441Srpaulo * 1119286441Srpaulo * Driver sets physical address [35:8] of base of RBD circular buffer 1120286441Srpaulo * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1121286441Srpaulo * 1122286441Srpaulo * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1123286441Srpaulo * (RBs) have been filled, via a "write pointer", actually the index of 1124286441Srpaulo * the RB's corresponding RBD within the circular buffer. Driver sets 1125286441Srpaulo * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1126286441Srpaulo * 1127286441Srpaulo * Bit fields in lower dword of Rx status buffer (upper dword not used 1128286441Srpaulo * by driver: 1129286441Srpaulo * 31-12: Not used by driver 1130286441Srpaulo * 11- 0: Index of last filled Rx buffer descriptor 1131286441Srpaulo * (device writes, driver reads this value) 1132286441Srpaulo * 1133286441Srpaulo * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1134286441Srpaulo * enter pointers to these RBs into contiguous RBD circular buffer entries, 1135286441Srpaulo * and update the device's "write" index register, 1136286441Srpaulo * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1137286441Srpaulo * 1138286441Srpaulo * This "write" index corresponds to the *next* RBD that the driver will make 1139286441Srpaulo * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1140286441Srpaulo * the circular buffer. This value should initially be 0 (before preparing any 1141286441Srpaulo * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1142286441Srpaulo * wrap back to 0 at the end of the circular buffer (but don't wrap before 1143286441Srpaulo * "read" index has advanced past 1! See below). 1144286441Srpaulo * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1145286441Srpaulo * 1146286441Srpaulo * As the device fills RBs (referenced from contiguous RBDs within the circular 1147286441Srpaulo * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1148286441Srpaulo * to tell the driver the index of the latest filled RBD. The driver must 1149286441Srpaulo * read this "read" index from DRAM after receiving an Rx interrupt from device 1150286441Srpaulo * 1151286441Srpaulo * The driver must also internally keep track of a third index, which is the 1152286441Srpaulo * next RBD to process. When receiving an Rx interrupt, driver should process 1153286441Srpaulo * all filled but unprocessed RBs up to, but not including, the RB 1154286441Srpaulo * corresponding to the "read" index. For example, if "read" index becomes "1", 1155286441Srpaulo * driver may process the RB pointed to by RBD 0. Depending on volume of 1156286441Srpaulo * traffic, there may be many RBs to process. 1157286441Srpaulo * 1158286441Srpaulo * If read index == write index, device thinks there is no room to put new data. 1159286441Srpaulo * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1160286441Srpaulo * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1161286441Srpaulo * and "read" indexes; that is, make sure that there are no more than 254 1162286441Srpaulo * buffers waiting to be filled. 1163286441Srpaulo */ 1164286441Srpaulo#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1165286441Srpaulo#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1166286441Srpaulo#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1167286441Srpaulo 1168286441Srpaulo/** 1169286441Srpaulo * Physical base address of 8-byte Rx Status buffer. 1170286441Srpaulo * Bit fields: 1171286441Srpaulo * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1172286441Srpaulo */ 1173286441Srpaulo#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1174286441Srpaulo 1175286441Srpaulo/** 1176286441Srpaulo * Physical base address of Rx Buffer Descriptor Circular Buffer. 1177286441Srpaulo * Bit fields: 1178286441Srpaulo * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1179286441Srpaulo */ 1180286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1181286441Srpaulo 1182286441Srpaulo/** 1183286441Srpaulo * Rx write pointer (index, really!). 1184286441Srpaulo * Bit fields: 1185286441Srpaulo * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1186286441Srpaulo * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1187286441Srpaulo */ 1188286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1189286441Srpaulo#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1190286441Srpaulo 1191286441Srpaulo#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1192286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1193286441Srpaulo 1194286441Srpaulo/** 1195286441Srpaulo * Rx Config/Status Registers (RCSR) 1196286441Srpaulo * Rx Config Reg for channel 0 (only channel used) 1197286441Srpaulo * 1198286441Srpaulo * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1199286441Srpaulo * normal operation (see bit fields). 1200286441Srpaulo * 1201286441Srpaulo * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1202286441Srpaulo * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1203286441Srpaulo * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1204286441Srpaulo * 1205286441Srpaulo * Bit fields: 1206286441Srpaulo * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1207286441Srpaulo * '10' operate normally 1208286441Srpaulo * 29-24: reserved 1209286441Srpaulo * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1210286441Srpaulo * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1211286441Srpaulo * 19-18: reserved 1212286441Srpaulo * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1213286441Srpaulo * '10' 12K, '11' 16K. 1214286441Srpaulo * 15-14: reserved 1215286441Srpaulo * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1216286441Srpaulo * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1217286441Srpaulo * typical value 0x10 (about 1/2 msec) 1218286441Srpaulo * 3- 0: reserved 1219286441Srpaulo */ 1220286441Srpaulo#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1221286441Srpaulo#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1222286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1223286441Srpaulo 1224286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1225286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1226286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1227286441Srpaulo 1228286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1229286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1230286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1231286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1232286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1233286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1234286441Srpaulo 1235286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1236286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1237286441Srpaulo#define IWM_RX_RB_TIMEOUT (0x11) 1238286441Srpaulo 1239286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1240286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1241286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1242286441Srpaulo 1243286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1244286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1245286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1246286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1247286441Srpaulo 1248286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1249286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1250286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1251286441Srpaulo 1252286441Srpaulo/** 1253286441Srpaulo * Rx Shared Status Registers (RSSR) 1254286441Srpaulo * 1255286441Srpaulo * After stopping Rx DMA channel (writing 0 to 1256286441Srpaulo * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1257286441Srpaulo * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1258286441Srpaulo * 1259286441Srpaulo * Bit fields: 1260286441Srpaulo * 24: 1 = Channel 0 is idle 1261286441Srpaulo * 1262286441Srpaulo * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1263286441Srpaulo * contain default values that should not be altered by the driver. 1264286441Srpaulo */ 1265286441Srpaulo#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1266286441Srpaulo#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1267286441Srpaulo 1268286441Srpaulo#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1269286441Srpaulo#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1270286441Srpaulo#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1271286441Srpaulo (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1272286441Srpaulo 1273286441Srpaulo#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1274286441Srpaulo 1275286441Srpaulo#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1276286441Srpaulo 1277286441Srpaulo/* TFDB Area - TFDs buffer table */ 1278286441Srpaulo#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1279286441Srpaulo#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1280286441Srpaulo#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1281286441Srpaulo#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1282286441Srpaulo#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1283286441Srpaulo 1284286441Srpaulo/** 1285286441Srpaulo * Transmit DMA Channel Control/Status Registers (TCSR) 1286286441Srpaulo * 1287286441Srpaulo * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1288286441Srpaulo * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1289286441Srpaulo * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1290286441Srpaulo * 1291286441Srpaulo * To use a Tx DMA channel, driver must initialize its 1292286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1293286441Srpaulo * 1294286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1295286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1296286441Srpaulo * 1297286441Srpaulo * All other bits should be 0. 1298286441Srpaulo * 1299286441Srpaulo * Bit fields: 1300286441Srpaulo * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1301286441Srpaulo * '10' operate normally 1302286441Srpaulo * 29- 4: Reserved, set to "0" 1303286441Srpaulo * 3: Enable internal DMA requests (1, normal operation), disable (0) 1304286441Srpaulo * 2- 0: Reserved, set to "0" 1305286441Srpaulo */ 1306286441Srpaulo#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1307286441Srpaulo#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1308286441Srpaulo 1309286441Srpaulo/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1310286441Srpaulo#define IWM_FH_TCSR_CHNL_NUM (8) 1311286441Srpaulo 1312286441Srpaulo/* TCSR: tx_config register values */ 1313286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1314286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1315286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1316286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1317286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1318286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1319286441Srpaulo 1320286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1321286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1322286441Srpaulo 1323286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1324286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1325286441Srpaulo 1326286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1327286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1328286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1329286441Srpaulo 1330286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1331286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1332286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1333286441Srpaulo 1334286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1335286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1336286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1337286441Srpaulo 1338286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1339286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1340286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1341286441Srpaulo 1342286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1343286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1344286441Srpaulo 1345286441Srpaulo/** 1346286441Srpaulo * Tx Shared Status Registers (TSSR) 1347286441Srpaulo * 1348286441Srpaulo * After stopping Tx DMA channel (writing 0 to 1349286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1350286441Srpaulo * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1351286441Srpaulo * (channel's buffers empty | no pending requests). 1352286441Srpaulo * 1353286441Srpaulo * Bit fields: 1354286441Srpaulo * 31-24: 1 = Channel buffers empty (channel 7:0) 1355286441Srpaulo * 23-16: 1 = No pending requests (channel 7:0) 1356286441Srpaulo */ 1357286441Srpaulo#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1358286441Srpaulo#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1359286441Srpaulo 1360286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1361286441Srpaulo 1362286441Srpaulo/** 1363286441Srpaulo * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1364286441Srpaulo * 31: Indicates an address error when accessed to internal memory 1365286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1366286441Srpaulo * 30: Indicates that Host did not send the expected number of dwords to FH 1367286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1368286441Srpaulo * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1369286441Srpaulo * command was received from the scheduler while the TRB was already full 1370286441Srpaulo * with previous command 1371286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1372286441Srpaulo * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1373286441Srpaulo * bit is set, it indicates that the FH has received a full indication 1374286441Srpaulo * from the RTC TxFIFO and the current value of the TxCredit counter was 1375286441Srpaulo * not equal to zero. This mean that the credit mechanism was not 1376286441Srpaulo * synchronized to the TxFIFO status 1377286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1378286441Srpaulo */ 1379286441Srpaulo#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1380286441Srpaulo#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1381286441Srpaulo 1382286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1383286441Srpaulo 1384286441Srpaulo/* Tx service channels */ 1385286441Srpaulo#define IWM_FH_SRVC_CHNL (9) 1386286441Srpaulo#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1387286441Srpaulo#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1388286441Srpaulo#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1389286441Srpaulo (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1390286441Srpaulo 1391286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1392286441Srpaulo#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1393286441Srpaulo (_chan) * 4) 1394286441Srpaulo 1395286441Srpaulo/* Instruct FH to increment the retry count of a packet when 1396286441Srpaulo * it is brought from the memory to TX-FIFO 1397286441Srpaulo */ 1398286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1399286441Srpaulo 1400286441Srpaulo#define IWM_RX_QUEUE_SIZE 256 1401286441Srpaulo#define IWM_RX_QUEUE_MASK 255 1402286441Srpaulo#define IWM_RX_QUEUE_SIZE_LOG 8 1403286441Srpaulo 1404286441Srpaulo/* 1405286441Srpaulo * RX related structures and functions 1406286441Srpaulo */ 1407286441Srpaulo#define IWM_RX_FREE_BUFFERS 64 1408286441Srpaulo#define IWM_RX_LOW_WATERMARK 8 1409286441Srpaulo 1410286441Srpaulo/** 1411286441Srpaulo * struct iwm_rb_status - reseve buffer status 1412286441Srpaulo * host memory mapped FH registers 1413286441Srpaulo * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1414286441Srpaulo * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1415286441Srpaulo * @finished_rb_num [0:11] - Indicates the index of the current RB 1416286441Srpaulo * in which the last frame was written to 1417286441Srpaulo * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1418286441Srpaulo * which was transferred 1419286441Srpaulo */ 1420286441Srpaulostruct iwm_rb_status { 1421286441Srpaulo uint16_t closed_rb_num; 1422286441Srpaulo uint16_t closed_fr_num; 1423286441Srpaulo uint16_t finished_rb_num; 1424286441Srpaulo uint16_t finished_fr_nam; 1425286441Srpaulo uint32_t unused; 1426286441Srpaulo} __packed; 1427286441Srpaulo 1428286441Srpaulo 1429286441Srpaulo#define IWM_TFD_QUEUE_SIZE_MAX (256) 1430286441Srpaulo#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1431286441Srpaulo#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1432286441Srpaulo IWM_TFD_QUEUE_SIZE_BC_DUP) 1433286441Srpaulo#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1434286441Srpaulo#define IWM_NUM_OF_TBS 20 1435286441Srpaulo 1436286441Srpaulostatic inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1437286441Srpaulo{ 1438286441Srpaulo return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1439286441Srpaulo} 1440286441Srpaulo/** 1441286441Srpaulo * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1442286441Srpaulo * 1443286441Srpaulo * This structure contains dma address and length of transmission address 1444286441Srpaulo * 1445286441Srpaulo * @lo: low [31:0] portion of the dma address of TX buffer 1446286441Srpaulo * every even is unaligned on 16 bit boundary 1447286441Srpaulo * @hi_n_len 0-3 [35:32] portion of dma 1448286441Srpaulo * 4-15 length of the tx buffer 1449286441Srpaulo */ 1450286441Srpaulostruct iwm_tfd_tb { 1451286441Srpaulo uint32_t lo; 1452286441Srpaulo uint16_t hi_n_len; 1453286441Srpaulo} __packed; 1454286441Srpaulo 1455286441Srpaulo/** 1456286441Srpaulo * struct iwm_tfd 1457286441Srpaulo * 1458286441Srpaulo * Transmit Frame Descriptor (TFD) 1459286441Srpaulo * 1460286441Srpaulo * @ __reserved1[3] reserved 1461286441Srpaulo * @ num_tbs 0-4 number of active tbs 1462286441Srpaulo * 5 reserved 1463286441Srpaulo * 6-7 padding (not used) 1464286441Srpaulo * @ tbs[20] transmit frame buffer descriptors 1465286441Srpaulo * @ __pad padding 1466286441Srpaulo * 1467286441Srpaulo * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1468286441Srpaulo * Both driver and device share these circular buffers, each of which must be 1469286441Srpaulo * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1470286441Srpaulo * 1471286441Srpaulo * Driver must indicate the physical address of the base of each 1472286441Srpaulo * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1473286441Srpaulo * 1474286441Srpaulo * Each TFD contains pointer/size information for up to 20 data buffers 1475286441Srpaulo * in host DRAM. These buffers collectively contain the (one) frame described 1476286441Srpaulo * by the TFD. Each buffer must be a single contiguous block of memory within 1477286441Srpaulo * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1478286441Srpaulo * of (4K - 4). The concatenates all of a TFD's buffers into a single 1479286441Srpaulo * Tx frame, up to 8 KBytes in size. 1480286441Srpaulo * 1481286441Srpaulo * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1482286441Srpaulo */ 1483286441Srpaulostruct iwm_tfd { 1484286441Srpaulo uint8_t __reserved1[3]; 1485286441Srpaulo uint8_t num_tbs; 1486286441Srpaulo struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1487286441Srpaulo uint32_t __pad; 1488286441Srpaulo} __packed; 1489286441Srpaulo 1490286441Srpaulo/* Keep Warm Size */ 1491286441Srpaulo#define IWM_KW_SIZE 0x1000 /* 4k */ 1492286441Srpaulo 1493286441Srpaulo/* Fixed (non-configurable) rx data from phy */ 1494286441Srpaulo 1495286441Srpaulo/** 1496286441Srpaulo * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1497286441Srpaulo * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1498286441Srpaulo * @tfd_offset 0-12 - tx command byte count 1499286441Srpaulo * 12-16 - station index 1500286441Srpaulo */ 1501286441Srpaulostruct iwm_agn_scd_bc_tbl { 1502286441Srpaulo uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1503286441Srpaulo} __packed; 1504286441Srpaulo 1505286441Srpaulo/* 1506286441Srpaulo * END iwl-fh.h 1507286441Srpaulo */ 1508286441Srpaulo 1509286441Srpaulo/* 1510286441Srpaulo * BEGIN mvm/fw-api.h 1511286441Srpaulo */ 1512286441Srpaulo 1513286441Srpaulo/* maximal number of Tx queues in any platform */ 1514286441Srpaulo#define IWM_MVM_MAX_QUEUES 20 1515286441Srpaulo 1516286441Srpaulo/* Tx queue numbers */ 1517286441Srpauloenum { 1518286441Srpaulo IWM_MVM_OFFCHANNEL_QUEUE = 8, 1519286441Srpaulo IWM_MVM_CMD_QUEUE = 9, 1520286441Srpaulo}; 1521286441Srpaulo 1522286441Srpaulo#define IWM_MVM_CMD_FIFO 7 1523286441Srpaulo 1524286441Srpaulo#define IWM_MVM_STATION_COUNT 16 1525286441Srpaulo 1526286441Srpaulo/* commands */ 1527286441Srpauloenum { 1528286441Srpaulo IWM_MVM_ALIVE = 0x1, 1529286441Srpaulo IWM_REPLY_ERROR = 0x2, 1530286441Srpaulo 1531286441Srpaulo IWM_INIT_COMPLETE_NOTIF = 0x4, 1532286441Srpaulo 1533286441Srpaulo /* PHY context commands */ 1534286441Srpaulo IWM_PHY_CONTEXT_CMD = 0x8, 1535286441Srpaulo IWM_DBG_CFG = 0x9, 1536286441Srpaulo 1537286441Srpaulo /* station table */ 1538286441Srpaulo IWM_ADD_STA_KEY = 0x17, 1539286441Srpaulo IWM_ADD_STA = 0x18, 1540286441Srpaulo IWM_REMOVE_STA = 0x19, 1541286441Srpaulo 1542286441Srpaulo /* TX */ 1543286441Srpaulo IWM_TX_CMD = 0x1c, 1544286441Srpaulo IWM_TXPATH_FLUSH = 0x1e, 1545286441Srpaulo IWM_MGMT_MCAST_KEY = 0x1f, 1546286441Srpaulo 1547286441Srpaulo /* global key */ 1548286441Srpaulo IWM_WEP_KEY = 0x20, 1549286441Srpaulo 1550286441Srpaulo /* MAC and Binding commands */ 1551286441Srpaulo IWM_MAC_CONTEXT_CMD = 0x28, 1552286441Srpaulo IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1553286441Srpaulo IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1554286441Srpaulo IWM_BINDING_CONTEXT_CMD = 0x2b, 1555286441Srpaulo IWM_TIME_QUOTA_CMD = 0x2c, 1556286441Srpaulo IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1557286441Srpaulo 1558286441Srpaulo IWM_LQ_CMD = 0x4e, 1559286441Srpaulo 1560286441Srpaulo /* Calibration */ 1561286441Srpaulo IWM_TEMPERATURE_NOTIFICATION = 0x62, 1562286441Srpaulo IWM_CALIBRATION_CFG_CMD = 0x65, 1563286441Srpaulo IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1564286441Srpaulo IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1565286441Srpaulo IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1566286441Srpaulo 1567286441Srpaulo /* Scan offload */ 1568286441Srpaulo IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1569286441Srpaulo IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1570286441Srpaulo IWM_SCAN_OFFLOAD_COMPLETE = 0x6D, 1571286441Srpaulo IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E, 1572286441Srpaulo IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1573286441Srpaulo IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1574286441Srpaulo 1575286441Srpaulo /* Phy */ 1576286441Srpaulo IWM_PHY_CONFIGURATION_CMD = 0x6a, 1577286441Srpaulo IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1578286441Srpaulo /* IWM_PHY_DB_CMD = 0x6c, */ 1579286441Srpaulo 1580286441Srpaulo /* Power - legacy power table command */ 1581286441Srpaulo IWM_POWER_TABLE_CMD = 0x77, 1582286441Srpaulo IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1583286441Srpaulo 1584286441Srpaulo /* Thermal Throttling*/ 1585286441Srpaulo IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1586286441Srpaulo 1587286441Srpaulo /* Scanning */ 1588286441Srpaulo IWM_SCAN_REQUEST_CMD = 0x80, 1589286441Srpaulo IWM_SCAN_ABORT_CMD = 0x81, 1590286441Srpaulo IWM_SCAN_START_NOTIFICATION = 0x82, 1591286441Srpaulo IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1592286441Srpaulo IWM_SCAN_COMPLETE_NOTIFICATION = 0x84, 1593286441Srpaulo 1594286441Srpaulo /* NVM */ 1595286441Srpaulo IWM_NVM_ACCESS_CMD = 0x88, 1596286441Srpaulo 1597286441Srpaulo IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1598286441Srpaulo 1599286441Srpaulo IWM_BEACON_NOTIFICATION = 0x90, 1600286441Srpaulo IWM_BEACON_TEMPLATE_CMD = 0x91, 1601286441Srpaulo IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1602286441Srpaulo IWM_BT_CONFIG = 0x9b, 1603286441Srpaulo IWM_STATISTICS_NOTIFICATION = 0x9d, 1604286441Srpaulo IWM_REDUCE_TX_POWER_CMD = 0x9f, 1605286441Srpaulo 1606286441Srpaulo /* RF-KILL commands and notifications */ 1607286441Srpaulo IWM_CARD_STATE_CMD = 0xa0, 1608286441Srpaulo IWM_CARD_STATE_NOTIFICATION = 0xa1, 1609286441Srpaulo 1610286441Srpaulo IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1611286441Srpaulo 1612286441Srpaulo /* Power - new power table command */ 1613286441Srpaulo IWM_MAC_PM_POWER_TABLE = 0xa9, 1614286441Srpaulo 1615286441Srpaulo IWM_REPLY_RX_PHY_CMD = 0xc0, 1616286441Srpaulo IWM_REPLY_RX_MPDU_CMD = 0xc1, 1617286441Srpaulo IWM_BA_NOTIF = 0xc5, 1618286441Srpaulo 1619286441Srpaulo /* BT Coex */ 1620286441Srpaulo IWM_BT_COEX_PRIO_TABLE = 0xcc, 1621286441Srpaulo IWM_BT_COEX_PROT_ENV = 0xcd, 1622286441Srpaulo IWM_BT_PROFILE_NOTIFICATION = 0xce, 1623286441Srpaulo IWM_BT_COEX_CI = 0x5d, 1624286441Srpaulo 1625286441Srpaulo IWM_REPLY_SF_CFG_CMD = 0xd1, 1626286441Srpaulo IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1627286441Srpaulo 1628286441Srpaulo IWM_REPLY_DEBUG_CMD = 0xf0, 1629286441Srpaulo IWM_DEBUG_LOG_MSG = 0xf7, 1630286441Srpaulo 1631286441Srpaulo IWM_MCAST_FILTER_CMD = 0xd0, 1632286441Srpaulo 1633286441Srpaulo /* D3 commands/notifications */ 1634286441Srpaulo IWM_D3_CONFIG_CMD = 0xd3, 1635286441Srpaulo IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1636286441Srpaulo IWM_OFFLOADS_QUERY_CMD = 0xd5, 1637286441Srpaulo IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1638286441Srpaulo 1639286441Srpaulo /* for WoWLAN in particular */ 1640286441Srpaulo IWM_WOWLAN_PATTERNS = 0xe0, 1641286441Srpaulo IWM_WOWLAN_CONFIGURATION = 0xe1, 1642286441Srpaulo IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1643286441Srpaulo IWM_WOWLAN_TKIP_PARAM = 0xe3, 1644286441Srpaulo IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1645286441Srpaulo IWM_WOWLAN_GET_STATUSES = 0xe5, 1646286441Srpaulo IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1647286441Srpaulo 1648286441Srpaulo /* and for NetDetect */ 1649286441Srpaulo IWM_NET_DETECT_CONFIG_CMD = 0x54, 1650286441Srpaulo IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1651286441Srpaulo IWM_NET_DETECT_PROFILES_CMD = 0x57, 1652286441Srpaulo IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1653286441Srpaulo IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1654286441Srpaulo 1655286441Srpaulo IWM_REPLY_MAX = 0xff, 1656286441Srpaulo}; 1657286441Srpaulo 1658286441Srpaulo/** 1659286441Srpaulo * struct iwm_cmd_response - generic response struct for most commands 1660286441Srpaulo * @status: status of the command asked, changes for each one 1661286441Srpaulo */ 1662286441Srpaulostruct iwm_cmd_response { 1663286441Srpaulo uint32_t status; 1664286441Srpaulo}; 1665286441Srpaulo 1666286441Srpaulo/* 1667286441Srpaulo * struct iwm_tx_ant_cfg_cmd 1668286441Srpaulo * @valid: valid antenna configuration 1669286441Srpaulo */ 1670286441Srpaulostruct iwm_tx_ant_cfg_cmd { 1671286441Srpaulo uint32_t valid; 1672286441Srpaulo} __packed; 1673286441Srpaulo 1674286441Srpaulo/** 1675286441Srpaulo * struct iwm_reduce_tx_power_cmd - TX power reduction command 1676286441Srpaulo * IWM_REDUCE_TX_POWER_CMD = 0x9f 1677286441Srpaulo * @flags: (reserved for future implementation) 1678286441Srpaulo * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1679286441Srpaulo * @pwr_restriction: TX power restriction in dBms. 1680286441Srpaulo */ 1681286441Srpaulostruct iwm_reduce_tx_power_cmd { 1682286441Srpaulo uint8_t flags; 1683286441Srpaulo uint8_t mac_context_id; 1684286441Srpaulo uint16_t pwr_restriction; 1685286441Srpaulo} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1686286441Srpaulo 1687286441Srpaulo/* 1688286441Srpaulo * Calibration control struct. 1689286441Srpaulo * Sent as part of the phy configuration command. 1690286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 1691286441Srpaulo * flow triggers. 1692286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 1693286441Srpaulo * event triggers. 1694286441Srpaulo */ 1695286441Srpaulostruct iwm_calib_ctrl { 1696286441Srpaulo uint32_t flow_trigger; 1697286441Srpaulo uint32_t event_trigger; 1698286441Srpaulo} __packed; 1699286441Srpaulo 1700286441Srpaulo/* This enum defines the bitmap of various calibrations to enable in both 1701286441Srpaulo * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1702286441Srpaulo */ 1703286441Srpauloenum iwm_calib_cfg { 1704286441Srpaulo IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1705286441Srpaulo IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1706286441Srpaulo IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1707286441Srpaulo IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1708286441Srpaulo IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1709286441Srpaulo IWM_CALIB_CFG_DC_IDX = (1 << 5), 1710286441Srpaulo IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1711286441Srpaulo IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1712286441Srpaulo IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1713286441Srpaulo IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1714286441Srpaulo IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1715286441Srpaulo IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1716286441Srpaulo IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1717286441Srpaulo IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1718286441Srpaulo IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1719286441Srpaulo IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1720286441Srpaulo IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1721286441Srpaulo IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1722286441Srpaulo IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1723286441Srpaulo}; 1724286441Srpaulo 1725286441Srpaulo/* 1726286441Srpaulo * Phy configuration command. 1727286441Srpaulo */ 1728286441Srpaulostruct iwm_phy_cfg_cmd { 1729286441Srpaulo uint32_t phy_cfg; 1730286441Srpaulo struct iwm_calib_ctrl calib_control; 1731286441Srpaulo} __packed; 1732286441Srpaulo 1733286441Srpaulo#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1734286441Srpaulo#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1735286441Srpaulo#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1736286441Srpaulo#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1737286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1738286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1739286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1740286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1741286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1742286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1743286441Srpaulo 1744286441Srpaulo 1745286441Srpaulo/* Target of the IWM_NVM_ACCESS_CMD */ 1746286441Srpauloenum { 1747286441Srpaulo IWM_NVM_ACCESS_TARGET_CACHE = 0, 1748286441Srpaulo IWM_NVM_ACCESS_TARGET_OTP = 1, 1749286441Srpaulo IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1750286441Srpaulo}; 1751286441Srpaulo 1752286441Srpaulo/* Section types for IWM_NVM_ACCESS_CMD */ 1753286441Srpauloenum { 1754286441Srpaulo IWM_NVM_SECTION_TYPE_HW = 0, 1755286441Srpaulo IWM_NVM_SECTION_TYPE_SW, 1756286441Srpaulo IWM_NVM_SECTION_TYPE_PAPD, 1757286441Srpaulo IWM_NVM_SECTION_TYPE_BT, 1758286441Srpaulo IWM_NVM_SECTION_TYPE_CALIBRATION, 1759286441Srpaulo IWM_NVM_SECTION_TYPE_PRODUCTION, 1760286441Srpaulo IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 1761286441Srpaulo IWM_NVM_NUM_OF_SECTIONS, 1762286441Srpaulo}; 1763286441Srpaulo 1764286441Srpaulo/** 1765286441Srpaulo * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 1766286441Srpaulo * @op_code: 0 - read, 1 - write 1767286441Srpaulo * @target: IWM_NVM_ACCESS_TARGET_* 1768286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 1769286441Srpaulo * @offset: offset in bytes into the section 1770286441Srpaulo * @length: in bytes, to read/write 1771286441Srpaulo * @data: if write operation, the data to write. On read its empty 1772286441Srpaulo */ 1773286441Srpaulostruct iwm_nvm_access_cmd { 1774286441Srpaulo uint8_t op_code; 1775286441Srpaulo uint8_t target; 1776286441Srpaulo uint16_t type; 1777286441Srpaulo uint16_t offset; 1778286441Srpaulo uint16_t length; 1779286441Srpaulo uint8_t data[]; 1780286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 1781286441Srpaulo 1782286441Srpaulo/** 1783286441Srpaulo * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 1784286441Srpaulo * @offset: offset in bytes into the section 1785286441Srpaulo * @length: in bytes, either how much was written or read 1786286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 1787286441Srpaulo * @status: 0 for success, fail otherwise 1788286441Srpaulo * @data: if read operation, the data returned. Empty on write. 1789286441Srpaulo */ 1790286441Srpaulostruct iwm_nvm_access_resp { 1791286441Srpaulo uint16_t offset; 1792286441Srpaulo uint16_t length; 1793286441Srpaulo uint16_t type; 1794286441Srpaulo uint16_t status; 1795286441Srpaulo uint8_t data[]; 1796286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 1797286441Srpaulo 1798286441Srpaulo/* IWM_MVM_ALIVE 0x1 */ 1799286441Srpaulo 1800286441Srpaulo/* alive response is_valid values */ 1801286441Srpaulo#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 1802286441Srpaulo#define IWM_ALIVE_RESP_RFKILL (1 << 1) 1803286441Srpaulo 1804286441Srpaulo/* alive response ver_type values */ 1805286441Srpauloenum { 1806286441Srpaulo IWM_FW_TYPE_HW = 0, 1807286441Srpaulo IWM_FW_TYPE_PROT = 1, 1808286441Srpaulo IWM_FW_TYPE_AP = 2, 1809286441Srpaulo IWM_FW_TYPE_WOWLAN = 3, 1810286441Srpaulo IWM_FW_TYPE_TIMING = 4, 1811286441Srpaulo IWM_FW_TYPE_WIPAN = 5 1812286441Srpaulo}; 1813286441Srpaulo 1814286441Srpaulo/* alive response ver_subtype values */ 1815286441Srpauloenum { 1816286441Srpaulo IWM_FW_SUBTYPE_FULL_FEATURE = 0, 1817286441Srpaulo IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 1818286441Srpaulo IWM_FW_SUBTYPE_REDUCED = 2, 1819286441Srpaulo IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 1820286441Srpaulo IWM_FW_SUBTYPE_WOWLAN = 4, 1821286441Srpaulo IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 1822286441Srpaulo IWM_FW_SUBTYPE_WIPAN = 6, 1823286441Srpaulo IWM_FW_SUBTYPE_INITIALIZE = 9 1824286441Srpaulo}; 1825286441Srpaulo 1826286441Srpaulo#define IWM_ALIVE_STATUS_ERR 0xDEAD 1827286441Srpaulo#define IWM_ALIVE_STATUS_OK 0xCAFE 1828286441Srpaulo 1829286441Srpaulo#define IWM_ALIVE_FLG_RFKILL (1 << 0) 1830286441Srpaulo 1831286441Srpaulostruct iwm_mvm_alive_resp { 1832286441Srpaulo uint16_t status; 1833286441Srpaulo uint16_t flags; 1834286441Srpaulo uint8_t ucode_minor; 1835286441Srpaulo uint8_t ucode_major; 1836286441Srpaulo uint16_t id; 1837286441Srpaulo uint8_t api_minor; 1838286441Srpaulo uint8_t api_major; 1839286441Srpaulo uint8_t ver_subtype; 1840286441Srpaulo uint8_t ver_type; 1841286441Srpaulo uint8_t mac; 1842286441Srpaulo uint8_t opt; 1843286441Srpaulo uint16_t reserved2; 1844286441Srpaulo uint32_t timestamp; 1845286441Srpaulo uint32_t error_event_table_ptr; /* SRAM address for error log */ 1846286441Srpaulo uint32_t log_event_table_ptr; /* SRAM address for event log */ 1847286441Srpaulo uint32_t cpu_register_ptr; 1848286441Srpaulo uint32_t dbgm_config_ptr; 1849286441Srpaulo uint32_t alive_counter_ptr; 1850286441Srpaulo uint32_t scd_base_ptr; /* SRAM address for SCD */ 1851286441Srpaulo} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 1852286441Srpaulo 1853286441Srpaulo/* Error response/notification */ 1854286441Srpauloenum { 1855286441Srpaulo IWM_FW_ERR_UNKNOWN_CMD = 0x0, 1856286441Srpaulo IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 1857286441Srpaulo IWM_FW_ERR_SERVICE = 0x2, 1858286441Srpaulo IWM_FW_ERR_ARC_MEMORY = 0x3, 1859286441Srpaulo IWM_FW_ERR_ARC_CODE = 0x4, 1860286441Srpaulo IWM_FW_ERR_WATCH_DOG = 0x5, 1861286441Srpaulo IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 1862286441Srpaulo IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 1863286441Srpaulo IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 1864286441Srpaulo IWM_FW_ERR_UNEXPECTED = 0xFE, 1865286441Srpaulo IWM_FW_ERR_FATAL = 0xFF 1866286441Srpaulo}; 1867286441Srpaulo 1868286441Srpaulo/** 1869286441Srpaulo * struct iwm_error_resp - FW error indication 1870286441Srpaulo * ( IWM_REPLY_ERROR = 0x2 ) 1871286441Srpaulo * @error_type: one of IWM_FW_ERR_* 1872298955Spfg * @cmd_id: the command ID for which the error occurred 1873286441Srpaulo * @bad_cmd_seq_num: sequence number of the erroneous command 1874286441Srpaulo * @error_service: which service created the error, applicable only if 1875286441Srpaulo * error_type = 2, otherwise 0 1876286441Srpaulo * @timestamp: TSF in usecs. 1877286441Srpaulo */ 1878286441Srpaulostruct iwm_error_resp { 1879286441Srpaulo uint32_t error_type; 1880286441Srpaulo uint8_t cmd_id; 1881286441Srpaulo uint8_t reserved1; 1882286441Srpaulo uint16_t bad_cmd_seq_num; 1883286441Srpaulo uint32_t error_service; 1884286441Srpaulo uint64_t timestamp; 1885286441Srpaulo} __packed; 1886286441Srpaulo 1887286441Srpaulo 1888286441Srpaulo/* Common PHY, MAC and Bindings definitions */ 1889286441Srpaulo 1890286441Srpaulo#define IWM_MAX_MACS_IN_BINDING (3) 1891286441Srpaulo#define IWM_MAX_BINDINGS (4) 1892286441Srpaulo#define IWM_AUX_BINDING_INDEX (3) 1893286441Srpaulo#define IWM_MAX_PHYS (4) 1894286441Srpaulo 1895286441Srpaulo/* Used to extract ID and color from the context dword */ 1896286441Srpaulo#define IWM_FW_CTXT_ID_POS (0) 1897286441Srpaulo#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 1898286441Srpaulo#define IWM_FW_CTXT_COLOR_POS (8) 1899286441Srpaulo#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 1900286441Srpaulo#define IWM_FW_CTXT_INVALID (0xffffffff) 1901286441Srpaulo 1902286441Srpaulo#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 1903286441Srpaulo (_color << IWM_FW_CTXT_COLOR_POS)) 1904286441Srpaulo 1905286441Srpaulo/* Possible actions on PHYs, MACs and Bindings */ 1906286441Srpauloenum { 1907286441Srpaulo IWM_FW_CTXT_ACTION_STUB = 0, 1908286441Srpaulo IWM_FW_CTXT_ACTION_ADD, 1909286441Srpaulo IWM_FW_CTXT_ACTION_MODIFY, 1910286441Srpaulo IWM_FW_CTXT_ACTION_REMOVE, 1911286441Srpaulo IWM_FW_CTXT_ACTION_NUM 1912286441Srpaulo}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 1913286441Srpaulo 1914286441Srpaulo/* Time Events */ 1915286441Srpaulo 1916286441Srpaulo/* Time Event types, according to MAC type */ 1917286441Srpauloenum iwm_time_event_type { 1918286441Srpaulo /* BSS Station Events */ 1919286441Srpaulo IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 1920286441Srpaulo IWM_TE_BSS_STA_ASSOC, 1921286441Srpaulo IWM_TE_BSS_EAP_DHCP_PROT, 1922286441Srpaulo IWM_TE_BSS_QUIET_PERIOD, 1923286441Srpaulo 1924286441Srpaulo /* P2P Device Events */ 1925286441Srpaulo IWM_TE_P2P_DEVICE_DISCOVERABLE, 1926286441Srpaulo IWM_TE_P2P_DEVICE_LISTEN, 1927286441Srpaulo IWM_TE_P2P_DEVICE_ACTION_SCAN, 1928286441Srpaulo IWM_TE_P2P_DEVICE_FULL_SCAN, 1929286441Srpaulo 1930286441Srpaulo /* P2P Client Events */ 1931286441Srpaulo IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 1932286441Srpaulo IWM_TE_P2P_CLIENT_ASSOC, 1933286441Srpaulo IWM_TE_P2P_CLIENT_QUIET_PERIOD, 1934286441Srpaulo 1935286441Srpaulo /* P2P GO Events */ 1936286441Srpaulo IWM_TE_P2P_GO_ASSOC_PROT, 1937286441Srpaulo IWM_TE_P2P_GO_REPETITIVE_NOA, 1938286441Srpaulo IWM_TE_P2P_GO_CT_WINDOW, 1939286441Srpaulo 1940286441Srpaulo /* WiDi Sync Events */ 1941286441Srpaulo IWM_TE_WIDI_TX_SYNC, 1942286441Srpaulo 1943286441Srpaulo IWM_TE_MAX 1944286441Srpaulo}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 1945286441Srpaulo 1946286441Srpaulo 1947286441Srpaulo 1948286441Srpaulo/* Time event - defines for command API v1 */ 1949286441Srpaulo 1950286441Srpaulo/* 1951286441Srpaulo * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 1952286441Srpaulo * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 1953286441Srpaulo * the first fragment is scheduled. 1954286441Srpaulo * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 1955286441Srpaulo * the first 2 fragments are scheduled. 1956286441Srpaulo * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 1957286441Srpaulo * number of fragments are valid. 1958286441Srpaulo * 1959286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 1960286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 1961286441Srpaulo * scheduled. 1962286441Srpaulo */ 1963286441Srpauloenum { 1964286441Srpaulo IWM_TE_V1_FRAG_NONE = 0, 1965286441Srpaulo IWM_TE_V1_FRAG_SINGLE = 1, 1966286441Srpaulo IWM_TE_V1_FRAG_DUAL = 2, 1967286441Srpaulo IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 1968286441Srpaulo}; 1969286441Srpaulo 1970286441Srpaulo/* If a Time Event can be fragmented, this is the max number of fragments */ 1971286441Srpaulo#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 1972286441Srpaulo/* Repeat the time event endlessly (until removed) */ 1973286441Srpaulo#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 1974286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 1975286441Srpaulo#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 1976286441Srpaulo 1977286441Srpaulo/* Time Event dependencies: none, on another TE, or in a specific time */ 1978286441Srpauloenum { 1979286441Srpaulo IWM_TE_V1_INDEPENDENT = 0, 1980286441Srpaulo IWM_TE_V1_DEP_OTHER = (1 << 0), 1981286441Srpaulo IWM_TE_V1_DEP_TSF = (1 << 1), 1982286441Srpaulo IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 1983286441Srpaulo}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 1984286441Srpaulo 1985286441Srpaulo/* 1986286441Srpaulo * @IWM_TE_V1_NOTIF_NONE: no notifications 1987286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 1988286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 1989286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 1990286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 1991286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 1992286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 1993286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 1994286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 1995286441Srpaulo * 1996286441Srpaulo * Supported Time event notifications configuration. 1997286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 1998286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 1999286441Srpaulo * notification the status is always success. There is no start/end fragment 2000286441Srpaulo * notification for monolithic events. 2001286441Srpaulo */ 2002286441Srpauloenum { 2003286441Srpaulo IWM_TE_V1_NOTIF_NONE = 0, 2004286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2005286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2006286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2007286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2008286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2009286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2010286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2011286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2012286441Srpaulo}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2013286441Srpaulo 2014286441Srpaulo 2015286441Srpaulo/** 2016286441Srpaulo * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2017286441Srpaulo * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2018286441Srpaulo * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2019286441Srpaulo * ( IWM_TIME_EVENT_CMD = 0x29 ) 2020286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2021286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2022286441Srpaulo * @id: this field has two meanings, depending on the action: 2023286441Srpaulo * If the action is ADD, then it means the type of event to add. 2024286441Srpaulo * For all other actions it is the unique event ID assigned when the 2025286441Srpaulo * event was added by the FW. 2026286441Srpaulo * @apply_time: When to start the Time Event (in GP2) 2027286441Srpaulo * @max_delay: maximum delay to event's start (apply time), in TU 2028286441Srpaulo * @depends_on: the unique ID of the event we depend on (if any) 2029286441Srpaulo * @interval: interval between repetitions, in TU 2030286441Srpaulo * @interval_reciprocal: 2^32 / interval 2031286441Srpaulo * @duration: duration of event in TU 2032286441Srpaulo * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2033286441Srpaulo * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2034286441Srpaulo * and IWM_TE_V1_EVENT_SOCIOPATHIC 2035286441Srpaulo * @is_present: 0 or 1, are we present or absent during the Time Event 2036286441Srpaulo * @max_frags: maximal number of fragments the Time Event can be divided to 2037286441Srpaulo * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2038286441Srpaulo */ 2039286441Srpaulostruct iwm_time_event_cmd_v1 { 2040286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2041286441Srpaulo uint32_t id_and_color; 2042286441Srpaulo uint32_t action; 2043286441Srpaulo uint32_t id; 2044286441Srpaulo /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2045286441Srpaulo uint32_t apply_time; 2046286441Srpaulo uint32_t max_delay; 2047286441Srpaulo uint32_t dep_policy; 2048286441Srpaulo uint32_t depends_on; 2049286441Srpaulo uint32_t is_present; 2050286441Srpaulo uint32_t max_frags; 2051286441Srpaulo uint32_t interval; 2052286441Srpaulo uint32_t interval_reciprocal; 2053286441Srpaulo uint32_t duration; 2054286441Srpaulo uint32_t repeat; 2055286441Srpaulo uint32_t notify; 2056286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2057286441Srpaulo 2058286441Srpaulo 2059286441Srpaulo/* Time event - defines for command API v2 */ 2060286441Srpaulo 2061286441Srpaulo/* 2062286441Srpaulo * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2063286441Srpaulo * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2064286441Srpaulo * the first fragment is scheduled. 2065286441Srpaulo * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2066286441Srpaulo * the first 2 fragments are scheduled. 2067286441Srpaulo * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2068286441Srpaulo * number of fragments are valid. 2069286441Srpaulo * 2070286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2071286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2072286441Srpaulo * scheduled. 2073286441Srpaulo */ 2074286441Srpauloenum { 2075286441Srpaulo IWM_TE_V2_FRAG_NONE = 0, 2076286441Srpaulo IWM_TE_V2_FRAG_SINGLE = 1, 2077286441Srpaulo IWM_TE_V2_FRAG_DUAL = 2, 2078286441Srpaulo IWM_TE_V2_FRAG_MAX = 0xfe, 2079286441Srpaulo IWM_TE_V2_FRAG_ENDLESS = 0xff 2080286441Srpaulo}; 2081286441Srpaulo 2082286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2083286441Srpaulo#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2084286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2085286441Srpaulo#define IWM_TE_V2_REPEAT_MAX 0xfe 2086286441Srpaulo 2087286441Srpaulo#define IWM_TE_V2_PLACEMENT_POS 12 2088286441Srpaulo#define IWM_TE_V2_ABSENCE_POS 15 2089286441Srpaulo 2090286441Srpaulo/* Time event policy values (for time event cmd api v2) 2091286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2092286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2093286441Srpaulo * notification the status is always success. There is no start/end fragment 2094286441Srpaulo * notification for monolithic events. 2095286441Srpaulo * 2096286441Srpaulo * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2097286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2098286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2099286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2100286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2101286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2102286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2103286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2104286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2105286441Srpaulo * @IWM_TE_V2_DEP_OTHER: depends on another time event 2106286441Srpaulo * @IWM_TE_V2_DEP_TSF: depends on a specific time 2107286441Srpaulo * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2108286441Srpaulo * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2109286441Srpaulo */ 2110286441Srpauloenum { 2111286441Srpaulo IWM_TE_V2_DEFAULT_POLICY = 0x0, 2112286441Srpaulo 2113286441Srpaulo /* notifications (event start/stop, fragment start/stop) */ 2114286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2115286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2116286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2117286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2118286441Srpaulo 2119286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2120286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2121286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2122286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2123286441Srpaulo 2124286441Srpaulo IWM_TE_V2_NOTIF_MSK = 0xff, 2125286441Srpaulo 2126286441Srpaulo /* placement characteristics */ 2127286441Srpaulo IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2128286441Srpaulo IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2129286441Srpaulo IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2130286441Srpaulo 2131286441Srpaulo /* are we present or absent during the Time Event. */ 2132286441Srpaulo IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2133286441Srpaulo}; 2134286441Srpaulo 2135286441Srpaulo/** 2136286441Srpaulo * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2137286441Srpaulo * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2138286441Srpaulo * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2139286441Srpaulo * ( IWM_TIME_EVENT_CMD = 0x29 ) 2140286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2141286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2142286441Srpaulo * @id: this field has two meanings, depending on the action: 2143286441Srpaulo * If the action is ADD, then it means the type of event to add. 2144286441Srpaulo * For all other actions it is the unique event ID assigned when the 2145286441Srpaulo * event was added by the FW. 2146286441Srpaulo * @apply_time: When to start the Time Event (in GP2) 2147286441Srpaulo * @max_delay: maximum delay to event's start (apply time), in TU 2148286441Srpaulo * @depends_on: the unique ID of the event we depend on (if any) 2149286441Srpaulo * @interval: interval between repetitions, in TU 2150286441Srpaulo * @duration: duration of event in TU 2151286441Srpaulo * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2152286441Srpaulo * @max_frags: maximal number of fragments the Time Event can be divided to 2153286441Srpaulo * @policy: defines whether uCode shall notify the host or other uCode modules 2154286441Srpaulo * on event and/or fragment start and/or end 2155286441Srpaulo * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2156286441Srpaulo * IWM_TE_EVENT_SOCIOPATHIC 2157286441Srpaulo * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2158286441Srpaulo */ 2159286441Srpaulostruct iwm_time_event_cmd_v2 { 2160286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2161286441Srpaulo uint32_t id_and_color; 2162286441Srpaulo uint32_t action; 2163286441Srpaulo uint32_t id; 2164286441Srpaulo /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2165286441Srpaulo uint32_t apply_time; 2166286441Srpaulo uint32_t max_delay; 2167286441Srpaulo uint32_t depends_on; 2168286441Srpaulo uint32_t interval; 2169286441Srpaulo uint32_t duration; 2170286441Srpaulo uint8_t repeat; 2171286441Srpaulo uint8_t max_frags; 2172286441Srpaulo uint16_t policy; 2173286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2174286441Srpaulo 2175286441Srpaulo/** 2176286441Srpaulo * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2177286441Srpaulo * @status: bit 0 indicates success, all others specify errors 2178286441Srpaulo * @id: the Time Event type 2179286441Srpaulo * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2180286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2181286441Srpaulo */ 2182286441Srpaulostruct iwm_time_event_resp { 2183286441Srpaulo uint32_t status; 2184286441Srpaulo uint32_t id; 2185286441Srpaulo uint32_t unique_id; 2186286441Srpaulo uint32_t id_and_color; 2187286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2188286441Srpaulo 2189286441Srpaulo/** 2190286441Srpaulo * struct iwm_time_event_notif - notifications of time event start/stop 2191286441Srpaulo * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2192286441Srpaulo * @timestamp: action timestamp in GP2 2193286441Srpaulo * @session_id: session's unique id 2194286441Srpaulo * @unique_id: unique id of the Time Event itself 2195286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2196286441Srpaulo * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2197286441Srpaulo * @status: true if scheduled, false otherwise (not executed) 2198286441Srpaulo */ 2199286441Srpaulostruct iwm_time_event_notif { 2200286441Srpaulo uint32_t timestamp; 2201286441Srpaulo uint32_t session_id; 2202286441Srpaulo uint32_t unique_id; 2203286441Srpaulo uint32_t id_and_color; 2204286441Srpaulo uint32_t action; 2205286441Srpaulo uint32_t status; 2206286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2207286441Srpaulo 2208286441Srpaulo 2209286441Srpaulo/* Bindings and Time Quota */ 2210286441Srpaulo 2211286441Srpaulo/** 2212286441Srpaulo * struct iwm_binding_cmd - configuring bindings 2213286441Srpaulo * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2214286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2215286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2216286441Srpaulo * @macs: array of MAC id and colors which belong to the binding 2217286441Srpaulo * @phy: PHY id and color which belongs to the binding 2218286441Srpaulo */ 2219286441Srpaulostruct iwm_binding_cmd { 2220286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2221286441Srpaulo uint32_t id_and_color; 2222286441Srpaulo uint32_t action; 2223286441Srpaulo /* IWM_BINDING_DATA_API_S_VER_1 */ 2224286441Srpaulo uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2225286441Srpaulo uint32_t phy; 2226286441Srpaulo} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2227286441Srpaulo 2228286441Srpaulo/* The maximal number of fragments in the FW's schedule session */ 2229286441Srpaulo#define IWM_MVM_MAX_QUOTA 128 2230286441Srpaulo 2231286441Srpaulo/** 2232286441Srpaulo * struct iwm_time_quota_data - configuration of time quota per binding 2233286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2234286441Srpaulo * @quota: absolute time quota in TU. The scheduler will try to divide the 2235286441Srpaulo * remainig quota (after Time Events) according to this quota. 2236286441Srpaulo * @max_duration: max uninterrupted context duration in TU 2237286441Srpaulo */ 2238286441Srpaulostruct iwm_time_quota_data { 2239286441Srpaulo uint32_t id_and_color; 2240286441Srpaulo uint32_t quota; 2241286441Srpaulo uint32_t max_duration; 2242286441Srpaulo} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2243286441Srpaulo 2244286441Srpaulo/** 2245286441Srpaulo * struct iwm_time_quota_cmd - configuration of time quota between bindings 2246286441Srpaulo * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2247286441Srpaulo * @quotas: allocations per binding 2248286441Srpaulo */ 2249286441Srpaulostruct iwm_time_quota_cmd { 2250286441Srpaulo struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2251286441Srpaulo} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2252286441Srpaulo 2253286441Srpaulo 2254286441Srpaulo/* PHY context */ 2255286441Srpaulo 2256286441Srpaulo/* Supported bands */ 2257286441Srpaulo#define IWM_PHY_BAND_5 (0) 2258286441Srpaulo#define IWM_PHY_BAND_24 (1) 2259286441Srpaulo 2260286441Srpaulo/* Supported channel width, vary if there is VHT support */ 2261286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2262286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2263286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2264286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2265286441Srpaulo 2266286441Srpaulo/* 2267286441Srpaulo * Control channel position: 2268286441Srpaulo * For legacy set bit means upper channel, otherwise lower. 2269286441Srpaulo * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2270286441Srpaulo * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2271286441Srpaulo * center_freq 2272286441Srpaulo * | 2273286441Srpaulo * 40Mhz |_______|_______| 2274286441Srpaulo * 80Mhz |_______|_______|_______|_______| 2275286441Srpaulo * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2276286441Srpaulo * code 011 010 001 000 | 100 101 110 111 2277286441Srpaulo */ 2278286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2279286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2280286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2281286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2282286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2283286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2284286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2285286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2286286441Srpaulo 2287286441Srpaulo/* 2288286441Srpaulo * @band: IWM_PHY_BAND_* 2289286441Srpaulo * @channel: channel number 2290286441Srpaulo * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2291286441Srpaulo * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2292286441Srpaulo */ 2293286441Srpaulostruct iwm_fw_channel_info { 2294286441Srpaulo uint8_t band; 2295286441Srpaulo uint8_t channel; 2296286441Srpaulo uint8_t width; 2297286441Srpaulo uint8_t ctrl_pos; 2298286441Srpaulo} __packed; 2299286441Srpaulo 2300286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2301286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2302286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2303286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2304286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2305286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2306286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2307286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2308286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2309286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2310286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2311286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2312286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2313286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2314286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2315286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2316286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2317286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2318286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2319286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2320286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2321286441Srpaulo 2322286441Srpaulo/* TODO: fix the value, make it depend on firmware at runtime? */ 2323286441Srpaulo#define IWM_NUM_PHY_CTX 3 2324286441Srpaulo 2325286441Srpaulo/* TODO: complete missing documentation */ 2326286441Srpaulo/** 2327286441Srpaulo * struct iwm_phy_context_cmd - config of the PHY context 2328286441Srpaulo * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2329286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2330286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2331286441Srpaulo * @apply_time: 0 means immediate apply and context switch. 2332286441Srpaulo * other value means apply new params after X usecs 2333286441Srpaulo * @tx_param_color: ??? 2334286441Srpaulo * @channel_info: 2335286441Srpaulo * @txchain_info: ??? 2336286441Srpaulo * @rxchain_info: ??? 2337286441Srpaulo * @acquisition_data: ??? 2338286441Srpaulo * @dsp_cfg_flags: set to 0 2339286441Srpaulo */ 2340286441Srpaulostruct iwm_phy_context_cmd { 2341286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2342286441Srpaulo uint32_t id_and_color; 2343286441Srpaulo uint32_t action; 2344286441Srpaulo /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2345286441Srpaulo uint32_t apply_time; 2346286441Srpaulo uint32_t tx_param_color; 2347286441Srpaulo struct iwm_fw_channel_info ci; 2348286441Srpaulo uint32_t txchain_info; 2349286441Srpaulo uint32_t rxchain_info; 2350286441Srpaulo uint32_t acquisition_data; 2351286441Srpaulo uint32_t dsp_cfg_flags; 2352286441Srpaulo} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2353286441Srpaulo 2354286441Srpaulo#define IWM_RX_INFO_PHY_CNT 8 2355286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2356286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2357286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2358286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2359286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2360286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2361286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2362286441Srpaulo 2363286441Srpaulo#define IWM_RX_INFO_AGC_IDX 1 2364286441Srpaulo#define IWM_RX_INFO_RSSI_AB_IDX 2 2365286441Srpaulo#define IWM_OFDM_AGC_A_MSK 0x0000007f 2366286441Srpaulo#define IWM_OFDM_AGC_A_POS 0 2367286441Srpaulo#define IWM_OFDM_AGC_B_MSK 0x00003f80 2368286441Srpaulo#define IWM_OFDM_AGC_B_POS 7 2369286441Srpaulo#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2370286441Srpaulo#define IWM_OFDM_AGC_CODE_POS 20 2371286441Srpaulo#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2372286441Srpaulo#define IWM_OFDM_RSSI_A_POS 0 2373286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2374286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2375286441Srpaulo#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2376286441Srpaulo#define IWM_OFDM_RSSI_B_POS 16 2377286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2378286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2379286441Srpaulo 2380286441Srpaulo/** 2381286441Srpaulo * struct iwm_rx_phy_info - phy info 2382286441Srpaulo * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2383286441Srpaulo * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2384286441Srpaulo * @cfg_phy_cnt: configurable DSP phy data byte count 2385286441Srpaulo * @stat_id: configurable DSP phy data set ID 2386286441Srpaulo * @reserved1: 2387286441Srpaulo * @system_timestamp: GP2 at on air rise 2388286441Srpaulo * @timestamp: TSF at on air rise 2389286441Srpaulo * @beacon_time_stamp: beacon at on-air rise 2390286441Srpaulo * @phy_flags: general phy flags: band, modulation, ... 2391286441Srpaulo * @channel: channel number 2392286441Srpaulo * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2393286441Srpaulo * @rate_n_flags: IWM_RATE_MCS_* 2394286441Srpaulo * @byte_count: frame's byte-count 2395286441Srpaulo * @frame_time: frame's time on the air, based on byte count and frame rate 2396286441Srpaulo * calculation 2397286441Srpaulo * @mac_active_msk: what MACs were active when the frame was received 2398286441Srpaulo * 2399286441Srpaulo * Before each Rx, the device sends this data. It contains PHY information 2400286441Srpaulo * about the reception of the packet. 2401286441Srpaulo */ 2402286441Srpaulostruct iwm_rx_phy_info { 2403286441Srpaulo uint8_t non_cfg_phy_cnt; 2404286441Srpaulo uint8_t cfg_phy_cnt; 2405286441Srpaulo uint8_t stat_id; 2406286441Srpaulo uint8_t reserved1; 2407286441Srpaulo uint32_t system_timestamp; 2408286441Srpaulo uint64_t timestamp; 2409286441Srpaulo uint32_t beacon_time_stamp; 2410286441Srpaulo uint16_t phy_flags; 2411286441Srpaulo#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2412286441Srpaulo uint16_t channel; 2413286441Srpaulo uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2414286441Srpaulo uint8_t rate; 2415286441Srpaulo uint8_t rflags; 2416286441Srpaulo uint16_t xrflags; 2417286441Srpaulo uint32_t byte_count; 2418286441Srpaulo uint16_t mac_active_msk; 2419286441Srpaulo uint16_t frame_time; 2420286441Srpaulo} __packed; 2421286441Srpaulo 2422286441Srpaulostruct iwm_rx_mpdu_res_start { 2423286441Srpaulo uint16_t byte_count; 2424286441Srpaulo uint16_t reserved; 2425286441Srpaulo} __packed; 2426286441Srpaulo 2427286441Srpaulo/** 2428286441Srpaulo * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2429286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2430286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2431286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2432286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2433286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2434286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2435286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2436286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2437286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2438286441Srpaulo */ 2439286441Srpauloenum iwm_rx_phy_flags { 2440286441Srpaulo IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2441286441Srpaulo IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2442286441Srpaulo IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2443286441Srpaulo IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2444286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2445286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2446286441Srpaulo IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2447286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2448286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2449286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2450286441Srpaulo}; 2451286441Srpaulo 2452286441Srpaulo/** 2453286441Srpaulo * enum iwm_mvm_rx_status - written by fw for each Rx packet 2454286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2455286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2456286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2457286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2458286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2459286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2460286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2461286441Srpaulo * in the driver. 2462286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2463286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2464286441Srpaulo * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2465286441Srpaulo * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2466286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2467286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2468286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2469286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2470286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2471286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2472286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2473286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2474286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2475286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2476286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2477286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2478286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2479286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2480286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2481286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2482286441Srpaulo * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2483286441Srpaulo */ 2484286441Srpauloenum iwm_mvm_rx_status { 2485286441Srpaulo IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2486286441Srpaulo IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2487286441Srpaulo IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2488286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2489286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2490286441Srpaulo IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2491286441Srpaulo IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2492286441Srpaulo IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2493286441Srpaulo IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2494286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2495286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2496286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2497286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2498286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2499286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2500286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2501286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2502286441Srpaulo IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2503286441Srpaulo IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2504286441Srpaulo IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2505286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2506286441Srpaulo IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2507286441Srpaulo IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2508286441Srpaulo IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2509286441Srpaulo IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2510286441Srpaulo IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2511286441Srpaulo IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2512286441Srpaulo}; 2513286441Srpaulo 2514286441Srpaulo/** 2515286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2516286441Srpaulo * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2517286441Srpaulo * @radio_flavor: 2518286441Srpaulo * @radio_step: 2519286441Srpaulo * @radio_dash: 2520286441Srpaulo */ 2521286441Srpaulostruct iwm_radio_version_notif { 2522286441Srpaulo uint32_t radio_flavor; 2523286441Srpaulo uint32_t radio_step; 2524286441Srpaulo uint32_t radio_dash; 2525286441Srpaulo} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2526286441Srpaulo 2527286441Srpauloenum iwm_card_state_flags { 2528286441Srpaulo IWM_CARD_ENABLED = 0x00, 2529286441Srpaulo IWM_HW_CARD_DISABLED = 0x01, 2530286441Srpaulo IWM_SW_CARD_DISABLED = 0x02, 2531286441Srpaulo IWM_CT_KILL_CARD_DISABLED = 0x04, 2532286441Srpaulo IWM_HALT_CARD_DISABLED = 0x08, 2533286441Srpaulo IWM_CARD_DISABLED_MSK = 0x0f, 2534286441Srpaulo IWM_CARD_IS_RX_ON = 0x10, 2535286441Srpaulo}; 2536286441Srpaulo 2537286441Srpaulo/** 2538286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2539286441Srpaulo * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2540286441Srpaulo * @flags: %iwm_card_state_flags 2541286441Srpaulo */ 2542286441Srpaulostruct iwm_card_state_notif { 2543286441Srpaulo uint32_t flags; 2544286441Srpaulo} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2545286441Srpaulo 2546286441Srpaulo/** 2547286441Srpaulo * struct iwm_missed_beacons_notif - information on missed beacons 2548286441Srpaulo * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2549286441Srpaulo * @mac_id: interface ID 2550286441Srpaulo * @consec_missed_beacons_since_last_rx: number of consecutive missed 2551286441Srpaulo * beacons since last RX. 2552286441Srpaulo * @consec_missed_beacons: number of consecutive missed beacons 2553286441Srpaulo * @num_expected_beacons: 2554286441Srpaulo * @num_recvd_beacons: 2555286441Srpaulo */ 2556286441Srpaulostruct iwm_missed_beacons_notif { 2557286441Srpaulo uint32_t mac_id; 2558286441Srpaulo uint32_t consec_missed_beacons_since_last_rx; 2559286441Srpaulo uint32_t consec_missed_beacons; 2560286441Srpaulo uint32_t num_expected_beacons; 2561286441Srpaulo uint32_t num_recvd_beacons; 2562286441Srpaulo} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2563286441Srpaulo 2564286441Srpaulo/** 2565286441Srpaulo * struct iwm_set_calib_default_cmd - set default value for calibration. 2566286441Srpaulo * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2567286441Srpaulo * @calib_index: the calibration to set value for 2568286441Srpaulo * @length: of data 2569286441Srpaulo * @data: the value to set for the calibration result 2570286441Srpaulo */ 2571286441Srpaulostruct iwm_set_calib_default_cmd { 2572286441Srpaulo uint16_t calib_index; 2573286441Srpaulo uint16_t length; 2574286441Srpaulo uint8_t data[0]; 2575286441Srpaulo} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2576286441Srpaulo 2577286441Srpaulo#define IWM_MAX_PORT_ID_NUM 2 2578286441Srpaulo#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2579286441Srpaulo 2580286441Srpaulo/** 2581286441Srpaulo * struct iwm_mcast_filter_cmd - configure multicast filter. 2582286441Srpaulo * @filter_own: Set 1 to filter out multicast packets sent by station itself 2583286441Srpaulo * @port_id: Multicast MAC addresses array specifier. This is a strange way 2584286441Srpaulo * to identify network interface adopted in host-device IF. 2585286441Srpaulo * It is used by FW as index in array of addresses. This array has 2586286441Srpaulo * IWM_MAX_PORT_ID_NUM members. 2587286441Srpaulo * @count: Number of MAC addresses in the array 2588286441Srpaulo * @pass_all: Set 1 to pass all multicast packets. 2589286441Srpaulo * @bssid: current association BSSID. 2590286441Srpaulo * @addr_list: Place holder for array of MAC addresses. 2591286441Srpaulo * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2592286441Srpaulo */ 2593286441Srpaulostruct iwm_mcast_filter_cmd { 2594286441Srpaulo uint8_t filter_own; 2595286441Srpaulo uint8_t port_id; 2596286441Srpaulo uint8_t count; 2597286441Srpaulo uint8_t pass_all; 2598286441Srpaulo uint8_t bssid[6]; 2599286441Srpaulo uint8_t reserved[2]; 2600286441Srpaulo uint8_t addr_list[0]; 2601286441Srpaulo} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2602286441Srpaulo 2603286441Srpaulostruct iwm_mvm_statistics_dbg { 2604286441Srpaulo uint32_t burst_check; 2605286441Srpaulo uint32_t burst_count; 2606286441Srpaulo uint32_t wait_for_silence_timeout_cnt; 2607286441Srpaulo uint32_t reserved[3]; 2608286441Srpaulo} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2609286441Srpaulo 2610286441Srpaulostruct iwm_mvm_statistics_div { 2611286441Srpaulo uint32_t tx_on_a; 2612286441Srpaulo uint32_t tx_on_b; 2613286441Srpaulo uint32_t exec_time; 2614286441Srpaulo uint32_t probe_time; 2615286441Srpaulo uint32_t rssi_ant; 2616286441Srpaulo uint32_t reserved2; 2617286441Srpaulo} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2618286441Srpaulo 2619286441Srpaulostruct iwm_mvm_statistics_general_common { 2620286441Srpaulo uint32_t temperature; /* radio temperature */ 2621286441Srpaulo uint32_t temperature_m; /* radio voltage */ 2622286441Srpaulo struct iwm_mvm_statistics_dbg dbg; 2623286441Srpaulo uint32_t sleep_time; 2624286441Srpaulo uint32_t slots_out; 2625286441Srpaulo uint32_t slots_idle; 2626286441Srpaulo uint32_t ttl_timestamp; 2627286441Srpaulo struct iwm_mvm_statistics_div div; 2628286441Srpaulo uint32_t rx_enable_counter; 2629286441Srpaulo /* 2630286441Srpaulo * num_of_sos_states: 2631286441Srpaulo * count the number of times we have to re-tune 2632286441Srpaulo * in order to get out of bad PHY status 2633286441Srpaulo */ 2634286441Srpaulo uint32_t num_of_sos_states; 2635286441Srpaulo} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 2636286441Srpaulo 2637286441Srpaulostruct iwm_mvm_statistics_rx_non_phy { 2638286441Srpaulo uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2639286441Srpaulo uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2640286441Srpaulo uint32_t non_bssid_frames; /* number of frames with BSSID that 2641286441Srpaulo * doesn't belong to the STA BSSID */ 2642286441Srpaulo uint32_t filtered_frames; /* count frames that were dumped in the 2643286441Srpaulo * filtering process */ 2644286441Srpaulo uint32_t non_channel_beacons; /* beacons with our bss id but not on 2645286441Srpaulo * our serving channel */ 2646286441Srpaulo uint32_t channel_beacons; /* beacons with our bss id and in our 2647286441Srpaulo * serving channel */ 2648286441Srpaulo uint32_t num_missed_bcon; /* number of missed beacons */ 2649286441Srpaulo uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2650286441Srpaulo * ADC was in saturation */ 2651286441Srpaulo uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2652286441Srpaulo * for INA */ 2653286441Srpaulo uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2654286441Srpaulo uint32_t interference_data_flag; /* flag for interference data 2655286441Srpaulo * availability. 1 when data is 2656286441Srpaulo * available. */ 2657286441Srpaulo uint32_t channel_load; /* counts RX Enable time in uSec */ 2658286441Srpaulo uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2659286441Srpaulo * and CCK) counter */ 2660286441Srpaulo uint32_t beacon_rssi_a; 2661286441Srpaulo uint32_t beacon_rssi_b; 2662286441Srpaulo uint32_t beacon_rssi_c; 2663286441Srpaulo uint32_t beacon_energy_a; 2664286441Srpaulo uint32_t beacon_energy_b; 2665286441Srpaulo uint32_t beacon_energy_c; 2666286441Srpaulo uint32_t num_bt_kills; 2667286441Srpaulo uint32_t mac_id; 2668286441Srpaulo uint32_t directed_data_mpdu; 2669286441Srpaulo} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2670286441Srpaulo 2671286441Srpaulostruct iwm_mvm_statistics_rx_phy { 2672286441Srpaulo uint32_t ina_cnt; 2673286441Srpaulo uint32_t fina_cnt; 2674286441Srpaulo uint32_t plcp_err; 2675286441Srpaulo uint32_t crc32_err; 2676286441Srpaulo uint32_t overrun_err; 2677286441Srpaulo uint32_t early_overrun_err; 2678286441Srpaulo uint32_t crc32_good; 2679286441Srpaulo uint32_t false_alarm_cnt; 2680286441Srpaulo uint32_t fina_sync_err_cnt; 2681286441Srpaulo uint32_t sfd_timeout; 2682286441Srpaulo uint32_t fina_timeout; 2683286441Srpaulo uint32_t unresponded_rts; 2684286441Srpaulo uint32_t rxe_frame_limit_overrun; 2685286441Srpaulo uint32_t sent_ack_cnt; 2686286441Srpaulo uint32_t sent_cts_cnt; 2687286441Srpaulo uint32_t sent_ba_rsp_cnt; 2688286441Srpaulo uint32_t dsp_self_kill; 2689286441Srpaulo uint32_t mh_format_err; 2690286441Srpaulo uint32_t re_acq_main_rssi_sum; 2691286441Srpaulo uint32_t reserved; 2692286441Srpaulo} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2693286441Srpaulo 2694286441Srpaulostruct iwm_mvm_statistics_rx_ht_phy { 2695286441Srpaulo uint32_t plcp_err; 2696286441Srpaulo uint32_t overrun_err; 2697286441Srpaulo uint32_t early_overrun_err; 2698286441Srpaulo uint32_t crc32_good; 2699286441Srpaulo uint32_t crc32_err; 2700286441Srpaulo uint32_t mh_format_err; 2701286441Srpaulo uint32_t agg_crc32_good; 2702286441Srpaulo uint32_t agg_mpdu_cnt; 2703286441Srpaulo uint32_t agg_cnt; 2704286441Srpaulo uint32_t unsupport_mcs; 2705286441Srpaulo} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 2706286441Srpaulo 2707286441Srpaulo#define IWM_MAX_CHAINS 3 2708286441Srpaulo 2709286441Srpaulostruct iwm_mvm_statistics_tx_non_phy_agg { 2710286441Srpaulo uint32_t ba_timeout; 2711286441Srpaulo uint32_t ba_reschedule_frames; 2712286441Srpaulo uint32_t scd_query_agg_frame_cnt; 2713286441Srpaulo uint32_t scd_query_no_agg; 2714286441Srpaulo uint32_t scd_query_agg; 2715286441Srpaulo uint32_t scd_query_mismatch; 2716286441Srpaulo uint32_t frame_not_ready; 2717286441Srpaulo uint32_t underrun; 2718286441Srpaulo uint32_t bt_prio_kill; 2719286441Srpaulo uint32_t rx_ba_rsp_cnt; 2720286441Srpaulo int8_t txpower[IWM_MAX_CHAINS]; 2721286441Srpaulo int8_t reserved; 2722286441Srpaulo uint32_t reserved2; 2723286441Srpaulo} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 2724286441Srpaulo 2725286441Srpaulostruct iwm_mvm_statistics_tx_channel_width { 2726286441Srpaulo uint32_t ext_cca_narrow_ch20[1]; 2727286441Srpaulo uint32_t ext_cca_narrow_ch40[2]; 2728286441Srpaulo uint32_t ext_cca_narrow_ch80[3]; 2729286441Srpaulo uint32_t ext_cca_narrow_ch160[4]; 2730286441Srpaulo uint32_t last_tx_ch_width_indx; 2731286441Srpaulo uint32_t rx_detected_per_ch_width[4]; 2732286441Srpaulo uint32_t success_per_ch_width[4]; 2733286441Srpaulo uint32_t fail_per_ch_width[4]; 2734286441Srpaulo}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 2735286441Srpaulo 2736286441Srpaulostruct iwm_mvm_statistics_tx { 2737286441Srpaulo uint32_t preamble_cnt; 2738286441Srpaulo uint32_t rx_detected_cnt; 2739286441Srpaulo uint32_t bt_prio_defer_cnt; 2740286441Srpaulo uint32_t bt_prio_kill_cnt; 2741286441Srpaulo uint32_t few_bytes_cnt; 2742286441Srpaulo uint32_t cts_timeout; 2743286441Srpaulo uint32_t ack_timeout; 2744286441Srpaulo uint32_t expected_ack_cnt; 2745286441Srpaulo uint32_t actual_ack_cnt; 2746286441Srpaulo uint32_t dump_msdu_cnt; 2747286441Srpaulo uint32_t burst_abort_next_frame_mismatch_cnt; 2748286441Srpaulo uint32_t burst_abort_missing_next_frame_cnt; 2749286441Srpaulo uint32_t cts_timeout_collision; 2750286441Srpaulo uint32_t ack_or_ba_timeout_collision; 2751286441Srpaulo struct iwm_mvm_statistics_tx_non_phy_agg agg; 2752286441Srpaulo struct iwm_mvm_statistics_tx_channel_width channel_width; 2753286441Srpaulo} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 2754286441Srpaulo 2755286441Srpaulo 2756286441Srpaulostruct iwm_mvm_statistics_bt_activity { 2757286441Srpaulo uint32_t hi_priority_tx_req_cnt; 2758286441Srpaulo uint32_t hi_priority_tx_denied_cnt; 2759286441Srpaulo uint32_t lo_priority_tx_req_cnt; 2760286441Srpaulo uint32_t lo_priority_tx_denied_cnt; 2761286441Srpaulo uint32_t hi_priority_rx_req_cnt; 2762286441Srpaulo uint32_t hi_priority_rx_denied_cnt; 2763286441Srpaulo uint32_t lo_priority_rx_req_cnt; 2764286441Srpaulo uint32_t lo_priority_rx_denied_cnt; 2765286441Srpaulo} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 2766286441Srpaulo 2767286441Srpaulostruct iwm_mvm_statistics_general { 2768286441Srpaulo struct iwm_mvm_statistics_general_common common; 2769286441Srpaulo uint32_t beacon_filtered; 2770286441Srpaulo uint32_t missed_beacons; 2771286441Srpaulo int8_t beacon_filter_average_energy; 2772286441Srpaulo int8_t beacon_filter_reason; 2773286441Srpaulo int8_t beacon_filter_current_energy; 2774286441Srpaulo int8_t beacon_filter_reserved; 2775286441Srpaulo uint32_t beacon_filter_delta_time; 2776286441Srpaulo struct iwm_mvm_statistics_bt_activity bt_activity; 2777286441Srpaulo} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 2778286441Srpaulo 2779286441Srpaulostruct iwm_mvm_statistics_rx { 2780286441Srpaulo struct iwm_mvm_statistics_rx_phy ofdm; 2781286441Srpaulo struct iwm_mvm_statistics_rx_phy cck; 2782286441Srpaulo struct iwm_mvm_statistics_rx_non_phy general; 2783286441Srpaulo struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 2784286441Srpaulo} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 2785286441Srpaulo 2786286441Srpaulo/* 2787286441Srpaulo * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 2788286441Srpaulo * 2789286441Srpaulo * By default, uCode issues this notification after receiving a beacon 2790286441Srpaulo * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 2791286441Srpaulo * IWM_REPLY_STATISTICS_CMD 0x9c, above. 2792286441Srpaulo * 2793286441Srpaulo * Statistics counters continue to increment beacon after beacon, but are 2794286441Srpaulo * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 2795286441Srpaulo * 0x9c with CLEAR_STATS bit set (see above). 2796286441Srpaulo * 2797286441Srpaulo * uCode also issues this notification during scans. uCode clears statistics 2798286441Srpaulo * appropriately so that each notification contains statistics for only the 2799286441Srpaulo * one channel that has just been scanned. 2800286441Srpaulo */ 2801286441Srpaulo 2802286441Srpaulostruct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 2803286441Srpaulo uint32_t flag; 2804286441Srpaulo struct iwm_mvm_statistics_rx rx; 2805286441Srpaulo struct iwm_mvm_statistics_tx tx; 2806286441Srpaulo struct iwm_mvm_statistics_general general; 2807286441Srpaulo} __packed; 2808286441Srpaulo 2809286441Srpaulo/*********************************** 2810286441Srpaulo * Smart Fifo API 2811286441Srpaulo ***********************************/ 2812286441Srpaulo/* Smart Fifo state */ 2813286441Srpauloenum iwm_sf_state { 2814286441Srpaulo IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 2815286441Srpaulo IWM_SF_FULL_ON, 2816286441Srpaulo IWM_SF_UNINIT, 2817286441Srpaulo IWM_SF_INIT_OFF, 2818286441Srpaulo IWM_SF_HW_NUM_STATES 2819286441Srpaulo}; 2820286441Srpaulo 2821286441Srpaulo/* Smart Fifo possible scenario */ 2822286441Srpauloenum iwm_sf_scenario { 2823286441Srpaulo IWM_SF_SCENARIO_SINGLE_UNICAST, 2824286441Srpaulo IWM_SF_SCENARIO_AGG_UNICAST, 2825286441Srpaulo IWM_SF_SCENARIO_MULTICAST, 2826286441Srpaulo IWM_SF_SCENARIO_BA_RESP, 2827286441Srpaulo IWM_SF_SCENARIO_TX_RESP, 2828286441Srpaulo IWM_SF_NUM_SCENARIO 2829286441Srpaulo}; 2830286441Srpaulo 2831286441Srpaulo#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 2832286441Srpaulo#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 2833286441Srpaulo 2834286441Srpaulo/* smart FIFO default values */ 2835286441Srpaulo#define IWM_SF_W_MARK_SISO 4096 2836286441Srpaulo#define IWM_SF_W_MARK_MIMO2 8192 2837286441Srpaulo#define IWM_SF_W_MARK_MIMO3 6144 2838286441Srpaulo#define IWM_SF_W_MARK_LEGACY 4096 2839286441Srpaulo#define IWM_SF_W_MARK_SCAN 4096 2840286441Srpaulo 2841286441Srpaulo/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 2842286441Srpaulo#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 2843286441Srpaulo#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 2844286441Srpaulo#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 2845286441Srpaulo#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 2846286441Srpaulo#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 2847286441Srpaulo#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 2848286441Srpaulo#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 2849286441Srpaulo#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 2850286441Srpaulo#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 2851286441Srpaulo#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 2852286441Srpaulo 2853286441Srpaulo#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 2854286441Srpaulo 2855286441Srpaulo/** 2856286441Srpaulo * Smart Fifo configuration command. 2857286441Srpaulo * @state: smart fifo state, types listed in iwm_sf_sate. 2858298955Spfg * @watermark: Minimum allowed available free space in RXF for transient state. 2859286441Srpaulo * @long_delay_timeouts: aging and idle timer values for each scenario 2860286441Srpaulo * in long delay state. 2861286441Srpaulo * @full_on_timeouts: timer values for each scenario in full on state. 2862286441Srpaulo */ 2863286441Srpaulostruct iwm_sf_cfg_cmd { 2864286441Srpaulo enum iwm_sf_state state; 2865286441Srpaulo uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 2866286441Srpaulo uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 2867286441Srpaulo uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 2868286441Srpaulo} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 2869286441Srpaulo 2870286441Srpaulo/* 2871286441Srpaulo * END mvm/fw-api.h 2872286441Srpaulo */ 2873286441Srpaulo 2874286441Srpaulo/* 2875286441Srpaulo * BEGIN mvm/fw-api-mac.h 2876286441Srpaulo */ 2877286441Srpaulo 2878286441Srpaulo/* 2879286441Srpaulo * The first MAC indices (starting from 0) 2880286441Srpaulo * are available to the driver, AUX follows 2881286441Srpaulo */ 2882286441Srpaulo#define IWM_MAC_INDEX_AUX 4 2883286441Srpaulo#define IWM_MAC_INDEX_MIN_DRIVER 0 2884286441Srpaulo#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2885286441Srpaulo 2886286441Srpauloenum iwm_ac { 2887286441Srpaulo IWM_AC_BK, 2888286441Srpaulo IWM_AC_BE, 2889286441Srpaulo IWM_AC_VI, 2890286441Srpaulo IWM_AC_VO, 2891286441Srpaulo IWM_AC_NUM, 2892286441Srpaulo}; 2893286441Srpaulo 2894286441Srpaulo/** 2895286441Srpaulo * enum iwm_mac_protection_flags - MAC context flags 2896286441Srpaulo * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 2897286441Srpaulo * this will require CCK RTS/CTS2self. 2898286441Srpaulo * RTS/CTS will protect full burst time. 2899286441Srpaulo * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 2900286441Srpaulo * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 2901286441Srpaulo * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 2902286441Srpaulo */ 2903286441Srpauloenum iwm_mac_protection_flags { 2904286441Srpaulo IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 2905286441Srpaulo IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 2906286441Srpaulo IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 2907286441Srpaulo IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 2908286441Srpaulo}; 2909286441Srpaulo 2910286441Srpaulo#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 2911286441Srpaulo#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 2912286441Srpaulo 2913286441Srpaulo/** 2914286441Srpaulo * enum iwm_mac_types - Supported MAC types 2915286441Srpaulo * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 2916286441Srpaulo * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 2917286441Srpaulo * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 2918286441Srpaulo * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 2919286441Srpaulo * @IWM_FW_MAC_TYPE_IBSS: IBSS 2920286441Srpaulo * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 2921286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 2922286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 2923286441Srpaulo * @IWM_FW_MAC_TYPE_GO: P2P GO 2924286441Srpaulo * @IWM_FW_MAC_TYPE_TEST: ? 2925286441Srpaulo * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 2926286441Srpaulo */ 2927286441Srpauloenum iwm_mac_types { 2928286441Srpaulo IWM_FW_MAC_TYPE_FIRST = 1, 2929286441Srpaulo IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 2930286441Srpaulo IWM_FW_MAC_TYPE_LISTENER, 2931286441Srpaulo IWM_FW_MAC_TYPE_PIBSS, 2932286441Srpaulo IWM_FW_MAC_TYPE_IBSS, 2933286441Srpaulo IWM_FW_MAC_TYPE_BSS_STA, 2934286441Srpaulo IWM_FW_MAC_TYPE_P2P_DEVICE, 2935286441Srpaulo IWM_FW_MAC_TYPE_P2P_STA, 2936286441Srpaulo IWM_FW_MAC_TYPE_GO, 2937286441Srpaulo IWM_FW_MAC_TYPE_TEST, 2938286441Srpaulo IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 2939286441Srpaulo}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 2940286441Srpaulo 2941286441Srpaulo/** 2942286441Srpaulo * enum iwm_tsf_id - TSF hw timer ID 2943286441Srpaulo * @IWM_TSF_ID_A: use TSF A 2944286441Srpaulo * @IWM_TSF_ID_B: use TSF B 2945286441Srpaulo * @IWM_TSF_ID_C: use TSF C 2946286441Srpaulo * @IWM_TSF_ID_D: use TSF D 2947286441Srpaulo * @IWM_NUM_TSF_IDS: number of TSF timers available 2948286441Srpaulo */ 2949286441Srpauloenum iwm_tsf_id { 2950286441Srpaulo IWM_TSF_ID_A = 0, 2951286441Srpaulo IWM_TSF_ID_B = 1, 2952286441Srpaulo IWM_TSF_ID_C = 2, 2953286441Srpaulo IWM_TSF_ID_D = 3, 2954286441Srpaulo IWM_NUM_TSF_IDS = 4, 2955286441Srpaulo}; /* IWM_TSF_ID_API_E_VER_1 */ 2956286441Srpaulo 2957286441Srpaulo/** 2958286441Srpaulo * struct iwm_mac_data_ap - configuration data for AP MAC context 2959286441Srpaulo * @beacon_time: beacon transmit time in system time 2960286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 2961286441Srpaulo * @bi: beacon interval in TU 2962286441Srpaulo * @bi_reciprocal: 2^32 / bi 2963286441Srpaulo * @dtim_interval: dtim transmit time in TU 2964286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval 2965286441Srpaulo * @mcast_qid: queue ID for multicast traffic 2966286441Srpaulo * @beacon_template: beacon template ID 2967286441Srpaulo */ 2968286441Srpaulostruct iwm_mac_data_ap { 2969286441Srpaulo uint32_t beacon_time; 2970286441Srpaulo uint64_t beacon_tsf; 2971286441Srpaulo uint32_t bi; 2972286441Srpaulo uint32_t bi_reciprocal; 2973286441Srpaulo uint32_t dtim_interval; 2974286441Srpaulo uint32_t dtim_reciprocal; 2975286441Srpaulo uint32_t mcast_qid; 2976286441Srpaulo uint32_t beacon_template; 2977286441Srpaulo} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 2978286441Srpaulo 2979286441Srpaulo/** 2980286441Srpaulo * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 2981286441Srpaulo * @beacon_time: beacon transmit time in system time 2982286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 2983286441Srpaulo * @bi: beacon interval in TU 2984286441Srpaulo * @bi_reciprocal: 2^32 / bi 2985286441Srpaulo * @beacon_template: beacon template ID 2986286441Srpaulo */ 2987286441Srpaulostruct iwm_mac_data_ibss { 2988286441Srpaulo uint32_t beacon_time; 2989286441Srpaulo uint64_t beacon_tsf; 2990286441Srpaulo uint32_t bi; 2991286441Srpaulo uint32_t bi_reciprocal; 2992286441Srpaulo uint32_t beacon_template; 2993286441Srpaulo} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 2994286441Srpaulo 2995286441Srpaulo/** 2996286441Srpaulo * struct iwm_mac_data_sta - configuration data for station MAC context 2997286441Srpaulo * @is_assoc: 1 for associated state, 0 otherwise 2998286441Srpaulo * @dtim_time: DTIM arrival time in system time 2999286441Srpaulo * @dtim_tsf: DTIM arrival time in TSF 3000286441Srpaulo * @bi: beacon interval in TU, applicable only when associated 3001286441Srpaulo * @bi_reciprocal: 2^32 / bi , applicable only when associated 3002286441Srpaulo * @dtim_interval: DTIM interval in TU, applicable only when associated 3003286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3004286441Srpaulo * @listen_interval: in beacon intervals, applicable only when associated 3005286441Srpaulo * @assoc_id: unique ID assigned by the AP during association 3006286441Srpaulo */ 3007286441Srpaulostruct iwm_mac_data_sta { 3008286441Srpaulo uint32_t is_assoc; 3009286441Srpaulo uint32_t dtim_time; 3010286441Srpaulo uint64_t dtim_tsf; 3011286441Srpaulo uint32_t bi; 3012286441Srpaulo uint32_t bi_reciprocal; 3013286441Srpaulo uint32_t dtim_interval; 3014286441Srpaulo uint32_t dtim_reciprocal; 3015286441Srpaulo uint32_t listen_interval; 3016286441Srpaulo uint32_t assoc_id; 3017286441Srpaulo uint32_t assoc_beacon_arrive_time; 3018286441Srpaulo} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3019286441Srpaulo 3020286441Srpaulo/** 3021286441Srpaulo * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3022286441Srpaulo * @ap: iwm_mac_data_ap struct with most config data 3023286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3024286441Srpaulo * 0 indicates that there is no CT window. 3025286441Srpaulo * @opp_ps_enabled: indicate that opportunistic PS allowed 3026286441Srpaulo */ 3027286441Srpaulostruct iwm_mac_data_go { 3028286441Srpaulo struct iwm_mac_data_ap ap; 3029286441Srpaulo uint32_t ctwin; 3030286441Srpaulo uint32_t opp_ps_enabled; 3031286441Srpaulo} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3032286441Srpaulo 3033286441Srpaulo/** 3034286441Srpaulo * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3035286441Srpaulo * @sta: iwm_mac_data_sta struct with most config data 3036286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3037286441Srpaulo * 0 indicates that there is no CT window. 3038286441Srpaulo */ 3039286441Srpaulostruct iwm_mac_data_p2p_sta { 3040286441Srpaulo struct iwm_mac_data_sta sta; 3041286441Srpaulo uint32_t ctwin; 3042286441Srpaulo} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3043286441Srpaulo 3044286441Srpaulo/** 3045286441Srpaulo * struct iwm_mac_data_pibss - Pseudo IBSS config data 3046286441Srpaulo * @stats_interval: interval in TU between statistics notifications to host. 3047286441Srpaulo */ 3048286441Srpaulostruct iwm_mac_data_pibss { 3049286441Srpaulo uint32_t stats_interval; 3050286441Srpaulo} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3051286441Srpaulo 3052286441Srpaulo/* 3053286441Srpaulo * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3054286441Srpaulo * context. 3055286441Srpaulo * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3056286441Srpaulo * other channels as well. This should be to true only in case that the 3057286441Srpaulo * device is discoverable and there is an active GO. Note that setting this 3058286441Srpaulo * field when not needed, will increase the number of interrupts and have 3059286441Srpaulo * effect on the platform power, as this setting opens the Rx filters on 3060286441Srpaulo * all macs. 3061286441Srpaulo */ 3062286441Srpaulostruct iwm_mac_data_p2p_dev { 3063286441Srpaulo uint32_t is_disc_extended; 3064286441Srpaulo} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3065286441Srpaulo 3066286441Srpaulo/** 3067286441Srpaulo * enum iwm_mac_filter_flags - MAC context filter flags 3068286441Srpaulo * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3069286441Srpaulo * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3070286441Srpaulo * control frames to the host 3071286441Srpaulo * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3072286441Srpaulo * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3073286441Srpaulo * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3074286441Srpaulo * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3075286441Srpaulo * (in station mode when associated) 3076286441Srpaulo * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3077286441Srpaulo * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3078286441Srpaulo * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3079286441Srpaulo */ 3080286441Srpauloenum iwm_mac_filter_flags { 3081286441Srpaulo IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3082286441Srpaulo IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3083286441Srpaulo IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3084286441Srpaulo IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3085286441Srpaulo IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3086286441Srpaulo IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3087286441Srpaulo IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3088286441Srpaulo IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3089286441Srpaulo IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3090286441Srpaulo}; 3091286441Srpaulo 3092286441Srpaulo/** 3093286441Srpaulo * enum iwm_mac_qos_flags - QoS flags 3094286441Srpaulo * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3095286441Srpaulo * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3096286441Srpaulo * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3097286441Srpaulo * 3098286441Srpaulo */ 3099286441Srpauloenum iwm_mac_qos_flags { 3100286441Srpaulo IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3101286441Srpaulo IWM_MAC_QOS_FLG_TGN = (1 << 1), 3102286441Srpaulo IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3103286441Srpaulo}; 3104286441Srpaulo 3105286441Srpaulo/** 3106286441Srpaulo * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3107286441Srpaulo * @cw_min: Contention window, start value in numbers of slots. 3108286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x0f. 3109286441Srpaulo * @cw_max: Contention window, max value in numbers of slots. 3110286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x3f. 3111286441Srpaulo * @aifsn: Number of slots in Arbitration Interframe Space (before 3112286441Srpaulo * performing random backoff timing prior to Tx). Device default 1. 3113286441Srpaulo * @fifos_mask: FIFOs used by this MAC for this AC 3114286441Srpaulo * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3115286441Srpaulo * 3116286441Srpaulo * One instance of this config struct for each of 4 EDCA access categories 3117286441Srpaulo * in struct iwm_qosparam_cmd. 3118286441Srpaulo * 3119286441Srpaulo * Device will automatically increase contention window by (2*CW) + 1 for each 3120286441Srpaulo * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3121286441Srpaulo * value, to cap the CW value. 3122286441Srpaulo */ 3123286441Srpaulostruct iwm_ac_qos { 3124286441Srpaulo uint16_t cw_min; 3125286441Srpaulo uint16_t cw_max; 3126286441Srpaulo uint8_t aifsn; 3127286441Srpaulo uint8_t fifos_mask; 3128286441Srpaulo uint16_t edca_txop; 3129286441Srpaulo} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3130286441Srpaulo 3131286441Srpaulo/** 3132286441Srpaulo * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3133286441Srpaulo * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3134286441Srpaulo * @id_and_color: ID and color of the MAC 3135286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3136286441Srpaulo * @mac_type: one of IWM_FW_MAC_TYPE_* 3137286441Srpaulo * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3138286441Srpaulo * @node_addr: MAC address 3139286441Srpaulo * @bssid_addr: BSSID 3140286441Srpaulo * @cck_rates: basic rates available for CCK 3141286441Srpaulo * @ofdm_rates: basic rates available for OFDM 3142286441Srpaulo * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3143286441Srpaulo * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3144286441Srpaulo * @short_slot: 0x10 for enabling short slots, 0 otherwise 3145286441Srpaulo * @filter_flags: combination of IWM_MAC_FILTER_* 3146286441Srpaulo * @qos_flags: from IWM_MAC_QOS_FLG_* 3147286441Srpaulo * @ac: one iwm_mac_qos configuration for each AC 3148286441Srpaulo * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3149286441Srpaulo */ 3150286441Srpaulostruct iwm_mac_ctx_cmd { 3151286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 3152286441Srpaulo uint32_t id_and_color; 3153286441Srpaulo uint32_t action; 3154286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3155286441Srpaulo uint32_t mac_type; 3156286441Srpaulo uint32_t tsf_id; 3157286441Srpaulo uint8_t node_addr[6]; 3158286441Srpaulo uint16_t reserved_for_node_addr; 3159286441Srpaulo uint8_t bssid_addr[6]; 3160286441Srpaulo uint16_t reserved_for_bssid_addr; 3161286441Srpaulo uint32_t cck_rates; 3162286441Srpaulo uint32_t ofdm_rates; 3163286441Srpaulo uint32_t protection_flags; 3164286441Srpaulo uint32_t cck_short_preamble; 3165286441Srpaulo uint32_t short_slot; 3166286441Srpaulo uint32_t filter_flags; 3167286441Srpaulo /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3168286441Srpaulo uint32_t qos_flags; 3169286441Srpaulo struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3170286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3171286441Srpaulo union { 3172286441Srpaulo struct iwm_mac_data_ap ap; 3173286441Srpaulo struct iwm_mac_data_go go; 3174286441Srpaulo struct iwm_mac_data_sta sta; 3175286441Srpaulo struct iwm_mac_data_p2p_sta p2p_sta; 3176286441Srpaulo struct iwm_mac_data_p2p_dev p2p_dev; 3177286441Srpaulo struct iwm_mac_data_pibss pibss; 3178286441Srpaulo struct iwm_mac_data_ibss ibss; 3179286441Srpaulo }; 3180286441Srpaulo} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3181286441Srpaulo 3182286441Srpaulostatic inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3183286441Srpaulo{ 3184286441Srpaulo if (!v) 3185286441Srpaulo return 0; 3186286441Srpaulo return 0xFFFFFFFF / v; 3187286441Srpaulo} 3188286441Srpaulo 3189286441Srpaulo#define IWM_NONQOS_SEQ_GET 0x1 3190286441Srpaulo#define IWM_NONQOS_SEQ_SET 0x2 3191286441Srpaulostruct iwm_nonqos_seq_query_cmd { 3192286441Srpaulo uint32_t get_set_flag; 3193286441Srpaulo uint32_t mac_id_n_color; 3194286441Srpaulo uint16_t value; 3195286441Srpaulo uint16_t reserved; 3196286441Srpaulo} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3197286441Srpaulo 3198286441Srpaulo/* 3199286441Srpaulo * END mvm/fw-api-mac.h 3200286441Srpaulo */ 3201286441Srpaulo 3202286441Srpaulo/* 3203286441Srpaulo * BEGIN mvm/fw-api-power.h 3204286441Srpaulo */ 3205286441Srpaulo 3206286441Srpaulo/* Power Management Commands, Responses, Notifications */ 3207286441Srpaulo 3208286441Srpaulo/* Radio LP RX Energy Threshold measured in dBm */ 3209286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3210286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3211286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3212286441Srpaulo 3213286441Srpaulo/** 3214286441Srpaulo * enum iwm_scan_flags - masks for power table command flags 3215286441Srpaulo * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3216286441Srpaulo * receiver and transmitter. '0' - does not allow. 3217286441Srpaulo * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3218286441Srpaulo * '1' Driver enables PM (use rest of parameters) 3219286441Srpaulo * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3220286441Srpaulo * '1' PM could sleep over DTIM till listen Interval. 3221286441Srpaulo * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3222286441Srpaulo * access categories are both delivery and trigger enabled. 3223286441Srpaulo * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3224286441Srpaulo * PBW Snoozing enabled 3225286441Srpaulo * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3226286441Srpaulo * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3227286441Srpaulo * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3228286441Srpaulo * detection enablement 3229286441Srpaulo*/ 3230286441Srpauloenum iwm_power_flags { 3231286441Srpaulo IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3232286441Srpaulo IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3233286441Srpaulo IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3234286441Srpaulo IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3235286441Srpaulo IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3236286441Srpaulo IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3237286441Srpaulo IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3238286441Srpaulo IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3239286441Srpaulo}; 3240286441Srpaulo 3241286441Srpaulo#define IWM_POWER_VEC_SIZE 5 3242286441Srpaulo 3243286441Srpaulo/** 3244286441Srpaulo * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3245286441Srpaulo * is used also with a new power API for device wide power settings. 3246286441Srpaulo * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3247286441Srpaulo * 3248286441Srpaulo * @flags: Power table command flags from IWM_POWER_FLAGS_* 3249286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3250286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3251286441Srpaulo * set regardless of power scheme or current power state. 3252286441Srpaulo * FW use this value also when PM is disabled. 3253286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3254286441Srpaulo * PSM transition - legacy PM 3255286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3256286441Srpaulo * PSM transition - legacy PM 3257286441Srpaulo * @sleep_interval: not in use 3258286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3259286441Srpaulo * is set. For example, if it is required to skip over 3260286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3261286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3262286441Srpaulo * Default: 80dbm 3263286441Srpaulo */ 3264286441Srpaulostruct iwm_powertable_cmd { 3265286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3266286441Srpaulo uint16_t flags; 3267286441Srpaulo uint8_t keep_alive_seconds; 3268286441Srpaulo uint8_t debug_flags; 3269286441Srpaulo uint32_t rx_data_timeout; 3270286441Srpaulo uint32_t tx_data_timeout; 3271286441Srpaulo uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3272286441Srpaulo uint32_t skip_dtim_periods; 3273286441Srpaulo uint32_t lprx_rssi_threshold; 3274286441Srpaulo} __packed; 3275286441Srpaulo 3276286441Srpaulo/** 3277286441Srpaulo * enum iwm_device_power_flags - masks for device power command flags 3278286441Srpaulo * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3279286441Srpaulo * receiver and transmitter. '0' - does not allow. This flag should be 3280286441Srpaulo * always set to '1' unless one need to disable actual power down for debug 3281286441Srpaulo * purposes. 3282286441Srpaulo * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3283286441Srpaulo * that power management is disabled. '0' Power management is enabled, one 3284286441Srpaulo * of power schemes is applied. 3285286441Srpaulo*/ 3286286441Srpauloenum iwm_device_power_flags { 3287286441Srpaulo IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3288286441Srpaulo IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3289286441Srpaulo}; 3290286441Srpaulo 3291286441Srpaulo/** 3292286441Srpaulo * struct iwm_device_power_cmd - device wide power command. 3293286441Srpaulo * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3294286441Srpaulo * 3295286441Srpaulo * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3296286441Srpaulo */ 3297286441Srpaulostruct iwm_device_power_cmd { 3298286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3299286441Srpaulo uint16_t flags; 3300286441Srpaulo uint16_t reserved; 3301286441Srpaulo} __packed; 3302286441Srpaulo 3303286441Srpaulo/** 3304286441Srpaulo * struct iwm_mac_power_cmd - New power command containing uAPSD support 3305286441Srpaulo * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3306286441Srpaulo * @id_and_color: MAC contex identifier 3307286441Srpaulo * @flags: Power table command flags from POWER_FLAGS_* 3308286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3309286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3310286441Srpaulo * set regardless of power scheme or current power state. 3311286441Srpaulo * FW use this value also when PM is disabled. 3312286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3313286441Srpaulo * PSM transition - legacy PM 3314286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3315286441Srpaulo * PSM transition - legacy PM 3316286441Srpaulo * @sleep_interval: not in use 3317286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3318286441Srpaulo * is set. For example, if it is required to skip over 3319286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3320286441Srpaulo * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3321286441Srpaulo * PSM transition - uAPSD 3322286441Srpaulo * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3323286441Srpaulo * PSM transition - uAPSD 3324286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3325286441Srpaulo * Default: 80dbm 3326286441Srpaulo * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3327286441Srpaulo * @snooze_interval: Maximum time between attempts to retrieve buffered data 3328286441Srpaulo * from the AP [msec] 3329286441Srpaulo * @snooze_window: A window of time in which PBW snoozing insures that all 3330286441Srpaulo * packets received. It is also the minimum time from last 3331286441Srpaulo * received unicast RX packet, before client stops snoozing 3332286441Srpaulo * for data. [msec] 3333286441Srpaulo * @snooze_step: TBD 3334286441Srpaulo * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3335286441Srpaulo * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3336286441Srpaulo * each corresponding AC. 3337286441Srpaulo * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3338286441Srpaulo * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3339286441Srpaulo * values. 3340286441Srpaulo * @heavy_tx_thld_packets: TX threshold measured in number of packets 3341286441Srpaulo * @heavy_rx_thld_packets: RX threshold measured in number of packets 3342286441Srpaulo * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3343286441Srpaulo * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3344286441Srpaulo * @limited_ps_threshold: 3345286441Srpaulo*/ 3346286441Srpaulostruct iwm_mac_power_cmd { 3347286441Srpaulo /* CONTEXT_DESC_API_T_VER_1 */ 3348286441Srpaulo uint32_t id_and_color; 3349286441Srpaulo 3350286441Srpaulo /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3351286441Srpaulo uint16_t flags; 3352286441Srpaulo uint16_t keep_alive_seconds; 3353286441Srpaulo uint32_t rx_data_timeout; 3354286441Srpaulo uint32_t tx_data_timeout; 3355286441Srpaulo uint32_t rx_data_timeout_uapsd; 3356286441Srpaulo uint32_t tx_data_timeout_uapsd; 3357286441Srpaulo uint8_t lprx_rssi_threshold; 3358286441Srpaulo uint8_t skip_dtim_periods; 3359286441Srpaulo uint16_t snooze_interval; 3360286441Srpaulo uint16_t snooze_window; 3361286441Srpaulo uint8_t snooze_step; 3362286441Srpaulo uint8_t qndp_tid; 3363286441Srpaulo uint8_t uapsd_ac_flags; 3364286441Srpaulo uint8_t uapsd_max_sp; 3365286441Srpaulo uint8_t heavy_tx_thld_packets; 3366286441Srpaulo uint8_t heavy_rx_thld_packets; 3367286441Srpaulo uint8_t heavy_tx_thld_percentage; 3368286441Srpaulo uint8_t heavy_rx_thld_percentage; 3369286441Srpaulo uint8_t limited_ps_threshold; 3370286441Srpaulo uint8_t reserved; 3371286441Srpaulo} __packed; 3372286441Srpaulo 3373286441Srpaulo/* 3374286441Srpaulo * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3375286441Srpaulo * associated AP is identified as improperly implementing uAPSD protocol. 3376286441Srpaulo * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3377286441Srpaulo * @sta_id: index of station in uCode's station table - associated AP ID in 3378286441Srpaulo * this context. 3379286441Srpaulo */ 3380286441Srpaulostruct iwm_uapsd_misbehaving_ap_notif { 3381286441Srpaulo uint32_t sta_id; 3382286441Srpaulo uint8_t mac_id; 3383286441Srpaulo uint8_t reserved[3]; 3384286441Srpaulo} __packed; 3385286441Srpaulo 3386286441Srpaulo/** 3387286441Srpaulo * struct iwm_beacon_filter_cmd 3388286441Srpaulo * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3389286441Srpaulo * @id_and_color: MAC contex identifier 3390286441Srpaulo * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3391286441Srpaulo * to driver if delta in Energy values calculated for this and last 3392286441Srpaulo * passed beacon is greater than this threshold. Zero value means that 3393286441Srpaulo * the Energy change is ignored for beacon filtering, and beacon will 3394286441Srpaulo * not be forced to be sent to driver regardless of this delta. Typical 3395286441Srpaulo * energy delta 5dB. 3396286441Srpaulo * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3397286441Srpaulo * Send beacon to driver if delta in Energy values calculated for this 3398286441Srpaulo * and last passed beacon is greater than this threshold. Zero value 3399286441Srpaulo * means that the Energy change is ignored for beacon filtering while in 3400286441Srpaulo * Roaming state, typical energy delta 1dB. 3401286441Srpaulo * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3402286441Srpaulo * calculated for current beacon is less than the threshold, use 3403286441Srpaulo * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3404286441Srpaulo * Threshold. Typical energy threshold is -72dBm. 3405286441Srpaulo * @bf_temp_threshold: This threshold determines the type of temperature 3406286441Srpaulo * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3407286441Srpaulo * If the current temperature is above this threshold - Fast filter 3408286441Srpaulo * will be used, If the current temperature is below this threshold - 3409286441Srpaulo * Slow filter will be used. 3410286441Srpaulo * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3411286441Srpaulo * calculated for this and the last passed beacon is greater than this 3412286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3413286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3414298955Spfg * regardless of whether its temperature has been changed. 3415286441Srpaulo * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3416286441Srpaulo * calculated for this and the last passed beacon is greater than this 3417286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3418286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3419298955Spfg * regardless of whether its temperature has been changed. 3420286441Srpaulo * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3421286441Srpaulo * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3422286441Srpaulo * for a specific period of time. Units: Beacons. 3423286441Srpaulo * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3424286441Srpaulo * for a longer period of time then this escape-timeout. Units: Beacons. 3425286441Srpaulo * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3426286441Srpaulo */ 3427286441Srpaulostruct iwm_beacon_filter_cmd { 3428286441Srpaulo uint32_t bf_energy_delta; 3429286441Srpaulo uint32_t bf_roaming_energy_delta; 3430286441Srpaulo uint32_t bf_roaming_state; 3431286441Srpaulo uint32_t bf_temp_threshold; 3432286441Srpaulo uint32_t bf_temp_fast_filter; 3433286441Srpaulo uint32_t bf_temp_slow_filter; 3434286441Srpaulo uint32_t bf_enable_beacon_filter; 3435286441Srpaulo uint32_t bf_debug_flag; 3436286441Srpaulo uint32_t bf_escape_timer; 3437286441Srpaulo uint32_t ba_escape_timer; 3438286441Srpaulo uint32_t ba_enable_beacon_abort; 3439286441Srpaulo} __packed; 3440286441Srpaulo 3441286441Srpaulo/* Beacon filtering and beacon abort */ 3442286441Srpaulo#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3443286441Srpaulo#define IWM_BF_ENERGY_DELTA_MAX 255 3444286441Srpaulo#define IWM_BF_ENERGY_DELTA_MIN 0 3445286441Srpaulo 3446286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3447286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3448286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3449286441Srpaulo 3450286441Srpaulo#define IWM_BF_ROAMING_STATE_DEFAULT 72 3451286441Srpaulo#define IWM_BF_ROAMING_STATE_MAX 255 3452286441Srpaulo#define IWM_BF_ROAMING_STATE_MIN 0 3453286441Srpaulo 3454286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3455286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MAX 255 3456286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MIN 0 3457286441Srpaulo 3458286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3459286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3460286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3461286441Srpaulo 3462286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3463286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3464286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3465286441Srpaulo 3466286441Srpaulo#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3467286441Srpaulo 3468286441Srpaulo#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3469286441Srpaulo 3470286441Srpaulo#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3471286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MAX 1024 3472286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MIN 0 3473286441Srpaulo 3474286441Srpaulo#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3475286441Srpaulo#define IWM_BA_ESCAPE_TIMER_D3 9 3476286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MAX 1024 3477286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MIN 0 3478286441Srpaulo 3479286441Srpaulo#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3480286441Srpaulo 3481286441Srpaulo#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3482286441Srpaulo .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3483286441Srpaulo .bf_roaming_energy_delta = \ 3484286441Srpaulo htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3485286441Srpaulo .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3486286441Srpaulo .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3487286441Srpaulo .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3488286441Srpaulo .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3489286441Srpaulo .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3490286441Srpaulo .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3491286441Srpaulo .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3492286441Srpaulo 3493286441Srpaulo/* 3494286441Srpaulo * END mvm/fw-api-power.h 3495286441Srpaulo */ 3496286441Srpaulo 3497286441Srpaulo/* 3498286441Srpaulo * BEGIN mvm/fw-api-rs.h 3499286441Srpaulo */ 3500286441Srpaulo 3501286441Srpaulo/* 3502286441Srpaulo * These serve as indexes into 3503286441Srpaulo * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3504286441Srpaulo * TODO: avoid overlap between legacy and HT rates 3505286441Srpaulo */ 3506286441Srpauloenum { 3507286441Srpaulo IWM_RATE_1M_INDEX = 0, 3508286441Srpaulo IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3509286441Srpaulo IWM_RATE_2M_INDEX, 3510286441Srpaulo IWM_RATE_5M_INDEX, 3511286441Srpaulo IWM_RATE_11M_INDEX, 3512286441Srpaulo IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3513286441Srpaulo IWM_RATE_6M_INDEX, 3514286441Srpaulo IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3515286441Srpaulo IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3516286441Srpaulo IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3517286441Srpaulo IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3518286441Srpaulo IWM_RATE_9M_INDEX, 3519286441Srpaulo IWM_RATE_12M_INDEX, 3520286441Srpaulo IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3521286441Srpaulo IWM_RATE_18M_INDEX, 3522286441Srpaulo IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3523286441Srpaulo IWM_RATE_24M_INDEX, 3524286441Srpaulo IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3525286441Srpaulo IWM_RATE_36M_INDEX, 3526286441Srpaulo IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3527286441Srpaulo IWM_RATE_48M_INDEX, 3528286441Srpaulo IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3529286441Srpaulo IWM_RATE_54M_INDEX, 3530286441Srpaulo IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3531286441Srpaulo IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3532286441Srpaulo IWM_RATE_60M_INDEX, 3533286441Srpaulo IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3534286441Srpaulo IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3535286441Srpaulo IWM_RATE_MCS_8_INDEX, 3536286441Srpaulo IWM_RATE_MCS_9_INDEX, 3537286441Srpaulo IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3538286441Srpaulo IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3539286441Srpaulo IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3540286441Srpaulo}; 3541286441Srpaulo 3542286441Srpaulo#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3543286441Srpaulo 3544286441Srpaulo/* fw API values for legacy bit rates, both OFDM and CCK */ 3545286441Srpauloenum { 3546286441Srpaulo IWM_RATE_6M_PLCP = 13, 3547286441Srpaulo IWM_RATE_9M_PLCP = 15, 3548286441Srpaulo IWM_RATE_12M_PLCP = 5, 3549286441Srpaulo IWM_RATE_18M_PLCP = 7, 3550286441Srpaulo IWM_RATE_24M_PLCP = 9, 3551286441Srpaulo IWM_RATE_36M_PLCP = 11, 3552286441Srpaulo IWM_RATE_48M_PLCP = 1, 3553286441Srpaulo IWM_RATE_54M_PLCP = 3, 3554286441Srpaulo IWM_RATE_1M_PLCP = 10, 3555286441Srpaulo IWM_RATE_2M_PLCP = 20, 3556286441Srpaulo IWM_RATE_5M_PLCP = 55, 3557286441Srpaulo IWM_RATE_11M_PLCP = 110, 3558286441Srpaulo IWM_RATE_INVM_PLCP = -1, 3559286441Srpaulo}; 3560286441Srpaulo 3561286441Srpaulo/* 3562286441Srpaulo * rate_n_flags bit fields 3563286441Srpaulo * 3564286441Srpaulo * The 32-bit value has different layouts in the low 8 bites depending on the 3565286441Srpaulo * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3566286441Srpaulo * for CCK and OFDM). 3567286441Srpaulo * 3568286441Srpaulo * High-throughput (HT) rate format 3569286441Srpaulo * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3570286441Srpaulo * Very High-throughput (VHT) rate format 3571286441Srpaulo * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3572286441Srpaulo * Legacy OFDM rate format for bits 7:0 3573286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3574286441Srpaulo * Legacy CCK rate format for bits 7:0: 3575286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3576286441Srpaulo */ 3577286441Srpaulo 3578286441Srpaulo/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3579286441Srpaulo#define IWM_RATE_MCS_HT_POS 8 3580286441Srpaulo#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3581286441Srpaulo 3582286441Srpaulo/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3583286441Srpaulo#define IWM_RATE_MCS_CCK_POS 9 3584286441Srpaulo#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3585286441Srpaulo 3586286441Srpaulo/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3587286441Srpaulo#define IWM_RATE_MCS_VHT_POS 26 3588286441Srpaulo#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3589286441Srpaulo 3590286441Srpaulo 3591286441Srpaulo/* 3592286441Srpaulo * High-throughput (HT) rate format for bits 7:0 3593286441Srpaulo * 3594286441Srpaulo * 2-0: MCS rate base 3595286441Srpaulo * 0) 6 Mbps 3596286441Srpaulo * 1) 12 Mbps 3597286441Srpaulo * 2) 18 Mbps 3598286441Srpaulo * 3) 24 Mbps 3599286441Srpaulo * 4) 36 Mbps 3600286441Srpaulo * 5) 48 Mbps 3601286441Srpaulo * 6) 54 Mbps 3602286441Srpaulo * 7) 60 Mbps 3603286441Srpaulo * 4-3: 0) Single stream (SISO) 3604286441Srpaulo * 1) Dual stream (MIMO) 3605286441Srpaulo * 2) Triple stream (MIMO) 3606286441Srpaulo * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3607286441Srpaulo * (bits 7-6 are zero) 3608286441Srpaulo * 3609286441Srpaulo * Together the low 5 bits work out to the MCS index because we don't 3610286441Srpaulo * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3611286441Srpaulo * streams and 16-23 have three streams. We could also support MCS 32 3612286441Srpaulo * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3613286441Srpaulo */ 3614286441Srpaulo#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3615286441Srpaulo#define IWM_RATE_HT_MCS_NSS_POS 3 3616286441Srpaulo#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3617286441Srpaulo 3618286441Srpaulo/* Bit 10: (1) Use Green Field preamble */ 3619286441Srpaulo#define IWM_RATE_HT_MCS_GF_POS 10 3620286441Srpaulo#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3621286441Srpaulo 3622286441Srpaulo#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3623286441Srpaulo 3624286441Srpaulo/* 3625286441Srpaulo * Very High-throughput (VHT) rate format for bits 7:0 3626286441Srpaulo * 3627286441Srpaulo * 3-0: VHT MCS (0-9) 3628286441Srpaulo * 5-4: number of streams - 1: 3629286441Srpaulo * 0) Single stream (SISO) 3630286441Srpaulo * 1) Dual stream (MIMO) 3631286441Srpaulo * 2) Triple stream (MIMO) 3632286441Srpaulo */ 3633286441Srpaulo 3634286441Srpaulo/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3635286441Srpaulo#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3636286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_POS 4 3637286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3638286441Srpaulo 3639286441Srpaulo/* 3640286441Srpaulo * Legacy OFDM rate format for bits 7:0 3641286441Srpaulo * 3642286441Srpaulo * 3-0: 0xD) 6 Mbps 3643286441Srpaulo * 0xF) 9 Mbps 3644286441Srpaulo * 0x5) 12 Mbps 3645286441Srpaulo * 0x7) 18 Mbps 3646286441Srpaulo * 0x9) 24 Mbps 3647286441Srpaulo * 0xB) 36 Mbps 3648286441Srpaulo * 0x1) 48 Mbps 3649286441Srpaulo * 0x3) 54 Mbps 3650286441Srpaulo * (bits 7-4 are 0) 3651286441Srpaulo * 3652286441Srpaulo * Legacy CCK rate format for bits 7:0: 3653286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3654286441Srpaulo * 3655286441Srpaulo * 6-0: 10) 1 Mbps 3656286441Srpaulo * 20) 2 Mbps 3657286441Srpaulo * 55) 5.5 Mbps 3658286441Srpaulo * 110) 11 Mbps 3659286441Srpaulo * (bit 7 is 0) 3660286441Srpaulo */ 3661286441Srpaulo#define IWM_RATE_LEGACY_RATE_MSK 0xff 3662286441Srpaulo 3663286441Srpaulo 3664286441Srpaulo/* 3665286441Srpaulo * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 3666286441Srpaulo * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 3667286441Srpaulo */ 3668286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 3669286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3670286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3671286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3672286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3673286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3674286441Srpaulo 3675286441Srpaulo/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 3676286441Srpaulo#define IWM_RATE_MCS_SGI_POS 13 3677286441Srpaulo#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 3678286441Srpaulo 3679286441Srpaulo/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 3680286441Srpaulo#define IWM_RATE_MCS_ANT_POS 14 3681286441Srpaulo#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 3682286441Srpaulo#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 3683286441Srpaulo#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 3684286441Srpaulo#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 3685286441Srpaulo IWM_RATE_MCS_ANT_B_MSK) 3686286441Srpaulo#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 3687286441Srpaulo IWM_RATE_MCS_ANT_C_MSK) 3688286441Srpaulo#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 3689286441Srpaulo#define IWM_RATE_MCS_ANT_NUM 3 3690286441Srpaulo 3691286441Srpaulo/* Bit 17-18: (0) SS, (1) SS*2 */ 3692286441Srpaulo#define IWM_RATE_MCS_STBC_POS 17 3693286441Srpaulo#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 3694286441Srpaulo 3695286441Srpaulo/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 3696286441Srpaulo#define IWM_RATE_MCS_BF_POS 19 3697286441Srpaulo#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 3698286441Srpaulo 3699286441Srpaulo/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 3700286441Srpaulo#define IWM_RATE_MCS_ZLF_POS 20 3701286441Srpaulo#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 3702286441Srpaulo 3703286441Srpaulo/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 3704286441Srpaulo#define IWM_RATE_MCS_DUP_POS 24 3705286441Srpaulo#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 3706286441Srpaulo 3707286441Srpaulo/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 3708286441Srpaulo#define IWM_RATE_MCS_LDPC_POS 27 3709286441Srpaulo#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 3710286441Srpaulo 3711286441Srpaulo 3712286441Srpaulo/* Link Quality definitions */ 3713286441Srpaulo 3714286441Srpaulo/* # entries in rate scale table to support Tx retries */ 3715286441Srpaulo#define IWM_LQ_MAX_RETRY_NUM 16 3716286441Srpaulo 3717286441Srpaulo/* Link quality command flags bit fields */ 3718286441Srpaulo 3719286441Srpaulo/* Bit 0: (0) Don't use RTS (1) Use RTS */ 3720286441Srpaulo#define IWM_LQ_FLAG_USE_RTS_POS 0 3721286441Srpaulo#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 3722286441Srpaulo 3723286441Srpaulo/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 3724286441Srpaulo#define IWM_LQ_FLAG_COLOR_POS 1 3725286441Srpaulo#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 3726286441Srpaulo 3727286441Srpaulo/* Bit 4-5: Tx RTS BW Signalling 3728286441Srpaulo * (0) No RTS BW signalling 3729286441Srpaulo * (1) Static BW signalling 3730286441Srpaulo * (2) Dynamic BW signalling 3731286441Srpaulo */ 3732286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 3733286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 3734286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 3735286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 3736286441Srpaulo 3737286441Srpaulo/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 3738286441Srpaulo * Dyanmic BW selection allows Tx with narrower BW then requested in rates 3739286441Srpaulo */ 3740286441Srpaulo#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 3741286441Srpaulo#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 3742286441Srpaulo 3743286441Srpaulo/** 3744286441Srpaulo * struct iwm_lq_cmd - link quality command 3745286441Srpaulo * @sta_id: station to update 3746286441Srpaulo * @control: not used 3747286441Srpaulo * @flags: combination of IWM_LQ_FLAG_* 3748286441Srpaulo * @mimo_delim: the first SISO index in rs_table, which separates MIMO 3749286441Srpaulo * and SISO rates 3750286441Srpaulo * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 3751286441Srpaulo * Should be ANT_[ABC] 3752286441Srpaulo * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 3753286441Srpaulo * @initial_rate_index: first index from rs_table per AC category 3754286441Srpaulo * @agg_time_limit: aggregation max time threshold in usec/100, meaning 3755286441Srpaulo * value of 100 is one usec. Range is 100 to 8000 3756286441Srpaulo * @agg_disable_start_th: try-count threshold for starting aggregation. 3757286441Srpaulo * If a frame has higher try-count, it should not be selected for 3758286441Srpaulo * starting an aggregation sequence. 3759286441Srpaulo * @agg_frame_cnt_limit: max frame count in an aggregation. 3760286441Srpaulo * 0: no limit 3761286441Srpaulo * 1: no aggregation (one frame per aggregation) 3762286441Srpaulo * 2 - 0x3f: maximal number of frames (up to 3f == 63) 3763286441Srpaulo * @rs_table: array of rates for each TX try, each is rate_n_flags, 3764286441Srpaulo * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 3765286441Srpaulo * @bf_params: beam forming params, currently not used 3766286441Srpaulo */ 3767286441Srpaulostruct iwm_lq_cmd { 3768286441Srpaulo uint8_t sta_id; 3769286441Srpaulo uint8_t reserved1; 3770286441Srpaulo uint16_t control; 3771286441Srpaulo /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 3772286441Srpaulo uint8_t flags; 3773286441Srpaulo uint8_t mimo_delim; 3774286441Srpaulo uint8_t single_stream_ant_msk; 3775286441Srpaulo uint8_t dual_stream_ant_msk; 3776286441Srpaulo uint8_t initial_rate_index[IWM_AC_NUM]; 3777286441Srpaulo /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 3778286441Srpaulo uint16_t agg_time_limit; 3779286441Srpaulo uint8_t agg_disable_start_th; 3780286441Srpaulo uint8_t agg_frame_cnt_limit; 3781286441Srpaulo uint32_t reserved2; 3782286441Srpaulo uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 3783286441Srpaulo uint32_t bf_params; 3784286441Srpaulo}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 3785286441Srpaulo 3786286441Srpaulo/* 3787286441Srpaulo * END mvm/fw-api-rs.h 3788286441Srpaulo */ 3789286441Srpaulo 3790286441Srpaulo/* 3791286441Srpaulo * BEGIN mvm/fw-api-tx.h 3792286441Srpaulo */ 3793286441Srpaulo 3794286441Srpaulo/** 3795286441Srpaulo * enum iwm_tx_flags - bitmasks for tx_flags in TX command 3796286441Srpaulo * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 3797286441Srpaulo * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 3798286441Srpaulo * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 3799286441Srpaulo * Otherwise, use rate_n_flags from the TX command 3800286441Srpaulo * @IWM_TX_CMD_FLG_BA: this frame is a block ack 3801286441Srpaulo * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 3802286441Srpaulo * Must set IWM_TX_CMD_FLG_ACK with this flag. 3803286441Srpaulo * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 3804286441Srpaulo * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 3805286441Srpaulo * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 3806286441Srpaulo * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 3807286441Srpaulo * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 3808286441Srpaulo * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 3809286441Srpaulo * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 3810286441Srpaulo * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 3811286441Srpaulo * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 3812286441Srpaulo * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 3813286441Srpaulo * Should be set for beacons and probe responses 3814286441Srpaulo * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 3815286441Srpaulo * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 3816286441Srpaulo * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 3817286441Srpaulo * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 3818286441Srpaulo * Should be set for 26/30 length MAC headers 3819286441Srpaulo * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 3820286441Srpaulo * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 3821286441Srpaulo * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 3822286441Srpaulo * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 3823286441Srpaulo * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 3824286441Srpaulo * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 3825286441Srpaulo * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 3826286441Srpaulo * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 3827286441Srpaulo */ 3828286441Srpauloenum iwm_tx_flags { 3829286441Srpaulo IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 3830286441Srpaulo IWM_TX_CMD_FLG_ACK = (1 << 3), 3831286441Srpaulo IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 3832286441Srpaulo IWM_TX_CMD_FLG_BA = (1 << 5), 3833286441Srpaulo IWM_TX_CMD_FLG_BAR = (1 << 6), 3834286441Srpaulo IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 3835286441Srpaulo IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 3836286441Srpaulo IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 3837286441Srpaulo IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 3838286441Srpaulo IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 3839286441Srpaulo IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 3840286441Srpaulo IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 3841286441Srpaulo IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 3842286441Srpaulo IWM_TX_CMD_FLG_TSF = (1 << 16), 3843286441Srpaulo IWM_TX_CMD_FLG_CALIB = (1 << 17), 3844286441Srpaulo IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 3845286441Srpaulo IWM_TX_CMD_FLG_AGG_START = (1 << 19), 3846286441Srpaulo IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 3847286441Srpaulo IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 3848286441Srpaulo IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 3849286441Srpaulo IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 3850286441Srpaulo IWM_TX_CMD_FLG_DUR = (1 << 25), 3851286441Srpaulo IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 3852286441Srpaulo IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 3853286441Srpaulo IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 3854286441Srpaulo IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 3855286441Srpaulo}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 3856286441Srpaulo 3857286441Srpaulo/* 3858286441Srpaulo * TX command security control 3859286441Srpaulo */ 3860286441Srpaulo#define IWM_TX_CMD_SEC_WEP 0x01 3861286441Srpaulo#define IWM_TX_CMD_SEC_CCM 0x02 3862286441Srpaulo#define IWM_TX_CMD_SEC_TKIP 0x03 3863286441Srpaulo#define IWM_TX_CMD_SEC_EXT 0x04 3864286441Srpaulo#define IWM_TX_CMD_SEC_MSK 0x07 3865286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 3866286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 3867286441Srpaulo#define IWM_TX_CMD_SEC_KEY128 0x08 3868286441Srpaulo 3869286441Srpaulo/* TODO: how does these values are OK with only 16 bit variable??? */ 3870286441Srpaulo/* 3871286441Srpaulo * TX command next frame info 3872286441Srpaulo * 3873286441Srpaulo * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 3874286441Srpaulo * bit 3 - immediate ACK required 3875286441Srpaulo * bit 4 - rate is taken from STA table 3876286441Srpaulo * bit 5 - frame belongs to BA stream 3877286441Srpaulo * bit 6 - immediate BA response expected 3878286441Srpaulo * bit 7 - unused 3879286441Srpaulo * bits 8:15 - Station ID 3880286441Srpaulo * bits 16:31 - rate 3881286441Srpaulo */ 3882286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 3883286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 3884286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 3885286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 3886286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 3887286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 3888286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 3889286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 3890286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 3891286441Srpaulo 3892286441Srpaulo/* 3893286441Srpaulo * TX command Frame life time in us - to be written in pm_frame_timeout 3894286441Srpaulo */ 3895286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 3896286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 3897286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 3898286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 3899286441Srpaulo 3900286441Srpaulo/* 3901286441Srpaulo * TID for non QoS frames - to be written in tid_tspec 3902286441Srpaulo */ 3903286441Srpaulo#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 3904286441Srpaulo 3905286441Srpaulo/* 3906286441Srpaulo * Limits on the retransmissions - to be written in {data,rts}_retry_limit 3907286441Srpaulo */ 3908286441Srpaulo#define IWM_DEFAULT_TX_RETRY 15 3909286441Srpaulo#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 3910286441Srpaulo#define IWM_RTS_DFAULT_RETRY_LIMIT 60 3911286441Srpaulo#define IWM_BAR_DFAULT_RETRY_LIMIT 60 3912286441Srpaulo#define IWM_LOW_RETRY_LIMIT 7 3913286441Srpaulo 3914286441Srpaulo/* TODO: complete documentation for try_cnt and btkill_cnt */ 3915286441Srpaulo/** 3916286441Srpaulo * struct iwm_tx_cmd - TX command struct to FW 3917286441Srpaulo * ( IWM_TX_CMD = 0x1c ) 3918286441Srpaulo * @len: in bytes of the payload, see below for details 3919286441Srpaulo * @next_frame_len: same as len, but for next frame (0 if not applicable) 3920286441Srpaulo * Used for fragmentation and bursting, but not in 11n aggregation. 3921286441Srpaulo * @tx_flags: combination of IWM_TX_CMD_FLG_* 3922286441Srpaulo * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 3923286441Srpaulo * cleared. Combination of IWM_RATE_MCS_* 3924286441Srpaulo * @sta_id: index of destination station in FW station table 3925286441Srpaulo * @sec_ctl: security control, IWM_TX_CMD_SEC_* 3926300050Seadler * @initial_rate_index: index into the rate table for initial TX attempt. 3927286441Srpaulo * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 3928286441Srpaulo * @key: security key 3929286441Srpaulo * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 3930286441Srpaulo * @life_time: frame life time (usecs??) 3931286441Srpaulo * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 3932286441Srpaulo * btkill_cnd + reserved), first 32 bits. "0" disables usage. 3933286441Srpaulo * @dram_msb_ptr: upper bits of the scratch physical address 3934286441Srpaulo * @rts_retry_limit: max attempts for RTS 3935286441Srpaulo * @data_retry_limit: max attempts to send the data packet 3936286441Srpaulo * @tid_spec: TID/tspec 3937286441Srpaulo * @pm_frame_timeout: PM TX frame timeout 3938286441Srpaulo * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 3939286441Srpaulo * specified by HCCA protocol 3940286441Srpaulo * 3941286441Srpaulo * The byte count (both len and next_frame_len) includes MAC header 3942286441Srpaulo * (24/26/30/32 bytes) 3943286441Srpaulo * + 2 bytes pad if 26/30 header size 3944286441Srpaulo * + 8 byte IV for CCM or TKIP (not used for WEP) 3945286441Srpaulo * + Data payload 3946286441Srpaulo * + 8-byte MIC (not used for CCM/WEP) 3947286441Srpaulo * It does not include post-MAC padding, i.e., 3948286441Srpaulo * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 3949286441Srpaulo * Range of len: 14-2342 bytes. 3950286441Srpaulo * 3951286441Srpaulo * After the struct fields the MAC header is placed, plus any padding, 3952286441Srpaulo * and then the actial payload. 3953286441Srpaulo */ 3954286441Srpaulostruct iwm_tx_cmd { 3955286441Srpaulo uint16_t len; 3956286441Srpaulo uint16_t next_frame_len; 3957286441Srpaulo uint32_t tx_flags; 3958286441Srpaulo struct { 3959286441Srpaulo uint8_t try_cnt; 3960286441Srpaulo uint8_t btkill_cnt; 3961286441Srpaulo uint16_t reserved; 3962286441Srpaulo } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 3963286441Srpaulo uint32_t rate_n_flags; 3964286441Srpaulo uint8_t sta_id; 3965286441Srpaulo uint8_t sec_ctl; 3966286441Srpaulo uint8_t initial_rate_index; 3967286441Srpaulo uint8_t reserved2; 3968286441Srpaulo uint8_t key[16]; 3969286441Srpaulo uint16_t next_frame_flags; 3970286441Srpaulo uint16_t reserved3; 3971286441Srpaulo uint32_t life_time; 3972286441Srpaulo uint32_t dram_lsb_ptr; 3973286441Srpaulo uint8_t dram_msb_ptr; 3974286441Srpaulo uint8_t rts_retry_limit; 3975286441Srpaulo uint8_t data_retry_limit; 3976286441Srpaulo uint8_t tid_tspec; 3977286441Srpaulo uint16_t pm_frame_timeout; 3978286441Srpaulo uint16_t driver_txop; 3979286441Srpaulo uint8_t payload[0]; 3980286441Srpaulo struct ieee80211_frame hdr[0]; 3981286441Srpaulo} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 3982286441Srpaulo 3983286441Srpaulo/* 3984286441Srpaulo * TX response related data 3985286441Srpaulo */ 3986286441Srpaulo 3987286441Srpaulo/* 3988286441Srpaulo * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 3989286441Srpaulo * @IWM_TX_STATUS_SUCCESS: 3990286441Srpaulo * @IWM_TX_STATUS_DIRECT_DONE: 3991286441Srpaulo * @IWM_TX_STATUS_POSTPONE_DELAY: 3992286441Srpaulo * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 3993286441Srpaulo * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 3994286441Srpaulo * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 3995286441Srpaulo * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 3996286441Srpaulo * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 3997286441Srpaulo * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 3998286441Srpaulo * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 3999286441Srpaulo * @IWM_TX_STATUS_FAIL_UNDERRUN: 4000286441Srpaulo * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4001286441Srpaulo * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4002286441Srpaulo * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4003286441Srpaulo * @IWM_TX_STATUS_FAIL_DEST_PS: 4004286441Srpaulo * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4005286441Srpaulo * @IWM_TX_STATUS_FAIL_BT_RETRY: 4006286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_INVALID: 4007286441Srpaulo * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4008286441Srpaulo * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4009286441Srpaulo * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4010286441Srpaulo * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4011286441Srpaulo * @IWM_TX_STATUS_FAIL_FW_DROP: 4012286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4013286441Srpaulo * STA table 4014286441Srpaulo * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4015286441Srpaulo * @IWM_TX_MODE_MSK: 4016286441Srpaulo * @IWM_TX_MODE_NO_BURST: 4017286441Srpaulo * @IWM_TX_MODE_IN_BURST_SEQ: 4018286441Srpaulo * @IWM_TX_MODE_FIRST_IN_BURST: 4019286441Srpaulo * @IWM_TX_QUEUE_NUM_MSK: 4020286441Srpaulo * 4021286441Srpaulo * Valid only if frame_count =1 4022286441Srpaulo * TODO: complete documentation 4023286441Srpaulo */ 4024286441Srpauloenum iwm_tx_status { 4025286441Srpaulo IWM_TX_STATUS_MSK = 0x000000ff, 4026286441Srpaulo IWM_TX_STATUS_SUCCESS = 0x01, 4027286441Srpaulo IWM_TX_STATUS_DIRECT_DONE = 0x02, 4028286441Srpaulo /* postpone TX */ 4029286441Srpaulo IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4030286441Srpaulo IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4031286441Srpaulo IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4032286441Srpaulo IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4033286441Srpaulo IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4034286441Srpaulo /* abort TX */ 4035286441Srpaulo IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4036286441Srpaulo IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4037286441Srpaulo IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4038286441Srpaulo IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4039286441Srpaulo IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4040286441Srpaulo IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4041286441Srpaulo IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4042286441Srpaulo IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4043286441Srpaulo IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4044286441Srpaulo IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4045286441Srpaulo IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4046286441Srpaulo IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4047286441Srpaulo IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4048286441Srpaulo IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4049286441Srpaulo IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4050286441Srpaulo IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4051286441Srpaulo IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4052286441Srpaulo IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4053286441Srpaulo IWM_TX_MODE_MSK = 0x00000f00, 4054286441Srpaulo IWM_TX_MODE_NO_BURST = 0x00000000, 4055286441Srpaulo IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4056286441Srpaulo IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4057286441Srpaulo IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4058286441Srpaulo IWM_TX_NARROW_BW_MSK = 0x00060000, 4059286441Srpaulo IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4060286441Srpaulo IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4061286441Srpaulo IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4062286441Srpaulo}; 4063286441Srpaulo 4064286441Srpaulo/* 4065286441Srpaulo * enum iwm_tx_agg_status - TX aggregation status 4066286441Srpaulo * @IWM_AGG_TX_STATE_STATUS_MSK: 4067286441Srpaulo * @IWM_AGG_TX_STATE_TRANSMITTED: 4068286441Srpaulo * @IWM_AGG_TX_STATE_UNDERRUN: 4069286441Srpaulo * @IWM_AGG_TX_STATE_BT_PRIO: 4070286441Srpaulo * @IWM_AGG_TX_STATE_FEW_BYTES: 4071286441Srpaulo * @IWM_AGG_TX_STATE_ABORT: 4072286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4073286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4074286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4075286441Srpaulo * @IWM_AGG_TX_STATE_SCD_QUERY: 4076286441Srpaulo * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4077286441Srpaulo * @IWM_AGG_TX_STATE_RESPONSE: 4078286441Srpaulo * @IWM_AGG_TX_STATE_DUMP_TX: 4079286441Srpaulo * @IWM_AGG_TX_STATE_DELAY_TX: 4080286441Srpaulo * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4081286441Srpaulo * occur if tx failed for this frame when it was a member of a previous 4082286441Srpaulo * aggregation block). If rate scaling is used, retry count indicates the 4083286441Srpaulo * rate table entry used for all frames in the new agg. 4084286441Srpaulo *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4085286441Srpaulo * this frame 4086286441Srpaulo * 4087286441Srpaulo * TODO: complete documentation 4088286441Srpaulo */ 4089286441Srpauloenum iwm_tx_agg_status { 4090286441Srpaulo IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4091286441Srpaulo IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4092286441Srpaulo IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4093286441Srpaulo IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4094286441Srpaulo IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4095286441Srpaulo IWM_AGG_TX_STATE_ABORT = 0x008, 4096286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4097286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4098286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4099286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4100286441Srpaulo IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4101286441Srpaulo IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4102286441Srpaulo IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4103286441Srpaulo IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4104286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4105286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4106286441Srpaulo}; 4107286441Srpaulo 4108286441Srpaulo#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4109286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4110286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4111286441Srpaulo 4112286441Srpaulo/* 4113286441Srpaulo * The mask below describes a status where we are absolutely sure that the MPDU 4114286441Srpaulo * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4115286441Srpaulo * written the bytes to the TXE, but we know nothing about what the DSP did. 4116286441Srpaulo */ 4117286441Srpaulo#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4118286441Srpaulo IWM_AGG_TX_STATE_ABORT | \ 4119286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY) 4120286441Srpaulo 4121286441Srpaulo/* 4122286441Srpaulo * IWM_REPLY_TX = 0x1c (response) 4123286441Srpaulo * 4124286441Srpaulo * This response may be in one of two slightly different formats, indicated 4125286441Srpaulo * by the frame_count field: 4126286441Srpaulo * 4127286441Srpaulo * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4128286441Srpaulo * frame. Multiple attempts, at various bit rates, may have been made for 4129286441Srpaulo * this frame. 4130286441Srpaulo * 4131286441Srpaulo * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4132286441Srpaulo * frames that used block-acknowledge. All frames were transmitted at 4133286441Srpaulo * same rate. Rate scaling may have been used if first frame in this new 4134286441Srpaulo * agg block failed in previous agg block(s). 4135286441Srpaulo * 4136286441Srpaulo * Note that, for aggregation, ACK (block-ack) status is not delivered 4137286441Srpaulo * here; block-ack has not been received by the time the device records 4138286441Srpaulo * this status. 4139286441Srpaulo * This status relates to reasons the tx might have been blocked or aborted 4140286441Srpaulo * within the device, rather than whether it was received successfully by 4141286441Srpaulo * the destination station. 4142286441Srpaulo */ 4143286441Srpaulo 4144286441Srpaulo/** 4145286441Srpaulo * struct iwm_agg_tx_status - per packet TX aggregation status 4146286441Srpaulo * @status: enum iwm_tx_agg_status 4147286441Srpaulo * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4148286441Srpaulo */ 4149286441Srpaulostruct iwm_agg_tx_status { 4150286441Srpaulo uint16_t status; 4151286441Srpaulo uint16_t sequence; 4152286441Srpaulo} __packed; 4153286441Srpaulo 4154286441Srpaulo/* 4155286441Srpaulo * definitions for initial rate index field 4156286441Srpaulo * bits [3:0] initial rate index 4157286441Srpaulo * bits [6:4] rate table color, used for the initial rate 4158286441Srpaulo * bit-7 invalid rate indication 4159286441Srpaulo */ 4160286441Srpaulo#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4161286441Srpaulo#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4162286441Srpaulo#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4163286441Srpaulo 4164286441Srpaulo#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4165286441Srpaulo#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4166286441Srpaulo 4167286441Srpaulo/** 4168286441Srpaulo * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4169286441Srpaulo * ( IWM_REPLY_TX = 0x1c ) 4170286441Srpaulo * @frame_count: 1 no aggregation, >1 aggregation 4171286441Srpaulo * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4172286441Srpaulo * @failure_rts: num of failures due to unsuccessful RTS 4173286441Srpaulo * @failure_frame: num failures due to no ACK (unused for agg) 4174286441Srpaulo * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4175286441Srpaulo * Tx of all the batch. IWM_RATE_MCS_* 4176286441Srpaulo * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4177286441Srpaulo * for agg: RTS + CTS + aggregation tx time + block-ack time. 4178286441Srpaulo * in usec. 4179286441Srpaulo * @pa_status: tx power info 4180286441Srpaulo * @pa_integ_res_a: tx power info 4181286441Srpaulo * @pa_integ_res_b: tx power info 4182286441Srpaulo * @pa_integ_res_c: tx power info 4183286441Srpaulo * @measurement_req_id: tx power info 4184286441Srpaulo * @tfd_info: TFD information set by the FH 4185286441Srpaulo * @seq_ctl: sequence control from the Tx cmd 4186286441Srpaulo * @byte_cnt: byte count from the Tx cmd 4187286441Srpaulo * @tlc_info: TLC rate info 4188286441Srpaulo * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4189286441Srpaulo * @frame_ctrl: frame control 4190286441Srpaulo * @status: for non-agg: frame status IWM_TX_STATUS_* 4191286441Srpaulo * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4192286441Srpaulo * follow this one, up to frame_count. 4193286441Srpaulo * 4194286441Srpaulo * After the array of statuses comes the SSN of the SCD. Look at 4195286441Srpaulo * %iwm_mvm_get_scd_ssn for more details. 4196286441Srpaulo */ 4197286441Srpaulostruct iwm_mvm_tx_resp { 4198286441Srpaulo uint8_t frame_count; 4199286441Srpaulo uint8_t bt_kill_count; 4200286441Srpaulo uint8_t failure_rts; 4201286441Srpaulo uint8_t failure_frame; 4202286441Srpaulo uint32_t initial_rate; 4203286441Srpaulo uint16_t wireless_media_time; 4204286441Srpaulo 4205286441Srpaulo uint8_t pa_status; 4206286441Srpaulo uint8_t pa_integ_res_a[3]; 4207286441Srpaulo uint8_t pa_integ_res_b[3]; 4208286441Srpaulo uint8_t pa_integ_res_c[3]; 4209286441Srpaulo uint16_t measurement_req_id; 4210286441Srpaulo uint16_t reserved; 4211286441Srpaulo 4212286441Srpaulo uint32_t tfd_info; 4213286441Srpaulo uint16_t seq_ctl; 4214286441Srpaulo uint16_t byte_cnt; 4215286441Srpaulo uint8_t tlc_info; 4216286441Srpaulo uint8_t ra_tid; 4217286441Srpaulo uint16_t frame_ctrl; 4218286441Srpaulo 4219286441Srpaulo struct iwm_agg_tx_status status; 4220286441Srpaulo} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4221286441Srpaulo 4222286441Srpaulo/** 4223286441Srpaulo * struct iwm_mvm_ba_notif - notifies about reception of BA 4224286441Srpaulo * ( IWM_BA_NOTIF = 0xc5 ) 4225286441Srpaulo * @sta_addr_lo32: lower 32 bits of the MAC address 4226286441Srpaulo * @sta_addr_hi16: upper 16 bits of the MAC address 4227286441Srpaulo * @sta_id: Index of recipient (BA-sending) station in fw's station table 4228286441Srpaulo * @tid: tid of the session 4229286441Srpaulo * @seq_ctl: 4230286441Srpaulo * @bitmap: the bitmap of the BA notification as seen in the air 4231286441Srpaulo * @scd_flow: the tx queue this BA relates to 4232286441Srpaulo * @scd_ssn: the index of the last contiguously sent packet 4233286441Srpaulo * @txed: number of Txed frames in this batch 4234286441Srpaulo * @txed_2_done: number of Acked frames in this batch 4235286441Srpaulo */ 4236286441Srpaulostruct iwm_mvm_ba_notif { 4237286441Srpaulo uint32_t sta_addr_lo32; 4238286441Srpaulo uint16_t sta_addr_hi16; 4239286441Srpaulo uint16_t reserved; 4240286441Srpaulo 4241286441Srpaulo uint8_t sta_id; 4242286441Srpaulo uint8_t tid; 4243286441Srpaulo uint16_t seq_ctl; 4244286441Srpaulo uint64_t bitmap; 4245286441Srpaulo uint16_t scd_flow; 4246286441Srpaulo uint16_t scd_ssn; 4247286441Srpaulo uint8_t txed; 4248286441Srpaulo uint8_t txed_2_done; 4249286441Srpaulo uint16_t reserved1; 4250286441Srpaulo} __packed; 4251286441Srpaulo 4252286441Srpaulo/* 4253286441Srpaulo * struct iwm_mac_beacon_cmd - beacon template command 4254286441Srpaulo * @tx: the tx commands associated with the beacon frame 4255286441Srpaulo * @template_id: currently equal to the mac context id of the coresponding 4256286441Srpaulo * mac. 4257286441Srpaulo * @tim_idx: the offset of the tim IE in the beacon 4258286441Srpaulo * @tim_size: the length of the tim IE 4259286441Srpaulo * @frame: the template of the beacon frame 4260286441Srpaulo */ 4261286441Srpaulostruct iwm_mac_beacon_cmd { 4262286441Srpaulo struct iwm_tx_cmd tx; 4263286441Srpaulo uint32_t template_id; 4264286441Srpaulo uint32_t tim_idx; 4265286441Srpaulo uint32_t tim_size; 4266286441Srpaulo struct ieee80211_frame frame[0]; 4267286441Srpaulo} __packed; 4268286441Srpaulo 4269286441Srpaulostruct iwm_beacon_notif { 4270286441Srpaulo struct iwm_mvm_tx_resp beacon_notify_hdr; 4271286441Srpaulo uint64_t tsf; 4272286441Srpaulo uint32_t ibss_mgr_status; 4273286441Srpaulo} __packed; 4274286441Srpaulo 4275286441Srpaulo/** 4276286441Srpaulo * enum iwm_dump_control - dump (flush) control flags 4277300050Seadler * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4278286441Srpaulo * and the TFD queues are empty. 4279286441Srpaulo */ 4280286441Srpauloenum iwm_dump_control { 4281286441Srpaulo IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4282286441Srpaulo}; 4283286441Srpaulo 4284286441Srpaulo/** 4285286441Srpaulo * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4286286441Srpaulo * @queues_ctl: bitmap of queues to flush 4287286441Srpaulo * @flush_ctl: control flags 4288286441Srpaulo * @reserved: reserved 4289286441Srpaulo */ 4290286441Srpaulostruct iwm_tx_path_flush_cmd { 4291286441Srpaulo uint32_t queues_ctl; 4292286441Srpaulo uint16_t flush_ctl; 4293286441Srpaulo uint16_t reserved; 4294286441Srpaulo} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4295286441Srpaulo 4296286441Srpaulo/** 4297286441Srpaulo * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4298286441Srpaulo * @tx_resp: the Tx response from the fw (agg or non-agg) 4299286441Srpaulo * 4300286441Srpaulo * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4301286441Srpaulo * it can't know that everything will go well until the end of the AMPDU, it 4302286441Srpaulo * can't know in advance the number of MPDUs that will be sent in the current 4303286441Srpaulo * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4304286441Srpaulo * Hence, it can't know in advance what the SSN of the SCD will be at the end 4305286441Srpaulo * of the batch. This is why the SSN of the SCD is written at the end of the 4306286441Srpaulo * whole struct at a variable offset. This function knows how to cope with the 4307286441Srpaulo * variable offset and returns the SSN of the SCD. 4308286441Srpaulo */ 4309286441Srpaulostatic inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4310286441Srpaulo{ 4311286441Srpaulo return le32_to_cpup((uint32_t *)&tx_resp->status + 4312286441Srpaulo tx_resp->frame_count) & 0xfff; 4313286441Srpaulo} 4314286441Srpaulo 4315286441Srpaulo/* 4316286441Srpaulo * END mvm/fw-api-tx.h 4317286441Srpaulo */ 4318286441Srpaulo 4319286441Srpaulo/* 4320286441Srpaulo * BEGIN mvm/fw-api-scan.h 4321286441Srpaulo */ 4322286441Srpaulo 4323286441Srpaulo/* Scan Commands, Responses, Notifications */ 4324286441Srpaulo 4325286441Srpaulo/* Masks for iwm_scan_channel.type flags */ 4326286441Srpaulo#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4327286441Srpaulo#define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 4328286441Srpaulo 4329286441Srpaulo/* Max number of IEs for direct SSID scans in a command */ 4330286441Srpaulo#define IWM_PROBE_OPTION_MAX 20 4331286441Srpaulo 4332286441Srpaulo/** 4333286441Srpaulo * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 4334286441Srpaulo * @channel: band is selected by iwm_scan_cmd "flags" field 4335286441Srpaulo * @tx_gain: gain for analog radio 4336286441Srpaulo * @dsp_atten: gain for DSP 4337286441Srpaulo * @active_dwell: dwell time for active scan in TU, typically 5-50 4338286441Srpaulo * @passive_dwell: dwell time for passive scan in TU, typically 20-500 4339286441Srpaulo * @type: type is broken down to these bits: 4340286441Srpaulo * bit 0: 0 = passive, 1 = active 4341286441Srpaulo * bits 1-20: SSID direct bit map. If any of these bits is set then 4342286441Srpaulo * the corresponding SSID IE is transmitted in probe request 4343286441Srpaulo * (bit i adds IE in position i to the probe request) 4344286441Srpaulo * bit 22: channel width, 0 = regular, 1 = TGj narrow channel 4345286441Srpaulo * 4346286441Srpaulo * @iteration_count: 4347286441Srpaulo * @iteration_interval: 4348286441Srpaulo * This struct is used once for each channel in the scan list. 4349286441Srpaulo * Each channel can independently select: 4350286441Srpaulo * 1) SSID for directed active scans 4351286441Srpaulo * 2) Txpower setting (for rate specified within Tx command) 4352286441Srpaulo * 3) How long to stay on-channel (behavior may be modified by quiet_time, 4353286441Srpaulo * quiet_plcp_th, good_CRC_th) 4354286441Srpaulo * 4355286441Srpaulo * To avoid uCode errors, make sure the following are true (see comments 4356286441Srpaulo * under struct iwm_scan_cmd about max_out_time and quiet_time): 4357286441Srpaulo * 1) If using passive_dwell (i.e. passive_dwell != 0): 4358286441Srpaulo * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 4359286441Srpaulo * 2) quiet_time <= active_dwell 4360286441Srpaulo * 3) If restricting off-channel time (i.e. max_out_time !=0): 4361286441Srpaulo * passive_dwell < max_out_time 4362286441Srpaulo * active_dwell < max_out_time 4363286441Srpaulo */ 4364286441Srpaulostruct iwm_scan_channel { 4365286441Srpaulo uint32_t type; 4366286441Srpaulo uint16_t channel; 4367286441Srpaulo uint16_t iteration_count; 4368286441Srpaulo uint32_t iteration_interval; 4369286441Srpaulo uint16_t active_dwell; 4370286441Srpaulo uint16_t passive_dwell; 4371286441Srpaulo} __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ 4372286441Srpaulo 4373286441Srpaulo/** 4374286441Srpaulo * struct iwm_ssid_ie - directed scan network information element 4375286441Srpaulo * 4376286441Srpaulo * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4377286441Srpaulo * selected by "type" bit field in struct iwm_scan_channel; 4378286441Srpaulo * each channel may select different ssids from among the 20 entries. 4379286441Srpaulo * SSID IEs get transmitted in reverse order of entry. 4380286441Srpaulo */ 4381286441Srpaulostruct iwm_ssid_ie { 4382286441Srpaulo uint8_t id; 4383286441Srpaulo uint8_t len; 4384286441Srpaulo uint8_t ssid[IEEE80211_NWID_LEN]; 4385286441Srpaulo} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4386286441Srpaulo 4387286441Srpaulo/** 4388286441Srpaulo * iwm_scan_flags - masks for scan command flags 4389286441Srpaulo *@IWM_SCAN_FLAGS_PERIODIC_SCAN: 4390286441Srpaulo *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX: 4391286441Srpaulo *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND: 4392286441Srpaulo *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND: 4393286441Srpaulo *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN: 4394286441Srpaulo *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active 4395286441Srpaulo * in the past hour, even if they are marked as passive. 4396286441Srpaulo */ 4397286441Srpauloenum iwm_scan_flags { 4398286441Srpaulo IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0), 4399286441Srpaulo IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1), 4400286441Srpaulo IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2), 4401286441Srpaulo IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3), 4402286441Srpaulo IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4), 4403286441Srpaulo IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5), 4404286441Srpaulo}; 4405286441Srpaulo 4406286441Srpaulo/** 4407286441Srpaulo * enum iwm_scan_type - Scan types for scan command 4408286441Srpaulo * @IWM_SCAN_TYPE_FORCED: 4409286441Srpaulo * @IWM_SCAN_TYPE_BACKGROUND: 4410286441Srpaulo * @IWM_SCAN_TYPE_OS: 4411286441Srpaulo * @IWM_SCAN_TYPE_ROAMING: 4412286441Srpaulo * @IWM_SCAN_TYPE_ACTION: 4413286441Srpaulo * @IWM_SCAN_TYPE_DISCOVERY: 4414286441Srpaulo * @IWM_SCAN_TYPE_DISCOVERY_FORCED: 4415286441Srpaulo */ 4416286441Srpauloenum iwm_scan_type { 4417286441Srpaulo IWM_SCAN_TYPE_FORCED = 0, 4418286441Srpaulo IWM_SCAN_TYPE_BACKGROUND = 1, 4419286441Srpaulo IWM_SCAN_TYPE_OS = 2, 4420286441Srpaulo IWM_SCAN_TYPE_ROAMING = 3, 4421286441Srpaulo IWM_SCAN_TYPE_ACTION = 4, 4422286441Srpaulo IWM_SCAN_TYPE_DISCOVERY = 5, 4423286441Srpaulo IWM_SCAN_TYPE_DISCOVERY_FORCED = 6, 4424286441Srpaulo}; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ 4425286441Srpaulo 4426286441Srpaulo/* Maximal number of channels to scan */ 4427286441Srpaulo#define IWM_MAX_NUM_SCAN_CHANNELS 0x24 4428286441Srpaulo 4429286441Srpaulo/** 4430286441Srpaulo * struct iwm_scan_cmd - scan request command 4431286441Srpaulo * ( IWM_SCAN_REQUEST_CMD = 0x80 ) 4432286441Srpaulo * @len: command length in bytes 4433286441Srpaulo * @scan_flags: scan flags from IWM_SCAN_FLAGS_* 4434286441Srpaulo * @channel_count: num of channels in channel list (1 - IWM_MAX_NUM_SCAN_CHANNELS) 4435286441Srpaulo * @quiet_time: in msecs, dwell this time for active scan on quiet channels 4436286441Srpaulo * @quiet_plcp_th: quiet PLCP threshold (channel is quiet if less than 4437286441Srpaulo * this number of packets were received (typically 1) 4438286441Srpaulo * @passive2active: is auto switching from passive to active during scan allowed 4439286441Srpaulo * @rxchain_sel_flags: RXON_RX_CHAIN_* 4440286441Srpaulo * @max_out_time: in usecs, max out of serving channel time 4441286441Srpaulo * @suspend_time: how long to pause scan when returning to service channel: 4442298955Spfg * bits 0-19: beacon interval in usecs (suspend before executing) 4443286441Srpaulo * bits 20-23: reserved 4444286441Srpaulo * bits 24-31: number of beacons (suspend between channels) 4445286441Srpaulo * @rxon_flags: RXON_FLG_* 4446286441Srpaulo * @filter_flags: RXON_FILTER_* 4447286441Srpaulo * @tx_cmd: for active scans (zero for passive), w/o payload, 4448286441Srpaulo * no RS so specify TX rate 4449286441Srpaulo * @direct_scan: direct scan SSIDs 4450286441Srpaulo * @type: one of IWM_SCAN_TYPE_* 4451286441Srpaulo * @repeats: how many time to repeat the scan 4452286441Srpaulo */ 4453286441Srpaulostruct iwm_scan_cmd { 4454286441Srpaulo uint16_t len; 4455286441Srpaulo uint8_t scan_flags; 4456286441Srpaulo uint8_t channel_count; 4457286441Srpaulo uint16_t quiet_time; 4458286441Srpaulo uint16_t quiet_plcp_th; 4459286441Srpaulo uint16_t passive2active; 4460286441Srpaulo uint16_t rxchain_sel_flags; 4461286441Srpaulo uint32_t max_out_time; 4462286441Srpaulo uint32_t suspend_time; 4463286441Srpaulo /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 4464286441Srpaulo uint32_t rxon_flags; 4465286441Srpaulo uint32_t filter_flags; 4466286441Srpaulo struct iwm_tx_cmd tx_cmd; 4467286441Srpaulo struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4468286441Srpaulo uint32_t type; 4469286441Srpaulo uint32_t repeats; 4470286441Srpaulo 4471286441Srpaulo /* 4472286441Srpaulo * Probe request frame, followed by channel list. 4473286441Srpaulo * 4474286441Srpaulo * Size of probe request frame is specified by byte count in tx_cmd. 4475286441Srpaulo * Channel list follows immediately after probe request frame. 4476286441Srpaulo * Number of channels in list is specified by channel_count. 4477286441Srpaulo * Each channel in list is of type: 4478286441Srpaulo * 4479286441Srpaulo * struct iwm_scan_channel channels[0]; 4480286441Srpaulo * 4481286441Srpaulo * NOTE: Only one band of channels can be scanned per pass. You 4482286441Srpaulo * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait 4483286441Srpaulo * for one scan to complete (i.e. receive IWM_SCAN_COMPLETE_NOTIFICATION) 4484286441Srpaulo * before requesting another scan. 4485286441Srpaulo */ 4486286441Srpaulo uint8_t data[0]; 4487286441Srpaulo} __packed; /* IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_5 */ 4488286441Srpaulo 4489286441Srpaulo/* Response to scan request contains only status with one of these values */ 4490286441Srpaulo#define IWM_SCAN_RESPONSE_OK 0x1 4491286441Srpaulo#define IWM_SCAN_RESPONSE_ERROR 0x2 4492286441Srpaulo 4493286441Srpaulo/* 4494286441Srpaulo * IWM_SCAN_ABORT_CMD = 0x81 4495286441Srpaulo * When scan abort is requested, the command has no fields except the common 4496286441Srpaulo * header. The response contains only a status with one of these values. 4497286441Srpaulo */ 4498286441Srpaulo#define IWM_SCAN_ABORT_POSSIBLE 0x1 4499286441Srpaulo#define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ 4500286441Srpaulo 4501286441Srpaulo/* TODO: complete documentation */ 4502286441Srpaulo#define IWM_SCAN_OWNER_STATUS 0x1 4503286441Srpaulo#define IWM_MEASURE_OWNER_STATUS 0x2 4504286441Srpaulo 4505286441Srpaulo/** 4506286441Srpaulo * struct iwm_scan_start_notif - notifies start of scan in the device 4507286441Srpaulo * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) 4508286441Srpaulo * @tsf_low: TSF timer (lower half) in usecs 4509286441Srpaulo * @tsf_high: TSF timer (higher half) in usecs 4510286441Srpaulo * @beacon_timer: structured as follows: 4511286441Srpaulo * bits 0:19 - beacon interval in usecs 4512286441Srpaulo * bits 20:23 - reserved (0) 4513286441Srpaulo * bits 24:31 - number of beacons 4514286441Srpaulo * @channel: which channel is scanned 4515286441Srpaulo * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4516286441Srpaulo * @status: one of *_OWNER_STATUS 4517286441Srpaulo */ 4518286441Srpaulostruct iwm_scan_start_notif { 4519286441Srpaulo uint32_t tsf_low; 4520286441Srpaulo uint32_t tsf_high; 4521286441Srpaulo uint32_t beacon_timer; 4522286441Srpaulo uint8_t channel; 4523286441Srpaulo uint8_t band; 4524286441Srpaulo uint8_t reserved[2]; 4525286441Srpaulo uint32_t status; 4526286441Srpaulo} __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ 4527286441Srpaulo 4528286441Srpaulo/* scan results probe_status first bit indicates success */ 4529286441Srpaulo#define IWM_SCAN_PROBE_STATUS_OK 0 4530286441Srpaulo#define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) 4531286441Srpaulo/* error statuses combined with TX_FAILED */ 4532286441Srpaulo#define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) 4533286441Srpaulo#define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) 4534286441Srpaulo 4535286441Srpaulo/* How many statistics are gathered for each channel */ 4536286441Srpaulo#define IWM_SCAN_RESULTS_STATISTICS 1 4537286441Srpaulo 4538286441Srpaulo/** 4539286441Srpaulo * enum iwm_scan_complete_status - status codes for scan complete notifications 4540286441Srpaulo * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4541286441Srpaulo * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4542286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4543286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4544286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4545286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4546286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4547286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4548286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4549286441Srpaulo * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4550286441Srpaulo * (not an error!) 4551286441Srpaulo * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4552286441Srpaulo * asked for 4553286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4554286441Srpaulo*/ 4555286441Srpauloenum iwm_scan_complete_status { 4556286441Srpaulo IWM_SCAN_COMP_STATUS_OK = 0x1, 4557286441Srpaulo IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4558286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4559286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4560286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4561286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4562286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4563286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4564286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4565286441Srpaulo IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4566286441Srpaulo IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4567286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4568286441Srpaulo}; 4569286441Srpaulo 4570286441Srpaulo/** 4571286441Srpaulo * struct iwm_scan_results_notif - scan results for one channel 4572286441Srpaulo * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4573286441Srpaulo * @channel: which channel the results are from 4574286441Srpaulo * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4575286441Srpaulo * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4576286441Srpaulo * @num_probe_not_sent: # of request that weren't sent due to not enough time 4577286441Srpaulo * @duration: duration spent in channel, in usecs 4578286441Srpaulo * @statistics: statistics gathered for this channel 4579286441Srpaulo */ 4580286441Srpaulostruct iwm_scan_results_notif { 4581286441Srpaulo uint8_t channel; 4582286441Srpaulo uint8_t band; 4583286441Srpaulo uint8_t probe_status; 4584286441Srpaulo uint8_t num_probe_not_sent; 4585286441Srpaulo uint32_t duration; 4586286441Srpaulo uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 4587286441Srpaulo} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 4588286441Srpaulo 4589286441Srpaulo/** 4590286441Srpaulo * struct iwm_scan_complete_notif - notifies end of scanning (all channels) 4591286441Srpaulo * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) 4592286441Srpaulo * @scanned_channels: number of channels scanned (and number of valid results) 4593286441Srpaulo * @status: one of IWM_SCAN_COMP_STATUS_* 4594286441Srpaulo * @bt_status: BT on/off status 4595286441Srpaulo * @last_channel: last channel that was scanned 4596286441Srpaulo * @tsf_low: TSF timer (lower half) in usecs 4597286441Srpaulo * @tsf_high: TSF timer (higher half) in usecs 4598286441Srpaulo * @results: all scan results, only "scanned_channels" of them are valid 4599286441Srpaulo */ 4600286441Srpaulostruct iwm_scan_complete_notif { 4601286441Srpaulo uint8_t scanned_channels; 4602286441Srpaulo uint8_t status; 4603286441Srpaulo uint8_t bt_status; 4604286441Srpaulo uint8_t last_channel; 4605286441Srpaulo uint32_t tsf_low; 4606286441Srpaulo uint32_t tsf_high; 4607286441Srpaulo struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; 4608286441Srpaulo} __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ 4609286441Srpaulo 4610286441Srpaulo/* scan offload */ 4611286441Srpaulo#define IWM_MAX_SCAN_CHANNELS 40 4612286441Srpaulo#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4613286441Srpaulo#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4614286441Srpaulo#define IWM_SCAN_MAX_PROFILES 11 4615286441Srpaulo#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4616286441Srpaulo 4617286441Srpaulo/* Default watchdog (in MS) for scheduled scan iteration */ 4618286441Srpaulo#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4619286441Srpaulo 4620286441Srpaulo#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4621286441Srpaulo#define IWM_CAN_ABORT_STATUS 1 4622286441Srpaulo 4623286441Srpaulo#define IWM_FULL_SCAN_MULTIPLIER 5 4624286441Srpaulo#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4625286441Srpaulo 4626286441Srpauloenum iwm_scan_framework_client { 4627286441Srpaulo IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4628286441Srpaulo IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 4629286441Srpaulo IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 4630286441Srpaulo}; 4631286441Srpaulo 4632286441Srpaulo/** 4633286441Srpaulo * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 4634286441Srpaulo * @scan_flags: see enum iwm_scan_flags 4635286441Srpaulo * @channel_count: channels in channel list 4636286441Srpaulo * @quiet_time: dwell time, in milisiconds, on quiet channel 4637286441Srpaulo * @quiet_plcp_th: quiet channel num of packets threshold 4638286441Srpaulo * @good_CRC_th: passive to active promotion threshold 4639286441Srpaulo * @rx_chain: RXON rx chain. 4640286441Srpaulo * @max_out_time: max uSec to be out of assoceated channel 4641286441Srpaulo * @suspend_time: pause scan this long when returning to service channel 4642286441Srpaulo * @flags: RXON flags 4643286441Srpaulo * @filter_flags: RXONfilter 4644286441Srpaulo * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. 4645286441Srpaulo * @direct_scan: list of SSIDs for directed active scan 4646286441Srpaulo * @scan_type: see enum iwm_scan_type. 4647286441Srpaulo * @rep_count: repetition count for each scheduled scan iteration. 4648286441Srpaulo */ 4649286441Srpaulostruct iwm_scan_offload_cmd { 4650286441Srpaulo uint16_t len; 4651286441Srpaulo uint8_t scan_flags; 4652286441Srpaulo uint8_t channel_count; 4653286441Srpaulo uint16_t quiet_time; 4654286441Srpaulo uint16_t quiet_plcp_th; 4655286441Srpaulo uint16_t good_CRC_th; 4656286441Srpaulo uint16_t rx_chain; 4657286441Srpaulo uint32_t max_out_time; 4658286441Srpaulo uint32_t suspend_time; 4659286441Srpaulo /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 4660286441Srpaulo uint32_t flags; 4661286441Srpaulo uint32_t filter_flags; 4662286441Srpaulo struct iwm_tx_cmd tx_cmd[2]; 4663286441Srpaulo /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4664286441Srpaulo struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4665286441Srpaulo uint32_t scan_type; 4666286441Srpaulo uint32_t rep_count; 4667286441Srpaulo} __packed; 4668286441Srpaulo 4669286441Srpauloenum iwm_scan_offload_channel_flags { 4670286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0), 4671286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22), 4672286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24), 4673286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25), 4674286441Srpaulo}; 4675286441Srpaulo 4676286441Srpaulo/** 4677286441Srpaulo * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S 4678286441Srpaulo * @type: bitmap - see enum iwm_scan_offload_channel_flags. 4679286441Srpaulo * 0: passive (0) or active (1) scan. 4680286441Srpaulo * 1-20: directed scan to i'th ssid. 4681286441Srpaulo * 22: channel width configuation - 1 for narrow. 4682286441Srpaulo * 24: full scan. 4683286441Srpaulo * 25: partial scan. 4684286441Srpaulo * @channel_number: channel number 1-13 etc. 4685286441Srpaulo * @iter_count: repetition count for the channel. 4686286441Srpaulo * @iter_interval: interval between two innteration on one channel. 4687286441Srpaulo * @dwell_time: entry 0 - active scan, entry 1 - passive scan. 4688286441Srpaulo */ 4689286441Srpaulostruct iwm_scan_channel_cfg { 4690286441Srpaulo uint32_t type[IWM_MAX_SCAN_CHANNELS]; 4691286441Srpaulo uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; 4692286441Srpaulo uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; 4693286441Srpaulo uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; 4694286441Srpaulo uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; 4695286441Srpaulo} __packed; 4696286441Srpaulo 4697286441Srpaulo/** 4698286441Srpaulo * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S 4699286441Srpaulo * @scan_cmd: scan command fixed part 4700286441Srpaulo * @channel_cfg: scan channel configuration 4701286441Srpaulo * @data: probe request frames (one per band) 4702286441Srpaulo */ 4703286441Srpaulostruct iwm_scan_offload_cfg { 4704286441Srpaulo struct iwm_scan_offload_cmd scan_cmd; 4705286441Srpaulo struct iwm_scan_channel_cfg channel_cfg; 4706286441Srpaulo uint8_t data[0]; 4707286441Srpaulo} __packed; 4708286441Srpaulo 4709286441Srpaulo/** 4710286441Srpaulo * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 4711286441Srpaulo * @ssid: MAC address to filter out 4712286441Srpaulo * @reported_rssi: AP rssi reported to the host 4713286441Srpaulo * @client_bitmap: clients ignore this entry - enum scan_framework_client 4714286441Srpaulo */ 4715286441Srpaulostruct iwm_scan_offload_blacklist { 4716286441Srpaulo uint8_t ssid[IEEE80211_ADDR_LEN]; 4717286441Srpaulo uint8_t reported_rssi; 4718286441Srpaulo uint8_t client_bitmap; 4719286441Srpaulo} __packed; 4720286441Srpaulo 4721286441Srpauloenum iwm_scan_offload_network_type { 4722286441Srpaulo IWM_NETWORK_TYPE_BSS = 1, 4723286441Srpaulo IWM_NETWORK_TYPE_IBSS = 2, 4724286441Srpaulo IWM_NETWORK_TYPE_ANY = 3, 4725286441Srpaulo}; 4726286441Srpaulo 4727286441Srpauloenum iwm_scan_offload_band_selection { 4728286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 4729286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 4730286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 4731286441Srpaulo}; 4732286441Srpaulo 4733286441Srpaulo/** 4734286441Srpaulo * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 4735286441Srpaulo * @ssid_index: index to ssid list in fixed part 4736286441Srpaulo * @unicast_cipher: encryption olgorithm to match - bitmap 4737286441Srpaulo * @aut_alg: authentication olgorithm to match - bitmap 4738286441Srpaulo * @network_type: enum iwm_scan_offload_network_type 4739286441Srpaulo * @band_selection: enum iwm_scan_offload_band_selection 4740286441Srpaulo * @client_bitmap: clients waiting for match - enum scan_framework_client 4741286441Srpaulo */ 4742286441Srpaulostruct iwm_scan_offload_profile { 4743286441Srpaulo uint8_t ssid_index; 4744286441Srpaulo uint8_t unicast_cipher; 4745286441Srpaulo uint8_t auth_alg; 4746286441Srpaulo uint8_t network_type; 4747286441Srpaulo uint8_t band_selection; 4748286441Srpaulo uint8_t client_bitmap; 4749286441Srpaulo uint8_t reserved[2]; 4750286441Srpaulo} __packed; 4751286441Srpaulo 4752286441Srpaulo/** 4753286441Srpaulo * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 4754286441Srpaulo * @blaclist: AP list to filter off from scan results 4755286441Srpaulo * @profiles: profiles to search for match 4756286441Srpaulo * @blacklist_len: length of blacklist 4757286441Srpaulo * @num_profiles: num of profiles in the list 4758286441Srpaulo * @match_notify: clients waiting for match found notification 4759286441Srpaulo * @pass_match: clients waiting for the results 4760286441Srpaulo * @active_clients: active clients bitmap - enum scan_framework_client 4761286441Srpaulo * @any_beacon_notify: clients waiting for match notification without match 4762286441Srpaulo */ 4763286441Srpaulostruct iwm_scan_offload_profile_cfg { 4764286441Srpaulo struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 4765286441Srpaulo uint8_t blacklist_len; 4766286441Srpaulo uint8_t num_profiles; 4767286441Srpaulo uint8_t match_notify; 4768286441Srpaulo uint8_t pass_match; 4769286441Srpaulo uint8_t active_clients; 4770286441Srpaulo uint8_t any_beacon_notify; 4771286441Srpaulo uint8_t reserved[2]; 4772286441Srpaulo} __packed; 4773286441Srpaulo 4774286441Srpaulo/** 4775286441Srpaulo * iwm_scan_offload_schedule - schedule of scan offload 4776286441Srpaulo * @delay: delay between iterations, in seconds. 4777286441Srpaulo * @iterations: num of scan iterations 4778286441Srpaulo * @full_scan_mul: number of partial scans before each full scan 4779286441Srpaulo */ 4780286441Srpaulostruct iwm_scan_offload_schedule { 4781286441Srpaulo uint16_t delay; 4782286441Srpaulo uint8_t iterations; 4783286441Srpaulo uint8_t full_scan_mul; 4784286441Srpaulo} __packed; 4785286441Srpaulo 4786286441Srpaulo/* 4787286441Srpaulo * iwm_scan_offload_flags 4788286441Srpaulo * 4789286441Srpaulo * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. 4790286441Srpaulo * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. 4791286441Srpaulo * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan 4792286441Srpaulo * on A band. 4793286441Srpaulo */ 4794286441Srpauloenum iwm_scan_offload_flags { 4795286441Srpaulo IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0), 4796286441Srpaulo IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2), 4797286441Srpaulo IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3), 4798286441Srpaulo}; 4799286441Srpaulo 4800286441Srpaulo/** 4801286441Srpaulo * iwm_scan_offload_req - scan offload request command 4802286441Srpaulo * @flags: bitmap - enum iwm_scan_offload_flags. 4803286441Srpaulo * @watchdog: maximum scan duration in TU. 4804286441Srpaulo * @delay: delay in seconds before first iteration. 4805286441Srpaulo * @schedule_line: scan offload schedule, for fast and regular scan. 4806286441Srpaulo */ 4807286441Srpaulostruct iwm_scan_offload_req { 4808286441Srpaulo uint16_t flags; 4809286441Srpaulo uint16_t watchdog; 4810286441Srpaulo uint16_t delay; 4811286441Srpaulo uint16_t reserved; 4812286441Srpaulo struct iwm_scan_offload_schedule schedule_line[2]; 4813286441Srpaulo} __packed; 4814286441Srpaulo 4815286441Srpauloenum iwm_scan_offload_compleate_status { 4816286441Srpaulo IWM_SCAN_OFFLOAD_COMPLETED = 1, 4817286441Srpaulo IWM_SCAN_OFFLOAD_ABORTED = 2, 4818286441Srpaulo}; 4819286441Srpaulo 4820286441Srpaulo/** 4821286441Srpaulo * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 4822286441Srpaulo * @last_schedule_line: last schedule line executed (fast or regular) 4823286441Srpaulo * @last_schedule_iteration: last scan iteration executed before scan abort 4824286441Srpaulo * @status: enum iwm_scan_offload_compleate_status 4825286441Srpaulo */ 4826286441Srpaulostruct iwm_scan_offload_complete { 4827286441Srpaulo uint8_t last_schedule_line; 4828286441Srpaulo uint8_t last_schedule_iteration; 4829286441Srpaulo uint8_t status; 4830286441Srpaulo uint8_t reserved; 4831286441Srpaulo} __packed; 4832286441Srpaulo 4833286441Srpaulo/** 4834286441Srpaulo * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 4835286441Srpaulo * @ssid_bitmap: SSIDs indexes found in this iteration 4836286441Srpaulo * @client_bitmap: clients that are active and wait for this notification 4837286441Srpaulo */ 4838286441Srpaulostruct iwm_sched_scan_results { 4839286441Srpaulo uint16_t ssid_bitmap; 4840286441Srpaulo uint8_t client_bitmap; 4841286441Srpaulo uint8_t reserved; 4842286441Srpaulo}; 4843286441Srpaulo 4844286441Srpaulo/* 4845286441Srpaulo * END mvm/fw-api-scan.h 4846286441Srpaulo */ 4847286441Srpaulo 4848286441Srpaulo/* 4849286441Srpaulo * BEGIN mvm/fw-api-sta.h 4850286441Srpaulo */ 4851286441Srpaulo 4852286441Srpaulo/** 4853286441Srpaulo * enum iwm_sta_flags - flags for the ADD_STA host command 4854286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 4855286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 4856286441Srpaulo * @IWM_STA_FLG_FLG_ANT_MSK: Antenna selection 4857286441Srpaulo * @IWM_STA_FLG_PS: set if STA is in Power Save 4858286441Srpaulo * @IWM_STA_FLG_INVALID: set if STA is invalid 4859286441Srpaulo * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 4860286441Srpaulo * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 4861286441Srpaulo * @IWM_STA_FLG_DRAIN_FLOW: drain flow 4862286441Srpaulo * @IWM_STA_FLG_PAN: STA is for PAN interface 4863286441Srpaulo * @IWM_STA_FLG_CLASS_AUTH: 4864286441Srpaulo * @IWM_STA_FLG_CLASS_ASSOC: 4865286441Srpaulo * @IWM_STA_FLG_CLASS_MIMO_PROT: 4866286441Srpaulo * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 4867286441Srpaulo * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 4868286441Srpaulo * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 4869286441Srpaulo * initialised by driver and can be updated by fw upon reception of 4870286441Srpaulo * action frames that can change the channel width. When cleared the fw 4871286441Srpaulo * will send all the frames in 20MHz even when FAT channel is requested. 4872286441Srpaulo * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 4873286441Srpaulo * driver and can be updated by fw upon reception of action frames. 4874286441Srpaulo * @IWM_STA_FLG_MFP_EN: Management Frame Protection 4875286441Srpaulo */ 4876286441Srpauloenum iwm_sta_flags { 4877286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 4878286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 4879286441Srpaulo 4880286441Srpaulo IWM_STA_FLG_FLG_ANT_A = (1 << 4), 4881286441Srpaulo IWM_STA_FLG_FLG_ANT_B = (2 << 4), 4882286441Srpaulo IWM_STA_FLG_FLG_ANT_MSK = (IWM_STA_FLG_FLG_ANT_A | 4883286441Srpaulo IWM_STA_FLG_FLG_ANT_B), 4884286441Srpaulo 4885286441Srpaulo IWM_STA_FLG_PS = (1 << 8), 4886286441Srpaulo IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 4887286441Srpaulo IWM_STA_FLG_PAN = (1 << 13), 4888286441Srpaulo IWM_STA_FLG_CLASS_AUTH = (1 << 14), 4889286441Srpaulo IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 4890286441Srpaulo IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 4891286441Srpaulo 4892286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 4893286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4894286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4895286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4896286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4897286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4898286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4899286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4900286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4901286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 4902286441Srpaulo 4903286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 4904286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 4905286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 4906286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 4907286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 4908286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 4909286441Srpaulo 4910286441Srpaulo IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 4911286441Srpaulo IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 4912286441Srpaulo IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 4913286441Srpaulo IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 4914286441Srpaulo IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 4915286441Srpaulo 4916286441Srpaulo IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 4917286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 4918286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 4919286441Srpaulo IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 4920286441Srpaulo}; 4921286441Srpaulo 4922286441Srpaulo/** 4923286441Srpaulo * enum iwm_sta_key_flag - key flags for the ADD_STA host command 4924286441Srpaulo * @IWM_STA_KEY_FLG_NO_ENC: no encryption 4925286441Srpaulo * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 4926286441Srpaulo * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 4927286441Srpaulo * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 4928286441Srpaulo * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 4929286441Srpaulo * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 4930286441Srpaulo * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 4931286441Srpaulo * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 4932286441Srpaulo * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 4933286441Srpaulo * station info array (1 - n 1X mode) 4934286441Srpaulo * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 4935286441Srpaulo * @IWM_STA_KEY_NOT_VALID: key is invalid 4936286441Srpaulo * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 4937286441Srpaulo * @IWM_STA_KEY_MULTICAST: set for multical key 4938286441Srpaulo * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 4939286441Srpaulo */ 4940286441Srpauloenum iwm_sta_key_flag { 4941286441Srpaulo IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 4942286441Srpaulo IWM_STA_KEY_FLG_WEP = (1 << 0), 4943286441Srpaulo IWM_STA_KEY_FLG_CCM = (2 << 0), 4944286441Srpaulo IWM_STA_KEY_FLG_TKIP = (3 << 0), 4945286441Srpaulo IWM_STA_KEY_FLG_EXT = (4 << 0), 4946286441Srpaulo IWM_STA_KEY_FLG_CMAC = (6 << 0), 4947286441Srpaulo IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 4948286441Srpaulo IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 4949286441Srpaulo 4950286441Srpaulo IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 4951286441Srpaulo IWM_STA_KEY_FLG_KEYID_POS = 8, 4952286441Srpaulo IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 4953286441Srpaulo IWM_STA_KEY_NOT_VALID = (1 << 11), 4954286441Srpaulo IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 4955286441Srpaulo IWM_STA_KEY_MULTICAST = (1 << 14), 4956286441Srpaulo IWM_STA_KEY_MFP = (1 << 15), 4957286441Srpaulo}; 4958286441Srpaulo 4959286441Srpaulo/** 4960286441Srpaulo * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 4961286441Srpaulo * @IWM_STA_MODIFY_KEY: this command modifies %key 4962286441Srpaulo * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 4963286441Srpaulo * @IWM_STA_MODIFY_TX_RATE: unused 4964286441Srpaulo * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 4965286441Srpaulo * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 4966286441Srpaulo * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 4967286441Srpaulo * @IWM_STA_MODIFY_PROT_TH: 4968286441Srpaulo * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 4969286441Srpaulo */ 4970286441Srpauloenum iwm_sta_modify_flag { 4971286441Srpaulo IWM_STA_MODIFY_KEY = (1 << 0), 4972286441Srpaulo IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 4973286441Srpaulo IWM_STA_MODIFY_TX_RATE = (1 << 2), 4974286441Srpaulo IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 4975286441Srpaulo IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 4976286441Srpaulo IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 4977286441Srpaulo IWM_STA_MODIFY_PROT_TH = (1 << 6), 4978286441Srpaulo IWM_STA_MODIFY_QUEUES = (1 << 7), 4979286441Srpaulo}; 4980286441Srpaulo 4981286441Srpaulo#define IWM_STA_MODE_MODIFY 1 4982286441Srpaulo 4983286441Srpaulo/** 4984286441Srpaulo * enum iwm_sta_sleep_flag - type of sleep of the station 4985286441Srpaulo * @IWM_STA_SLEEP_STATE_AWAKE: 4986286441Srpaulo * @IWM_STA_SLEEP_STATE_PS_POLL: 4987286441Srpaulo * @IWM_STA_SLEEP_STATE_UAPSD: 4988286441Srpaulo */ 4989286441Srpauloenum iwm_sta_sleep_flag { 4990286441Srpaulo IWM_STA_SLEEP_STATE_AWAKE = 0, 4991286441Srpaulo IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 4992286441Srpaulo IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 4993286441Srpaulo}; 4994286441Srpaulo 4995286441Srpaulo/* STA ID and color bits definitions */ 4996286441Srpaulo#define IWM_STA_ID_SEED (0x0f) 4997286441Srpaulo#define IWM_STA_ID_POS (0) 4998286441Srpaulo#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 4999286441Srpaulo 5000286441Srpaulo#define IWM_STA_COLOR_SEED (0x7) 5001286441Srpaulo#define IWM_STA_COLOR_POS (4) 5002286441Srpaulo#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5003286441Srpaulo 5004286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5005286441Srpaulo (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5006286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5007286441Srpaulo (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5008286441Srpaulo 5009286441Srpaulo#define IWM_STA_KEY_MAX_NUM (16) 5010286441Srpaulo#define IWM_STA_KEY_IDX_INVALID (0xff) 5011286441Srpaulo#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5012286441Srpaulo#define IWM_MAX_GLOBAL_KEYS (4) 5013286441Srpaulo#define IWM_STA_KEY_LEN_WEP40 (5) 5014286441Srpaulo#define IWM_STA_KEY_LEN_WEP104 (13) 5015286441Srpaulo 5016286441Srpaulo/** 5017286441Srpaulo * struct iwm_mvm_keyinfo - key information 5018286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5019286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5020286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5021286441Srpaulo * @key_offset: key offset in the fw's key table 5022286441Srpaulo * @key: 16-byte unicast decryption key 5023286441Srpaulo * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5024286441Srpaulo * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5025286441Srpaulo * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5026286441Srpaulo */ 5027286441Srpaulostruct iwm_mvm_keyinfo { 5028286441Srpaulo uint16_t key_flags; 5029286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5030286441Srpaulo uint8_t reserved1; 5031286441Srpaulo uint16_t tkip_rx_ttak[5]; 5032286441Srpaulo uint8_t key_offset; 5033286441Srpaulo uint8_t reserved2; 5034286441Srpaulo uint8_t key[16]; 5035286441Srpaulo uint64_t tx_secur_seq_cnt; 5036286441Srpaulo uint64_t hw_tkip_mic_rx_key; 5037286441Srpaulo uint64_t hw_tkip_mic_tx_key; 5038286441Srpaulo} __packed; 5039286441Srpaulo 5040286441Srpaulo/** 5041286441Srpaulo * struct iwm_mvm_add_sta_cmd_v5 - Add/modify a station in the fw's sta table. 5042286441Srpaulo * ( IWM_REPLY_ADD_STA = 0x18 ) 5043286441Srpaulo * @add_modify: 1: modify existing, 0: add new station 5044286441Srpaulo * @unicast_tx_key_id: unicast tx key id. Relevant only when unicast key sent 5045286441Srpaulo * @multicast_tx_key_id: multicast tx key id. Relevant only when multicast key 5046286441Srpaulo * sent 5047286441Srpaulo * @mac_id_n_color: the Mac context this station belongs to 5048286441Srpaulo * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5049286441Srpaulo * @sta_id: index of station in uCode's station table 5050286441Srpaulo * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5051286441Srpaulo * alone. 1 - modify, 0 - don't change. 5052286441Srpaulo * @key: look at %iwm_mvm_keyinfo 5053286441Srpaulo * @station_flags: look at %iwm_sta_flags 5054286441Srpaulo * @station_flags_msk: what of %station_flags have changed 5055286441Srpaulo * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5056286441Srpaulo * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5057286441Srpaulo * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5058286441Srpaulo * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5059286441Srpaulo * add_immediate_ba_ssn. 5060286441Srpaulo * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5061286441Srpaulo * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5062286441Srpaulo * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5063286441Srpaulo * add_immediate_ba_tid. 5064286441Srpaulo * @sleep_tx_count: number of packets to transmit to station even though it is 5065286441Srpaulo * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5066286441Srpaulo * keeps track of STA sleep state. 5067286441Srpaulo * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5068286441Srpaulo * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5069286441Srpaulo * mac-addr. 5070286441Srpaulo * @beamform_flags: beam forming controls 5071286441Srpaulo * @tfd_queue_msk: tfd queues used by this station 5072286441Srpaulo * 5073286441Srpaulo * The device contains an internal table of per-station information, with info 5074286441Srpaulo * on security keys, aggregation parameters, and Tx rates for initial Tx 5075286441Srpaulo * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5076286441Srpaulo * 5077286441Srpaulo * ADD_STA sets up the table entry for one station, either creating a new 5078286441Srpaulo * entry, or modifying a pre-existing one. 5079286441Srpaulo */ 5080286441Srpaulostruct iwm_mvm_add_sta_cmd_v5 { 5081286441Srpaulo uint8_t add_modify; 5082286441Srpaulo uint8_t unicast_tx_key_id; 5083286441Srpaulo uint8_t multicast_tx_key_id; 5084286441Srpaulo uint8_t reserved1; 5085286441Srpaulo uint32_t mac_id_n_color; 5086286441Srpaulo uint8_t addr[IEEE80211_ADDR_LEN]; 5087286441Srpaulo uint16_t reserved2; 5088286441Srpaulo uint8_t sta_id; 5089286441Srpaulo uint8_t modify_mask; 5090286441Srpaulo uint16_t reserved3; 5091286441Srpaulo struct iwm_mvm_keyinfo key; 5092286441Srpaulo uint32_t station_flags; 5093286441Srpaulo uint32_t station_flags_msk; 5094286441Srpaulo uint16_t tid_disable_tx; 5095286441Srpaulo uint16_t reserved4; 5096286441Srpaulo uint8_t add_immediate_ba_tid; 5097286441Srpaulo uint8_t remove_immediate_ba_tid; 5098286441Srpaulo uint16_t add_immediate_ba_ssn; 5099286441Srpaulo uint16_t sleep_tx_count; 5100286441Srpaulo uint16_t sleep_state_flags; 5101286441Srpaulo uint16_t assoc_id; 5102286441Srpaulo uint16_t beamform_flags; 5103286441Srpaulo uint32_t tfd_queue_msk; 5104286441Srpaulo} __packed; /* IWM_ADD_STA_CMD_API_S_VER_5 */ 5105286441Srpaulo 5106286441Srpaulo/** 5107286441Srpaulo * struct iwm_mvm_add_sta_cmd_v6 - Add / modify a station 5108286441Srpaulo * VER_6 of this command is quite similar to VER_5 except 5109286441Srpaulo * exclusion of all fields related to the security key installation. 5110286441Srpaulo */ 5111286441Srpaulostruct iwm_mvm_add_sta_cmd_v6 { 5112286441Srpaulo uint8_t add_modify; 5113286441Srpaulo uint8_t reserved1; 5114286441Srpaulo uint16_t tid_disable_tx; 5115286441Srpaulo uint32_t mac_id_n_color; 5116286441Srpaulo uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5117286441Srpaulo uint16_t reserved2; 5118286441Srpaulo uint8_t sta_id; 5119286441Srpaulo uint8_t modify_mask; 5120286441Srpaulo uint16_t reserved3; 5121286441Srpaulo uint32_t station_flags; 5122286441Srpaulo uint32_t station_flags_msk; 5123286441Srpaulo uint8_t add_immediate_ba_tid; 5124286441Srpaulo uint8_t remove_immediate_ba_tid; 5125286441Srpaulo uint16_t add_immediate_ba_ssn; 5126286441Srpaulo uint16_t sleep_tx_count; 5127286441Srpaulo uint16_t sleep_state_flags; 5128286441Srpaulo uint16_t assoc_id; 5129286441Srpaulo uint16_t beamform_flags; 5130286441Srpaulo uint32_t tfd_queue_msk; 5131286441Srpaulo} __packed; /* IWM_ADD_STA_CMD_API_S_VER_6 */ 5132286441Srpaulo 5133286441Srpaulo/** 5134286441Srpaulo * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5135286441Srpaulo * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5136286441Srpaulo * @sta_id: index of station in uCode's station table 5137286441Srpaulo * @key_offset: key offset in key storage 5138286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5139286441Srpaulo * @key: key material data 5140286441Srpaulo * @key2: key material data 5141286441Srpaulo * @rx_secur_seq_cnt: RX security sequence counter for the key 5142286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5143286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5144286441Srpaulo */ 5145286441Srpaulostruct iwm_mvm_add_sta_key_cmd { 5146286441Srpaulo uint8_t sta_id; 5147286441Srpaulo uint8_t key_offset; 5148286441Srpaulo uint16_t key_flags; 5149286441Srpaulo uint8_t key[16]; 5150286441Srpaulo uint8_t key2[16]; 5151286441Srpaulo uint8_t rx_secur_seq_cnt[16]; 5152286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5153286441Srpaulo uint8_t reserved; 5154286441Srpaulo uint16_t tkip_rx_ttak[5]; 5155286441Srpaulo} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5156286441Srpaulo 5157286441Srpaulo/** 5158286441Srpaulo * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5159286441Srpaulo * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5160286441Srpaulo * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5161286441Srpaulo * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5162286441Srpaulo * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5163286441Srpaulo * that doesn't exist. 5164286441Srpaulo */ 5165286441Srpauloenum iwm_mvm_add_sta_rsp_status { 5166286441Srpaulo IWM_ADD_STA_SUCCESS = 0x1, 5167286441Srpaulo IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5168286441Srpaulo IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5169286441Srpaulo IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5170286441Srpaulo}; 5171286441Srpaulo 5172286441Srpaulo/** 5173286441Srpaulo * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5174286441Srpaulo * ( IWM_REMOVE_STA = 0x19 ) 5175286441Srpaulo * @sta_id: the station id of the station to be removed 5176286441Srpaulo */ 5177286441Srpaulostruct iwm_mvm_rm_sta_cmd { 5178286441Srpaulo uint8_t sta_id; 5179286441Srpaulo uint8_t reserved[3]; 5180286441Srpaulo} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5181286441Srpaulo 5182286441Srpaulo/** 5183286441Srpaulo * struct iwm_mvm_mgmt_mcast_key_cmd 5184286441Srpaulo * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5185286441Srpaulo * @ctrl_flags: %iwm_sta_key_flag 5186286441Srpaulo * @IGTK: 5187286441Srpaulo * @K1: IGTK master key 5188286441Srpaulo * @K2: IGTK sub key 5189286441Srpaulo * @sta_id: station ID that support IGTK 5190286441Srpaulo * @key_id: 5191286441Srpaulo * @receive_seq_cnt: initial RSC/PN needed for replay check 5192286441Srpaulo */ 5193286441Srpaulostruct iwm_mvm_mgmt_mcast_key_cmd { 5194286441Srpaulo uint32_t ctrl_flags; 5195286441Srpaulo uint8_t IGTK[16]; 5196286441Srpaulo uint8_t K1[16]; 5197286441Srpaulo uint8_t K2[16]; 5198286441Srpaulo uint32_t key_id; 5199286441Srpaulo uint32_t sta_id; 5200286441Srpaulo uint64_t receive_seq_cnt; 5201286441Srpaulo} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5202286441Srpaulo 5203286441Srpaulostruct iwm_mvm_wep_key { 5204286441Srpaulo uint8_t key_index; 5205286441Srpaulo uint8_t key_offset; 5206286441Srpaulo uint16_t reserved1; 5207286441Srpaulo uint8_t key_size; 5208286441Srpaulo uint8_t reserved2[3]; 5209286441Srpaulo uint8_t key[16]; 5210286441Srpaulo} __packed; 5211286441Srpaulo 5212286441Srpaulostruct iwm_mvm_wep_key_cmd { 5213286441Srpaulo uint32_t mac_id_n_color; 5214286441Srpaulo uint8_t num_keys; 5215286441Srpaulo uint8_t decryption_type; 5216286441Srpaulo uint8_t flags; 5217286441Srpaulo uint8_t reserved; 5218286441Srpaulo struct iwm_mvm_wep_key wep_key[0]; 5219286441Srpaulo} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5220286441Srpaulo 5221286441Srpaulo 5222286441Srpaulo/* 5223286441Srpaulo * END mvm/fw-api-sta.h 5224286441Srpaulo */ 5225286441Srpaulo 5226286441Srpaulo/* 5227286441Srpaulo * Some cherry-picked definitions 5228286441Srpaulo */ 5229286441Srpaulo 5230286441Srpaulo#define IWM_FRAME_LIMIT 64 5231286441Srpaulo 5232286441Srpaulostruct iwm_cmd_header { 5233286441Srpaulo uint8_t code; 5234286441Srpaulo uint8_t flags; 5235286441Srpaulo uint8_t idx; 5236286441Srpaulo uint8_t qid; 5237286441Srpaulo} __packed; 5238286441Srpaulo 5239286441Srpauloenum iwm_power_scheme { 5240286441Srpaulo IWM_POWER_SCHEME_CAM = 1, 5241286441Srpaulo IWM_POWER_SCHEME_BPS, 5242286441Srpaulo IWM_POWER_SCHEME_LP 5243286441Srpaulo}; 5244286441Srpaulo 5245286441Srpaulo#define IWM_DEF_CMD_PAYLOAD_SIZE 320 5246301189Sadrian#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 5247286441Srpaulo#define IWM_CMD_FAILED_MSK 0x40 5248286441Srpaulo 5249286441Srpaulostruct iwm_device_cmd { 5250286441Srpaulo struct iwm_cmd_header hdr; 5251286441Srpaulo 5252286441Srpaulo uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 5253286441Srpaulo} __packed; 5254286441Srpaulo 5255286441Srpaulostruct iwm_rx_packet { 5256286441Srpaulo /* 5257286441Srpaulo * The first 4 bytes of the RX frame header contain both the RX frame 5258286441Srpaulo * size and some flags. 5259286441Srpaulo * Bit fields: 5260286441Srpaulo * 31: flag flush RB request 5261286441Srpaulo * 30: flag ignore TC (terminal counter) request 5262286441Srpaulo * 29: flag fast IRQ request 5263286441Srpaulo * 28-14: Reserved 5264286441Srpaulo * 13-00: RX frame size 5265286441Srpaulo */ 5266286441Srpaulo uint32_t len_n_flags; 5267286441Srpaulo struct iwm_cmd_header hdr; 5268286441Srpaulo uint8_t data[]; 5269286441Srpaulo} __packed; 5270286441Srpaulo 5271286441Srpaulo#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 5272286441Srpaulo 5273286441Srpaulostatic inline uint32_t 5274286441Srpauloiwm_rx_packet_len(const struct iwm_rx_packet *pkt) 5275286441Srpaulo{ 5276286441Srpaulo 5277286441Srpaulo return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 5278286441Srpaulo} 5279286441Srpaulo 5280286441Srpaulostatic inline uint32_t 5281286441Srpauloiwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 5282286441Srpaulo{ 5283286441Srpaulo 5284286441Srpaulo return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 5285286441Srpaulo} 5286286441Srpaulo 5287286441Srpaulo 5288286441Srpaulo#define IWM_MIN_DBM -100 5289286441Srpaulo#define IWM_MAX_DBM -33 /* realistic guess */ 5290286441Srpaulo 5291286441Srpaulo#define IWM_READ(sc, reg) \ 5292286441Srpaulo bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 5293286441Srpaulo 5294286441Srpaulo#define IWM_WRITE(sc, reg, val) \ 5295286441Srpaulo bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 5296286441Srpaulo 5297286441Srpaulo#define IWM_WRITE_1(sc, reg, val) \ 5298286441Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 5299286441Srpaulo 5300286441Srpaulo#define IWM_SETBITS(sc, reg, mask) \ 5301286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 5302286441Srpaulo 5303286441Srpaulo#define IWM_CLRBITS(sc, reg, mask) \ 5304286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 5305286441Srpaulo 5306286441Srpaulo#define IWM_BARRIER_WRITE(sc) \ 5307286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 5308286441Srpaulo BUS_SPACE_BARRIER_WRITE) 5309286441Srpaulo 5310286441Srpaulo#define IWM_BARRIER_READ_WRITE(sc) \ 5311286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 5312286441Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 5313286441Srpaulo 5314286441Srpaulo#define IWM_FW_VALID_TX_ANT(sc) \ 5315286441Srpaulo ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN) \ 5316286441Srpaulo >> IWM_FW_PHY_CFG_TX_CHAIN_POS) 5317286441Srpaulo#define IWM_FW_VALID_RX_ANT(sc) \ 5318286441Srpaulo ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RX_CHAIN) \ 5319286441Srpaulo >> IWM_FW_PHY_CFG_RX_CHAIN_POS) 5320286441Srpaulo 5321286441Srpaulo#endif /* __IF_IWM_REG_H__ */ 5322