1303628Ssbruno/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2286441Srpaulo/* $FreeBSD: stable/11/sys/dev/iwm/if_iwmreg.h 330446 2018-03-05 06:59:30Z eadler $ */ 3286441Srpaulo 4286441Srpaulo/****************************************************************************** 5286441Srpaulo * 6286441Srpaulo * This file is provided under a dual BSD/GPLv2 license. When using or 7286441Srpaulo * redistributing this file, you may do so under either license. 8286441Srpaulo * 9286441Srpaulo * GPL LICENSE SUMMARY 10286441Srpaulo * 11286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12286441Srpaulo * 13286441Srpaulo * This program is free software; you can redistribute it and/or modify 14286441Srpaulo * it under the terms of version 2 of the GNU General Public License as 15286441Srpaulo * published by the Free Software Foundation. 16286441Srpaulo * 17286441Srpaulo * This program is distributed in the hope that it will be useful, but 18286441Srpaulo * WITHOUT ANY WARRANTY; without even the implied warranty of 19286441Srpaulo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20286441Srpaulo * General Public License for more details. 21286441Srpaulo * 22286441Srpaulo * You should have received a copy of the GNU General Public License 23286441Srpaulo * along with this program; if not, write to the Free Software 24286441Srpaulo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25286441Srpaulo * USA 26286441Srpaulo * 27286441Srpaulo * The full GNU General Public License is included in this distribution 28286441Srpaulo * in the file called COPYING. 29286441Srpaulo * 30286441Srpaulo * Contact Information: 31286441Srpaulo * Intel Linux Wireless <ilw@linux.intel.com> 32286441Srpaulo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33286441Srpaulo * 34286441Srpaulo * BSD LICENSE 35286441Srpaulo * 36286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37286441Srpaulo * All rights reserved. 38286441Srpaulo * 39286441Srpaulo * Redistribution and use in source and binary forms, with or without 40286441Srpaulo * modification, are permitted provided that the following conditions 41286441Srpaulo * are met: 42286441Srpaulo * 43286441Srpaulo * * Redistributions of source code must retain the above copyright 44286441Srpaulo * notice, this list of conditions and the following disclaimer. 45286441Srpaulo * * Redistributions in binary form must reproduce the above copyright 46286441Srpaulo * notice, this list of conditions and the following disclaimer in 47286441Srpaulo * the documentation and/or other materials provided with the 48286441Srpaulo * distribution. 49286441Srpaulo * * Neither the name Intel Corporation nor the names of its 50286441Srpaulo * contributors may be used to endorse or promote products derived 51286441Srpaulo * from this software without specific prior written permission. 52286441Srpaulo * 53286441Srpaulo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54286441Srpaulo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55286441Srpaulo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56286441Srpaulo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57286441Srpaulo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58286441Srpaulo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59286441Srpaulo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60286441Srpaulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61286441Srpaulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62286441Srpaulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63286441Srpaulo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64286441Srpaulo * 65286441Srpaulo *****************************************************************************/ 66286441Srpaulo#ifndef __IF_IWM_REG_H__ 67286441Srpaulo#define __IF_IWM_REG_H__ 68286441Srpaulo 69286441Srpaulo#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70286441Srpaulo#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71286441Srpaulo 72286441Srpaulo/* 73286441Srpaulo * BEGIN iwl-csr.h 74286441Srpaulo */ 75286441Srpaulo 76286441Srpaulo/* 77286441Srpaulo * CSR (control and status registers) 78286441Srpaulo * 79286441Srpaulo * CSR registers are mapped directly into PCI bus space, and are accessible 80286441Srpaulo * whenever platform supplies power to device, even when device is in 81286441Srpaulo * low power states due to driver-invoked device resets 82286441Srpaulo * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83286441Srpaulo * 84286441Srpaulo * Use iwl_write32() and iwl_read32() family to access these registers; 85286441Srpaulo * these provide simple PCI bus access, without waking up the MAC. 86286441Srpaulo * Do not use iwl_write_direct32() family for these registers; 87286441Srpaulo * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88286441Srpaulo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89286441Srpaulo * the CSR registers. 90286441Srpaulo * 91286441Srpaulo * NOTE: Device does need to be awake in order to read this memory 92286441Srpaulo * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93286441Srpaulo */ 94286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95286441Srpaulo#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96286441Srpaulo#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97286441Srpaulo#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98286441Srpaulo#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99286441Srpaulo#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100286441Srpaulo#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101286441Srpaulo#define IWM_CSR_GP_CNTRL (0x024) 102286441Srpaulo 103286441Srpaulo/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104286441Srpaulo#define IWM_CSR_INT_PERIODIC_REG (0x005) 105286441Srpaulo 106286441Srpaulo/* 107286441Srpaulo * Hardware revision info 108286441Srpaulo * Bit fields: 109286441Srpaulo * 31-16: Reserved 110286441Srpaulo * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111286441Srpaulo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112286441Srpaulo * 1-0: "Dash" (-) value, as in A-1, etc. 113286441Srpaulo */ 114286441Srpaulo#define IWM_CSR_HW_REV (0x028) 115286441Srpaulo 116286441Srpaulo/* 117286441Srpaulo * EEPROM and OTP (one-time-programmable) memory reads 118286441Srpaulo * 119286441Srpaulo * NOTE: Device must be awake, initialized via apm_ops.init(), 120286441Srpaulo * in order to read. 121286441Srpaulo */ 122286441Srpaulo#define IWM_CSR_EEPROM_REG (0x02c) 123286441Srpaulo#define IWM_CSR_EEPROM_GP (0x030) 124286441Srpaulo#define IWM_CSR_OTP_GP_REG (0x034) 125286441Srpaulo 126286441Srpaulo#define IWM_CSR_GIO_REG (0x03C) 127286441Srpaulo#define IWM_CSR_GP_UCODE_REG (0x048) 128286441Srpaulo#define IWM_CSR_GP_DRIVER_REG (0x050) 129286441Srpaulo 130286441Srpaulo/* 131286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox registers. 132286441Srpaulo * SET/CLR registers set/clear bit(s) if "1" is written. 133286441Srpaulo */ 134286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137286441Srpaulo#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138286441Srpaulo 139303628Ssbruno#define IWM_CSR_MBOX_SET_REG (0x088) 140303628Ssbruno#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141303628Ssbruno 142286441Srpaulo#define IWM_CSR_LED_REG (0x094) 143286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144286441Srpaulo#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145286441Srpaulo 146286441Srpaulo 147286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 148286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149286441Srpaulo 150286441Srpaulo/* Analog phase-lock-loop configuration */ 151286441Srpaulo#define IWM_CSR_ANA_PLL_CFG (0x20c) 152286441Srpaulo 153286441Srpaulo/* 154286441Srpaulo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155286441Srpaulo * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156286441Srpaulo * See also IWM_CSR_HW_REV register. 157286441Srpaulo * Bit fields: 158286441Srpaulo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159286441Srpaulo * 1-0: "Dash" (-) value, as in C-1, etc. 160286441Srpaulo */ 161286441Srpaulo#define IWM_CSR_HW_REV_WA_REG (0x22C) 162286441Srpaulo 163286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164286441Srpaulo#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165286441Srpaulo 166286441Srpaulo/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175286441Srpaulo 176286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182286441Srpaulo 183286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188303628Ssbruno#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189303628Ssbruno#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190286441Srpaulo 191286441Srpaulo#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192286441Srpaulo#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193286441Srpaulo 194286441Srpaulo/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195286441Srpaulo * acknowledged (reset) by host writing "1" to flagged bits. */ 196286441Srpaulo#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197286441Srpaulo#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198286441Srpaulo#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199286441Srpaulo#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200286441Srpaulo#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201286441Srpaulo#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202286441Srpaulo#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203286441Srpaulo#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204286441Srpaulo#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205286441Srpaulo#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206286441Srpaulo#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207286441Srpaulo 208286441Srpaulo#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209286441Srpaulo IWM_CSR_INT_BIT_HW_ERR | \ 210286441Srpaulo IWM_CSR_INT_BIT_FH_TX | \ 211286441Srpaulo IWM_CSR_INT_BIT_SW_ERR | \ 212286441Srpaulo IWM_CSR_INT_BIT_RF_KILL | \ 213286441Srpaulo IWM_CSR_INT_BIT_SW_RX | \ 214286441Srpaulo IWM_CSR_INT_BIT_WAKEUP | \ 215286441Srpaulo IWM_CSR_INT_BIT_ALIVE | \ 216286441Srpaulo IWM_CSR_INT_BIT_RX_PERIODIC) 217286441Srpaulo 218286441Srpaulo/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219286441Srpaulo#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220286441Srpaulo#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225286441Srpaulo 226286441Srpaulo#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL0) 229286441Srpaulo 230286441Srpaulo#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231286441Srpaulo IWM_CSR_FH_INT_BIT_TX_CHNL0) 232286441Srpaulo 233286441Srpaulo/* GPIO */ 234286441Srpaulo#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237286441Srpaulo 238286441Srpaulo/* RESET */ 239286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244286441Srpaulo#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245286441Srpaulo 246286441Srpaulo/* 247286441Srpaulo * GP (general purpose) CONTROL REGISTER 248286441Srpaulo * Bit fields: 249286441Srpaulo * 27: HW_RF_KILL_SW 250286441Srpaulo * Indicates state of (platform's) hardware RF-Kill switch 251286441Srpaulo * 26-24: POWER_SAVE_TYPE 252286441Srpaulo * Indicates current power-saving mode: 253286441Srpaulo * 000 -- No power saving 254286441Srpaulo * 001 -- MAC power-down 255286441Srpaulo * 010 -- PHY (radio) power-down 256286441Srpaulo * 011 -- Error 257286441Srpaulo * 9-6: SYS_CONFIG 258286441Srpaulo * Indicates current system configuration, reflecting pins on chip 259286441Srpaulo * as forced high/low by device circuit board. 260286441Srpaulo * 4: GOING_TO_SLEEP 261286441Srpaulo * Indicates MAC is entering a power-saving sleep power-down. 262286441Srpaulo * Not a good time to access device-internal resources. 263286441Srpaulo * 3: MAC_ACCESS_REQ 264286441Srpaulo * Host sets this to request and maintain MAC wakeup, to allow host 265286441Srpaulo * access to device-internal resources. Host must wait for 266286441Srpaulo * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267286441Srpaulo * device registers. 268286441Srpaulo * 2: INIT_DONE 269286441Srpaulo * Host sets this to put device into fully operational D0 power mode. 270286441Srpaulo * Host resets this after SW_RESET to put device into low power mode. 271286441Srpaulo * 0: MAC_CLOCK_READY 272286441Srpaulo * Indicates MAC (ucode processor, etc.) is powered up and can run. 273286441Srpaulo * Internal resources are accessible. 274286441Srpaulo * NOTE: This does not indicate that the processor is actually running. 275286441Srpaulo * NOTE: This does not indicate that device has completed 276286441Srpaulo * init or post-power-down restore of internal SRAM memory. 277286441Srpaulo * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278286441Srpaulo * SRAM is restored and uCode is in normal operation mode. 279286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280286441Srpaulo * do not need to save/restore it. 281286441Srpaulo * NOTE: After device reset, this bit remains "0" until host sets 282286441Srpaulo * INIT_DONE 283286441Srpaulo */ 284286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288286441Srpaulo 289286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290286441Srpaulo 291286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294286441Srpaulo 295286441Srpaulo 296286441Srpaulo/* HW REV */ 297286441Srpaulo#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298286441Srpaulo#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299286441Srpaulo 300330162Seadler/** 301330162Seadler * hw_rev values 302330162Seadler */ 303330162Seadlerenum { 304330162Seadler IWM_SILICON_A_STEP = 0, 305330162Seadler IWM_SILICON_B_STEP, 306330162Seadler IWM_SILICON_C_STEP, 307330162Seadler}; 308330162Seadler 309330162Seadler 310286441Srpaulo#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315286441Srpaulo#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324286441Srpaulo#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325286441Srpaulo#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326303628Ssbruno#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327286441Srpaulo#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328286441Srpaulo 329286441Srpaulo/* EEPROM REG */ 330286441Srpaulo#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331286441Srpaulo#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334286441Srpaulo 335286441Srpaulo/* EEPROM GP */ 336286441Srpaulo#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337286441Srpaulo#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342286441Srpaulo 343286441Srpaulo/* One-time-programmable memory general purpose reg */ 344286441Srpaulo#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345286441Srpaulo#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348286441Srpaulo 349286441Srpaulo/* GP REG */ 350286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351286441Srpaulo#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352286441Srpaulo#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353286441Srpaulo#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355286441Srpaulo 356286441Srpaulo 357286441Srpaulo/* CSR GIO */ 358286441Srpaulo#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359286441Srpaulo 360286441Srpaulo/* 361286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox register 1 362286441Srpaulo * Host driver and uCode write and/or read this register to communicate with 363286441Srpaulo * each other. 364286441Srpaulo * Bit fields: 365286441Srpaulo * 4: UCODE_DISABLE 366286441Srpaulo * Host sets this to request permanent halt of uCode, same as 367286441Srpaulo * sending CARD_STATE command with "halt" bit set. 368286441Srpaulo * 3: CT_KILL_EXIT 369286441Srpaulo * Host sets this to request exit from CT_KILL state, i.e. host thinks 370286441Srpaulo * device temperature is low enough to continue normal operation. 371286441Srpaulo * 2: CMD_BLOCKED 372286441Srpaulo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373286441Srpaulo * to release uCode to clear all Tx and command queues, enter 374286441Srpaulo * unassociated mode, and power down. 375286441Srpaulo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376286441Srpaulo * 1: SW_BIT_RFKILL 377286441Srpaulo * Host sets this when issuing CARD_STATE command to request 378286441Srpaulo * device sleep. 379286441Srpaulo * 0: MAC_SLEEP 380286441Srpaulo * uCode sets this when preparing a power-saving power-down. 381286441Srpaulo * uCode resets this when power-up is complete and SRAM is sane. 382286441Srpaulo * NOTE: device saves internal SRAM data to host when powering down, 383286441Srpaulo * and must restore this data after powering back up. 384286441Srpaulo * MAC_SLEEP is the best indication that restore is complete. 385286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386286441Srpaulo * do not need to save/restore it. 387286441Srpaulo */ 388286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389286441Srpaulo#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393286441Srpaulo 394286441Srpaulo/* GP Driver */ 395286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401286441Srpaulo 402286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403286441Srpaulo 404286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 405286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407286441Srpaulo 408286441Srpaulo/* LED */ 409286441Srpaulo#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410286441Srpaulo#define IWM_CSR_LED_REG_TURN_ON (0x60) 411286441Srpaulo#define IWM_CSR_LED_REG_TURN_OFF (0x20) 412286441Srpaulo 413286441Srpaulo/* ANA_PLL */ 414286441Srpaulo#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415286441Srpaulo 416286441Srpaulo/* HPET MEM debug */ 417286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418286441Srpaulo 419286441Srpaulo/* DRAM INT TABLE */ 420286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421303628Ssbruno#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422286441Srpaulo#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423286441Srpaulo 424286441Srpaulo/* SECURE boot registers */ 425286441Srpaulo#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426286441Srpauloenum iwm_secure_boot_config_reg { 427286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429286441Srpaulo}; 430286441Srpaulo 431286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433286441Srpauloenum iwm_secure_boot_status_reg { 434286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439286441Srpaulo}; 440286441Srpaulo 441303628Ssbruno#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442303628Ssbruno#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 443286441Srpaulo 444303628Ssbruno#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445303628Ssbruno#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446286441Srpaulo 447303628Ssbruno#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 448303628Ssbruno#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 449303628Ssbruno 450286441Srpaulo#define IWM_CSR_SECURE_TIME_OUT (100) 451286441Srpaulo 452303628Ssbruno/* extended range in FW SRAM */ 453303628Ssbruno#define IWM_FW_MEM_EXTENDED_START 0x40000 454303628Ssbruno#define IWM_FW_MEM_EXTENDED_END 0x57FFF 455303628Ssbruno 456303628Ssbruno/* FW chicken bits */ 457303628Ssbruno#define IWM_LMPM_CHICK 0xa01ff8 458303628Ssbruno#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 459303628Ssbruno 460286441Srpaulo#define IWM_FH_TCSR_0_REG0 (0x1D00) 461286441Srpaulo 462286441Srpaulo/* 463286441Srpaulo * HBUS (Host-side Bus) 464286441Srpaulo * 465286441Srpaulo * HBUS registers are mapped directly into PCI bus space, but are used 466286441Srpaulo * to indirectly access device's internal memory or registers that 467286441Srpaulo * may be powered-down. 468286441Srpaulo * 469286441Srpaulo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 470286441Srpaulo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 471286441Srpaulo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 472286441Srpaulo * internal resources. 473286441Srpaulo * 474286441Srpaulo * Do not use iwl_write32()/iwl_read32() family to access these registers; 475286441Srpaulo * these provide only simple PCI bus access, without waking up the MAC. 476286441Srpaulo */ 477286441Srpaulo#define IWM_HBUS_BASE (0x400) 478286441Srpaulo 479286441Srpaulo/* 480286441Srpaulo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 481286441Srpaulo * structures, error log, event log, verifying uCode load). 482286441Srpaulo * First write to address register, then read from or write to data register 483286441Srpaulo * to complete the job. Once the address register is set up, accesses to 484286441Srpaulo * data registers auto-increment the address by one dword. 485286441Srpaulo * Bit usage for address registers (read or write): 486286441Srpaulo * 0-31: memory address within device 487286441Srpaulo */ 488286441Srpaulo#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 489286441Srpaulo#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 490286441Srpaulo#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 491286441Srpaulo#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 492286441Srpaulo 493286441Srpaulo/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 494286441Srpaulo#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 495286441Srpaulo#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 496286441Srpaulo 497286441Srpaulo/* 498286441Srpaulo * Registers for accessing device's internal peripheral registers 499286441Srpaulo * (e.g. SCD, BSM, etc.). First write to address register, 500286441Srpaulo * then read from or write to data register to complete the job. 501286441Srpaulo * Bit usage for address registers (read or write): 502286441Srpaulo * 0-15: register address (offset) within device 503286441Srpaulo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 504286441Srpaulo */ 505286441Srpaulo#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 506286441Srpaulo#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 507286441Srpaulo#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 508286441Srpaulo#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 509286441Srpaulo 510303628Ssbruno/* enable the ID buf for read */ 511303628Ssbruno#define IWM_WFPM_PS_CTL_CLR 0xa0300c 512303628Ssbruno#define IWM_WFMP_MAC_ADDR_0 0xa03080 513303628Ssbruno#define IWM_WFMP_MAC_ADDR_1 0xa03084 514303628Ssbruno#define IWM_LMPM_PMG_EN 0xa01cec 515303628Ssbruno#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 516303628Ssbruno#define IWM_RFIC_REG_RD 0xad0470 517303628Ssbruno#define IWM_WFPM_CTRL_REG 0xa03030 518303628Ssbruno#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 519303628Ssbruno#define IWM_ENABLE_WFPM 0x80000000 520303628Ssbruno 521303628Ssbruno#define IWM_AUX_MISC_REG 0xa200b0 522303628Ssbruno#define IWM_HW_STEP_LOCATION_BITS 24 523303628Ssbruno 524303628Ssbruno#define IWM_AUX_MISC_MASTER1_EN 0xa20818 525303628Ssbruno#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 526303628Ssbruno#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 527303628Ssbruno#define IWM_RSA_ENABLE 0xa24b08 528303628Ssbruno#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 529303628Ssbruno#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 530303628Ssbruno#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 531303628Ssbruno#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 532303628Ssbruno#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 533303628Ssbruno#define IWM_SB_CPU_1_STATUS 0xa01e30 534303628Ssbruno#define IWM_SB_CPU_2_STATUS 0Xa01e34 535303628Ssbruno 536286441Srpaulo/* Used to enable DBGM */ 537286441Srpaulo#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 538286441Srpaulo 539286441Srpaulo/* 540286441Srpaulo * Per-Tx-queue write pointer (index, really!) 541286441Srpaulo * Indicates index to next TFD that driver will fill (1 past latest filled). 542286441Srpaulo * Bit usage: 543286441Srpaulo * 0-7: queue write index 544286441Srpaulo * 11-8: queue selector 545286441Srpaulo */ 546286441Srpaulo#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 547286441Srpaulo 548286441Srpaulo/********************************************************** 549286441Srpaulo * CSR values 550286441Srpaulo **********************************************************/ 551286441Srpaulo /* 552286441Srpaulo * host interrupt timeout value 553286441Srpaulo * used with setting interrupt coalescing timer 554286441Srpaulo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 555286441Srpaulo * 556286441Srpaulo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 557286441Srpaulo */ 558286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 559286441Srpaulo#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 560286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 561286441Srpaulo#define IWM_HOST_INT_OPER_MODE (1 << 31) 562286441Srpaulo 563286441Srpaulo/***************************************************************************** 564286441Srpaulo * 7000/3000 series SHR DTS addresses * 565286441Srpaulo *****************************************************************************/ 566286441Srpaulo 567286441Srpaulo/* Diode Results Register Structure: */ 568286441Srpauloenum iwm_dtd_diode_reg { 569286441Srpaulo IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 570286441Srpaulo IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 571286441Srpaulo IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 572286441Srpaulo IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 573286441Srpaulo IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 574286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 575286441Srpaulo/* Those are the masks INSIDE the flags bit-field: */ 576286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 577286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 578286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 579286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 580286441Srpaulo}; 581286441Srpaulo 582286441Srpaulo/* 583286441Srpaulo * END iwl-csr.h 584286441Srpaulo */ 585286441Srpaulo 586286441Srpaulo/* 587286441Srpaulo * BEGIN iwl-fw.h 588286441Srpaulo */ 589286441Srpaulo 590286441Srpaulo/** 591301192Sadrian * enum iwm_ucode_tlv_flag - ucode API flags 592286441Srpaulo * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 593286441Srpaulo * was a separate TLV but moved here to save space. 594286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 595286441Srpaulo * treats good CRC threshold as a boolean 596286441Srpaulo * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 597286441Srpaulo * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 598286441Srpaulo * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 599286441Srpaulo * offload profile config command. 600286441Srpaulo * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 601286441Srpaulo * (rather than two) IPv6 addresses 602286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 603286441Srpaulo * from the probe request template. 604286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 605286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 606303628Ssbruno * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 607303628Ssbruno * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 608286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 609303628Ssbruno * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 610286441Srpaulo */ 611286441Srpauloenum iwm_ucode_tlv_flag { 612286441Srpaulo IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 613286441Srpaulo IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 614286441Srpaulo IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 615286441Srpaulo IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 616286441Srpaulo IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 617286441Srpaulo IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 618286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 619286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 620286441Srpaulo IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 621303628Ssbruno IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 622286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 623303628Ssbruno IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 624286441Srpaulo}; 625286441Srpaulo 626303628Ssbruno#define IWM_UCODE_TLV_FLAG_BITS \ 627303628Ssbruno "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 628303628SsbrunoY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 629303628SsbrunoL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 630303628SsbrunoP2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 631303628Ssbruno 632303628Ssbruno/** 633303628Ssbruno * enum iwm_ucode_tlv_api - ucode api 634303628Ssbruno * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 635303628Ssbruno * longer than the passive one, which is essential for fragmented scan. 636303628Ssbruno * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 637303628Ssbruno * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 638303628Ssbruno * 639303628Ssbruno * @IWM_NUM_UCODE_TLV_API: number of bits used 640303628Ssbruno */ 641303628Ssbrunoenum iwm_ucode_tlv_api { 642330207Seadler IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 643330207Seadler IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 644330207Seadler IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 645303628Ssbruno 646303628Ssbruno IWM_NUM_UCODE_TLV_API = 32 647303628Ssbruno}; 648303628Ssbruno 649303628Ssbruno#define IWM_UCODE_TLV_API_BITS \ 650303628Ssbruno "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 651303628Ssbruno 652303628Ssbruno/** 653303628Ssbruno * enum iwm_ucode_tlv_capa - ucode capabilities 654303628Ssbruno * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 655303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 656303628Ssbruno * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 657303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 658303628Ssbruno * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 659303628Ssbruno * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 660303628Ssbruno * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 661303628Ssbruno * tx power value into TPC Report action frame and Link Measurement Report 662303628Ssbruno * action frame 663303628Ssbruno * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 664303628Ssbruno * channel in DS parameter set element in probe requests. 665303628Ssbruno * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 666303628Ssbruno * probe requests. 667303628Ssbruno * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 668303628Ssbruno * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 669303628Ssbruno * which also implies support for the scheduler configuration command 670303628Ssbruno * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 671303628Ssbruno * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 672303628Ssbruno * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 673303628Ssbruno * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 674303628Ssbruno * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 675303628Ssbruno * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 676303628Ssbruno * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 677303628Ssbruno * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 678303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 679303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 680303628Ssbruno * sources for the MCC. This TLV bit is a future replacement to 681303628Ssbruno * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 682303628Ssbruno * is supported. 683303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 684303628Ssbruno * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 685303628Ssbruno * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 686303628Ssbruno * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 687303628Ssbruno * 0=no support) 688303628Ssbruno * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 689303628Ssbruno * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 690303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 691303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 692303628Ssbruno * antenna the beacon should be transmitted 693303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 694303628Ssbruno * from AP and will send it upon d0i3 exit. 695303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 696303628Ssbruno * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 697303628Ssbruno * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 698303628Ssbruno * thresholds reporting 699303628Ssbruno * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 700303628Ssbruno * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 701303628Ssbruno * regular image. 702303628Ssbruno * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 703303628Ssbruno * memory addresses from the firmware. 704303628Ssbruno * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 705303628Ssbruno * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 706303628Ssbruno * 0=no support) 707303628Ssbruno * 708303628Ssbruno * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 709303628Ssbruno */ 710303628Ssbrunoenum iwm_ucode_tlv_capa { 711303628Ssbruno IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 712303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 713303628Ssbruno IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 714303628Ssbruno IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 715303628Ssbruno IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 716303628Ssbruno IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 717303628Ssbruno IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 718303628Ssbruno IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 719303628Ssbruno IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 720303628Ssbruno IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 721303628Ssbruno IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 722303628Ssbruno IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 723303628Ssbruno IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 724303628Ssbruno IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 725303628Ssbruno IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 726303628Ssbruno IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 727303628Ssbruno IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 728303628Ssbruno IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 729303628Ssbruno IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 730303628Ssbruno IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 731303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 732303628Ssbruno IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 733303628Ssbruno IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 734303628Ssbruno IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 735303628Ssbruno IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 736303628Ssbruno IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 737303628Ssbruno IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 738303628Ssbruno IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 739303628Ssbruno IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 740303628Ssbruno IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 741303628Ssbruno IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 742303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 743303628Ssbruno IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 744303628Ssbruno IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 745303628Ssbruno IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 746303628Ssbruno IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 747303628Ssbruno IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 748303628Ssbruno IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 749303628Ssbruno IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 750303628Ssbruno 751303628Ssbruno IWM_NUM_UCODE_TLV_CAPA = 128 752303628Ssbruno}; 753303628Ssbruno 754286441Srpaulo/* The default calibrate table size if not specified by firmware file */ 755286441Srpaulo#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 756286441Srpaulo#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 757286441Srpaulo#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 758286441Srpaulo 759286441Srpaulo/* The default max probe length if not specified by the firmware file */ 760286441Srpaulo#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 761286441Srpaulo 762286441Srpaulo/* 763286441Srpaulo * enumeration of ucode section. 764286441Srpaulo * This enumeration is used directly for older firmware (before 16.0). 765286441Srpaulo * For new firmware, there can be up to 4 sections (see below) but the 766286441Srpaulo * first one packaged into the firmware file is the DATA section and 767286441Srpaulo * some debugging code accesses that. 768286441Srpaulo */ 769286441Srpauloenum iwm_ucode_sec { 770286441Srpaulo IWM_UCODE_SECTION_DATA, 771286441Srpaulo IWM_UCODE_SECTION_INST, 772286441Srpaulo}; 773286441Srpaulo/* 774286441Srpaulo * For 16.0 uCode and above, there is no differentiation between sections, 775286441Srpaulo * just an offset to the HW address. 776286441Srpaulo */ 777303628Ssbruno#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 778303628Ssbruno#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 779286441Srpaulo 780286441Srpaulo/* uCode version contains 4 values: Major/Minor/API/Serial */ 781286441Srpaulo#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 782286441Srpaulo#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 783286441Srpaulo#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 784286441Srpaulo#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 785286441Srpaulo 786286441Srpaulo/* 787286441Srpaulo * Calibration control struct. 788286441Srpaulo * Sent as part of the phy configuration command. 789286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 790286441Srpaulo * flow triggers. 791286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 792286441Srpaulo * event triggers. 793286441Srpaulo */ 794286441Srpaulostruct iwm_tlv_calib_ctrl { 795286441Srpaulo uint32_t flow_trigger; 796286441Srpaulo uint32_t event_trigger; 797286441Srpaulo} __packed; 798286441Srpaulo 799286441Srpauloenum iwm_fw_phy_cfg { 800286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 801286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 802286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 803286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 804286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 805286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 806286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 807286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 808286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 809286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 810286441Srpaulo}; 811286441Srpaulo 812286441Srpaulo#define IWM_UCODE_MAX_CS 1 813286441Srpaulo 814286441Srpaulo/** 815286441Srpaulo * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 816286441Srpaulo * @cipher: a cipher suite selector 817286441Srpaulo * @flags: cipher scheme flags (currently reserved for a future use) 818286441Srpaulo * @hdr_len: a size of MPDU security header 819286441Srpaulo * @pn_len: a size of PN 820286441Srpaulo * @pn_off: an offset of pn from the beginning of the security header 821286441Srpaulo * @key_idx_off: an offset of key index byte in the security header 822286441Srpaulo * @key_idx_mask: a bit mask of key_idx bits 823286441Srpaulo * @key_idx_shift: bit shift needed to get key_idx 824286441Srpaulo * @mic_len: mic length in bytes 825286441Srpaulo * @hw_cipher: a HW cipher index used in host commands 826286441Srpaulo */ 827286441Srpaulostruct iwm_fw_cipher_scheme { 828286441Srpaulo uint32_t cipher; 829286441Srpaulo uint8_t flags; 830286441Srpaulo uint8_t hdr_len; 831286441Srpaulo uint8_t pn_len; 832286441Srpaulo uint8_t pn_off; 833286441Srpaulo uint8_t key_idx_off; 834286441Srpaulo uint8_t key_idx_mask; 835286441Srpaulo uint8_t key_idx_shift; 836286441Srpaulo uint8_t mic_len; 837286441Srpaulo uint8_t hw_cipher; 838286441Srpaulo} __packed; 839286441Srpaulo 840286441Srpaulo/** 841286441Srpaulo * struct iwm_fw_cscheme_list - a cipher scheme list 842286441Srpaulo * @size: a number of entries 843286441Srpaulo * @cs: cipher scheme entries 844286441Srpaulo */ 845286441Srpaulostruct iwm_fw_cscheme_list { 846286441Srpaulo uint8_t size; 847286441Srpaulo struct iwm_fw_cipher_scheme cs[]; 848286441Srpaulo} __packed; 849286441Srpaulo 850286441Srpaulo/* 851286441Srpaulo * END iwl-fw.h 852286441Srpaulo */ 853286441Srpaulo 854286441Srpaulo/* 855286441Srpaulo * BEGIN iwl-fw-file.h 856286441Srpaulo */ 857286441Srpaulo 858286441Srpaulo/* v1/v2 uCode file layout */ 859286441Srpaulostruct iwm_ucode_header { 860286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 861286441Srpaulo union { 862286441Srpaulo struct { 863286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 864286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 865286441Srpaulo uint32_t init_size; /* bytes of init code */ 866286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 867286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 868286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 869286441Srpaulo } v1; 870286441Srpaulo struct { 871286441Srpaulo uint32_t build; /* build number */ 872286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 873286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 874286441Srpaulo uint32_t init_size; /* bytes of init code */ 875286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 876286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 877286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 878286441Srpaulo } v2; 879286441Srpaulo } u; 880286441Srpaulo}; 881286441Srpaulo 882286441Srpaulo/* 883286441Srpaulo * new TLV uCode file layout 884286441Srpaulo * 885286441Srpaulo * The new TLV file format contains TLVs, that each specify 886286441Srpaulo * some piece of data. 887286441Srpaulo */ 888286441Srpaulo 889286441Srpauloenum iwm_ucode_tlv_type { 890286441Srpaulo IWM_UCODE_TLV_INVALID = 0, /* unused */ 891286441Srpaulo IWM_UCODE_TLV_INST = 1, 892286441Srpaulo IWM_UCODE_TLV_DATA = 2, 893286441Srpaulo IWM_UCODE_TLV_INIT = 3, 894286441Srpaulo IWM_UCODE_TLV_INIT_DATA = 4, 895286441Srpaulo IWM_UCODE_TLV_BOOT = 5, 896286441Srpaulo IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 897286441Srpaulo IWM_UCODE_TLV_PAN = 7, 898286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 899286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 900286441Srpaulo IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 901286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 902286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 903286441Srpaulo IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 904286441Srpaulo IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 905286441Srpaulo IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 906286441Srpaulo IWM_UCODE_TLV_WOWLAN_INST = 16, 907286441Srpaulo IWM_UCODE_TLV_WOWLAN_DATA = 17, 908286441Srpaulo IWM_UCODE_TLV_FLAGS = 18, 909286441Srpaulo IWM_UCODE_TLV_SEC_RT = 19, 910286441Srpaulo IWM_UCODE_TLV_SEC_INIT = 20, 911286441Srpaulo IWM_UCODE_TLV_SEC_WOWLAN = 21, 912286441Srpaulo IWM_UCODE_TLV_DEF_CALIB = 22, 913286441Srpaulo IWM_UCODE_TLV_PHY_SKU = 23, 914286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_RT = 24, 915286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 916286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 917286441Srpaulo IWM_UCODE_TLV_NUM_OF_CPU = 27, 918286441Srpaulo IWM_UCODE_TLV_CSCHEME = 28, 919286441Srpaulo 920286441Srpaulo /* 921286441Srpaulo * Following two are not in our base tag, but allow 922286441Srpaulo * handling ucode version 9. 923286441Srpaulo */ 924286441Srpaulo IWM_UCODE_TLV_API_CHANGES_SET = 29, 925303628Ssbruno IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 926303628Ssbruno 927303628Ssbruno IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 928303628Ssbruno IWM_UCODE_TLV_PAGING = 32, 929303628Ssbruno IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 930303628Ssbruno IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 931303628Ssbruno IWM_UCODE_TLV_FW_VERSION = 36, 932303628Ssbruno IWM_UCODE_TLV_FW_DBG_DEST = 38, 933303628Ssbruno IWM_UCODE_TLV_FW_DBG_CONF = 39, 934303628Ssbruno IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 935303628Ssbruno IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 936330179Seadler IWM_UCODE_TLV_FW_MEM_SEG = 51, 937286441Srpaulo}; 938286441Srpaulo 939286441Srpaulostruct iwm_ucode_tlv { 940286441Srpaulo uint32_t type; /* see above */ 941286441Srpaulo uint32_t length; /* not including type/length fields */ 942286441Srpaulo uint8_t data[0]; 943286441Srpaulo}; 944286441Srpaulo 945303628Ssbrunostruct iwm_ucode_api { 946303628Ssbruno uint32_t api_index; 947303628Ssbruno uint32_t api_flags; 948303628Ssbruno} __packed; 949303628Ssbruno 950303628Ssbrunostruct iwm_ucode_capa { 951303628Ssbruno uint32_t api_index; 952303628Ssbruno uint32_t api_capa; 953303628Ssbruno} __packed; 954303628Ssbruno 955286441Srpaulo#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 956286441Srpaulo 957286441Srpaulostruct iwm_tlv_ucode_header { 958286441Srpaulo /* 959286441Srpaulo * The TLV style ucode header is distinguished from 960286441Srpaulo * the v1/v2 style header by first four bytes being 961286441Srpaulo * zero, as such is an invalid combination of 962286441Srpaulo * major/minor/API/serial versions. 963286441Srpaulo */ 964286441Srpaulo uint32_t zero; 965286441Srpaulo uint32_t magic; 966286441Srpaulo uint8_t human_readable[64]; 967286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 968286441Srpaulo uint32_t build; 969286441Srpaulo uint64_t ignore; 970286441Srpaulo /* 971286441Srpaulo * The data contained herein has a TLV layout, 972286441Srpaulo * see above for the TLV header and types. 973286441Srpaulo * Note that each TLV is padded to a length 974286441Srpaulo * that is a multiple of 4 for alignment. 975286441Srpaulo */ 976286441Srpaulo uint8_t data[0]; 977286441Srpaulo}; 978286441Srpaulo 979286441Srpaulo/* 980286441Srpaulo * END iwl-fw-file.h 981286441Srpaulo */ 982286441Srpaulo 983286441Srpaulo/* 984286441Srpaulo * BEGIN iwl-prph.h 985286441Srpaulo */ 986286441Srpaulo 987286441Srpaulo/* 988286441Srpaulo * Registers in this file are internal, not PCI bus memory mapped. 989286441Srpaulo * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 990286441Srpaulo */ 991286441Srpaulo#define IWM_PRPH_BASE (0x00000) 992286441Srpaulo#define IWM_PRPH_END (0xFFFFF) 993286441Srpaulo 994286441Srpaulo/* APMG (power management) constants */ 995286441Srpaulo#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 996286441Srpaulo#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 997286441Srpaulo#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 998286441Srpaulo#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 999286441Srpaulo#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1000286441Srpaulo#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1001286441Srpaulo#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1002286441Srpaulo#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1003286441Srpaulo#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1004286441Srpaulo#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1005286441Srpaulo#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1006286441Srpaulo 1007286441Srpaulo#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1008286441Srpaulo#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1009286441Srpaulo#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1010286441Srpaulo 1011286441Srpaulo#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1012286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1013286441Srpaulo#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1014286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1015286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1016286441Srpaulo#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1017286441Srpaulo#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1018286441Srpaulo 1019286441Srpaulo#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1020286441Srpaulo 1021286441Srpaulo#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1022286441Srpaulo 1023286441Srpaulo/* Device system time */ 1024286441Srpaulo#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1025286441Srpaulo 1026286441Srpaulo/* Device NMI register */ 1027303628Ssbruno#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1028303628Ssbruno#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1029303628Ssbruno#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1030303628Ssbruno#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1031303628Ssbruno#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1032286441Srpaulo 1033303628Ssbruno/* 1034303628Ssbruno * Device reset for family 8000 1035303628Ssbruno * write to bit 24 in order to reset the CPU 1036303628Ssbruno */ 1037303628Ssbruno#define IWM_RELEASE_CPU_RESET 0x300c 1038303628Ssbruno#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1039303628Ssbruno 1040303628Ssbruno 1041286441Srpaulo/***************************************************************************** 1042286441Srpaulo * 7000/3000 series SHR DTS addresses * 1043286441Srpaulo *****************************************************************************/ 1044286441Srpaulo 1045286441Srpaulo#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1046286441Srpaulo#define IWM_DTSC_CFG_MODE (0x00a10604) 1047286441Srpaulo#define IWM_DTSC_VREF_AVG (0x00a10648) 1048286441Srpaulo#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1049286441Srpaulo#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1050286441Srpaulo#define IWM_DTSC_PTAT_AVG (0x00a10650) 1051286441Srpaulo 1052286441Srpaulo 1053286441Srpaulo/** 1054286441Srpaulo * Tx Scheduler 1055286441Srpaulo * 1056286441Srpaulo * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1057286441Srpaulo * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1058286441Srpaulo * host DRAM. It steers each frame's Tx command (which contains the frame 1059286441Srpaulo * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1060286441Srpaulo * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1061286441Srpaulo * but one DMA channel may take input from several queues. 1062286441Srpaulo * 1063286441Srpaulo * Tx DMA FIFOs have dedicated purposes. 1064286441Srpaulo * 1065286441Srpaulo * For 5000 series and up, they are used differently 1066286441Srpaulo * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1067286441Srpaulo * 1068286441Srpaulo * 0 -- EDCA BK (background) frames, lowest priority 1069286441Srpaulo * 1 -- EDCA BE (best effort) frames, normal priority 1070286441Srpaulo * 2 -- EDCA VI (video) frames, higher priority 1071286441Srpaulo * 3 -- EDCA VO (voice) and management frames, highest priority 1072286441Srpaulo * 4 -- unused 1073286441Srpaulo * 5 -- unused 1074286441Srpaulo * 6 -- unused 1075286441Srpaulo * 7 -- Commands 1076286441Srpaulo * 1077286441Srpaulo * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1078286441Srpaulo * In addition, driver can map the remaining queues to Tx DMA/FIFO 1079286441Srpaulo * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1080286441Srpaulo * 1081286441Srpaulo * The driver sets up each queue to work in one of two modes: 1082286441Srpaulo * 1083286441Srpaulo * 1) Scheduler-Ack, in which the scheduler automatically supports a 1084286441Srpaulo * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1085286441Srpaulo * contains TFDs for a unique combination of Recipient Address (RA) 1086286441Srpaulo * and Traffic Identifier (TID), that is, traffic of a given 1087286441Srpaulo * Quality-Of-Service (QOS) priority, destined for a single station. 1088286441Srpaulo * 1089286441Srpaulo * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1090286441Srpaulo * each frame within the BA window, including whether it's been transmitted, 1091286441Srpaulo * and whether it's been acknowledged by the receiving station. The device 1092286441Srpaulo * automatically processes block-acks received from the receiving STA, 1093286441Srpaulo * and reschedules un-acked frames to be retransmitted (successful 1094286441Srpaulo * Tx completion may end up being out-of-order). 1095286441Srpaulo * 1096286441Srpaulo * The driver must maintain the queue's Byte Count table in host DRAM 1097286441Srpaulo * for this mode. 1098286441Srpaulo * This mode does not support fragmentation. 1099286441Srpaulo * 1100286441Srpaulo * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1101286441Srpaulo * The device may automatically retry Tx, but will retry only one frame 1102286441Srpaulo * at a time, until receiving ACK from receiving station, or reaching 1103286441Srpaulo * retry limit and giving up. 1104286441Srpaulo * 1105286441Srpaulo * The command queue (#4/#9) must use this mode! 1106286441Srpaulo * This mode does not require use of the Byte Count table in host DRAM. 1107286441Srpaulo * 1108286441Srpaulo * Driver controls scheduler operation via 3 means: 1109286441Srpaulo * 1) Scheduler registers 1110286441Srpaulo * 2) Shared scheduler data base in internal SRAM 1111286441Srpaulo * 3) Shared data in host DRAM 1112286441Srpaulo * 1113286441Srpaulo * Initialization: 1114286441Srpaulo * 1115286441Srpaulo * When loading, driver should allocate memory for: 1116286441Srpaulo * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1117286441Srpaulo * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1118286441Srpaulo * (1024 bytes for each queue). 1119286441Srpaulo * 1120286441Srpaulo * After receiving "Alive" response from uCode, driver must initialize 1121286441Srpaulo * the scheduler (especially for queue #4/#9, the command queue, otherwise 1122286441Srpaulo * the driver can't issue commands!): 1123286441Srpaulo */ 1124286441Srpaulo#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1125286441Srpaulo 1126286441Srpaulo/** 1127286441Srpaulo * Max Tx window size is the max number of contiguous TFDs that the scheduler 1128286441Srpaulo * can keep track of at one time when creating block-ack chains of frames. 1129286441Srpaulo * Note that "64" matches the number of ack bits in a block-ack packet. 1130286441Srpaulo */ 1131286441Srpaulo#define IWM_SCD_WIN_SIZE 64 1132286441Srpaulo#define IWM_SCD_FRAME_LIMIT 64 1133286441Srpaulo 1134286441Srpaulo#define IWM_SCD_TXFIFO_POS_TID (0) 1135286441Srpaulo#define IWM_SCD_TXFIFO_POS_RA (4) 1136286441Srpaulo#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1137286441Srpaulo 1138286441Srpaulo/* agn SCD */ 1139286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1140286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1141286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1142286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1143286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1144286441Srpaulo 1145286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1146286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1147286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1148286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1149286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1150286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1151286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1152286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1153303628Ssbruno#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1154303628Ssbruno#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1155286441Srpaulo 1156286441Srpaulo/* Context Data */ 1157286441Srpaulo#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1158286441Srpaulo#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1159286441Srpaulo 1160286441Srpaulo/* Tx status */ 1161286441Srpaulo#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1162286441Srpaulo#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1163286441Srpaulo 1164286441Srpaulo/* Translation Data */ 1165286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1166286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1167286441Srpaulo 1168286441Srpaulo#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1169286441Srpaulo (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1170286441Srpaulo 1171286441Srpaulo#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1172286441Srpaulo (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1173286441Srpaulo 1174286441Srpaulo#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1175286441Srpaulo ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1176286441Srpaulo 1177286441Srpaulo#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1178286441Srpaulo 1179286441Srpaulo#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1180286441Srpaulo#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1181286441Srpaulo#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1182286441Srpaulo#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1183286441Srpaulo#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1184286441Srpaulo#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1185286441Srpaulo#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1186286441Srpaulo#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1187286441Srpaulo#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1188303628Ssbruno#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1189303628Ssbruno#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1190286441Srpaulo 1191286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1192286441Srpaulo{ 1193286441Srpaulo if (chnl < 20) 1194286441Srpaulo return IWM_SCD_BASE + 0x18 + chnl * 4; 1195286441Srpaulo return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1196286441Srpaulo} 1197286441Srpaulo 1198286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1199286441Srpaulo{ 1200286441Srpaulo if (chnl < 20) 1201286441Srpaulo return IWM_SCD_BASE + 0x68 + chnl * 4; 1202286441Srpaulo return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1203286441Srpaulo} 1204286441Srpaulo 1205286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1206286441Srpaulo{ 1207286441Srpaulo if (chnl < 20) 1208286441Srpaulo return IWM_SCD_BASE + 0x10c + chnl * 4; 1209286441Srpaulo return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1210286441Srpaulo} 1211286441Srpaulo 1212286441Srpaulo/*********************** END TX SCHEDULER *************************************/ 1213286441Srpaulo 1214286441Srpaulo/* Oscillator clock */ 1215286441Srpaulo#define IWM_OSC_CLK (0xa04068) 1216286441Srpaulo#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1217286441Srpaulo 1218286441Srpaulo/* 1219286441Srpaulo * END iwl-prph.h 1220286441Srpaulo */ 1221286441Srpaulo 1222286441Srpaulo/* 1223286441Srpaulo * BEGIN iwl-fh.h 1224286441Srpaulo */ 1225286441Srpaulo 1226286441Srpaulo/****************************/ 1227286441Srpaulo/* Flow Handler Definitions */ 1228286441Srpaulo/****************************/ 1229286441Srpaulo 1230286441Srpaulo/** 1231286441Srpaulo * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1232286441Srpaulo * Addresses are offsets from device's PCI hardware base address. 1233286441Srpaulo */ 1234286441Srpaulo#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1235286441Srpaulo#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1236286441Srpaulo 1237286441Srpaulo/** 1238286441Srpaulo * Keep-Warm (KW) buffer base address. 1239286441Srpaulo * 1240286441Srpaulo * Driver must allocate a 4KByte buffer that is for keeping the 1241286441Srpaulo * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1242286441Srpaulo * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1243286441Srpaulo * from going into a power-savings mode that would cause higher DRAM latency, 1244286441Srpaulo * and possible data over/under-runs, before all Tx/Rx is complete. 1245286441Srpaulo * 1246286441Srpaulo * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1247286441Srpaulo * of the buffer, which must be 4K aligned. Once this is set up, the device 1248286441Srpaulo * automatically invokes keep-warm accesses when normal accesses might not 1249286441Srpaulo * be sufficient to maintain fast DRAM response. 1250286441Srpaulo * 1251286441Srpaulo * Bit fields: 1252286441Srpaulo * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1253286441Srpaulo */ 1254286441Srpaulo#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1255286441Srpaulo 1256286441Srpaulo 1257286441Srpaulo/** 1258286441Srpaulo * TFD Circular Buffers Base (CBBC) addresses 1259286441Srpaulo * 1260286441Srpaulo * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1261286441Srpaulo * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1262286441Srpaulo * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1263286441Srpaulo * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1264286441Srpaulo * aligned (address bits 0-7 must be 0). 1265286441Srpaulo * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1266286441Srpaulo * for them are in different places. 1267286441Srpaulo * 1268286441Srpaulo * Bit fields in each pointer register: 1269286441Srpaulo * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1270286441Srpaulo */ 1271286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1272286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1273286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1274286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1275286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1276286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1277286441Srpaulo 1278286441Srpaulo/* Find TFD CB base pointer for given queue */ 1279286441Srpaulostatic inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1280286441Srpaulo{ 1281286441Srpaulo if (chnl < 16) 1282286441Srpaulo return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1283286441Srpaulo if (chnl < 20) 1284286441Srpaulo return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1285286441Srpaulo return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1286286441Srpaulo} 1287286441Srpaulo 1288286441Srpaulo 1289286441Srpaulo/** 1290286441Srpaulo * Rx SRAM Control and Status Registers (RSCSR) 1291286441Srpaulo * 1292286441Srpaulo * These registers provide handshake between driver and device for the Rx queue 1293286441Srpaulo * (this queue handles *all* command responses, notifications, Rx data, etc. 1294286441Srpaulo * sent from uCode to host driver). Unlike Tx, there is only one Rx 1295286441Srpaulo * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1296286441Srpaulo * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1297286441Srpaulo * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1298286441Srpaulo * mapping between RBDs and RBs. 1299286441Srpaulo * 1300286441Srpaulo * Driver must allocate host DRAM memory for the following, and set the 1301286441Srpaulo * physical address of each into device registers: 1302286441Srpaulo * 1303286441Srpaulo * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1304286441Srpaulo * entries (although any power of 2, up to 4096, is selectable by driver). 1305286441Srpaulo * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1306286441Srpaulo * (typically 4K, although 8K or 16K are also selectable by driver). 1307286441Srpaulo * Driver sets up RB size and number of RBDs in the CB via Rx config 1308286441Srpaulo * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1309286441Srpaulo * 1310286441Srpaulo * Bit fields within one RBD: 1311286441Srpaulo * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1312286441Srpaulo * 1313286441Srpaulo * Driver sets physical address [35:8] of base of RBD circular buffer 1314286441Srpaulo * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1315286441Srpaulo * 1316286441Srpaulo * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1317286441Srpaulo * (RBs) have been filled, via a "write pointer", actually the index of 1318286441Srpaulo * the RB's corresponding RBD within the circular buffer. Driver sets 1319286441Srpaulo * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1320286441Srpaulo * 1321286441Srpaulo * Bit fields in lower dword of Rx status buffer (upper dword not used 1322286441Srpaulo * by driver: 1323286441Srpaulo * 31-12: Not used by driver 1324286441Srpaulo * 11- 0: Index of last filled Rx buffer descriptor 1325286441Srpaulo * (device writes, driver reads this value) 1326286441Srpaulo * 1327286441Srpaulo * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1328286441Srpaulo * enter pointers to these RBs into contiguous RBD circular buffer entries, 1329286441Srpaulo * and update the device's "write" index register, 1330286441Srpaulo * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1331286441Srpaulo * 1332286441Srpaulo * This "write" index corresponds to the *next* RBD that the driver will make 1333286441Srpaulo * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1334286441Srpaulo * the circular buffer. This value should initially be 0 (before preparing any 1335286441Srpaulo * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1336286441Srpaulo * wrap back to 0 at the end of the circular buffer (but don't wrap before 1337286441Srpaulo * "read" index has advanced past 1! See below). 1338286441Srpaulo * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1339286441Srpaulo * 1340286441Srpaulo * As the device fills RBs (referenced from contiguous RBDs within the circular 1341286441Srpaulo * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1342286441Srpaulo * to tell the driver the index of the latest filled RBD. The driver must 1343286441Srpaulo * read this "read" index from DRAM after receiving an Rx interrupt from device 1344286441Srpaulo * 1345286441Srpaulo * The driver must also internally keep track of a third index, which is the 1346286441Srpaulo * next RBD to process. When receiving an Rx interrupt, driver should process 1347286441Srpaulo * all filled but unprocessed RBs up to, but not including, the RB 1348286441Srpaulo * corresponding to the "read" index. For example, if "read" index becomes "1", 1349286441Srpaulo * driver may process the RB pointed to by RBD 0. Depending on volume of 1350286441Srpaulo * traffic, there may be many RBs to process. 1351286441Srpaulo * 1352286441Srpaulo * If read index == write index, device thinks there is no room to put new data. 1353286441Srpaulo * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1354286441Srpaulo * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1355286441Srpaulo * and "read" indexes; that is, make sure that there are no more than 254 1356286441Srpaulo * buffers waiting to be filled. 1357286441Srpaulo */ 1358286441Srpaulo#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1359286441Srpaulo#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1360286441Srpaulo#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1361286441Srpaulo 1362286441Srpaulo/** 1363286441Srpaulo * Physical base address of 8-byte Rx Status buffer. 1364286441Srpaulo * Bit fields: 1365286441Srpaulo * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1366286441Srpaulo */ 1367286441Srpaulo#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1368286441Srpaulo 1369286441Srpaulo/** 1370286441Srpaulo * Physical base address of Rx Buffer Descriptor Circular Buffer. 1371286441Srpaulo * Bit fields: 1372286441Srpaulo * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1373286441Srpaulo */ 1374286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1375286441Srpaulo 1376286441Srpaulo/** 1377286441Srpaulo * Rx write pointer (index, really!). 1378286441Srpaulo * Bit fields: 1379286441Srpaulo * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1380286441Srpaulo * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1381286441Srpaulo */ 1382286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1383286441Srpaulo#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1384286441Srpaulo 1385286441Srpaulo#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1386286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1387286441Srpaulo 1388286441Srpaulo/** 1389286441Srpaulo * Rx Config/Status Registers (RCSR) 1390286441Srpaulo * Rx Config Reg for channel 0 (only channel used) 1391286441Srpaulo * 1392286441Srpaulo * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1393286441Srpaulo * normal operation (see bit fields). 1394286441Srpaulo * 1395286441Srpaulo * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1396286441Srpaulo * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1397286441Srpaulo * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1398286441Srpaulo * 1399286441Srpaulo * Bit fields: 1400286441Srpaulo * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1401286441Srpaulo * '10' operate normally 1402286441Srpaulo * 29-24: reserved 1403286441Srpaulo * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1404286441Srpaulo * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1405286441Srpaulo * 19-18: reserved 1406286441Srpaulo * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1407286441Srpaulo * '10' 12K, '11' 16K. 1408286441Srpaulo * 15-14: reserved 1409286441Srpaulo * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1410286441Srpaulo * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1411286441Srpaulo * typical value 0x10 (about 1/2 msec) 1412286441Srpaulo * 3- 0: reserved 1413286441Srpaulo */ 1414286441Srpaulo#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1415286441Srpaulo#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1416286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1417286441Srpaulo 1418286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1419286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1420286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1421286441Srpaulo 1422286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1423286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1424286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1425286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1426286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1427286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1428286441Srpaulo 1429286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1430286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1431286441Srpaulo#define IWM_RX_RB_TIMEOUT (0x11) 1432286441Srpaulo 1433286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1434286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1435286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1436286441Srpaulo 1437286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1438286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1439286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1440286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1441286441Srpaulo 1442286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1443286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1444286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1445286441Srpaulo 1446286441Srpaulo/** 1447286441Srpaulo * Rx Shared Status Registers (RSSR) 1448286441Srpaulo * 1449286441Srpaulo * After stopping Rx DMA channel (writing 0 to 1450286441Srpaulo * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1451286441Srpaulo * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1452286441Srpaulo * 1453286441Srpaulo * Bit fields: 1454286441Srpaulo * 24: 1 = Channel 0 is idle 1455286441Srpaulo * 1456286441Srpaulo * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1457286441Srpaulo * contain default values that should not be altered by the driver. 1458286441Srpaulo */ 1459286441Srpaulo#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1460286441Srpaulo#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1461286441Srpaulo 1462286441Srpaulo#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1463286441Srpaulo#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1464286441Srpaulo#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1465286441Srpaulo (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1466286441Srpaulo 1467286441Srpaulo#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1468286441Srpaulo 1469286441Srpaulo#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1470286441Srpaulo 1471286441Srpaulo/* TFDB Area - TFDs buffer table */ 1472286441Srpaulo#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1473286441Srpaulo#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1474286441Srpaulo#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1475286441Srpaulo#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1476286441Srpaulo#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1477286441Srpaulo 1478286441Srpaulo/** 1479286441Srpaulo * Transmit DMA Channel Control/Status Registers (TCSR) 1480286441Srpaulo * 1481286441Srpaulo * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1482286441Srpaulo * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1483286441Srpaulo * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1484286441Srpaulo * 1485286441Srpaulo * To use a Tx DMA channel, driver must initialize its 1486286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1487286441Srpaulo * 1488286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1489286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1490286441Srpaulo * 1491286441Srpaulo * All other bits should be 0. 1492286441Srpaulo * 1493286441Srpaulo * Bit fields: 1494286441Srpaulo * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1495286441Srpaulo * '10' operate normally 1496286441Srpaulo * 29- 4: Reserved, set to "0" 1497286441Srpaulo * 3: Enable internal DMA requests (1, normal operation), disable (0) 1498286441Srpaulo * 2- 0: Reserved, set to "0" 1499286441Srpaulo */ 1500286441Srpaulo#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1501286441Srpaulo#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1502286441Srpaulo 1503286441Srpaulo/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1504286441Srpaulo#define IWM_FH_TCSR_CHNL_NUM (8) 1505286441Srpaulo 1506286441Srpaulo/* TCSR: tx_config register values */ 1507286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1508286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1509286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1510286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1511286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1512286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1513286441Srpaulo 1514286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1515286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1516286441Srpaulo 1517286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1518286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1519286441Srpaulo 1520286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1521286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1522286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1523286441Srpaulo 1524286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1525286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1526286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1527286441Srpaulo 1528286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1529286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1530286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1531286441Srpaulo 1532286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1533286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1534286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1535286441Srpaulo 1536286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1537286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1538286441Srpaulo 1539286441Srpaulo/** 1540286441Srpaulo * Tx Shared Status Registers (TSSR) 1541286441Srpaulo * 1542286441Srpaulo * After stopping Tx DMA channel (writing 0 to 1543286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1544286441Srpaulo * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1545286441Srpaulo * (channel's buffers empty | no pending requests). 1546286441Srpaulo * 1547286441Srpaulo * Bit fields: 1548286441Srpaulo * 31-24: 1 = Channel buffers empty (channel 7:0) 1549286441Srpaulo * 23-16: 1 = No pending requests (channel 7:0) 1550286441Srpaulo */ 1551286441Srpaulo#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1552286441Srpaulo#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1553286441Srpaulo 1554286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1555286441Srpaulo 1556286441Srpaulo/** 1557286441Srpaulo * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1558286441Srpaulo * 31: Indicates an address error when accessed to internal memory 1559286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1560286441Srpaulo * 30: Indicates that Host did not send the expected number of dwords to FH 1561286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1562286441Srpaulo * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1563286441Srpaulo * command was received from the scheduler while the TRB was already full 1564286441Srpaulo * with previous command 1565286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1566286441Srpaulo * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1567286441Srpaulo * bit is set, it indicates that the FH has received a full indication 1568286441Srpaulo * from the RTC TxFIFO and the current value of the TxCredit counter was 1569286441Srpaulo * not equal to zero. This mean that the credit mechanism was not 1570286441Srpaulo * synchronized to the TxFIFO status 1571286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1572286441Srpaulo */ 1573286441Srpaulo#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1574286441Srpaulo#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1575286441Srpaulo 1576286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1577286441Srpaulo 1578286441Srpaulo/* Tx service channels */ 1579286441Srpaulo#define IWM_FH_SRVC_CHNL (9) 1580286441Srpaulo#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1581286441Srpaulo#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1582286441Srpaulo#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1583286441Srpaulo (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1584286441Srpaulo 1585286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1586286441Srpaulo#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1587286441Srpaulo (_chan) * 4) 1588286441Srpaulo 1589286441Srpaulo/* Instruct FH to increment the retry count of a packet when 1590286441Srpaulo * it is brought from the memory to TX-FIFO 1591286441Srpaulo */ 1592286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1593286441Srpaulo 1594286441Srpaulo#define IWM_RX_QUEUE_SIZE 256 1595286441Srpaulo#define IWM_RX_QUEUE_MASK 255 1596286441Srpaulo#define IWM_RX_QUEUE_SIZE_LOG 8 1597286441Srpaulo 1598286441Srpaulo/* 1599286441Srpaulo * RX related structures and functions 1600286441Srpaulo */ 1601286441Srpaulo#define IWM_RX_FREE_BUFFERS 64 1602286441Srpaulo#define IWM_RX_LOW_WATERMARK 8 1603286441Srpaulo 1604286441Srpaulo/** 1605286441Srpaulo * struct iwm_rb_status - reseve buffer status 1606286441Srpaulo * host memory mapped FH registers 1607286441Srpaulo * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1608286441Srpaulo * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1609286441Srpaulo * @finished_rb_num [0:11] - Indicates the index of the current RB 1610286441Srpaulo * in which the last frame was written to 1611286441Srpaulo * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1612286441Srpaulo * which was transferred 1613286441Srpaulo */ 1614286441Srpaulostruct iwm_rb_status { 1615286441Srpaulo uint16_t closed_rb_num; 1616286441Srpaulo uint16_t closed_fr_num; 1617286441Srpaulo uint16_t finished_rb_num; 1618286441Srpaulo uint16_t finished_fr_nam; 1619286441Srpaulo uint32_t unused; 1620286441Srpaulo} __packed; 1621286441Srpaulo 1622286441Srpaulo 1623286441Srpaulo#define IWM_TFD_QUEUE_SIZE_MAX (256) 1624286441Srpaulo#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1625286441Srpaulo#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1626286441Srpaulo IWM_TFD_QUEUE_SIZE_BC_DUP) 1627286441Srpaulo#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1628286441Srpaulo#define IWM_NUM_OF_TBS 20 1629286441Srpaulo 1630286441Srpaulostatic inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1631286441Srpaulo{ 1632286441Srpaulo return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1633286441Srpaulo} 1634286441Srpaulo/** 1635286441Srpaulo * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1636286441Srpaulo * 1637286441Srpaulo * This structure contains dma address and length of transmission address 1638286441Srpaulo * 1639286441Srpaulo * @lo: low [31:0] portion of the dma address of TX buffer 1640286441Srpaulo * every even is unaligned on 16 bit boundary 1641286441Srpaulo * @hi_n_len 0-3 [35:32] portion of dma 1642286441Srpaulo * 4-15 length of the tx buffer 1643286441Srpaulo */ 1644286441Srpaulostruct iwm_tfd_tb { 1645286441Srpaulo uint32_t lo; 1646286441Srpaulo uint16_t hi_n_len; 1647286441Srpaulo} __packed; 1648286441Srpaulo 1649286441Srpaulo/** 1650286441Srpaulo * struct iwm_tfd 1651286441Srpaulo * 1652286441Srpaulo * Transmit Frame Descriptor (TFD) 1653286441Srpaulo * 1654286441Srpaulo * @ __reserved1[3] reserved 1655286441Srpaulo * @ num_tbs 0-4 number of active tbs 1656286441Srpaulo * 5 reserved 1657286441Srpaulo * 6-7 padding (not used) 1658286441Srpaulo * @ tbs[20] transmit frame buffer descriptors 1659286441Srpaulo * @ __pad padding 1660286441Srpaulo * 1661286441Srpaulo * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1662286441Srpaulo * Both driver and device share these circular buffers, each of which must be 1663286441Srpaulo * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1664286441Srpaulo * 1665286441Srpaulo * Driver must indicate the physical address of the base of each 1666286441Srpaulo * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1667286441Srpaulo * 1668286441Srpaulo * Each TFD contains pointer/size information for up to 20 data buffers 1669286441Srpaulo * in host DRAM. These buffers collectively contain the (one) frame described 1670286441Srpaulo * by the TFD. Each buffer must be a single contiguous block of memory within 1671286441Srpaulo * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1672286441Srpaulo * of (4K - 4). The concatenates all of a TFD's buffers into a single 1673286441Srpaulo * Tx frame, up to 8 KBytes in size. 1674286441Srpaulo * 1675286441Srpaulo * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1676286441Srpaulo */ 1677286441Srpaulostruct iwm_tfd { 1678286441Srpaulo uint8_t __reserved1[3]; 1679286441Srpaulo uint8_t num_tbs; 1680286441Srpaulo struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1681286441Srpaulo uint32_t __pad; 1682286441Srpaulo} __packed; 1683286441Srpaulo 1684286441Srpaulo/* Keep Warm Size */ 1685286441Srpaulo#define IWM_KW_SIZE 0x1000 /* 4k */ 1686286441Srpaulo 1687286441Srpaulo/* Fixed (non-configurable) rx data from phy */ 1688286441Srpaulo 1689286441Srpaulo/** 1690286441Srpaulo * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1691286441Srpaulo * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1692286441Srpaulo * @tfd_offset 0-12 - tx command byte count 1693286441Srpaulo * 12-16 - station index 1694286441Srpaulo */ 1695286441Srpaulostruct iwm_agn_scd_bc_tbl { 1696286441Srpaulo uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1697286441Srpaulo} __packed; 1698286441Srpaulo 1699286441Srpaulo/* 1700286441Srpaulo * END iwl-fh.h 1701286441Srpaulo */ 1702286441Srpaulo 1703286441Srpaulo/* 1704286441Srpaulo * BEGIN mvm/fw-api.h 1705286441Srpaulo */ 1706286441Srpaulo 1707303628Ssbruno/* Maximum number of Tx queues. */ 1708303628Ssbruno#define IWM_MVM_MAX_QUEUES 31 1709286441Srpaulo 1710286441Srpaulo/* Tx queue numbers */ 1711286441Srpauloenum { 1712286441Srpaulo IWM_MVM_OFFCHANNEL_QUEUE = 8, 1713286441Srpaulo IWM_MVM_CMD_QUEUE = 9, 1714303628Ssbruno IWM_MVM_AUX_QUEUE = 15, 1715286441Srpaulo}; 1716286441Srpaulo 1717301192Sadrianenum iwm_mvm_tx_fifo { 1718301192Sadrian IWM_MVM_TX_FIFO_BK = 0, 1719301192Sadrian IWM_MVM_TX_FIFO_BE, 1720301192Sadrian IWM_MVM_TX_FIFO_VI, 1721301192Sadrian IWM_MVM_TX_FIFO_VO, 1722301192Sadrian IWM_MVM_TX_FIFO_MCAST = 5, 1723301192Sadrian IWM_MVM_TX_FIFO_CMD = 7, 1724301192Sadrian}; 1725286441Srpaulo 1726286441Srpaulo#define IWM_MVM_STATION_COUNT 16 1727286441Srpaulo 1728286441Srpaulo/* commands */ 1729286441Srpauloenum { 1730286441Srpaulo IWM_MVM_ALIVE = 0x1, 1731286441Srpaulo IWM_REPLY_ERROR = 0x2, 1732286441Srpaulo 1733286441Srpaulo IWM_INIT_COMPLETE_NOTIF = 0x4, 1734286441Srpaulo 1735286441Srpaulo /* PHY context commands */ 1736286441Srpaulo IWM_PHY_CONTEXT_CMD = 0x8, 1737286441Srpaulo IWM_DBG_CFG = 0x9, 1738286441Srpaulo 1739303628Ssbruno /* UMAC scan commands */ 1740303628Ssbruno IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1741303628Ssbruno IWM_SCAN_CFG_CMD = 0xc, 1742303628Ssbruno IWM_SCAN_REQ_UMAC = 0xd, 1743303628Ssbruno IWM_SCAN_ABORT_UMAC = 0xe, 1744303628Ssbruno IWM_SCAN_COMPLETE_UMAC = 0xf, 1745303628Ssbruno 1746286441Srpaulo /* station table */ 1747286441Srpaulo IWM_ADD_STA_KEY = 0x17, 1748286441Srpaulo IWM_ADD_STA = 0x18, 1749286441Srpaulo IWM_REMOVE_STA = 0x19, 1750286441Srpaulo 1751286441Srpaulo /* TX */ 1752286441Srpaulo IWM_TX_CMD = 0x1c, 1753286441Srpaulo IWM_TXPATH_FLUSH = 0x1e, 1754286441Srpaulo IWM_MGMT_MCAST_KEY = 0x1f, 1755286441Srpaulo 1756303628Ssbruno /* scheduler config */ 1757303628Ssbruno IWM_SCD_QUEUE_CFG = 0x1d, 1758303628Ssbruno 1759286441Srpaulo /* global key */ 1760286441Srpaulo IWM_WEP_KEY = 0x20, 1761286441Srpaulo 1762286441Srpaulo /* MAC and Binding commands */ 1763286441Srpaulo IWM_MAC_CONTEXT_CMD = 0x28, 1764286441Srpaulo IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1765286441Srpaulo IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1766286441Srpaulo IWM_BINDING_CONTEXT_CMD = 0x2b, 1767286441Srpaulo IWM_TIME_QUOTA_CMD = 0x2c, 1768286441Srpaulo IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1769286441Srpaulo 1770286441Srpaulo IWM_LQ_CMD = 0x4e, 1771286441Srpaulo 1772330192Seadler /* paging block to FW cpu2 */ 1773330192Seadler IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1774286441Srpaulo 1775286441Srpaulo /* Scan offload */ 1776286441Srpaulo IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1777286441Srpaulo IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1778303628Ssbruno IWM_HOT_SPOT_CMD = 0x53, 1779303628Ssbruno IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1780303628Ssbruno IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1781286441Srpaulo IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1782286441Srpaulo IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1783303628Ssbruno IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1784286441Srpaulo 1785286441Srpaulo /* Phy */ 1786286441Srpaulo IWM_PHY_CONFIGURATION_CMD = 0x6a, 1787286441Srpaulo IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1788330219Seadler IWM_PHY_DB_CMD = 0x6c, 1789286441Srpaulo 1790286441Srpaulo /* Power - legacy power table command */ 1791286441Srpaulo IWM_POWER_TABLE_CMD = 0x77, 1792286441Srpaulo IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1793286441Srpaulo 1794286441Srpaulo /* Thermal Throttling*/ 1795286441Srpaulo IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1796286441Srpaulo 1797286441Srpaulo /* Scanning */ 1798286441Srpaulo IWM_SCAN_ABORT_CMD = 0x81, 1799286441Srpaulo IWM_SCAN_START_NOTIFICATION = 0x82, 1800286441Srpaulo IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1801286441Srpaulo 1802286441Srpaulo /* NVM */ 1803286441Srpaulo IWM_NVM_ACCESS_CMD = 0x88, 1804286441Srpaulo 1805286441Srpaulo IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1806286441Srpaulo 1807286441Srpaulo IWM_BEACON_NOTIFICATION = 0x90, 1808286441Srpaulo IWM_BEACON_TEMPLATE_CMD = 0x91, 1809286441Srpaulo IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1810286441Srpaulo IWM_BT_CONFIG = 0x9b, 1811286441Srpaulo IWM_STATISTICS_NOTIFICATION = 0x9d, 1812286441Srpaulo IWM_REDUCE_TX_POWER_CMD = 0x9f, 1813286441Srpaulo 1814286441Srpaulo /* RF-KILL commands and notifications */ 1815286441Srpaulo IWM_CARD_STATE_CMD = 0xa0, 1816286441Srpaulo IWM_CARD_STATE_NOTIFICATION = 0xa1, 1817286441Srpaulo 1818286441Srpaulo IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1819286441Srpaulo 1820303628Ssbruno IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1821303628Ssbruno 1822286441Srpaulo /* Power - new power table command */ 1823286441Srpaulo IWM_MAC_PM_POWER_TABLE = 0xa9, 1824286441Srpaulo 1825286441Srpaulo IWM_REPLY_RX_PHY_CMD = 0xc0, 1826286441Srpaulo IWM_REPLY_RX_MPDU_CMD = 0xc1, 1827286441Srpaulo IWM_BA_NOTIF = 0xc5, 1828286441Srpaulo 1829303628Ssbruno /* Location Aware Regulatory */ 1830303628Ssbruno IWM_MCC_UPDATE_CMD = 0xc8, 1831303628Ssbruno IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1832303628Ssbruno 1833286441Srpaulo /* BT Coex */ 1834286441Srpaulo IWM_BT_COEX_PRIO_TABLE = 0xcc, 1835286441Srpaulo IWM_BT_COEX_PROT_ENV = 0xcd, 1836286441Srpaulo IWM_BT_PROFILE_NOTIFICATION = 0xce, 1837286441Srpaulo IWM_BT_COEX_CI = 0x5d, 1838286441Srpaulo 1839286441Srpaulo IWM_REPLY_SF_CFG_CMD = 0xd1, 1840286441Srpaulo IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1841286441Srpaulo 1842303628Ssbruno /* DTS measurements */ 1843303628Ssbruno IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1844303628Ssbruno IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1845303628Ssbruno 1846286441Srpaulo IWM_REPLY_DEBUG_CMD = 0xf0, 1847286441Srpaulo IWM_DEBUG_LOG_MSG = 0xf7, 1848286441Srpaulo 1849286441Srpaulo IWM_MCAST_FILTER_CMD = 0xd0, 1850286441Srpaulo 1851286441Srpaulo /* D3 commands/notifications */ 1852286441Srpaulo IWM_D3_CONFIG_CMD = 0xd3, 1853286441Srpaulo IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1854286441Srpaulo IWM_OFFLOADS_QUERY_CMD = 0xd5, 1855286441Srpaulo IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1856286441Srpaulo 1857286441Srpaulo /* for WoWLAN in particular */ 1858286441Srpaulo IWM_WOWLAN_PATTERNS = 0xe0, 1859286441Srpaulo IWM_WOWLAN_CONFIGURATION = 0xe1, 1860286441Srpaulo IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1861286441Srpaulo IWM_WOWLAN_TKIP_PARAM = 0xe3, 1862286441Srpaulo IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1863286441Srpaulo IWM_WOWLAN_GET_STATUSES = 0xe5, 1864286441Srpaulo IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1865286441Srpaulo 1866286441Srpaulo /* and for NetDetect */ 1867286441Srpaulo IWM_NET_DETECT_CONFIG_CMD = 0x54, 1868286441Srpaulo IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1869286441Srpaulo IWM_NET_DETECT_PROFILES_CMD = 0x57, 1870286441Srpaulo IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1871286441Srpaulo IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1872286441Srpaulo 1873286441Srpaulo IWM_REPLY_MAX = 0xff, 1874286441Srpaulo}; 1875286441Srpaulo 1876330178Seadlerenum iwm_phy_ops_subcmd_ids { 1877330178Seadler IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1878330178Seadler IWM_CTDP_CONFIG_CMD = 0x03, 1879330178Seadler IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1880330178Seadler IWM_CT_KILL_NOTIFICATION = 0xFE, 1881330178Seadler IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1882330178Seadler}; 1883330178Seadler 1884330178Seadler/* command groups */ 1885330178Seadlerenum { 1886330178Seadler IWM_LEGACY_GROUP = 0x0, 1887330178Seadler IWM_LONG_GROUP = 0x1, 1888330178Seadler IWM_SYSTEM_GROUP = 0x2, 1889330178Seadler IWM_MAC_CONF_GROUP = 0x3, 1890330178Seadler IWM_PHY_OPS_GROUP = 0x4, 1891330178Seadler IWM_DATA_PATH_GROUP = 0x5, 1892330178Seadler IWM_PROT_OFFLOAD_GROUP = 0xb, 1893330178Seadler}; 1894330178Seadler 1895286441Srpaulo/** 1896286441Srpaulo * struct iwm_cmd_response - generic response struct for most commands 1897286441Srpaulo * @status: status of the command asked, changes for each one 1898286441Srpaulo */ 1899286441Srpaulostruct iwm_cmd_response { 1900286441Srpaulo uint32_t status; 1901286441Srpaulo}; 1902286441Srpaulo 1903286441Srpaulo/* 1904286441Srpaulo * struct iwm_tx_ant_cfg_cmd 1905286441Srpaulo * @valid: valid antenna configuration 1906286441Srpaulo */ 1907286441Srpaulostruct iwm_tx_ant_cfg_cmd { 1908286441Srpaulo uint32_t valid; 1909286441Srpaulo} __packed; 1910286441Srpaulo 1911286441Srpaulo/** 1912286441Srpaulo * struct iwm_reduce_tx_power_cmd - TX power reduction command 1913286441Srpaulo * IWM_REDUCE_TX_POWER_CMD = 0x9f 1914286441Srpaulo * @flags: (reserved for future implementation) 1915286441Srpaulo * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1916286441Srpaulo * @pwr_restriction: TX power restriction in dBms. 1917286441Srpaulo */ 1918286441Srpaulostruct iwm_reduce_tx_power_cmd { 1919286441Srpaulo uint8_t flags; 1920286441Srpaulo uint8_t mac_context_id; 1921286441Srpaulo uint16_t pwr_restriction; 1922286441Srpaulo} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1923286441Srpaulo 1924286441Srpaulo/* 1925286441Srpaulo * Calibration control struct. 1926286441Srpaulo * Sent as part of the phy configuration command. 1927286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 1928286441Srpaulo * flow triggers. 1929286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 1930286441Srpaulo * event triggers. 1931286441Srpaulo */ 1932286441Srpaulostruct iwm_calib_ctrl { 1933286441Srpaulo uint32_t flow_trigger; 1934286441Srpaulo uint32_t event_trigger; 1935286441Srpaulo} __packed; 1936286441Srpaulo 1937286441Srpaulo/* This enum defines the bitmap of various calibrations to enable in both 1938286441Srpaulo * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1939286441Srpaulo */ 1940286441Srpauloenum iwm_calib_cfg { 1941286441Srpaulo IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1942286441Srpaulo IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1943286441Srpaulo IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1944286441Srpaulo IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1945286441Srpaulo IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1946286441Srpaulo IWM_CALIB_CFG_DC_IDX = (1 << 5), 1947286441Srpaulo IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1948286441Srpaulo IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1949286441Srpaulo IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1950286441Srpaulo IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1951286441Srpaulo IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1952286441Srpaulo IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1953286441Srpaulo IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1954286441Srpaulo IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1955286441Srpaulo IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1956286441Srpaulo IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1957286441Srpaulo IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1958286441Srpaulo IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1959286441Srpaulo IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1960286441Srpaulo}; 1961286441Srpaulo 1962286441Srpaulo/* 1963286441Srpaulo * Phy configuration command. 1964286441Srpaulo */ 1965286441Srpaulostruct iwm_phy_cfg_cmd { 1966286441Srpaulo uint32_t phy_cfg; 1967286441Srpaulo struct iwm_calib_ctrl calib_control; 1968286441Srpaulo} __packed; 1969286441Srpaulo 1970286441Srpaulo#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1971286441Srpaulo#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1972286441Srpaulo#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1973286441Srpaulo#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1974286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1975286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1976286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1977286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1978286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1979286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1980286441Srpaulo 1981286441Srpaulo 1982286441Srpaulo/* Target of the IWM_NVM_ACCESS_CMD */ 1983286441Srpauloenum { 1984286441Srpaulo IWM_NVM_ACCESS_TARGET_CACHE = 0, 1985286441Srpaulo IWM_NVM_ACCESS_TARGET_OTP = 1, 1986286441Srpaulo IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1987286441Srpaulo}; 1988286441Srpaulo 1989286441Srpaulo/* Section types for IWM_NVM_ACCESS_CMD */ 1990286441Srpauloenum { 1991330165Seadler IWM_NVM_SECTION_TYPE_SW = 1, 1992330165Seadler IWM_NVM_SECTION_TYPE_REGULATORY = 3, 1993330165Seadler IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 1994330165Seadler IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 1995330165Seadler IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 1996330165Seadler IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 1997330165Seadler IWM_NVM_MAX_NUM_SECTIONS = 13, 1998286441Srpaulo}; 1999286441Srpaulo 2000286441Srpaulo/** 2001286441Srpaulo * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2002286441Srpaulo * @op_code: 0 - read, 1 - write 2003286441Srpaulo * @target: IWM_NVM_ACCESS_TARGET_* 2004286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 2005286441Srpaulo * @offset: offset in bytes into the section 2006286441Srpaulo * @length: in bytes, to read/write 2007286441Srpaulo * @data: if write operation, the data to write. On read its empty 2008286441Srpaulo */ 2009286441Srpaulostruct iwm_nvm_access_cmd { 2010286441Srpaulo uint8_t op_code; 2011286441Srpaulo uint8_t target; 2012286441Srpaulo uint16_t type; 2013286441Srpaulo uint16_t offset; 2014286441Srpaulo uint16_t length; 2015286441Srpaulo uint8_t data[]; 2016286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2017286441Srpaulo 2018330192Seadler#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2019330192Seadler 2020330192Seadler/* 2021330192Seadler * struct iwm_fw_paging_cmd - paging layout 2022330192Seadler * 2023330192Seadler * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2024330192Seadler * 2025330192Seadler * Send to FW the paging layout in the driver. 2026330192Seadler * 2027330192Seadler * @flags: various flags for the command 2028330192Seadler * @block_size: the block size in powers of 2 2029330192Seadler * @block_num: number of blocks specified in the command. 2030330192Seadler * @device_phy_addr: virtual addresses from device side 2031330192Seadler*/ 2032330192Seadlerstruct iwm_fw_paging_cmd { 2033330192Seadler uint32_t flags; 2034330192Seadler uint32_t block_size; 2035330192Seadler uint32_t block_num; 2036330192Seadler uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2037330192Seadler} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2038330192Seadler 2039330192Seadler/* 2040330192Seadler * Fw items ID's 2041330192Seadler * 2042330192Seadler * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2043330192Seadler * download 2044330192Seadler */ 2045330192Seadlerenum iwm_fw_item_id { 2046330192Seadler IWM_FW_ITEM_ID_PAGING = 3, 2047330192Seadler}; 2048330192Seadler 2049330192Seadler/* 2050330192Seadler * struct iwm_fw_get_item_cmd - get an item from the fw 2051330192Seadler */ 2052330192Seadlerstruct iwm_fw_get_item_cmd { 2053330192Seadler uint32_t item_id; 2054330192Seadler} __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2055330192Seadler 2056286441Srpaulo/** 2057286441Srpaulo * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2058286441Srpaulo * @offset: offset in bytes into the section 2059286441Srpaulo * @length: in bytes, either how much was written or read 2060286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 2061286441Srpaulo * @status: 0 for success, fail otherwise 2062286441Srpaulo * @data: if read operation, the data returned. Empty on write. 2063286441Srpaulo */ 2064286441Srpaulostruct iwm_nvm_access_resp { 2065286441Srpaulo uint16_t offset; 2066286441Srpaulo uint16_t length; 2067286441Srpaulo uint16_t type; 2068286441Srpaulo uint16_t status; 2069286441Srpaulo uint8_t data[]; 2070286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2071286441Srpaulo 2072286441Srpaulo/* IWM_MVM_ALIVE 0x1 */ 2073286441Srpaulo 2074286441Srpaulo/* alive response is_valid values */ 2075286441Srpaulo#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2076286441Srpaulo#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2077286441Srpaulo 2078286441Srpaulo/* alive response ver_type values */ 2079286441Srpauloenum { 2080286441Srpaulo IWM_FW_TYPE_HW = 0, 2081286441Srpaulo IWM_FW_TYPE_PROT = 1, 2082286441Srpaulo IWM_FW_TYPE_AP = 2, 2083286441Srpaulo IWM_FW_TYPE_WOWLAN = 3, 2084286441Srpaulo IWM_FW_TYPE_TIMING = 4, 2085286441Srpaulo IWM_FW_TYPE_WIPAN = 5 2086286441Srpaulo}; 2087286441Srpaulo 2088286441Srpaulo/* alive response ver_subtype values */ 2089286441Srpauloenum { 2090286441Srpaulo IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2091286441Srpaulo IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2092286441Srpaulo IWM_FW_SUBTYPE_REDUCED = 2, 2093286441Srpaulo IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2094286441Srpaulo IWM_FW_SUBTYPE_WOWLAN = 4, 2095286441Srpaulo IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2096286441Srpaulo IWM_FW_SUBTYPE_WIPAN = 6, 2097286441Srpaulo IWM_FW_SUBTYPE_INITIALIZE = 9 2098286441Srpaulo}; 2099286441Srpaulo 2100286441Srpaulo#define IWM_ALIVE_STATUS_ERR 0xDEAD 2101286441Srpaulo#define IWM_ALIVE_STATUS_OK 0xCAFE 2102286441Srpaulo 2103286441Srpaulo#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2104286441Srpaulo 2105330183Seadlerstruct iwm_mvm_alive_resp_ver1 { 2106286441Srpaulo uint16_t status; 2107286441Srpaulo uint16_t flags; 2108286441Srpaulo uint8_t ucode_minor; 2109286441Srpaulo uint8_t ucode_major; 2110286441Srpaulo uint16_t id; 2111286441Srpaulo uint8_t api_minor; 2112286441Srpaulo uint8_t api_major; 2113286441Srpaulo uint8_t ver_subtype; 2114286441Srpaulo uint8_t ver_type; 2115286441Srpaulo uint8_t mac; 2116286441Srpaulo uint8_t opt; 2117286441Srpaulo uint16_t reserved2; 2118286441Srpaulo uint32_t timestamp; 2119286441Srpaulo uint32_t error_event_table_ptr; /* SRAM address for error log */ 2120286441Srpaulo uint32_t log_event_table_ptr; /* SRAM address for event log */ 2121286441Srpaulo uint32_t cpu_register_ptr; 2122286441Srpaulo uint32_t dbgm_config_ptr; 2123286441Srpaulo uint32_t alive_counter_ptr; 2124286441Srpaulo uint32_t scd_base_ptr; /* SRAM address for SCD */ 2125286441Srpaulo} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2126286441Srpaulo 2127330183Seadlerstruct iwm_mvm_alive_resp_ver2 { 2128303628Ssbruno uint16_t status; 2129303628Ssbruno uint16_t flags; 2130303628Ssbruno uint8_t ucode_minor; 2131303628Ssbruno uint8_t ucode_major; 2132303628Ssbruno uint16_t id; 2133303628Ssbruno uint8_t api_minor; 2134303628Ssbruno uint8_t api_major; 2135303628Ssbruno uint8_t ver_subtype; 2136303628Ssbruno uint8_t ver_type; 2137303628Ssbruno uint8_t mac; 2138303628Ssbruno uint8_t opt; 2139303628Ssbruno uint16_t reserved2; 2140303628Ssbruno uint32_t timestamp; 2141303628Ssbruno uint32_t error_event_table_ptr; /* SRAM address for error log */ 2142303628Ssbruno uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2143303628Ssbruno uint32_t cpu_register_ptr; 2144303628Ssbruno uint32_t dbgm_config_ptr; 2145303628Ssbruno uint32_t alive_counter_ptr; 2146303628Ssbruno uint32_t scd_base_ptr; /* SRAM address for SCD */ 2147303628Ssbruno uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2148303628Ssbruno uint32_t st_fwrd_size; 2149330183Seadler uint8_t umac_minor; /* UMAC version: minor */ 2150330183Seadler uint8_t umac_major; /* UMAC version: major */ 2151330183Seadler uint16_t umac_id; /* UMAC version: id */ 2152330183Seadler uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2153303628Ssbruno uint32_t dbg_print_buff_addr; 2154303628Ssbruno} __packed; /* ALIVE_RES_API_S_VER_2 */ 2155303628Ssbruno 2156330183Seadlerstruct iwm_mvm_alive_resp { 2157303628Ssbruno uint16_t status; 2158303628Ssbruno uint16_t flags; 2159303628Ssbruno uint32_t ucode_minor; 2160303628Ssbruno uint32_t ucode_major; 2161303628Ssbruno uint8_t ver_subtype; 2162303628Ssbruno uint8_t ver_type; 2163303628Ssbruno uint8_t mac; 2164303628Ssbruno uint8_t opt; 2165303628Ssbruno uint32_t timestamp; 2166303628Ssbruno uint32_t error_event_table_ptr; /* SRAM address for error log */ 2167303628Ssbruno uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2168303628Ssbruno uint32_t cpu_register_ptr; 2169303628Ssbruno uint32_t dbgm_config_ptr; 2170303628Ssbruno uint32_t alive_counter_ptr; 2171303628Ssbruno uint32_t scd_base_ptr; /* SRAM address for SCD */ 2172303628Ssbruno uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2173303628Ssbruno uint32_t st_fwrd_size; 2174303628Ssbruno uint32_t umac_minor; /* UMAC version: minor */ 2175303628Ssbruno uint32_t umac_major; /* UMAC version: major */ 2176330183Seadler uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2177303628Ssbruno uint32_t dbg_print_buff_addr; 2178303628Ssbruno} __packed; /* ALIVE_RES_API_S_VER_3 */ 2179303628Ssbruno 2180286441Srpaulo/* Error response/notification */ 2181286441Srpauloenum { 2182286441Srpaulo IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2183286441Srpaulo IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2184286441Srpaulo IWM_FW_ERR_SERVICE = 0x2, 2185286441Srpaulo IWM_FW_ERR_ARC_MEMORY = 0x3, 2186286441Srpaulo IWM_FW_ERR_ARC_CODE = 0x4, 2187286441Srpaulo IWM_FW_ERR_WATCH_DOG = 0x5, 2188286441Srpaulo IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2189286441Srpaulo IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2190286441Srpaulo IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2191286441Srpaulo IWM_FW_ERR_UNEXPECTED = 0xFE, 2192286441Srpaulo IWM_FW_ERR_FATAL = 0xFF 2193286441Srpaulo}; 2194286441Srpaulo 2195286441Srpaulo/** 2196286441Srpaulo * struct iwm_error_resp - FW error indication 2197286441Srpaulo * ( IWM_REPLY_ERROR = 0x2 ) 2198286441Srpaulo * @error_type: one of IWM_FW_ERR_* 2199298955Spfg * @cmd_id: the command ID for which the error occurred 2200286441Srpaulo * @bad_cmd_seq_num: sequence number of the erroneous command 2201286441Srpaulo * @error_service: which service created the error, applicable only if 2202286441Srpaulo * error_type = 2, otherwise 0 2203286441Srpaulo * @timestamp: TSF in usecs. 2204286441Srpaulo */ 2205286441Srpaulostruct iwm_error_resp { 2206286441Srpaulo uint32_t error_type; 2207286441Srpaulo uint8_t cmd_id; 2208286441Srpaulo uint8_t reserved1; 2209286441Srpaulo uint16_t bad_cmd_seq_num; 2210286441Srpaulo uint32_t error_service; 2211286441Srpaulo uint64_t timestamp; 2212286441Srpaulo} __packed; 2213286441Srpaulo 2214286441Srpaulo 2215286441Srpaulo/* Common PHY, MAC and Bindings definitions */ 2216286441Srpaulo 2217286441Srpaulo#define IWM_MAX_MACS_IN_BINDING (3) 2218286441Srpaulo#define IWM_MAX_BINDINGS (4) 2219286441Srpaulo#define IWM_AUX_BINDING_INDEX (3) 2220286441Srpaulo#define IWM_MAX_PHYS (4) 2221286441Srpaulo 2222286441Srpaulo/* Used to extract ID and color from the context dword */ 2223286441Srpaulo#define IWM_FW_CTXT_ID_POS (0) 2224286441Srpaulo#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2225286441Srpaulo#define IWM_FW_CTXT_COLOR_POS (8) 2226286441Srpaulo#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2227286441Srpaulo#define IWM_FW_CTXT_INVALID (0xffffffff) 2228286441Srpaulo 2229286441Srpaulo#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2230286441Srpaulo (_color << IWM_FW_CTXT_COLOR_POS)) 2231286441Srpaulo 2232286441Srpaulo/* Possible actions on PHYs, MACs and Bindings */ 2233286441Srpauloenum { 2234286441Srpaulo IWM_FW_CTXT_ACTION_STUB = 0, 2235286441Srpaulo IWM_FW_CTXT_ACTION_ADD, 2236286441Srpaulo IWM_FW_CTXT_ACTION_MODIFY, 2237286441Srpaulo IWM_FW_CTXT_ACTION_REMOVE, 2238286441Srpaulo IWM_FW_CTXT_ACTION_NUM 2239286441Srpaulo}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2240286441Srpaulo 2241286441Srpaulo/* Time Events */ 2242286441Srpaulo 2243286441Srpaulo/* Time Event types, according to MAC type */ 2244286441Srpauloenum iwm_time_event_type { 2245286441Srpaulo /* BSS Station Events */ 2246286441Srpaulo IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2247286441Srpaulo IWM_TE_BSS_STA_ASSOC, 2248286441Srpaulo IWM_TE_BSS_EAP_DHCP_PROT, 2249286441Srpaulo IWM_TE_BSS_QUIET_PERIOD, 2250286441Srpaulo 2251286441Srpaulo /* P2P Device Events */ 2252286441Srpaulo IWM_TE_P2P_DEVICE_DISCOVERABLE, 2253286441Srpaulo IWM_TE_P2P_DEVICE_LISTEN, 2254286441Srpaulo IWM_TE_P2P_DEVICE_ACTION_SCAN, 2255286441Srpaulo IWM_TE_P2P_DEVICE_FULL_SCAN, 2256286441Srpaulo 2257286441Srpaulo /* P2P Client Events */ 2258286441Srpaulo IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2259286441Srpaulo IWM_TE_P2P_CLIENT_ASSOC, 2260286441Srpaulo IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2261286441Srpaulo 2262286441Srpaulo /* P2P GO Events */ 2263286441Srpaulo IWM_TE_P2P_GO_ASSOC_PROT, 2264286441Srpaulo IWM_TE_P2P_GO_REPETITIVE_NOA, 2265286441Srpaulo IWM_TE_P2P_GO_CT_WINDOW, 2266286441Srpaulo 2267286441Srpaulo /* WiDi Sync Events */ 2268286441Srpaulo IWM_TE_WIDI_TX_SYNC, 2269286441Srpaulo 2270286441Srpaulo IWM_TE_MAX 2271286441Srpaulo}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2272286441Srpaulo 2273286441Srpaulo 2274286441Srpaulo 2275286441Srpaulo/* Time event - defines for command API v1 */ 2276286441Srpaulo 2277286441Srpaulo/* 2278286441Srpaulo * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2279286441Srpaulo * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2280286441Srpaulo * the first fragment is scheduled. 2281286441Srpaulo * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2282286441Srpaulo * the first 2 fragments are scheduled. 2283286441Srpaulo * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2284286441Srpaulo * number of fragments are valid. 2285286441Srpaulo * 2286286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2287286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2288286441Srpaulo * scheduled. 2289286441Srpaulo */ 2290286441Srpauloenum { 2291286441Srpaulo IWM_TE_V1_FRAG_NONE = 0, 2292286441Srpaulo IWM_TE_V1_FRAG_SINGLE = 1, 2293286441Srpaulo IWM_TE_V1_FRAG_DUAL = 2, 2294286441Srpaulo IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2295286441Srpaulo}; 2296286441Srpaulo 2297286441Srpaulo/* If a Time Event can be fragmented, this is the max number of fragments */ 2298286441Srpaulo#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2299286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2300286441Srpaulo#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2301286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2302286441Srpaulo#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2303286441Srpaulo 2304286441Srpaulo/* Time Event dependencies: none, on another TE, or in a specific time */ 2305286441Srpauloenum { 2306286441Srpaulo IWM_TE_V1_INDEPENDENT = 0, 2307286441Srpaulo IWM_TE_V1_DEP_OTHER = (1 << 0), 2308286441Srpaulo IWM_TE_V1_DEP_TSF = (1 << 1), 2309286441Srpaulo IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2310286441Srpaulo}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2311286441Srpaulo 2312286441Srpaulo/* 2313286441Srpaulo * @IWM_TE_V1_NOTIF_NONE: no notifications 2314286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2315286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2316286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2317286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2318286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2319286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2320286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2321286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2322286441Srpaulo * 2323286441Srpaulo * Supported Time event notifications configuration. 2324286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2325286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2326286441Srpaulo * notification the status is always success. There is no start/end fragment 2327286441Srpaulo * notification for monolithic events. 2328286441Srpaulo */ 2329286441Srpauloenum { 2330286441Srpaulo IWM_TE_V1_NOTIF_NONE = 0, 2331286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2332286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2333286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2334286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2335286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2336286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2337286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2338286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2339303628Ssbruno IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2340286441Srpaulo}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2341286441Srpaulo 2342330195Seadler/* Time event - defines for command API */ 2343286441Srpaulo 2344286441Srpaulo/* 2345286441Srpaulo * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2346286441Srpaulo * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2347286441Srpaulo * the first fragment is scheduled. 2348286441Srpaulo * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2349286441Srpaulo * the first 2 fragments are scheduled. 2350286441Srpaulo * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2351286441Srpaulo * number of fragments are valid. 2352286441Srpaulo * 2353286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2354286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2355286441Srpaulo * scheduled. 2356286441Srpaulo */ 2357286441Srpauloenum { 2358286441Srpaulo IWM_TE_V2_FRAG_NONE = 0, 2359286441Srpaulo IWM_TE_V2_FRAG_SINGLE = 1, 2360286441Srpaulo IWM_TE_V2_FRAG_DUAL = 2, 2361286441Srpaulo IWM_TE_V2_FRAG_MAX = 0xfe, 2362286441Srpaulo IWM_TE_V2_FRAG_ENDLESS = 0xff 2363286441Srpaulo}; 2364286441Srpaulo 2365286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2366286441Srpaulo#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2367286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2368286441Srpaulo#define IWM_TE_V2_REPEAT_MAX 0xfe 2369286441Srpaulo 2370286441Srpaulo#define IWM_TE_V2_PLACEMENT_POS 12 2371286441Srpaulo#define IWM_TE_V2_ABSENCE_POS 15 2372286441Srpaulo 2373330195Seadler/* Time event policy values 2374286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2375286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2376286441Srpaulo * notification the status is always success. There is no start/end fragment 2377286441Srpaulo * notification for monolithic events. 2378286441Srpaulo * 2379286441Srpaulo * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2380286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2381286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2382286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2383286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2384286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2385286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2386286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2387286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2388286441Srpaulo * @IWM_TE_V2_DEP_OTHER: depends on another time event 2389286441Srpaulo * @IWM_TE_V2_DEP_TSF: depends on a specific time 2390286441Srpaulo * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2391286441Srpaulo * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2392286441Srpaulo */ 2393286441Srpauloenum { 2394286441Srpaulo IWM_TE_V2_DEFAULT_POLICY = 0x0, 2395286441Srpaulo 2396286441Srpaulo /* notifications (event start/stop, fragment start/stop) */ 2397286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2398286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2399286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2400286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2401286441Srpaulo 2402286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2403286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2404286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2405286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2406286441Srpaulo 2407286441Srpaulo IWM_TE_V2_NOTIF_MSK = 0xff, 2408286441Srpaulo 2409286441Srpaulo /* placement characteristics */ 2410286441Srpaulo IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2411286441Srpaulo IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2412286441Srpaulo IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2413286441Srpaulo 2414286441Srpaulo /* are we present or absent during the Time Event. */ 2415286441Srpaulo IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2416286441Srpaulo}; 2417286441Srpaulo 2418286441Srpaulo/** 2419330195Seadler * struct iwm_time_event_cmd_api - configuring Time Events 2420286441Srpaulo * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2421286441Srpaulo * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2422286441Srpaulo * ( IWM_TIME_EVENT_CMD = 0x29 ) 2423286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2424286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2425286441Srpaulo * @id: this field has two meanings, depending on the action: 2426286441Srpaulo * If the action is ADD, then it means the type of event to add. 2427286441Srpaulo * For all other actions it is the unique event ID assigned when the 2428286441Srpaulo * event was added by the FW. 2429286441Srpaulo * @apply_time: When to start the Time Event (in GP2) 2430286441Srpaulo * @max_delay: maximum delay to event's start (apply time), in TU 2431286441Srpaulo * @depends_on: the unique ID of the event we depend on (if any) 2432286441Srpaulo * @interval: interval between repetitions, in TU 2433286441Srpaulo * @duration: duration of event in TU 2434286441Srpaulo * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2435286441Srpaulo * @max_frags: maximal number of fragments the Time Event can be divided to 2436286441Srpaulo * @policy: defines whether uCode shall notify the host or other uCode modules 2437286441Srpaulo * on event and/or fragment start and/or end 2438286441Srpaulo * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2439286441Srpaulo * IWM_TE_EVENT_SOCIOPATHIC 2440286441Srpaulo * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2441286441Srpaulo */ 2442330195Seadlerstruct iwm_time_event_cmd { 2443286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2444286441Srpaulo uint32_t id_and_color; 2445286441Srpaulo uint32_t action; 2446286441Srpaulo uint32_t id; 2447286441Srpaulo /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2448286441Srpaulo uint32_t apply_time; 2449286441Srpaulo uint32_t max_delay; 2450286441Srpaulo uint32_t depends_on; 2451286441Srpaulo uint32_t interval; 2452286441Srpaulo uint32_t duration; 2453286441Srpaulo uint8_t repeat; 2454286441Srpaulo uint8_t max_frags; 2455286441Srpaulo uint16_t policy; 2456286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2457286441Srpaulo 2458286441Srpaulo/** 2459286441Srpaulo * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2460286441Srpaulo * @status: bit 0 indicates success, all others specify errors 2461286441Srpaulo * @id: the Time Event type 2462286441Srpaulo * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2463286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2464286441Srpaulo */ 2465286441Srpaulostruct iwm_time_event_resp { 2466286441Srpaulo uint32_t status; 2467286441Srpaulo uint32_t id; 2468286441Srpaulo uint32_t unique_id; 2469286441Srpaulo uint32_t id_and_color; 2470286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2471286441Srpaulo 2472286441Srpaulo/** 2473286441Srpaulo * struct iwm_time_event_notif - notifications of time event start/stop 2474286441Srpaulo * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2475286441Srpaulo * @timestamp: action timestamp in GP2 2476286441Srpaulo * @session_id: session's unique id 2477286441Srpaulo * @unique_id: unique id of the Time Event itself 2478286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2479286441Srpaulo * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2480286441Srpaulo * @status: true if scheduled, false otherwise (not executed) 2481286441Srpaulo */ 2482286441Srpaulostruct iwm_time_event_notif { 2483286441Srpaulo uint32_t timestamp; 2484286441Srpaulo uint32_t session_id; 2485286441Srpaulo uint32_t unique_id; 2486286441Srpaulo uint32_t id_and_color; 2487286441Srpaulo uint32_t action; 2488286441Srpaulo uint32_t status; 2489286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2490286441Srpaulo 2491286441Srpaulo 2492286441Srpaulo/* Bindings and Time Quota */ 2493286441Srpaulo 2494286441Srpaulo/** 2495286441Srpaulo * struct iwm_binding_cmd - configuring bindings 2496286441Srpaulo * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2497286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2498286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2499286441Srpaulo * @macs: array of MAC id and colors which belong to the binding 2500286441Srpaulo * @phy: PHY id and color which belongs to the binding 2501286441Srpaulo */ 2502286441Srpaulostruct iwm_binding_cmd { 2503286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2504286441Srpaulo uint32_t id_and_color; 2505286441Srpaulo uint32_t action; 2506286441Srpaulo /* IWM_BINDING_DATA_API_S_VER_1 */ 2507286441Srpaulo uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2508286441Srpaulo uint32_t phy; 2509286441Srpaulo} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2510286441Srpaulo 2511286441Srpaulo/* The maximal number of fragments in the FW's schedule session */ 2512286441Srpaulo#define IWM_MVM_MAX_QUOTA 128 2513286441Srpaulo 2514286441Srpaulo/** 2515286441Srpaulo * struct iwm_time_quota_data - configuration of time quota per binding 2516286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2517286441Srpaulo * @quota: absolute time quota in TU. The scheduler will try to divide the 2518286441Srpaulo * remainig quota (after Time Events) according to this quota. 2519286441Srpaulo * @max_duration: max uninterrupted context duration in TU 2520286441Srpaulo */ 2521286441Srpaulostruct iwm_time_quota_data { 2522286441Srpaulo uint32_t id_and_color; 2523286441Srpaulo uint32_t quota; 2524286441Srpaulo uint32_t max_duration; 2525286441Srpaulo} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2526286441Srpaulo 2527286441Srpaulo/** 2528286441Srpaulo * struct iwm_time_quota_cmd - configuration of time quota between bindings 2529286441Srpaulo * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2530286441Srpaulo * @quotas: allocations per binding 2531286441Srpaulo */ 2532286441Srpaulostruct iwm_time_quota_cmd { 2533286441Srpaulo struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2534286441Srpaulo} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2535286441Srpaulo 2536286441Srpaulo 2537286441Srpaulo/* PHY context */ 2538286441Srpaulo 2539286441Srpaulo/* Supported bands */ 2540286441Srpaulo#define IWM_PHY_BAND_5 (0) 2541286441Srpaulo#define IWM_PHY_BAND_24 (1) 2542286441Srpaulo 2543286441Srpaulo/* Supported channel width, vary if there is VHT support */ 2544286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2545286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2546286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2547286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2548286441Srpaulo 2549286441Srpaulo/* 2550286441Srpaulo * Control channel position: 2551286441Srpaulo * For legacy set bit means upper channel, otherwise lower. 2552286441Srpaulo * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2553286441Srpaulo * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2554286441Srpaulo * center_freq 2555286441Srpaulo * | 2556286441Srpaulo * 40Mhz |_______|_______| 2557286441Srpaulo * 80Mhz |_______|_______|_______|_______| 2558286441Srpaulo * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2559286441Srpaulo * code 011 010 001 000 | 100 101 110 111 2560286441Srpaulo */ 2561286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2562286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2563286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2564286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2565286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2566286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2567286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2568286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2569286441Srpaulo 2570286441Srpaulo/* 2571286441Srpaulo * @band: IWM_PHY_BAND_* 2572286441Srpaulo * @channel: channel number 2573286441Srpaulo * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2574286441Srpaulo * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2575286441Srpaulo */ 2576286441Srpaulostruct iwm_fw_channel_info { 2577286441Srpaulo uint8_t band; 2578286441Srpaulo uint8_t channel; 2579286441Srpaulo uint8_t width; 2580286441Srpaulo uint8_t ctrl_pos; 2581286441Srpaulo} __packed; 2582286441Srpaulo 2583286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2584286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2585286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2586286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2587286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2588286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2589286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2590286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2591286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2592286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2593286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2594286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2595286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2596286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2597286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2598286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2599286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2600286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2601286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2602286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2603286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2604286441Srpaulo 2605286441Srpaulo/* TODO: fix the value, make it depend on firmware at runtime? */ 2606286441Srpaulo#define IWM_NUM_PHY_CTX 3 2607286441Srpaulo 2608286441Srpaulo/* TODO: complete missing documentation */ 2609286441Srpaulo/** 2610286441Srpaulo * struct iwm_phy_context_cmd - config of the PHY context 2611286441Srpaulo * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2612286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2613286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2614286441Srpaulo * @apply_time: 0 means immediate apply and context switch. 2615286441Srpaulo * other value means apply new params after X usecs 2616286441Srpaulo * @tx_param_color: ??? 2617286441Srpaulo * @channel_info: 2618286441Srpaulo * @txchain_info: ??? 2619286441Srpaulo * @rxchain_info: ??? 2620286441Srpaulo * @acquisition_data: ??? 2621286441Srpaulo * @dsp_cfg_flags: set to 0 2622286441Srpaulo */ 2623286441Srpaulostruct iwm_phy_context_cmd { 2624286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2625286441Srpaulo uint32_t id_and_color; 2626286441Srpaulo uint32_t action; 2627286441Srpaulo /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2628286441Srpaulo uint32_t apply_time; 2629286441Srpaulo uint32_t tx_param_color; 2630286441Srpaulo struct iwm_fw_channel_info ci; 2631286441Srpaulo uint32_t txchain_info; 2632286441Srpaulo uint32_t rxchain_info; 2633286441Srpaulo uint32_t acquisition_data; 2634286441Srpaulo uint32_t dsp_cfg_flags; 2635286441Srpaulo} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2636286441Srpaulo 2637286441Srpaulo#define IWM_RX_INFO_PHY_CNT 8 2638286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2639286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2640286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2641286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2642286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2643286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2644286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2645286441Srpaulo 2646286441Srpaulo#define IWM_RX_INFO_AGC_IDX 1 2647286441Srpaulo#define IWM_RX_INFO_RSSI_AB_IDX 2 2648286441Srpaulo#define IWM_OFDM_AGC_A_MSK 0x0000007f 2649286441Srpaulo#define IWM_OFDM_AGC_A_POS 0 2650286441Srpaulo#define IWM_OFDM_AGC_B_MSK 0x00003f80 2651286441Srpaulo#define IWM_OFDM_AGC_B_POS 7 2652286441Srpaulo#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2653286441Srpaulo#define IWM_OFDM_AGC_CODE_POS 20 2654286441Srpaulo#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2655286441Srpaulo#define IWM_OFDM_RSSI_A_POS 0 2656286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2657286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2658286441Srpaulo#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2659286441Srpaulo#define IWM_OFDM_RSSI_B_POS 16 2660286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2661286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2662286441Srpaulo 2663286441Srpaulo/** 2664286441Srpaulo * struct iwm_rx_phy_info - phy info 2665286441Srpaulo * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2666286441Srpaulo * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2667286441Srpaulo * @cfg_phy_cnt: configurable DSP phy data byte count 2668286441Srpaulo * @stat_id: configurable DSP phy data set ID 2669286441Srpaulo * @reserved1: 2670286441Srpaulo * @system_timestamp: GP2 at on air rise 2671286441Srpaulo * @timestamp: TSF at on air rise 2672286441Srpaulo * @beacon_time_stamp: beacon at on-air rise 2673286441Srpaulo * @phy_flags: general phy flags: band, modulation, ... 2674286441Srpaulo * @channel: channel number 2675286441Srpaulo * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2676286441Srpaulo * @rate_n_flags: IWM_RATE_MCS_* 2677286441Srpaulo * @byte_count: frame's byte-count 2678286441Srpaulo * @frame_time: frame's time on the air, based on byte count and frame rate 2679286441Srpaulo * calculation 2680286441Srpaulo * @mac_active_msk: what MACs were active when the frame was received 2681286441Srpaulo * 2682286441Srpaulo * Before each Rx, the device sends this data. It contains PHY information 2683286441Srpaulo * about the reception of the packet. 2684286441Srpaulo */ 2685286441Srpaulostruct iwm_rx_phy_info { 2686286441Srpaulo uint8_t non_cfg_phy_cnt; 2687286441Srpaulo uint8_t cfg_phy_cnt; 2688286441Srpaulo uint8_t stat_id; 2689286441Srpaulo uint8_t reserved1; 2690286441Srpaulo uint32_t system_timestamp; 2691286441Srpaulo uint64_t timestamp; 2692286441Srpaulo uint32_t beacon_time_stamp; 2693286441Srpaulo uint16_t phy_flags; 2694286441Srpaulo#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2695286441Srpaulo uint16_t channel; 2696286441Srpaulo uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2697286441Srpaulo uint8_t rate; 2698286441Srpaulo uint8_t rflags; 2699286441Srpaulo uint16_t xrflags; 2700286441Srpaulo uint32_t byte_count; 2701286441Srpaulo uint16_t mac_active_msk; 2702286441Srpaulo uint16_t frame_time; 2703286441Srpaulo} __packed; 2704286441Srpaulo 2705286441Srpaulostruct iwm_rx_mpdu_res_start { 2706286441Srpaulo uint16_t byte_count; 2707286441Srpaulo uint16_t reserved; 2708286441Srpaulo} __packed; 2709286441Srpaulo 2710286441Srpaulo/** 2711286441Srpaulo * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2712286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2713286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2714286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2715286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2716286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2717286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2718286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2719286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2720286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2721286441Srpaulo */ 2722286441Srpauloenum iwm_rx_phy_flags { 2723286441Srpaulo IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2724286441Srpaulo IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2725286441Srpaulo IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2726286441Srpaulo IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2727286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2728286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2729286441Srpaulo IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2730286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2731286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2732286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2733286441Srpaulo}; 2734286441Srpaulo 2735286441Srpaulo/** 2736286441Srpaulo * enum iwm_mvm_rx_status - written by fw for each Rx packet 2737286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2738286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2739286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2740286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2741286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2742286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2743286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2744286441Srpaulo * in the driver. 2745286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2746286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2747286441Srpaulo * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2748286441Srpaulo * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2749286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2750286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2751286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2752286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2753286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2754286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2755286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2756286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2757286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2758286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2759286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2760286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2761286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2762286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2763286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2764286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2765286441Srpaulo * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2766286441Srpaulo */ 2767286441Srpauloenum iwm_mvm_rx_status { 2768286441Srpaulo IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2769286441Srpaulo IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2770286441Srpaulo IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2771286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2772286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2773286441Srpaulo IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2774286441Srpaulo IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2775286441Srpaulo IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2776286441Srpaulo IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2777286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2778286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2779286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2780286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2781286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2782286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2783286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2784286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2785286441Srpaulo IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2786286441Srpaulo IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2787286441Srpaulo IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2788286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2789286441Srpaulo IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2790286441Srpaulo IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2791286441Srpaulo IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2792286441Srpaulo IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2793286441Srpaulo IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2794286441Srpaulo IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2795286441Srpaulo}; 2796286441Srpaulo 2797286441Srpaulo/** 2798286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2799286441Srpaulo * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2800286441Srpaulo * @radio_flavor: 2801286441Srpaulo * @radio_step: 2802286441Srpaulo * @radio_dash: 2803286441Srpaulo */ 2804286441Srpaulostruct iwm_radio_version_notif { 2805286441Srpaulo uint32_t radio_flavor; 2806286441Srpaulo uint32_t radio_step; 2807286441Srpaulo uint32_t radio_dash; 2808286441Srpaulo} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2809286441Srpaulo 2810286441Srpauloenum iwm_card_state_flags { 2811286441Srpaulo IWM_CARD_ENABLED = 0x00, 2812286441Srpaulo IWM_HW_CARD_DISABLED = 0x01, 2813286441Srpaulo IWM_SW_CARD_DISABLED = 0x02, 2814286441Srpaulo IWM_CT_KILL_CARD_DISABLED = 0x04, 2815286441Srpaulo IWM_HALT_CARD_DISABLED = 0x08, 2816286441Srpaulo IWM_CARD_DISABLED_MSK = 0x0f, 2817286441Srpaulo IWM_CARD_IS_RX_ON = 0x10, 2818286441Srpaulo}; 2819286441Srpaulo 2820286441Srpaulo/** 2821286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2822286441Srpaulo * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2823286441Srpaulo * @flags: %iwm_card_state_flags 2824286441Srpaulo */ 2825286441Srpaulostruct iwm_card_state_notif { 2826286441Srpaulo uint32_t flags; 2827286441Srpaulo} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2828286441Srpaulo 2829286441Srpaulo/** 2830286441Srpaulo * struct iwm_missed_beacons_notif - information on missed beacons 2831286441Srpaulo * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2832286441Srpaulo * @mac_id: interface ID 2833286441Srpaulo * @consec_missed_beacons_since_last_rx: number of consecutive missed 2834286441Srpaulo * beacons since last RX. 2835286441Srpaulo * @consec_missed_beacons: number of consecutive missed beacons 2836286441Srpaulo * @num_expected_beacons: 2837286441Srpaulo * @num_recvd_beacons: 2838286441Srpaulo */ 2839286441Srpaulostruct iwm_missed_beacons_notif { 2840286441Srpaulo uint32_t mac_id; 2841286441Srpaulo uint32_t consec_missed_beacons_since_last_rx; 2842286441Srpaulo uint32_t consec_missed_beacons; 2843286441Srpaulo uint32_t num_expected_beacons; 2844286441Srpaulo uint32_t num_recvd_beacons; 2845286441Srpaulo} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2846286441Srpaulo 2847286441Srpaulo/** 2848303628Ssbruno * struct iwm_mfuart_load_notif - mfuart image version & status 2849303628Ssbruno * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2850303628Ssbruno * @installed_ver: installed image version 2851303628Ssbruno * @external_ver: external image version 2852303628Ssbruno * @status: MFUART loading status 2853303628Ssbruno * @duration: MFUART loading time 2854303628Ssbruno*/ 2855303628Ssbrunostruct iwm_mfuart_load_notif { 2856303628Ssbruno uint32_t installed_ver; 2857303628Ssbruno uint32_t external_ver; 2858303628Ssbruno uint32_t status; 2859303628Ssbruno uint32_t duration; 2860303628Ssbruno} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2861303628Ssbruno 2862303628Ssbruno/** 2863286441Srpaulo * struct iwm_set_calib_default_cmd - set default value for calibration. 2864286441Srpaulo * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2865286441Srpaulo * @calib_index: the calibration to set value for 2866286441Srpaulo * @length: of data 2867286441Srpaulo * @data: the value to set for the calibration result 2868286441Srpaulo */ 2869286441Srpaulostruct iwm_set_calib_default_cmd { 2870286441Srpaulo uint16_t calib_index; 2871286441Srpaulo uint16_t length; 2872286441Srpaulo uint8_t data[0]; 2873286441Srpaulo} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2874286441Srpaulo 2875286441Srpaulo#define IWM_MAX_PORT_ID_NUM 2 2876286441Srpaulo#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2877286441Srpaulo 2878286441Srpaulo/** 2879286441Srpaulo * struct iwm_mcast_filter_cmd - configure multicast filter. 2880286441Srpaulo * @filter_own: Set 1 to filter out multicast packets sent by station itself 2881286441Srpaulo * @port_id: Multicast MAC addresses array specifier. This is a strange way 2882286441Srpaulo * to identify network interface adopted in host-device IF. 2883286441Srpaulo * It is used by FW as index in array of addresses. This array has 2884286441Srpaulo * IWM_MAX_PORT_ID_NUM members. 2885286441Srpaulo * @count: Number of MAC addresses in the array 2886286441Srpaulo * @pass_all: Set 1 to pass all multicast packets. 2887286441Srpaulo * @bssid: current association BSSID. 2888286441Srpaulo * @addr_list: Place holder for array of MAC addresses. 2889286441Srpaulo * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2890286441Srpaulo */ 2891286441Srpaulostruct iwm_mcast_filter_cmd { 2892286441Srpaulo uint8_t filter_own; 2893286441Srpaulo uint8_t port_id; 2894286441Srpaulo uint8_t count; 2895286441Srpaulo uint8_t pass_all; 2896286441Srpaulo uint8_t bssid[6]; 2897286441Srpaulo uint8_t reserved[2]; 2898286441Srpaulo uint8_t addr_list[0]; 2899286441Srpaulo} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2900286441Srpaulo 2901330224Seadler/* 2902330224Seadler * The first MAC indices (starting from 0) 2903330224Seadler * are available to the driver, AUX follows 2904330224Seadler */ 2905330224Seadler#define IWM_MAC_INDEX_AUX 4 2906330224Seadler#define IWM_MAC_INDEX_MIN_DRIVER 0 2907330224Seadler#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2908330224Seadler#define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1) 2909330224Seadler 2910330224Seadler/*********************************** 2911330224Seadler * Statistics API 2912330224Seadler ***********************************/ 2913286441Srpaulostruct iwm_mvm_statistics_dbg { 2914286441Srpaulo uint32_t burst_check; 2915286441Srpaulo uint32_t burst_count; 2916286441Srpaulo uint32_t wait_for_silence_timeout_cnt; 2917286441Srpaulo uint32_t reserved[3]; 2918286441Srpaulo} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2919286441Srpaulo 2920286441Srpaulostruct iwm_mvm_statistics_div { 2921286441Srpaulo uint32_t tx_on_a; 2922286441Srpaulo uint32_t tx_on_b; 2923286441Srpaulo uint32_t exec_time; 2924286441Srpaulo uint32_t probe_time; 2925286441Srpaulo uint32_t rssi_ant; 2926286441Srpaulo uint32_t reserved2; 2927286441Srpaulo} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2928286441Srpaulo 2929286441Srpaulostruct iwm_mvm_statistics_rx_non_phy { 2930286441Srpaulo uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2931286441Srpaulo uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2932286441Srpaulo uint32_t non_bssid_frames; /* number of frames with BSSID that 2933286441Srpaulo * doesn't belong to the STA BSSID */ 2934286441Srpaulo uint32_t filtered_frames; /* count frames that were dumped in the 2935286441Srpaulo * filtering process */ 2936286441Srpaulo uint32_t non_channel_beacons; /* beacons with our bss id but not on 2937286441Srpaulo * our serving channel */ 2938286441Srpaulo uint32_t channel_beacons; /* beacons with our bss id and in our 2939286441Srpaulo * serving channel */ 2940286441Srpaulo uint32_t num_missed_bcon; /* number of missed beacons */ 2941286441Srpaulo uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2942286441Srpaulo * ADC was in saturation */ 2943286441Srpaulo uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2944286441Srpaulo * for INA */ 2945286441Srpaulo uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2946286441Srpaulo uint32_t interference_data_flag; /* flag for interference data 2947286441Srpaulo * availability. 1 when data is 2948286441Srpaulo * available. */ 2949286441Srpaulo uint32_t channel_load; /* counts RX Enable time in uSec */ 2950286441Srpaulo uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2951286441Srpaulo * and CCK) counter */ 2952286441Srpaulo uint32_t beacon_rssi_a; 2953286441Srpaulo uint32_t beacon_rssi_b; 2954286441Srpaulo uint32_t beacon_rssi_c; 2955286441Srpaulo uint32_t beacon_energy_a; 2956286441Srpaulo uint32_t beacon_energy_b; 2957286441Srpaulo uint32_t beacon_energy_c; 2958286441Srpaulo uint32_t num_bt_kills; 2959286441Srpaulo uint32_t mac_id; 2960286441Srpaulo uint32_t directed_data_mpdu; 2961286441Srpaulo} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2962286441Srpaulo 2963286441Srpaulostruct iwm_mvm_statistics_rx_phy { 2964286441Srpaulo uint32_t ina_cnt; 2965286441Srpaulo uint32_t fina_cnt; 2966286441Srpaulo uint32_t plcp_err; 2967286441Srpaulo uint32_t crc32_err; 2968286441Srpaulo uint32_t overrun_err; 2969286441Srpaulo uint32_t early_overrun_err; 2970286441Srpaulo uint32_t crc32_good; 2971286441Srpaulo uint32_t false_alarm_cnt; 2972286441Srpaulo uint32_t fina_sync_err_cnt; 2973286441Srpaulo uint32_t sfd_timeout; 2974286441Srpaulo uint32_t fina_timeout; 2975286441Srpaulo uint32_t unresponded_rts; 2976286441Srpaulo uint32_t rxe_frame_limit_overrun; 2977286441Srpaulo uint32_t sent_ack_cnt; 2978286441Srpaulo uint32_t sent_cts_cnt; 2979286441Srpaulo uint32_t sent_ba_rsp_cnt; 2980286441Srpaulo uint32_t dsp_self_kill; 2981286441Srpaulo uint32_t mh_format_err; 2982286441Srpaulo uint32_t re_acq_main_rssi_sum; 2983286441Srpaulo uint32_t reserved; 2984286441Srpaulo} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2985286441Srpaulo 2986286441Srpaulostruct iwm_mvm_statistics_rx_ht_phy { 2987286441Srpaulo uint32_t plcp_err; 2988286441Srpaulo uint32_t overrun_err; 2989286441Srpaulo uint32_t early_overrun_err; 2990286441Srpaulo uint32_t crc32_good; 2991286441Srpaulo uint32_t crc32_err; 2992286441Srpaulo uint32_t mh_format_err; 2993286441Srpaulo uint32_t agg_crc32_good; 2994286441Srpaulo uint32_t agg_mpdu_cnt; 2995286441Srpaulo uint32_t agg_cnt; 2996286441Srpaulo uint32_t unsupport_mcs; 2997286441Srpaulo} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 2998286441Srpaulo 2999330224Seadlerstruct iwm_mvm_statistics_tx_non_phy { 3000330224Seadler uint32_t preamble_cnt; 3001330224Seadler uint32_t rx_detected_cnt; 3002330224Seadler uint32_t bt_prio_defer_cnt; 3003330224Seadler uint32_t bt_prio_kill_cnt; 3004330224Seadler uint32_t few_bytes_cnt; 3005330224Seadler uint32_t cts_timeout; 3006330224Seadler uint32_t ack_timeout; 3007330224Seadler uint32_t expected_ack_cnt; 3008330224Seadler uint32_t actual_ack_cnt; 3009330224Seadler uint32_t dump_msdu_cnt; 3010330224Seadler uint32_t burst_abort_next_frame_mismatch_cnt; 3011330224Seadler uint32_t burst_abort_missing_next_frame_cnt; 3012330224Seadler uint32_t cts_timeout_collision; 3013330224Seadler uint32_t ack_or_ba_timeout_collision; 3014330224Seadler} __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */ 3015330224Seadler 3016286441Srpaulo#define IWM_MAX_CHAINS 3 3017286441Srpaulo 3018286441Srpaulostruct iwm_mvm_statistics_tx_non_phy_agg { 3019286441Srpaulo uint32_t ba_timeout; 3020286441Srpaulo uint32_t ba_reschedule_frames; 3021286441Srpaulo uint32_t scd_query_agg_frame_cnt; 3022286441Srpaulo uint32_t scd_query_no_agg; 3023286441Srpaulo uint32_t scd_query_agg; 3024286441Srpaulo uint32_t scd_query_mismatch; 3025286441Srpaulo uint32_t frame_not_ready; 3026286441Srpaulo uint32_t underrun; 3027286441Srpaulo uint32_t bt_prio_kill; 3028286441Srpaulo uint32_t rx_ba_rsp_cnt; 3029286441Srpaulo int8_t txpower[IWM_MAX_CHAINS]; 3030286441Srpaulo int8_t reserved; 3031286441Srpaulo uint32_t reserved2; 3032286441Srpaulo} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3033286441Srpaulo 3034286441Srpaulostruct iwm_mvm_statistics_tx_channel_width { 3035286441Srpaulo uint32_t ext_cca_narrow_ch20[1]; 3036286441Srpaulo uint32_t ext_cca_narrow_ch40[2]; 3037286441Srpaulo uint32_t ext_cca_narrow_ch80[3]; 3038286441Srpaulo uint32_t ext_cca_narrow_ch160[4]; 3039286441Srpaulo uint32_t last_tx_ch_width_indx; 3040286441Srpaulo uint32_t rx_detected_per_ch_width[4]; 3041286441Srpaulo uint32_t success_per_ch_width[4]; 3042286441Srpaulo uint32_t fail_per_ch_width[4]; 3043286441Srpaulo}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3044286441Srpaulo 3045286441Srpaulostruct iwm_mvm_statistics_tx { 3046330224Seadler struct iwm_mvm_statistics_tx_non_phy general; 3047286441Srpaulo struct iwm_mvm_statistics_tx_non_phy_agg agg; 3048286441Srpaulo struct iwm_mvm_statistics_tx_channel_width channel_width; 3049286441Srpaulo} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3050286441Srpaulo 3051286441Srpaulo 3052286441Srpaulostruct iwm_mvm_statistics_bt_activity { 3053286441Srpaulo uint32_t hi_priority_tx_req_cnt; 3054286441Srpaulo uint32_t hi_priority_tx_denied_cnt; 3055286441Srpaulo uint32_t lo_priority_tx_req_cnt; 3056286441Srpaulo uint32_t lo_priority_tx_denied_cnt; 3057286441Srpaulo uint32_t hi_priority_rx_req_cnt; 3058286441Srpaulo uint32_t hi_priority_rx_denied_cnt; 3059286441Srpaulo uint32_t lo_priority_rx_req_cnt; 3060286441Srpaulo uint32_t lo_priority_rx_denied_cnt; 3061286441Srpaulo} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3062286441Srpaulo 3063330224Seadlerstruct iwm_mvm_statistics_general_v8 { 3064330224Seadler uint32_t radio_temperature; 3065330224Seadler uint32_t radio_voltage; 3066330224Seadler struct iwm_mvm_statistics_dbg dbg; 3067330224Seadler uint32_t sleep_time; 3068330224Seadler uint32_t slots_out; 3069330224Seadler uint32_t slots_idle; 3070330224Seadler uint32_t ttl_timestamp; 3071330224Seadler struct iwm_mvm_statistics_div slow_div; 3072330224Seadler uint32_t rx_enable_counter; 3073330224Seadler /* 3074330224Seadler * num_of_sos_states: 3075330224Seadler * count the number of times we have to re-tune 3076330224Seadler * in order to get out of bad PHY status 3077330224Seadler */ 3078330224Seadler uint32_t num_of_sos_states; 3079286441Srpaulo uint32_t beacon_filtered; 3080286441Srpaulo uint32_t missed_beacons; 3081330224Seadler uint8_t beacon_filter_average_energy; 3082330224Seadler uint8_t beacon_filter_reason; 3083330224Seadler uint8_t beacon_filter_current_energy; 3084330224Seadler uint8_t beacon_filter_reserved; 3085286441Srpaulo uint32_t beacon_filter_delta_time; 3086286441Srpaulo struct iwm_mvm_statistics_bt_activity bt_activity; 3087330224Seadler uint64_t rx_time; 3088330224Seadler uint64_t on_time_rf; 3089330224Seadler uint64_t on_time_scan; 3090330224Seadler uint64_t tx_time; 3091330224Seadler uint32_t beacon_counter[IWM_NUM_MAC_INDEX]; 3092330224Seadler uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX]; 3093330224Seadler uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)]; 3094330224Seadler} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */ 3095286441Srpaulo 3096286441Srpaulostruct iwm_mvm_statistics_rx { 3097286441Srpaulo struct iwm_mvm_statistics_rx_phy ofdm; 3098286441Srpaulo struct iwm_mvm_statistics_rx_phy cck; 3099286441Srpaulo struct iwm_mvm_statistics_rx_non_phy general; 3100286441Srpaulo struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3101286441Srpaulo} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3102286441Srpaulo 3103286441Srpaulo/* 3104286441Srpaulo * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3105286441Srpaulo * 3106286441Srpaulo * By default, uCode issues this notification after receiving a beacon 3107286441Srpaulo * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3108330224Seadler * IWM_STATISTICS_CMD (0x9c), below. 3109286441Srpaulo */ 3110286441Srpaulo 3111330224Seadlerstruct iwm_notif_statistics_v10 { 3112286441Srpaulo uint32_t flag; 3113286441Srpaulo struct iwm_mvm_statistics_rx rx; 3114286441Srpaulo struct iwm_mvm_statistics_tx tx; 3115330224Seadler struct iwm_mvm_statistics_general_v8 general; 3116330224Seadler} __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */ 3117286441Srpaulo 3118330224Seadler#define IWM_STATISTICS_FLG_CLEAR 0x1 3119330224Seadler#define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2 3120330224Seadler 3121330224Seadlerstruct iwm_statistics_cmd { 3122330224Seadler uint32_t flags; 3123330224Seadler} __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */ 3124330224Seadler 3125286441Srpaulo/*********************************** 3126286441Srpaulo * Smart Fifo API 3127286441Srpaulo ***********************************/ 3128286441Srpaulo/* Smart Fifo state */ 3129286441Srpauloenum iwm_sf_state { 3130286441Srpaulo IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3131286441Srpaulo IWM_SF_FULL_ON, 3132286441Srpaulo IWM_SF_UNINIT, 3133286441Srpaulo IWM_SF_INIT_OFF, 3134286441Srpaulo IWM_SF_HW_NUM_STATES 3135286441Srpaulo}; 3136286441Srpaulo 3137286441Srpaulo/* Smart Fifo possible scenario */ 3138286441Srpauloenum iwm_sf_scenario { 3139286441Srpaulo IWM_SF_SCENARIO_SINGLE_UNICAST, 3140286441Srpaulo IWM_SF_SCENARIO_AGG_UNICAST, 3141286441Srpaulo IWM_SF_SCENARIO_MULTICAST, 3142286441Srpaulo IWM_SF_SCENARIO_BA_RESP, 3143286441Srpaulo IWM_SF_SCENARIO_TX_RESP, 3144286441Srpaulo IWM_SF_NUM_SCENARIO 3145286441Srpaulo}; 3146286441Srpaulo 3147286441Srpaulo#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3148286441Srpaulo#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3149286441Srpaulo 3150286441Srpaulo/* smart FIFO default values */ 3151286441Srpaulo#define IWM_SF_W_MARK_SISO 4096 3152286441Srpaulo#define IWM_SF_W_MARK_MIMO2 8192 3153286441Srpaulo#define IWM_SF_W_MARK_MIMO3 6144 3154286441Srpaulo#define IWM_SF_W_MARK_LEGACY 4096 3155286441Srpaulo#define IWM_SF_W_MARK_SCAN 4096 3156286441Srpaulo 3157303628Ssbruno/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3158303628Ssbruno#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3159303628Ssbruno#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3160303628Ssbruno#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3161303628Ssbruno#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3162330143Seadler#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3163303628Ssbruno#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3164303628Ssbruno#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3165303628Ssbruno#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3166303628Ssbruno#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3167303628Ssbruno#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3168303628Ssbruno 3169286441Srpaulo/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3170286441Srpaulo#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3171286441Srpaulo#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3172286441Srpaulo#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3173286441Srpaulo#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3174286441Srpaulo#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3175286441Srpaulo#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3176286441Srpaulo#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3177286441Srpaulo#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3178286441Srpaulo#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3179286441Srpaulo#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3180286441Srpaulo 3181286441Srpaulo#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3182286441Srpaulo 3183303628Ssbruno#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3184303628Ssbruno 3185286441Srpaulo/** 3186286441Srpaulo * Smart Fifo configuration command. 3187330143Seadler * @state: smart fifo state, types listed in iwm_sf_state. 3188298955Spfg * @watermark: Minimum allowed available free space in RXF for transient state. 3189286441Srpaulo * @long_delay_timeouts: aging and idle timer values for each scenario 3190286441Srpaulo * in long delay state. 3191286441Srpaulo * @full_on_timeouts: timer values for each scenario in full on state. 3192286441Srpaulo */ 3193286441Srpaulostruct iwm_sf_cfg_cmd { 3194330146Seadler uint32_t state; 3195286441Srpaulo uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3196286441Srpaulo uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3197286441Srpaulo uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3198286441Srpaulo} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3199286441Srpaulo 3200286441Srpaulo/* 3201286441Srpaulo * END mvm/fw-api.h 3202286441Srpaulo */ 3203286441Srpaulo 3204286441Srpaulo/* 3205286441Srpaulo * BEGIN mvm/fw-api-mac.h 3206286441Srpaulo */ 3207286441Srpaulo 3208286441Srpauloenum iwm_ac { 3209286441Srpaulo IWM_AC_BK, 3210286441Srpaulo IWM_AC_BE, 3211286441Srpaulo IWM_AC_VI, 3212286441Srpaulo IWM_AC_VO, 3213286441Srpaulo IWM_AC_NUM, 3214286441Srpaulo}; 3215286441Srpaulo 3216286441Srpaulo/** 3217286441Srpaulo * enum iwm_mac_protection_flags - MAC context flags 3218286441Srpaulo * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3219286441Srpaulo * this will require CCK RTS/CTS2self. 3220286441Srpaulo * RTS/CTS will protect full burst time. 3221286441Srpaulo * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3222286441Srpaulo * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3223286441Srpaulo * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3224286441Srpaulo */ 3225286441Srpauloenum iwm_mac_protection_flags { 3226286441Srpaulo IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3227286441Srpaulo IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3228286441Srpaulo IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3229286441Srpaulo IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3230286441Srpaulo}; 3231286441Srpaulo 3232286441Srpaulo#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3233286441Srpaulo#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3234286441Srpaulo 3235286441Srpaulo/** 3236286441Srpaulo * enum iwm_mac_types - Supported MAC types 3237286441Srpaulo * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3238286441Srpaulo * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3239286441Srpaulo * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3240286441Srpaulo * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3241286441Srpaulo * @IWM_FW_MAC_TYPE_IBSS: IBSS 3242286441Srpaulo * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3243286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3244286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3245286441Srpaulo * @IWM_FW_MAC_TYPE_GO: P2P GO 3246286441Srpaulo * @IWM_FW_MAC_TYPE_TEST: ? 3247286441Srpaulo * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3248286441Srpaulo */ 3249286441Srpauloenum iwm_mac_types { 3250286441Srpaulo IWM_FW_MAC_TYPE_FIRST = 1, 3251286441Srpaulo IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3252286441Srpaulo IWM_FW_MAC_TYPE_LISTENER, 3253286441Srpaulo IWM_FW_MAC_TYPE_PIBSS, 3254286441Srpaulo IWM_FW_MAC_TYPE_IBSS, 3255286441Srpaulo IWM_FW_MAC_TYPE_BSS_STA, 3256286441Srpaulo IWM_FW_MAC_TYPE_P2P_DEVICE, 3257286441Srpaulo IWM_FW_MAC_TYPE_P2P_STA, 3258286441Srpaulo IWM_FW_MAC_TYPE_GO, 3259286441Srpaulo IWM_FW_MAC_TYPE_TEST, 3260286441Srpaulo IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3261286441Srpaulo}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3262286441Srpaulo 3263286441Srpaulo/** 3264286441Srpaulo * enum iwm_tsf_id - TSF hw timer ID 3265286441Srpaulo * @IWM_TSF_ID_A: use TSF A 3266286441Srpaulo * @IWM_TSF_ID_B: use TSF B 3267286441Srpaulo * @IWM_TSF_ID_C: use TSF C 3268286441Srpaulo * @IWM_TSF_ID_D: use TSF D 3269286441Srpaulo * @IWM_NUM_TSF_IDS: number of TSF timers available 3270286441Srpaulo */ 3271286441Srpauloenum iwm_tsf_id { 3272286441Srpaulo IWM_TSF_ID_A = 0, 3273286441Srpaulo IWM_TSF_ID_B = 1, 3274286441Srpaulo IWM_TSF_ID_C = 2, 3275286441Srpaulo IWM_TSF_ID_D = 3, 3276286441Srpaulo IWM_NUM_TSF_IDS = 4, 3277286441Srpaulo}; /* IWM_TSF_ID_API_E_VER_1 */ 3278286441Srpaulo 3279286441Srpaulo/** 3280286441Srpaulo * struct iwm_mac_data_ap - configuration data for AP MAC context 3281286441Srpaulo * @beacon_time: beacon transmit time in system time 3282286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 3283286441Srpaulo * @bi: beacon interval in TU 3284286441Srpaulo * @bi_reciprocal: 2^32 / bi 3285286441Srpaulo * @dtim_interval: dtim transmit time in TU 3286286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval 3287286441Srpaulo * @mcast_qid: queue ID for multicast traffic 3288286441Srpaulo * @beacon_template: beacon template ID 3289286441Srpaulo */ 3290286441Srpaulostruct iwm_mac_data_ap { 3291286441Srpaulo uint32_t beacon_time; 3292286441Srpaulo uint64_t beacon_tsf; 3293286441Srpaulo uint32_t bi; 3294286441Srpaulo uint32_t bi_reciprocal; 3295286441Srpaulo uint32_t dtim_interval; 3296286441Srpaulo uint32_t dtim_reciprocal; 3297286441Srpaulo uint32_t mcast_qid; 3298286441Srpaulo uint32_t beacon_template; 3299286441Srpaulo} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3300286441Srpaulo 3301286441Srpaulo/** 3302286441Srpaulo * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3303286441Srpaulo * @beacon_time: beacon transmit time in system time 3304286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 3305286441Srpaulo * @bi: beacon interval in TU 3306286441Srpaulo * @bi_reciprocal: 2^32 / bi 3307286441Srpaulo * @beacon_template: beacon template ID 3308286441Srpaulo */ 3309286441Srpaulostruct iwm_mac_data_ibss { 3310286441Srpaulo uint32_t beacon_time; 3311286441Srpaulo uint64_t beacon_tsf; 3312286441Srpaulo uint32_t bi; 3313286441Srpaulo uint32_t bi_reciprocal; 3314286441Srpaulo uint32_t beacon_template; 3315286441Srpaulo} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3316286441Srpaulo 3317286441Srpaulo/** 3318286441Srpaulo * struct iwm_mac_data_sta - configuration data for station MAC context 3319286441Srpaulo * @is_assoc: 1 for associated state, 0 otherwise 3320286441Srpaulo * @dtim_time: DTIM arrival time in system time 3321286441Srpaulo * @dtim_tsf: DTIM arrival time in TSF 3322286441Srpaulo * @bi: beacon interval in TU, applicable only when associated 3323286441Srpaulo * @bi_reciprocal: 2^32 / bi , applicable only when associated 3324286441Srpaulo * @dtim_interval: DTIM interval in TU, applicable only when associated 3325286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3326286441Srpaulo * @listen_interval: in beacon intervals, applicable only when associated 3327286441Srpaulo * @assoc_id: unique ID assigned by the AP during association 3328286441Srpaulo */ 3329286441Srpaulostruct iwm_mac_data_sta { 3330286441Srpaulo uint32_t is_assoc; 3331286441Srpaulo uint32_t dtim_time; 3332286441Srpaulo uint64_t dtim_tsf; 3333286441Srpaulo uint32_t bi; 3334286441Srpaulo uint32_t bi_reciprocal; 3335286441Srpaulo uint32_t dtim_interval; 3336286441Srpaulo uint32_t dtim_reciprocal; 3337286441Srpaulo uint32_t listen_interval; 3338286441Srpaulo uint32_t assoc_id; 3339286441Srpaulo uint32_t assoc_beacon_arrive_time; 3340286441Srpaulo} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3341286441Srpaulo 3342286441Srpaulo/** 3343286441Srpaulo * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3344286441Srpaulo * @ap: iwm_mac_data_ap struct with most config data 3345286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3346286441Srpaulo * 0 indicates that there is no CT window. 3347286441Srpaulo * @opp_ps_enabled: indicate that opportunistic PS allowed 3348286441Srpaulo */ 3349286441Srpaulostruct iwm_mac_data_go { 3350286441Srpaulo struct iwm_mac_data_ap ap; 3351286441Srpaulo uint32_t ctwin; 3352286441Srpaulo uint32_t opp_ps_enabled; 3353286441Srpaulo} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3354286441Srpaulo 3355286441Srpaulo/** 3356286441Srpaulo * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3357286441Srpaulo * @sta: iwm_mac_data_sta struct with most config data 3358286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3359286441Srpaulo * 0 indicates that there is no CT window. 3360286441Srpaulo */ 3361286441Srpaulostruct iwm_mac_data_p2p_sta { 3362286441Srpaulo struct iwm_mac_data_sta sta; 3363286441Srpaulo uint32_t ctwin; 3364286441Srpaulo} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3365286441Srpaulo 3366286441Srpaulo/** 3367286441Srpaulo * struct iwm_mac_data_pibss - Pseudo IBSS config data 3368286441Srpaulo * @stats_interval: interval in TU between statistics notifications to host. 3369286441Srpaulo */ 3370286441Srpaulostruct iwm_mac_data_pibss { 3371286441Srpaulo uint32_t stats_interval; 3372286441Srpaulo} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3373286441Srpaulo 3374286441Srpaulo/* 3375286441Srpaulo * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3376286441Srpaulo * context. 3377286441Srpaulo * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3378286441Srpaulo * other channels as well. This should be to true only in case that the 3379286441Srpaulo * device is discoverable and there is an active GO. Note that setting this 3380286441Srpaulo * field when not needed, will increase the number of interrupts and have 3381286441Srpaulo * effect on the platform power, as this setting opens the Rx filters on 3382286441Srpaulo * all macs. 3383286441Srpaulo */ 3384286441Srpaulostruct iwm_mac_data_p2p_dev { 3385286441Srpaulo uint32_t is_disc_extended; 3386286441Srpaulo} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3387286441Srpaulo 3388286441Srpaulo/** 3389286441Srpaulo * enum iwm_mac_filter_flags - MAC context filter flags 3390286441Srpaulo * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3391286441Srpaulo * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3392286441Srpaulo * control frames to the host 3393286441Srpaulo * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3394286441Srpaulo * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3395286441Srpaulo * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3396286441Srpaulo * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3397286441Srpaulo * (in station mode when associated) 3398286441Srpaulo * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3399286441Srpaulo * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3400286441Srpaulo * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3401286441Srpaulo */ 3402286441Srpauloenum iwm_mac_filter_flags { 3403286441Srpaulo IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3404286441Srpaulo IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3405286441Srpaulo IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3406286441Srpaulo IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3407286441Srpaulo IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3408286441Srpaulo IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3409286441Srpaulo IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3410286441Srpaulo IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3411286441Srpaulo IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3412286441Srpaulo}; 3413286441Srpaulo 3414286441Srpaulo/** 3415286441Srpaulo * enum iwm_mac_qos_flags - QoS flags 3416286441Srpaulo * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3417286441Srpaulo * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3418286441Srpaulo * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3419286441Srpaulo * 3420286441Srpaulo */ 3421286441Srpauloenum iwm_mac_qos_flags { 3422286441Srpaulo IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3423286441Srpaulo IWM_MAC_QOS_FLG_TGN = (1 << 1), 3424286441Srpaulo IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3425286441Srpaulo}; 3426286441Srpaulo 3427286441Srpaulo/** 3428286441Srpaulo * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3429286441Srpaulo * @cw_min: Contention window, start value in numbers of slots. 3430286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x0f. 3431286441Srpaulo * @cw_max: Contention window, max value in numbers of slots. 3432286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x3f. 3433286441Srpaulo * @aifsn: Number of slots in Arbitration Interframe Space (before 3434286441Srpaulo * performing random backoff timing prior to Tx). Device default 1. 3435286441Srpaulo * @fifos_mask: FIFOs used by this MAC for this AC 3436286441Srpaulo * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3437286441Srpaulo * 3438286441Srpaulo * One instance of this config struct for each of 4 EDCA access categories 3439286441Srpaulo * in struct iwm_qosparam_cmd. 3440286441Srpaulo * 3441286441Srpaulo * Device will automatically increase contention window by (2*CW) + 1 for each 3442286441Srpaulo * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3443286441Srpaulo * value, to cap the CW value. 3444286441Srpaulo */ 3445286441Srpaulostruct iwm_ac_qos { 3446286441Srpaulo uint16_t cw_min; 3447286441Srpaulo uint16_t cw_max; 3448286441Srpaulo uint8_t aifsn; 3449286441Srpaulo uint8_t fifos_mask; 3450286441Srpaulo uint16_t edca_txop; 3451286441Srpaulo} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3452286441Srpaulo 3453286441Srpaulo/** 3454286441Srpaulo * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3455286441Srpaulo * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3456286441Srpaulo * @id_and_color: ID and color of the MAC 3457286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3458286441Srpaulo * @mac_type: one of IWM_FW_MAC_TYPE_* 3459286441Srpaulo * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3460286441Srpaulo * @node_addr: MAC address 3461286441Srpaulo * @bssid_addr: BSSID 3462286441Srpaulo * @cck_rates: basic rates available for CCK 3463286441Srpaulo * @ofdm_rates: basic rates available for OFDM 3464286441Srpaulo * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3465286441Srpaulo * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3466286441Srpaulo * @short_slot: 0x10 for enabling short slots, 0 otherwise 3467286441Srpaulo * @filter_flags: combination of IWM_MAC_FILTER_* 3468286441Srpaulo * @qos_flags: from IWM_MAC_QOS_FLG_* 3469286441Srpaulo * @ac: one iwm_mac_qos configuration for each AC 3470286441Srpaulo * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3471286441Srpaulo */ 3472286441Srpaulostruct iwm_mac_ctx_cmd { 3473286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 3474286441Srpaulo uint32_t id_and_color; 3475286441Srpaulo uint32_t action; 3476286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3477286441Srpaulo uint32_t mac_type; 3478286441Srpaulo uint32_t tsf_id; 3479286441Srpaulo uint8_t node_addr[6]; 3480286441Srpaulo uint16_t reserved_for_node_addr; 3481286441Srpaulo uint8_t bssid_addr[6]; 3482286441Srpaulo uint16_t reserved_for_bssid_addr; 3483286441Srpaulo uint32_t cck_rates; 3484286441Srpaulo uint32_t ofdm_rates; 3485286441Srpaulo uint32_t protection_flags; 3486286441Srpaulo uint32_t cck_short_preamble; 3487286441Srpaulo uint32_t short_slot; 3488286441Srpaulo uint32_t filter_flags; 3489286441Srpaulo /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3490286441Srpaulo uint32_t qos_flags; 3491286441Srpaulo struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3492286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3493286441Srpaulo union { 3494286441Srpaulo struct iwm_mac_data_ap ap; 3495286441Srpaulo struct iwm_mac_data_go go; 3496286441Srpaulo struct iwm_mac_data_sta sta; 3497286441Srpaulo struct iwm_mac_data_p2p_sta p2p_sta; 3498286441Srpaulo struct iwm_mac_data_p2p_dev p2p_dev; 3499286441Srpaulo struct iwm_mac_data_pibss pibss; 3500286441Srpaulo struct iwm_mac_data_ibss ibss; 3501286441Srpaulo }; 3502286441Srpaulo} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3503286441Srpaulo 3504286441Srpaulostatic inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3505286441Srpaulo{ 3506286441Srpaulo if (!v) 3507286441Srpaulo return 0; 3508286441Srpaulo return 0xFFFFFFFF / v; 3509286441Srpaulo} 3510286441Srpaulo 3511286441Srpaulo#define IWM_NONQOS_SEQ_GET 0x1 3512286441Srpaulo#define IWM_NONQOS_SEQ_SET 0x2 3513286441Srpaulostruct iwm_nonqos_seq_query_cmd { 3514286441Srpaulo uint32_t get_set_flag; 3515286441Srpaulo uint32_t mac_id_n_color; 3516286441Srpaulo uint16_t value; 3517286441Srpaulo uint16_t reserved; 3518286441Srpaulo} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3519286441Srpaulo 3520286441Srpaulo/* 3521286441Srpaulo * END mvm/fw-api-mac.h 3522286441Srpaulo */ 3523286441Srpaulo 3524286441Srpaulo/* 3525286441Srpaulo * BEGIN mvm/fw-api-power.h 3526286441Srpaulo */ 3527286441Srpaulo 3528286441Srpaulo/* Power Management Commands, Responses, Notifications */ 3529286441Srpaulo 3530286441Srpaulo/* Radio LP RX Energy Threshold measured in dBm */ 3531286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3532286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3533286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3534286441Srpaulo 3535286441Srpaulo/** 3536286441Srpaulo * enum iwm_scan_flags - masks for power table command flags 3537286441Srpaulo * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3538286441Srpaulo * receiver and transmitter. '0' - does not allow. 3539286441Srpaulo * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3540286441Srpaulo * '1' Driver enables PM (use rest of parameters) 3541286441Srpaulo * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3542286441Srpaulo * '1' PM could sleep over DTIM till listen Interval. 3543286441Srpaulo * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3544286441Srpaulo * access categories are both delivery and trigger enabled. 3545286441Srpaulo * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3546286441Srpaulo * PBW Snoozing enabled 3547286441Srpaulo * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3548286441Srpaulo * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3549286441Srpaulo * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3550286441Srpaulo * detection enablement 3551286441Srpaulo*/ 3552286441Srpauloenum iwm_power_flags { 3553286441Srpaulo IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3554286441Srpaulo IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3555286441Srpaulo IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3556286441Srpaulo IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3557286441Srpaulo IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3558286441Srpaulo IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3559286441Srpaulo IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3560286441Srpaulo IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3561286441Srpaulo}; 3562286441Srpaulo 3563286441Srpaulo#define IWM_POWER_VEC_SIZE 5 3564286441Srpaulo 3565286441Srpaulo/** 3566286441Srpaulo * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3567286441Srpaulo * is used also with a new power API for device wide power settings. 3568286441Srpaulo * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3569286441Srpaulo * 3570286441Srpaulo * @flags: Power table command flags from IWM_POWER_FLAGS_* 3571286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3572286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3573286441Srpaulo * set regardless of power scheme or current power state. 3574286441Srpaulo * FW use this value also when PM is disabled. 3575286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3576286441Srpaulo * PSM transition - legacy PM 3577286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3578286441Srpaulo * PSM transition - legacy PM 3579286441Srpaulo * @sleep_interval: not in use 3580286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3581286441Srpaulo * is set. For example, if it is required to skip over 3582286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3583286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3584286441Srpaulo * Default: 80dbm 3585286441Srpaulo */ 3586286441Srpaulostruct iwm_powertable_cmd { 3587286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3588286441Srpaulo uint16_t flags; 3589286441Srpaulo uint8_t keep_alive_seconds; 3590286441Srpaulo uint8_t debug_flags; 3591286441Srpaulo uint32_t rx_data_timeout; 3592286441Srpaulo uint32_t tx_data_timeout; 3593286441Srpaulo uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3594286441Srpaulo uint32_t skip_dtim_periods; 3595286441Srpaulo uint32_t lprx_rssi_threshold; 3596286441Srpaulo} __packed; 3597286441Srpaulo 3598286441Srpaulo/** 3599286441Srpaulo * enum iwm_device_power_flags - masks for device power command flags 3600330201Seadler * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3601330201Seadler * receiver and transmitter. '0' - does not allow. 3602330201Seadler */ 3603286441Srpauloenum iwm_device_power_flags { 3604286441Srpaulo IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3605286441Srpaulo}; 3606286441Srpaulo 3607286441Srpaulo/** 3608286441Srpaulo * struct iwm_device_power_cmd - device wide power command. 3609286441Srpaulo * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3610286441Srpaulo * 3611286441Srpaulo * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3612286441Srpaulo */ 3613286441Srpaulostruct iwm_device_power_cmd { 3614286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3615286441Srpaulo uint16_t flags; 3616286441Srpaulo uint16_t reserved; 3617286441Srpaulo} __packed; 3618286441Srpaulo 3619286441Srpaulo/** 3620286441Srpaulo * struct iwm_mac_power_cmd - New power command containing uAPSD support 3621286441Srpaulo * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3622286441Srpaulo * @id_and_color: MAC contex identifier 3623286441Srpaulo * @flags: Power table command flags from POWER_FLAGS_* 3624286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3625286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3626286441Srpaulo * set regardless of power scheme or current power state. 3627286441Srpaulo * FW use this value also when PM is disabled. 3628286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3629286441Srpaulo * PSM transition - legacy PM 3630286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3631286441Srpaulo * PSM transition - legacy PM 3632286441Srpaulo * @sleep_interval: not in use 3633286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3634286441Srpaulo * is set. For example, if it is required to skip over 3635286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3636286441Srpaulo * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3637286441Srpaulo * PSM transition - uAPSD 3638286441Srpaulo * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3639286441Srpaulo * PSM transition - uAPSD 3640286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3641286441Srpaulo * Default: 80dbm 3642286441Srpaulo * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3643286441Srpaulo * @snooze_interval: Maximum time between attempts to retrieve buffered data 3644286441Srpaulo * from the AP [msec] 3645286441Srpaulo * @snooze_window: A window of time in which PBW snoozing insures that all 3646286441Srpaulo * packets received. It is also the minimum time from last 3647286441Srpaulo * received unicast RX packet, before client stops snoozing 3648286441Srpaulo * for data. [msec] 3649286441Srpaulo * @snooze_step: TBD 3650286441Srpaulo * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3651286441Srpaulo * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3652286441Srpaulo * each corresponding AC. 3653286441Srpaulo * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3654286441Srpaulo * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3655286441Srpaulo * values. 3656286441Srpaulo * @heavy_tx_thld_packets: TX threshold measured in number of packets 3657286441Srpaulo * @heavy_rx_thld_packets: RX threshold measured in number of packets 3658286441Srpaulo * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3659286441Srpaulo * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3660286441Srpaulo * @limited_ps_threshold: 3661286441Srpaulo*/ 3662286441Srpaulostruct iwm_mac_power_cmd { 3663286441Srpaulo /* CONTEXT_DESC_API_T_VER_1 */ 3664286441Srpaulo uint32_t id_and_color; 3665286441Srpaulo 3666286441Srpaulo /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3667286441Srpaulo uint16_t flags; 3668286441Srpaulo uint16_t keep_alive_seconds; 3669286441Srpaulo uint32_t rx_data_timeout; 3670286441Srpaulo uint32_t tx_data_timeout; 3671286441Srpaulo uint32_t rx_data_timeout_uapsd; 3672286441Srpaulo uint32_t tx_data_timeout_uapsd; 3673286441Srpaulo uint8_t lprx_rssi_threshold; 3674286441Srpaulo uint8_t skip_dtim_periods; 3675286441Srpaulo uint16_t snooze_interval; 3676286441Srpaulo uint16_t snooze_window; 3677286441Srpaulo uint8_t snooze_step; 3678286441Srpaulo uint8_t qndp_tid; 3679286441Srpaulo uint8_t uapsd_ac_flags; 3680286441Srpaulo uint8_t uapsd_max_sp; 3681286441Srpaulo uint8_t heavy_tx_thld_packets; 3682286441Srpaulo uint8_t heavy_rx_thld_packets; 3683286441Srpaulo uint8_t heavy_tx_thld_percentage; 3684286441Srpaulo uint8_t heavy_rx_thld_percentage; 3685286441Srpaulo uint8_t limited_ps_threshold; 3686286441Srpaulo uint8_t reserved; 3687286441Srpaulo} __packed; 3688286441Srpaulo 3689286441Srpaulo/* 3690286441Srpaulo * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3691286441Srpaulo * associated AP is identified as improperly implementing uAPSD protocol. 3692286441Srpaulo * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3693286441Srpaulo * @sta_id: index of station in uCode's station table - associated AP ID in 3694286441Srpaulo * this context. 3695286441Srpaulo */ 3696286441Srpaulostruct iwm_uapsd_misbehaving_ap_notif { 3697286441Srpaulo uint32_t sta_id; 3698286441Srpaulo uint8_t mac_id; 3699286441Srpaulo uint8_t reserved[3]; 3700286441Srpaulo} __packed; 3701286441Srpaulo 3702286441Srpaulo/** 3703286441Srpaulo * struct iwm_beacon_filter_cmd 3704286441Srpaulo * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3705286441Srpaulo * @id_and_color: MAC contex identifier 3706286441Srpaulo * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3707286441Srpaulo * to driver if delta in Energy values calculated for this and last 3708286441Srpaulo * passed beacon is greater than this threshold. Zero value means that 3709286441Srpaulo * the Energy change is ignored for beacon filtering, and beacon will 3710286441Srpaulo * not be forced to be sent to driver regardless of this delta. Typical 3711286441Srpaulo * energy delta 5dB. 3712286441Srpaulo * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3713286441Srpaulo * Send beacon to driver if delta in Energy values calculated for this 3714286441Srpaulo * and last passed beacon is greater than this threshold. Zero value 3715286441Srpaulo * means that the Energy change is ignored for beacon filtering while in 3716286441Srpaulo * Roaming state, typical energy delta 1dB. 3717286441Srpaulo * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3718286441Srpaulo * calculated for current beacon is less than the threshold, use 3719286441Srpaulo * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3720286441Srpaulo * Threshold. Typical energy threshold is -72dBm. 3721286441Srpaulo * @bf_temp_threshold: This threshold determines the type of temperature 3722286441Srpaulo * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3723286441Srpaulo * If the current temperature is above this threshold - Fast filter 3724286441Srpaulo * will be used, If the current temperature is below this threshold - 3725286441Srpaulo * Slow filter will be used. 3726286441Srpaulo * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3727286441Srpaulo * calculated for this and the last passed beacon is greater than this 3728286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3729286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3730298955Spfg * regardless of whether its temperature has been changed. 3731286441Srpaulo * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3732286441Srpaulo * calculated for this and the last passed beacon is greater than this 3733286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3734286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3735298955Spfg * regardless of whether its temperature has been changed. 3736286441Srpaulo * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3737330446Seadler * @bf_filter_escape_timer: Send beacons to the driver if no beacons were passed 3738286441Srpaulo * for a specific period of time. Units: Beacons. 3739286441Srpaulo * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3740286441Srpaulo * for a longer period of time then this escape-timeout. Units: Beacons. 3741286441Srpaulo * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3742286441Srpaulo */ 3743286441Srpaulostruct iwm_beacon_filter_cmd { 3744286441Srpaulo uint32_t bf_energy_delta; 3745286441Srpaulo uint32_t bf_roaming_energy_delta; 3746286441Srpaulo uint32_t bf_roaming_state; 3747286441Srpaulo uint32_t bf_temp_threshold; 3748286441Srpaulo uint32_t bf_temp_fast_filter; 3749286441Srpaulo uint32_t bf_temp_slow_filter; 3750286441Srpaulo uint32_t bf_enable_beacon_filter; 3751286441Srpaulo uint32_t bf_debug_flag; 3752286441Srpaulo uint32_t bf_escape_timer; 3753286441Srpaulo uint32_t ba_escape_timer; 3754286441Srpaulo uint32_t ba_enable_beacon_abort; 3755286441Srpaulo} __packed; 3756286441Srpaulo 3757286441Srpaulo/* Beacon filtering and beacon abort */ 3758286441Srpaulo#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3759286441Srpaulo#define IWM_BF_ENERGY_DELTA_MAX 255 3760286441Srpaulo#define IWM_BF_ENERGY_DELTA_MIN 0 3761286441Srpaulo 3762286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3763286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3764286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3765286441Srpaulo 3766286441Srpaulo#define IWM_BF_ROAMING_STATE_DEFAULT 72 3767286441Srpaulo#define IWM_BF_ROAMING_STATE_MAX 255 3768286441Srpaulo#define IWM_BF_ROAMING_STATE_MIN 0 3769286441Srpaulo 3770286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3771286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MAX 255 3772286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MIN 0 3773286441Srpaulo 3774286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3775286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3776286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3777286441Srpaulo 3778286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3779286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3780286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3781286441Srpaulo 3782286441Srpaulo#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3783286441Srpaulo 3784286441Srpaulo#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3785286441Srpaulo 3786286441Srpaulo#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3787286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MAX 1024 3788286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MIN 0 3789286441Srpaulo 3790286441Srpaulo#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3791286441Srpaulo#define IWM_BA_ESCAPE_TIMER_D3 9 3792286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MAX 1024 3793286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MIN 0 3794286441Srpaulo 3795286441Srpaulo#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3796286441Srpaulo 3797286441Srpaulo#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3798286441Srpaulo .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3799286441Srpaulo .bf_roaming_energy_delta = \ 3800286441Srpaulo htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3801286441Srpaulo .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3802286441Srpaulo .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3803286441Srpaulo .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3804286441Srpaulo .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3805286441Srpaulo .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3806286441Srpaulo .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3807286441Srpaulo .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3808286441Srpaulo 3809286441Srpaulo/* 3810286441Srpaulo * END mvm/fw-api-power.h 3811286441Srpaulo */ 3812286441Srpaulo 3813286441Srpaulo/* 3814286441Srpaulo * BEGIN mvm/fw-api-rs.h 3815286441Srpaulo */ 3816286441Srpaulo 3817286441Srpaulo/* 3818286441Srpaulo * These serve as indexes into 3819286441Srpaulo * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3820286441Srpaulo * TODO: avoid overlap between legacy and HT rates 3821286441Srpaulo */ 3822286441Srpauloenum { 3823286441Srpaulo IWM_RATE_1M_INDEX = 0, 3824286441Srpaulo IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3825286441Srpaulo IWM_RATE_2M_INDEX, 3826286441Srpaulo IWM_RATE_5M_INDEX, 3827286441Srpaulo IWM_RATE_11M_INDEX, 3828286441Srpaulo IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3829286441Srpaulo IWM_RATE_6M_INDEX, 3830286441Srpaulo IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3831286441Srpaulo IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3832286441Srpaulo IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3833286441Srpaulo IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3834286441Srpaulo IWM_RATE_9M_INDEX, 3835286441Srpaulo IWM_RATE_12M_INDEX, 3836286441Srpaulo IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3837286441Srpaulo IWM_RATE_18M_INDEX, 3838286441Srpaulo IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3839286441Srpaulo IWM_RATE_24M_INDEX, 3840286441Srpaulo IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3841286441Srpaulo IWM_RATE_36M_INDEX, 3842286441Srpaulo IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3843286441Srpaulo IWM_RATE_48M_INDEX, 3844286441Srpaulo IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3845286441Srpaulo IWM_RATE_54M_INDEX, 3846286441Srpaulo IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3847286441Srpaulo IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3848286441Srpaulo IWM_RATE_60M_INDEX, 3849286441Srpaulo IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3850286441Srpaulo IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3851286441Srpaulo IWM_RATE_MCS_8_INDEX, 3852286441Srpaulo IWM_RATE_MCS_9_INDEX, 3853286441Srpaulo IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3854286441Srpaulo IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3855286441Srpaulo IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3856286441Srpaulo}; 3857286441Srpaulo 3858286441Srpaulo#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3859286441Srpaulo 3860286441Srpaulo/* fw API values for legacy bit rates, both OFDM and CCK */ 3861286441Srpauloenum { 3862286441Srpaulo IWM_RATE_6M_PLCP = 13, 3863286441Srpaulo IWM_RATE_9M_PLCP = 15, 3864286441Srpaulo IWM_RATE_12M_PLCP = 5, 3865286441Srpaulo IWM_RATE_18M_PLCP = 7, 3866286441Srpaulo IWM_RATE_24M_PLCP = 9, 3867286441Srpaulo IWM_RATE_36M_PLCP = 11, 3868286441Srpaulo IWM_RATE_48M_PLCP = 1, 3869286441Srpaulo IWM_RATE_54M_PLCP = 3, 3870286441Srpaulo IWM_RATE_1M_PLCP = 10, 3871286441Srpaulo IWM_RATE_2M_PLCP = 20, 3872286441Srpaulo IWM_RATE_5M_PLCP = 55, 3873286441Srpaulo IWM_RATE_11M_PLCP = 110, 3874286441Srpaulo IWM_RATE_INVM_PLCP = -1, 3875286441Srpaulo}; 3876286441Srpaulo 3877286441Srpaulo/* 3878286441Srpaulo * rate_n_flags bit fields 3879286441Srpaulo * 3880286441Srpaulo * The 32-bit value has different layouts in the low 8 bites depending on the 3881286441Srpaulo * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3882286441Srpaulo * for CCK and OFDM). 3883286441Srpaulo * 3884286441Srpaulo * High-throughput (HT) rate format 3885286441Srpaulo * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3886286441Srpaulo * Very High-throughput (VHT) rate format 3887286441Srpaulo * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3888286441Srpaulo * Legacy OFDM rate format for bits 7:0 3889286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3890286441Srpaulo * Legacy CCK rate format for bits 7:0: 3891286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3892286441Srpaulo */ 3893286441Srpaulo 3894286441Srpaulo/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3895286441Srpaulo#define IWM_RATE_MCS_HT_POS 8 3896286441Srpaulo#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3897286441Srpaulo 3898286441Srpaulo/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3899286441Srpaulo#define IWM_RATE_MCS_CCK_POS 9 3900286441Srpaulo#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3901286441Srpaulo 3902286441Srpaulo/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3903286441Srpaulo#define IWM_RATE_MCS_VHT_POS 26 3904286441Srpaulo#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3905286441Srpaulo 3906286441Srpaulo 3907286441Srpaulo/* 3908286441Srpaulo * High-throughput (HT) rate format for bits 7:0 3909286441Srpaulo * 3910286441Srpaulo * 2-0: MCS rate base 3911286441Srpaulo * 0) 6 Mbps 3912286441Srpaulo * 1) 12 Mbps 3913286441Srpaulo * 2) 18 Mbps 3914286441Srpaulo * 3) 24 Mbps 3915286441Srpaulo * 4) 36 Mbps 3916286441Srpaulo * 5) 48 Mbps 3917286441Srpaulo * 6) 54 Mbps 3918286441Srpaulo * 7) 60 Mbps 3919286441Srpaulo * 4-3: 0) Single stream (SISO) 3920286441Srpaulo * 1) Dual stream (MIMO) 3921286441Srpaulo * 2) Triple stream (MIMO) 3922286441Srpaulo * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3923286441Srpaulo * (bits 7-6 are zero) 3924286441Srpaulo * 3925286441Srpaulo * Together the low 5 bits work out to the MCS index because we don't 3926286441Srpaulo * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3927286441Srpaulo * streams and 16-23 have three streams. We could also support MCS 32 3928286441Srpaulo * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3929286441Srpaulo */ 3930286441Srpaulo#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3931286441Srpaulo#define IWM_RATE_HT_MCS_NSS_POS 3 3932286441Srpaulo#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3933286441Srpaulo 3934286441Srpaulo/* Bit 10: (1) Use Green Field preamble */ 3935286441Srpaulo#define IWM_RATE_HT_MCS_GF_POS 10 3936286441Srpaulo#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3937286441Srpaulo 3938286441Srpaulo#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3939286441Srpaulo 3940286441Srpaulo/* 3941286441Srpaulo * Very High-throughput (VHT) rate format for bits 7:0 3942286441Srpaulo * 3943286441Srpaulo * 3-0: VHT MCS (0-9) 3944286441Srpaulo * 5-4: number of streams - 1: 3945286441Srpaulo * 0) Single stream (SISO) 3946286441Srpaulo * 1) Dual stream (MIMO) 3947286441Srpaulo * 2) Triple stream (MIMO) 3948286441Srpaulo */ 3949286441Srpaulo 3950286441Srpaulo/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3951286441Srpaulo#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3952286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_POS 4 3953286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3954286441Srpaulo 3955286441Srpaulo/* 3956286441Srpaulo * Legacy OFDM rate format for bits 7:0 3957286441Srpaulo * 3958286441Srpaulo * 3-0: 0xD) 6 Mbps 3959286441Srpaulo * 0xF) 9 Mbps 3960286441Srpaulo * 0x5) 12 Mbps 3961286441Srpaulo * 0x7) 18 Mbps 3962286441Srpaulo * 0x9) 24 Mbps 3963286441Srpaulo * 0xB) 36 Mbps 3964286441Srpaulo * 0x1) 48 Mbps 3965286441Srpaulo * 0x3) 54 Mbps 3966286441Srpaulo * (bits 7-4 are 0) 3967286441Srpaulo * 3968286441Srpaulo * Legacy CCK rate format for bits 7:0: 3969286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3970286441Srpaulo * 3971286441Srpaulo * 6-0: 10) 1 Mbps 3972286441Srpaulo * 20) 2 Mbps 3973286441Srpaulo * 55) 5.5 Mbps 3974286441Srpaulo * 110) 11 Mbps 3975286441Srpaulo * (bit 7 is 0) 3976286441Srpaulo */ 3977286441Srpaulo#define IWM_RATE_LEGACY_RATE_MSK 0xff 3978286441Srpaulo 3979286441Srpaulo 3980286441Srpaulo/* 3981286441Srpaulo * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 3982286441Srpaulo * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 3983286441Srpaulo */ 3984330226Seadler#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 3985330226Seadler#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3986330226Seadler#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3987330226Seadler#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3988330226Seadler#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3989330226Seadler#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3990286441Srpaulo 3991286441Srpaulo/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 3992286441Srpaulo#define IWM_RATE_MCS_SGI_POS 13 3993286441Srpaulo#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 3994286441Srpaulo 3995286441Srpaulo/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 3996286441Srpaulo#define IWM_RATE_MCS_ANT_POS 14 3997286441Srpaulo#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 3998286441Srpaulo#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 3999286441Srpaulo#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4000286441Srpaulo#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4001286441Srpaulo IWM_RATE_MCS_ANT_B_MSK) 4002330226Seadler#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4003286441Srpaulo IWM_RATE_MCS_ANT_C_MSK) 4004286441Srpaulo#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4005286441Srpaulo#define IWM_RATE_MCS_ANT_NUM 3 4006286441Srpaulo 4007286441Srpaulo/* Bit 17-18: (0) SS, (1) SS*2 */ 4008286441Srpaulo#define IWM_RATE_MCS_STBC_POS 17 4009286441Srpaulo#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4010286441Srpaulo 4011286441Srpaulo/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4012330226Seadler#define IWM_RATE_MCS_BF_POS 19 4013330226Seadler#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4014286441Srpaulo 4015286441Srpaulo/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4016286441Srpaulo#define IWM_RATE_MCS_ZLF_POS 20 4017286441Srpaulo#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4018286441Srpaulo 4019286441Srpaulo/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4020286441Srpaulo#define IWM_RATE_MCS_DUP_POS 24 4021286441Srpaulo#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4022286441Srpaulo 4023286441Srpaulo/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4024286441Srpaulo#define IWM_RATE_MCS_LDPC_POS 27 4025286441Srpaulo#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4026286441Srpaulo 4027286441Srpaulo 4028286441Srpaulo/* Link Quality definitions */ 4029286441Srpaulo 4030286441Srpaulo/* # entries in rate scale table to support Tx retries */ 4031286441Srpaulo#define IWM_LQ_MAX_RETRY_NUM 16 4032286441Srpaulo 4033286441Srpaulo/* Link quality command flags bit fields */ 4034286441Srpaulo 4035286441Srpaulo/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4036330226Seadler#define IWM_LQ_FLAG_USE_RTS_POS 0 4037330226Seadler#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4038286441Srpaulo 4039286441Srpaulo/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4040330226Seadler#define IWM_LQ_FLAG_COLOR_POS 1 4041330226Seadler#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4042286441Srpaulo 4043286441Srpaulo/* Bit 4-5: Tx RTS BW Signalling 4044286441Srpaulo * (0) No RTS BW signalling 4045286441Srpaulo * (1) Static BW signalling 4046286441Srpaulo * (2) Dynamic BW signalling 4047286441Srpaulo */ 4048330226Seadler#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4049330226Seadler#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4050330226Seadler#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4051330226Seadler#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4052286441Srpaulo 4053286441Srpaulo/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4054286441Srpaulo * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4055286441Srpaulo */ 4056330226Seadler#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4057330226Seadler#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4058286441Srpaulo 4059330226Seadler/* Single Stream Tx Parameters (lq_cmd->ss_params) 4060330226Seadler * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 4061330226Seadler * used for single stream Tx. 4062330226Seadler */ 4063330226Seadler 4064330226Seadler/* Bit 0-1: Max STBC streams allowed. Can be 0-3. 4065330226Seadler * (0) - No STBC allowed 4066330226Seadler * (1) - 2x1 STBC allowed (HT/VHT) 4067330226Seadler * (2) - 4x2 STBC allowed (HT/VHT) 4068330226Seadler * (3) - 3x2 STBC allowed (HT only) 4069330226Seadler * All our chips are at most 2 antennas so only (1) is valid for now. 4070330226Seadler */ 4071330226Seadler#define IWM_LQ_SS_STBC_ALLOWED_POS 0 4072330226Seadler#define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK) 4073330226Seadler 4074330226Seadler/* 2x1 STBC is allowed */ 4075330226Seadler#define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS) 4076330226Seadler 4077330226Seadler/* Bit 2: Beamformer (VHT only) is allowed */ 4078330226Seadler#define IWM_LQ_SS_BFER_ALLOWED_POS 2 4079330226Seadler#define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS) 4080330226Seadler 4081330226Seadler/* Bit 3: Force BFER or STBC for testing 4082330226Seadler * If this is set: 4083330226Seadler * If BFER is allowed then force the ucode to choose BFER else 4084330226Seadler * If STBC is allowed then force the ucode to choose STBC over SISO 4085330226Seadler */ 4086330226Seadler#define IWM_LQ_SS_FORCE_POS 3 4087330226Seadler#define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS) 4088330226Seadler 4089330226Seadler/* Bit 31: ss_params field is valid. Used for FW backward compatibility 4090330226Seadler * with other drivers which don't support the ss_params API yet 4091330226Seadler */ 4092330226Seadler#define IWM_LQ_SS_PARAMS_VALID_POS 31 4093330226Seadler#define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS) 4094330226Seadler 4095286441Srpaulo/** 4096286441Srpaulo * struct iwm_lq_cmd - link quality command 4097286441Srpaulo * @sta_id: station to update 4098286441Srpaulo * @control: not used 4099286441Srpaulo * @flags: combination of IWM_LQ_FLAG_* 4100286441Srpaulo * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4101286441Srpaulo * and SISO rates 4102286441Srpaulo * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4103286441Srpaulo * Should be ANT_[ABC] 4104286441Srpaulo * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4105286441Srpaulo * @initial_rate_index: first index from rs_table per AC category 4106286441Srpaulo * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4107286441Srpaulo * value of 100 is one usec. Range is 100 to 8000 4108286441Srpaulo * @agg_disable_start_th: try-count threshold for starting aggregation. 4109286441Srpaulo * If a frame has higher try-count, it should not be selected for 4110286441Srpaulo * starting an aggregation sequence. 4111286441Srpaulo * @agg_frame_cnt_limit: max frame count in an aggregation. 4112286441Srpaulo * 0: no limit 4113286441Srpaulo * 1: no aggregation (one frame per aggregation) 4114286441Srpaulo * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4115286441Srpaulo * @rs_table: array of rates for each TX try, each is rate_n_flags, 4116286441Srpaulo * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4117330226Seadler * @ss_params: single stream features. declare whether STBC or BFER are allowed. 4118286441Srpaulo */ 4119286441Srpaulostruct iwm_lq_cmd { 4120286441Srpaulo uint8_t sta_id; 4121330226Seadler uint8_t reduced_tpc; 4122286441Srpaulo uint16_t control; 4123286441Srpaulo /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4124286441Srpaulo uint8_t flags; 4125286441Srpaulo uint8_t mimo_delim; 4126286441Srpaulo uint8_t single_stream_ant_msk; 4127286441Srpaulo uint8_t dual_stream_ant_msk; 4128286441Srpaulo uint8_t initial_rate_index[IWM_AC_NUM]; 4129286441Srpaulo /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4130286441Srpaulo uint16_t agg_time_limit; 4131286441Srpaulo uint8_t agg_disable_start_th; 4132286441Srpaulo uint8_t agg_frame_cnt_limit; 4133286441Srpaulo uint32_t reserved2; 4134286441Srpaulo uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4135330226Seadler uint32_t ss_params; 4136286441Srpaulo}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4137286441Srpaulo 4138286441Srpaulo/* 4139286441Srpaulo * END mvm/fw-api-rs.h 4140286441Srpaulo */ 4141286441Srpaulo 4142286441Srpaulo/* 4143286441Srpaulo * BEGIN mvm/fw-api-tx.h 4144286441Srpaulo */ 4145286441Srpaulo 4146286441Srpaulo/** 4147286441Srpaulo * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4148286441Srpaulo * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4149286441Srpaulo * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4150286441Srpaulo * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4151286441Srpaulo * Otherwise, use rate_n_flags from the TX command 4152286441Srpaulo * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4153286441Srpaulo * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4154286441Srpaulo * Must set IWM_TX_CMD_FLG_ACK with this flag. 4155286441Srpaulo * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4156286441Srpaulo * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4157286441Srpaulo * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4158286441Srpaulo * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4159286441Srpaulo * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4160286441Srpaulo * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4161286441Srpaulo * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4162286441Srpaulo * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4163286441Srpaulo * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4164286441Srpaulo * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4165286441Srpaulo * Should be set for beacons and probe responses 4166286441Srpaulo * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4167286441Srpaulo * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4168286441Srpaulo * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4169286441Srpaulo * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4170286441Srpaulo * Should be set for 26/30 length MAC headers 4171286441Srpaulo * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4172286441Srpaulo * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4173286441Srpaulo * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4174286441Srpaulo * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4175286441Srpaulo * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4176286441Srpaulo * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4177286441Srpaulo * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4178286441Srpaulo */ 4179286441Srpauloenum iwm_tx_flags { 4180286441Srpaulo IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4181286441Srpaulo IWM_TX_CMD_FLG_ACK = (1 << 3), 4182286441Srpaulo IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4183286441Srpaulo IWM_TX_CMD_FLG_BA = (1 << 5), 4184286441Srpaulo IWM_TX_CMD_FLG_BAR = (1 << 6), 4185286441Srpaulo IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4186286441Srpaulo IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4187286441Srpaulo IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4188286441Srpaulo IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4189286441Srpaulo IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4190286441Srpaulo IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4191286441Srpaulo IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4192286441Srpaulo IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4193286441Srpaulo IWM_TX_CMD_FLG_TSF = (1 << 16), 4194286441Srpaulo IWM_TX_CMD_FLG_CALIB = (1 << 17), 4195286441Srpaulo IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4196286441Srpaulo IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4197286441Srpaulo IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4198286441Srpaulo IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4199286441Srpaulo IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4200286441Srpaulo IWM_TX_CMD_FLG_DUR = (1 << 25), 4201286441Srpaulo IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4202286441Srpaulo IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4203286441Srpaulo IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4204286441Srpaulo IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4205286441Srpaulo}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4206286441Srpaulo 4207303628Ssbruno/** 4208303628Ssbruno * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4209303628Ssbruno * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4210303628Ssbruno * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4211303628Ssbruno * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4212303628Ssbruno */ 4213303628Ssbrunoenum iwm_tx_pm_timeouts { 4214303628Ssbruno IWM_PM_FRAME_NONE = 0, 4215303628Ssbruno IWM_PM_FRAME_MGMT = 2, 4216303628Ssbruno IWM_PM_FRAME_ASSOC = 3, 4217303628Ssbruno}; 4218303628Ssbruno 4219286441Srpaulo/* 4220286441Srpaulo * TX command security control 4221286441Srpaulo */ 4222286441Srpaulo#define IWM_TX_CMD_SEC_WEP 0x01 4223286441Srpaulo#define IWM_TX_CMD_SEC_CCM 0x02 4224286441Srpaulo#define IWM_TX_CMD_SEC_TKIP 0x03 4225286441Srpaulo#define IWM_TX_CMD_SEC_EXT 0x04 4226286441Srpaulo#define IWM_TX_CMD_SEC_MSK 0x07 4227286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4228286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4229286441Srpaulo#define IWM_TX_CMD_SEC_KEY128 0x08 4230286441Srpaulo 4231286441Srpaulo/* TODO: how does these values are OK with only 16 bit variable??? */ 4232286441Srpaulo/* 4233286441Srpaulo * TX command next frame info 4234286441Srpaulo * 4235286441Srpaulo * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4236286441Srpaulo * bit 3 - immediate ACK required 4237286441Srpaulo * bit 4 - rate is taken from STA table 4238286441Srpaulo * bit 5 - frame belongs to BA stream 4239286441Srpaulo * bit 6 - immediate BA response expected 4240286441Srpaulo * bit 7 - unused 4241286441Srpaulo * bits 8:15 - Station ID 4242286441Srpaulo * bits 16:31 - rate 4243286441Srpaulo */ 4244286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4245286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4246286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4247286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4248286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4249286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4250286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4251286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4252286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4253286441Srpaulo 4254286441Srpaulo/* 4255286441Srpaulo * TX command Frame life time in us - to be written in pm_frame_timeout 4256286441Srpaulo */ 4257286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4258286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4259286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4260286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4261286441Srpaulo 4262286441Srpaulo/* 4263286441Srpaulo * TID for non QoS frames - to be written in tid_tspec 4264286441Srpaulo */ 4265286441Srpaulo#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4266286441Srpaulo 4267286441Srpaulo/* 4268286441Srpaulo * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4269286441Srpaulo */ 4270286441Srpaulo#define IWM_DEFAULT_TX_RETRY 15 4271286441Srpaulo#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4272286441Srpaulo#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4273286441Srpaulo#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4274286441Srpaulo#define IWM_LOW_RETRY_LIMIT 7 4275286441Srpaulo 4276286441Srpaulo/* TODO: complete documentation for try_cnt and btkill_cnt */ 4277286441Srpaulo/** 4278286441Srpaulo * struct iwm_tx_cmd - TX command struct to FW 4279286441Srpaulo * ( IWM_TX_CMD = 0x1c ) 4280286441Srpaulo * @len: in bytes of the payload, see below for details 4281286441Srpaulo * @next_frame_len: same as len, but for next frame (0 if not applicable) 4282286441Srpaulo * Used for fragmentation and bursting, but not in 11n aggregation. 4283286441Srpaulo * @tx_flags: combination of IWM_TX_CMD_FLG_* 4284286441Srpaulo * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4285286441Srpaulo * cleared. Combination of IWM_RATE_MCS_* 4286286441Srpaulo * @sta_id: index of destination station in FW station table 4287286441Srpaulo * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4288300050Seadler * @initial_rate_index: index into the rate table for initial TX attempt. 4289286441Srpaulo * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4290286441Srpaulo * @key: security key 4291286441Srpaulo * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4292286441Srpaulo * @life_time: frame life time (usecs??) 4293286441Srpaulo * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4294286441Srpaulo * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4295286441Srpaulo * @dram_msb_ptr: upper bits of the scratch physical address 4296286441Srpaulo * @rts_retry_limit: max attempts for RTS 4297286441Srpaulo * @data_retry_limit: max attempts to send the data packet 4298286441Srpaulo * @tid_spec: TID/tspec 4299286441Srpaulo * @pm_frame_timeout: PM TX frame timeout 4300286441Srpaulo * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4301286441Srpaulo * specified by HCCA protocol 4302286441Srpaulo * 4303286441Srpaulo * The byte count (both len and next_frame_len) includes MAC header 4304286441Srpaulo * (24/26/30/32 bytes) 4305286441Srpaulo * + 2 bytes pad if 26/30 header size 4306286441Srpaulo * + 8 byte IV for CCM or TKIP (not used for WEP) 4307286441Srpaulo * + Data payload 4308286441Srpaulo * + 8-byte MIC (not used for CCM/WEP) 4309286441Srpaulo * It does not include post-MAC padding, i.e., 4310286441Srpaulo * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4311286441Srpaulo * Range of len: 14-2342 bytes. 4312286441Srpaulo * 4313286441Srpaulo * After the struct fields the MAC header is placed, plus any padding, 4314286441Srpaulo * and then the actial payload. 4315286441Srpaulo */ 4316286441Srpaulostruct iwm_tx_cmd { 4317286441Srpaulo uint16_t len; 4318286441Srpaulo uint16_t next_frame_len; 4319286441Srpaulo uint32_t tx_flags; 4320286441Srpaulo struct { 4321286441Srpaulo uint8_t try_cnt; 4322286441Srpaulo uint8_t btkill_cnt; 4323286441Srpaulo uint16_t reserved; 4324286441Srpaulo } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4325286441Srpaulo uint32_t rate_n_flags; 4326286441Srpaulo uint8_t sta_id; 4327286441Srpaulo uint8_t sec_ctl; 4328286441Srpaulo uint8_t initial_rate_index; 4329286441Srpaulo uint8_t reserved2; 4330286441Srpaulo uint8_t key[16]; 4331286441Srpaulo uint16_t next_frame_flags; 4332286441Srpaulo uint16_t reserved3; 4333286441Srpaulo uint32_t life_time; 4334286441Srpaulo uint32_t dram_lsb_ptr; 4335286441Srpaulo uint8_t dram_msb_ptr; 4336286441Srpaulo uint8_t rts_retry_limit; 4337286441Srpaulo uint8_t data_retry_limit; 4338286441Srpaulo uint8_t tid_tspec; 4339286441Srpaulo uint16_t pm_frame_timeout; 4340286441Srpaulo uint16_t driver_txop; 4341286441Srpaulo uint8_t payload[0]; 4342286441Srpaulo struct ieee80211_frame hdr[0]; 4343286441Srpaulo} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4344286441Srpaulo 4345286441Srpaulo/* 4346286441Srpaulo * TX response related data 4347286441Srpaulo */ 4348286441Srpaulo 4349286441Srpaulo/* 4350286441Srpaulo * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4351286441Srpaulo * @IWM_TX_STATUS_SUCCESS: 4352286441Srpaulo * @IWM_TX_STATUS_DIRECT_DONE: 4353286441Srpaulo * @IWM_TX_STATUS_POSTPONE_DELAY: 4354286441Srpaulo * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4355286441Srpaulo * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4356286441Srpaulo * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4357286441Srpaulo * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4358286441Srpaulo * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4359286441Srpaulo * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4360286441Srpaulo * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4361286441Srpaulo * @IWM_TX_STATUS_FAIL_UNDERRUN: 4362286441Srpaulo * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4363286441Srpaulo * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4364286441Srpaulo * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4365286441Srpaulo * @IWM_TX_STATUS_FAIL_DEST_PS: 4366286441Srpaulo * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4367286441Srpaulo * @IWM_TX_STATUS_FAIL_BT_RETRY: 4368286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_INVALID: 4369286441Srpaulo * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4370286441Srpaulo * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4371286441Srpaulo * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4372286441Srpaulo * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4373286441Srpaulo * @IWM_TX_STATUS_FAIL_FW_DROP: 4374286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4375286441Srpaulo * STA table 4376286441Srpaulo * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4377286441Srpaulo * @IWM_TX_MODE_MSK: 4378286441Srpaulo * @IWM_TX_MODE_NO_BURST: 4379286441Srpaulo * @IWM_TX_MODE_IN_BURST_SEQ: 4380286441Srpaulo * @IWM_TX_MODE_FIRST_IN_BURST: 4381286441Srpaulo * @IWM_TX_QUEUE_NUM_MSK: 4382286441Srpaulo * 4383286441Srpaulo * Valid only if frame_count =1 4384286441Srpaulo * TODO: complete documentation 4385286441Srpaulo */ 4386286441Srpauloenum iwm_tx_status { 4387286441Srpaulo IWM_TX_STATUS_MSK = 0x000000ff, 4388286441Srpaulo IWM_TX_STATUS_SUCCESS = 0x01, 4389286441Srpaulo IWM_TX_STATUS_DIRECT_DONE = 0x02, 4390286441Srpaulo /* postpone TX */ 4391286441Srpaulo IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4392286441Srpaulo IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4393286441Srpaulo IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4394286441Srpaulo IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4395286441Srpaulo IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4396286441Srpaulo /* abort TX */ 4397286441Srpaulo IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4398286441Srpaulo IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4399286441Srpaulo IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4400286441Srpaulo IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4401286441Srpaulo IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4402286441Srpaulo IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4403286441Srpaulo IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4404286441Srpaulo IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4405286441Srpaulo IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4406286441Srpaulo IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4407286441Srpaulo IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4408286441Srpaulo IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4409286441Srpaulo IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4410286441Srpaulo IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4411286441Srpaulo IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4412286441Srpaulo IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4413286441Srpaulo IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4414286441Srpaulo IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4415286441Srpaulo IWM_TX_MODE_MSK = 0x00000f00, 4416286441Srpaulo IWM_TX_MODE_NO_BURST = 0x00000000, 4417286441Srpaulo IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4418286441Srpaulo IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4419286441Srpaulo IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4420286441Srpaulo IWM_TX_NARROW_BW_MSK = 0x00060000, 4421286441Srpaulo IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4422286441Srpaulo IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4423286441Srpaulo IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4424286441Srpaulo}; 4425286441Srpaulo 4426286441Srpaulo/* 4427286441Srpaulo * enum iwm_tx_agg_status - TX aggregation status 4428286441Srpaulo * @IWM_AGG_TX_STATE_STATUS_MSK: 4429286441Srpaulo * @IWM_AGG_TX_STATE_TRANSMITTED: 4430286441Srpaulo * @IWM_AGG_TX_STATE_UNDERRUN: 4431286441Srpaulo * @IWM_AGG_TX_STATE_BT_PRIO: 4432286441Srpaulo * @IWM_AGG_TX_STATE_FEW_BYTES: 4433286441Srpaulo * @IWM_AGG_TX_STATE_ABORT: 4434286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4435286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4436286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4437286441Srpaulo * @IWM_AGG_TX_STATE_SCD_QUERY: 4438286441Srpaulo * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4439286441Srpaulo * @IWM_AGG_TX_STATE_RESPONSE: 4440286441Srpaulo * @IWM_AGG_TX_STATE_DUMP_TX: 4441286441Srpaulo * @IWM_AGG_TX_STATE_DELAY_TX: 4442286441Srpaulo * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4443286441Srpaulo * occur if tx failed for this frame when it was a member of a previous 4444286441Srpaulo * aggregation block). If rate scaling is used, retry count indicates the 4445286441Srpaulo * rate table entry used for all frames in the new agg. 4446286441Srpaulo *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4447286441Srpaulo * this frame 4448286441Srpaulo * 4449286441Srpaulo * TODO: complete documentation 4450286441Srpaulo */ 4451286441Srpauloenum iwm_tx_agg_status { 4452286441Srpaulo IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4453286441Srpaulo IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4454286441Srpaulo IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4455286441Srpaulo IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4456286441Srpaulo IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4457286441Srpaulo IWM_AGG_TX_STATE_ABORT = 0x008, 4458286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4459286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4460286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4461286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4462286441Srpaulo IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4463286441Srpaulo IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4464286441Srpaulo IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4465286441Srpaulo IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4466286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4467286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4468286441Srpaulo}; 4469286441Srpaulo 4470286441Srpaulo#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4471286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4472286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4473286441Srpaulo 4474286441Srpaulo/* 4475286441Srpaulo * The mask below describes a status where we are absolutely sure that the MPDU 4476286441Srpaulo * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4477286441Srpaulo * written the bytes to the TXE, but we know nothing about what the DSP did. 4478286441Srpaulo */ 4479286441Srpaulo#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4480286441Srpaulo IWM_AGG_TX_STATE_ABORT | \ 4481286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY) 4482286441Srpaulo 4483286441Srpaulo/* 4484286441Srpaulo * IWM_REPLY_TX = 0x1c (response) 4485286441Srpaulo * 4486286441Srpaulo * This response may be in one of two slightly different formats, indicated 4487286441Srpaulo * by the frame_count field: 4488286441Srpaulo * 4489286441Srpaulo * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4490286441Srpaulo * frame. Multiple attempts, at various bit rates, may have been made for 4491286441Srpaulo * this frame. 4492286441Srpaulo * 4493286441Srpaulo * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4494286441Srpaulo * frames that used block-acknowledge. All frames were transmitted at 4495286441Srpaulo * same rate. Rate scaling may have been used if first frame in this new 4496286441Srpaulo * agg block failed in previous agg block(s). 4497286441Srpaulo * 4498286441Srpaulo * Note that, for aggregation, ACK (block-ack) status is not delivered 4499286441Srpaulo * here; block-ack has not been received by the time the device records 4500286441Srpaulo * this status. 4501286441Srpaulo * This status relates to reasons the tx might have been blocked or aborted 4502286441Srpaulo * within the device, rather than whether it was received successfully by 4503286441Srpaulo * the destination station. 4504286441Srpaulo */ 4505286441Srpaulo 4506286441Srpaulo/** 4507286441Srpaulo * struct iwm_agg_tx_status - per packet TX aggregation status 4508286441Srpaulo * @status: enum iwm_tx_agg_status 4509286441Srpaulo * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4510286441Srpaulo */ 4511286441Srpaulostruct iwm_agg_tx_status { 4512286441Srpaulo uint16_t status; 4513286441Srpaulo uint16_t sequence; 4514286441Srpaulo} __packed; 4515286441Srpaulo 4516286441Srpaulo/* 4517286441Srpaulo * definitions for initial rate index field 4518286441Srpaulo * bits [3:0] initial rate index 4519286441Srpaulo * bits [6:4] rate table color, used for the initial rate 4520286441Srpaulo * bit-7 invalid rate indication 4521286441Srpaulo */ 4522286441Srpaulo#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4523286441Srpaulo#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4524286441Srpaulo#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4525286441Srpaulo 4526286441Srpaulo#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4527286441Srpaulo#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4528286441Srpaulo 4529286441Srpaulo/** 4530286441Srpaulo * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4531286441Srpaulo * ( IWM_REPLY_TX = 0x1c ) 4532286441Srpaulo * @frame_count: 1 no aggregation, >1 aggregation 4533286441Srpaulo * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4534286441Srpaulo * @failure_rts: num of failures due to unsuccessful RTS 4535286441Srpaulo * @failure_frame: num failures due to no ACK (unused for agg) 4536286441Srpaulo * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4537286441Srpaulo * Tx of all the batch. IWM_RATE_MCS_* 4538286441Srpaulo * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4539286441Srpaulo * for agg: RTS + CTS + aggregation tx time + block-ack time. 4540286441Srpaulo * in usec. 4541286441Srpaulo * @pa_status: tx power info 4542286441Srpaulo * @pa_integ_res_a: tx power info 4543286441Srpaulo * @pa_integ_res_b: tx power info 4544286441Srpaulo * @pa_integ_res_c: tx power info 4545286441Srpaulo * @measurement_req_id: tx power info 4546286441Srpaulo * @tfd_info: TFD information set by the FH 4547286441Srpaulo * @seq_ctl: sequence control from the Tx cmd 4548286441Srpaulo * @byte_cnt: byte count from the Tx cmd 4549286441Srpaulo * @tlc_info: TLC rate info 4550286441Srpaulo * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4551286441Srpaulo * @frame_ctrl: frame control 4552286441Srpaulo * @status: for non-agg: frame status IWM_TX_STATUS_* 4553286441Srpaulo * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4554286441Srpaulo * follow this one, up to frame_count. 4555286441Srpaulo * 4556286441Srpaulo * After the array of statuses comes the SSN of the SCD. Look at 4557286441Srpaulo * %iwm_mvm_get_scd_ssn for more details. 4558286441Srpaulo */ 4559286441Srpaulostruct iwm_mvm_tx_resp { 4560286441Srpaulo uint8_t frame_count; 4561286441Srpaulo uint8_t bt_kill_count; 4562286441Srpaulo uint8_t failure_rts; 4563286441Srpaulo uint8_t failure_frame; 4564286441Srpaulo uint32_t initial_rate; 4565286441Srpaulo uint16_t wireless_media_time; 4566286441Srpaulo 4567286441Srpaulo uint8_t pa_status; 4568286441Srpaulo uint8_t pa_integ_res_a[3]; 4569286441Srpaulo uint8_t pa_integ_res_b[3]; 4570286441Srpaulo uint8_t pa_integ_res_c[3]; 4571286441Srpaulo uint16_t measurement_req_id; 4572330226Seadler uint8_t reduced_tpc; 4573330226Seadler uint8_t reserved; 4574286441Srpaulo 4575286441Srpaulo uint32_t tfd_info; 4576286441Srpaulo uint16_t seq_ctl; 4577286441Srpaulo uint16_t byte_cnt; 4578286441Srpaulo uint8_t tlc_info; 4579286441Srpaulo uint8_t ra_tid; 4580286441Srpaulo uint16_t frame_ctrl; 4581286441Srpaulo 4582286441Srpaulo struct iwm_agg_tx_status status; 4583286441Srpaulo} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4584286441Srpaulo 4585286441Srpaulo/** 4586286441Srpaulo * struct iwm_mvm_ba_notif - notifies about reception of BA 4587286441Srpaulo * ( IWM_BA_NOTIF = 0xc5 ) 4588286441Srpaulo * @sta_addr_lo32: lower 32 bits of the MAC address 4589286441Srpaulo * @sta_addr_hi16: upper 16 bits of the MAC address 4590286441Srpaulo * @sta_id: Index of recipient (BA-sending) station in fw's station table 4591286441Srpaulo * @tid: tid of the session 4592286441Srpaulo * @seq_ctl: 4593286441Srpaulo * @bitmap: the bitmap of the BA notification as seen in the air 4594286441Srpaulo * @scd_flow: the tx queue this BA relates to 4595286441Srpaulo * @scd_ssn: the index of the last contiguously sent packet 4596286441Srpaulo * @txed: number of Txed frames in this batch 4597286441Srpaulo * @txed_2_done: number of Acked frames in this batch 4598286441Srpaulo */ 4599286441Srpaulostruct iwm_mvm_ba_notif { 4600286441Srpaulo uint32_t sta_addr_lo32; 4601286441Srpaulo uint16_t sta_addr_hi16; 4602286441Srpaulo uint16_t reserved; 4603286441Srpaulo 4604286441Srpaulo uint8_t sta_id; 4605286441Srpaulo uint8_t tid; 4606286441Srpaulo uint16_t seq_ctl; 4607286441Srpaulo uint64_t bitmap; 4608286441Srpaulo uint16_t scd_flow; 4609286441Srpaulo uint16_t scd_ssn; 4610286441Srpaulo uint8_t txed; 4611286441Srpaulo uint8_t txed_2_done; 4612286441Srpaulo uint16_t reserved1; 4613286441Srpaulo} __packed; 4614286441Srpaulo 4615286441Srpaulo/* 4616286441Srpaulo * struct iwm_mac_beacon_cmd - beacon template command 4617286441Srpaulo * @tx: the tx commands associated with the beacon frame 4618286441Srpaulo * @template_id: currently equal to the mac context id of the coresponding 4619286441Srpaulo * mac. 4620286441Srpaulo * @tim_idx: the offset of the tim IE in the beacon 4621286441Srpaulo * @tim_size: the length of the tim IE 4622286441Srpaulo * @frame: the template of the beacon frame 4623286441Srpaulo */ 4624286441Srpaulostruct iwm_mac_beacon_cmd { 4625286441Srpaulo struct iwm_tx_cmd tx; 4626286441Srpaulo uint32_t template_id; 4627286441Srpaulo uint32_t tim_idx; 4628286441Srpaulo uint32_t tim_size; 4629286441Srpaulo struct ieee80211_frame frame[0]; 4630286441Srpaulo} __packed; 4631286441Srpaulo 4632286441Srpaulostruct iwm_beacon_notif { 4633286441Srpaulo struct iwm_mvm_tx_resp beacon_notify_hdr; 4634286441Srpaulo uint64_t tsf; 4635286441Srpaulo uint32_t ibss_mgr_status; 4636286441Srpaulo} __packed; 4637286441Srpaulo 4638286441Srpaulo/** 4639286441Srpaulo * enum iwm_dump_control - dump (flush) control flags 4640300050Seadler * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4641286441Srpaulo * and the TFD queues are empty. 4642286441Srpaulo */ 4643286441Srpauloenum iwm_dump_control { 4644286441Srpaulo IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4645286441Srpaulo}; 4646286441Srpaulo 4647286441Srpaulo/** 4648286441Srpaulo * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4649286441Srpaulo * @queues_ctl: bitmap of queues to flush 4650286441Srpaulo * @flush_ctl: control flags 4651286441Srpaulo * @reserved: reserved 4652286441Srpaulo */ 4653286441Srpaulostruct iwm_tx_path_flush_cmd { 4654286441Srpaulo uint32_t queues_ctl; 4655286441Srpaulo uint16_t flush_ctl; 4656286441Srpaulo uint16_t reserved; 4657286441Srpaulo} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4658286441Srpaulo 4659286441Srpaulo/** 4660286441Srpaulo * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4661286441Srpaulo * @tx_resp: the Tx response from the fw (agg or non-agg) 4662286441Srpaulo * 4663286441Srpaulo * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4664286441Srpaulo * it can't know that everything will go well until the end of the AMPDU, it 4665286441Srpaulo * can't know in advance the number of MPDUs that will be sent in the current 4666286441Srpaulo * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4667286441Srpaulo * Hence, it can't know in advance what the SSN of the SCD will be at the end 4668286441Srpaulo * of the batch. This is why the SSN of the SCD is written at the end of the 4669286441Srpaulo * whole struct at a variable offset. This function knows how to cope with the 4670286441Srpaulo * variable offset and returns the SSN of the SCD. 4671286441Srpaulo */ 4672286441Srpaulostatic inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4673286441Srpaulo{ 4674286441Srpaulo return le32_to_cpup((uint32_t *)&tx_resp->status + 4675286441Srpaulo tx_resp->frame_count) & 0xfff; 4676286441Srpaulo} 4677286441Srpaulo 4678286441Srpaulo/* 4679286441Srpaulo * END mvm/fw-api-tx.h 4680286441Srpaulo */ 4681286441Srpaulo 4682286441Srpaulo/* 4683286441Srpaulo * BEGIN mvm/fw-api-scan.h 4684286441Srpaulo */ 4685286441Srpaulo 4686303628Ssbruno/** 4687303628Ssbruno * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4688303628Ssbruno * @token: 4689303628Ssbruno * @sta_id: station id 4690303628Ssbruno * @tid: 4691303628Ssbruno * @scd_queue: scheduler queue to confiug 4692303628Ssbruno * @enable: 1 queue enable, 0 queue disable 4693303628Ssbruno * @aggregate: 1 aggregated queue, 0 otherwise 4694303628Ssbruno * @tx_fifo: %enum iwm_mvm_tx_fifo 4695303628Ssbruno * @window: BA window size 4696303628Ssbruno * @ssn: SSN for the BA agreement 4697303628Ssbruno */ 4698303628Ssbrunostruct iwm_scd_txq_cfg_cmd { 4699303628Ssbruno uint8_t token; 4700303628Ssbruno uint8_t sta_id; 4701303628Ssbruno uint8_t tid; 4702303628Ssbruno uint8_t scd_queue; 4703303628Ssbruno uint8_t enable; 4704303628Ssbruno uint8_t aggregate; 4705303628Ssbruno uint8_t tx_fifo; 4706303628Ssbruno uint8_t window; 4707303628Ssbruno uint16_t ssn; 4708303628Ssbruno uint16_t reserved; 4709303628Ssbruno} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4710303628Ssbruno 4711303628Ssbruno/** 4712303628Ssbruno * struct iwm_scd_txq_cfg_rsp 4713303628Ssbruno * @token: taken from the command 4714303628Ssbruno * @sta_id: station id from the command 4715303628Ssbruno * @tid: tid from the command 4716303628Ssbruno * @scd_queue: scd_queue from the command 4717303628Ssbruno */ 4718303628Ssbrunostruct iwm_scd_txq_cfg_rsp { 4719303628Ssbruno uint8_t token; 4720303628Ssbruno uint8_t sta_id; 4721303628Ssbruno uint8_t tid; 4722303628Ssbruno uint8_t scd_queue; 4723303628Ssbruno} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4724303628Ssbruno 4725303628Ssbruno 4726286441Srpaulo/* Scan Commands, Responses, Notifications */ 4727286441Srpaulo 4728286441Srpaulo/* Masks for iwm_scan_channel.type flags */ 4729286441Srpaulo#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4730305762Savos#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4731286441Srpaulo 4732286441Srpaulo/* Max number of IEs for direct SSID scans in a command */ 4733286441Srpaulo#define IWM_PROBE_OPTION_MAX 20 4734286441Srpaulo 4735286441Srpaulo/** 4736286441Srpaulo * struct iwm_ssid_ie - directed scan network information element 4737286441Srpaulo * 4738286441Srpaulo * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4739286441Srpaulo * selected by "type" bit field in struct iwm_scan_channel; 4740286441Srpaulo * each channel may select different ssids from among the 20 entries. 4741286441Srpaulo * SSID IEs get transmitted in reverse order of entry. 4742286441Srpaulo */ 4743286441Srpaulostruct iwm_ssid_ie { 4744286441Srpaulo uint8_t id; 4745286441Srpaulo uint8_t len; 4746286441Srpaulo uint8_t ssid[IEEE80211_NWID_LEN]; 4747286441Srpaulo} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4748286441Srpaulo 4749303628Ssbruno/* scan offload */ 4750303628Ssbruno#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4751303628Ssbruno#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4752303628Ssbruno#define IWM_SCAN_MAX_PROFILES 11 4753303628Ssbruno#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4754303628Ssbruno 4755303628Ssbruno/* Default watchdog (in MS) for scheduled scan iteration */ 4756303628Ssbruno#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4757303628Ssbruno 4758303628Ssbruno#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4759303628Ssbruno#define IWM_CAN_ABORT_STATUS 1 4760303628Ssbruno 4761303628Ssbruno#define IWM_FULL_SCAN_MULTIPLIER 5 4762303628Ssbruno#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4763303628Ssbruno#define IWM_MAX_SCHED_SCAN_PLANS 2 4764303628Ssbruno 4765286441Srpaulo/** 4766303628Ssbruno * iwm_scan_schedule_lmac - schedule of scan offload 4767303628Ssbruno * @delay: delay between iterations, in seconds. 4768303628Ssbruno * @iterations: num of scan iterations 4769303628Ssbruno * @full_scan_mul: number of partial scans before each full scan 4770286441Srpaulo */ 4771303628Ssbrunostruct iwm_scan_schedule_lmac { 4772303628Ssbruno uint16_t delay; 4773303628Ssbruno uint8_t iterations; 4774303628Ssbruno uint8_t full_scan_mul; 4775303628Ssbruno} __packed; /* SCAN_SCHEDULE_API_S */ 4776303628Ssbruno 4777303628Ssbruno/** 4778303628Ssbruno * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4779303628Ssbruno * @tx_flags: combination of TX_CMD_FLG_* 4780303628Ssbruno * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4781303628Ssbruno * cleared. Combination of RATE_MCS_* 4782303628Ssbruno * @sta_id: index of destination station in FW station table 4783303628Ssbruno * @reserved: for alignment and future use 4784303628Ssbruno */ 4785303628Ssbrunostruct iwm_scan_req_tx_cmd { 4786303628Ssbruno uint32_t tx_flags; 4787303628Ssbruno uint32_t rate_n_flags; 4788303628Ssbruno uint8_t sta_id; 4789303628Ssbruno uint8_t reserved[3]; 4790303628Ssbruno} __packed; 4791303628Ssbruno 4792303628Ssbrunoenum iwm_scan_channel_flags_lmac { 4793303628Ssbruno IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4794303628Ssbruno IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4795303628Ssbruno}; 4796303628Ssbruno 4797303628Ssbruno/** 4798303628Ssbruno * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4799303628Ssbruno * @flags: bits 1-20: directed scan to i'th ssid 4800303628Ssbruno * other bits &enum iwm_scan_channel_flags_lmac 4801303628Ssbruno * @channel_number: channel number 1-13 etc 4802303628Ssbruno * @iter_count: scan iteration on this channel 4803303628Ssbruno * @iter_interval: interval in seconds between iterations on one channel 4804303628Ssbruno */ 4805303628Ssbrunostruct iwm_scan_channel_cfg_lmac { 4806303628Ssbruno uint32_t flags; 4807303628Ssbruno uint16_t channel_num; 4808303628Ssbruno uint16_t iter_count; 4809303628Ssbruno uint32_t iter_interval; 4810303628Ssbruno} __packed; 4811303628Ssbruno 4812303628Ssbruno/* 4813303628Ssbruno * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4814303628Ssbruno * @offset: offset in the data block 4815303628Ssbruno * @len: length of the segment 4816303628Ssbruno */ 4817303628Ssbrunostruct iwm_scan_probe_segment { 4818303628Ssbruno uint16_t offset; 4819286441Srpaulo uint16_t len; 4820303628Ssbruno} __packed; 4821303628Ssbruno 4822303628Ssbruno/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4823303628Ssbruno * @mac_header: first (and common) part of the probe 4824303628Ssbruno * @band_data: band specific data 4825303628Ssbruno * @common_data: last (and common) part of the probe 4826303628Ssbruno * @buf: raw data block 4827303628Ssbruno */ 4828303628Ssbrunostruct iwm_scan_probe_req { 4829303628Ssbruno struct iwm_scan_probe_segment mac_header; 4830303628Ssbruno struct iwm_scan_probe_segment band_data[2]; 4831303628Ssbruno struct iwm_scan_probe_segment common_data; 4832303628Ssbruno uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4833303628Ssbruno} __packed; 4834303628Ssbruno 4835303628Ssbrunoenum iwm_scan_channel_flags { 4836303628Ssbruno IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4837303628Ssbruno IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4838303628Ssbruno IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4839303628Ssbruno}; 4840303628Ssbruno 4841303628Ssbruno/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4842303628Ssbruno * @flags: enum iwm_scan_channel_flags 4843303628Ssbruno * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4844303628Ssbruno * involved. 4845303628Ssbruno * 1 - EBS is disabled. 4846303628Ssbruno * 2 - every second scan will be full scan(and so on). 4847303628Ssbruno */ 4848303628Ssbrunostruct iwm_scan_channel_opt { 4849303628Ssbruno uint16_t flags; 4850303628Ssbruno uint16_t non_ebs_ratio; 4851303628Ssbruno} __packed; 4852303628Ssbruno 4853303628Ssbruno/** 4854303628Ssbruno * iwm_mvm_lmac_scan_flags 4855303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4856303628Ssbruno * without filtering. 4857303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4858303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4859303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4860303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4861303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4862303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4863303628Ssbruno * and DS parameter set IEs into probe requests. 4864303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4865303628Ssbruno * 1, 6 and 11. 4866303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4867303628Ssbruno */ 4868303628Ssbrunoenum iwm_mvm_lmac_scan_flags { 4869303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4870303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4871303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4872303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4873303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4874303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4875303628Ssbruno IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4876303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4877303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4878303628Ssbruno}; 4879303628Ssbruno 4880303628Ssbrunoenum iwm_scan_priority { 4881303628Ssbruno IWM_SCAN_PRIORITY_LOW, 4882303628Ssbruno IWM_SCAN_PRIORITY_MEDIUM, 4883303628Ssbruno IWM_SCAN_PRIORITY_HIGH, 4884303628Ssbruno}; 4885303628Ssbruno 4886303628Ssbruno/** 4887303628Ssbruno * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4888303628Ssbruno * @reserved1: for alignment and future use 4889303628Ssbruno * @channel_num: num of channels to scan 4890303628Ssbruno * @active-dwell: dwell time for active channels 4891303628Ssbruno * @passive-dwell: dwell time for passive channels 4892303628Ssbruno * @fragmented-dwell: dwell time for fragmented passive scan 4893303628Ssbruno * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4894303628Ssbruno * @reserved2: for alignment and future use 4895303628Ssbruno * @rx_chain_selct: PHY_RX_CHAIN_* flags 4896303628Ssbruno * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4897303628Ssbruno * @max_out_time: max time (in TU) to be out of associated channel 4898303628Ssbruno * @suspend_time: pause scan this long (TUs) when returning to service channel 4899303628Ssbruno * @flags: RXON flags 4900303628Ssbruno * @filter_flags: RXON filter 4901303628Ssbruno * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4902303628Ssbruno * @direct_scan: list of SSIDs for directed active scan 4903303628Ssbruno * @scan_prio: enum iwm_scan_priority 4904303628Ssbruno * @iter_num: number of scan iterations 4905303628Ssbruno * @delay: delay in seconds before first iteration 4906303628Ssbruno * @schedule: two scheduling plans. The first one is finite, the second one can 4907303628Ssbruno * be infinite. 4908303628Ssbruno * @channel_opt: channel optimization options, for full and partial scan 4909303628Ssbruno * @data: channel configuration and probe request packet. 4910303628Ssbruno */ 4911303628Ssbrunostruct iwm_scan_req_lmac { 4912303628Ssbruno /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4913303628Ssbruno uint32_t reserved1; 4914303628Ssbruno uint8_t n_channels; 4915303628Ssbruno uint8_t active_dwell; 4916303628Ssbruno uint8_t passive_dwell; 4917303628Ssbruno uint8_t fragmented_dwell; 4918303628Ssbruno uint8_t extended_dwell; 4919303628Ssbruno uint8_t reserved2; 4920303628Ssbruno uint16_t rx_chain_select; 4921303628Ssbruno uint32_t scan_flags; 4922286441Srpaulo uint32_t max_out_time; 4923286441Srpaulo uint32_t suspend_time; 4924303628Ssbruno /* RX_ON_FLAGS_API_S_VER_1 */ 4925303628Ssbruno uint32_t flags; 4926286441Srpaulo uint32_t filter_flags; 4927303628Ssbruno struct iwm_scan_req_tx_cmd tx_cmd[2]; 4928286441Srpaulo struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4929303628Ssbruno uint32_t scan_prio; 4930303628Ssbruno /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4931303628Ssbruno uint32_t iter_num; 4932303628Ssbruno uint32_t delay; 4933303628Ssbruno struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4934303628Ssbruno struct iwm_scan_channel_opt channel_opt[2]; 4935303628Ssbruno uint8_t data[]; 4936303628Ssbruno} __packed; 4937286441Srpaulo 4938303628Ssbruno/** 4939303628Ssbruno * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4940303628Ssbruno * @last_schedule_line: last schedule line executed (fast or regular) 4941303628Ssbruno * @last_schedule_iteration: last scan iteration executed before scan abort 4942303628Ssbruno * @status: enum iwm_scan_offload_complete_status 4943303628Ssbruno * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4944303628Ssbruno * @time_after_last_iter; time in seconds elapsed after last iteration 4945303628Ssbruno */ 4946303628Ssbrunostruct iwm_periodic_scan_complete { 4947303628Ssbruno uint8_t last_schedule_line; 4948303628Ssbruno uint8_t last_schedule_iteration; 4949303628Ssbruno uint8_t status; 4950303628Ssbruno uint8_t ebs_status; 4951303628Ssbruno uint32_t time_after_last_iter; 4952303628Ssbruno uint32_t reserved; 4953303628Ssbruno} __packed; 4954286441Srpaulo 4955286441Srpaulo/* How many statistics are gathered for each channel */ 4956286441Srpaulo#define IWM_SCAN_RESULTS_STATISTICS 1 4957286441Srpaulo 4958286441Srpaulo/** 4959286441Srpaulo * enum iwm_scan_complete_status - status codes for scan complete notifications 4960286441Srpaulo * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4961286441Srpaulo * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4962286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4963286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4964286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4965286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4966286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4967286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4968286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4969286441Srpaulo * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4970286441Srpaulo * (not an error!) 4971286441Srpaulo * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4972286441Srpaulo * asked for 4973286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4974286441Srpaulo*/ 4975286441Srpauloenum iwm_scan_complete_status { 4976286441Srpaulo IWM_SCAN_COMP_STATUS_OK = 0x1, 4977286441Srpaulo IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4978286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4979286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4980286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4981286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4982286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4983286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4984286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4985286441Srpaulo IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4986286441Srpaulo IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4987286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4988286441Srpaulo}; 4989286441Srpaulo 4990286441Srpaulo/** 4991286441Srpaulo * struct iwm_scan_results_notif - scan results for one channel 4992286441Srpaulo * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4993286441Srpaulo * @channel: which channel the results are from 4994286441Srpaulo * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4995286441Srpaulo * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4996286441Srpaulo * @num_probe_not_sent: # of request that weren't sent due to not enough time 4997286441Srpaulo * @duration: duration spent in channel, in usecs 4998286441Srpaulo * @statistics: statistics gathered for this channel 4999286441Srpaulo */ 5000286441Srpaulostruct iwm_scan_results_notif { 5001286441Srpaulo uint8_t channel; 5002286441Srpaulo uint8_t band; 5003286441Srpaulo uint8_t probe_status; 5004286441Srpaulo uint8_t num_probe_not_sent; 5005286441Srpaulo uint32_t duration; 5006286441Srpaulo uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5007286441Srpaulo} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5008286441Srpaulo 5009286441Srpauloenum iwm_scan_framework_client { 5010286441Srpaulo IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5011286441Srpaulo IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5012286441Srpaulo IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5013286441Srpaulo}; 5014286441Srpaulo 5015286441Srpaulo/** 5016286441Srpaulo * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5017286441Srpaulo * @ssid: MAC address to filter out 5018286441Srpaulo * @reported_rssi: AP rssi reported to the host 5019286441Srpaulo * @client_bitmap: clients ignore this entry - enum scan_framework_client 5020286441Srpaulo */ 5021286441Srpaulostruct iwm_scan_offload_blacklist { 5022286441Srpaulo uint8_t ssid[IEEE80211_ADDR_LEN]; 5023286441Srpaulo uint8_t reported_rssi; 5024286441Srpaulo uint8_t client_bitmap; 5025286441Srpaulo} __packed; 5026286441Srpaulo 5027286441Srpauloenum iwm_scan_offload_network_type { 5028286441Srpaulo IWM_NETWORK_TYPE_BSS = 1, 5029286441Srpaulo IWM_NETWORK_TYPE_IBSS = 2, 5030286441Srpaulo IWM_NETWORK_TYPE_ANY = 3, 5031286441Srpaulo}; 5032286441Srpaulo 5033286441Srpauloenum iwm_scan_offload_band_selection { 5034286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5035286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5036286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5037286441Srpaulo}; 5038286441Srpaulo 5039286441Srpaulo/** 5040286441Srpaulo * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5041286441Srpaulo * @ssid_index: index to ssid list in fixed part 5042286441Srpaulo * @unicast_cipher: encryption olgorithm to match - bitmap 5043286441Srpaulo * @aut_alg: authentication olgorithm to match - bitmap 5044286441Srpaulo * @network_type: enum iwm_scan_offload_network_type 5045286441Srpaulo * @band_selection: enum iwm_scan_offload_band_selection 5046286441Srpaulo * @client_bitmap: clients waiting for match - enum scan_framework_client 5047286441Srpaulo */ 5048286441Srpaulostruct iwm_scan_offload_profile { 5049286441Srpaulo uint8_t ssid_index; 5050286441Srpaulo uint8_t unicast_cipher; 5051286441Srpaulo uint8_t auth_alg; 5052286441Srpaulo uint8_t network_type; 5053286441Srpaulo uint8_t band_selection; 5054286441Srpaulo uint8_t client_bitmap; 5055286441Srpaulo uint8_t reserved[2]; 5056286441Srpaulo} __packed; 5057286441Srpaulo 5058286441Srpaulo/** 5059286441Srpaulo * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5060286441Srpaulo * @blaclist: AP list to filter off from scan results 5061286441Srpaulo * @profiles: profiles to search for match 5062286441Srpaulo * @blacklist_len: length of blacklist 5063286441Srpaulo * @num_profiles: num of profiles in the list 5064286441Srpaulo * @match_notify: clients waiting for match found notification 5065286441Srpaulo * @pass_match: clients waiting for the results 5066286441Srpaulo * @active_clients: active clients bitmap - enum scan_framework_client 5067286441Srpaulo * @any_beacon_notify: clients waiting for match notification without match 5068286441Srpaulo */ 5069286441Srpaulostruct iwm_scan_offload_profile_cfg { 5070286441Srpaulo struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5071286441Srpaulo uint8_t blacklist_len; 5072286441Srpaulo uint8_t num_profiles; 5073286441Srpaulo uint8_t match_notify; 5074286441Srpaulo uint8_t pass_match; 5075286441Srpaulo uint8_t active_clients; 5076286441Srpaulo uint8_t any_beacon_notify; 5077286441Srpaulo uint8_t reserved[2]; 5078286441Srpaulo} __packed; 5079286441Srpaulo 5080330151Seadlerenum iwm_scan_offload_complete_status { 5081286441Srpaulo IWM_SCAN_OFFLOAD_COMPLETED = 1, 5082286441Srpaulo IWM_SCAN_OFFLOAD_ABORTED = 2, 5083286441Srpaulo}; 5084286441Srpaulo 5085286441Srpaulo/** 5086303628Ssbruno * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5087303628Ssbruno * SCAN_COMPLETE_NTF_API_S_VER_3 5088303628Ssbruno * @scanned_channels: number of channels scanned (and number of valid results) 5089303628Ssbruno * @status: one of SCAN_COMP_STATUS_* 5090303628Ssbruno * @bt_status: BT on/off status 5091303628Ssbruno * @last_channel: last channel that was scanned 5092303628Ssbruno * @tsf_low: TSF timer (lower half) in usecs 5093303628Ssbruno * @tsf_high: TSF timer (higher half) in usecs 5094303628Ssbruno * @results: an array of scan results, only "scanned_channels" of them are valid 5095303628Ssbruno */ 5096303628Ssbrunostruct iwm_lmac_scan_complete_notif { 5097303628Ssbruno uint8_t scanned_channels; 5098303628Ssbruno uint8_t status; 5099303628Ssbruno uint8_t bt_status; 5100303628Ssbruno uint8_t last_channel; 5101303628Ssbruno uint32_t tsf_low; 5102303628Ssbruno uint32_t tsf_high; 5103303628Ssbruno struct iwm_scan_results_notif results[]; 5104303628Ssbruno} __packed; 5105303628Ssbruno 5106303628Ssbruno 5107286441Srpaulo/* 5108286441Srpaulo * END mvm/fw-api-scan.h 5109286441Srpaulo */ 5110286441Srpaulo 5111286441Srpaulo/* 5112286441Srpaulo * BEGIN mvm/fw-api-sta.h 5113286441Srpaulo */ 5114286441Srpaulo 5115303628Ssbruno/* UMAC Scan API */ 5116303628Ssbruno 5117303628Ssbruno/* The maximum of either of these cannot exceed 8, because we use an 5118303628Ssbruno * 8-bit mask (see IWM_MVM_SCAN_MASK). 5119303628Ssbruno */ 5120303628Ssbruno#define IWM_MVM_MAX_UMAC_SCANS 8 5121303628Ssbruno#define IWM_MVM_MAX_LMAC_SCANS 1 5122303628Ssbruno 5123303628Ssbrunoenum iwm_scan_config_flags { 5124303628Ssbruno IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5125303628Ssbruno IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5126303628Ssbruno IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5127303628Ssbruno IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5128303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5129303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5130303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5131303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5132303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5133303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5134303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5135303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5136303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5137303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5138303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5139303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5140303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5141303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5142303628Ssbruno 5143303628Ssbruno /* Bits 26-31 are for num of channels in channel_array */ 5144303628Ssbruno#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5145303628Ssbruno}; 5146303628Ssbruno 5147303628Ssbrunoenum iwm_scan_config_rates { 5148303628Ssbruno /* OFDM basic rates */ 5149303628Ssbruno IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5150303628Ssbruno IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5151303628Ssbruno IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5152303628Ssbruno IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5153303628Ssbruno IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5154303628Ssbruno IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5155303628Ssbruno IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5156303628Ssbruno IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5157303628Ssbruno /* CCK basic rates */ 5158303628Ssbruno IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5159303628Ssbruno IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5160303628Ssbruno IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5161303628Ssbruno IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5162303628Ssbruno 5163303628Ssbruno /* Bits 16-27 are for supported rates */ 5164303628Ssbruno#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5165303628Ssbruno}; 5166303628Ssbruno 5167303628Ssbrunoenum iwm_channel_flags { 5168303628Ssbruno IWM_CHANNEL_FLAG_EBS = (1 << 0), 5169303628Ssbruno IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5170303628Ssbruno IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5171303628Ssbruno IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5172303628Ssbruno}; 5173303628Ssbruno 5174286441Srpaulo/** 5175303628Ssbruno * struct iwm_scan_config 5176303628Ssbruno * @flags: enum scan_config_flags 5177303628Ssbruno * @tx_chains: valid_tx antenna - ANT_* definitions 5178303628Ssbruno * @rx_chains: valid_rx antenna - ANT_* definitions 5179303628Ssbruno * @legacy_rates: default legacy rates - enum scan_config_rates 5180303628Ssbruno * @out_of_channel_time: default max out of serving channel time 5181303628Ssbruno * @suspend_time: default max suspend time 5182303628Ssbruno * @dwell_active: default dwell time for active scan 5183303628Ssbruno * @dwell_passive: default dwell time for passive scan 5184303628Ssbruno * @dwell_fragmented: default dwell time for fragmented scan 5185303628Ssbruno * @dwell_extended: default dwell time for channels 1, 6 and 11 5186303628Ssbruno * @mac_addr: default mac address to be used in probes 5187303628Ssbruno * @bcast_sta_id: the index of the station in the fw 5188303628Ssbruno * @channel_flags: default channel flags - enum iwm_channel_flags 5189303628Ssbruno * scan_config_channel_flag 5190303628Ssbruno * @channel_array: default supported channels 5191303628Ssbruno */ 5192303628Ssbrunostruct iwm_scan_config { 5193303628Ssbruno uint32_t flags; 5194303628Ssbruno uint32_t tx_chains; 5195303628Ssbruno uint32_t rx_chains; 5196303628Ssbruno uint32_t legacy_rates; 5197303628Ssbruno uint32_t out_of_channel_time; 5198303628Ssbruno uint32_t suspend_time; 5199303628Ssbruno uint8_t dwell_active; 5200303628Ssbruno uint8_t dwell_passive; 5201303628Ssbruno uint8_t dwell_fragmented; 5202303628Ssbruno uint8_t dwell_extended; 5203303628Ssbruno uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5204303628Ssbruno uint8_t bcast_sta_id; 5205303628Ssbruno uint8_t channel_flags; 5206303628Ssbruno uint8_t channel_array[]; 5207303628Ssbruno} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5208303628Ssbruno 5209303628Ssbruno/** 5210303628Ssbruno * iwm_umac_scan_flags 5211303628Ssbruno *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5212303628Ssbruno * can be preempted by other scan requests with higher priority. 5213303628Ssbruno * The low priority scan will be resumed when the higher proirity scan is 5214303628Ssbruno * completed. 5215303628Ssbruno *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5216303628Ssbruno * when scan starts. 5217303628Ssbruno */ 5218303628Ssbrunoenum iwm_umac_scan_flags { 5219303628Ssbruno IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5220303628Ssbruno IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5221303628Ssbruno}; 5222303628Ssbruno 5223303628Ssbrunoenum iwm_umac_scan_uid_offsets { 5224303628Ssbruno IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5225303628Ssbruno IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5226303628Ssbruno}; 5227303628Ssbruno 5228303628Ssbrunoenum iwm_umac_scan_general_flags { 5229303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5230303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5231303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5232303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5233303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5234303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5235303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5236303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5237303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5238303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5239303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5240303628Ssbruno}; 5241303628Ssbruno 5242303628Ssbruno/** 5243303628Ssbruno * struct iwm_scan_channel_cfg_umac 5244303628Ssbruno * @flags: bitmap - 0-19: directed scan to i'th ssid. 5245303628Ssbruno * @channel_num: channel number 1-13 etc. 5246303628Ssbruno * @iter_count: repetition count for the channel. 5247303628Ssbruno * @iter_interval: interval between two scan iterations on one channel. 5248303628Ssbruno */ 5249303628Ssbrunostruct iwm_scan_channel_cfg_umac { 5250303628Ssbruno uint32_t flags; 5251305762Savos#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5252305762Savos 5253303628Ssbruno uint8_t channel_num; 5254303628Ssbruno uint8_t iter_count; 5255303628Ssbruno uint16_t iter_interval; 5256303628Ssbruno} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5257303628Ssbruno 5258303628Ssbruno/** 5259303628Ssbruno * struct iwm_scan_umac_schedule 5260303628Ssbruno * @interval: interval in seconds between scan iterations 5261303628Ssbruno * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5262303628Ssbruno * @reserved: for alignment and future use 5263303628Ssbruno */ 5264303628Ssbrunostruct iwm_scan_umac_schedule { 5265303628Ssbruno uint16_t interval; 5266303628Ssbruno uint8_t iter_count; 5267303628Ssbruno uint8_t reserved; 5268303628Ssbruno} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5269303628Ssbruno 5270303628Ssbruno/** 5271303628Ssbruno * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5272303628Ssbruno * parameters following channels configuration array. 5273303628Ssbruno * @schedule: two scheduling plans. 5274303628Ssbruno * @delay: delay in TUs before starting the first scan iteration 5275303628Ssbruno * @reserved: for future use and alignment 5276303628Ssbruno * @preq: probe request with IEs blocks 5277303628Ssbruno * @direct_scan: list of SSIDs for directed active scan 5278303628Ssbruno */ 5279303628Ssbrunostruct iwm_scan_req_umac_tail { 5280303628Ssbruno /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5281303628Ssbruno struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5282303628Ssbruno uint16_t delay; 5283303628Ssbruno uint16_t reserved; 5284303628Ssbruno /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5285303628Ssbruno struct iwm_scan_probe_req preq; 5286303628Ssbruno struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5287303628Ssbruno} __packed; 5288303628Ssbruno 5289303628Ssbruno/** 5290303628Ssbruno * struct iwm_scan_req_umac 5291303628Ssbruno * @flags: &enum iwm_umac_scan_flags 5292303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5293303628Ssbruno * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5294303628Ssbruno * @general_flags: &enum iwm_umac_scan_general_flags 5295303628Ssbruno * @extended_dwell: dwell time for channels 1, 6 and 11 5296303628Ssbruno * @active_dwell: dwell time for active scan 5297303628Ssbruno * @passive_dwell: dwell time for passive scan 5298303628Ssbruno * @fragmented_dwell: dwell time for fragmented passive scan 5299303628Ssbruno * @max_out_time: max out of serving channel time 5300303628Ssbruno * @suspend_time: max suspend time 5301303628Ssbruno * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5302303628Ssbruno * @channel_flags: &enum iwm_scan_channel_flags 5303303628Ssbruno * @n_channels: num of channels in scan request 5304303628Ssbruno * @reserved: for future use and alignment 5305303628Ssbruno * @data: &struct iwm_scan_channel_cfg_umac and 5306303628Ssbruno * &struct iwm_scan_req_umac_tail 5307303628Ssbruno */ 5308303628Ssbrunostruct iwm_scan_req_umac { 5309303628Ssbruno uint32_t flags; 5310303628Ssbruno uint32_t uid; 5311303628Ssbruno uint32_t ooc_priority; 5312303628Ssbruno /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5313303628Ssbruno uint32_t general_flags; 5314303628Ssbruno uint8_t extended_dwell; 5315303628Ssbruno uint8_t active_dwell; 5316303628Ssbruno uint8_t passive_dwell; 5317303628Ssbruno uint8_t fragmented_dwell; 5318303628Ssbruno uint32_t max_out_time; 5319303628Ssbruno uint32_t suspend_time; 5320303628Ssbruno uint32_t scan_priority; 5321303628Ssbruno /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5322303628Ssbruno uint8_t channel_flags; 5323303628Ssbruno uint8_t n_channels; 5324303628Ssbruno uint16_t reserved; 5325303628Ssbruno uint8_t data[]; 5326303628Ssbruno} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5327303628Ssbruno 5328303628Ssbruno/** 5329303628Ssbruno * struct iwm_umac_scan_abort 5330303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5331303628Ssbruno * @flags: reserved 5332303628Ssbruno */ 5333303628Ssbrunostruct iwm_umac_scan_abort { 5334303628Ssbruno uint32_t uid; 5335303628Ssbruno uint32_t flags; 5336303628Ssbruno} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5337303628Ssbruno 5338303628Ssbruno/** 5339303628Ssbruno * struct iwm_umac_scan_complete 5340303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5341303628Ssbruno * @last_schedule: last scheduling line 5342303628Ssbruno * @last_iter: last scan iteration number 5343303628Ssbruno * @scan status: &enum iwm_scan_offload_complete_status 5344303628Ssbruno * @ebs_status: &enum iwm_scan_ebs_status 5345303628Ssbruno * @time_from_last_iter: time elapsed from last iteration 5346303628Ssbruno * @reserved: for future use 5347303628Ssbruno */ 5348303628Ssbrunostruct iwm_umac_scan_complete { 5349303628Ssbruno uint32_t uid; 5350303628Ssbruno uint8_t last_schedule; 5351303628Ssbruno uint8_t last_iter; 5352303628Ssbruno uint8_t status; 5353303628Ssbruno uint8_t ebs_status; 5354303628Ssbruno uint32_t time_from_last_iter; 5355303628Ssbruno uint32_t reserved; 5356303628Ssbruno} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5357303628Ssbruno 5358303628Ssbruno#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5359303628Ssbruno/** 5360303628Ssbruno * struct iwm_scan_offload_profile_match - match information 5361303628Ssbruno * @bssid: matched bssid 5362303628Ssbruno * @channel: channel where the match occurred 5363303628Ssbruno * @energy: 5364303628Ssbruno * @matching_feature: 5365303628Ssbruno * @matching_channels: bitmap of channels that matched, referencing 5366303628Ssbruno * the channels passed in tue scan offload request 5367303628Ssbruno */ 5368303628Ssbrunostruct iwm_scan_offload_profile_match { 5369303628Ssbruno uint8_t bssid[IEEE80211_ADDR_LEN]; 5370303628Ssbruno uint16_t reserved; 5371303628Ssbruno uint8_t channel; 5372303628Ssbruno uint8_t energy; 5373303628Ssbruno uint8_t matching_feature; 5374303628Ssbruno uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5375303628Ssbruno} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5376303628Ssbruno 5377303628Ssbruno/** 5378303628Ssbruno * struct iwm_scan_offload_profiles_query - match results query response 5379303628Ssbruno * @matched_profiles: bitmap of matched profiles, referencing the 5380303628Ssbruno * matches passed in the scan offload request 5381303628Ssbruno * @last_scan_age: age of the last offloaded scan 5382303628Ssbruno * @n_scans_done: number of offloaded scans done 5383303628Ssbruno * @gp2_d0u: GP2 when D0U occurred 5384303628Ssbruno * @gp2_invoked: GP2 when scan offload was invoked 5385303628Ssbruno * @resume_while_scanning: not used 5386303628Ssbruno * @self_recovery: obsolete 5387303628Ssbruno * @reserved: reserved 5388303628Ssbruno * @matches: array of match information, one for each match 5389303628Ssbruno */ 5390303628Ssbrunostruct iwm_scan_offload_profiles_query { 5391303628Ssbruno uint32_t matched_profiles; 5392303628Ssbruno uint32_t last_scan_age; 5393303628Ssbruno uint32_t n_scans_done; 5394303628Ssbruno uint32_t gp2_d0u; 5395303628Ssbruno uint32_t gp2_invoked; 5396303628Ssbruno uint8_t resume_while_scanning; 5397303628Ssbruno uint8_t self_recovery; 5398303628Ssbruno uint16_t reserved; 5399303628Ssbruno struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5400303628Ssbruno} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5401303628Ssbruno 5402303628Ssbruno/** 5403303628Ssbruno * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5404303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5405303628Ssbruno * @scanned_channels: number of channels scanned and number of valid elements in 5406303628Ssbruno * results array 5407303628Ssbruno * @status: one of SCAN_COMP_STATUS_* 5408303628Ssbruno * @bt_status: BT on/off status 5409303628Ssbruno * @last_channel: last channel that was scanned 5410303628Ssbruno * @tsf_low: TSF timer (lower half) in usecs 5411303628Ssbruno * @tsf_high: TSF timer (higher half) in usecs 5412303628Ssbruno * @results: array of scan results, only "scanned_channels" of them are valid 5413303628Ssbruno */ 5414303628Ssbrunostruct iwm_umac_scan_iter_complete_notif { 5415303628Ssbruno uint32_t uid; 5416303628Ssbruno uint8_t scanned_channels; 5417303628Ssbruno uint8_t status; 5418303628Ssbruno uint8_t bt_status; 5419303628Ssbruno uint8_t last_channel; 5420303628Ssbruno uint32_t tsf_low; 5421303628Ssbruno uint32_t tsf_high; 5422303628Ssbruno struct iwm_scan_results_notif results[]; 5423303628Ssbruno} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5424303628Ssbruno 5425303628Ssbruno/* Please keep this enum *SORTED* by hex value. 5426303628Ssbruno * Needed for binary search, otherwise a warning will be triggered. 5427303628Ssbruno */ 5428303628Ssbrunoenum iwm_scan_subcmd_ids { 5429303628Ssbruno IWM_GSCAN_START_CMD = 0x0, 5430303628Ssbruno IWM_GSCAN_STOP_CMD = 0x1, 5431303628Ssbruno IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5432303628Ssbruno IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5433303628Ssbruno IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5434303628Ssbruno IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5435303628Ssbruno IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5436303628Ssbruno IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5437303628Ssbruno IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5438303628Ssbruno}; 5439303628Ssbruno 5440303628Ssbruno/* STA API */ 5441303628Ssbruno 5442303628Ssbruno/** 5443286441Srpaulo * enum iwm_sta_flags - flags for the ADD_STA host command 5444286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5445286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5446303628Ssbruno * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5447286441Srpaulo * @IWM_STA_FLG_PS: set if STA is in Power Save 5448286441Srpaulo * @IWM_STA_FLG_INVALID: set if STA is invalid 5449286441Srpaulo * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5450286441Srpaulo * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5451286441Srpaulo * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5452286441Srpaulo * @IWM_STA_FLG_PAN: STA is for PAN interface 5453286441Srpaulo * @IWM_STA_FLG_CLASS_AUTH: 5454286441Srpaulo * @IWM_STA_FLG_CLASS_ASSOC: 5455286441Srpaulo * @IWM_STA_FLG_CLASS_MIMO_PROT: 5456286441Srpaulo * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5457286441Srpaulo * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5458286441Srpaulo * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5459286441Srpaulo * initialised by driver and can be updated by fw upon reception of 5460286441Srpaulo * action frames that can change the channel width. When cleared the fw 5461286441Srpaulo * will send all the frames in 20MHz even when FAT channel is requested. 5462286441Srpaulo * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5463286441Srpaulo * driver and can be updated by fw upon reception of action frames. 5464286441Srpaulo * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5465286441Srpaulo */ 5466286441Srpauloenum iwm_sta_flags { 5467286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5468286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5469286441Srpaulo 5470303628Ssbruno IWM_STA_FLG_DISABLE_TX = (1 << 4), 5471286441Srpaulo 5472286441Srpaulo IWM_STA_FLG_PS = (1 << 8), 5473286441Srpaulo IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5474286441Srpaulo IWM_STA_FLG_PAN = (1 << 13), 5475286441Srpaulo IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5476286441Srpaulo IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5477286441Srpaulo IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5478286441Srpaulo 5479286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5480286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5481286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5482286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5483286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5484286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5485286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5486286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5487286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5488286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5489286441Srpaulo 5490286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5491286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5492286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5493286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5494286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5495286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5496286441Srpaulo 5497286441Srpaulo IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5498286441Srpaulo IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5499286441Srpaulo IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5500286441Srpaulo IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5501286441Srpaulo IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5502286441Srpaulo 5503286441Srpaulo IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5504286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5505286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5506286441Srpaulo IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5507286441Srpaulo}; 5508286441Srpaulo 5509286441Srpaulo/** 5510286441Srpaulo * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5511286441Srpaulo * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5512286441Srpaulo * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5513286441Srpaulo * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5514286441Srpaulo * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5515286441Srpaulo * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5516286441Srpaulo * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5517286441Srpaulo * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5518286441Srpaulo * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5519286441Srpaulo * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5520286441Srpaulo * station info array (1 - n 1X mode) 5521286441Srpaulo * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5522286441Srpaulo * @IWM_STA_KEY_NOT_VALID: key is invalid 5523286441Srpaulo * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5524286441Srpaulo * @IWM_STA_KEY_MULTICAST: set for multical key 5525286441Srpaulo * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5526286441Srpaulo */ 5527286441Srpauloenum iwm_sta_key_flag { 5528286441Srpaulo IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5529286441Srpaulo IWM_STA_KEY_FLG_WEP = (1 << 0), 5530286441Srpaulo IWM_STA_KEY_FLG_CCM = (2 << 0), 5531286441Srpaulo IWM_STA_KEY_FLG_TKIP = (3 << 0), 5532286441Srpaulo IWM_STA_KEY_FLG_EXT = (4 << 0), 5533286441Srpaulo IWM_STA_KEY_FLG_CMAC = (6 << 0), 5534286441Srpaulo IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5535286441Srpaulo IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5536286441Srpaulo 5537286441Srpaulo IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5538286441Srpaulo IWM_STA_KEY_FLG_KEYID_POS = 8, 5539286441Srpaulo IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5540286441Srpaulo IWM_STA_KEY_NOT_VALID = (1 << 11), 5541286441Srpaulo IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5542286441Srpaulo IWM_STA_KEY_MULTICAST = (1 << 14), 5543286441Srpaulo IWM_STA_KEY_MFP = (1 << 15), 5544286441Srpaulo}; 5545286441Srpaulo 5546286441Srpaulo/** 5547286441Srpaulo * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5548303628Ssbruno * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5549286441Srpaulo * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5550286441Srpaulo * @IWM_STA_MODIFY_TX_RATE: unused 5551286441Srpaulo * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5552286441Srpaulo * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5553286441Srpaulo * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5554286441Srpaulo * @IWM_STA_MODIFY_PROT_TH: 5555286441Srpaulo * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5556286441Srpaulo */ 5557286441Srpauloenum iwm_sta_modify_flag { 5558303628Ssbruno IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5559286441Srpaulo IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5560286441Srpaulo IWM_STA_MODIFY_TX_RATE = (1 << 2), 5561286441Srpaulo IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5562286441Srpaulo IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5563286441Srpaulo IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5564286441Srpaulo IWM_STA_MODIFY_PROT_TH = (1 << 6), 5565286441Srpaulo IWM_STA_MODIFY_QUEUES = (1 << 7), 5566286441Srpaulo}; 5567286441Srpaulo 5568286441Srpaulo#define IWM_STA_MODE_MODIFY 1 5569286441Srpaulo 5570286441Srpaulo/** 5571286441Srpaulo * enum iwm_sta_sleep_flag - type of sleep of the station 5572286441Srpaulo * @IWM_STA_SLEEP_STATE_AWAKE: 5573286441Srpaulo * @IWM_STA_SLEEP_STATE_PS_POLL: 5574286441Srpaulo * @IWM_STA_SLEEP_STATE_UAPSD: 5575303628Ssbruno * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5576303628Ssbruno * (last) released frame 5577286441Srpaulo */ 5578286441Srpauloenum iwm_sta_sleep_flag { 5579286441Srpaulo IWM_STA_SLEEP_STATE_AWAKE = 0, 5580286441Srpaulo IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5581286441Srpaulo IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5582303628Ssbruno IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5583286441Srpaulo}; 5584286441Srpaulo 5585286441Srpaulo/* STA ID and color bits definitions */ 5586286441Srpaulo#define IWM_STA_ID_SEED (0x0f) 5587286441Srpaulo#define IWM_STA_ID_POS (0) 5588286441Srpaulo#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5589286441Srpaulo 5590286441Srpaulo#define IWM_STA_COLOR_SEED (0x7) 5591286441Srpaulo#define IWM_STA_COLOR_POS (4) 5592286441Srpaulo#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5593286441Srpaulo 5594286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5595286441Srpaulo (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5596286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5597286441Srpaulo (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5598286441Srpaulo 5599286441Srpaulo#define IWM_STA_KEY_MAX_NUM (16) 5600286441Srpaulo#define IWM_STA_KEY_IDX_INVALID (0xff) 5601286441Srpaulo#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5602286441Srpaulo#define IWM_MAX_GLOBAL_KEYS (4) 5603286441Srpaulo#define IWM_STA_KEY_LEN_WEP40 (5) 5604286441Srpaulo#define IWM_STA_KEY_LEN_WEP104 (13) 5605286441Srpaulo 5606286441Srpaulo/** 5607286441Srpaulo * struct iwm_mvm_keyinfo - key information 5608286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5609286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5610286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5611286441Srpaulo * @key_offset: key offset in the fw's key table 5612286441Srpaulo * @key: 16-byte unicast decryption key 5613286441Srpaulo * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5614286441Srpaulo * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5615286441Srpaulo * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5616286441Srpaulo */ 5617286441Srpaulostruct iwm_mvm_keyinfo { 5618286441Srpaulo uint16_t key_flags; 5619286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5620286441Srpaulo uint8_t reserved1; 5621286441Srpaulo uint16_t tkip_rx_ttak[5]; 5622286441Srpaulo uint8_t key_offset; 5623286441Srpaulo uint8_t reserved2; 5624286441Srpaulo uint8_t key[16]; 5625286441Srpaulo uint64_t tx_secur_seq_cnt; 5626286441Srpaulo uint64_t hw_tkip_mic_rx_key; 5627286441Srpaulo uint64_t hw_tkip_mic_tx_key; 5628286441Srpaulo} __packed; 5629286441Srpaulo 5630303628Ssbruno#define IWM_ADD_STA_STATUS_MASK 0xFF 5631303628Ssbruno#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5632303628Ssbruno#define IWM_ADD_STA_BAID_MASK 0x7F00 5633303628Ssbruno#define IWM_ADD_STA_BAID_SHIFT 8 5634303628Ssbruno 5635286441Srpaulo/** 5636330195Seadler * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5637303628Ssbruno * ( REPLY_ADD_STA = 0x18 ) 5638286441Srpaulo * @add_modify: 1: modify existing, 0: add new station 5639303628Ssbruno * @awake_acs: 5640303628Ssbruno * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5641303628Ssbruno * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5642286441Srpaulo * @mac_id_n_color: the Mac context this station belongs to 5643286441Srpaulo * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5644286441Srpaulo * @sta_id: index of station in uCode's station table 5645286441Srpaulo * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5646286441Srpaulo * alone. 1 - modify, 0 - don't change. 5647286441Srpaulo * @station_flags: look at %iwm_sta_flags 5648286441Srpaulo * @station_flags_msk: what of %station_flags have changed 5649286441Srpaulo * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5650286441Srpaulo * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5651286441Srpaulo * add_immediate_ba_ssn. 5652286441Srpaulo * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5653286441Srpaulo * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5654286441Srpaulo * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5655286441Srpaulo * add_immediate_ba_tid. 5656286441Srpaulo * @sleep_tx_count: number of packets to transmit to station even though it is 5657286441Srpaulo * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5658286441Srpaulo * keeps track of STA sleep state. 5659286441Srpaulo * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5660286441Srpaulo * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5661286441Srpaulo * mac-addr. 5662286441Srpaulo * @beamform_flags: beam forming controls 5663286441Srpaulo * @tfd_queue_msk: tfd queues used by this station 5664286441Srpaulo * 5665286441Srpaulo * The device contains an internal table of per-station information, with info 5666286441Srpaulo * on security keys, aggregation parameters, and Tx rates for initial Tx 5667286441Srpaulo * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5668286441Srpaulo * 5669286441Srpaulo * ADD_STA sets up the table entry for one station, either creating a new 5670286441Srpaulo * entry, or modifying a pre-existing one. 5671286441Srpaulo */ 5672330195Seadlerstruct iwm_mvm_add_sta_cmd { 5673286441Srpaulo uint8_t add_modify; 5674303628Ssbruno uint8_t awake_acs; 5675286441Srpaulo uint16_t tid_disable_tx; 5676286441Srpaulo uint32_t mac_id_n_color; 5677286441Srpaulo uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5678286441Srpaulo uint16_t reserved2; 5679286441Srpaulo uint8_t sta_id; 5680286441Srpaulo uint8_t modify_mask; 5681286441Srpaulo uint16_t reserved3; 5682286441Srpaulo uint32_t station_flags; 5683286441Srpaulo uint32_t station_flags_msk; 5684286441Srpaulo uint8_t add_immediate_ba_tid; 5685286441Srpaulo uint8_t remove_immediate_ba_tid; 5686286441Srpaulo uint16_t add_immediate_ba_ssn; 5687286441Srpaulo uint16_t sleep_tx_count; 5688286441Srpaulo uint16_t sleep_state_flags; 5689286441Srpaulo uint16_t assoc_id; 5690286441Srpaulo uint16_t beamform_flags; 5691286441Srpaulo uint32_t tfd_queue_msk; 5692303628Ssbruno} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5693286441Srpaulo 5694286441Srpaulo/** 5695286441Srpaulo * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5696286441Srpaulo * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5697286441Srpaulo * @sta_id: index of station in uCode's station table 5698286441Srpaulo * @key_offset: key offset in key storage 5699286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5700286441Srpaulo * @key: key material data 5701286441Srpaulo * @key2: key material data 5702286441Srpaulo * @rx_secur_seq_cnt: RX security sequence counter for the key 5703286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5704286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5705286441Srpaulo */ 5706286441Srpaulostruct iwm_mvm_add_sta_key_cmd { 5707286441Srpaulo uint8_t sta_id; 5708286441Srpaulo uint8_t key_offset; 5709286441Srpaulo uint16_t key_flags; 5710286441Srpaulo uint8_t key[16]; 5711286441Srpaulo uint8_t key2[16]; 5712286441Srpaulo uint8_t rx_secur_seq_cnt[16]; 5713286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5714286441Srpaulo uint8_t reserved; 5715286441Srpaulo uint16_t tkip_rx_ttak[5]; 5716286441Srpaulo} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5717286441Srpaulo 5718286441Srpaulo/** 5719286441Srpaulo * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5720286441Srpaulo * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5721286441Srpaulo * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5722286441Srpaulo * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5723286441Srpaulo * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5724286441Srpaulo * that doesn't exist. 5725286441Srpaulo */ 5726286441Srpauloenum iwm_mvm_add_sta_rsp_status { 5727286441Srpaulo IWM_ADD_STA_SUCCESS = 0x1, 5728286441Srpaulo IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5729286441Srpaulo IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5730286441Srpaulo IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5731286441Srpaulo}; 5732286441Srpaulo 5733286441Srpaulo/** 5734286441Srpaulo * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5735286441Srpaulo * ( IWM_REMOVE_STA = 0x19 ) 5736286441Srpaulo * @sta_id: the station id of the station to be removed 5737286441Srpaulo */ 5738286441Srpaulostruct iwm_mvm_rm_sta_cmd { 5739286441Srpaulo uint8_t sta_id; 5740286441Srpaulo uint8_t reserved[3]; 5741286441Srpaulo} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5742286441Srpaulo 5743286441Srpaulo/** 5744286441Srpaulo * struct iwm_mvm_mgmt_mcast_key_cmd 5745286441Srpaulo * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5746286441Srpaulo * @ctrl_flags: %iwm_sta_key_flag 5747286441Srpaulo * @IGTK: 5748286441Srpaulo * @K1: IGTK master key 5749286441Srpaulo * @K2: IGTK sub key 5750286441Srpaulo * @sta_id: station ID that support IGTK 5751286441Srpaulo * @key_id: 5752286441Srpaulo * @receive_seq_cnt: initial RSC/PN needed for replay check 5753286441Srpaulo */ 5754286441Srpaulostruct iwm_mvm_mgmt_mcast_key_cmd { 5755286441Srpaulo uint32_t ctrl_flags; 5756286441Srpaulo uint8_t IGTK[16]; 5757286441Srpaulo uint8_t K1[16]; 5758286441Srpaulo uint8_t K2[16]; 5759286441Srpaulo uint32_t key_id; 5760286441Srpaulo uint32_t sta_id; 5761286441Srpaulo uint64_t receive_seq_cnt; 5762286441Srpaulo} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5763286441Srpaulo 5764286441Srpaulostruct iwm_mvm_wep_key { 5765286441Srpaulo uint8_t key_index; 5766286441Srpaulo uint8_t key_offset; 5767286441Srpaulo uint16_t reserved1; 5768286441Srpaulo uint8_t key_size; 5769286441Srpaulo uint8_t reserved2[3]; 5770286441Srpaulo uint8_t key[16]; 5771286441Srpaulo} __packed; 5772286441Srpaulo 5773286441Srpaulostruct iwm_mvm_wep_key_cmd { 5774286441Srpaulo uint32_t mac_id_n_color; 5775286441Srpaulo uint8_t num_keys; 5776286441Srpaulo uint8_t decryption_type; 5777286441Srpaulo uint8_t flags; 5778286441Srpaulo uint8_t reserved; 5779286441Srpaulo struct iwm_mvm_wep_key wep_key[0]; 5780286441Srpaulo} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5781286441Srpaulo 5782286441Srpaulo/* 5783286441Srpaulo * END mvm/fw-api-sta.h 5784286441Srpaulo */ 5785286441Srpaulo 5786286441Srpaulo/* 5787303628Ssbruno * BT coex 5788303628Ssbruno */ 5789303628Ssbruno 5790303628Ssbrunoenum iwm_bt_coex_mode { 5791303628Ssbruno IWM_BT_COEX_DISABLE = 0x0, 5792303628Ssbruno IWM_BT_COEX_NW = 0x1, 5793303628Ssbruno IWM_BT_COEX_BT = 0x2, 5794303628Ssbruno IWM_BT_COEX_WIFI = 0x3, 5795303628Ssbruno}; /* BT_COEX_MODES_E */ 5796303628Ssbruno 5797303628Ssbrunoenum iwm_bt_coex_enabled_modules { 5798303628Ssbruno IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5799303628Ssbruno IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5800303628Ssbruno IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5801303628Ssbruno IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5802303628Ssbruno IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5803303628Ssbruno}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5804303628Ssbruno 5805303628Ssbruno/** 5806303628Ssbruno * struct iwm_bt_coex_cmd - bt coex configuration command 5807303628Ssbruno * @mode: enum %iwm_bt_coex_mode 5808303628Ssbruno * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5809303628Ssbruno * 5810303628Ssbruno * The structure is used for the BT_COEX command. 5811303628Ssbruno */ 5812303628Ssbrunostruct iwm_bt_coex_cmd { 5813303628Ssbruno uint32_t mode; 5814303628Ssbruno uint32_t enabled_modules; 5815303628Ssbruno} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5816303628Ssbruno 5817303628Ssbruno 5818303628Ssbruno/* 5819303628Ssbruno * Location Aware Regulatory (LAR) API - MCC updates 5820303628Ssbruno */ 5821303628Ssbruno 5822303628Ssbruno/** 5823303628Ssbruno * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5824303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 5825303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5826303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5827303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 5828303628Ssbruno * @mcc: given mobile country code 5829303628Ssbruno * @source_id: the source from where we got the MCC, see iwm_mcc_source 5830303628Ssbruno * @reserved: reserved for alignment 5831303628Ssbruno */ 5832303628Ssbrunostruct iwm_mcc_update_cmd_v1 { 5833303628Ssbruno uint16_t mcc; 5834303628Ssbruno uint8_t source_id; 5835303628Ssbruno uint8_t reserved; 5836303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5837303628Ssbruno 5838303628Ssbruno/** 5839303628Ssbruno * struct iwm_mcc_update_cmd - Request the device to update geographic 5840303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 5841303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5842303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5843303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 5844303628Ssbruno * @mcc: given mobile country code 5845303628Ssbruno * @source_id: the source from where we got the MCC, see iwm_mcc_source 5846303628Ssbruno * @reserved: reserved for alignment 5847303628Ssbruno * @key: integrity key for MCC API OEM testing 5848303628Ssbruno * @reserved2: reserved 5849303628Ssbruno */ 5850303628Ssbrunostruct iwm_mcc_update_cmd { 5851303628Ssbruno uint16_t mcc; 5852303628Ssbruno uint8_t source_id; 5853303628Ssbruno uint8_t reserved; 5854303628Ssbruno uint32_t key; 5855303628Ssbruno uint32_t reserved2[5]; 5856303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5857303628Ssbruno 5858303628Ssbruno/** 5859303628Ssbruno * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5860303628Ssbruno * Contains the new channel control profile map, if changed, and the new MCC 5861303628Ssbruno * (mobile country code). 5862303628Ssbruno * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5863303628Ssbruno * @status: see &enum iwm_mcc_update_status 5864303628Ssbruno * @mcc: the new applied MCC 5865303628Ssbruno * @cap: capabilities for all channels which matches the MCC 5866303628Ssbruno * @source_id: the MCC source, see iwm_mcc_source 5867303628Ssbruno * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5868303628Ssbruno * channels, depending on platform) 5869303628Ssbruno * @channels: channel control data map, DWORD for each channel. Only the first 5870303628Ssbruno * 16bits are used. 5871303628Ssbruno */ 5872303628Ssbrunostruct iwm_mcc_update_resp_v1 { 5873303628Ssbruno uint32_t status; 5874303628Ssbruno uint16_t mcc; 5875303628Ssbruno uint8_t cap; 5876303628Ssbruno uint8_t source_id; 5877303628Ssbruno uint32_t n_channels; 5878303628Ssbruno uint32_t channels[0]; 5879303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5880303628Ssbruno 5881303628Ssbruno/** 5882303628Ssbruno * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5883303628Ssbruno * Contains the new channel control profile map, if changed, and the new MCC 5884303628Ssbruno * (mobile country code). 5885303628Ssbruno * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5886303628Ssbruno * @status: see &enum iwm_mcc_update_status 5887303628Ssbruno * @mcc: the new applied MCC 5888303628Ssbruno * @cap: capabilities for all channels which matches the MCC 5889303628Ssbruno * @source_id: the MCC source, see iwm_mcc_source 5890303628Ssbruno * @time: time elapsed from the MCC test start (in 30 seconds TU) 5891303628Ssbruno * @reserved: reserved. 5892303628Ssbruno * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5893303628Ssbruno * channels, depending on platform) 5894303628Ssbruno * @channels: channel control data map, DWORD for each channel. Only the first 5895303628Ssbruno * 16bits are used. 5896303628Ssbruno */ 5897303628Ssbrunostruct iwm_mcc_update_resp { 5898303628Ssbruno uint32_t status; 5899303628Ssbruno uint16_t mcc; 5900303628Ssbruno uint8_t cap; 5901303628Ssbruno uint8_t source_id; 5902303628Ssbruno uint16_t time; 5903303628Ssbruno uint16_t reserved; 5904303628Ssbruno uint32_t n_channels; 5905303628Ssbruno uint32_t channels[0]; 5906303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5907303628Ssbruno 5908303628Ssbruno/** 5909303628Ssbruno * struct iwm_mcc_chub_notif - chub notifies of mcc change 5910303628Ssbruno * (MCC_CHUB_UPDATE_CMD = 0xc9) 5911303628Ssbruno * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5912303628Ssbruno * the cellular and connectivity cores that gets updates of the mcc, and 5913303628Ssbruno * notifies the ucode directly of any mcc change. 5914303628Ssbruno * The ucode requests the driver to request the device to update geographic 5915303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 5916303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5917303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5918303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 5919303628Ssbruno * @mcc: given mobile country code 5920303628Ssbruno * @source_id: identity of the change originator, see iwm_mcc_source 5921303628Ssbruno * @reserved1: reserved for alignment 5922303628Ssbruno */ 5923303628Ssbrunostruct iwm_mcc_chub_notif { 5924303628Ssbruno uint16_t mcc; 5925303628Ssbruno uint8_t source_id; 5926303628Ssbruno uint8_t reserved1; 5927303628Ssbruno} __packed; /* LAR_MCC_NOTIFY_S */ 5928303628Ssbruno 5929303628Ssbrunoenum iwm_mcc_update_status { 5930303628Ssbruno IWM_MCC_RESP_NEW_CHAN_PROFILE, 5931303628Ssbruno IWM_MCC_RESP_SAME_CHAN_PROFILE, 5932303628Ssbruno IWM_MCC_RESP_INVALID, 5933303628Ssbruno IWM_MCC_RESP_NVM_DISABLED, 5934303628Ssbruno IWM_MCC_RESP_ILLEGAL, 5935303628Ssbruno IWM_MCC_RESP_LOW_PRIORITY, 5936303628Ssbruno IWM_MCC_RESP_TEST_MODE_ACTIVE, 5937303628Ssbruno IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5938303628Ssbruno IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5939303628Ssbruno}; 5940303628Ssbruno 5941303628Ssbrunoenum iwm_mcc_source { 5942303628Ssbruno IWM_MCC_SOURCE_OLD_FW = 0, 5943303628Ssbruno IWM_MCC_SOURCE_ME = 1, 5944303628Ssbruno IWM_MCC_SOURCE_BIOS = 2, 5945303628Ssbruno IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5946303628Ssbruno IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5947303628Ssbruno IWM_MCC_SOURCE_WIFI = 5, 5948303628Ssbruno IWM_MCC_SOURCE_RESERVED = 6, 5949303628Ssbruno IWM_MCC_SOURCE_DEFAULT = 7, 5950303628Ssbruno IWM_MCC_SOURCE_UNINITIALIZED = 8, 5951303628Ssbruno IWM_MCC_SOURCE_MCC_API = 9, 5952303628Ssbruno IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5953303628Ssbruno IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5954303628Ssbruno}; 5955303628Ssbruno 5956330177Seadler/** 5957330177Seadler * struct iwm_dts_measurement_notif_v1 - measurements notification 5958330177Seadler * 5959330177Seadler * @temp: the measured temperature 5960330177Seadler * @voltage: the measured voltage 5961330177Seadler */ 5962330177Seadlerstruct iwm_dts_measurement_notif_v1 { 5963330177Seadler int32_t temp; 5964330177Seadler int32_t voltage; 5965330177Seadler} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5966330177Seadler 5967330177Seadler/** 5968330177Seadler * struct iwm_dts_measurement_notif_v2 - measurements notification 5969330177Seadler * 5970330177Seadler * @temp: the measured temperature 5971330177Seadler * @voltage: the measured voltage 5972330177Seadler * @threshold_idx: the trip index that was crossed 5973330177Seadler */ 5974330177Seadlerstruct iwm_dts_measurement_notif_v2 { 5975330177Seadler int32_t temp; 5976330177Seadler int32_t voltage; 5977330177Seadler int32_t threshold_idx; 5978330177Seadler} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5979330177Seadler 5980303628Ssbruno/* 5981286441Srpaulo * Some cherry-picked definitions 5982286441Srpaulo */ 5983286441Srpaulo 5984286441Srpaulo#define IWM_FRAME_LIMIT 64 5985286441Srpaulo 5986303628Ssbruno/* 5987303628Ssbruno * These functions retrieve specific information from the id field in 5988303628Ssbruno * the iwm_host_cmd struct which contains the command id, the group id, 5989330208Seadler * and the version of the command and vice versa. 5990303628Ssbruno*/ 5991303628Ssbrunostatic inline uint8_t 5992303628Ssbrunoiwm_cmd_opcode(uint32_t cmdid) 5993303628Ssbruno{ 5994303628Ssbruno return cmdid & 0xff; 5995303628Ssbruno} 5996303628Ssbruno 5997303628Ssbrunostatic inline uint8_t 5998303628Ssbrunoiwm_cmd_groupid(uint32_t cmdid) 5999303628Ssbruno{ 6000330208Seadler return ((cmdid & 0xff00) >> 8); 6001303628Ssbruno} 6002303628Ssbruno 6003303628Ssbrunostatic inline uint8_t 6004303628Ssbrunoiwm_cmd_version(uint32_t cmdid) 6005303628Ssbruno{ 6006303628Ssbruno return ((cmdid & 0xff0000) >> 16); 6007303628Ssbruno} 6008303628Ssbruno 6009303628Ssbrunostatic inline uint32_t 6010303628Ssbrunoiwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6011303628Ssbruno{ 6012303628Ssbruno return opcode + (groupid << 8) + (version << 16); 6013303628Ssbruno} 6014303628Ssbruno 6015303628Ssbruno/* make uint16_t wide id out of uint8_t group and opcode */ 6016303628Ssbruno#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6017303628Ssbruno 6018303628Ssbruno/* due to the conversion, this group is special */ 6019303628Ssbruno#define IWM_ALWAYS_LONG_GROUP 1 6020303628Ssbruno 6021286441Srpaulostruct iwm_cmd_header { 6022286441Srpaulo uint8_t code; 6023286441Srpaulo uint8_t flags; 6024286441Srpaulo uint8_t idx; 6025286441Srpaulo uint8_t qid; 6026286441Srpaulo} __packed; 6027286441Srpaulo 6028303628Ssbrunostruct iwm_cmd_header_wide { 6029303628Ssbruno uint8_t opcode; 6030303628Ssbruno uint8_t group_id; 6031303628Ssbruno uint8_t idx; 6032303628Ssbruno uint8_t qid; 6033303628Ssbruno uint16_t length; 6034303628Ssbruno uint8_t reserved; 6035303628Ssbruno uint8_t version; 6036303628Ssbruno} __packed; 6037303628Ssbruno 6038330201Seadler/** 6039330201Seadler * enum iwm_power_scheme 6040330201Seadler * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6041330201Seadler * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6042330201Seadler * @IWM_POWER_LEVEL_LP - Low Power 6043330201Seadler */ 6044286441Srpauloenum iwm_power_scheme { 6045286441Srpaulo IWM_POWER_SCHEME_CAM = 1, 6046286441Srpaulo IWM_POWER_SCHEME_BPS, 6047286441Srpaulo IWM_POWER_SCHEME_LP 6048286441Srpaulo}; 6049286441Srpaulo 6050286441Srpaulo#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6051301189Sadrian#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6052286441Srpaulo#define IWM_CMD_FAILED_MSK 0x40 6053286441Srpaulo 6054303628Ssbruno/** 6055303628Ssbruno * struct iwm_device_cmd 6056303628Ssbruno * 6057303628Ssbruno * For allocation of the command and tx queues, this establishes the overall 6058303628Ssbruno * size of the largest command we send to uCode, except for commands that 6059303628Ssbruno * aren't fully copied and use other TFD space. 6060303628Ssbruno */ 6061286441Srpaulostruct iwm_device_cmd { 6062303628Ssbruno union { 6063303628Ssbruno struct { 6064303628Ssbruno struct iwm_cmd_header hdr; 6065303628Ssbruno uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6066303628Ssbruno }; 6067303628Ssbruno struct { 6068303628Ssbruno struct iwm_cmd_header_wide hdr_wide; 6069303628Ssbruno uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6070303628Ssbruno sizeof(struct iwm_cmd_header_wide) + 6071303628Ssbruno sizeof(struct iwm_cmd_header)]; 6072303628Ssbruno }; 6073303628Ssbruno }; 6074286441Srpaulo} __packed; 6075286441Srpaulo 6076286441Srpaulostruct iwm_rx_packet { 6077286441Srpaulo /* 6078286441Srpaulo * The first 4 bytes of the RX frame header contain both the RX frame 6079286441Srpaulo * size and some flags. 6080286441Srpaulo * Bit fields: 6081286441Srpaulo * 31: flag flush RB request 6082286441Srpaulo * 30: flag ignore TC (terminal counter) request 6083286441Srpaulo * 29: flag fast IRQ request 6084286441Srpaulo * 28-14: Reserved 6085286441Srpaulo * 13-00: RX frame size 6086286441Srpaulo */ 6087286441Srpaulo uint32_t len_n_flags; 6088286441Srpaulo struct iwm_cmd_header hdr; 6089286441Srpaulo uint8_t data[]; 6090286441Srpaulo} __packed; 6091286441Srpaulo 6092286441Srpaulo#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6093330208Seadler#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6094330208Seadler#define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6095286441Srpaulo 6096286441Srpaulostatic inline uint32_t 6097286441Srpauloiwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6098286441Srpaulo{ 6099286441Srpaulo 6100286441Srpaulo return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6101286441Srpaulo} 6102286441Srpaulo 6103286441Srpaulostatic inline uint32_t 6104286441Srpauloiwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6105286441Srpaulo{ 6106286441Srpaulo 6107286441Srpaulo return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6108286441Srpaulo} 6109286441Srpaulo 6110286441Srpaulo 6111286441Srpaulo#define IWM_MIN_DBM -100 6112286441Srpaulo#define IWM_MAX_DBM -33 /* realistic guess */ 6113286441Srpaulo 6114286441Srpaulo#define IWM_READ(sc, reg) \ 6115286441Srpaulo bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6116286441Srpaulo 6117286441Srpaulo#define IWM_WRITE(sc, reg, val) \ 6118286441Srpaulo bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6119286441Srpaulo 6120286441Srpaulo#define IWM_WRITE_1(sc, reg, val) \ 6121286441Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6122286441Srpaulo 6123286441Srpaulo#define IWM_SETBITS(sc, reg, mask) \ 6124286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6125286441Srpaulo 6126286441Srpaulo#define IWM_CLRBITS(sc, reg, mask) \ 6127286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6128286441Srpaulo 6129286441Srpaulo#define IWM_BARRIER_WRITE(sc) \ 6130286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6131286441Srpaulo BUS_SPACE_BARRIER_WRITE) 6132286441Srpaulo 6133286441Srpaulo#define IWM_BARRIER_READ_WRITE(sc) \ 6134286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6135286441Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6136286441Srpaulo 6137286441Srpaulo#endif /* __IF_IWM_REG_H__ */ 6138