if_ipw.c revision 156687
1/* $FreeBSD: head/sys/dev/ipw/if_ipw.c 156687 2006-03-13 20:05:32Z damien $ */ 2 3/*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ipw/if_ipw.c 156687 2006-03-13 20:05:32Z damien $"); 32 33/*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38#include <sys/param.h> 39#include <sys/sysctl.h> 40#include <sys/sockio.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/systm.h> 45#include <sys/malloc.h> 46#include <sys/queue.h> 47#include <sys/taskqueue.h> 48#include <sys/module.h> 49#include <sys/bus.h> 50#include <sys/endian.h> 51#include <sys/linker.h> 52#include <sys/firmware.h> 53 54#include <machine/bus.h> 55#include <machine/resource.h> 56#include <machine/clock.h> 57#include <sys/rman.h> 58 59#include <dev/pci/pcireg.h> 60#include <dev/pci/pcivar.h> 61 62#include <net/bpf.h> 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68#include <net/if_types.h> 69 70#include <net80211/ieee80211_var.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#include <netinet/in.h> 74#include <netinet/in_systm.h> 75#include <netinet/in_var.h> 76#include <netinet/ip.h> 77#include <netinet/if_ether.h> 78 79#include <dev/ipw/if_ipwreg.h> 80#include <dev/ipw/if_ipwvar.h> 81 82#ifdef IPW_DEBUG 83#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 84#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 85int ipw_debug = 0; 86SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 87#else 88#define DPRINTF(x) 89#define DPRINTFN(n, x) 90#endif 91 92MODULE_DEPEND(ipw, pci, 1, 1, 1); 93MODULE_DEPEND(ipw, wlan, 1, 1, 1); 94MODULE_DEPEND(ipw, firmware, 1, 1, 1); 95 96struct ipw_ident { 97 uint16_t vendor; 98 uint16_t device; 99 const char *name; 100}; 101 102static const struct ipw_ident ipw_ident_table[] = { 103 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 104 105 { 0, 0, NULL } 106}; 107 108static int ipw_dma_alloc(struct ipw_softc *); 109static void ipw_release(struct ipw_softc *); 110static int ipw_media_change(struct ifnet *); 111static void ipw_media_status(struct ifnet *, struct ifmediareq *); 112static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 113static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 114static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 115static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 116static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 117 struct ipw_soft_bd *, struct ipw_soft_buf *); 118static void ipw_rx_intr(struct ipw_softc *); 119static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 120static void ipw_tx_intr(struct ipw_softc *); 121static void ipw_intr(void *); 122static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 123static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 124static int ipw_tx_start(struct ifnet *, struct mbuf *, 125 struct ieee80211_node *); 126static void ipw_start(struct ifnet *); 127static void ipw_watchdog(struct ifnet *); 128static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 129static void ipw_stop_master(struct ipw_softc *); 130static int ipw_reset(struct ipw_softc *); 131static int ipw_load_ucode(struct ipw_softc *, const char *, int); 132static int ipw_load_firmware(struct ipw_softc *, const char *, int); 133static int ipw_config(struct ipw_softc *); 134static void ipw_init_task(void *, int); 135static void ipw_init(void *); 136static void ipw_stop(void *); 137static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 138static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 139static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 140static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 141static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 142 uint32_t *); 143static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 144 bus_size_t); 145static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, 146 const uint8_t *, bus_size_t); 147 148static int ipw_probe(device_t); 149static int ipw_attach(device_t); 150static int ipw_detach(device_t); 151static int ipw_shutdown(device_t); 152static int ipw_suspend(device_t); 153static int ipw_resume(device_t); 154 155static device_method_t ipw_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, ipw_probe), 158 DEVMETHOD(device_attach, ipw_attach), 159 DEVMETHOD(device_detach, ipw_detach), 160 DEVMETHOD(device_shutdown, ipw_shutdown), 161 DEVMETHOD(device_suspend, ipw_suspend), 162 DEVMETHOD(device_resume, ipw_resume), 163 164 { 0, 0 } 165}; 166 167static driver_t ipw_driver = { 168 "ipw", 169 ipw_methods, 170 sizeof (struct ipw_softc) 171}; 172 173static devclass_t ipw_devclass; 174 175DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 176 177/* 178 * Supported rates for 802.11b mode (in 500Kbps unit). 179 */ 180static const struct ieee80211_rateset ipw_rateset_11b = 181 { 4, { 2, 4, 11, 22 } }; 182 183static int 184ipw_probe(device_t dev) 185{ 186 const struct ipw_ident *ident; 187 188 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 189 if (pci_get_vendor(dev) == ident->vendor && 190 pci_get_device(dev) == ident->device) { 191 device_set_desc(dev, ident->name); 192 return 0; 193 } 194 } 195 return ENXIO; 196} 197 198/* Base Address Register */ 199#define IPW_PCI_BAR0 0x10 200 201static int 202ipw_attach(device_t dev) 203{ 204 struct ipw_softc *sc = device_get_softc(dev); 205 struct ifnet *ifp; 206 struct ieee80211com *ic = &sc->sc_ic; 207 uint16_t val; 208 int error, i; 209 210 sc->sc_dev = dev; 211 212 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 213 MTX_DEF | MTX_RECURSE); 214 215 TASK_INIT(&sc->sc_init_task, 0, ipw_init_task, sc); 216 217 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 218 device_printf(dev, "chip is in D%d power mode " 219 "-- setting to D0\n", pci_get_powerstate(dev)); 220 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 221 } 222 223 pci_write_config(dev, 0x41, 0, 1); 224 225 /* enable bus-mastering */ 226 pci_enable_busmaster(dev); 227 228 sc->mem_rid = IPW_PCI_BAR0; 229 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 230 RF_ACTIVE); 231 if (sc->mem == NULL) { 232 device_printf(dev, "could not allocate memory resource\n"); 233 goto fail; 234 } 235 236 sc->sc_st = rman_get_bustag(sc->mem); 237 sc->sc_sh = rman_get_bushandle(sc->mem); 238 239 sc->irq_rid = 0; 240 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 241 RF_ACTIVE | RF_SHAREABLE); 242 if (sc->irq == NULL) { 243 device_printf(dev, "could not allocate interrupt resource\n"); 244 goto fail; 245 } 246 247 if (ipw_reset(sc) != 0) { 248 device_printf(dev, "could not reset adapter\n"); 249 goto fail; 250 } 251 252 if (ipw_dma_alloc(sc) != 0) { 253 device_printf(dev, "could not allocate DMA resources\n"); 254 goto fail; 255 } 256 257 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 258 if (ifp == NULL) { 259 device_printf(dev, "can not if_alloc()\n"); 260 goto fail; 261 } 262 263 ifp->if_softc = sc; 264 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_init = ipw_init; 267 ifp->if_ioctl = ipw_ioctl; 268 ifp->if_start = ipw_start; 269 ifp->if_watchdog = ipw_watchdog; 270 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 271 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 272 IFQ_SET_READY(&ifp->if_snd); 273 274 ic->ic_ifp = ifp; 275 ic->ic_phytype = IEEE80211_T_DS; 276 ic->ic_opmode = IEEE80211_M_STA; 277 ic->ic_state = IEEE80211_S_INIT; 278 279 /* set device capabilities */ 280 ic->ic_caps = 281 IEEE80211_C_IBSS | /* IBSS mode supported */ 282 IEEE80211_C_MONITOR | /* monitor mode supported */ 283 IEEE80211_C_TXPMGT | /* tx power management */ 284 IEEE80211_C_SHPREAMBLE; /* short preamble supported */ 285 286 /* read MAC address from EEPROM */ 287 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 288 ic->ic_myaddr[0] = val >> 8; 289 ic->ic_myaddr[1] = val & 0xff; 290 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 291 ic->ic_myaddr[2] = val >> 8; 292 ic->ic_myaddr[3] = val & 0xff; 293 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 294 ic->ic_myaddr[4] = val >> 8; 295 ic->ic_myaddr[5] = val & 0xff; 296 297 /* set supported .11b rates */ 298 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 299 300 /* set supported .11b channels */ 301 for (i = 1; i < 14; i++) { 302 ic->ic_channels[i].ic_freq = 303 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 304 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 305 } 306 307 /* check support for radio transmitter switch in EEPROM */ 308 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 309 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 310 311 ieee80211_ifattach(ic); 312 /* override state transition machine */ 313 sc->sc_newstate = ic->ic_newstate; 314 ic->ic_newstate = ipw_newstate; 315 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 316 317 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 318 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 319 320 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 321 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 322 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 323 324 sc->sc_txtap_len = sizeof sc->sc_txtapu; 325 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 326 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 327 328 /* 329 * Add a few sysctl knobs. 330 */ 331 sc->dwelltime = 100; 332 333 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 334 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 335 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 336 "radio transmitter switch state (0=off, 1=on)"); 337 338 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 339 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 340 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 341 "statistics"); 342 343 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 344 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 345 CTLFLAG_RW, &sc->dwelltime, 0, 346 "channel dwell time (ms) for AP/station scanning"); 347 348 /* 349 * Hook our interrupt after all initialization is complete. 350 */ 351 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 352 ipw_intr, sc, &sc->sc_ih); 353 if (error != 0) { 354 device_printf(dev, "could not set up interrupt\n"); 355 goto fail; 356 } 357 358 if (bootverbose) 359 ieee80211_announce(ic); 360 361 return 0; 362 363fail: ipw_detach(dev); 364 return ENXIO; 365} 366 367static int 368ipw_detach(device_t dev) 369{ 370 struct ipw_softc *sc = device_get_softc(dev); 371 struct ieee80211com *ic = &sc->sc_ic; 372 struct ifnet *ifp = ic->ic_ifp; 373 374 ipw_stop(sc); 375 376 if (ifp != NULL) { 377 bpfdetach(ifp); 378 ieee80211_ifdetach(ic); 379 } 380 381 ipw_release(sc); 382 383 if (sc->irq != NULL) { 384 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 385 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 386 } 387 388 if (sc->mem != NULL) 389 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 390 391 if (ifp != NULL) 392 if_free(ifp); 393 394 mtx_destroy(&sc->sc_mtx); 395 396 return 0; 397} 398 399static int 400ipw_dma_alloc(struct ipw_softc *sc) 401{ 402 struct ipw_soft_bd *sbd; 403 struct ipw_soft_hdr *shdr; 404 struct ipw_soft_buf *sbuf; 405 bus_addr_t physaddr; 406 int error, i; 407 408 /* 409 * Allocate and map tx ring. 410 */ 411 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 412 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 413 NULL, &sc->tbd_dmat); 414 if (error != 0) { 415 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 416 goto fail; 417 } 418 419 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 420 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 421 if (error != 0) { 422 device_printf(sc->sc_dev, 423 "could not allocate tx ring DMA memory\n"); 424 goto fail; 425 } 426 427 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 428 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 429 if (error != 0) { 430 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 431 goto fail; 432 } 433 434 /* 435 * Allocate and map rx ring. 436 */ 437 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 438 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 439 NULL, &sc->rbd_dmat); 440 if (error != 0) { 441 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 442 goto fail; 443 } 444 445 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 446 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 447 if (error != 0) { 448 device_printf(sc->sc_dev, 449 "could not allocate rx ring DMA memory\n"); 450 goto fail; 451 } 452 453 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 454 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 455 if (error != 0) { 456 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 457 goto fail; 458 } 459 460 /* 461 * Allocate and map status ring. 462 */ 463 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 464 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 465 NULL, NULL, &sc->status_dmat); 466 if (error != 0) { 467 device_printf(sc->sc_dev, 468 "could not create status ring DMA tag\n"); 469 goto fail; 470 } 471 472 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 473 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 474 if (error != 0) { 475 device_printf(sc->sc_dev, 476 "could not allocate status ring DMA memory\n"); 477 goto fail; 478 } 479 480 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 481 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 482 0); 483 if (error != 0) { 484 device_printf(sc->sc_dev, 485 "could not map status ring DMA memory\n"); 486 goto fail; 487 } 488 489 /* 490 * Allocate command DMA map. 491 */ 492 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 493 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 494 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 495 if (error != 0) { 496 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 497 goto fail; 498 } 499 500 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 501 if (error != 0) { 502 device_printf(sc->sc_dev, 503 "could not create command DMA map\n"); 504 goto fail; 505 } 506 507 /* 508 * Allocate headers DMA maps. 509 */ 510 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 511 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 512 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 513 if (error != 0) { 514 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 515 goto fail; 516 } 517 518 SLIST_INIT(&sc->free_shdr); 519 for (i = 0; i < IPW_NDATA; i++) { 520 shdr = &sc->shdr_list[i]; 521 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 522 if (error != 0) { 523 device_printf(sc->sc_dev, 524 "could not create header DMA map\n"); 525 goto fail; 526 } 527 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 528 } 529 530 /* 531 * Allocate tx buffers DMA maps. 532 */ 533 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 534 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 535 NULL, NULL, &sc->txbuf_dmat); 536 if (error != 0) { 537 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 538 goto fail; 539 } 540 541 SLIST_INIT(&sc->free_sbuf); 542 for (i = 0; i < IPW_NDATA; i++) { 543 sbuf = &sc->tx_sbuf_list[i]; 544 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 545 if (error != 0) { 546 device_printf(sc->sc_dev, 547 "could not create tx DMA map\n"); 548 goto fail; 549 } 550 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 551 } 552 553 /* 554 * Initialize tx ring. 555 */ 556 for (i = 0; i < IPW_NTBD; i++) { 557 sbd = &sc->stbd_list[i]; 558 sbd->bd = &sc->tbd_list[i]; 559 sbd->type = IPW_SBD_TYPE_NOASSOC; 560 } 561 562 /* 563 * Pre-allocate rx buffers and DMA maps. 564 */ 565 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 566 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 567 NULL, &sc->rxbuf_dmat); 568 if (error != 0) { 569 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 570 goto fail; 571 } 572 573 for (i = 0; i < IPW_NRBD; i++) { 574 sbd = &sc->srbd_list[i]; 575 sbuf = &sc->rx_sbuf_list[i]; 576 sbd->bd = &sc->rbd_list[i]; 577 578 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 579 if (sbuf->m == NULL) { 580 device_printf(sc->sc_dev, 581 "could not allocate rx mbuf\n"); 582 error = ENOMEM; 583 goto fail; 584 } 585 586 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 587 if (error != 0) { 588 device_printf(sc->sc_dev, 589 "could not create rx DMA map\n"); 590 goto fail; 591 } 592 593 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 594 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 595 &physaddr, 0); 596 if (error != 0) { 597 device_printf(sc->sc_dev, 598 "could not map rx DMA memory\n"); 599 goto fail; 600 } 601 602 sbd->type = IPW_SBD_TYPE_DATA; 603 sbd->priv = sbuf; 604 sbd->bd->physaddr = htole32(physaddr); 605 sbd->bd->len = htole32(MCLBYTES); 606 } 607 608 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 609 610 return 0; 611 612fail: ipw_release(sc); 613 return error; 614} 615 616static void 617ipw_release(struct ipw_softc *sc) 618{ 619 struct ipw_soft_buf *sbuf; 620 int i; 621 622 if (sc->tbd_dmat != NULL) { 623 if (sc->stbd_list != NULL) { 624 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 625 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 626 sc->tbd_map); 627 } 628 bus_dma_tag_destroy(sc->tbd_dmat); 629 } 630 631 if (sc->rbd_dmat != NULL) { 632 if (sc->rbd_list != NULL) { 633 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 634 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 635 sc->rbd_map); 636 } 637 bus_dma_tag_destroy(sc->rbd_dmat); 638 } 639 640 if (sc->status_dmat != NULL) { 641 if (sc->status_list != NULL) { 642 bus_dmamap_unload(sc->status_dmat, sc->status_map); 643 bus_dmamem_free(sc->status_dmat, sc->status_list, 644 sc->status_map); 645 } 646 bus_dma_tag_destroy(sc->status_dmat); 647 } 648 649 for (i = 0; i < IPW_NTBD; i++) 650 ipw_release_sbd(sc, &sc->stbd_list[i]); 651 652 if (sc->cmd_dmat != NULL) { 653 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 654 bus_dma_tag_destroy(sc->cmd_dmat); 655 } 656 657 if (sc->hdr_dmat != NULL) { 658 for (i = 0; i < IPW_NDATA; i++) 659 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 660 bus_dma_tag_destroy(sc->hdr_dmat); 661 } 662 663 if (sc->txbuf_dmat != NULL) { 664 for (i = 0; i < IPW_NDATA; i++) { 665 bus_dmamap_destroy(sc->txbuf_dmat, 666 sc->tx_sbuf_list[i].map); 667 } 668 bus_dma_tag_destroy(sc->txbuf_dmat); 669 } 670 671 if (sc->rxbuf_dmat != NULL) { 672 for (i = 0; i < IPW_NRBD; i++) { 673 sbuf = &sc->rx_sbuf_list[i]; 674 if (sbuf->m != NULL) { 675 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 676 BUS_DMASYNC_POSTREAD); 677 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 678 m_freem(sbuf->m); 679 } 680 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 681 } 682 bus_dma_tag_destroy(sc->rxbuf_dmat); 683 } 684} 685 686static int 687ipw_shutdown(device_t dev) 688{ 689 struct ipw_softc *sc = device_get_softc(dev); 690 691 ipw_stop(sc); 692 693 return 0; 694} 695 696static int 697ipw_suspend(device_t dev) 698{ 699 struct ipw_softc *sc = device_get_softc(dev); 700 701 ipw_stop(sc); 702 703 return 0; 704} 705 706static int 707ipw_resume(device_t dev) 708{ 709 struct ipw_softc *sc = device_get_softc(dev); 710 struct ifnet *ifp = sc->sc_ic.ic_ifp; 711 712 mtx_lock(&sc->sc_mtx); 713 714 pci_write_config(dev, 0x41, 0, 1); 715 716 if (ifp->if_flags & IFF_UP) { 717 ifp->if_init(ifp->if_softc); 718 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 719 ifp->if_start(ifp); 720 } 721 722 mtx_unlock(&sc->sc_mtx); 723 724 return 0; 725} 726 727static int 728ipw_media_change(struct ifnet *ifp) 729{ 730 struct ipw_softc *sc = ifp->if_softc; 731 int error; 732 733 mtx_lock(&sc->sc_mtx); 734 735 error = ieee80211_media_change(ifp); 736 if (error != ENETRESET) { 737 mtx_unlock(&sc->sc_mtx); 738 return error; 739 } 740 741 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 742 ipw_init(sc); 743 744 mtx_unlock(&sc->sc_mtx); 745 746 return 0; 747} 748 749/* 750 * The firmware automatically adapts the transmit speed. We report its current 751 * value here. 752 */ 753static void 754ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 755{ 756#define N(a) (sizeof (a) / sizeof (a[0])) 757 struct ipw_softc *sc = ifp->if_softc; 758 struct ieee80211com *ic = &sc->sc_ic; 759 static const struct { 760 uint32_t val; 761 int rate; 762 } rates[] = { 763 { IPW_RATE_DS1, 2 }, 764 { IPW_RATE_DS2, 4 }, 765 { IPW_RATE_DS5, 11 }, 766 { IPW_RATE_DS11, 22 }, 767 }; 768 uint32_t val; 769 int rate, i; 770 771 imr->ifm_status = IFM_AVALID; 772 imr->ifm_active = IFM_IEEE80211; 773 if (ic->ic_state == IEEE80211_S_RUN) 774 imr->ifm_status |= IFM_ACTIVE; 775 776 /* read current transmission rate from adapter */ 777 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 778 779 /* convert ipw rate to 802.11 rate */ 780 for (i = 0; i < N(rates) && rates[i].val != val; i++); 781 rate = (i < N(rates)) ? rates[i].rate : 0; 782 783 imr->ifm_active |= IFM_IEEE80211_11B; 784 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 785 switch (ic->ic_opmode) { 786 case IEEE80211_M_STA: 787 break; 788 789 case IEEE80211_M_IBSS: 790 imr->ifm_active |= IFM_IEEE80211_IBSS; 791 break; 792 793 case IEEE80211_M_MONITOR: 794 imr->ifm_active |= IFM_IEEE80211_MONITOR; 795 break; 796 797 case IEEE80211_M_AHDEMO: 798 case IEEE80211_M_HOSTAP: 799 /* should not get there */ 800 break; 801 } 802#undef N 803} 804 805static int 806ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 807{ 808 struct ifnet *ifp = ic->ic_ifp; 809 struct ipw_softc *sc = ifp->if_softc; 810 struct ieee80211_node *ni; 811 uint8_t macaddr[IEEE80211_ADDR_LEN]; 812 uint32_t len; 813 814 switch (nstate) { 815 case IEEE80211_S_RUN: 816 DELAY(200); /* firmware needs a short delay here */ 817 818 len = IEEE80211_ADDR_LEN; 819 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 820 821 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 822 if (ni == NULL) 823 break; 824 825 ieee80211_ref_node(ni); 826 ieee80211_sta_join(ic, ni); 827 ieee80211_node_authorize(ni); 828 829 if (ic->ic_opmode == IEEE80211_M_STA) 830 ieee80211_notify_node_join(ic, ni, 1); 831 break; 832 833 case IEEE80211_S_INIT: 834 case IEEE80211_S_SCAN: 835 case IEEE80211_S_AUTH: 836 case IEEE80211_S_ASSOC: 837 break; 838 } 839 840 ic->ic_state = nstate; 841 842 return 0; 843} 844 845/* 846 * Read 16 bits at address 'addr' from the serial EEPROM. 847 */ 848static uint16_t 849ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 850{ 851 uint32_t tmp; 852 uint16_t val; 853 int n; 854 855 /* clock C once before the first command */ 856 IPW_EEPROM_CTL(sc, 0); 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 859 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 860 861 /* write start bit (1) */ 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 864 865 /* write READ opcode (10) */ 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 870 871 /* write address A7-A0 */ 872 for (n = 7; n >= 0; n--) { 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 874 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 876 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 877 } 878 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 880 881 /* read data Q15-Q0 */ 882 val = 0; 883 for (n = 15; n >= 0; n--) { 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 886 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 887 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 888 } 889 890 IPW_EEPROM_CTL(sc, 0); 891 892 /* clear Chip Select and clock C */ 893 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 894 IPW_EEPROM_CTL(sc, 0); 895 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 896 897 return le16toh(val); 898} 899 900static void 901ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 902{ 903 struct ipw_cmd *cmd; 904 905 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 906 907 cmd = mtod(sbuf->m, struct ipw_cmd *); 908 909 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 910 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 911 le32toh(cmd->status))); 912 913 wakeup(sc); 914} 915 916static void 917ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 918{ 919 struct ieee80211com *ic = &sc->sc_ic; 920 uint32_t state; 921 922 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 923 924 state = le32toh(*mtod(sbuf->m, uint32_t *)); 925 926 DPRINTFN(2, ("entering state %u\n", state)); 927 928 switch (state) { 929 case IPW_STATE_ASSOCIATED: 930 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 931 break; 932 933 case IPW_STATE_SCANNING: 934 /* don't leave run state on background scan */ 935 if (ic->ic_state != IEEE80211_S_RUN) 936 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 937 938 ic->ic_flags |= IEEE80211_F_SCAN; 939 break; 940 941 case IPW_STATE_SCAN_COMPLETE: 942 ieee80211_notify_scan_done(ic); 943 ic->ic_flags &= ~IEEE80211_F_SCAN; 944 break; 945 946 case IPW_STATE_ASSOCIATION_LOST: 947 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 948 break; 949 950 case IPW_STATE_RADIO_DISABLED: 951 ic->ic_ifp->if_flags &= ~IFF_UP; 952 ipw_stop(sc); 953 break; 954 } 955} 956 957/* 958 * XXX: Hack to set the current channel to the value advertised in beacons or 959 * probe responses. Only used during AP detection. 960 */ 961static void 962ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 963{ 964 struct ieee80211_frame *wh; 965 uint8_t subtype; 966 uint8_t *frm, *efrm; 967 968 wh = mtod(m, struct ieee80211_frame *); 969 970 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 971 return; 972 973 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 974 975 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 976 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 977 return; 978 979 frm = (uint8_t *)(wh + 1); 980 efrm = mtod(m, uint8_t *) + m->m_len; 981 982 frm += 12; /* skip tstamp, bintval and capinfo fields */ 983 while (frm < efrm) { 984 if (*frm == IEEE80211_ELEMID_DSPARMS) 985#if IEEE80211_CHAN_MAX < 255 986 if (frm[2] <= IEEE80211_CHAN_MAX) 987#endif 988 ic->ic_curchan = &ic->ic_channels[frm[2]]; 989 990 frm += frm[1] + 2; 991 } 992} 993 994static void 995ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 996 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 997{ 998 struct ieee80211com *ic = &sc->sc_ic; 999 struct ifnet *ifp = ic->ic_ifp; 1000 struct mbuf *mnew, *m; 1001 struct ieee80211_frame *wh; 1002 struct ieee80211_node *ni; 1003 bus_addr_t physaddr; 1004 int error; 1005 1006 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1007 status->rssi)); 1008 1009 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1010 le32toh(status->len) > MCLBYTES) 1011 return; 1012 1013 /* 1014 * Try to allocate a new mbuf for this ring element and load it before 1015 * processing the current mbuf. If the ring element cannot be loaded, 1016 * drop the received packet and reuse the old mbuf. In the unlikely 1017 * case that the old mbuf can't be reloaded either, explicitly panic. 1018 */ 1019 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1020 if (mnew == NULL) { 1021 ifp->if_ierrors++; 1022 return; 1023 } 1024 1025 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1026 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1027 1028 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(mnew, void *), 1029 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1030 if (error != 0) { 1031 m_freem(mnew); 1032 1033 /* try to reload the old mbuf */ 1034 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 1035 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 1036 &physaddr, 0); 1037 if (error != 0) { 1038 /* very unlikely that it will fail... */ 1039 panic("%s: could not load old rx mbuf", 1040 device_get_name(sc->sc_dev)); 1041 } 1042 ifp->if_ierrors++; 1043 return; 1044 } 1045 1046 /* 1047 * New mbuf successfully loaded, update Rx ring and continue 1048 * processing. 1049 */ 1050 m = sbuf->m; 1051 sbuf->m = mnew; 1052 sbd->bd->physaddr = htole32(physaddr); 1053 1054 /* finalize mbuf */ 1055 m->m_pkthdr.rcvif = ifp; 1056 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1057 1058 if (sc->sc_drvbpf != NULL) { 1059 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1060 1061 tap->wr_flags = 0; 1062 tap->wr_antsignal = status->rssi; 1063 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1064 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1065 1066 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1067 } 1068 1069 if (ic->ic_state == IEEE80211_S_SCAN) 1070 ipw_fix_channel(ic, m); 1071 1072 wh = mtod(m, struct ieee80211_frame *); 1073 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1074 1075 /* send the frame to the 802.11 layer */ 1076 ieee80211_input(ic, m, ni, status->rssi, 0); 1077 1078 /* node is no longer needed */ 1079 ieee80211_free_node(ni); 1080 1081 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1082} 1083 1084static void 1085ipw_rx_intr(struct ipw_softc *sc) 1086{ 1087 struct ipw_status *status; 1088 struct ipw_soft_bd *sbd; 1089 struct ipw_soft_buf *sbuf; 1090 uint32_t r, i; 1091 1092 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1093 return; 1094 1095 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1096 1097 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1098 1099 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1100 status = &sc->status_list[i]; 1101 sbd = &sc->srbd_list[i]; 1102 sbuf = sbd->priv; 1103 1104 switch (le16toh(status->code) & 0xf) { 1105 case IPW_STATUS_CODE_COMMAND: 1106 ipw_command_intr(sc, sbuf); 1107 break; 1108 1109 case IPW_STATUS_CODE_NEWSTATE: 1110 ipw_newstate_intr(sc, sbuf); 1111 break; 1112 1113 case IPW_STATUS_CODE_DATA_802_3: 1114 case IPW_STATUS_CODE_DATA_802_11: 1115 ipw_data_intr(sc, status, sbd, sbuf); 1116 break; 1117 1118 case IPW_STATUS_CODE_NOTIFICATION: 1119 DPRINTFN(2, ("received notification\n")); 1120 break; 1121 1122 default: 1123 device_printf(sc->sc_dev, "unknown status code %u\n", 1124 le16toh(status->code)); 1125 } 1126 1127 /* firmware was killed, stop processing received frames */ 1128 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1129 return; 1130 1131 sbd->bd->flags = 0; 1132 } 1133 1134 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1135 1136 /* kick the firmware */ 1137 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1138 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1139} 1140 1141static void 1142ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1143{ 1144 struct ipw_soft_hdr *shdr; 1145 struct ipw_soft_buf *sbuf; 1146 1147 switch (sbd->type) { 1148 case IPW_SBD_TYPE_COMMAND: 1149 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1150 BUS_DMASYNC_POSTWRITE); 1151 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1152 break; 1153 1154 case IPW_SBD_TYPE_HEADER: 1155 shdr = sbd->priv; 1156 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1157 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1158 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1159 break; 1160 1161 case IPW_SBD_TYPE_DATA: 1162 sbuf = sbd->priv; 1163 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1164 BUS_DMASYNC_POSTWRITE); 1165 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1166 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1167 1168 m_freem(sbuf->m); 1169 ieee80211_free_node(sbuf->ni); 1170 1171 sc->sc_tx_timer = 0; 1172 break; 1173 } 1174 1175 sbd->type = IPW_SBD_TYPE_NOASSOC; 1176} 1177 1178static void 1179ipw_tx_intr(struct ipw_softc *sc) 1180{ 1181 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1182 struct ipw_soft_bd *sbd; 1183 uint32_t r, i; 1184 1185 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1186 return; 1187 1188 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1189 1190 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1191 sbd = &sc->stbd_list[i]; 1192 1193 if (sbd->type == IPW_SBD_TYPE_DATA) 1194 ifp->if_opackets++; 1195 1196 ipw_release_sbd(sc, sbd); 1197 sc->txfree++; 1198 } 1199 1200 /* remember what the firmware has processed */ 1201 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1202 1203 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1204 ipw_start(ifp); 1205} 1206 1207static void 1208ipw_intr(void *arg) 1209{ 1210 struct ipw_softc *sc = arg; 1211 uint32_t r; 1212 1213 mtx_lock(&sc->sc_mtx); 1214 1215 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1216 mtx_unlock(&sc->sc_mtx); 1217 return; 1218 } 1219 1220 /* disable interrupts */ 1221 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1222 1223 /* acknowledge all interrupts */ 1224 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1225 1226 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1227 device_printf(sc->sc_dev, "firmware error\n"); 1228 taskqueue_enqueue_fast(taskqueue_fast, &sc->sc_init_task); 1229 r = 0; /* don't process more interrupts */ 1230 } 1231 1232 if (r & IPW_INTR_FW_INIT_DONE) 1233 wakeup(sc); 1234 1235 if (r & IPW_INTR_RX_TRANSFER) 1236 ipw_rx_intr(sc); 1237 1238 if (r & IPW_INTR_TX_TRANSFER) 1239 ipw_tx_intr(sc); 1240 1241 /* re-enable interrupts */ 1242 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1243 1244 mtx_unlock(&sc->sc_mtx); 1245} 1246 1247static void 1248ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1249{ 1250 if (error != 0) 1251 return; 1252 1253 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1254 1255 *(bus_addr_t *)arg = segs[0].ds_addr; 1256} 1257 1258/* 1259 * Send a command to the firmware and wait for the acknowledgement. 1260 */ 1261static int 1262ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1263{ 1264 struct ipw_soft_bd *sbd; 1265 bus_addr_t physaddr; 1266 int error; 1267 1268 sbd = &sc->stbd_list[sc->txcur]; 1269 1270 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1271 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1272 if (error != 0) { 1273 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1274 return error; 1275 } 1276 1277 sc->cmd.type = htole32(type); 1278 sc->cmd.subtype = 0; 1279 sc->cmd.len = htole32(len); 1280 sc->cmd.seq = 0; 1281 memcpy(sc->cmd.data, data, len); 1282 1283 sbd->type = IPW_SBD_TYPE_COMMAND; 1284 sbd->bd->physaddr = htole32(physaddr); 1285 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1286 sbd->bd->nfrag = 1; 1287 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1288 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1289 1290 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1291 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1292 1293 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1294 1295 /* kick firmware */ 1296 sc->txfree--; 1297 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1298 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1299 1300 /* wait at most one second for command to complete */ 1301 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1302} 1303 1304static int 1305ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1306{ 1307 struct ipw_softc *sc = ifp->if_softc; 1308 struct ieee80211com *ic = &sc->sc_ic; 1309 struct ieee80211_frame *wh; 1310 struct ipw_soft_bd *sbd; 1311 struct ipw_soft_hdr *shdr; 1312 struct ipw_soft_buf *sbuf; 1313 struct ieee80211_key *k; 1314 struct mbuf *mnew; 1315 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1316 bus_addr_t physaddr; 1317 int nsegs, error, i; 1318 1319 wh = mtod(m0, struct ieee80211_frame *); 1320 1321 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1322 k = ieee80211_crypto_encap(ic, ni, m0); 1323 if (k == NULL) { 1324 m_freem(m0); 1325 return ENOBUFS; 1326 } 1327 1328 /* packet header may have moved, reset our local pointer */ 1329 wh = mtod(m0, struct ieee80211_frame *); 1330 } 1331 1332 if (sc->sc_drvbpf != NULL) { 1333 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1334 1335 tap->wt_flags = 0; 1336 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1337 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1338 1339 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1340 } 1341 1342 shdr = SLIST_FIRST(&sc->free_shdr); 1343 sbuf = SLIST_FIRST(&sc->free_sbuf); 1344 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1345 1346 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1347 shdr->hdr.subtype = 0; 1348 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1349 shdr->hdr.encrypt = 0; 1350 shdr->hdr.keyidx = 0; 1351 shdr->hdr.keysz = 0; 1352 shdr->hdr.fragmentsz = 0; 1353 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1354 if (ic->ic_opmode == IEEE80211_M_STA) 1355 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1356 else 1357 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1358 1359 /* trim IEEE802.11 header */ 1360 m_adj(m0, sizeof (struct ieee80211_frame)); 1361 1362 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1363 &nsegs, 0); 1364 if (error != 0 && error != EFBIG) { 1365 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1366 error); 1367 m_freem(m0); 1368 return error; 1369 } 1370 if (error != 0) { 1371 mnew = m_defrag(m0, M_DONTWAIT); 1372 if (mnew == NULL) { 1373 device_printf(sc->sc_dev, 1374 "could not defragment mbuf\n"); 1375 m_freem(m0); 1376 return ENOBUFS; 1377 } 1378 m0 = mnew; 1379 1380 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1381 segs, &nsegs, 0); 1382 if (error != 0) { 1383 device_printf(sc->sc_dev, 1384 "could not map mbuf (error %d)\n", error); 1385 m_freem(m0); 1386 return error; 1387 } 1388 } 1389 1390 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1391 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1392 if (error != 0) { 1393 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1394 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1395 m_freem(m0); 1396 return error; 1397 } 1398 1399 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1400 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1401 1402 sbd = &sc->stbd_list[sc->txcur]; 1403 sbd->type = IPW_SBD_TYPE_HEADER; 1404 sbd->priv = shdr; 1405 sbd->bd->physaddr = htole32(physaddr); 1406 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1407 sbd->bd->nfrag = 1 + nsegs; 1408 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1409 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1410 1411 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1412 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1413 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1414 ":")); 1415 1416 sc->txfree--; 1417 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1418 1419 sbuf->m = m0; 1420 sbuf->ni = ni; 1421 1422 for (i = 0; i < nsegs; i++) { 1423 sbd = &sc->stbd_list[sc->txcur]; 1424 1425 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1426 sbd->bd->len = htole32(segs[i].ds_len); 1427 sbd->bd->nfrag = 0; 1428 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1429 if (i == nsegs - 1) { 1430 sbd->type = IPW_SBD_TYPE_DATA; 1431 sbd->priv = sbuf; 1432 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1433 } else { 1434 sbd->type = IPW_SBD_TYPE_NOASSOC; 1435 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1436 } 1437 1438 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1439 1440 sc->txfree--; 1441 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1442 } 1443 1444 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1445 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1446 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1447 1448 /* kick firmware */ 1449 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1450 1451 return 0; 1452} 1453 1454static void 1455ipw_start(struct ifnet *ifp) 1456{ 1457 struct ipw_softc *sc = ifp->if_softc; 1458 struct ieee80211com *ic = &sc->sc_ic; 1459 struct mbuf *m0; 1460 struct ether_header *eh; 1461 struct ieee80211_node *ni; 1462 1463 mtx_lock(&sc->sc_mtx); 1464 1465 if (ic->ic_state != IEEE80211_S_RUN) { 1466 mtx_unlock(&sc->sc_mtx); 1467 return; 1468 } 1469 1470 for (;;) { 1471 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1472 if (m0 == NULL) 1473 break; 1474 1475 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1476 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1477 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1478 break; 1479 } 1480 1481 if (m0->m_len < sizeof (struct ether_header) && 1482 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1483 continue; 1484 1485 eh = mtod(m0, struct ether_header *); 1486 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1487 if (ni == NULL) { 1488 m_freem(m0); 1489 continue; 1490 } 1491 BPF_MTAP(ifp, m0); 1492 1493 m0 = ieee80211_encap(ic, m0, ni); 1494 if (m0 == NULL) { 1495 ieee80211_free_node(ni); 1496 continue; 1497 } 1498 1499 if (ic->ic_rawbpf != NULL) 1500 bpf_mtap(ic->ic_rawbpf, m0); 1501 1502 if (ipw_tx_start(ifp, m0, ni) != 0) { 1503 ieee80211_free_node(ni); 1504 ifp->if_oerrors++; 1505 break; 1506 } 1507 1508 /* start watchdog timer */ 1509 sc->sc_tx_timer = 5; 1510 ifp->if_timer = 1; 1511 } 1512 1513 mtx_unlock(&sc->sc_mtx); 1514} 1515 1516static void 1517ipw_watchdog(struct ifnet *ifp) 1518{ 1519 struct ipw_softc *sc = ifp->if_softc; 1520 struct ieee80211com *ic = &sc->sc_ic; 1521 1522 mtx_lock(&sc->sc_mtx); 1523 1524 ifp->if_timer = 0; 1525 1526 if (sc->sc_tx_timer > 0) { 1527 if (--sc->sc_tx_timer == 0) { 1528 if_printf(ifp, "device timeout\n"); 1529 ifp->if_oerrors++; 1530 taskqueue_enqueue_fast(taskqueue_fast, 1531 &sc->sc_init_task); 1532 mtx_unlock(&sc->sc_mtx); 1533 return; 1534 } 1535 ifp->if_timer = 1; 1536 } 1537 1538 ieee80211_watchdog(ic); 1539 1540 mtx_unlock(&sc->sc_mtx); 1541} 1542 1543static int 1544ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1545{ 1546 struct ipw_softc *sc = ifp->if_softc; 1547 struct ieee80211com *ic = &sc->sc_ic; 1548 int error = 0; 1549 1550 mtx_lock(&sc->sc_mtx); 1551 1552 switch (cmd) { 1553 case SIOCSIFFLAGS: 1554 if (ifp->if_flags & IFF_UP) { 1555 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1556 ipw_init(sc); 1557 } else { 1558 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1559 ipw_stop(sc); 1560 } 1561 break; 1562 1563 default: 1564 error = ieee80211_ioctl(ic, cmd, data); 1565 } 1566 1567 if (error == ENETRESET) { 1568 if ((ifp->if_flags & IFF_UP) && 1569 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1570 ipw_init(sc); 1571 error = 0; 1572 } 1573 1574 mtx_unlock(&sc->sc_mtx); 1575 1576 return error; 1577} 1578 1579static void 1580ipw_stop_master(struct ipw_softc *sc) 1581{ 1582 uint32_t tmp; 1583 int ntries; 1584 1585 /* disable interrupts */ 1586 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1587 1588 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1589 for (ntries = 0; ntries < 50; ntries++) { 1590 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1591 break; 1592 DELAY(10); 1593 } 1594 if (ntries == 50) 1595 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1596 1597 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1598 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1599 1600 sc->flags &= ~IPW_FLAG_FW_INITED; 1601} 1602 1603static int 1604ipw_reset(struct ipw_softc *sc) 1605{ 1606 uint32_t tmp; 1607 int ntries; 1608 1609 ipw_stop_master(sc); 1610 1611 /* move adapter to D0 state */ 1612 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1613 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1614 1615 /* wait for clock stabilization */ 1616 for (ntries = 0; ntries < 1000; ntries++) { 1617 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1618 break; 1619 DELAY(200); 1620 } 1621 if (ntries == 1000) 1622 return EIO; 1623 1624 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1625 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1626 1627 DELAY(10); 1628 1629 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1630 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1631 1632 return 0; 1633} 1634 1635/* 1636 * Upload the microcode to the device. 1637 */ 1638static int 1639ipw_load_ucode(struct ipw_softc *sc, const char *uc, int size) 1640{ 1641 int ntries; 1642 1643 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1644 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1645 1646 MEM_WRITE_2(sc, 0x220000, 0x0703); 1647 MEM_WRITE_2(sc, 0x220000, 0x0707); 1648 1649 MEM_WRITE_1(sc, 0x210014, 0x72); 1650 MEM_WRITE_1(sc, 0x210014, 0x72); 1651 1652 MEM_WRITE_1(sc, 0x210000, 0x40); 1653 MEM_WRITE_1(sc, 0x210000, 0x00); 1654 MEM_WRITE_1(sc, 0x210000, 0x40); 1655 1656 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1657 1658 MEM_WRITE_1(sc, 0x210000, 0x00); 1659 MEM_WRITE_1(sc, 0x210000, 0x00); 1660 MEM_WRITE_1(sc, 0x210000, 0x80); 1661 1662 MEM_WRITE_2(sc, 0x220000, 0x0703); 1663 MEM_WRITE_2(sc, 0x220000, 0x0707); 1664 1665 MEM_WRITE_1(sc, 0x210014, 0x72); 1666 MEM_WRITE_1(sc, 0x210014, 0x72); 1667 1668 MEM_WRITE_1(sc, 0x210000, 0x00); 1669 MEM_WRITE_1(sc, 0x210000, 0x80); 1670 1671 for (ntries = 0; ntries < 10; ntries++) { 1672 if (MEM_READ_1(sc, 0x210000) & 1) 1673 break; 1674 DELAY(10); 1675 } 1676 if (ntries == 10) { 1677 device_printf(sc->sc_dev, 1678 "timeout waiting for ucode to initialize\n"); 1679 return EIO; 1680 } 1681 1682 MEM_WRITE_4(sc, 0x3000e0, 0); 1683 1684 return 0; 1685} 1686 1687/* set of macros to handle unaligned little endian data in firmware image */ 1688#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1689#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1690static int 1691ipw_load_firmware(struct ipw_softc *sc, const char *fw, int size) 1692{ 1693 const uint8_t *p, *end; 1694 uint32_t tmp, dst; 1695 uint16_t len; 1696 int error; 1697 1698 p = fw; 1699 end = fw + size; 1700 while (p < end) { 1701 dst = GETLE32(p); p += 4; 1702 len = GETLE16(p); p += 2; 1703 1704 ipw_write_mem_1(sc, dst, p, len); 1705 p += len; 1706 } 1707 1708 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1709 IPW_IO_LED_OFF); 1710 1711 /* enable interrupts */ 1712 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1713 1714 /* kick the firmware */ 1715 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1716 1717 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1718 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1719 1720 /* wait at most one second for firmware initialization to complete */ 1721 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1722 device_printf(sc->sc_dev, "timeout waiting for firmware " 1723 "initialization to complete\n"); 1724 return error; 1725 } 1726 1727 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1728 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1729 IPW_IO_GPIO3_MASK); 1730 1731 return 0; 1732} 1733 1734static int 1735ipw_config(struct ipw_softc *sc) 1736{ 1737 struct ieee80211com *ic = &sc->sc_ic; 1738 struct ifnet *ifp = ic->ic_ifp; 1739 struct ipw_security security; 1740 struct ieee80211_key *k; 1741 struct ipw_wep_key wepkey; 1742 struct ipw_scan_options options; 1743 struct ipw_configuration config; 1744 uint32_t data; 1745 int error, i; 1746 1747 switch (ic->ic_opmode) { 1748 case IEEE80211_M_STA: 1749 case IEEE80211_M_HOSTAP: 1750 data = htole32(IPW_MODE_BSS); 1751 break; 1752 case IEEE80211_M_IBSS: 1753 case IEEE80211_M_AHDEMO: 1754 data = htole32(IPW_MODE_IBSS); 1755 break; 1756 case IEEE80211_M_MONITOR: 1757 data = htole32(IPW_MODE_MONITOR); 1758 break; 1759 } 1760 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1761 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1762 if (error != 0) 1763 return error; 1764 1765 if (ic->ic_opmode == IEEE80211_M_IBSS || 1766 ic->ic_opmode == IEEE80211_M_MONITOR) { 1767 data = htole32(ieee80211_chan2ieee(ic, ic->ic_curchan)); 1768 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1769 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1770 if (error != 0) 1771 return error; 1772 } 1773 1774 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1775 DPRINTF(("Enabling adapter\n")); 1776 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1777 } 1778 1779 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1780 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1781 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1782 IEEE80211_ADDR_LEN); 1783 if (error != 0) 1784 return error; 1785 1786 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1787 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1788 if (ic->ic_opmode == IEEE80211_M_IBSS) 1789 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1790 if (ifp->if_flags & IFF_PROMISC) 1791 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1792 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1793 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1794 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1795 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1796 if (error != 0) 1797 return error; 1798 1799 data = htole32(0x3); /* 1, 2 */ 1800 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1801 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1802 if (error != 0) 1803 return error; 1804 1805 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1806 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1807 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1808 if (error != 0) 1809 return error; 1810 1811 data = htole32(IPW_POWER_MODE_CAM); 1812 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1813 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1814 if (error != 0) 1815 return error; 1816 1817 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1818 data = htole32(32); /* default value */ 1819 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1820 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1821 sizeof data); 1822 if (error != 0) 1823 return error; 1824 } 1825 1826 data = htole32(ic->ic_rtsthreshold); 1827 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1828 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1829 if (error != 0) 1830 return error; 1831 1832 data = htole32(ic->ic_fragthreshold); 1833 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1834 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1835 if (error != 0) 1836 return error; 1837 1838#ifdef IPW_DEBUG 1839 if (ipw_debug > 0) { 1840 printf("Setting ESSID to "); 1841 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1842 printf("\n"); 1843 } 1844#endif 1845 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1846 ic->ic_des_esslen); 1847 if (error != 0) 1848 return error; 1849 1850 /* no mandatory BSSID */ 1851 DPRINTF(("Setting mandatory BSSID to null\n")); 1852 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1853 if (error != 0) 1854 return error; 1855 1856 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1857 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1858 ":")); 1859 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1860 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1861 if (error != 0) 1862 return error; 1863 } 1864 1865 memset(&security, 0, sizeof security); 1866 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1867 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1868 security.ciphers = htole32(IPW_CIPHER_NONE); 1869 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1870 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1871 sizeof security); 1872 if (error != 0) 1873 return error; 1874 1875 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1876 k = ic->ic_crypto.cs_nw_keys; 1877 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1878 if (k->wk_keylen == 0) 1879 continue; 1880 1881 wepkey.idx = i; 1882 wepkey.len = k->wk_keylen; 1883 memset(wepkey.key, 0, sizeof wepkey.key); 1884 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 1885 DPRINTF(("Setting wep key index %u len %u\n", 1886 wepkey.idx, wepkey.len)); 1887 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1888 sizeof wepkey); 1889 if (error != 0) 1890 return error; 1891 } 1892 1893 data = htole32(ic->ic_crypto.cs_def_txkey); 1894 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1895 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1896 sizeof data); 1897 if (error != 0) 1898 return error; 1899 } 1900 1901 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1902 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1903 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1904 if (error != 0) 1905 return error; 1906 1907#if 0 1908 struct ipw_wpa_ie ie; 1909 1910 memset(&ie, 0, sizeof ie); 1911 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1912 DPRINTF(("Setting wpa ie\n")); 1913 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1914 if (error != 0) 1915 return error; 1916#endif 1917 1918 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1919 data = htole32(ic->ic_bintval); 1920 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1921 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1922 sizeof data); 1923 if (error != 0) 1924 return error; 1925 } 1926 1927 options.flags = 0; 1928 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1929 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 1930 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1931 if (error != 0) 1932 return error; 1933 1934 /* finally, enable adapter (start scanning for an access point) */ 1935 DPRINTF(("Enabling adapter\n")); 1936 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1937} 1938 1939/* 1940 * Handler for sc_init_task. This is a simple wrapper around ipw_init(). 1941 * It is called on firmware panics or on watchdog timeouts. 1942 */ 1943static void 1944ipw_init_task(void *context, int pending) 1945{ 1946 ipw_init(context); 1947} 1948 1949static void 1950ipw_init(void *priv) 1951{ 1952 struct ipw_softc *sc = priv; 1953 struct ieee80211com *ic = &sc->sc_ic; 1954 struct ifnet *ifp = ic->ic_ifp; 1955 struct firmware *fp; 1956 const struct ipw_firmware_hdr *hdr; 1957 const char *imagename, *fw; 1958 int owned; 1959 1960 /* 1961 * ipw_init() is exposed through ifp->if_init so it might be called 1962 * without the driver's lock held. Since msleep() doesn't like being 1963 * called on a recursed mutex, we acquire the driver's lock only if 1964 * we're not already holding it. 1965 */ 1966 if (!(owned = mtx_owned(&sc->sc_mtx))) 1967 mtx_lock(&sc->sc_mtx); 1968 1969 /* 1970 * Avoid re-entrant calls. We need to release the mutex in ipw_init() 1971 * when loading the firmware and we don't want to be called during this 1972 * operation. 1973 */ 1974 if (sc->flags & IPW_FLAG_INIT_LOCKED) { 1975 if (!owned) 1976 mtx_unlock(&sc->sc_mtx); 1977 return; 1978 } 1979 sc->flags |= IPW_FLAG_INIT_LOCKED; 1980 1981 ipw_stop(sc); 1982 1983 if (ipw_reset(sc) != 0) { 1984 device_printf(sc->sc_dev, "could not reset adapter\n"); 1985 goto fail1; 1986 } 1987 1988 switch (ic->ic_opmode) { 1989 case IEEE80211_M_STA: 1990 imagename = "ipw_bss"; 1991 break; 1992 case IEEE80211_M_IBSS: 1993 imagename = "ipw_ibss"; 1994 break; 1995 case IEEE80211_M_MONITOR: 1996 imagename = "ipw_monitor"; 1997 break; 1998 default: 1999 imagename = NULL; /* should not get there */ 2000 } 2001 2002 /* 2003 * Load firmware image using the firmware(9) subsystem. We need to 2004 * release the driver's lock first. 2005 */ 2006 mtx_unlock(&sc->sc_mtx); 2007 fp = firmware_get(imagename); 2008 mtx_lock(&sc->sc_mtx); 2009 2010 if (fp == NULL) { 2011 device_printf(sc->sc_dev, 2012 "could not load firmware image '%s'\n", imagename); 2013 goto fail1; 2014 } 2015 2016 if (fp->datasize < sizeof *hdr) { 2017 device_printf(sc->sc_dev, 2018 "firmware image too short %zu\n", fp->datasize); 2019 goto fail2; 2020 } 2021 2022 hdr = (const struct ipw_firmware_hdr *)fp->data; 2023 2024 if (fp->datasize < sizeof *hdr + le32toh(hdr->mainsz) + 2025 le32toh(hdr->ucodesz)) { 2026 device_printf(sc->sc_dev, 2027 "firmware image too short %zu\n", fp->datasize); 2028 goto fail2; 2029 } 2030 2031 fw = (const char *)fp->data + sizeof *hdr + le32toh(hdr->mainsz); 2032 if (ipw_load_ucode(sc, fw, le32toh(hdr->ucodesz)) != 0) { 2033 device_printf(sc->sc_dev, "could not load microcode\n"); 2034 goto fail2; 2035 } 2036 2037 ipw_stop_master(sc); 2038 2039 /* 2040 * Setup tx, rx and status rings. 2041 */ 2042 sc->txold = IPW_NTBD - 1; 2043 sc->txcur = 0; 2044 sc->txfree = IPW_NTBD - 2; 2045 sc->rxcur = IPW_NRBD - 1; 2046 2047 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2048 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2049 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2050 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2051 2052 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2053 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2054 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2055 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2056 2057 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2058 2059 fw = (const char *)fp->data + sizeof *hdr; 2060 if (ipw_load_firmware(sc, fw, le32toh(hdr->mainsz)) != 0) { 2061 device_printf(sc->sc_dev, "could not load firmware\n"); 2062 goto fail2; 2063 } 2064 2065 firmware_put(fp, FIRMWARE_UNLOAD); 2066 sc->flags |= IPW_FLAG_FW_INITED; 2067 2068 /* retrieve information tables base addresses */ 2069 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2070 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2071 2072 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2073 2074 if (ipw_config(sc) != 0) { 2075 device_printf(sc->sc_dev, "device configuration failed\n"); 2076 goto fail1; 2077 } 2078 2079 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2080 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2081 2082 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2083 2084 if (!owned) 2085 mtx_unlock(&sc->sc_mtx); 2086 2087 return; 2088 2089fail2: firmware_put(fp, FIRMWARE_UNLOAD); 2090fail1: ifp->if_flags &= ~IFF_UP; 2091 ipw_stop(sc); 2092 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2093 if (!owned) 2094 mtx_unlock(&sc->sc_mtx); 2095} 2096 2097static void 2098ipw_stop(void *priv) 2099{ 2100 struct ipw_softc *sc = priv; 2101 struct ieee80211com *ic = &sc->sc_ic; 2102 struct ifnet *ifp = ic->ic_ifp; 2103 int i; 2104 2105 mtx_lock(&sc->sc_mtx); 2106 2107 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2108 2109 ipw_stop_master(sc); 2110 2111 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2112 2113 /* 2114 * Release tx buffers. 2115 */ 2116 for (i = 0; i < IPW_NTBD; i++) 2117 ipw_release_sbd(sc, &sc->stbd_list[i]); 2118 2119 sc->sc_tx_timer = 0; 2120 ifp->if_timer = 0; 2121 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2122 2123 mtx_unlock(&sc->sc_mtx); 2124} 2125 2126static int 2127ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2128{ 2129 struct ipw_softc *sc = arg1; 2130 uint32_t i, size, buf[256]; 2131 2132 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2133 memset(buf, 0, sizeof buf); 2134 return SYSCTL_OUT(req, buf, sizeof buf); 2135 } 2136 2137 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2138 2139 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2140 for (i = 1; i < size; i++) 2141 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2142 2143 return SYSCTL_OUT(req, buf, sizeof buf); 2144} 2145 2146static int 2147ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2148{ 2149 struct ipw_softc *sc = arg1; 2150 int val; 2151 2152 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2153 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2154 2155 return SYSCTL_OUT(req, &val, sizeof val); 2156} 2157 2158static uint32_t 2159ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2160{ 2161 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2162} 2163 2164static void 2165ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2166{ 2167 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2168} 2169 2170static int 2171ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2172{ 2173 uint32_t addr, info; 2174 uint16_t count, size; 2175 uint32_t total; 2176 2177 /* addr[4] + count[2] + size[2] */ 2178 addr = MEM_READ_4(sc, sc->table2_base + off); 2179 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2180 2181 count = info >> 16; 2182 size = info & 0xffff; 2183 total = count * size; 2184 2185 if (total > *len) { 2186 *len = total; 2187 return EINVAL; 2188 } 2189 2190 *len = total; 2191 ipw_read_mem_1(sc, addr, buf, total); 2192 2193 return 0; 2194} 2195 2196static void 2197ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2198 bus_size_t count) 2199{ 2200 for (; count > 0; offset++, datap++, count--) { 2201 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2202 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2203 } 2204} 2205 2206static void 2207ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, const uint8_t *datap, 2208 bus_size_t count) 2209{ 2210 for (; count > 0; offset++, datap++, count--) { 2211 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2212 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2213 } 2214} 2215