if_ipw.c revision 156599
1/* $FreeBSD: head/sys/dev/ipw/if_ipw.c 156599 2006-03-12 19:01:00Z damien $ */ 2 3/*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ipw/if_ipw.c 156599 2006-03-12 19:01:00Z damien $"); 32 33/*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38#include <sys/param.h> 39#include <sys/sysctl.h> 40#include <sys/sockio.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/systm.h> 45#include <sys/malloc.h> 46#include <sys/queue.h> 47#include <sys/taskqueue.h> 48#include <sys/module.h> 49#include <sys/bus.h> 50#include <sys/endian.h> 51#include <sys/linker.h> 52#include <sys/firmware.h> 53 54#include <machine/bus.h> 55#include <machine/resource.h> 56#include <machine/clock.h> 57#include <sys/rman.h> 58 59#include <dev/pci/pcireg.h> 60#include <dev/pci/pcivar.h> 61 62#include <net/bpf.h> 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68#include <net/if_types.h> 69 70#include <net80211/ieee80211_var.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#include <netinet/in.h> 74#include <netinet/in_systm.h> 75#include <netinet/in_var.h> 76#include <netinet/ip.h> 77#include <netinet/if_ether.h> 78 79#include <dev/ipw/if_ipwreg.h> 80#include <dev/ipw/if_ipwvar.h> 81 82#ifdef IPW_DEBUG 83#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 84#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 85int ipw_debug = 0; 86SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 87#else 88#define DPRINTF(x) 89#define DPRINTFN(n, x) 90#endif 91 92MODULE_DEPEND(ipw, pci, 1, 1, 1); 93MODULE_DEPEND(ipw, wlan, 1, 1, 1); 94MODULE_DEPEND(ipw, firmware, 1, 1, 1); 95 96struct ipw_ident { 97 uint16_t vendor; 98 uint16_t device; 99 const char *name; 100}; 101 102static const struct ipw_ident ipw_ident_table[] = { 103 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 104 105 { 0, 0, NULL } 106}; 107 108static int ipw_dma_alloc(struct ipw_softc *); 109static void ipw_release(struct ipw_softc *); 110static int ipw_media_change(struct ifnet *); 111static void ipw_media_status(struct ifnet *, struct ifmediareq *); 112static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 113static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 114static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 115static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 116static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 117 struct ipw_soft_bd *, struct ipw_soft_buf *); 118static void ipw_rx_intr(struct ipw_softc *); 119static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 120static void ipw_tx_intr(struct ipw_softc *); 121static void ipw_intr(void *); 122static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 123static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 124static int ipw_tx_start(struct ifnet *, struct mbuf *, 125 struct ieee80211_node *); 126static void ipw_start(struct ifnet *); 127static void ipw_watchdog(struct ifnet *); 128static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 129static void ipw_stop_master(struct ipw_softc *); 130static int ipw_reset(struct ipw_softc *); 131static int ipw_load_ucode(struct ipw_softc *, const char *, int); 132static int ipw_load_firmware(struct ipw_softc *, const char *, int); 133static int ipw_config(struct ipw_softc *); 134static void ipw_init_task(void *, int); 135static void ipw_init(void *); 136static void ipw_stop(void *); 137static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 138static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 139static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 140static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 141static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 142 uint32_t *); 143static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 144 bus_size_t); 145static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, 146 const uint8_t *, bus_size_t); 147 148static int ipw_probe(device_t); 149static int ipw_attach(device_t); 150static int ipw_detach(device_t); 151static int ipw_shutdown(device_t); 152static int ipw_suspend(device_t); 153static int ipw_resume(device_t); 154 155static device_method_t ipw_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, ipw_probe), 158 DEVMETHOD(device_attach, ipw_attach), 159 DEVMETHOD(device_detach, ipw_detach), 160 DEVMETHOD(device_shutdown, ipw_shutdown), 161 DEVMETHOD(device_suspend, ipw_suspend), 162 DEVMETHOD(device_resume, ipw_resume), 163 164 { 0, 0 } 165}; 166 167static driver_t ipw_driver = { 168 "ipw", 169 ipw_methods, 170 sizeof (struct ipw_softc) 171}; 172 173static devclass_t ipw_devclass; 174 175DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 176 177/* 178 * Supported rates for 802.11b mode (in 500Kbps unit). 179 */ 180static const struct ieee80211_rateset ipw_rateset_11b = 181 { 4, { 2, 4, 11, 22 } }; 182 183static int 184ipw_probe(device_t dev) 185{ 186 const struct ipw_ident *ident; 187 188 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 189 if (pci_get_vendor(dev) == ident->vendor && 190 pci_get_device(dev) == ident->device) { 191 device_set_desc(dev, ident->name); 192 return 0; 193 } 194 } 195 return ENXIO; 196} 197 198/* Base Address Register */ 199#define IPW_PCI_BAR0 0x10 200 201static int 202ipw_attach(device_t dev) 203{ 204 struct ipw_softc *sc = device_get_softc(dev); 205 struct ifnet *ifp; 206 struct ieee80211com *ic = &sc->sc_ic; 207 uint16_t val; 208 int error, i; 209 210 sc->sc_dev = dev; 211 212 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 213 MTX_DEF | MTX_RECURSE); 214 215 TASK_INIT(&sc->sc_init_task, 0, ipw_init_task, sc); 216 217 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 218 device_printf(dev, "chip is in D%d power mode " 219 "-- setting to D0\n", pci_get_powerstate(dev)); 220 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 221 } 222 223 pci_write_config(dev, 0x41, 0, 1); 224 225 /* enable bus-mastering */ 226 pci_enable_busmaster(dev); 227 228 sc->mem_rid = IPW_PCI_BAR0; 229 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 230 RF_ACTIVE); 231 if (sc->mem == NULL) { 232 device_printf(dev, "could not allocate memory resource\n"); 233 goto fail; 234 } 235 236 sc->sc_st = rman_get_bustag(sc->mem); 237 sc->sc_sh = rman_get_bushandle(sc->mem); 238 239 sc->irq_rid = 0; 240 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 241 RF_ACTIVE | RF_SHAREABLE); 242 if (sc->irq == NULL) { 243 device_printf(dev, "could not allocate interrupt resource\n"); 244 goto fail; 245 } 246 247 if (ipw_reset(sc) != 0) { 248 device_printf(dev, "could not reset adapter\n"); 249 goto fail; 250 } 251 252 if (ipw_dma_alloc(sc) != 0) { 253 device_printf(dev, "could not allocate DMA resources\n"); 254 goto fail; 255 } 256 257 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 258 if (ifp == NULL) { 259 device_printf(dev, "can not if_alloc()\n"); 260 goto fail; 261 } 262 263 ifp->if_softc = sc; 264 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_init = ipw_init; 267 ifp->if_ioctl = ipw_ioctl; 268 ifp->if_start = ipw_start; 269 ifp->if_watchdog = ipw_watchdog; 270 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 271 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 272 IFQ_SET_READY(&ifp->if_snd); 273 274 ic->ic_ifp = ifp; 275 ic->ic_phytype = IEEE80211_T_DS; 276 ic->ic_opmode = IEEE80211_M_STA; 277 ic->ic_state = IEEE80211_S_INIT; 278 279 /* set device capabilities */ 280 ic->ic_caps = 281 IEEE80211_C_IBSS | /* IBSS mode supported */ 282 IEEE80211_C_MONITOR | /* monitor mode supported */ 283 IEEE80211_C_TXPMGT | /* tx power management */ 284 IEEE80211_C_SHPREAMBLE; /* short preamble supported */ 285 286 /* read MAC address from EEPROM */ 287 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 288 ic->ic_myaddr[0] = val >> 8; 289 ic->ic_myaddr[1] = val & 0xff; 290 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 291 ic->ic_myaddr[2] = val >> 8; 292 ic->ic_myaddr[3] = val & 0xff; 293 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 294 ic->ic_myaddr[4] = val >> 8; 295 ic->ic_myaddr[5] = val & 0xff; 296 297 /* set supported .11b rates */ 298 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 299 300 /* set supported .11b channels (read from EEPROM) */ 301 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 302 val = 0x7ff; /* default to channels 1-11 */ 303 val <<= 1; 304 for (i = 1; i < 16; i++) { 305 if (val & (1 << i)) { 306 ic->ic_channels[i].ic_freq = 307 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 308 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 309 } 310 } 311 312 /* check support for radio transmitter switch in EEPROM */ 313 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 314 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 315 316 ieee80211_ifattach(ic); 317 /* override state transition machine */ 318 sc->sc_newstate = ic->ic_newstate; 319 ic->ic_newstate = ipw_newstate; 320 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 321 322 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 323 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 324 325 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 326 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 327 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 328 329 sc->sc_txtap_len = sizeof sc->sc_txtapu; 330 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 331 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 332 333 /* 334 * Add a few sysctl knobs. 335 */ 336 sc->dwelltime = 100; 337 338 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 339 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 340 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 341 "radio transmitter switch state (0=off, 1=on)"); 342 343 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 344 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 345 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 346 "statistics"); 347 348 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 349 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 350 CTLFLAG_RW, &sc->dwelltime, 0, 351 "channel dwell time (ms) for AP/station scanning"); 352 353 /* 354 * Hook our interrupt after all initialization is complete. 355 */ 356 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 357 ipw_intr, sc, &sc->sc_ih); 358 if (error != 0) { 359 device_printf(dev, "could not set up interrupt\n"); 360 goto fail; 361 } 362 363 if (bootverbose) 364 ieee80211_announce(ic); 365 366 return 0; 367 368fail: ipw_detach(dev); 369 return ENXIO; 370} 371 372static int 373ipw_detach(device_t dev) 374{ 375 struct ipw_softc *sc = device_get_softc(dev); 376 struct ieee80211com *ic = &sc->sc_ic; 377 struct ifnet *ifp = ic->ic_ifp; 378 379 ipw_stop(sc); 380 381 if (ifp != NULL) { 382 bpfdetach(ifp); 383 ieee80211_ifdetach(ic); 384 } 385 386 ipw_release(sc); 387 388 if (sc->irq != NULL) { 389 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 390 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 391 } 392 393 if (sc->mem != NULL) 394 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 395 396 if (ifp != NULL) 397 if_free(ifp); 398 399 mtx_destroy(&sc->sc_mtx); 400 401 return 0; 402} 403 404static int 405ipw_dma_alloc(struct ipw_softc *sc) 406{ 407 struct ipw_soft_bd *sbd; 408 struct ipw_soft_hdr *shdr; 409 struct ipw_soft_buf *sbuf; 410 bus_addr_t physaddr; 411 int error, i; 412 413 /* 414 * Allocate and map tx ring. 415 */ 416 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 417 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 418 NULL, &sc->tbd_dmat); 419 if (error != 0) { 420 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 421 goto fail; 422 } 423 424 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 425 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 426 if (error != 0) { 427 device_printf(sc->sc_dev, 428 "could not allocate tx ring DMA memory\n"); 429 goto fail; 430 } 431 432 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 433 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 434 if (error != 0) { 435 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 436 goto fail; 437 } 438 439 /* 440 * Allocate and map rx ring. 441 */ 442 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 443 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 444 NULL, &sc->rbd_dmat); 445 if (error != 0) { 446 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 447 goto fail; 448 } 449 450 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 451 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 452 if (error != 0) { 453 device_printf(sc->sc_dev, 454 "could not allocate rx ring DMA memory\n"); 455 goto fail; 456 } 457 458 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 459 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 460 if (error != 0) { 461 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 462 goto fail; 463 } 464 465 /* 466 * Allocate and map status ring. 467 */ 468 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 469 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 470 NULL, NULL, &sc->status_dmat); 471 if (error != 0) { 472 device_printf(sc->sc_dev, 473 "could not create status ring DMA tag\n"); 474 goto fail; 475 } 476 477 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 478 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 479 if (error != 0) { 480 device_printf(sc->sc_dev, 481 "could not allocate status ring DMA memory\n"); 482 goto fail; 483 } 484 485 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 486 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 487 0); 488 if (error != 0) { 489 device_printf(sc->sc_dev, 490 "could not map status ring DMA memory\n"); 491 goto fail; 492 } 493 494 /* 495 * Allocate command DMA map. 496 */ 497 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 498 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 499 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 500 if (error != 0) { 501 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 502 goto fail; 503 } 504 505 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 506 if (error != 0) { 507 device_printf(sc->sc_dev, 508 "could not create command DMA map\n"); 509 goto fail; 510 } 511 512 /* 513 * Allocate headers DMA maps. 514 */ 515 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 516 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 517 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 518 if (error != 0) { 519 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 520 goto fail; 521 } 522 523 SLIST_INIT(&sc->free_shdr); 524 for (i = 0; i < IPW_NDATA; i++) { 525 shdr = &sc->shdr_list[i]; 526 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 527 if (error != 0) { 528 device_printf(sc->sc_dev, 529 "could not create header DMA map\n"); 530 goto fail; 531 } 532 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 533 } 534 535 /* 536 * Allocate tx buffers DMA maps. 537 */ 538 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 539 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 540 NULL, NULL, &sc->txbuf_dmat); 541 if (error != 0) { 542 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 543 goto fail; 544 } 545 546 SLIST_INIT(&sc->free_sbuf); 547 for (i = 0; i < IPW_NDATA; i++) { 548 sbuf = &sc->tx_sbuf_list[i]; 549 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 550 if (error != 0) { 551 device_printf(sc->sc_dev, 552 "could not create tx DMA map\n"); 553 goto fail; 554 } 555 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 556 } 557 558 /* 559 * Initialize tx ring. 560 */ 561 for (i = 0; i < IPW_NTBD; i++) { 562 sbd = &sc->stbd_list[i]; 563 sbd->bd = &sc->tbd_list[i]; 564 sbd->type = IPW_SBD_TYPE_NOASSOC; 565 } 566 567 /* 568 * Pre-allocate rx buffers and DMA maps. 569 */ 570 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 571 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 572 NULL, &sc->rxbuf_dmat); 573 if (error != 0) { 574 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 575 goto fail; 576 } 577 578 for (i = 0; i < IPW_NRBD; i++) { 579 sbd = &sc->srbd_list[i]; 580 sbuf = &sc->rx_sbuf_list[i]; 581 sbd->bd = &sc->rbd_list[i]; 582 583 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 584 if (sbuf->m == NULL) { 585 device_printf(sc->sc_dev, 586 "could not allocate rx mbuf\n"); 587 error = ENOMEM; 588 goto fail; 589 } 590 591 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 592 if (error != 0) { 593 device_printf(sc->sc_dev, 594 "could not create rx DMA map\n"); 595 goto fail; 596 } 597 598 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 599 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 600 &physaddr, 0); 601 if (error != 0) { 602 device_printf(sc->sc_dev, 603 "could not map rx DMA memory\n"); 604 goto fail; 605 } 606 607 sbd->type = IPW_SBD_TYPE_DATA; 608 sbd->priv = sbuf; 609 sbd->bd->physaddr = htole32(physaddr); 610 sbd->bd->len = htole32(MCLBYTES); 611 } 612 613 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 614 615 return 0; 616 617fail: ipw_release(sc); 618 return error; 619} 620 621static void 622ipw_release(struct ipw_softc *sc) 623{ 624 struct ipw_soft_buf *sbuf; 625 int i; 626 627 if (sc->tbd_dmat != NULL) { 628 if (sc->stbd_list != NULL) { 629 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 630 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 631 sc->tbd_map); 632 } 633 bus_dma_tag_destroy(sc->tbd_dmat); 634 } 635 636 if (sc->rbd_dmat != NULL) { 637 if (sc->rbd_list != NULL) { 638 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 639 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 640 sc->rbd_map); 641 } 642 bus_dma_tag_destroy(sc->rbd_dmat); 643 } 644 645 if (sc->status_dmat != NULL) { 646 if (sc->status_list != NULL) { 647 bus_dmamap_unload(sc->status_dmat, sc->status_map); 648 bus_dmamem_free(sc->status_dmat, sc->status_list, 649 sc->status_map); 650 } 651 bus_dma_tag_destroy(sc->status_dmat); 652 } 653 654 for (i = 0; i < IPW_NTBD; i++) 655 ipw_release_sbd(sc, &sc->stbd_list[i]); 656 657 if (sc->cmd_dmat != NULL) { 658 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 659 bus_dma_tag_destroy(sc->cmd_dmat); 660 } 661 662 if (sc->hdr_dmat != NULL) { 663 for (i = 0; i < IPW_NDATA; i++) 664 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 665 bus_dma_tag_destroy(sc->hdr_dmat); 666 } 667 668 if (sc->txbuf_dmat != NULL) { 669 for (i = 0; i < IPW_NDATA; i++) { 670 bus_dmamap_destroy(sc->txbuf_dmat, 671 sc->tx_sbuf_list[i].map); 672 } 673 bus_dma_tag_destroy(sc->txbuf_dmat); 674 } 675 676 if (sc->rxbuf_dmat != NULL) { 677 for (i = 0; i < IPW_NRBD; i++) { 678 sbuf = &sc->rx_sbuf_list[i]; 679 if (sbuf->m != NULL) { 680 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 681 BUS_DMASYNC_POSTREAD); 682 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 683 m_freem(sbuf->m); 684 } 685 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 686 } 687 bus_dma_tag_destroy(sc->rxbuf_dmat); 688 } 689} 690 691static int 692ipw_shutdown(device_t dev) 693{ 694 struct ipw_softc *sc = device_get_softc(dev); 695 696 ipw_stop(sc); 697 698 return 0; 699} 700 701static int 702ipw_suspend(device_t dev) 703{ 704 struct ipw_softc *sc = device_get_softc(dev); 705 706 ipw_stop(sc); 707 708 return 0; 709} 710 711static int 712ipw_resume(device_t dev) 713{ 714 struct ipw_softc *sc = device_get_softc(dev); 715 struct ifnet *ifp = sc->sc_ic.ic_ifp; 716 717 mtx_lock(&sc->sc_mtx); 718 719 pci_write_config(dev, 0x41, 0, 1); 720 721 if (ifp->if_flags & IFF_UP) { 722 ifp->if_init(ifp->if_softc); 723 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 724 ifp->if_start(ifp); 725 } 726 727 mtx_unlock(&sc->sc_mtx); 728 729 return 0; 730} 731 732static int 733ipw_media_change(struct ifnet *ifp) 734{ 735 struct ipw_softc *sc = ifp->if_softc; 736 int error; 737 738 mtx_lock(&sc->sc_mtx); 739 740 error = ieee80211_media_change(ifp); 741 if (error != ENETRESET) { 742 mtx_unlock(&sc->sc_mtx); 743 return error; 744 } 745 746 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 747 ipw_init(sc); 748 749 mtx_unlock(&sc->sc_mtx); 750 751 return 0; 752} 753 754/* 755 * The firmware automatically adapts the transmit speed. We report its current 756 * value here. 757 */ 758static void 759ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 760{ 761#define N(a) (sizeof (a) / sizeof (a[0])) 762 struct ipw_softc *sc = ifp->if_softc; 763 struct ieee80211com *ic = &sc->sc_ic; 764 static const struct { 765 uint32_t val; 766 int rate; 767 } rates[] = { 768 { IPW_RATE_DS1, 2 }, 769 { IPW_RATE_DS2, 4 }, 770 { IPW_RATE_DS5, 11 }, 771 { IPW_RATE_DS11, 22 }, 772 }; 773 uint32_t val; 774 int rate, i; 775 776 imr->ifm_status = IFM_AVALID; 777 imr->ifm_active = IFM_IEEE80211; 778 if (ic->ic_state == IEEE80211_S_RUN) 779 imr->ifm_status |= IFM_ACTIVE; 780 781 /* read current transmission rate from adapter */ 782 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 783 784 /* convert ipw rate to 802.11 rate */ 785 for (i = 0; i < N(rates) && rates[i].val != val; i++); 786 rate = (i < N(rates)) ? rates[i].rate : 0; 787 788 imr->ifm_active |= IFM_IEEE80211_11B; 789 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 790 switch (ic->ic_opmode) { 791 case IEEE80211_M_STA: 792 break; 793 794 case IEEE80211_M_IBSS: 795 imr->ifm_active |= IFM_IEEE80211_IBSS; 796 break; 797 798 case IEEE80211_M_MONITOR: 799 imr->ifm_active |= IFM_IEEE80211_MONITOR; 800 break; 801 802 case IEEE80211_M_AHDEMO: 803 case IEEE80211_M_HOSTAP: 804 /* should not get there */ 805 break; 806 } 807#undef N 808} 809 810static int 811ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 812{ 813 struct ifnet *ifp = ic->ic_ifp; 814 struct ipw_softc *sc = ifp->if_softc; 815 struct ieee80211_node *ni; 816 uint8_t macaddr[IEEE80211_ADDR_LEN]; 817 uint32_t len; 818 819 switch (nstate) { 820 case IEEE80211_S_RUN: 821 DELAY(200); /* firmware needs a short delay here */ 822 823 len = IEEE80211_ADDR_LEN; 824 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 825 826 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 827 if (ni == NULL) 828 break; 829 830 ieee80211_ref_node(ni); 831 ieee80211_sta_join(ic, ni); 832 ieee80211_node_authorize(ni); 833 834 if (ic->ic_opmode == IEEE80211_M_STA) 835 ieee80211_notify_node_join(ic, ni, 1); 836 break; 837 838 case IEEE80211_S_INIT: 839 case IEEE80211_S_SCAN: 840 case IEEE80211_S_AUTH: 841 case IEEE80211_S_ASSOC: 842 break; 843 } 844 845 ic->ic_state = nstate; 846 847 return 0; 848} 849 850/* 851 * Read 16 bits at address 'addr' from the serial EEPROM. 852 */ 853static uint16_t 854ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 855{ 856 uint32_t tmp; 857 uint16_t val; 858 int n; 859 860 /* clock C once before the first command */ 861 IPW_EEPROM_CTL(sc, 0); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 865 866 /* write start bit (1) */ 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 869 870 /* write READ opcode (10) */ 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 875 876 /* write address A7-A0 */ 877 for (n = 7; n >= 0; n--) { 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 879 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 881 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 882 } 883 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 885 886 /* read data Q15-Q0 */ 887 val = 0; 888 for (n = 15; n >= 0; n--) { 889 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 891 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 892 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 893 } 894 895 IPW_EEPROM_CTL(sc, 0); 896 897 /* clear Chip Select and clock C */ 898 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 899 IPW_EEPROM_CTL(sc, 0); 900 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 901 902 return le16toh(val); 903} 904 905static void 906ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 907{ 908 struct ipw_cmd *cmd; 909 910 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 911 912 cmd = mtod(sbuf->m, struct ipw_cmd *); 913 914 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 915 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 916 le32toh(cmd->status))); 917 918 wakeup(sc); 919} 920 921static void 922ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 923{ 924 struct ieee80211com *ic = &sc->sc_ic; 925 uint32_t state; 926 927 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 928 929 state = le32toh(*mtod(sbuf->m, uint32_t *)); 930 931 DPRINTFN(2, ("entering state %u\n", state)); 932 933 switch (state) { 934 case IPW_STATE_ASSOCIATED: 935 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 936 break; 937 938 case IPW_STATE_SCANNING: 939 /* don't leave run state on background scan */ 940 if (ic->ic_state != IEEE80211_S_RUN) 941 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 942 943 ic->ic_flags |= IEEE80211_F_SCAN; 944 break; 945 946 case IPW_STATE_SCAN_COMPLETE: 947 ieee80211_notify_scan_done(ic); 948 ic->ic_flags &= ~IEEE80211_F_SCAN; 949 break; 950 951 case IPW_STATE_ASSOCIATION_LOST: 952 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 953 break; 954 955 case IPW_STATE_RADIO_DISABLED: 956 ic->ic_ifp->if_flags &= ~IFF_UP; 957 ipw_stop(sc); 958 break; 959 } 960} 961 962/* 963 * XXX: Hack to set the current channel to the value advertised in beacons or 964 * probe responses. Only used during AP detection. 965 */ 966static void 967ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 968{ 969 struct ieee80211_frame *wh; 970 uint8_t subtype; 971 uint8_t *frm, *efrm; 972 973 wh = mtod(m, struct ieee80211_frame *); 974 975 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 976 return; 977 978 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 979 980 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 981 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 982 return; 983 984 frm = (uint8_t *)(wh + 1); 985 efrm = mtod(m, uint8_t *) + m->m_len; 986 987 frm += 12; /* skip tstamp, bintval and capinfo fields */ 988 while (frm < efrm) { 989 if (*frm == IEEE80211_ELEMID_DSPARMS) 990#if IEEE80211_CHAN_MAX < 255 991 if (frm[2] <= IEEE80211_CHAN_MAX) 992#endif 993 ic->ic_curchan = &ic->ic_channels[frm[2]]; 994 995 frm += frm[1] + 2; 996 } 997} 998 999static void 1000ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1001 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1002{ 1003 struct ieee80211com *ic = &sc->sc_ic; 1004 struct ifnet *ifp = ic->ic_ifp; 1005 struct mbuf *mnew, *m; 1006 struct ieee80211_frame *wh; 1007 struct ieee80211_node *ni; 1008 bus_addr_t physaddr; 1009 int error; 1010 1011 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1012 status->rssi)); 1013 1014 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1015 le32toh(status->len) > MCLBYTES) 1016 return; 1017 1018 /* 1019 * Try to allocate a new mbuf for this ring element and load it before 1020 * processing the current mbuf. If the ring element cannot be loaded, 1021 * drop the received packet and reuse the old mbuf. In the unlikely 1022 * case that the old mbuf can't be reloaded either, explicitly panic. 1023 */ 1024 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1025 if (mnew == NULL) { 1026 ifp->if_ierrors++; 1027 return; 1028 } 1029 1030 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1031 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1032 1033 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(mnew, void *), 1034 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1035 if (error != 0) { 1036 m_freem(mnew); 1037 1038 /* try to reload the old mbuf */ 1039 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 1040 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 1041 &physaddr, 0); 1042 if (error != 0) { 1043 /* very unlikely that it will fail... */ 1044 panic("%s: could not load old rx mbuf", 1045 device_get_name(sc->sc_dev)); 1046 } 1047 ifp->if_ierrors++; 1048 return; 1049 } 1050 1051 /* 1052 * New mbuf successfully loaded, update Rx ring and continue 1053 * processing. 1054 */ 1055 m = sbuf->m; 1056 sbuf->m = mnew; 1057 sbd->bd->physaddr = htole32(physaddr); 1058 1059 /* finalize mbuf */ 1060 m->m_pkthdr.rcvif = ifp; 1061 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1062 1063 if (sc->sc_drvbpf != NULL) { 1064 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1065 1066 tap->wr_flags = 0; 1067 tap->wr_antsignal = status->rssi; 1068 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1069 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1070 1071 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1072 } 1073 1074 if (ic->ic_state == IEEE80211_S_SCAN) 1075 ipw_fix_channel(ic, m); 1076 1077 wh = mtod(m, struct ieee80211_frame *); 1078 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1079 1080 /* send the frame to the 802.11 layer */ 1081 ieee80211_input(ic, m, ni, status->rssi, 0); 1082 1083 /* node is no longer needed */ 1084 ieee80211_free_node(ni); 1085 1086 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1087} 1088 1089static void 1090ipw_rx_intr(struct ipw_softc *sc) 1091{ 1092 struct ipw_status *status; 1093 struct ipw_soft_bd *sbd; 1094 struct ipw_soft_buf *sbuf; 1095 uint32_t r, i; 1096 1097 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1098 return; 1099 1100 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1101 1102 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1103 1104 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1105 status = &sc->status_list[i]; 1106 sbd = &sc->srbd_list[i]; 1107 sbuf = sbd->priv; 1108 1109 switch (le16toh(status->code) & 0xf) { 1110 case IPW_STATUS_CODE_COMMAND: 1111 ipw_command_intr(sc, sbuf); 1112 break; 1113 1114 case IPW_STATUS_CODE_NEWSTATE: 1115 ipw_newstate_intr(sc, sbuf); 1116 break; 1117 1118 case IPW_STATUS_CODE_DATA_802_3: 1119 case IPW_STATUS_CODE_DATA_802_11: 1120 ipw_data_intr(sc, status, sbd, sbuf); 1121 break; 1122 1123 case IPW_STATUS_CODE_NOTIFICATION: 1124 DPRINTFN(2, ("received notification\n")); 1125 break; 1126 1127 default: 1128 device_printf(sc->sc_dev, "unknown status code %u\n", 1129 le16toh(status->code)); 1130 } 1131 1132 /* firmware was killed, stop processing received frames */ 1133 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1134 return; 1135 1136 sbd->bd->flags = 0; 1137 } 1138 1139 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1140 1141 /* kick the firmware */ 1142 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1143 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1144} 1145 1146static void 1147ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1148{ 1149 struct ipw_soft_hdr *shdr; 1150 struct ipw_soft_buf *sbuf; 1151 1152 switch (sbd->type) { 1153 case IPW_SBD_TYPE_COMMAND: 1154 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1155 BUS_DMASYNC_POSTWRITE); 1156 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1157 break; 1158 1159 case IPW_SBD_TYPE_HEADER: 1160 shdr = sbd->priv; 1161 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1162 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1163 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1164 break; 1165 1166 case IPW_SBD_TYPE_DATA: 1167 sbuf = sbd->priv; 1168 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1169 BUS_DMASYNC_POSTWRITE); 1170 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1171 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1172 1173 m_freem(sbuf->m); 1174 ieee80211_free_node(sbuf->ni); 1175 1176 sc->sc_tx_timer = 0; 1177 break; 1178 } 1179 1180 sbd->type = IPW_SBD_TYPE_NOASSOC; 1181} 1182 1183static void 1184ipw_tx_intr(struct ipw_softc *sc) 1185{ 1186 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1187 struct ipw_soft_bd *sbd; 1188 uint32_t r, i; 1189 1190 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1191 return; 1192 1193 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1194 1195 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1196 sbd = &sc->stbd_list[i]; 1197 1198 if (sbd->type == IPW_SBD_TYPE_DATA) 1199 ifp->if_opackets++; 1200 1201 ipw_release_sbd(sc, sbd); 1202 sc->txfree++; 1203 } 1204 1205 /* remember what the firmware has processed */ 1206 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1207 1208 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1209 ipw_start(ifp); 1210} 1211 1212static void 1213ipw_intr(void *arg) 1214{ 1215 struct ipw_softc *sc = arg; 1216 uint32_t r; 1217 1218 mtx_lock(&sc->sc_mtx); 1219 1220 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1221 mtx_unlock(&sc->sc_mtx); 1222 return; 1223 } 1224 1225 /* disable interrupts */ 1226 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1227 1228 /* acknowledge all interrupts */ 1229 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1230 1231 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1232 device_printf(sc->sc_dev, "firmware error\n"); 1233 taskqueue_enqueue_fast(taskqueue_fast, &sc->sc_init_task); 1234 r = 0; /* don't process more interrupts */ 1235 } 1236 1237 if (r & IPW_INTR_FW_INIT_DONE) 1238 wakeup(sc); 1239 1240 if (r & IPW_INTR_RX_TRANSFER) 1241 ipw_rx_intr(sc); 1242 1243 if (r & IPW_INTR_TX_TRANSFER) 1244 ipw_tx_intr(sc); 1245 1246 /* re-enable interrupts */ 1247 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1248 1249 mtx_unlock(&sc->sc_mtx); 1250} 1251 1252static void 1253ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1254{ 1255 if (error != 0) 1256 return; 1257 1258 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1259 1260 *(bus_addr_t *)arg = segs[0].ds_addr; 1261} 1262 1263/* 1264 * Send a command to the firmware and wait for the acknowledgement. 1265 */ 1266static int 1267ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1268{ 1269 struct ipw_soft_bd *sbd; 1270 bus_addr_t physaddr; 1271 int error; 1272 1273 sbd = &sc->stbd_list[sc->txcur]; 1274 1275 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1276 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1277 if (error != 0) { 1278 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1279 return error; 1280 } 1281 1282 sc->cmd.type = htole32(type); 1283 sc->cmd.subtype = 0; 1284 sc->cmd.len = htole32(len); 1285 sc->cmd.seq = 0; 1286 memcpy(sc->cmd.data, data, len); 1287 1288 sbd->type = IPW_SBD_TYPE_COMMAND; 1289 sbd->bd->physaddr = htole32(physaddr); 1290 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1291 sbd->bd->nfrag = 1; 1292 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1293 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1294 1295 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1296 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1297 1298 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1299 1300 /* kick firmware */ 1301 sc->txfree--; 1302 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1303 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1304 1305 /* wait at most one second for command to complete */ 1306 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1307} 1308 1309static int 1310ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1311{ 1312 struct ipw_softc *sc = ifp->if_softc; 1313 struct ieee80211com *ic = &sc->sc_ic; 1314 struct ieee80211_frame *wh; 1315 struct ipw_soft_bd *sbd; 1316 struct ipw_soft_hdr *shdr; 1317 struct ipw_soft_buf *sbuf; 1318 struct ieee80211_key *k; 1319 struct mbuf *mnew; 1320 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1321 bus_addr_t physaddr; 1322 int nsegs, error, i; 1323 1324 wh = mtod(m0, struct ieee80211_frame *); 1325 1326 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1327 k = ieee80211_crypto_encap(ic, ni, m0); 1328 if (k == NULL) { 1329 m_freem(m0); 1330 return ENOBUFS; 1331 } 1332 1333 /* packet header may have moved, reset our local pointer */ 1334 wh = mtod(m0, struct ieee80211_frame *); 1335 } 1336 1337 if (sc->sc_drvbpf != NULL) { 1338 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1339 1340 tap->wt_flags = 0; 1341 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1342 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1343 1344 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1345 } 1346 1347 shdr = SLIST_FIRST(&sc->free_shdr); 1348 sbuf = SLIST_FIRST(&sc->free_sbuf); 1349 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1350 1351 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1352 shdr->hdr.subtype = 0; 1353 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1354 shdr->hdr.encrypt = 0; 1355 shdr->hdr.keyidx = 0; 1356 shdr->hdr.keysz = 0; 1357 shdr->hdr.fragmentsz = 0; 1358 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1359 if (ic->ic_opmode == IEEE80211_M_STA) 1360 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1361 else 1362 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1363 1364 /* trim IEEE802.11 header */ 1365 m_adj(m0, sizeof (struct ieee80211_frame)); 1366 1367 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1368 &nsegs, 0); 1369 if (error != 0 && error != EFBIG) { 1370 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1371 error); 1372 m_freem(m0); 1373 return error; 1374 } 1375 if (error != 0) { 1376 mnew = m_defrag(m0, M_DONTWAIT); 1377 if (mnew == NULL) { 1378 device_printf(sc->sc_dev, 1379 "could not defragment mbuf\n"); 1380 m_freem(m0); 1381 return ENOBUFS; 1382 } 1383 m0 = mnew; 1384 1385 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1386 segs, &nsegs, 0); 1387 if (error != 0) { 1388 device_printf(sc->sc_dev, 1389 "could not map mbuf (error %d)\n", error); 1390 m_freem(m0); 1391 return error; 1392 } 1393 } 1394 1395 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1396 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1397 if (error != 0) { 1398 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1399 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1400 m_freem(m0); 1401 return error; 1402 } 1403 1404 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1405 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1406 1407 sbd = &sc->stbd_list[sc->txcur]; 1408 sbd->type = IPW_SBD_TYPE_HEADER; 1409 sbd->priv = shdr; 1410 sbd->bd->physaddr = htole32(physaddr); 1411 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1412 sbd->bd->nfrag = 1 + nsegs; 1413 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1414 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1415 1416 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1417 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1418 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1419 ":")); 1420 1421 sc->txfree--; 1422 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1423 1424 sbuf->m = m0; 1425 sbuf->ni = ni; 1426 1427 for (i = 0; i < nsegs; i++) { 1428 sbd = &sc->stbd_list[sc->txcur]; 1429 1430 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1431 sbd->bd->len = htole32(segs[i].ds_len); 1432 sbd->bd->nfrag = 0; 1433 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1434 if (i == nsegs - 1) { 1435 sbd->type = IPW_SBD_TYPE_DATA; 1436 sbd->priv = sbuf; 1437 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1438 } else { 1439 sbd->type = IPW_SBD_TYPE_NOASSOC; 1440 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1441 } 1442 1443 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1444 1445 sc->txfree--; 1446 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1447 } 1448 1449 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1450 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1451 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1452 1453 /* kick firmware */ 1454 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1455 1456 return 0; 1457} 1458 1459static void 1460ipw_start(struct ifnet *ifp) 1461{ 1462 struct ipw_softc *sc = ifp->if_softc; 1463 struct ieee80211com *ic = &sc->sc_ic; 1464 struct mbuf *m0; 1465 struct ether_header *eh; 1466 struct ieee80211_node *ni; 1467 1468 mtx_lock(&sc->sc_mtx); 1469 1470 if (ic->ic_state != IEEE80211_S_RUN) { 1471 mtx_unlock(&sc->sc_mtx); 1472 return; 1473 } 1474 1475 for (;;) { 1476 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1477 if (m0 == NULL) 1478 break; 1479 1480 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1481 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1482 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1483 break; 1484 } 1485 1486 if (m0->m_len < sizeof (struct ether_header) && 1487 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1488 continue; 1489 1490 eh = mtod(m0, struct ether_header *); 1491 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1492 if (ni == NULL) { 1493 m_freem(m0); 1494 continue; 1495 } 1496 BPF_MTAP(ifp, m0); 1497 1498 m0 = ieee80211_encap(ic, m0, ni); 1499 if (m0 == NULL) { 1500 ieee80211_free_node(ni); 1501 continue; 1502 } 1503 1504 if (ic->ic_rawbpf != NULL) 1505 bpf_mtap(ic->ic_rawbpf, m0); 1506 1507 if (ipw_tx_start(ifp, m0, ni) != 0) { 1508 ieee80211_free_node(ni); 1509 ifp->if_oerrors++; 1510 break; 1511 } 1512 1513 /* start watchdog timer */ 1514 sc->sc_tx_timer = 5; 1515 ifp->if_timer = 1; 1516 } 1517 1518 mtx_unlock(&sc->sc_mtx); 1519} 1520 1521static void 1522ipw_watchdog(struct ifnet *ifp) 1523{ 1524 struct ipw_softc *sc = ifp->if_softc; 1525 struct ieee80211com *ic = &sc->sc_ic; 1526 1527 mtx_lock(&sc->sc_mtx); 1528 1529 ifp->if_timer = 0; 1530 1531 if (sc->sc_tx_timer > 0) { 1532 if (--sc->sc_tx_timer == 0) { 1533 if_printf(ifp, "device timeout\n"); 1534 ifp->if_oerrors++; 1535 taskqueue_enqueue_fast(taskqueue_fast, 1536 &sc->sc_init_task); 1537 mtx_unlock(&sc->sc_mtx); 1538 return; 1539 } 1540 ifp->if_timer = 1; 1541 } 1542 1543 ieee80211_watchdog(ic); 1544 1545 mtx_unlock(&sc->sc_mtx); 1546} 1547 1548static int 1549ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1550{ 1551 struct ipw_softc *sc = ifp->if_softc; 1552 struct ieee80211com *ic = &sc->sc_ic; 1553 int error = 0; 1554 1555 mtx_lock(&sc->sc_mtx); 1556 1557 switch (cmd) { 1558 case SIOCSIFFLAGS: 1559 if (ifp->if_flags & IFF_UP) { 1560 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1561 ipw_init(sc); 1562 } else { 1563 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1564 ipw_stop(sc); 1565 } 1566 break; 1567 1568 default: 1569 error = ieee80211_ioctl(ic, cmd, data); 1570 } 1571 1572 if (error == ENETRESET) { 1573 if ((ifp->if_flags & IFF_UP) && 1574 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1575 ipw_init(sc); 1576 error = 0; 1577 } 1578 1579 mtx_unlock(&sc->sc_mtx); 1580 1581 return error; 1582} 1583 1584static void 1585ipw_stop_master(struct ipw_softc *sc) 1586{ 1587 uint32_t tmp; 1588 int ntries; 1589 1590 /* disable interrupts */ 1591 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1592 1593 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1594 for (ntries = 0; ntries < 50; ntries++) { 1595 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1596 break; 1597 DELAY(10); 1598 } 1599 if (ntries == 50) 1600 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1601 1602 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1603 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1604 1605 sc->flags &= ~IPW_FLAG_FW_INITED; 1606} 1607 1608static int 1609ipw_reset(struct ipw_softc *sc) 1610{ 1611 uint32_t tmp; 1612 int ntries; 1613 1614 ipw_stop_master(sc); 1615 1616 /* move adapter to D0 state */ 1617 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1618 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1619 1620 /* wait for clock stabilization */ 1621 for (ntries = 0; ntries < 1000; ntries++) { 1622 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1623 break; 1624 DELAY(200); 1625 } 1626 if (ntries == 1000) 1627 return EIO; 1628 1629 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1630 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1631 1632 DELAY(10); 1633 1634 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1635 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1636 1637 return 0; 1638} 1639 1640/* 1641 * Upload the microcode to the device. 1642 */ 1643static int 1644ipw_load_ucode(struct ipw_softc *sc, const char *uc, int size) 1645{ 1646 int ntries; 1647 1648 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1649 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1650 1651 MEM_WRITE_2(sc, 0x220000, 0x0703); 1652 MEM_WRITE_2(sc, 0x220000, 0x0707); 1653 1654 MEM_WRITE_1(sc, 0x210014, 0x72); 1655 MEM_WRITE_1(sc, 0x210014, 0x72); 1656 1657 MEM_WRITE_1(sc, 0x210000, 0x40); 1658 MEM_WRITE_1(sc, 0x210000, 0x00); 1659 MEM_WRITE_1(sc, 0x210000, 0x40); 1660 1661 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1662 1663 MEM_WRITE_1(sc, 0x210000, 0x00); 1664 MEM_WRITE_1(sc, 0x210000, 0x00); 1665 MEM_WRITE_1(sc, 0x210000, 0x80); 1666 1667 MEM_WRITE_2(sc, 0x220000, 0x0703); 1668 MEM_WRITE_2(sc, 0x220000, 0x0707); 1669 1670 MEM_WRITE_1(sc, 0x210014, 0x72); 1671 MEM_WRITE_1(sc, 0x210014, 0x72); 1672 1673 MEM_WRITE_1(sc, 0x210000, 0x00); 1674 MEM_WRITE_1(sc, 0x210000, 0x80); 1675 1676 for (ntries = 0; ntries < 10; ntries++) { 1677 if (MEM_READ_1(sc, 0x210000) & 1) 1678 break; 1679 DELAY(10); 1680 } 1681 if (ntries == 10) { 1682 device_printf(sc->sc_dev, 1683 "timeout waiting for ucode to initialize\n"); 1684 return EIO; 1685 } 1686 1687 MEM_WRITE_4(sc, 0x3000e0, 0); 1688 1689 return 0; 1690} 1691 1692/* set of macros to handle unaligned little endian data in firmware image */ 1693#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1694#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1695static int 1696ipw_load_firmware(struct ipw_softc *sc, const char *fw, int size) 1697{ 1698 const uint8_t *p, *end; 1699 uint32_t tmp, dst; 1700 uint16_t len; 1701 int error; 1702 1703 p = fw; 1704 end = fw + size; 1705 while (p < end) { 1706 dst = GETLE32(p); p += 4; 1707 len = GETLE16(p); p += 2; 1708 1709 ipw_write_mem_1(sc, dst, p, len); 1710 p += len; 1711 } 1712 1713 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1714 IPW_IO_LED_OFF); 1715 1716 /* enable interrupts */ 1717 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1718 1719 /* kick the firmware */ 1720 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1721 1722 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1723 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1724 1725 /* wait at most one second for firmware initialization to complete */ 1726 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1727 device_printf(sc->sc_dev, "timeout waiting for firmware " 1728 "initialization to complete\n"); 1729 return error; 1730 } 1731 1732 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1733 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1734 IPW_IO_GPIO3_MASK); 1735 1736 return 0; 1737} 1738 1739static int 1740ipw_config(struct ipw_softc *sc) 1741{ 1742 struct ieee80211com *ic = &sc->sc_ic; 1743 struct ifnet *ifp = ic->ic_ifp; 1744 struct ipw_security security; 1745 struct ieee80211_key *k; 1746 struct ipw_wep_key wepkey; 1747 struct ipw_scan_options options; 1748 struct ipw_configuration config; 1749 uint32_t data; 1750 int error, i; 1751 1752 switch (ic->ic_opmode) { 1753 case IEEE80211_M_STA: 1754 case IEEE80211_M_HOSTAP: 1755 data = htole32(IPW_MODE_BSS); 1756 break; 1757 case IEEE80211_M_IBSS: 1758 case IEEE80211_M_AHDEMO: 1759 data = htole32(IPW_MODE_IBSS); 1760 break; 1761 case IEEE80211_M_MONITOR: 1762 data = htole32(IPW_MODE_MONITOR); 1763 break; 1764 } 1765 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1766 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1767 if (error != 0) 1768 return error; 1769 1770 if (ic->ic_opmode == IEEE80211_M_IBSS || 1771 ic->ic_opmode == IEEE80211_M_MONITOR) { 1772 data = htole32(ieee80211_chan2ieee(ic, ic->ic_curchan)); 1773 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1774 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1775 if (error != 0) 1776 return error; 1777 } 1778 1779 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1780 DPRINTF(("Enabling adapter\n")); 1781 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1782 } 1783 1784 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1785 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1786 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1787 IEEE80211_ADDR_LEN); 1788 if (error != 0) 1789 return error; 1790 1791 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1792 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1793 if (ic->ic_opmode == IEEE80211_M_IBSS) 1794 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1795 if (ifp->if_flags & IFF_PROMISC) 1796 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1797 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1798 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1799 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1800 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1801 if (error != 0) 1802 return error; 1803 1804 data = htole32(0x3); /* 1, 2 */ 1805 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1806 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1807 if (error != 0) 1808 return error; 1809 1810 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1811 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1812 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1813 if (error != 0) 1814 return error; 1815 1816 data = htole32(IPW_POWER_MODE_CAM); 1817 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1818 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1819 if (error != 0) 1820 return error; 1821 1822 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1823 data = htole32(32); /* default value */ 1824 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1825 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1826 sizeof data); 1827 if (error != 0) 1828 return error; 1829 } 1830 1831 data = htole32(ic->ic_rtsthreshold); 1832 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1833 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1834 if (error != 0) 1835 return error; 1836 1837 data = htole32(ic->ic_fragthreshold); 1838 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1839 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1840 if (error != 0) 1841 return error; 1842 1843#ifdef IPW_DEBUG 1844 if (ipw_debug > 0) { 1845 printf("Setting ESSID to "); 1846 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1847 printf("\n"); 1848 } 1849#endif 1850 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1851 ic->ic_des_esslen); 1852 if (error != 0) 1853 return error; 1854 1855 /* no mandatory BSSID */ 1856 DPRINTF(("Setting mandatory BSSID to null\n")); 1857 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1858 if (error != 0) 1859 return error; 1860 1861 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1862 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1863 ":")); 1864 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1865 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1866 if (error != 0) 1867 return error; 1868 } 1869 1870 memset(&security, 0, sizeof security); 1871 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1872 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1873 security.ciphers = htole32(IPW_CIPHER_NONE); 1874 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1875 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1876 sizeof security); 1877 if (error != 0) 1878 return error; 1879 1880 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1881 k = ic->ic_crypto.cs_nw_keys; 1882 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1883 if (k->wk_keylen == 0) 1884 continue; 1885 1886 wepkey.idx = i; 1887 wepkey.len = k->wk_keylen; 1888 memset(wepkey.key, 0, sizeof wepkey.key); 1889 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 1890 DPRINTF(("Setting wep key index %u len %u\n", 1891 wepkey.idx, wepkey.len)); 1892 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1893 sizeof wepkey); 1894 if (error != 0) 1895 return error; 1896 } 1897 1898 data = htole32(ic->ic_crypto.cs_def_txkey); 1899 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1900 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1901 sizeof data); 1902 if (error != 0) 1903 return error; 1904 } 1905 1906 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1907 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1908 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1909 if (error != 0) 1910 return error; 1911 1912#if 0 1913 struct ipw_wpa_ie ie; 1914 1915 memset(&ie, 0, sizeof ie); 1916 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1917 DPRINTF(("Setting wpa ie\n")); 1918 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1919 if (error != 0) 1920 return error; 1921#endif 1922 1923 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1924 data = htole32(ic->ic_bintval); 1925 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1926 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1927 sizeof data); 1928 if (error != 0) 1929 return error; 1930 } 1931 1932 options.flags = 0; 1933 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1934 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 1935 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1936 if (error != 0) 1937 return error; 1938 1939 /* finally, enable adapter (start scanning for an access point) */ 1940 DPRINTF(("Enabling adapter\n")); 1941 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1942} 1943 1944/* 1945 * Handler for sc_init_task. This is a simple wrapper around ipw_init(). 1946 * It is called on firmware panics or on watchdog timeouts. 1947 */ 1948static void 1949ipw_init_task(void *context, int pending) 1950{ 1951 ipw_init(context); 1952} 1953 1954static void 1955ipw_init(void *priv) 1956{ 1957 struct ipw_softc *sc = priv; 1958 struct ieee80211com *ic = &sc->sc_ic; 1959 struct ifnet *ifp = ic->ic_ifp; 1960 struct firmware *fp; 1961 const struct ipw_firmware_hdr *hdr; 1962 const char *imagename, *fw; 1963 int owned; 1964 1965 /* 1966 * ipw_init() is exposed through ifp->if_init so it might be called 1967 * without the driver's lock held. Since msleep() doesn't like being 1968 * called on a recursed mutex, we acquire the driver's lock only if 1969 * we're not already holding it. 1970 */ 1971 if (!(owned = mtx_owned(&sc->sc_mtx))) 1972 mtx_lock(&sc->sc_mtx); 1973 1974 /* 1975 * Avoid re-entrant calls. We need to release the mutex in ipw_init() 1976 * when loading the firmware and we don't want to be called during this 1977 * operation. 1978 */ 1979 if (sc->flags & IPW_FLAG_INIT_LOCKED) { 1980 if (!owned) 1981 mtx_unlock(&sc->sc_mtx); 1982 return; 1983 } 1984 sc->flags |= IPW_FLAG_INIT_LOCKED; 1985 1986 ipw_stop(sc); 1987 1988 if (ipw_reset(sc) != 0) { 1989 device_printf(sc->sc_dev, "could not reset adapter\n"); 1990 goto fail1; 1991 } 1992 1993 switch (ic->ic_opmode) { 1994 case IEEE80211_M_STA: 1995 imagename = "ipw_bss"; 1996 break; 1997 case IEEE80211_M_IBSS: 1998 imagename = "ipw_ibss"; 1999 break; 2000 case IEEE80211_M_MONITOR: 2001 imagename = "ipw_monitor"; 2002 break; 2003 default: 2004 imagename = NULL; /* should not get there */ 2005 } 2006 2007 /* 2008 * Load firmware image using the firmware(9) subsystem. We need to 2009 * release the driver's lock first. 2010 */ 2011 mtx_unlock(&sc->sc_mtx); 2012 fp = firmware_get(imagename); 2013 mtx_lock(&sc->sc_mtx); 2014 2015 if (fp == NULL) { 2016 device_printf(sc->sc_dev, 2017 "could not load firmware image '%s'\n", imagename); 2018 goto fail1; 2019 } 2020 2021 if (fp->datasize < sizeof *hdr) { 2022 device_printf(sc->sc_dev, 2023 "firmware image too short %zu\n", fp->datasize); 2024 goto fail2; 2025 } 2026 2027 hdr = (const struct ipw_firmware_hdr *)fp->data; 2028 2029 if (fp->datasize < sizeof *hdr + le32toh(hdr->mainsz) + 2030 le32toh(hdr->ucodesz)) { 2031 device_printf(sc->sc_dev, 2032 "firmware image too short %zu\n", fp->datasize); 2033 goto fail2; 2034 } 2035 2036 fw = (const char *)fp->data + sizeof *hdr + le32toh(hdr->mainsz); 2037 if (ipw_load_ucode(sc, fw, le32toh(hdr->ucodesz)) != 0) { 2038 device_printf(sc->sc_dev, "could not load microcode\n"); 2039 goto fail2; 2040 } 2041 2042 ipw_stop_master(sc); 2043 2044 /* 2045 * Setup tx, rx and status rings. 2046 */ 2047 sc->txold = IPW_NTBD - 1; 2048 sc->txcur = 0; 2049 sc->txfree = IPW_NTBD - 2; 2050 sc->rxcur = IPW_NRBD - 1; 2051 2052 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2053 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2054 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2055 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2056 2057 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2058 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2059 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2060 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2061 2062 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2063 2064 fw = (const char *)fp->data + sizeof *hdr; 2065 if (ipw_load_firmware(sc, fw, le32toh(hdr->mainsz)) != 0) { 2066 device_printf(sc->sc_dev, "could not load firmware\n"); 2067 goto fail2; 2068 } 2069 2070 firmware_put(fp, FIRMWARE_UNLOAD); 2071 sc->flags |= IPW_FLAG_FW_INITED; 2072 2073 /* retrieve information tables base addresses */ 2074 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2075 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2076 2077 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2078 2079 if (ipw_config(sc) != 0) { 2080 device_printf(sc->sc_dev, "device configuration failed\n"); 2081 goto fail1; 2082 } 2083 2084 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2085 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2086 2087 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2088 2089 if (!owned) 2090 mtx_unlock(&sc->sc_mtx); 2091 2092 return; 2093 2094fail2: firmware_put(fp, FIRMWARE_UNLOAD); 2095fail1: ifp->if_flags &= ~IFF_UP; 2096 ipw_stop(sc); 2097 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2098 if (!owned) 2099 mtx_unlock(&sc->sc_mtx); 2100} 2101 2102static void 2103ipw_stop(void *priv) 2104{ 2105 struct ipw_softc *sc = priv; 2106 struct ieee80211com *ic = &sc->sc_ic; 2107 struct ifnet *ifp = ic->ic_ifp; 2108 int i; 2109 2110 mtx_lock(&sc->sc_mtx); 2111 2112 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2113 2114 ipw_stop_master(sc); 2115 2116 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2117 2118 /* 2119 * Release tx buffers. 2120 */ 2121 for (i = 0; i < IPW_NTBD; i++) 2122 ipw_release_sbd(sc, &sc->stbd_list[i]); 2123 2124 sc->sc_tx_timer = 0; 2125 ifp->if_timer = 0; 2126 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2127 2128 mtx_unlock(&sc->sc_mtx); 2129} 2130 2131static int 2132ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2133{ 2134 struct ipw_softc *sc = arg1; 2135 uint32_t i, size, buf[256]; 2136 2137 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2138 memset(buf, 0, sizeof buf); 2139 return SYSCTL_OUT(req, buf, sizeof buf); 2140 } 2141 2142 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2143 2144 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2145 for (i = 1; i < size; i++) 2146 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2147 2148 return SYSCTL_OUT(req, buf, sizeof buf); 2149} 2150 2151static int 2152ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2153{ 2154 struct ipw_softc *sc = arg1; 2155 int val; 2156 2157 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2158 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2159 2160 return SYSCTL_OUT(req, &val, sizeof val); 2161} 2162 2163static uint32_t 2164ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2165{ 2166 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2167} 2168 2169static void 2170ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2171{ 2172 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2173} 2174 2175static int 2176ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2177{ 2178 uint32_t addr, info; 2179 uint16_t count, size; 2180 uint32_t total; 2181 2182 /* addr[4] + count[2] + size[2] */ 2183 addr = MEM_READ_4(sc, sc->table2_base + off); 2184 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2185 2186 count = info >> 16; 2187 size = info & 0xffff; 2188 total = count * size; 2189 2190 if (total > *len) { 2191 *len = total; 2192 return EINVAL; 2193 } 2194 2195 *len = total; 2196 ipw_read_mem_1(sc, addr, buf, total); 2197 2198 return 0; 2199} 2200 2201static void 2202ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2203 bus_size_t count) 2204{ 2205 for (; count > 0; offset++, datap++, count--) { 2206 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2207 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2208 } 2209} 2210 2211static void 2212ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, const uint8_t *datap, 2213 bus_size_t count) 2214{ 2215 for (; count > 0; offset++, datap++, count--) { 2216 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2217 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2218 } 2219} 2220