1/*- 2 * Copyright (c) 1998, 1999 Takanori Watanabe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/dev/intpm/intpm.c 349205 2019-06-19 20:03:02Z avg $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/rman.h> 38#include <machine/bus.h> 39#include <dev/smbus/smbconf.h> 40 41#include "smbus_if.h" 42 43#include <dev/pci/pcireg.h> 44#include <dev/pci/pcivar.h> 45#include <dev/intpm/intpmreg.h> 46#include <dev/amdsbwd/amd_chipset.h> 47 48#include "opt_intpm.h" 49 50struct intsmb_softc { 51 device_t dev; 52 struct resource *io_res; 53 struct resource *irq_res; 54 void *irq_hand; 55 device_t smbus; 56 int io_rid; 57 int isbusy; 58 int cfg_irq9; 59 int sb8xx; 60 int poll; 61 struct mtx lock; 62}; 63 64#define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock) 65#define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock) 66#define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED) 67 68static int intsmb_probe(device_t); 69static int intsmb_attach(device_t); 70static int intsmb_detach(device_t); 71static int intsmb_intr(struct intsmb_softc *sc); 72static int intsmb_slvintr(struct intsmb_softc *sc); 73static void intsmb_alrintr(struct intsmb_softc *sc); 74static int intsmb_callback(device_t dev, int index, void *data); 75static int intsmb_quick(device_t dev, u_char slave, int how); 76static int intsmb_sendb(device_t dev, u_char slave, char byte); 77static int intsmb_recvb(device_t dev, u_char slave, char *byte); 78static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte); 79static int intsmb_writew(device_t dev, u_char slave, char cmd, short word); 80static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte); 81static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word); 82static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata); 83static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf); 84static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf); 85static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr); 86static int intsmb_stop(struct intsmb_softc *sc); 87static int intsmb_stop_poll(struct intsmb_softc *sc); 88static int intsmb_free(struct intsmb_softc *sc); 89static void intsmb_rawintr(void *arg); 90 91static int 92intsmb_probe(device_t dev) 93{ 94 95 switch (pci_get_devid(dev)) { 96 case 0x71138086: /* Intel 82371AB */ 97 case 0x719b8086: /* Intel 82443MX */ 98#if 0 99 /* Not a good idea yet, this stops isab0 functioning */ 100 case 0x02001166: /* ServerWorks OSB4 */ 101#endif 102 device_set_desc(dev, "Intel PIIX4 SMBUS Interface"); 103 break; 104 case 0x43721002: 105 device_set_desc(dev, "ATI IXP400 SMBus Controller"); 106 break; 107 case AMDSB_SMBUS_DEVID: 108 device_set_desc(dev, "AMD SB600/7xx/8xx/9xx SMBus Controller"); 109 break; 110 case AMDFCH_SMBUS_DEVID: /* AMD FCH */ 111 case AMDCZ_SMBUS_DEVID: /* AMD Carizzo FCH */ 112 device_set_desc(dev, "AMD FCH SMBus Controller"); 113 break; 114 default: 115 return (ENXIO); 116 } 117 118 return (BUS_PROBE_DEFAULT); 119} 120 121static uint8_t 122amd_pmio_read(struct resource *res, uint8_t reg) 123{ 124 bus_write_1(res, 0, reg); /* Index */ 125 return (bus_read_1(res, 1)); /* Data */ 126} 127 128static int 129sb8xx_attach(device_t dev) 130{ 131 static const int AMDSB_SMBIO_WIDTH = 0x14; 132 struct intsmb_softc *sc; 133 struct resource *res; 134 uint32_t devid; 135 uint8_t revid; 136 uint16_t addr; 137 int rid; 138 int rc; 139 bool enabled; 140 141 sc = device_get_softc(dev); 142 rid = 0; 143 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX, 144 AMDSB_PMIO_WIDTH); 145 if (rc != 0) { 146 device_printf(dev, "bus_set_resource for PM IO failed\n"); 147 return (ENXIO); 148 } 149 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 150 RF_ACTIVE); 151 if (res == NULL) { 152 device_printf(dev, "bus_alloc_resource for PM IO failed\n"); 153 return (ENXIO); 154 } 155 156 devid = pci_get_devid(dev); 157 revid = pci_get_revid(dev); 158 if (devid == AMDSB_SMBUS_DEVID || 159 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 160 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) { 161 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1); 162 addr <<= 8; 163 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN); 164 enabled = (addr & AMDSB8_SMBUS_EN) != 0; 165 addr &= AMDSB8_SMBUS_ADDR_MASK; 166 } else { 167 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0); 168 enabled = (addr & AMDFCH41_SMBUS_EN) != 0; 169 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1); 170 addr <<= 8; 171 } 172 173 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 174 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 175 176 if (!enabled) { 177 device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n"); 178 return (ENXIO); 179 } 180 181 sc->io_rid = 0; 182 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr, 183 AMDSB_SMBIO_WIDTH); 184 if (rc != 0) { 185 device_printf(dev, "bus_set_resource for SMBus IO failed\n"); 186 return (ENXIO); 187 } 188 if (res == NULL) { 189 device_printf(dev, "bus_alloc_resource for SMBus IO failed\n"); 190 return (ENXIO); 191 } 192 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid, 193 RF_ACTIVE); 194 sc->poll = 1; 195 return (0); 196} 197 198static void 199intsmb_release_resources(device_t dev) 200{ 201 struct intsmb_softc *sc = device_get_softc(dev); 202 203 if (sc->smbus) 204 device_delete_child(dev, sc->smbus); 205 if (sc->irq_hand) 206 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand); 207 if (sc->irq_res) 208 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 209 if (sc->io_res) 210 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 211 sc->io_res); 212 mtx_destroy(&sc->lock); 213} 214 215static int 216intsmb_attach(device_t dev) 217{ 218 struct intsmb_softc *sc = device_get_softc(dev); 219 int error, rid, value; 220 int intr; 221 char *str; 222 223 sc->dev = dev; 224 225 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF); 226 227 sc->cfg_irq9 = 0; 228 switch (pci_get_devid(dev)) { 229#ifndef NO_CHANGE_PCICONF 230 case 0x71138086: /* Intel 82371AB */ 231 case 0x719b8086: /* Intel 82443MX */ 232 /* Changing configuration is allowed. */ 233 sc->cfg_irq9 = 1; 234 break; 235#endif 236 case AMDSB_SMBUS_DEVID: 237 if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID) 238 sc->sb8xx = 1; 239 break; 240 case AMDFCH_SMBUS_DEVID: 241 case AMDCZ_SMBUS_DEVID: 242 sc->sb8xx = 1; 243 break; 244 } 245 246 if (sc->sb8xx) { 247 error = sb8xx_attach(dev); 248 if (error != 0) 249 goto fail; 250 else 251 goto no_intr; 252 } 253 254 sc->io_rid = PCI_BASE_ADDR_SMB; 255 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid, 256 RF_ACTIVE); 257 if (sc->io_res == NULL) { 258 device_printf(dev, "Could not allocate I/O space\n"); 259 error = ENXIO; 260 goto fail; 261 } 262 263 if (sc->cfg_irq9) { 264 pci_write_config(dev, PCIR_INTLINE, 0x9, 1); 265 pci_write_config(dev, PCI_HST_CFG_SMB, 266 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1); 267 } 268 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1); 269 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0; 270 intr = value & PCI_INTR_SMB_MASK; 271 switch (intr) { 272 case PCI_INTR_SMB_SMI: 273 str = "SMI"; 274 break; 275 case PCI_INTR_SMB_IRQ9: 276 str = "IRQ 9"; 277 break; 278 case PCI_INTR_SMB_IRQ_PCI: 279 str = "PCI IRQ"; 280 break; 281 default: 282 str = "BOGUS"; 283 } 284 285 device_printf(dev, "intr %s %s ", str, 286 sc->poll == 0 ? "enabled" : "disabled"); 287 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1)); 288 289 if (!sc->poll && intr == PCI_INTR_SMB_SMI) { 290 device_printf(dev, 291 "using polling mode when configured interrupt is SMI\n"); 292 sc->poll = 1; 293 } 294 295 if (sc->poll) 296 goto no_intr; 297 298 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) { 299 device_printf(dev, "Unsupported interrupt mode\n"); 300 error = ENXIO; 301 goto fail; 302 } 303 304 /* Force IRQ 9. */ 305 rid = 0; 306 if (sc->cfg_irq9) 307 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1); 308 309 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 310 RF_SHAREABLE | RF_ACTIVE); 311 if (sc->irq_res == NULL) { 312 device_printf(dev, "Could not allocate irq\n"); 313 error = ENXIO; 314 goto fail; 315 } 316 317 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 318 NULL, intsmb_rawintr, sc, &sc->irq_hand); 319 if (error) { 320 device_printf(dev, "Failed to map intr\n"); 321 goto fail; 322 } 323 324no_intr: 325 sc->isbusy = 0; 326 sc->smbus = device_add_child(dev, "smbus", -1); 327 if (sc->smbus == NULL) { 328 device_printf(dev, "failed to add smbus child\n"); 329 error = ENXIO; 330 goto fail; 331 } 332 error = device_probe_and_attach(sc->smbus); 333 if (error) { 334 device_printf(dev, "failed to probe+attach smbus child\n"); 335 goto fail; 336 } 337 338#ifdef ENABLE_ALART 339 /* Enable Arart */ 340 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); 341#endif 342 return (0); 343 344fail: 345 intsmb_release_resources(dev); 346 return (error); 347} 348 349static int 350intsmb_detach(device_t dev) 351{ 352 int error; 353 354 error = bus_generic_detach(dev); 355 if (error) { 356 device_printf(dev, "bus detach failed\n"); 357 return (error); 358 } 359 360 intsmb_release_resources(dev); 361 return (0); 362} 363 364static void 365intsmb_rawintr(void *arg) 366{ 367 struct intsmb_softc *sc = arg; 368 369 INTSMB_LOCK(sc); 370 intsmb_intr(sc); 371 intsmb_slvintr(sc); 372 INTSMB_UNLOCK(sc); 373} 374 375static int 376intsmb_callback(device_t dev, int index, void *data) 377{ 378 int error = 0; 379 380 switch (index) { 381 case SMB_REQUEST_BUS: 382 break; 383 case SMB_RELEASE_BUS: 384 break; 385 default: 386 error = SMB_EINVAL; 387 } 388 389 return (error); 390} 391 392/* Counterpart of smbtx_smb_free(). */ 393static int 394intsmb_free(struct intsmb_softc *sc) 395{ 396 397 INTSMB_LOCK_ASSERT(sc); 398 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) || 399#ifdef ENABLE_ALART 400 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) || 401#endif 402 sc->isbusy) 403 return (SMB_EBUSY); 404 405 sc->isbusy = 1; 406 /* Disable Interrupt in slave part. */ 407#ifndef ENABLE_ALART 408 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0); 409#endif 410 /* Reset INTR Flag to prepare INTR. */ 411 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS, 412 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR | 413 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL); 414 return (0); 415} 416 417static int 418intsmb_intr(struct intsmb_softc *sc) 419{ 420 int status, tmp; 421 422 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); 423 if (status & PIIX4_SMBHSTSTAT_BUSY) 424 return (1); 425 426 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR | 427 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) { 428 429 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 430 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, 431 tmp & ~PIIX4_SMBHSTCNT_INTREN); 432 if (sc->isbusy) { 433 sc->isbusy = 0; 434 wakeup(sc); 435 } 436 return (0); 437 } 438 return (1); /* Not Completed */ 439} 440 441static int 442intsmb_slvintr(struct intsmb_softc *sc) 443{ 444 int status; 445 446 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS); 447 if (status & PIIX4_SMBSLVSTS_BUSY) 448 return (1); 449 if (status & PIIX4_SMBSLVSTS_ALART) 450 intsmb_alrintr(sc); 451 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 452 | PIIX4_SMBSLVSTS_SDW1)) { 453 } 454 455 /* Reset Status Register */ 456 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS, 457 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 | 458 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV); 459 return (0); 460} 461 462static void 463intsmb_alrintr(struct intsmb_softc *sc) 464{ 465 int slvcnt; 466#ifdef ENABLE_ALART 467 int error; 468 uint8_t addr; 469#endif 470 471 /* Stop generating INTR from ALART. */ 472 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT); 473#ifdef ENABLE_ALART 474 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 475 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN); 476#endif 477 DELAY(5); 478 479 /* Ask bus who asserted it and then ask it what's the matter. */ 480#ifdef ENABLE_ALART 481 error = intsmb_free(sc); 482 if (error) 483 return; 484 485 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB); 486 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1); 487 error = intsmb_stop_poll(sc); 488 if (error) 489 device_printf(sc->dev, "ALART: ERROR\n"); 490 else { 491 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 492 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr); 493 } 494 495 /* Re-enable INTR from ALART. */ 496 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 497 slvcnt | PIIX4_SMBSLVCNT_ALTEN); 498 DELAY(5); 499#endif 500} 501 502static void 503intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr) 504{ 505 unsigned char tmp; 506 507 INTSMB_LOCK_ASSERT(sc); 508 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 509 tmp &= 0xe0; 510 tmp |= cmd; 511 tmp |= PIIX4_SMBHSTCNT_START; 512 513 /* While not in autoconfiguration enable interrupts. */ 514 if (!sc->poll && !cold && !nointr) 515 tmp |= PIIX4_SMBHSTCNT_INTREN; 516 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp); 517} 518 519static int 520intsmb_error(device_t dev, int status) 521{ 522 int error = 0; 523 524 /* 525 * PIIX4_SMBHSTSTAT_ERR can mean either of 526 * - SMB_ENOACK ("Unclaimed cycle"), 527 * - SMB_ETIMEOUT ("Host device time-out"), 528 * - SMB_EINVAL ("Illegal command field"). 529 * SMB_ENOACK seems to be most typical. 530 */ 531 if (status & PIIX4_SMBHSTSTAT_ERR) 532 error |= SMB_ENOACK; 533 if (status & PIIX4_SMBHSTSTAT_BUSC) 534 error |= SMB_ECOLLI; 535 if (status & PIIX4_SMBHSTSTAT_FAIL) 536 error |= SMB_EABORT; 537 538 if (error != 0 && bootverbose) 539 device_printf(dev, "error = %d, status = %#x\n", error, status); 540 541 return (error); 542} 543 544/* 545 * Polling Code. 546 * 547 * Polling is not encouraged because it requires waiting for the 548 * device if it is busy. 549 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use 550 * polling code then. 551 */ 552static int 553intsmb_stop_poll(struct intsmb_softc *sc) 554{ 555 int error, i, status, tmp; 556 557 INTSMB_LOCK_ASSERT(sc); 558 559 /* First, wait for busy to be set. */ 560 for (i = 0; i < 0x7fff; i++) 561 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & 562 PIIX4_SMBHSTSTAT_BUSY) 563 break; 564 565 /* Wait for busy to clear. */ 566 for (i = 0; i < 0x7fff; i++) { 567 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); 568 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) { 569 sc->isbusy = 0; 570 error = intsmb_error(sc->dev, status); 571 return (error); 572 } 573 } 574 575 /* Timed out waiting for busy to clear. */ 576 sc->isbusy = 0; 577 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 578 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN); 579 return (SMB_ETIMEOUT); 580} 581 582/* 583 * Wait for completion and return result. 584 */ 585static int 586intsmb_stop(struct intsmb_softc *sc) 587{ 588 int error, status; 589 590 INTSMB_LOCK_ASSERT(sc); 591 592 if (sc->poll || cold) 593 /* So that it can use device during device probe on SMBus. */ 594 return (intsmb_stop_poll(sc)); 595 596 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8); 597 if (error == 0) { 598 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); 599 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) { 600 error = intsmb_error(sc->dev, status); 601 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR)) 602 device_printf(sc->dev, "unknown cause why?\n"); 603#ifdef ENABLE_ALART 604 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 605 PIIX4_SMBSLVCNT_ALTEN); 606#endif 607 return (error); 608 } 609 } 610 611 /* Timeout Procedure. */ 612 sc->isbusy = 0; 613 614 /* Re-enable suppressed interrupt from slave part. */ 615 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); 616 if (error == EWOULDBLOCK) 617 return (SMB_ETIMEOUT); 618 else 619 return (SMB_EABORT); 620} 621 622static int 623intsmb_quick(device_t dev, u_char slave, int how) 624{ 625 struct intsmb_softc *sc = device_get_softc(dev); 626 int error; 627 u_char data; 628 629 data = slave; 630 631 /* Quick command is part of Address, I think. */ 632 switch(how) { 633 case SMB_QWRITE: 634 data &= ~LSB; 635 break; 636 case SMB_QREAD: 637 data |= LSB; 638 break; 639 default: 640 return (SMB_EINVAL); 641 } 642 643 INTSMB_LOCK(sc); 644 error = intsmb_free(sc); 645 if (error) { 646 INTSMB_UNLOCK(sc); 647 return (error); 648 } 649 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data); 650 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0); 651 error = intsmb_stop(sc); 652 INTSMB_UNLOCK(sc); 653 return (error); 654} 655 656static int 657intsmb_sendb(device_t dev, u_char slave, char byte) 658{ 659 struct intsmb_softc *sc = device_get_softc(dev); 660 int error; 661 662 INTSMB_LOCK(sc); 663 error = intsmb_free(sc); 664 if (error) { 665 INTSMB_UNLOCK(sc); 666 return (error); 667 } 668 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 669 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte); 670 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0); 671 error = intsmb_stop(sc); 672 INTSMB_UNLOCK(sc); 673 return (error); 674} 675 676static int 677intsmb_recvb(device_t dev, u_char slave, char *byte) 678{ 679 struct intsmb_softc *sc = device_get_softc(dev); 680 int error; 681 682 INTSMB_LOCK(sc); 683 error = intsmb_free(sc); 684 if (error) { 685 INTSMB_UNLOCK(sc); 686 return (error); 687 } 688 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 689 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0); 690 error = intsmb_stop(sc); 691 if (error == 0) { 692#ifdef RECV_IS_IN_CMD 693 /* 694 * Linux SMBus stuff also troubles 695 * Because Intel's datasheet does not make clear. 696 */ 697 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD); 698#else 699 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 700#endif 701 } 702 INTSMB_UNLOCK(sc); 703 return (error); 704} 705 706static int 707intsmb_writeb(device_t dev, u_char slave, char cmd, char byte) 708{ 709 struct intsmb_softc *sc = device_get_softc(dev); 710 int error; 711 712 INTSMB_LOCK(sc); 713 error = intsmb_free(sc); 714 if (error) { 715 INTSMB_UNLOCK(sc); 716 return (error); 717 } 718 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 719 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 720 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte); 721 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0); 722 error = intsmb_stop(sc); 723 INTSMB_UNLOCK(sc); 724 return (error); 725} 726 727static int 728intsmb_writew(device_t dev, u_char slave, char cmd, short word) 729{ 730 struct intsmb_softc *sc = device_get_softc(dev); 731 int error; 732 733 INTSMB_LOCK(sc); 734 error = intsmb_free(sc); 735 if (error) { 736 INTSMB_UNLOCK(sc); 737 return (error); 738 } 739 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 740 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 741 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff); 742 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff); 743 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); 744 error = intsmb_stop(sc); 745 INTSMB_UNLOCK(sc); 746 return (error); 747} 748 749static int 750intsmb_readb(device_t dev, u_char slave, char cmd, char *byte) 751{ 752 struct intsmb_softc *sc = device_get_softc(dev); 753 int error; 754 755 INTSMB_LOCK(sc); 756 error = intsmb_free(sc); 757 if (error) { 758 INTSMB_UNLOCK(sc); 759 return (error); 760 } 761 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 762 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 763 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0); 764 error = intsmb_stop(sc); 765 if (error == 0) 766 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 767 INTSMB_UNLOCK(sc); 768 return (error); 769} 770 771static int 772intsmb_readw(device_t dev, u_char slave, char cmd, short *word) 773{ 774 struct intsmb_softc *sc = device_get_softc(dev); 775 int error; 776 777 INTSMB_LOCK(sc); 778 error = intsmb_free(sc); 779 if (error) { 780 INTSMB_UNLOCK(sc); 781 return (error); 782 } 783 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 784 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 785 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); 786 error = intsmb_stop(sc); 787 if (error == 0) { 788 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 789 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8; 790 } 791 INTSMB_UNLOCK(sc); 792 return (error); 793} 794 795static int 796intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) 797{ 798 799 return (SMB_ENOTSUPP); 800} 801 802static int 803intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) 804{ 805 struct intsmb_softc *sc = device_get_softc(dev); 806 int error, i; 807 808 if (count > SMBBLOCKTRANS_MAX || count == 0) 809 return (SMB_EINVAL); 810 811 INTSMB_LOCK(sc); 812 error = intsmb_free(sc); 813 if (error) { 814 INTSMB_UNLOCK(sc); 815 return (error); 816 } 817 818 /* Reset internal array index. */ 819 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 820 821 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 822 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 823 for (i = 0; i < count; i++) 824 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]); 825 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count); 826 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0); 827 error = intsmb_stop(sc); 828 INTSMB_UNLOCK(sc); 829 return (error); 830} 831 832static int 833intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) 834{ 835 struct intsmb_softc *sc = device_get_softc(dev); 836 int error, i; 837 u_char data, nread; 838 839 INTSMB_LOCK(sc); 840 error = intsmb_free(sc); 841 if (error) { 842 INTSMB_UNLOCK(sc); 843 return (error); 844 } 845 846 /* Reset internal array index. */ 847 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 848 849 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 850 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 851 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0); 852 error = intsmb_stop(sc); 853 if (error == 0) { 854 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 855 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) { 856 *count = nread; 857 for (i = 0; i < nread; i++) 858 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT); 859 } else 860 error = SMB_EBUSERR; 861 } 862 INTSMB_UNLOCK(sc); 863 return (error); 864} 865 866static devclass_t intsmb_devclass; 867 868static device_method_t intsmb_methods[] = { 869 /* Device interface */ 870 DEVMETHOD(device_probe, intsmb_probe), 871 DEVMETHOD(device_attach, intsmb_attach), 872 DEVMETHOD(device_detach, intsmb_detach), 873 874 /* SMBus interface */ 875 DEVMETHOD(smbus_callback, intsmb_callback), 876 DEVMETHOD(smbus_quick, intsmb_quick), 877 DEVMETHOD(smbus_sendb, intsmb_sendb), 878 DEVMETHOD(smbus_recvb, intsmb_recvb), 879 DEVMETHOD(smbus_writeb, intsmb_writeb), 880 DEVMETHOD(smbus_writew, intsmb_writew), 881 DEVMETHOD(smbus_readb, intsmb_readb), 882 DEVMETHOD(smbus_readw, intsmb_readw), 883 DEVMETHOD(smbus_pcall, intsmb_pcall), 884 DEVMETHOD(smbus_bwrite, intsmb_bwrite), 885 DEVMETHOD(smbus_bread, intsmb_bread), 886 887 DEVMETHOD_END 888}; 889 890static driver_t intsmb_driver = { 891 "intsmb", 892 intsmb_methods, 893 sizeof(struct intsmb_softc), 894}; 895 896DRIVER_MODULE_ORDERED(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0, 897 SI_ORDER_ANY); 898DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0); 899MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 900MODULE_VERSION(intsmb, 1); 901