1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/dev/hwpmc/hwpmc_core.c 355094 2019-11-25 16:46:41Z kib $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/smp.h> 39#include <sys/systm.h> 40 41#include <machine/intr_machdep.h> 42#include <x86/apicvar.h> 43#include <machine/cpu.h> 44#include <machine/cpufunc.h> 45#include <machine/md_var.h> 46#include <machine/specialreg.h> 47 48#define CORE_CPUID_REQUEST 0xA 49#define CORE_CPUID_REQUEST_SIZE 0x4 50#define CORE_CPUID_EAX 0x0 51#define CORE_CPUID_EBX 0x1 52#define CORE_CPUID_ECX 0x2 53#define CORE_CPUID_EDX 0x3 54 55#define IAF_PMC_CAPS \ 56 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 57 PMC_CAP_USER | PMC_CAP_SYSTEM) 58#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 59 60#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 61 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 62 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 63 64#define EV_IS_NOTARCH 0 65#define EV_IS_ARCH_SUPP 1 66#define EV_IS_ARCH_NOTSUPP -1 67 68/* 69 * "Architectural" events defined by Intel. The values of these 70 * symbols correspond to positions in the bitmask returned by 71 * the CPUID.0AH instruction. 72 */ 73enum core_arch_events { 74 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 75 CORE_AE_BRANCH_MISSES_RETIRED = 6, 76 CORE_AE_INSTRUCTION_RETIRED = 1, 77 CORE_AE_LLC_MISSES = 4, 78 CORE_AE_LLC_REFERENCE = 3, 79 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 80 CORE_AE_UNHALTED_CORE_CYCLES = 0 81}; 82 83static enum pmc_cputype core_cputype; 84 85struct core_cpu { 86 volatile uint32_t pc_resync; 87 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 88 volatile uint64_t pc_globalctrl; /* Global control register. */ 89 struct pmc_hw pc_corepmcs[]; 90}; 91 92static struct core_cpu **core_pcpu; 93 94static uint32_t core_architectural_events; 95static uint64_t core_pmcmask; 96 97static int core_iaf_ri; /* relative index of fixed counters */ 98static int core_iaf_width; 99static int core_iaf_npmc; 100 101static int core_iap_width; 102static int core_iap_npmc; 103static int core_iap_wroffset; 104 105static u_int pmc_alloc_refs; 106static bool pmc_tsx_force_abort_set; 107 108static int 109core_pcpu_noop(struct pmc_mdep *md, int cpu) 110{ 111 (void) md; 112 (void) cpu; 113 return (0); 114} 115 116static int 117core_pcpu_init(struct pmc_mdep *md, int cpu) 118{ 119 struct pmc_cpu *pc; 120 struct core_cpu *cc; 121 struct pmc_hw *phw; 122 int core_ri, n, npmc; 123 124 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 125 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 126 127 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 128 129 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 130 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 131 132 if (core_cputype != PMC_CPU_INTEL_CORE) 133 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 134 135 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 136 M_PMC, M_WAITOK | M_ZERO); 137 138 core_pcpu[cpu] = cc; 139 pc = pmc_pcpu[cpu]; 140 141 KASSERT(pc != NULL && cc != NULL, 142 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 143 144 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 145 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 146 PMC_PHW_CPU_TO_STATE(cpu) | 147 PMC_PHW_INDEX_TO_STATE(n + core_ri); 148 phw->phw_pmc = NULL; 149 pc->pc_hwpmcs[n + core_ri] = phw; 150 } 151 152 return (0); 153} 154 155static int 156core_pcpu_fini(struct pmc_mdep *md, int cpu) 157{ 158 int core_ri, n, npmc; 159 struct pmc_cpu *pc; 160 struct core_cpu *cc; 161 uint64_t msr = 0; 162 163 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 164 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 165 166 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 167 168 if ((cc = core_pcpu[cpu]) == NULL) 169 return (0); 170 171 core_pcpu[cpu] = NULL; 172 173 pc = pmc_pcpu[cpu]; 174 175 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 176 cpu)); 177 178 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 179 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 180 181 for (n = 0; n < npmc; n++) { 182 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 183 wrmsr(IAP_EVSEL0 + n, msr); 184 } 185 186 if (core_cputype != PMC_CPU_INTEL_CORE) { 187 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 188 wrmsr(IAF_CTRL, msr); 189 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 190 } 191 192 for (n = 0; n < npmc; n++) 193 pc->pc_hwpmcs[n + core_ri] = NULL; 194 195 free(cc, M_PMC); 196 197 return (0); 198} 199 200/* 201 * Fixed function counters. 202 */ 203 204static pmc_value_t 205iaf_perfctr_value_to_reload_count(pmc_value_t v) 206{ 207 208 /* If the PMC has overflowed, return a reload count of zero. */ 209 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 210 return (0); 211 v &= (1ULL << core_iaf_width) - 1; 212 return (1ULL << core_iaf_width) - v; 213} 214 215static pmc_value_t 216iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 217{ 218 return (1ULL << core_iaf_width) - rlc; 219} 220 221static int 222iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 223 const struct pmc_op_pmcallocate *a) 224{ 225 enum pmc_event ev; 226 uint32_t caps, flags, validflags; 227 228 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 229 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 230 231 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 232 233 if (ri < 0 || ri > core_iaf_npmc) 234 return (EINVAL); 235 236 caps = a->pm_caps; 237 238 if (a->pm_class != PMC_CLASS_IAF || 239 (caps & IAF_PMC_CAPS) != caps) 240 return (EINVAL); 241 242 ev = pm->pm_event; 243 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 244 return (EINVAL); 245 246 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 247 return (EINVAL); 248 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 249 return (EINVAL); 250 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 251 return (EINVAL); 252 253 pmc_alloc_refs++; 254 if ((cpu_stdext_feature3 & CPUID_STDEXT3_TSXFA) != 0 && 255 !pmc_tsx_force_abort_set) { 256 pmc_tsx_force_abort_set = true; 257 x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS | 258 MSR_OP_WRITE, 1); 259 } 260 261 flags = a->pm_md.pm_iaf.pm_iaf_flags; 262 263 validflags = IAF_MASK; 264 265 if (core_cputype != PMC_CPU_INTEL_ATOM && 266 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 267 validflags &= ~IAF_ANY; 268 269 if ((flags & ~validflags) != 0) 270 return (EINVAL); 271 272 if (caps & PMC_CAP_INTERRUPT) 273 flags |= IAF_PMI; 274 if (caps & PMC_CAP_SYSTEM) 275 flags |= IAF_OS; 276 if (caps & PMC_CAP_USER) 277 flags |= IAF_USR; 278 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 279 flags |= (IAF_OS | IAF_USR); 280 281 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 282 283 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 284 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 285 286 return (0); 287} 288 289static int 290iaf_config_pmc(int cpu, int ri, struct pmc *pm) 291{ 292 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 293 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 294 295 KASSERT(ri >= 0 && ri < core_iaf_npmc, 296 ("[core,%d] illegal row-index %d", __LINE__, ri)); 297 298 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 299 300 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 301 cpu)); 302 303 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 304 305 return (0); 306} 307 308static int 309iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 310{ 311 int error; 312 struct pmc_hw *phw; 313 char iaf_name[PMC_NAME_MAX]; 314 315 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 316 317 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 318 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 319 NULL)) != 0) 320 return (error); 321 322 pi->pm_class = PMC_CLASS_IAF; 323 324 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 325 pi->pm_enabled = TRUE; 326 *ppmc = phw->phw_pmc; 327 } else { 328 pi->pm_enabled = FALSE; 329 *ppmc = NULL; 330 } 331 332 return (0); 333} 334 335static int 336iaf_get_config(int cpu, int ri, struct pmc **ppm) 337{ 338 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 339 340 return (0); 341} 342 343static int 344iaf_get_msr(int ri, uint32_t *msr) 345{ 346 KASSERT(ri >= 0 && ri < core_iaf_npmc, 347 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 348 349 *msr = IAF_RI_TO_MSR(ri); 350 351 return (0); 352} 353 354static int 355iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 356{ 357 struct pmc *pm; 358 pmc_value_t tmp; 359 360 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 361 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 362 KASSERT(ri >= 0 && ri < core_iaf_npmc, 363 ("[core,%d] illegal row-index %d", __LINE__, ri)); 364 365 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 366 367 KASSERT(pm, 368 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 369 ri, ri + core_iaf_ri)); 370 371 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 372 373 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 374 *v = iaf_perfctr_value_to_reload_count(tmp); 375 else 376 *v = tmp & ((1ULL << core_iaf_width) - 1); 377 378 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 379 IAF_RI_TO_MSR(ri), *v); 380 381 return (0); 382} 383 384static int 385iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 386{ 387 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 388 389 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 390 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 391 KASSERT(ri >= 0 && ri < core_iaf_npmc, 392 ("[core,%d] illegal row-index %d", __LINE__, ri)); 393 394 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 395 ("[core,%d] PHW pmc non-NULL", __LINE__)); 396 397 MPASS(pmc_alloc_refs > 0); 398 if (pmc_alloc_refs-- == 1 && pmc_tsx_force_abort_set) { 399 pmc_tsx_force_abort_set = false; 400 x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS | 401 MSR_OP_WRITE, 0); 402 } 403 404 return (0); 405} 406 407static int 408iaf_start_pmc(int cpu, int ri) 409{ 410 struct pmc *pm; 411 struct core_cpu *iafc; 412 uint64_t msr = 0; 413 414 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 415 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 416 KASSERT(ri >= 0 && ri < core_iaf_npmc, 417 ("[core,%d] illegal row-index %d", __LINE__, ri)); 418 419 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 420 421 iafc = core_pcpu[cpu]; 422 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 423 424 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 425 426 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 427 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 428 429 do { 430 iafc->pc_resync = 0; 431 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 432 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 433 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 434 IAF_GLOBAL_CTRL_MASK)); 435 } while (iafc->pc_resync != 0); 436 437 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 438 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 439 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 440 441 return (0); 442} 443 444static int 445iaf_stop_pmc(int cpu, int ri) 446{ 447 uint32_t fc; 448 struct core_cpu *iafc; 449 uint64_t msr = 0; 450 451 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 452 453 iafc = core_pcpu[cpu]; 454 455 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 456 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 457 KASSERT(ri >= 0 && ri < core_iaf_npmc, 458 ("[core,%d] illegal row-index %d", __LINE__, ri)); 459 460 fc = (IAF_MASK << (ri * 4)); 461 462 if (core_cputype != PMC_CPU_INTEL_ATOM && 463 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 464 fc &= ~IAF_ANY; 465 466 iafc->pc_iafctrl &= ~fc; 467 468 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 469 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 470 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 471 472 do { 473 iafc->pc_resync = 0; 474 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 475 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 476 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 477 IAF_GLOBAL_CTRL_MASK)); 478 } while (iafc->pc_resync != 0); 479 480 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 481 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 482 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 483 484 return (0); 485} 486 487static int 488iaf_write_pmc(int cpu, int ri, pmc_value_t v) 489{ 490 struct core_cpu *cc; 491 struct pmc *pm; 492 uint64_t msr; 493 494 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 495 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 496 KASSERT(ri >= 0 && ri < core_iaf_npmc, 497 ("[core,%d] illegal row-index %d", __LINE__, ri)); 498 499 cc = core_pcpu[cpu]; 500 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 501 502 KASSERT(pm, 503 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 504 505 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 506 v = iaf_reload_count_to_perfctr_value(v); 507 508 /* Turn off fixed counters */ 509 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 510 wrmsr(IAF_CTRL, msr); 511 512 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 513 514 /* Turn on fixed counters */ 515 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 516 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 517 518 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 519 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 520 (uintmax_t) rdmsr(IAF_CTRL), 521 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 522 523 return (0); 524} 525 526 527static void 528iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 529{ 530 struct pmc_classdep *pcd; 531 532 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 533 534 PMCDBG0(MDP,INI,1, "iaf-initialize"); 535 536 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 537 538 pcd->pcd_caps = IAF_PMC_CAPS; 539 pcd->pcd_class = PMC_CLASS_IAF; 540 pcd->pcd_num = npmc; 541 pcd->pcd_ri = md->pmd_npmc; 542 pcd->pcd_width = pmcwidth; 543 544 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 545 pcd->pcd_config_pmc = iaf_config_pmc; 546 pcd->pcd_describe = iaf_describe; 547 pcd->pcd_get_config = iaf_get_config; 548 pcd->pcd_get_msr = iaf_get_msr; 549 pcd->pcd_pcpu_fini = core_pcpu_noop; 550 pcd->pcd_pcpu_init = core_pcpu_noop; 551 pcd->pcd_read_pmc = iaf_read_pmc; 552 pcd->pcd_release_pmc = iaf_release_pmc; 553 pcd->pcd_start_pmc = iaf_start_pmc; 554 pcd->pcd_stop_pmc = iaf_stop_pmc; 555 pcd->pcd_write_pmc = iaf_write_pmc; 556 557 md->pmd_npmc += npmc; 558} 559 560/* 561 * Intel programmable PMCs. 562 */ 563 564/* 565 * Event descriptor tables. 566 * 567 * For each event id, we track: 568 * 569 * 1. The CPUs that the event is valid for. 570 * 571 * 2. If the event uses a fixed UMASK, the value of the umask field. 572 * If the event doesn't use a fixed UMASK, a mask of legal bits 573 * to check against. 574 */ 575 576struct iap_event_descr { 577 enum pmc_event iap_ev; 578 unsigned char iap_evcode; 579 unsigned char iap_umask; 580 unsigned int iap_flags; 581}; 582 583#define IAP_F_CC (1 << 0) /* CPU: Core */ 584#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 585#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 586#define IAP_F_CA (1 << 3) /* CPU: Atom */ 587#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 588#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 589#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 590#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 591#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 592#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 593#define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 594#define IAP_F_HW (1 << 10) /* CPU: Haswell */ 595#define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 596#define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 597#define IAP_F_BW (1 << 13) /* CPU: Broadwell */ 598#define IAP_F_BWX (1 << 14) /* CPU: Broadwell Xeon */ 599#define IAP_F_SL (1 << 15) /* CPU: Skylake */ 600#define IAP_F_SLX (1 << 16) /* CPU: Skylake Xeon AKA scalable */ 601#define IAP_F_FM (1 << 18) /* Fixed mask */ 602 603#define IAP_F_ALLCPUSCORE2 \ 604 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 605 606/* Sub fields of UMASK that this event supports. */ 607#define IAP_M_CORE (1 << 0) /* Core specificity */ 608#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 609#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 610#define IAP_M_MESI (1 << 3) /* MESI */ 611#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 612#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 613#define IAP_M_TRANSITION (1 << 6) /* Transition */ 614 615#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 616#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 617#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 618#define IAP_F_MESI (0xF << 8) /* MESI */ 619#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 620#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 621#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 622 623#define IAP_PREFETCH_RESERVED (0x2 << 12) 624#define IAP_CORE_THIS (0x1 << 14) 625#define IAP_CORE_ALL (0x3 << 14) 626#define IAP_F_CMASK 0xFF000000 627 628static struct iap_event_descr iap_events[] = { 629#undef IAPDESCR 630#define IAPDESCR(N,EV,UM,FLAGS) { \ 631 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 632 .iap_evcode = (EV), \ 633 .iap_umask = (UM), \ 634 .iap_flags = (FLAGS) \ 635 } 636 637 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 638 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 639 640 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 641 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 642 IAP_F_SBX | IAP_F_CAS), 643 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 644 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 645 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 646 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 647 IAP_F_CAS), 648 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 649 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 650 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 651 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 652 IAP_F_SBX | IAP_F_CAS), 653 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 654 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_FM | IAP_F_CAS), 655 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_FM | IAP_F_CAS), 656 657 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 658 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 659 IAP_F_CAS), 660 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 661 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_FM | IAP_F_CAS), 662 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 663 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 664 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_FM | IAP_F_CAS), 665 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_FM | IAP_F_CAS), 666 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_FM | IAP_F_CAS), 667 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_FM | IAP_F_CAS), 668 669 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 670 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 671 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | 672 IAP_F_BWX), 673 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 674 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | 675 IAP_F_BW | IAP_F_BWX), 676 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 677 678 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 679 IAP_F_CC2E | IAP_F_CA), 680 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 681 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 682 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 683 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 684 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 685 686 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 687 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 688 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 689 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 690 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 691 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 692 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 693 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 694 IAP_F_SBX), 695 696 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 697 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 698 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 699 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 700 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 701 IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 702 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 703 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_SLX), 704 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 705 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 706 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 707 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SLX), 708 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 709 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 710 IAP_F_SLX), 711 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 712 IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 713 IAP_F_SLX), 714 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 715 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 716 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 717 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 718 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 719 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 720 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 721 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 722 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 723 724 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 725 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 726 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 727 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 728 729 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 733 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 734 IAP_F_WM | IAP_F_SL), 735 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 736 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 737 738 IAPDESCR(0DH_01H, 0x0D, 0x80, IAP_F_FM | IAP_F_SLX), 739 IAPDESCR(0DH_03H, 0x0D, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 740 IAP_F_IB | IAP_F_IBX | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 741 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 742 IAPDESCR(0DH_80H, 0x0D, 0x80, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 743 744 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 745 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 746 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 747 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL | 748 IAP_F_SLX), 749 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 750 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 751 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 752 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 753 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 754 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 755 756 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 757 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 761 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 762 763 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 764 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 765 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 766 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 770 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 771 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 772 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 773 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 774 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 775 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 776 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 777 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 778 779 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 780 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 781 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 782 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 783 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 784 785 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 786 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 787 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 788 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 789 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 790 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 791 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 792 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 793 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 794 795 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 796 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 797 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 798 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 799 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 800 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 801 802 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 803 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 804 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 805 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 806 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 807 808 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 809 IAP_F_SBX), 810 811 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 812 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 813 814 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 815 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 816 IAP_F_I7 | IAP_F_WM), 817 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 818 819 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 820 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 821 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 822 823 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 824 825 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 826 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 827 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 828 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 829 830 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 831 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 832 IAP_F_IB | IAP_F_SBX | IAP_F_IBX ), 833 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 834 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 835 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 836 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 837 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 838 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 839 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 840 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 841 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 842 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 843 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 844 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 845 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 846 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 847 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 848 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 849 IAP_F_SLX), 850 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 851 IAP_F_SLX), 852 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 853 IAP_F_SLX), 854 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 855 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 856 IAP_F_BW | IAP_F_BWX), 857 IAPDESCR(24H_38H, 0x24, 0x38, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 858 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 859 IAP_F_SLX), 860 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 861 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 862 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 863 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 864 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 865 IAP_F_SLX), 866 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 867 IAP_F_SLX), 868 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 869 IAP_F_BW | IAP_F_BWX), 870 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 871 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 872 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 873 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 874 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 875 IAPDESCR(24H_D8H, 0x24, 0xD8, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 876 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 877 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 878 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 879 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 880 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 881 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 882 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 883 IAP_F_SLX), 884 IAPDESCR(24H_EFH, 0x24, 0xEF, IAP_F_FM | IAP_F_SL), 885 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 886 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 887 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 888 IAP_F_HWX | IAP_F_SLX), 889 890 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 891 892 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 893 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 894 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 895 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 896 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 897 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 898 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 899 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 900 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 901 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 902 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 903 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 904 905 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 906 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 907 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 908 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 909 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 910 IAP_F_SBX), 911 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 912 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 913 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 914 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 915 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 916 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 917 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 918 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 919 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 920 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 921 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 922 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 923 924 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 925 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 926 IAP_F_SBX | IAP_F_IBX), 927 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 928 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 929 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 930 IAPDESCR(28H_07H, 0x28, 0x07, IAP_F_FM | IAP_F_SLX), 931 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 932 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 933 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 934 IAP_F_SBX | IAP_F_IBX), 935 IAPDESCR(28H_18H, 0x28, 0x18, IAP_F_SLX), 936 IAPDESCR(28H_20H, 0x28, 0x20, IAP_F_SLX), 937 IAPDESCR(28H_40H, 0x28, 0x40, IAP_F_SLX), 938 939 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 940 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 941 IAP_F_CA | IAP_F_CC2), 942 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 943 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 944 945 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 946 IAP_F_ALLCPUSCORE2), 947 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 948 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 949 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 950 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 951 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 952 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 953 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 954 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 955 956 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 957 IAP_F_ALLCPUSCORE2), 958 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_FM | IAP_F_CAS), 959 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_FM | IAP_F_CAS), 960 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 961 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 962 963 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 964 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 965 966 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 967 968 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 969 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 970 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 971 IAP_F_SLX), 972 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 973 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 974 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 975 IAP_F_SLX), 976 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_SL | 977 IAP_F_SLX), 978 979 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 980 981 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 982 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 983 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 984 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 985 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 986 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 987 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 988 989 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 990 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 991 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 992 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 993 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 994 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 995 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 996 997 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 998 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 999 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 1000 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 1001 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 1002 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1003 1004 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1005 IAP_F_I7), 1006 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 1007 IAP_F_CC2 | IAP_F_I7), 1008 1009 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 1010 1011 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1012 1013 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1014 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1015 1016 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1017 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1018 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1019 IAP_F_SL | IAP_F_SLX), 1020 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_SL | IAP_F_SLX), 1021 1022 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 1023 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1024 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 1025 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1026 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1027 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 1028 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 1029 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 1030 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SLX), 1031 IAPDESCR(49H_08H, 0x49, 0x08, IAP_F_FM | IAP_F_SLX), 1032 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 1033 IAP_F_SLX), 1034 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1035 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1036 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1037 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX | 1038 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1039 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1040 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1041 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 1042 IAP_F_HWX), 1043 1044 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1045 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 1046 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1047 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 1048 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 1049 1050 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1051 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1052 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1053 IAP_F_SL | IAP_F_SLX), 1054 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1055 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1056 1057 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 1058 1059 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1060 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1061 IAP_F_SB | IAP_F_SBX), 1062 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1063 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1064 1065 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 1066 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1067 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1068 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1069 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_BW | IAP_F_BWX | 1070 IAP_F_SL | IAP_F_SLX), 1071 1072 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1073 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1074 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1075 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1076 IAP_F_SB | IAP_F_SBX), 1077 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1078 IAP_F_SB | IAP_F_SBX), 1079 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1080 IAP_F_SB | IAP_F_SBX), 1081 1082 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1083 1084 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1085 1086 IAPDESCR(54H_01H, 0x54, 0x01, IAP_F_FM | IAP_F_SLX), 1087 IAPDESCR(54H_02H, 0x54, 0x02, IAP_F_FM | IAP_F_SLX), 1088 IAPDESCR(54H_04H, 0x54, 0x04, IAP_F_FM | IAP_F_SLX), 1089 IAPDESCR(54H_08H, 0x54, 0x08, IAP_F_FM | IAP_F_SLX), 1090 IAPDESCR(54H_10H, 0x54, 0x10, IAP_F_FM | IAP_F_SLX), 1091 IAPDESCR(54H_20H, 0x54, 0x20, IAP_F_FM | IAP_F_SLX), 1092 IAPDESCR(54H_40H, 0x54, 0x40, IAP_F_FM | IAP_F_SLX), 1093 1094 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1095 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1096 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1097 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1098 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1099 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1100 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1101 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1102 1103 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1104 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1105 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1106 1107 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1108 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1109 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1110 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1111 1112 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1113 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1114 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1115 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1116 1117 IAPDESCR(5DH_01H, 0x5d, 0x01, IAP_F_FM | IAP_F_SLX), 1118 IAPDESCR(5DH_02H, 0x5d, 0x02, IAP_F_FM | IAP_F_SLX), 1119 IAPDESCR(5DH_04H, 0x5d, 0x04, IAP_F_FM | IAP_F_SLX), 1120 IAPDESCR(5DH_08H, 0x5d, 0x08, IAP_F_FM | IAP_F_SLX), 1121 IAPDESCR(5DH_10H, 0x5d, 0x10, IAP_F_FM | IAP_F_SLX), 1122 1123 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1124 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1125 IAP_F_SL | IAP_F_SLX), 1126 1127 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1128 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_FM | IAP_F_IBX | IAP_F_IB), 1129 1130 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1131 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1132 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1133 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1134 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1135 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1136 IAP_F_SLX), 1137 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM |IAP_F_I7O | 1138 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1139 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1140 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM |IAP_F_I7O | 1141 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1142 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1143 IAPDESCR(60H_10H, 0x60, 0x10, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1144 1145 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1146 1147 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1148 1149 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1150 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1151 1152 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1153 IAP_F_CA | IAP_F_CC2), 1154 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1155 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1156 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1157 IAP_F_BW | IAP_F_BWX ), 1158 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1159 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1160 IAP_F_BW | IAP_F_BWX), 1161 1162 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1163 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1164 1165 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1166 IAP_F_CA | IAP_F_CC2), 1167 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1168 1169 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1170 1171 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1172 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1173 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1174 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1175 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1176 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1177 1178 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1179 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1180 1181 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1182 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1183 1184 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1185 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1186 1187 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1188 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1189 1190 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1191 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1192 1193 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1194 IAP_F_CA | IAP_F_CC2), 1195 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1196 1197 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1198 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1199 1200 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1201 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1202 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1203 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1204 IAP_F_SL | IAP_F_SLX), 1205 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1206 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_BW | 1207 IAP_F_BWX | IAP_F_SLX), 1208 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1210 IAP_F_SL | IAP_F_SLX), 1211 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1212 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1213 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1214 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1215 IAP_F_SL | IAP_F_SLX), 1216 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1217 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1218 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1219 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1220 IAP_F_SL | IAP_F_SLX), 1221 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1222 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1223 1224 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1225 1226 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1227 1228 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1229 1230 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1231 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1232 1233 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1234 1235 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1236 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1237 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1238 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1239 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1240 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1241 IAP_F_WM | IAP_F_CAS), 1242 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1243 IAP_F_IBX | IAP_F_SL | IAP_F_SLX), /* SL may have a spec bug two with 1244 same entry no cmask */ 1245 1246 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1247 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1248 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1249 1250 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1251 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1252 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1253 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1254 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1255 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1256 1257 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SL | IAP_F_SLX), 1258 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL | 1259 IAP_F_SLX), 1260 IAPDESCR(83H_04H, 0x83, 0x04, IAP_F_FM | IAP_F_SLX), 1261 1262 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1263 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1264 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1265 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1266 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1267 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1268 IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 1269 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1270 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1271 IAP_F_SLX), 1272 IAPDESCR(85H_08H, 0x85, 0x08, IAP_F_FM | IAP_F_SLX), 1273 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 1274 IAP_F_SLX), 1275 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1276 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1277 IAP_F_SL | IAP_F_SLX), 1278 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX | 1279 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1280 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1281 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1282 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1283 1284 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1285 1286 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1287 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1288 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1289 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1290 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1291 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1292 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1293 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1294 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1295 1296 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1297 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1298 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1299 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1300 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1301 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1302 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1303 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1304 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1305 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1306 IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1307 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1308 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1309 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1310 IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1311 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1312 IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1313 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1314 IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1315 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1316 IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1317 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1318 IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1319 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1320 IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1321 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1322 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1323 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1324 1325 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1326 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1327 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1328 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1329 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1330 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1331 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1332 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1333 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1334 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1335 IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1336 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1337 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1338 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1339 IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1340 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1341 IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1342 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1343 IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1344 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1345 IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1346 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1347 IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1348 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1349 IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1350 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1351 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1352 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1353 1354 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1355 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1356 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1357 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1358 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1359 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1360 1361 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1362 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1363 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1364 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1365 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1366 1367 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1368 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1369 1370 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1371 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1372 IAP_F_SL | IAP_F_SLX), 1373 1374 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1375 1376 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1377 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1378 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1379 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1380 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1381 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1382 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1383 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1384 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1385 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1386 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1387 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1388 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1389 IAP_F_SBX | IAP_F_IBX), 1390 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1391 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1392 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1393 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1394 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1395 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1396 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1397 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1398 IAP_F_SL | IAP_F_SLX), 1399 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1400 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1401 IAP_F_SL | IAP_F_SLX), 1402 1403 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1404 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1405 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1406 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1407 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1408 IAP_F_SB | IAP_F_SBX), 1409 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1410 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1411 IAP_F_BW | IAP_F_BWX), 1412 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1413 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1414 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1415 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1416 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1417 IAP_F_BW | IAP_F_BWX), 1418 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1419 IAP_F_SB | IAP_F_SBX), 1420 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1421 IAP_F_SB | IAP_F_SBX), 1422 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1423 IAP_F_SB | IAP_F_SBX), 1424 1425 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1426 IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1427 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1428 IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1429 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1430 IAP_F_SL | IAP_F_SLX), 1431 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 1432 IAP_F_SLX), 1433 IAPDESCR(A3H_06H, 0xA3, 0x06, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1434 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | 1435 IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1436 IAPDESCR(A3H_0CH, 0xA3, 0x0C, IAP_F_FM | IAP_F_HW | IAP_F_HW | IAP_F_SL | 1437 IAP_F_SLX), 1438 IAPDESCR(A3H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1439 IAPDESCR(A3H_14H, 0xA3, 0x14, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1440 1441 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL | 1442 IAP_F_SLX), 1443 IAPDESCR(A6H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1444 IAPDESCR(A6H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1445 IAPDESCR(A6H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1446 IAPDESCR(A6H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1447 IAPDESCR(A6H_40H, 0xA3, 0x40, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1448 1449 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM ), 1450 1451 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1452 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1453 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1454 1455 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1456 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1457 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1458 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1459 1460 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1461 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1462 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1463 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX | 1464 IAP_F_SLX), 1465 1466 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_SL), 1467 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1468 IAP_F_SBX | IAP_F_IBX), 1469 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1470 1471 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1472 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1473 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1474 1475 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1476 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1477 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1478 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1479 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1480 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1481 IAP_F_SLX), 1482 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1483 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1484 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1485 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1486 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1487 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1488 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SL | 1489 IAP_F_SLX), 1490 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1491 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1492 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O | 1493 IAP_F_SL | IAP_F_SLX), 1494 1495 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1496 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1497 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX | 1498 IAP_F_SL | IAP_F_SLX), 1499 IAPDESCR(B1H_02H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1500 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1501 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1502 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1503 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1504 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SLX), 1505 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1506 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1507 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1508 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1509 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1510 IAP_F_WM), 1511 1512 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1513 IAP_F_SB | IAP_F_SBX | IAP_F_SLX), 1514 1515 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1516 IAP_F_WM | IAP_F_I7O), 1517 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1518 IAP_F_WM | IAP_F_I7O), 1519 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1520 IAP_F_WM | IAP_F_I7O), 1521 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1522 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1523 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1524 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1525 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1526 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1527 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1528 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1529 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1530 1531 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1532 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1533 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1534 1535 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1536 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_FM | IAP_F_CAS), 1537 1538 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1539 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1540 IAP_F_HWX |IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1541 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1542 1543 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1544 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1545 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1546 1547 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1548 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1549 1550 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1551 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1552 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1553 1554 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1555 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1556 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1557 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1558 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1559 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1560 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1561 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1562 1563 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1564 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), /* spec bug SL? */ 1565 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1566 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SLX), 1567 1568 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1569 1570 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1571 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1572 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1573 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1574 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1575 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1576 IAP_F_SLX), 1577 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1578 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_BW | IAP_F_BWX), 1579 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1580 IAP_F_I7 | IAP_F_WM), 1581 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1582 1583 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1584 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1585 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1586 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1587 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1588 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1589 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1590 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1591 IAP_F_SBX | IAP_F_IBX), 1592 IAPDESCR(C1H_3FH, 0xC1, 0x3F, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1593 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1594 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_FM |IAP_F_IB | IAP_F_IBX), 1595 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1596 1597 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1598 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1599 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1600 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1601 IAP_F_SL | IAP_F_SLX), 1602 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1603 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1604 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1605 IAP_F_SLX), 1606 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1607 IAP_F_I7 | IAP_F_WM), 1608 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1609 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1610 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1611 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1612 1613 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1614 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1615 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1616 IAP_F_SLX), 1617 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1618 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1619 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1620 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1621 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1622 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1623 IAP_F_SL | IAP_F_SLX), 1624 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_FM | IAP_F_CAS), 1625 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1626 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1627 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1628 1629 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1630 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1631 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1632 IAP_F_SL | IAP_F_SLX), 1633 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1634 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1635 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1636 IAP_F_SLX), 1637 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1638 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1639 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1640 IAP_F_SLX), 1641 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1642 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1643 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1644 IAP_F_SLX), 1645 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1646 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1647 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1648 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1649 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1650 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1651 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1652 IAP_F_SL | IAP_F_SLX), 1653 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1654 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1655 IAP_F_SL | IAP_F_SLX), 1656 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1657 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1658 IAP_F_SL | IAP_F_SLX), 1659 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_FM | IAP_F_CAS), 1660 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_FM | IAP_F_CAS), 1661 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_FM | IAP_F_CAS), 1662 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_FM | IAP_F_CAS), 1663 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_FM | IAP_F_CAS), 1664 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_FM | IAP_F_CAS), 1665 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_FM | IAP_F_CAS), 1666 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_FM | IAP_F_CAS), 1667 1668 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1669 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1670 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1671 IAP_F_SL | IAP_F_SLX), 1672 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1673 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1674 IAP_F_BWX | IAP_F_SLX), 1675 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1676 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SL | IAP_F_SLX), 1677 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1678 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1679 IAP_F_BWX | IAP_F_SL), 1680 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1681 IAP_F_SBX | IAP_F_IBX), 1682 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1683 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1684 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_FM | IAP_F_CAS), 1685 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_FM | IAP_F_CAS), 1686 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_FM | IAP_F_CAS), 1687 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_FM | IAP_F_CAS), 1688 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_FM | IAP_F_CAS), 1689 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_FM | IAP_F_CAS), 1690 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_FM | IAP_F_CAS), 1691 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_FM | IAP_F_CAS), 1692 1693 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1694 /* For SL C6_01 needs EV_SEL? 0x11, 0x12, 0x13, 0x14, 0x15? */ 1695 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL | 1696 IAP_F_SLX), 1697 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1698 1699 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1700 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1701 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1702 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1703 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1704 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1705 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1706 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1707 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1708 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1709 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1710 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1711 IAPDESCR(C7H_20H, 0xC7, 0x20, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1712 IAPDESCR(C7H_40H, 0xc7, 0x40, IAP_F_FM | IAP_F_SLX), 1713 IAPDESCR(C7H_80H, 0xc7, 0x80, IAP_F_FM | IAP_F_SLX), 1714 1715 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1716 IAPDESCR(C8H_01H, 0xC8, 0x01, IAP_F_FM | IAP_F_SLX), 1717 IAPDESCR(C8H_02H, 0xC8, 0x02, IAP_F_FM | IAP_F_SLX), 1718 IAPDESCR(C8H_04H, 0xC8, 0x04, IAP_F_FM | IAP_F_SLX), 1719 IAPDESCR(C8H_08H, 0xC8, 0x08, IAP_F_FM | IAP_F_SLX), 1720 IAPDESCR(C8H_10H, 0xC8, 0x10, IAP_F_FM | IAP_F_SLX), 1721 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SLX), 1722 IAPDESCR(C8H_40H, 0xC8, 0x40, IAP_F_FM | IAP_F_SLX), 1723 IAPDESCR(C8H_80H, 0xC8, 0x80, IAP_F_FM | IAP_F_SLX), 1724 1725 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1726 IAPDESCR(C9H_01H, 0xC9, 0x01, IAP_F_FM | IAP_F_SLX), 1727 IAPDESCR(C9H_02H, 0xC9, 0x02, IAP_F_FM | IAP_F_SLX), 1728 IAPDESCR(C9H_04H, 0xC9, 0x04, IAP_F_FM | IAP_F_SLX), 1729 IAPDESCR(C9H_08H, 0xC9, 0x08, IAP_F_FM | IAP_F_SLX), 1730 IAPDESCR(C9H_10H, 0xC9, 0x10, IAP_F_FM | IAP_F_SLX), 1731 IAPDESCR(C9H_20H, 0xC9, 0x20, IAP_F_FM | IAP_F_SLX), 1732 IAPDESCR(C9H_40H, 0xC9, 0x40, IAP_F_FM | IAP_F_SLX), 1733 IAPDESCR(C9H_80H, 0xC9, 0x80, IAP_F_FM | IAP_F_SLX), 1734 1735 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1736 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1737 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1738 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1739 IAP_F_BW | IAP_F_BWX), 1740 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1741 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1742 IAP_F_BW | IAP_F_BWX), 1743 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1744 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1745 IAP_F_BW | IAP_F_BWX), 1746 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1747 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1748 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1749 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1750 IAP_F_SL | IAP_F_SLX), 1751 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_FM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX), 1752 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_FM | IAP_F_CAS), 1753 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_FM | IAP_F_CAS), 1754 1755 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1756 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_SL | IAP_F_SLX), 1757 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1758 IAP_F_I7 | IAP_F_WM), 1759 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1760 IAP_F_I7 | IAP_F_WM), 1761 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1762 IAP_F_I7 | IAP_F_WM), 1763 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1764 IAP_F_WM), 1765 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_FM | IAP_F_CAS), 1766 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1767 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1768 1769 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1770 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1771 IAP_F_I7 | IAP_F_WM), 1772 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1773 IAP_F_I7 | IAP_F_WM), 1774 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1775 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1776 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1777 IAP_F_SLX), 1778 1779 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1780 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1781 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | 1782 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1783 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1784 IAP_F_SBX | IAP_F_IBX), 1785 1786 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1787 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1788 1789 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1790 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1791 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1792 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1793 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1794 IAP_F_SLX), 1795 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1796 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1797 IAP_F_SLX), 1798 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_BW | 1799 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1800 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1801 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1802 IAP_F_SLX), 1803 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1804 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1805 IAP_F_SLX), 1806 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1807 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1808 IAP_F_SLX), 1809 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1810 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1811 IAP_F_SLX), 1812 1813 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1814 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1815 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1816 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1817 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1818 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1819 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1820 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1821 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1822 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1823 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1824 IAP_F_SLX), 1825 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX | 1826 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1827 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1828 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1829 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1830 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1831 IAP_F_SL | IAP_F_SLX), 1832 1833 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1834 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1835 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1836 IAP_F_SLX), 1837 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1838 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1839 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1840 IAP_F_SLX), 1841 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1842 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1843 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1844 IAP_F_SLX), 1845 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1846 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1847 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1848 IAP_F_SLX), 1849 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1850 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1851 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1852 1853 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1854 1855 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1856 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 1857 IAPDESCR(D3H_02H, 0xD3, 0x02, IAP_F_FM | IAP_F_SLX), 1858 IAPDESCR(D3H_03H, 0xD3, 0x03, IAP_F_FM | IAP_F_IBX), 1859 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), /* Not defined for IBX */ 1860 IAPDESCR(D3H_08H, 0xD3, 0x08, IAP_F_FM | IAP_F_SLX), 1861 IAPDESCR(D3H_0CH, 0xD3, 0x0C, IAP_F_FM | IAP_F_IBX), 1862 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_FM | IAP_F_IBX ), 1863 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_FM | IAP_F_IBX ), 1864 1865 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1866 IAP_F_I7 | IAP_F_WM), 1867 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1868 IAP_F_SB | IAP_F_SBX), 1869 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SLX), 1870 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1871 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1872 1873 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1874 IAP_F_I7 | IAP_F_WM), 1875 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1876 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1877 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1878 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1879 1880 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1881 1882 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1883 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1884 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1885 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1886 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1887 1888 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1889 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1890 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1891 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1892 1893 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1894 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1895 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1896 1897 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1898 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1899 1900 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1901 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1902 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1903 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1904 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1905 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1906 1907 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1908 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1909 IAP_F_WM), 1910 1911 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1912 1913 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1914 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1915 1916 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1917 1918 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1919 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1920 IAP_F_WM | IAP_F_SBX | IAP_F_CAS | IAP_F_SL | IAP_F_SLX), 1921 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1922 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_FM | IAP_F_CAS), 1923 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_FM | IAP_F_CAS), 1924 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1925 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1926 1927 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_FM | IAP_F_CAS), 1928 1929 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1930 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1931 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1932 1933 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1934 1935 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1936 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1937 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1938 IAP_F_BW | IAP_F_BWX), 1939 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1940 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1941 IAP_F_BW | IAP_F_BWX), 1942 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1943 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1944 IAP_F_BW | IAP_F_BWX), 1945 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1946 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1947 IAP_F_BW | IAP_F_BWX), 1948 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1949 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1950 IAP_F_BW | IAP_F_BWX), 1951 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1952 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1953 IAP_F_BW | IAP_F_BWX), 1954 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1955 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1956 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1957 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1958 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1959 IAP_F_BW | IAP_F_BWX), 1960 1961 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1962 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1963 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1964 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1965 IAP_F_BW | IAP_F_BWX), 1966 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1967 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1968 IAP_F_BW | IAP_F_BWX ), 1969 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1970 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1971 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1972 IAPDESCR(F1H_1FH, 0xF1, 0x1f, IAP_F_FM | IAP_F_SLX), 1973 1974 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1975 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), 1976 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1977 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), 1978 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1979 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), 1980 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1981 IAP_F_BWX), 1982 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1983 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1984 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1985 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1986 IAP_F_IBX), 1987 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1988 1989 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1990 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1991 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1992 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1993 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1994 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1995 1996 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1997 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1998 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1999 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 2000 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 2001 IAP_F_SB | IAP_F_SBX | IAP_F_SLX), 2002 2003 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 2004 2005 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2006 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2007 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2008 2009 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 2010 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 2011 2012 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2013 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2014 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2015 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2016 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2017 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2018 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2019 2020 IAPDESCR(FEH_02H, 0xfe, 0x02, IAP_F_FM | IAP_F_SLX), 2021 IAPDESCR(FEH_04H, 0xfe, 0x04, IAP_F_FM | IAP_F_SLX), 2022}; 2023 2024static pmc_value_t 2025iap_perfctr_value_to_reload_count(pmc_value_t v) 2026{ 2027 2028 /* If the PMC has overflowed, return a reload count of zero. */ 2029 if ((v & (1ULL << (core_iap_width - 1))) == 0) 2030 return (0); 2031 v &= (1ULL << core_iap_width) - 1; 2032 return (1ULL << core_iap_width) - v; 2033} 2034 2035static pmc_value_t 2036iap_reload_count_to_perfctr_value(pmc_value_t rlc) 2037{ 2038 return (1ULL << core_iap_width) - rlc; 2039} 2040 2041static int 2042iap_pmc_has_overflowed(int ri) 2043{ 2044 uint64_t v; 2045 2046 /* 2047 * We treat a Core (i.e., Intel architecture v1) PMC as has 2048 * having overflowed if its MSB is zero. 2049 */ 2050 v = rdpmc(ri); 2051 return ((v & (1ULL << (core_iap_width - 1))) == 0); 2052} 2053 2054/* 2055 * Check an event against the set of supported architectural events. 2056 * 2057 * If the event is not architectural EV_IS_NOTARCH is returned. 2058 * If the event is architectural and supported on this CPU, the correct 2059 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 2060 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 2061 */ 2062 2063static int 2064iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 2065{ 2066 enum core_arch_events ae; 2067 2068 switch (pe) { 2069 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 2070 ae = CORE_AE_UNHALTED_CORE_CYCLES; 2071 *map = PMC_EV_IAP_EVENT_3CH_00H; 2072 break; 2073 case PMC_EV_IAP_ARCH_INS_RET: 2074 ae = CORE_AE_INSTRUCTION_RETIRED; 2075 *map = PMC_EV_IAP_EVENT_C0H_00H; 2076 break; 2077 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 2078 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 2079 *map = PMC_EV_IAP_EVENT_3CH_01H; 2080 break; 2081 case PMC_EV_IAP_ARCH_LLC_REF: 2082 ae = CORE_AE_LLC_REFERENCE; 2083 *map = PMC_EV_IAP_EVENT_2EH_4FH; 2084 break; 2085 case PMC_EV_IAP_ARCH_LLC_MIS: 2086 ae = CORE_AE_LLC_MISSES; 2087 *map = PMC_EV_IAP_EVENT_2EH_41H; 2088 break; 2089 case PMC_EV_IAP_ARCH_BR_INS_RET: 2090 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 2091 *map = PMC_EV_IAP_EVENT_C4H_00H; 2092 break; 2093 case PMC_EV_IAP_ARCH_BR_MIS_RET: 2094 ae = CORE_AE_BRANCH_MISSES_RETIRED; 2095 *map = PMC_EV_IAP_EVENT_C5H_00H; 2096 break; 2097 2098 default: /* Non architectural event. */ 2099 return (EV_IS_NOTARCH); 2100 } 2101 2102 return (((core_architectural_events & (1 << ae)) == 0) ? 2103 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 2104} 2105 2106static int 2107iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 2108{ 2109 uint32_t mask; 2110 2111 switch (pe) { 2112 /* 2113 * Events valid only on counter 0, 1. 2114 */ 2115 case PMC_EV_IAP_EVENT_40H_01H: 2116 case PMC_EV_IAP_EVENT_40H_02H: 2117 case PMC_EV_IAP_EVENT_40H_04H: 2118 case PMC_EV_IAP_EVENT_40H_08H: 2119 case PMC_EV_IAP_EVENT_40H_0FH: 2120 case PMC_EV_IAP_EVENT_41H_02H: 2121 case PMC_EV_IAP_EVENT_41H_04H: 2122 case PMC_EV_IAP_EVENT_41H_08H: 2123 case PMC_EV_IAP_EVENT_42H_01H: 2124 case PMC_EV_IAP_EVENT_42H_02H: 2125 case PMC_EV_IAP_EVENT_42H_04H: 2126 case PMC_EV_IAP_EVENT_42H_08H: 2127 case PMC_EV_IAP_EVENT_43H_01H: 2128 case PMC_EV_IAP_EVENT_43H_02H: 2129 case PMC_EV_IAP_EVENT_51H_01H: 2130 case PMC_EV_IAP_EVENT_51H_02H: 2131 case PMC_EV_IAP_EVENT_51H_04H: 2132 case PMC_EV_IAP_EVENT_51H_08H: 2133 case PMC_EV_IAP_EVENT_63H_01H: 2134 case PMC_EV_IAP_EVENT_63H_02H: 2135 mask = 0x3; 2136 break; 2137 2138 default: 2139 mask = ~0; /* Any row index is ok. */ 2140 } 2141 2142 return (mask & (1 << ri)); 2143} 2144 2145static int 2146iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 2147{ 2148 uint32_t mask; 2149 2150 switch (pe) { 2151 /* 2152 * Events valid only on counter 0. 2153 */ 2154 case PMC_EV_IAP_EVENT_60H_01H: 2155 case PMC_EV_IAP_EVENT_60H_02H: 2156 case PMC_EV_IAP_EVENT_60H_04H: 2157 case PMC_EV_IAP_EVENT_60H_08H: 2158 case PMC_EV_IAP_EVENT_B3H_01H: 2159 case PMC_EV_IAP_EVENT_B3H_02H: 2160 case PMC_EV_IAP_EVENT_B3H_04H: 2161 mask = 0x1; 2162 break; 2163 2164 /* 2165 * Events valid only on counter 0, 1. 2166 */ 2167 case PMC_EV_IAP_EVENT_4CH_01H: 2168 case PMC_EV_IAP_EVENT_4EH_01H: 2169 case PMC_EV_IAP_EVENT_4EH_02H: 2170 case PMC_EV_IAP_EVENT_4EH_04H: 2171 case PMC_EV_IAP_EVENT_51H_01H: 2172 case PMC_EV_IAP_EVENT_51H_02H: 2173 case PMC_EV_IAP_EVENT_51H_04H: 2174 case PMC_EV_IAP_EVENT_51H_08H: 2175 case PMC_EV_IAP_EVENT_63H_01H: 2176 case PMC_EV_IAP_EVENT_63H_02H: 2177 mask = 0x3; 2178 break; 2179 2180 default: 2181 mask = ~0; /* Any row index is ok. */ 2182 } 2183 2184 return (mask & (1 << ri)); 2185} 2186 2187static int 2188iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 2189{ 2190 uint32_t mask; 2191 2192 switch (pe) { 2193 /* Events valid only on counter 0. */ 2194 case PMC_EV_IAP_EVENT_B7H_01H: 2195 mask = 0x1; 2196 break; 2197 /* Events valid only on counter 1. */ 2198 case PMC_EV_IAP_EVENT_C0H_01H: 2199 mask = 0x2; 2200 break; 2201 /* Events valid only on counter 2. */ 2202 case PMC_EV_IAP_EVENT_48H_01H: 2203 case PMC_EV_IAP_EVENT_A2H_02H: 2204 case PMC_EV_IAP_EVENT_A3H_08H: 2205 mask = 0x4; 2206 break; 2207 /* Events valid only on counter 3. */ 2208 case PMC_EV_IAP_EVENT_BBH_01H: 2209 case PMC_EV_IAP_EVENT_CDH_01H: 2210 case PMC_EV_IAP_EVENT_CDH_02H: 2211 mask = 0x8; 2212 break; 2213 default: 2214 mask = ~0; /* Any row index is ok. */ 2215 } 2216 2217 return (mask & (1 << ri)); 2218} 2219 2220static int 2221iap_event_ok_on_counter(enum pmc_event pe, int ri) 2222{ 2223 uint32_t mask; 2224 2225 switch (pe) { 2226 /* 2227 * Events valid only on counter 0. 2228 */ 2229 case PMC_EV_IAP_EVENT_10H_00H: 2230 case PMC_EV_IAP_EVENT_14H_00H: 2231 case PMC_EV_IAP_EVENT_18H_00H: 2232 case PMC_EV_IAP_EVENT_B3H_01H: 2233 case PMC_EV_IAP_EVENT_B3H_02H: 2234 case PMC_EV_IAP_EVENT_B3H_04H: 2235 case PMC_EV_IAP_EVENT_C1H_00H: 2236 case PMC_EV_IAP_EVENT_CBH_01H: 2237 case PMC_EV_IAP_EVENT_CBH_02H: 2238 mask = (1 << 0); 2239 break; 2240 2241 /* 2242 * Events valid only on counter 1. 2243 */ 2244 case PMC_EV_IAP_EVENT_11H_00H: 2245 case PMC_EV_IAP_EVENT_12H_00H: 2246 case PMC_EV_IAP_EVENT_13H_00H: 2247 mask = (1 << 1); 2248 break; 2249 2250 default: 2251 mask = ~0; /* Any row index is ok. */ 2252 } 2253 2254 return (mask & (1 << ri)); 2255} 2256 2257static int 2258iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2259 const struct pmc_op_pmcallocate *a) 2260{ 2261 int arch, n, model; 2262 enum pmc_event ev, map; 2263 struct iap_event_descr *ie; 2264 uint32_t c, caps, config, cpuflag, evsel, mask; 2265 2266 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2267 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2268 KASSERT(ri >= 0 && ri < core_iap_npmc, 2269 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2270 2271 /* check requested capabilities */ 2272 caps = a->pm_caps; 2273 if ((IAP_PMC_CAPS & caps) != caps) 2274 return (EPERM); 2275 map = 0; /* XXX: silent GCC warning */ 2276 arch = iap_is_event_architectural(pm->pm_event, &map); 2277 if (arch == EV_IS_ARCH_NOTSUPP) 2278 return (EOPNOTSUPP); 2279 else if (arch == EV_IS_ARCH_SUPP) 2280 ev = map; 2281 else 2282 ev = pm->pm_event; 2283 2284 /* 2285 * A small number of events are not supported in all the 2286 * processors based on a given microarchitecture. 2287 */ 2288 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2289 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2290 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2291 return (EINVAL); 2292 } 2293 2294 switch (core_cputype) { 2295 case PMC_CPU_INTEL_COREI7: 2296 case PMC_CPU_INTEL_NEHALEM_EX: 2297 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2298 return (EINVAL); 2299 break; 2300 case PMC_CPU_INTEL_SKYLAKE: 2301 case PMC_CPU_INTEL_SKYLAKE_XEON: 2302 case PMC_CPU_INTEL_BROADWELL: 2303 case PMC_CPU_INTEL_BROADWELL_XEON: 2304 case PMC_CPU_INTEL_SANDYBRIDGE: 2305 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2306 case PMC_CPU_INTEL_IVYBRIDGE: 2307 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2308 case PMC_CPU_INTEL_HASWELL: 2309 case PMC_CPU_INTEL_HASWELL_XEON: 2310 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2311 return (EINVAL); 2312 break; 2313 case PMC_CPU_INTEL_WESTMERE: 2314 case PMC_CPU_INTEL_WESTMERE_EX: 2315 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2316 return (EINVAL); 2317 break; 2318 default: 2319 if (iap_event_ok_on_counter(ev, ri) == 0) 2320 return (EINVAL); 2321 } 2322 2323 /* 2324 * Look for an event descriptor with matching CPU and event id 2325 * fields. 2326 */ 2327 2328 switch (core_cputype) { 2329 default: 2330 case PMC_CPU_INTEL_ATOM: 2331 cpuflag = IAP_F_CA; 2332 break; 2333 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2334 cpuflag = IAP_F_CAS; 2335 break; 2336 case PMC_CPU_INTEL_SKYLAKE_XEON: 2337 cpuflag = IAP_F_SLX; 2338 break; 2339 case PMC_CPU_INTEL_SKYLAKE: 2340 cpuflag = IAP_F_SL; 2341 break; 2342 case PMC_CPU_INTEL_BROADWELL_XEON: 2343 cpuflag = IAP_F_BWX; 2344 break; 2345 case PMC_CPU_INTEL_BROADWELL: 2346 cpuflag = IAP_F_BW; 2347 break; 2348 case PMC_CPU_INTEL_CORE: 2349 cpuflag = IAP_F_CC; 2350 break; 2351 case PMC_CPU_INTEL_CORE2: 2352 cpuflag = IAP_F_CC2; 2353 break; 2354 case PMC_CPU_INTEL_CORE2EXTREME: 2355 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2356 break; 2357 case PMC_CPU_INTEL_COREI7: 2358 cpuflag = IAP_F_I7; 2359 break; 2360 case PMC_CPU_INTEL_HASWELL: 2361 cpuflag = IAP_F_HW; 2362 break; 2363 case PMC_CPU_INTEL_HASWELL_XEON: 2364 cpuflag = IAP_F_HWX; 2365 break; 2366 case PMC_CPU_INTEL_IVYBRIDGE: 2367 cpuflag = IAP_F_IB; 2368 break; 2369 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2370 cpuflag = IAP_F_IBX; 2371 break; 2372 case PMC_CPU_INTEL_SANDYBRIDGE: 2373 cpuflag = IAP_F_SB; 2374 break; 2375 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2376 cpuflag = IAP_F_SBX; 2377 break; 2378 case PMC_CPU_INTEL_WESTMERE: 2379 cpuflag = IAP_F_WM; 2380 break; 2381 } 2382 2383 for (n = 0, ie = iap_events; n < nitems(iap_events); n++, ie++) 2384 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2385 break; 2386 2387 if (n == nitems(iap_events)) 2388 return (EINVAL); 2389 2390 /* 2391 * A matching event descriptor has been found, so start 2392 * assembling the contents of the event select register. 2393 */ 2394 evsel = ie->iap_evcode; 2395 2396 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2397 2398 /* 2399 * If the event uses a fixed umask value, reject any umask 2400 * bits set by the user. 2401 */ 2402 if (ie->iap_flags & IAP_F_FM) { 2403 2404 if (IAP_UMASK(config) != 0) 2405 return (EINVAL); 2406 2407 evsel |= (ie->iap_umask << 8); 2408 2409 } else { 2410 2411 /* 2412 * Otherwise, the UMASK value needs to be taken from 2413 * the MD fields of the allocation request. Reject 2414 * requests that specify reserved bits. 2415 */ 2416 2417 mask = 0; 2418 2419 if (ie->iap_umask & IAP_M_CORE) { 2420 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2421 c != IAP_CORE_THIS) 2422 return (EINVAL); 2423 mask |= IAP_F_CORE; 2424 } 2425 2426 if (ie->iap_umask & IAP_M_AGENT) 2427 mask |= IAP_F_AGENT; 2428 2429 if (ie->iap_umask & IAP_M_PREFETCH) { 2430 2431 if ((c = (config & IAP_F_PREFETCH)) == 2432 IAP_PREFETCH_RESERVED) 2433 return (EINVAL); 2434 2435 mask |= IAP_F_PREFETCH; 2436 } 2437 2438 if (ie->iap_umask & IAP_M_MESI) 2439 mask |= IAP_F_MESI; 2440 2441 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2442 mask |= IAP_F_SNOOPRESPONSE; 2443 2444 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2445 mask |= IAP_F_SNOOPTYPE; 2446 2447 if (ie->iap_umask & IAP_M_TRANSITION) 2448 mask |= IAP_F_TRANSITION; 2449 2450 /* 2451 * If bits outside of the allowed set of umask bits 2452 * are set, reject the request. 2453 */ 2454 if (config & ~mask) 2455 return (EINVAL); 2456 2457 evsel |= (config & mask); 2458 2459 } 2460 2461 /* 2462 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2463 */ 2464 if (core_cputype == PMC_CPU_INTEL_ATOM || 2465 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2466 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2467 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2468 evsel |= (config & IAP_ANY); 2469 else if (config & IAP_ANY) 2470 return (EINVAL); 2471 2472 /* 2473 * Check offcore response configuration. 2474 */ 2475 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2476 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2477 ev != PMC_EV_IAP_EVENT_BBH_01H) 2478 return (EINVAL); 2479 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2480 ev == PMC_EV_IAP_EVENT_BBH_01H) 2481 return (EINVAL); 2482 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2483 core_cputype == PMC_CPU_INTEL_WESTMERE || 2484 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2485 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2486 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2487 return (EINVAL); 2488 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2489 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2490 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2491 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2492 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2493 return (EINVAL); 2494 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2495 } 2496 2497 if (caps & PMC_CAP_THRESHOLD) 2498 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2499 if (caps & PMC_CAP_USER) 2500 evsel |= IAP_USR; 2501 if (caps & PMC_CAP_SYSTEM) 2502 evsel |= IAP_OS; 2503 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2504 evsel |= (IAP_OS | IAP_USR); 2505 if (caps & PMC_CAP_EDGE) 2506 evsel |= IAP_EDGE; 2507 if (caps & PMC_CAP_INVERT) 2508 evsel |= IAP_INV; 2509 if (caps & PMC_CAP_INTERRUPT) 2510 evsel |= IAP_INT; 2511 2512 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2513 2514 return (0); 2515} 2516 2517static int 2518iap_config_pmc(int cpu, int ri, struct pmc *pm) 2519{ 2520 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2521 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2522 2523 KASSERT(ri >= 0 && ri < core_iap_npmc, 2524 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2525 2526 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2527 2528 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2529 cpu)); 2530 2531 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2532 2533 return (0); 2534} 2535 2536static int 2537iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2538{ 2539 int error; 2540 struct pmc_hw *phw; 2541 char iap_name[PMC_NAME_MAX]; 2542 2543 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2544 2545 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2546 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2547 NULL)) != 0) 2548 return (error); 2549 2550 pi->pm_class = PMC_CLASS_IAP; 2551 2552 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2553 pi->pm_enabled = TRUE; 2554 *ppmc = phw->phw_pmc; 2555 } else { 2556 pi->pm_enabled = FALSE; 2557 *ppmc = NULL; 2558 } 2559 2560 return (0); 2561} 2562 2563static int 2564iap_get_config(int cpu, int ri, struct pmc **ppm) 2565{ 2566 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2567 2568 return (0); 2569} 2570 2571static int 2572iap_get_msr(int ri, uint32_t *msr) 2573{ 2574 KASSERT(ri >= 0 && ri < core_iap_npmc, 2575 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2576 2577 *msr = ri; 2578 2579 return (0); 2580} 2581 2582static int 2583iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2584{ 2585 struct pmc *pm; 2586 pmc_value_t tmp; 2587 2588 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2589 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2590 KASSERT(ri >= 0 && ri < core_iap_npmc, 2591 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2592 2593 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2594 2595 KASSERT(pm, 2596 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2597 ri)); 2598 2599 tmp = rdpmc(ri); 2600 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2601 *v = iap_perfctr_value_to_reload_count(tmp); 2602 else 2603 *v = tmp & ((1ULL << core_iap_width) - 1); 2604 2605 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2606 IAP_PMC0 + ri, *v); 2607 2608 return (0); 2609} 2610 2611static int 2612iap_release_pmc(int cpu, int ri, struct pmc *pm) 2613{ 2614 (void) pm; 2615 2616 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2617 pm); 2618 2619 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2620 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2621 KASSERT(ri >= 0 && ri < core_iap_npmc, 2622 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2623 2624 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2625 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2626 2627 return (0); 2628} 2629 2630static int 2631iap_start_pmc(int cpu, int ri) 2632{ 2633 struct pmc *pm; 2634 uint32_t evsel; 2635 struct core_cpu *cc; 2636 2637 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2638 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2639 KASSERT(ri >= 0 && ri < core_iap_npmc, 2640 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2641 2642 cc = core_pcpu[cpu]; 2643 pm = cc->pc_corepmcs[ri].phw_pmc; 2644 2645 KASSERT(pm, 2646 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2647 __LINE__, cpu, ri)); 2648 2649 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2650 2651 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2652 2653 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2654 cpu, ri, IAP_EVSEL0 + ri, evsel); 2655 2656 /* Event specific configuration. */ 2657 switch (pm->pm_event) { 2658 case PMC_EV_IAP_EVENT_B7H_01H: 2659 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2660 break; 2661 case PMC_EV_IAP_EVENT_BBH_01H: 2662 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2663 break; 2664 default: 2665 break; 2666 } 2667 2668 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2669 2670 if (core_cputype == PMC_CPU_INTEL_CORE) 2671 return (0); 2672 2673 do { 2674 cc->pc_resync = 0; 2675 cc->pc_globalctrl |= (1ULL << ri); 2676 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2677 } while (cc->pc_resync != 0); 2678 2679 return (0); 2680} 2681 2682static int 2683iap_stop_pmc(int cpu, int ri) 2684{ 2685 struct pmc *pm; 2686 struct core_cpu *cc; 2687 uint64_t msr; 2688 2689 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2690 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2691 KASSERT(ri >= 0 && ri < core_iap_npmc, 2692 ("[core,%d] illegal row index %d", __LINE__, ri)); 2693 2694 cc = core_pcpu[cpu]; 2695 pm = cc->pc_corepmcs[ri].phw_pmc; 2696 2697 KASSERT(pm, 2698 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2699 cpu, ri)); 2700 2701 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2702 2703 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2704 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2705 2706 if (core_cputype == PMC_CPU_INTEL_CORE) 2707 return (0); 2708 2709 msr = 0; 2710 do { 2711 cc->pc_resync = 0; 2712 cc->pc_globalctrl &= ~(1ULL << ri); 2713 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2714 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2715 } while (cc->pc_resync != 0); 2716 2717 return (0); 2718} 2719 2720static int 2721iap_write_pmc(int cpu, int ri, pmc_value_t v) 2722{ 2723 struct pmc *pm; 2724 struct core_cpu *cc; 2725 2726 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2727 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2728 KASSERT(ri >= 0 && ri < core_iap_npmc, 2729 ("[core,%d] illegal row index %d", __LINE__, ri)); 2730 2731 cc = core_pcpu[cpu]; 2732 pm = cc->pc_corepmcs[ri].phw_pmc; 2733 2734 KASSERT(pm, 2735 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2736 cpu, ri)); 2737 2738 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2739 v = iap_reload_count_to_perfctr_value(v); 2740 2741 v &= (1ULL << core_iap_width) - 1; 2742 2743 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2744 IAP_PMC0 + ri, v); 2745 2746 /* 2747 * Write the new value to the counter (or it's alias). The 2748 * counter will be in a stopped state when the pcd_write() 2749 * entry point is called. 2750 */ 2751 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 2752 return (0); 2753} 2754 2755 2756static void 2757iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2758 int flags) 2759{ 2760 struct pmc_classdep *pcd; 2761 2762 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2763 2764 PMCDBG0(MDP,INI,1, "iap-initialize"); 2765 2766 /* Remember the set of architectural events supported. */ 2767 core_architectural_events = ~flags; 2768 2769 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2770 2771 pcd->pcd_caps = IAP_PMC_CAPS; 2772 pcd->pcd_class = PMC_CLASS_IAP; 2773 pcd->pcd_num = npmc; 2774 pcd->pcd_ri = md->pmd_npmc; 2775 pcd->pcd_width = pmcwidth; 2776 2777 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2778 pcd->pcd_config_pmc = iap_config_pmc; 2779 pcd->pcd_describe = iap_describe; 2780 pcd->pcd_get_config = iap_get_config; 2781 pcd->pcd_get_msr = iap_get_msr; 2782 pcd->pcd_pcpu_fini = core_pcpu_fini; 2783 pcd->pcd_pcpu_init = core_pcpu_init; 2784 pcd->pcd_read_pmc = iap_read_pmc; 2785 pcd->pcd_release_pmc = iap_release_pmc; 2786 pcd->pcd_start_pmc = iap_start_pmc; 2787 pcd->pcd_stop_pmc = iap_stop_pmc; 2788 pcd->pcd_write_pmc = iap_write_pmc; 2789 2790 md->pmd_npmc += npmc; 2791} 2792 2793static int 2794core_intr(int cpu, struct trapframe *tf) 2795{ 2796 pmc_value_t v; 2797 struct pmc *pm; 2798 struct core_cpu *cc; 2799 int error, found_interrupt, ri; 2800 uint64_t msr; 2801 2802 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2803 TRAPF_USERMODE(tf)); 2804 2805 found_interrupt = 0; 2806 cc = core_pcpu[cpu]; 2807 2808 for (ri = 0; ri < core_iap_npmc; ri++) { 2809 2810 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2811 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2812 continue; 2813 2814 if (!iap_pmc_has_overflowed(ri)) 2815 continue; 2816 2817 found_interrupt = 1; 2818 2819 if (pm->pm_state != PMC_STATE_RUNNING) 2820 continue; 2821 2822 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2823 TRAPF_USERMODE(tf)); 2824 2825 v = pm->pm_sc.pm_reloadcount; 2826 v = iap_reload_count_to_perfctr_value(v); 2827 2828 /* 2829 * Stop the counter, reload it but only restart it if 2830 * the PMC is not stalled. 2831 */ 2832 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2833 wrmsr(IAP_EVSEL0 + ri, msr); 2834 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 2835 2836 if (error) 2837 continue; 2838 2839 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2840 IAP_EN)); 2841 } 2842 2843 if (found_interrupt) 2844 lapic_reenable_pmc(); 2845 2846 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2847 &pmc_stats.pm_intr_ignored, 1); 2848 2849 return (found_interrupt); 2850} 2851 2852static int 2853core2_intr(int cpu, struct trapframe *tf) 2854{ 2855 int error, found_interrupt, n; 2856 uint64_t flag, intrstatus, intrenable, msr; 2857 struct pmc *pm; 2858 struct core_cpu *cc; 2859 pmc_value_t v; 2860 2861 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2862 TRAPF_USERMODE(tf)); 2863 2864 /* 2865 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2866 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2867 * the current set of interrupting PMCs and process these 2868 * after stopping them. 2869 */ 2870 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2871 intrenable = intrstatus & core_pmcmask; 2872 2873 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2874 (uintmax_t) intrstatus); 2875 2876 found_interrupt = 0; 2877 cc = core_pcpu[cpu]; 2878 2879 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2880 2881 cc->pc_globalctrl &= ~intrenable; 2882 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2883 2884 /* 2885 * Stop PMCs and clear overflow status bits. 2886 */ 2887 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2888 wrmsr(IA_GLOBAL_CTRL, msr); 2889 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2890 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2891 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2892 2893 /* 2894 * Look for interrupts from fixed function PMCs. 2895 */ 2896 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2897 n++, flag <<= 1) { 2898 2899 if ((intrstatus & flag) == 0) 2900 continue; 2901 2902 found_interrupt = 1; 2903 2904 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2905 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2906 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2907 continue; 2908 2909 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2910 TRAPF_USERMODE(tf)); 2911 if (error) 2912 intrenable &= ~flag; 2913 2914 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2915 2916 /* Reload sampling count. */ 2917 wrmsr(IAF_CTR0 + n, v); 2918 2919 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2920 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2921 } 2922 2923 /* 2924 * Process interrupts from the programmable counters. 2925 */ 2926 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2927 if ((intrstatus & flag) == 0) 2928 continue; 2929 2930 found_interrupt = 1; 2931 2932 pm = cc->pc_corepmcs[n].phw_pmc; 2933 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2934 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2935 continue; 2936 2937 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2938 TRAPF_USERMODE(tf)); 2939 if (error) 2940 intrenable &= ~flag; 2941 2942 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2943 2944 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2945 (uintmax_t) v); 2946 2947 /* Reload sampling count. */ 2948 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v); 2949 } 2950 2951 /* 2952 * Reenable all non-stalled PMCs. 2953 */ 2954 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2955 (uintmax_t) intrenable); 2956 2957 cc->pc_globalctrl |= intrenable; 2958 2959 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2960 2961 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2962 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2963 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2964 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2965 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2966 2967 if (found_interrupt) 2968 lapic_reenable_pmc(); 2969 2970 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2971 &pmc_stats.pm_intr_ignored, 1); 2972 2973 return (found_interrupt); 2974} 2975 2976int 2977pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2978{ 2979 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2980 int ipa_version, flags, nflags; 2981 2982 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2983 2984 ipa_version = (version_override > 0) ? version_override : 2985 cpuid[CORE_CPUID_EAX] & 0xFF; 2986 core_cputype = md->pmd_cputype; 2987 2988 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2989 core_cputype, maxcpu, ipa_version); 2990 2991 if (ipa_version < 1 || ipa_version > 4 || 2992 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2993 /* Unknown PMC architecture. */ 2994 printf("hwpc_core: unknown PMC architecture: %d\n", 2995 ipa_version); 2996 return (EPROGMISMATCH); 2997 } 2998 2999 core_iap_wroffset = 0; 3000 if (cpu_feature2 & CPUID2_PDCM) { 3001 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) { 3002 PMCDBG0(MDP, INI, 1, 3003 "core-init full-width write supported"); 3004 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0; 3005 } else 3006 PMCDBG0(MDP, INI, 1, 3007 "core-init full-width write NOT supported"); 3008 } else 3009 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported"); 3010 3011 core_pmcmask = 0; 3012 3013 /* 3014 * Initialize programmable counters. 3015 */ 3016 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 3017 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 3018 3019 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 3020 3021 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 3022 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 3023 3024 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 3025 3026 /* 3027 * Initialize fixed function counters, if present. 3028 */ 3029 if (core_cputype != PMC_CPU_INTEL_CORE) { 3030 core_iaf_ri = core_iap_npmc; 3031 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 3032 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 3033 3034 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 3035 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 3036 } 3037 3038 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 3039 core_iaf_ri); 3040 3041 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 3042 M_ZERO | M_WAITOK); 3043 3044 /* 3045 * Choose the appropriate interrupt handler. 3046 */ 3047 if (ipa_version == 1) 3048 md->pmd_intr = core_intr; 3049 else 3050 md->pmd_intr = core2_intr; 3051 3052 md->pmd_pcpu_fini = NULL; 3053 md->pmd_pcpu_init = NULL; 3054 3055 return (0); 3056} 3057 3058void 3059pmc_core_finalize(struct pmc_mdep *md) 3060{ 3061 PMCDBG0(MDP,INI,1, "core-finalize"); 3062 3063 free(core_pcpu, M_PMC); 3064 core_pcpu = NULL; 3065} 3066