hifn7751.c revision 119690
1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3104477Ssam/* 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9104477Ssam * 10104477Ssam * This driver is based on a previous driver by Invertex, for which they 11104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 12104477Ssam * requests to software@invertex.com. 13104477Ssam * 14104477Ssam * Redistribution and use in source and binary forms, with or without 15104477Ssam * modification, are permitted provided that the following conditions 16104477Ssam * are met: 17104477Ssam * 18104477Ssam * 1. Redistributions of source code must retain the above copyright 19104477Ssam * notice, this list of conditions and the following disclaimer. 20104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 21104477Ssam * notice, this list of conditions and the following disclaimer in the 22104477Ssam * documentation and/or other materials provided with the distribution. 23104477Ssam * 3. The name of the author may not be used to endorse or promote products 24104477Ssam * derived from this software without specific prior written permission. 25104477Ssam * 26104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36104477Ssam * 37104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 38104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 39104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40104477Ssam */ 41104477Ssam 42119418Sobrien#include <sys/cdefs.h> 43119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/hifn/hifn7751.c 119690 2003-09-02 17:30:40Z jhb $"); 44119418Sobrien 45104477Ssam/* 46104477Ssam * Driver for the Hifn 7751 encryption processor. 47104477Ssam */ 48112124Ssam#include "opt_hifn.h" 49104477Ssam 50104477Ssam#include <sys/param.h> 51104477Ssam#include <sys/systm.h> 52104477Ssam#include <sys/proc.h> 53104477Ssam#include <sys/errno.h> 54104477Ssam#include <sys/malloc.h> 55104477Ssam#include <sys/kernel.h> 56104477Ssam#include <sys/mbuf.h> 57104477Ssam#include <sys/lock.h> 58104477Ssam#include <sys/mutex.h> 59104477Ssam#include <sys/sysctl.h> 60104477Ssam 61104477Ssam#include <vm/vm.h> 62104477Ssam#include <vm/pmap.h> 63104477Ssam 64104477Ssam#include <machine/clock.h> 65104477Ssam#include <machine/bus.h> 66104477Ssam#include <machine/resource.h> 67104477Ssam#include <sys/bus.h> 68104477Ssam#include <sys/rman.h> 69104477Ssam 70104477Ssam#include <opencrypto/cryptodev.h> 71104477Ssam#include <sys/random.h> 72104477Ssam 73119280Simp#include <dev/pci/pcivar.h> 74119280Simp#include <dev/pci/pcireg.h> 75112124Ssam 76112124Ssam#ifdef HIFN_RNDTEST 77112124Ssam#include <dev/rndtest/rndtest.h> 78112124Ssam#endif 79104477Ssam#include <dev/hifn/hifn7751reg.h> 80104477Ssam#include <dev/hifn/hifn7751var.h> 81104477Ssam 82104477Ssam/* 83104477Ssam * Prototypes and count for the pci_device structure 84104477Ssam */ 85104477Ssamstatic int hifn_probe(device_t); 86104477Ssamstatic int hifn_attach(device_t); 87104477Ssamstatic int hifn_detach(device_t); 88104477Ssamstatic int hifn_suspend(device_t); 89104477Ssamstatic int hifn_resume(device_t); 90104477Ssamstatic void hifn_shutdown(device_t); 91104477Ssam 92104477Ssamstatic device_method_t hifn_methods[] = { 93104477Ssam /* Device interface */ 94104477Ssam DEVMETHOD(device_probe, hifn_probe), 95104477Ssam DEVMETHOD(device_attach, hifn_attach), 96104477Ssam DEVMETHOD(device_detach, hifn_detach), 97104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 98104477Ssam DEVMETHOD(device_resume, hifn_resume), 99104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 100104477Ssam 101104477Ssam /* bus interface */ 102104477Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 103104477Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 104104477Ssam 105104477Ssam { 0, 0 } 106104477Ssam}; 107104477Ssamstatic driver_t hifn_driver = { 108104477Ssam "hifn", 109104477Ssam hifn_methods, 110104477Ssam sizeof (struct hifn_softc) 111104477Ssam}; 112104477Ssamstatic devclass_t hifn_devclass; 113104477Ssam 114104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 115105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 116112124Ssam#ifdef HIFN_RNDTEST 117112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 118112124Ssam#endif 119104477Ssam 120104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 121104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 122104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 123104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 124104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 125104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 126104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 127104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 128104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 129104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 130104477Ssamstatic void hifn_sessions(struct hifn_softc *); 131104477Ssamstatic void hifn_intr(void *); 132104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 133104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 134104477Ssamstatic int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 135104477Ssamstatic int hifn_freesession(void *, u_int64_t); 136104477Ssamstatic int hifn_process(void *, struct cryptop *, int); 137104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 138104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 139104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 140104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 141104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 142104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 143104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 144104477Ssamstatic void hifn_rng(void *); 145104477Ssamstatic void hifn_tick(void *); 146104477Ssamstatic void hifn_abort(struct hifn_softc *); 147104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 148104477Ssam 149104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 150104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 151104477Ssam 152104477Ssamstatic __inline__ u_int32_t 153104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 154104477Ssam{ 155104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 156104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 157104477Ssam return (v); 158104477Ssam} 159104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 160104477Ssam 161104477Ssamstatic __inline__ u_int32_t 162104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 163104477Ssam{ 164104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 165104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 166104477Ssam return (v); 167104477Ssam} 168104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 169104477Ssam 170109596SsamSYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 171109596Ssam 172104477Ssam#ifdef HIFN_DEBUG 173104477Ssamstatic int hifn_debug = 0; 174109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 175109596Ssam 0, "control debugging msgs"); 176104477Ssam#endif 177104477Ssam 178104477Ssamstatic struct hifn_stats hifnstats; 179109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 180109596Ssam hifn_stats, "driver statistics"); 181112121Ssamstatic int hifn_maxbatch = 1; 182109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 183109596Ssam 0, "max ops to batch w/o interrupt"); 184104477Ssam 185104477Ssam/* 186104477Ssam * Probe for a supported device. The PCI vendor and device 187104477Ssam * IDs are used to detect devices we know how to handle. 188104477Ssam */ 189104477Ssamstatic int 190104477Ssamhifn_probe(device_t dev) 191104477Ssam{ 192104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 193104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 194104477Ssam return (0); 195104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 196104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 197104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 198104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 199104477Ssam return (0); 200104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 201104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 202104477Ssam return (0); 203104477Ssam return (ENXIO); 204104477Ssam} 205104477Ssam 206104477Ssamstatic void 207104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 208104477Ssam{ 209104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 210104477Ssam *paddr = segs->ds_addr; 211104477Ssam} 212104477Ssam 213104477Ssamstatic const char* 214104477Ssamhifn_partname(struct hifn_softc *sc) 215104477Ssam{ 216104477Ssam /* XXX sprintf numbers when not decoded */ 217104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 218104477Ssam case PCI_VENDOR_HIFN: 219104477Ssam switch (pci_get_device(sc->sc_dev)) { 220104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 221104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 222104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 223104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 224104477Ssam } 225104477Ssam return "Hifn unknown-part"; 226104477Ssam case PCI_VENDOR_INVERTEX: 227104477Ssam switch (pci_get_device(sc->sc_dev)) { 228104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 229104477Ssam } 230104477Ssam return "Invertex unknown-part"; 231104477Ssam case PCI_VENDOR_NETSEC: 232104477Ssam switch (pci_get_device(sc->sc_dev)) { 233104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 234104477Ssam } 235104477Ssam return "NetSec unknown-part"; 236104477Ssam } 237104477Ssam return "Unknown-vendor unknown-part"; 238104477Ssam} 239104477Ssam 240112124Ssamstatic void 241112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 242112124Ssam{ 243112124Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 244112124Ssam} 245112124Ssam 246104477Ssam/* 247104477Ssam * Attach an interface that successfully probed. 248104477Ssam */ 249104477Ssamstatic int 250104477Ssamhifn_attach(device_t dev) 251104477Ssam{ 252104477Ssam struct hifn_softc *sc = device_get_softc(dev); 253104477Ssam u_int32_t cmd; 254104477Ssam caddr_t kva; 255104477Ssam int rseg, rid; 256104477Ssam char rbase; 257104477Ssam u_int16_t ena, rev; 258104477Ssam 259104477Ssam KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 260104477Ssam bzero(sc, sizeof (*sc)); 261104477Ssam sc->sc_dev = dev; 262104477Ssam 263115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 264104477Ssam 265104477Ssam /* XXX handle power management */ 266104477Ssam 267104477Ssam /* 268104477Ssam * The 7951 has a random number generator and 269104477Ssam * public key support; note this. 270104477Ssam */ 271104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 272104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 273104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 274104477Ssam /* 275104477Ssam * The 7811 has a random number generator and 276104477Ssam * we also note it's identity 'cuz of some quirks. 277104477Ssam */ 278104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 279104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 280104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 281104477Ssam 282104477Ssam /* 283104477Ssam * Configure support for memory-mapped access to 284104477Ssam * registers and for DMA operations. 285104477Ssam */ 286104477Ssam#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 287104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 288104477Ssam cmd |= PCIM_ENA; 289104477Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 290104477Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 291104477Ssam if ((cmd & PCIM_ENA) != PCIM_ENA) { 292104477Ssam device_printf(dev, "failed to enable %s\n", 293104477Ssam (cmd & PCIM_ENA) == 0 ? 294104477Ssam "memory mapping & bus mastering" : 295104477Ssam (cmd & PCIM_CMD_MEMEN) == 0 ? 296104477Ssam "memory mapping" : "bus mastering"); 297104477Ssam goto fail_pci; 298104477Ssam } 299104477Ssam#undef PCIM_ENA 300104477Ssam 301104477Ssam /* 302104477Ssam * Setup PCI resources. Note that we record the bus 303104477Ssam * tag and handle for each register mapping, this is 304104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 305104477Ssam * and WRITE_REG_1 macros throughout the driver. 306104477Ssam */ 307104477Ssam rid = HIFN_BAR0; 308104477Ssam sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 309104477Ssam 0, ~0, 1, RF_ACTIVE); 310104477Ssam if (sc->sc_bar0res == NULL) { 311104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 312104477Ssam goto fail_pci; 313104477Ssam } 314104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 315104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 316104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 317104477Ssam 318104477Ssam rid = HIFN_BAR1; 319104477Ssam sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 320104477Ssam 0, ~0, 1, RF_ACTIVE); 321104477Ssam if (sc->sc_bar1res == NULL) { 322104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 323104477Ssam goto fail_io0; 324104477Ssam } 325104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 326104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 327104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 328104477Ssam 329104477Ssam hifn_set_retry(sc); 330104477Ssam 331104477Ssam /* 332104477Ssam * Setup the area where the Hifn DMA's descriptors 333104477Ssam * and associated data structures. 334104477Ssam */ 335104477Ssam if (bus_dma_tag_create(NULL, /* parent */ 336104477Ssam 1, 0, /* alignment,boundary */ 337104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 338104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 339104477Ssam NULL, NULL, /* filter, filterarg */ 340104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 341104477Ssam MAX_SCATTER, /* nsegments */ 342104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 343104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 344117126Sscottl NULL, /* lockfunc */ 345117126Sscottl NULL, /* lockarg */ 346104477Ssam &sc->sc_dmat)) { 347104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 348104477Ssam goto fail_io1; 349104477Ssam } 350104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 351104477Ssam device_printf(dev, "cannot create dma map\n"); 352104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 353104477Ssam goto fail_io1; 354104477Ssam } 355104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 356104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 357104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 358104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 359104477Ssam goto fail_io1; 360104477Ssam } 361104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 362104477Ssam sizeof (*sc->sc_dma), 363104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 364104477Ssam BUS_DMA_NOWAIT)) { 365104477Ssam device_printf(dev, "cannot load dma map\n"); 366104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 367104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 368104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 369104477Ssam goto fail_io1; 370104477Ssam } 371104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 372104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 373104477Ssam 374104477Ssam KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 375104477Ssam KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 376104477Ssam KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 377104477Ssam KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 378104477Ssam 379104477Ssam /* 380104477Ssam * Reset the board and do the ``secret handshake'' 381104477Ssam * to enable the crypto support. Then complete the 382104477Ssam * initialization procedure by setting up the interrupt 383104477Ssam * and hooking in to the system crypto support so we'll 384104477Ssam * get used for system services like the crypto device, 385104477Ssam * IPsec, RNG device, etc. 386104477Ssam */ 387104477Ssam hifn_reset_board(sc, 0); 388104477Ssam 389104477Ssam if (hifn_enable_crypto(sc) != 0) { 390104477Ssam device_printf(dev, "crypto enabling failed\n"); 391104477Ssam goto fail_mem; 392104477Ssam } 393104477Ssam hifn_reset_puc(sc); 394104477Ssam 395104477Ssam hifn_init_dma(sc); 396104477Ssam hifn_init_pci_registers(sc); 397104477Ssam 398104477Ssam if (hifn_ramtype(sc)) 399104477Ssam goto fail_mem; 400104477Ssam 401104477Ssam if (sc->sc_drammodel == 0) 402104477Ssam hifn_sramsize(sc); 403104477Ssam else 404104477Ssam hifn_dramsize(sc); 405104477Ssam 406104477Ssam /* 407104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 408104477Ssam * of the address lines were left floating 409104477Ssam */ 410104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 411104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 412104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 413104477Ssam sc->sc_ramsize >>= 1; 414104477Ssam 415104477Ssam /* 416104477Ssam * Arrange the interrupt line. 417104477Ssam */ 418104477Ssam rid = 0; 419104477Ssam sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 420104477Ssam 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 421104477Ssam if (sc->sc_irq == NULL) { 422104477Ssam device_printf(dev, "could not map interrupt\n"); 423104477Ssam goto fail_mem; 424104477Ssam } 425104477Ssam /* 426104477Ssam * NB: Network code assumes we are blocked with splimp() 427104477Ssam * so make sure the IRQ is marked appropriately. 428104477Ssam */ 429115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 430104477Ssam hifn_intr, sc, &sc->sc_intrhand)) { 431104477Ssam device_printf(dev, "could not setup interrupt\n"); 432104477Ssam goto fail_intr2; 433104477Ssam } 434104477Ssam 435104477Ssam hifn_sessions(sc); 436104477Ssam 437104477Ssam /* 438104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 439104477Ssam * from the 7951. 440104477Ssam */ 441104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 442104477Ssam 443104477Ssam rseg = sc->sc_ramsize / 1024; 444104477Ssam rbase = 'K'; 445104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 446104477Ssam rbase = 'M'; 447104477Ssam rseg /= 1024; 448104477Ssam } 449104477Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 450104477Ssam hifn_partname(sc), rev, 451104477Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's', 452104477Ssam sc->sc_maxses); 453104477Ssam 454104477Ssam sc->sc_cid = crypto_get_driverid(0); 455104477Ssam if (sc->sc_cid < 0) { 456104477Ssam device_printf(dev, "could not get crypto driver id\n"); 457104477Ssam goto fail_intr; 458104477Ssam } 459104477Ssam 460104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 461104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 462104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 463104477Ssam 464104477Ssam switch (ena) { 465104477Ssam case HIFN_PUSTAT_ENA_2: 466104477Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 467104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 468104477Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 469104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 470104477Ssam /*FALLTHROUGH*/ 471104477Ssam case HIFN_PUSTAT_ENA_1: 472104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 473104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 474104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 475104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 476104477Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 477104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 478104477Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 479104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 480104477Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 481104477Ssam hifn_newsession, hifn_freesession, hifn_process, sc); 482104477Ssam break; 483104477Ssam } 484104477Ssam 485104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 486104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 487104477Ssam 488104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 489104477Ssam hifn_init_pubrng(sc); 490104477Ssam 491119137Ssam callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 492104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 493104477Ssam 494104477Ssam return (0); 495104477Ssam 496104477Ssamfail_intr: 497104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 498104477Ssamfail_intr2: 499104477Ssam /* XXX don't store rid */ 500104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 501104477Ssamfail_mem: 502104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 503104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 504104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 505104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 506104477Ssam 507104477Ssam /* Turn off DMA polling */ 508104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 509104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 510104477Ssamfail_io1: 511104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 512104477Ssamfail_io0: 513104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 514104477Ssamfail_pci: 515104477Ssam mtx_destroy(&sc->sc_mtx); 516104477Ssam return (ENXIO); 517104477Ssam} 518104477Ssam 519104477Ssam/* 520104477Ssam * Detach an interface that successfully probed. 521104477Ssam */ 522104477Ssamstatic int 523104477Ssamhifn_detach(device_t dev) 524104477Ssam{ 525104477Ssam struct hifn_softc *sc = device_get_softc(dev); 526104477Ssam 527104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 528104477Ssam 529115748Ssam /* disable interrupts */ 530115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 531104477Ssam 532104477Ssam /*XXX other resources */ 533104477Ssam callout_stop(&sc->sc_tickto); 534104477Ssam callout_stop(&sc->sc_rngto); 535115848Ssam#ifdef HIFN_RNDTEST 536115848Ssam if (sc->sc_rndtest) 537115862Ssam rndtest_detach(sc->sc_rndtest); 538115848Ssam#endif 539104477Ssam 540104477Ssam /* Turn off DMA polling */ 541104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 542104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 543104477Ssam 544104477Ssam crypto_unregister_all(sc->sc_cid); 545104477Ssam 546104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 547104477Ssam 548104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 549104477Ssam /* XXX don't store rid */ 550104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 551104477Ssam 552104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 553104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 554104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 555104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 556104477Ssam 557104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 558104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 559104477Ssam 560104477Ssam mtx_destroy(&sc->sc_mtx); 561104477Ssam 562104477Ssam return (0); 563104477Ssam} 564104477Ssam 565104477Ssam/* 566104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 567104477Ssam * get confused by errant DMAs when rebooting. 568104477Ssam */ 569104477Ssamstatic void 570104477Ssamhifn_shutdown(device_t dev) 571104477Ssam{ 572104477Ssam#ifdef notyet 573104477Ssam hifn_stop(device_get_softc(dev)); 574104477Ssam#endif 575104477Ssam} 576104477Ssam 577104477Ssam/* 578104477Ssam * Device suspend routine. Stop the interface and save some PCI 579104477Ssam * settings in case the BIOS doesn't restore them properly on 580104477Ssam * resume. 581104477Ssam */ 582104477Ssamstatic int 583104477Ssamhifn_suspend(device_t dev) 584104477Ssam{ 585104477Ssam struct hifn_softc *sc = device_get_softc(dev); 586104477Ssam#ifdef notyet 587104477Ssam int i; 588104477Ssam 589104477Ssam hifn_stop(sc); 590104477Ssam for (i = 0; i < 5; i++) 591119690Sjhb sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 592104477Ssam sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 593104477Ssam sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 594104477Ssam sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 595104477Ssam sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 596104477Ssam#endif 597104477Ssam sc->sc_suspended = 1; 598104477Ssam 599104477Ssam return (0); 600104477Ssam} 601104477Ssam 602104477Ssam/* 603104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 604104477Ssam * doesn't, re-enable busmastering, and restart the interface if 605104477Ssam * appropriate. 606104477Ssam */ 607104477Ssamstatic int 608104477Ssamhifn_resume(device_t dev) 609104477Ssam{ 610104477Ssam struct hifn_softc *sc = device_get_softc(dev); 611104477Ssam#ifdef notyet 612104477Ssam int i; 613104477Ssam 614104477Ssam /* better way to do this? */ 615104477Ssam for (i = 0; i < 5; i++) 616119690Sjhb pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 617104477Ssam pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 618104477Ssam pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 619104477Ssam pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 620104477Ssam pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 621104477Ssam 622104477Ssam /* reenable busmastering */ 623104477Ssam pci_enable_busmaster(dev); 624104477Ssam pci_enable_io(dev, HIFN_RES); 625104477Ssam 626104477Ssam /* reinitialize interface if necessary */ 627104477Ssam if (ifp->if_flags & IFF_UP) 628104477Ssam rl_init(sc); 629104477Ssam#endif 630104477Ssam sc->sc_suspended = 0; 631104477Ssam 632104477Ssam return (0); 633104477Ssam} 634104477Ssam 635104477Ssamstatic int 636104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 637104477Ssam{ 638104477Ssam u_int32_t r; 639104477Ssam int i; 640104477Ssam 641112124Ssam#ifdef HIFN_RNDTEST 642112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 643112124Ssam if (sc->sc_rndtest) 644112124Ssam sc->sc_harvest = rndtest_harvest; 645112124Ssam else 646112124Ssam sc->sc_harvest = default_harvest; 647112124Ssam#else 648112124Ssam sc->sc_harvest = default_harvest; 649112124Ssam#endif 650104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 651104477Ssam /* Reset 7951 public key/rng engine */ 652104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 653104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 654104477Ssam 655104477Ssam for (i = 0; i < 100; i++) { 656104477Ssam DELAY(1000); 657104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 658104477Ssam HIFN_PUBRST_RESET) == 0) 659104477Ssam break; 660104477Ssam } 661104477Ssam 662104477Ssam if (i == 100) { 663104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 664104477Ssam return (1); 665104477Ssam } 666104477Ssam } 667104477Ssam 668104477Ssam /* Enable the rng, if available */ 669104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 670104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 671104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 672104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 673104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 674104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 675104477Ssam } 676104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 677104477Ssam HIFN_7811_RNGCFG_DEFL); 678104477Ssam r |= HIFN_7811_RNGENA_ENA; 679104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 680104477Ssam } else 681104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 682104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 683104477Ssam HIFN_RNGCFG_ENA); 684104477Ssam 685104477Ssam sc->sc_rngfirst = 1; 686104477Ssam if (hz >= 100) 687104477Ssam sc->sc_rnghz = hz / 100; 688104477Ssam else 689104477Ssam sc->sc_rnghz = 1; 690119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 691104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 692104477Ssam } 693104477Ssam 694104477Ssam /* Enable public key engine, if available */ 695104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 696104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 697104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 698104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 699104477Ssam } 700104477Ssam 701104477Ssam return (0); 702104477Ssam} 703104477Ssam 704104477Ssamstatic void 705104477Ssamhifn_rng(void *vsc) 706104477Ssam{ 707104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 708104477Ssam struct hifn_softc *sc = vsc; 709104477Ssam u_int32_t sts, num[2]; 710104477Ssam int i; 711104477Ssam 712104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 713104477Ssam for (i = 0; i < 5; i++) { 714104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 715104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 716104477Ssam device_printf(sc->sc_dev, 717104477Ssam "RNG underflow: disabling\n"); 718104477Ssam return; 719104477Ssam } 720104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 721104477Ssam break; 722104477Ssam 723104477Ssam /* 724104477Ssam * There are at least two words in the RNG FIFO 725104477Ssam * at this point. 726104477Ssam */ 727104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 728104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 729104477Ssam /* NB: discard first data read */ 730104477Ssam if (sc->sc_rngfirst) 731104477Ssam sc->sc_rngfirst = 0; 732104477Ssam else 733112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 734112124Ssam num, sizeof (num)); 735104477Ssam } 736104477Ssam } else { 737104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 738104477Ssam 739104477Ssam /* NB: discard first data read */ 740104477Ssam if (sc->sc_rngfirst) 741104477Ssam sc->sc_rngfirst = 0; 742104477Ssam else 743112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 744112124Ssam num, sizeof (num[0])); 745104477Ssam } 746104477Ssam 747104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 748104477Ssam#undef RANDOM_BITS 749104477Ssam} 750104477Ssam 751104477Ssamstatic void 752104477Ssamhifn_puc_wait(struct hifn_softc *sc) 753104477Ssam{ 754104477Ssam int i; 755104477Ssam 756104477Ssam for (i = 5000; i > 0; i--) { 757104477Ssam DELAY(1); 758104477Ssam if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 759104477Ssam break; 760104477Ssam } 761104477Ssam if (!i) 762104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 763104477Ssam} 764104477Ssam 765104477Ssam/* 766104477Ssam * Reset the processing unit. 767104477Ssam */ 768104477Ssamstatic void 769104477Ssamhifn_reset_puc(struct hifn_softc *sc) 770104477Ssam{ 771104477Ssam /* Reset processing unit */ 772104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 773104477Ssam hifn_puc_wait(sc); 774104477Ssam} 775104477Ssam 776104477Ssam/* 777104477Ssam * Set the Retry and TRDY registers; note that we set them to 778104477Ssam * zero because the 7811 locks up when forced to retry (section 779104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 780104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 781104477Ssam */ 782104477Ssamstatic void 783104477Ssamhifn_set_retry(struct hifn_softc *sc) 784104477Ssam{ 785104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 786104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 787104477Ssam pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 788104477Ssam} 789104477Ssam 790104477Ssam/* 791104477Ssam * Resets the board. Values in the regesters are left as is 792104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 793104477Ssam */ 794104477Ssamstatic void 795104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 796104477Ssam{ 797104477Ssam u_int32_t reg; 798104477Ssam 799104477Ssam /* 800104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 801104477Ssam * resetting the board and zeros out the other fields. 802104477Ssam */ 803104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 804104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 805104477Ssam 806104477Ssam /* 807104477Ssam * Now that polling has been disabled, we have to wait 1 ms 808104477Ssam * before resetting the board. 809104477Ssam */ 810104477Ssam DELAY(1000); 811104477Ssam 812104477Ssam /* Reset the DMA unit */ 813104477Ssam if (full) { 814104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 815104477Ssam DELAY(1000); 816104477Ssam } else { 817104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 818104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 819104477Ssam hifn_reset_puc(sc); 820104477Ssam } 821104477Ssam 822104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 823104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 824104477Ssam 825104477Ssam /* Bring dma unit out of reset */ 826104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 827104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 828104477Ssam 829104477Ssam hifn_puc_wait(sc); 830104477Ssam hifn_set_retry(sc); 831104477Ssam 832104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 833104477Ssam for (reg = 0; reg < 1000; reg++) { 834104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 835104477Ssam HIFN_MIPSRST_CRAMINIT) 836104477Ssam break; 837104477Ssam DELAY(1000); 838104477Ssam } 839104477Ssam if (reg == 1000) 840104477Ssam printf(": cram init timeout\n"); 841104477Ssam } 842104477Ssam} 843104477Ssam 844104477Ssamstatic u_int32_t 845104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 846104477Ssam{ 847104477Ssam int i; 848104477Ssam u_int32_t v; 849104477Ssam 850104477Ssam for (i = 0; i < cnt; i++) { 851104477Ssam 852104477Ssam /* get the parity */ 853104477Ssam v = a & 0x80080125; 854104477Ssam v ^= v >> 16; 855104477Ssam v ^= v >> 8; 856104477Ssam v ^= v >> 4; 857104477Ssam v ^= v >> 2; 858104477Ssam v ^= v >> 1; 859104477Ssam 860104477Ssam a = (v & 1) ^ (a << 1); 861104477Ssam } 862104477Ssam 863104477Ssam return a; 864104477Ssam} 865104477Ssam 866104477Ssamstruct pci2id { 867104477Ssam u_short pci_vendor; 868104477Ssam u_short pci_prod; 869104477Ssam char card_id[13]; 870104477Ssam}; 871104477Ssamstatic struct pci2id pci2id[] = { 872104477Ssam { 873104477Ssam PCI_VENDOR_HIFN, 874104477Ssam PCI_PRODUCT_HIFN_7951, 875104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 876104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 877104477Ssam }, { 878104477Ssam PCI_VENDOR_NETSEC, 879104477Ssam PCI_PRODUCT_NETSEC_7751, 880104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 881104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 882104477Ssam }, { 883104477Ssam PCI_VENDOR_INVERTEX, 884104477Ssam PCI_PRODUCT_INVERTEX_AEON, 885104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 886104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 887104477Ssam }, { 888104477Ssam PCI_VENDOR_HIFN, 889104477Ssam PCI_PRODUCT_HIFN_7811, 890104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 891104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 892104477Ssam }, { 893104477Ssam /* 894104477Ssam * Other vendors share this PCI ID as well, such as 895104477Ssam * http://www.powercrypt.com, and obviously they also 896104477Ssam * use the same key. 897104477Ssam */ 898104477Ssam PCI_VENDOR_HIFN, 899104477Ssam PCI_PRODUCT_HIFN_7751, 900104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 901104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 902104477Ssam }, 903104477Ssam}; 904104477Ssam 905104477Ssam/* 906104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 907104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 908104477Ssam * as enabling crypto twice will lock the board. 909104477Ssam */ 910104477Ssamstatic int 911104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 912104477Ssam{ 913104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 914104477Ssam char *offtbl = NULL; 915104477Ssam 916104477Ssam for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 917104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 918104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 919104477Ssam offtbl = pci2id[i].card_id; 920104477Ssam break; 921104477Ssam } 922104477Ssam } 923104477Ssam if (offtbl == NULL) { 924104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 925104477Ssam return (1); 926104477Ssam } 927104477Ssam 928104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 929104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 930104477Ssam 931104477Ssam /* 932104477Ssam * The RAM config register's encrypt level bit needs to be set before 933104477Ssam * every read performed on the encryption level register. 934104477Ssam */ 935104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 936104477Ssam 937104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 938104477Ssam 939104477Ssam /* 940104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 941104477Ssam * next reboot. 942104477Ssam */ 943104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 944104477Ssam#ifdef HIFN_DEBUG 945104477Ssam if (hifn_debug) 946104477Ssam device_printf(sc->sc_dev, 947104477Ssam "Strong crypto already enabled!\n"); 948104477Ssam#endif 949104477Ssam goto report; 950104477Ssam } 951104477Ssam 952104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 953104477Ssam#ifdef HIFN_DEBUG 954104477Ssam if (hifn_debug) 955104477Ssam device_printf(sc->sc_dev, 956104477Ssam "Unknown encryption level 0x%x\n", encl); 957104477Ssam#endif 958104477Ssam return 1; 959104477Ssam } 960104477Ssam 961104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 962104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 963104477Ssam DELAY(1000); 964104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 965104477Ssam DELAY(1000); 966104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 967104477Ssam DELAY(1000); 968104477Ssam 969104477Ssam for (i = 0; i <= 12; i++) { 970104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 971104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 972104477Ssam 973104477Ssam DELAY(1000); 974104477Ssam } 975104477Ssam 976104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 977104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 978104477Ssam 979104477Ssam#ifdef HIFN_DEBUG 980104477Ssam if (hifn_debug) { 981104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 982104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 983104477Ssam "locked until next system reset!\n"); 984104477Ssam else 985104477Ssam device_printf(sc->sc_dev, "Engine enabled " 986104477Ssam "successfully!\n"); 987104477Ssam } 988104477Ssam#endif 989104477Ssam 990104477Ssamreport: 991104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 992104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 993104477Ssam 994104477Ssam switch (encl) { 995104477Ssam case HIFN_PUSTAT_ENA_1: 996104477Ssam case HIFN_PUSTAT_ENA_2: 997104477Ssam break; 998104477Ssam case HIFN_PUSTAT_ENA_0: 999104477Ssam default: 1000104477Ssam device_printf(sc->sc_dev, "disabled"); 1001104477Ssam break; 1002104477Ssam } 1003104477Ssam 1004104477Ssam return 0; 1005104477Ssam} 1006104477Ssam 1007104477Ssam/* 1008104477Ssam * Give initial values to the registers listed in the "Register Space" 1009104477Ssam * section of the HIFN Software Development reference manual. 1010104477Ssam */ 1011104477Ssamstatic void 1012104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1013104477Ssam{ 1014104477Ssam /* write fixed values needed by the Initialization registers */ 1015104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1016104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1017104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1018104477Ssam 1019104477Ssam /* write all 4 ring address registers */ 1020104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1021104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1022104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1023104477Ssam offsetof(struct hifn_dma, srcr[0])); 1024104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1025104477Ssam offsetof(struct hifn_dma, dstr[0])); 1026104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1027104477Ssam offsetof(struct hifn_dma, resr[0])); 1028104477Ssam 1029104477Ssam DELAY(2000); 1030104477Ssam 1031104477Ssam /* write status register */ 1032104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1033104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1034104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1035104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1036104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1037104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1038104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1039104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1040104477Ssam HIFN_DMACSR_S_WAIT | 1041104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1042104477Ssam HIFN_DMACSR_C_WAIT | 1043104477Ssam HIFN_DMACSR_ENGINE | 1044104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1045104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1046104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1047104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1048104477Ssam 1049104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1050104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1051104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1052104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1053104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1054104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1055104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1056104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1057104477Ssam 1058104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1059104477Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1060104477Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1061104477Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1062104477Ssam 1063104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1064104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1065104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1066104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1067104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1068104477Ssam} 1069104477Ssam 1070104477Ssam/* 1071104477Ssam * The maximum number of sessions supported by the card 1072104477Ssam * is dependent on the amount of context ram, which 1073104477Ssam * encryption algorithms are enabled, and how compression 1074104477Ssam * is configured. This should be configured before this 1075104477Ssam * routine is called. 1076104477Ssam */ 1077104477Ssamstatic void 1078104477Ssamhifn_sessions(struct hifn_softc *sc) 1079104477Ssam{ 1080104477Ssam u_int32_t pucnfg; 1081104477Ssam int ctxsize; 1082104477Ssam 1083104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1084104477Ssam 1085104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1086104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1087104477Ssam ctxsize = 128; 1088104477Ssam else 1089104477Ssam ctxsize = 512; 1090104477Ssam sc->sc_maxses = 1 + 1091104477Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1092104477Ssam } else 1093104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1094104477Ssam 1095104477Ssam if (sc->sc_maxses > 2048) 1096104477Ssam sc->sc_maxses = 2048; 1097104477Ssam} 1098104477Ssam 1099104477Ssam/* 1100104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1101104477Ssam * state when this is called. 1102104477Ssam */ 1103104477Ssamstatic int 1104104477Ssamhifn_ramtype(struct hifn_softc *sc) 1105104477Ssam{ 1106104477Ssam u_int8_t data[8], dataexpect[8]; 1107104477Ssam int i; 1108104477Ssam 1109104477Ssam for (i = 0; i < sizeof(data); i++) 1110104477Ssam data[i] = dataexpect[i] = 0x55; 1111104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1112104477Ssam return (-1); 1113104477Ssam if (hifn_readramaddr(sc, 0, data)) 1114104477Ssam return (-1); 1115104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1116104477Ssam sc->sc_drammodel = 1; 1117104477Ssam return (0); 1118104477Ssam } 1119104477Ssam 1120104477Ssam for (i = 0; i < sizeof(data); i++) 1121104477Ssam data[i] = dataexpect[i] = 0xaa; 1122104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1123104477Ssam return (-1); 1124104477Ssam if (hifn_readramaddr(sc, 0, data)) 1125104477Ssam return (-1); 1126104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1127104477Ssam sc->sc_drammodel = 1; 1128104477Ssam return (0); 1129104477Ssam } 1130104477Ssam 1131104477Ssam return (0); 1132104477Ssam} 1133104477Ssam 1134104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1135104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1136104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1137104477Ssam 1138104477Ssamstatic int 1139104477Ssamhifn_sramsize(struct hifn_softc *sc) 1140104477Ssam{ 1141104477Ssam u_int32_t a; 1142104477Ssam u_int8_t data[8]; 1143104477Ssam u_int8_t dataexpect[sizeof(data)]; 1144104477Ssam int32_t i; 1145104477Ssam 1146104477Ssam for (i = 0; i < sizeof(data); i++) 1147104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1148104477Ssam 1149104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1150104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1151104477Ssam bcopy(&i, data, sizeof(i)); 1152104477Ssam hifn_writeramaddr(sc, a, data); 1153104477Ssam } 1154104477Ssam 1155104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1156104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1157104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1158104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1159104477Ssam return (0); 1160104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1161104477Ssam return (0); 1162104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1163104477Ssam } 1164104477Ssam 1165104477Ssam return (0); 1166104477Ssam} 1167104477Ssam 1168104477Ssam/* 1169104477Ssam * XXX For dram boards, one should really try all of the 1170104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1171104477Ssam * is already set up correctly. 1172104477Ssam */ 1173104477Ssamstatic int 1174104477Ssamhifn_dramsize(struct hifn_softc *sc) 1175104477Ssam{ 1176104477Ssam u_int32_t cnfg; 1177104477Ssam 1178104477Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1179104477Ssam HIFN_PUCNFG_DRAMMASK; 1180104477Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1181104477Ssam return (0); 1182104477Ssam} 1183104477Ssam 1184104477Ssamstatic void 1185104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1186104477Ssam{ 1187104477Ssam struct hifn_dma *dma = sc->sc_dma; 1188104477Ssam 1189104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1190104477Ssam dma->cmdi = 0; 1191104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1192104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1193104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1194104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1195104477Ssam } 1196104477Ssam *cmdp = dma->cmdi++; 1197104477Ssam dma->cmdk = dma->cmdi; 1198104477Ssam 1199104477Ssam if (dma->srci == HIFN_D_SRC_RSIZE) { 1200104477Ssam dma->srci = 0; 1201104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1202104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1203104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1204104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1205104477Ssam } 1206104477Ssam *srcp = dma->srci++; 1207104477Ssam dma->srck = dma->srci; 1208104477Ssam 1209104477Ssam if (dma->dsti == HIFN_D_DST_RSIZE) { 1210104477Ssam dma->dsti = 0; 1211104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1212104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1213104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1214104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1215104477Ssam } 1216104477Ssam *dstp = dma->dsti++; 1217104477Ssam dma->dstk = dma->dsti; 1218104477Ssam 1219104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1220104477Ssam dma->resi = 0; 1221104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1222104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1223104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1224104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1225104477Ssam } 1226104477Ssam *resp = dma->resi++; 1227104477Ssam dma->resk = dma->resi; 1228104477Ssam} 1229104477Ssam 1230104477Ssamstatic int 1231104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1232104477Ssam{ 1233104477Ssam struct hifn_dma *dma = sc->sc_dma; 1234104477Ssam hifn_base_command_t wc; 1235104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1236104477Ssam int r, cmdi, resi, srci, dsti; 1237104477Ssam 1238104477Ssam wc.masks = htole16(3 << 13); 1239104477Ssam wc.session_num = htole16(addr >> 14); 1240104477Ssam wc.total_source_count = htole16(8); 1241104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1242104477Ssam 1243104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1244104477Ssam 1245104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1246104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1247104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1248104477Ssam 1249104477Ssam /* build write command */ 1250104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1251104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1252104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1253104477Ssam 1254104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1255104477Ssam + offsetof(struct hifn_dma, test_src)); 1256104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1257104477Ssam + offsetof(struct hifn_dma, test_dst)); 1258104477Ssam 1259104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1260104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1261104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1262104477Ssam dma->resr[resi].l = htole32(4 | masks); 1263104477Ssam 1264104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1265104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1266104477Ssam 1267104477Ssam for (r = 10000; r >= 0; r--) { 1268104477Ssam DELAY(10); 1269104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1270104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1271104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1272104477Ssam break; 1273104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1274104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1275104477Ssam } 1276104477Ssam if (r == 0) { 1277104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1278104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1279104477Ssam r = -1; 1280104477Ssam return (-1); 1281104477Ssam } else 1282104477Ssam r = 0; 1283104477Ssam 1284104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1285104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1286104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1287104477Ssam 1288104477Ssam return (r); 1289104477Ssam} 1290104477Ssam 1291104477Ssamstatic int 1292104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1293104477Ssam{ 1294104477Ssam struct hifn_dma *dma = sc->sc_dma; 1295104477Ssam hifn_base_command_t rc; 1296104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1297104477Ssam int r, cmdi, srci, dsti, resi; 1298104477Ssam 1299104477Ssam rc.masks = htole16(2 << 13); 1300104477Ssam rc.session_num = htole16(addr >> 14); 1301104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1302104477Ssam rc.total_dest_count = htole16(8); 1303104477Ssam 1304104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1305104477Ssam 1306104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1307104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1308104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1309104477Ssam 1310104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1311104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1312104477Ssam 1313104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1314104477Ssam offsetof(struct hifn_dma, test_src)); 1315104477Ssam dma->test_src = 0; 1316104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1317104477Ssam offsetof(struct hifn_dma, test_dst)); 1318104477Ssam dma->test_dst = 0; 1319104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1320104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1321104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1322104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1323104477Ssam 1324104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1325104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1326104477Ssam 1327104477Ssam for (r = 10000; r >= 0; r--) { 1328104477Ssam DELAY(10); 1329104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1330104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1331104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1332104477Ssam break; 1333104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1334104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1335104477Ssam } 1336104477Ssam if (r == 0) { 1337104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1338104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1339104477Ssam r = -1; 1340104477Ssam } else { 1341104477Ssam r = 0; 1342104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1343104477Ssam } 1344104477Ssam 1345104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1346104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1347104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1348104477Ssam 1349104477Ssam return (r); 1350104477Ssam} 1351104477Ssam 1352104477Ssam/* 1353104477Ssam * Initialize the descriptor rings. 1354104477Ssam */ 1355104477Ssamstatic void 1356104477Ssamhifn_init_dma(struct hifn_softc *sc) 1357104477Ssam{ 1358104477Ssam struct hifn_dma *dma = sc->sc_dma; 1359104477Ssam int i; 1360104477Ssam 1361104477Ssam hifn_set_retry(sc); 1362104477Ssam 1363104477Ssam /* initialize static pointer values */ 1364104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1365104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1366104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1367104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1368104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1369104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1370104477Ssam 1371104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1372104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1373104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1374104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1375104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1376104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1377104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1378104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1379104477Ssam 1380104477Ssam dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1381104477Ssam dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1382104477Ssam dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1383104477Ssam} 1384104477Ssam 1385104477Ssam/* 1386104477Ssam * Writes out the raw command buffer space. Returns the 1387104477Ssam * command buffer size. 1388104477Ssam */ 1389104477Ssamstatic u_int 1390104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1391104477Ssam{ 1392104477Ssam u_int8_t *buf_pos; 1393104477Ssam hifn_base_command_t *base_cmd; 1394104477Ssam hifn_mac_command_t *mac_cmd; 1395104477Ssam hifn_crypt_command_t *cry_cmd; 1396104477Ssam int using_mac, using_crypt, len; 1397104477Ssam u_int32_t dlen, slen; 1398104477Ssam 1399104477Ssam buf_pos = buf; 1400104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1401104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1402104477Ssam 1403104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1404104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1405104477Ssam slen = cmd->src_mapsize; 1406104477Ssam if (cmd->sloplen) 1407104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1408104477Ssam else 1409104477Ssam dlen = cmd->dst_mapsize; 1410104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1411104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1412104477Ssam dlen >>= 16; 1413104477Ssam slen >>= 16; 1414104477Ssam base_cmd->session_num = htole16(cmd->session_num | 1415104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1416104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1417104477Ssam buf_pos += sizeof(hifn_base_command_t); 1418104477Ssam 1419104477Ssam if (using_mac) { 1420104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1421104477Ssam dlen = cmd->maccrd->crd_len; 1422104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1423104477Ssam dlen >>= 16; 1424104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1425104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1426104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1427104477Ssam mac_cmd->reserved = 0; 1428104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1429104477Ssam } 1430104477Ssam 1431104477Ssam if (using_crypt) { 1432104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1433104477Ssam dlen = cmd->enccrd->crd_len; 1434104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1435104477Ssam dlen >>= 16; 1436104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1437104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1438104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1439104477Ssam cry_cmd->reserved = 0; 1440104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1441104477Ssam } 1442104477Ssam 1443104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1444104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1445104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1446104477Ssam } 1447104477Ssam 1448104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1449104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1450104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1451104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1452104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1453104477Ssam break; 1454104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1455104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1456104477Ssam buf_pos += cmd->cklen; 1457104477Ssam break; 1458104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1459104477Ssam len = 256; 1460104477Ssam do { 1461104477Ssam int clen; 1462104477Ssam 1463104477Ssam clen = MIN(cmd->cklen, len); 1464104477Ssam bcopy(cmd->ck, buf_pos, clen); 1465104477Ssam len -= clen; 1466104477Ssam buf_pos += clen; 1467104477Ssam } while (len > 0); 1468104477Ssam bzero(buf_pos, 4); 1469104477Ssam buf_pos += 4; 1470104477Ssam break; 1471104477Ssam } 1472104477Ssam } 1473104477Ssam 1474104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1475104477Ssam bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1476104477Ssam buf_pos += HIFN_IV_LENGTH; 1477104477Ssam } 1478104477Ssam 1479104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1480104477Ssam bzero(buf_pos, 8); 1481104477Ssam buf_pos += 8; 1482104477Ssam } 1483104477Ssam 1484104477Ssam return (buf_pos - buf); 1485104477Ssam} 1486104477Ssam 1487104477Ssamstatic int 1488104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1489104477Ssam{ 1490104477Ssam int i; 1491104477Ssam 1492104477Ssam for (i = 0; i < op->nsegs; i++) { 1493104477Ssam if (op->segs[i].ds_addr & 3) 1494104477Ssam return (0); 1495104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1496104477Ssam return (0); 1497104477Ssam } 1498104477Ssam return (1); 1499104477Ssam} 1500104477Ssam 1501104477Ssamstatic int 1502104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1503104477Ssam{ 1504104477Ssam struct hifn_dma *dma = sc->sc_dma; 1505104477Ssam struct hifn_operand *dst = &cmd->dst; 1506104477Ssam u_int32_t p, l; 1507104477Ssam int idx, used = 0, i; 1508104477Ssam 1509104477Ssam idx = dma->dsti; 1510104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1511104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1512104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1513104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1514104477Ssam HIFN_DSTR_SYNC(sc, idx, 1515104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1516104477Ssam used++; 1517104477Ssam 1518104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1519104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1520104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1521104477Ssam HIFN_DSTR_SYNC(sc, idx, 1522104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1523104477Ssam idx = 0; 1524104477Ssam } 1525104477Ssam } 1526104477Ssam 1527104477Ssam if (cmd->sloplen == 0) { 1528104477Ssam p = dst->segs[i].ds_addr; 1529104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1530104477Ssam dst->segs[i].ds_len; 1531104477Ssam } else { 1532104477Ssam p = sc->sc_dma_physaddr + 1533104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1534104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1535104477Ssam sizeof(u_int32_t); 1536104477Ssam 1537104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1538104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1539104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1540104477Ssam HIFN_D_MASKDONEIRQ | 1541104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1542104477Ssam HIFN_DSTR_SYNC(sc, idx, 1543104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1544104477Ssam used++; 1545104477Ssam 1546104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1547104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1548104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1549104477Ssam HIFN_DSTR_SYNC(sc, idx, 1550104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1551104477Ssam idx = 0; 1552104477Ssam } 1553104477Ssam } 1554104477Ssam } 1555104477Ssam dma->dstr[idx].p = htole32(p); 1556104477Ssam dma->dstr[idx].l = htole32(l); 1557104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1558104477Ssam used++; 1559104477Ssam 1560104477Ssam if (++idx == HIFN_D_DST_RSIZE) { 1561104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1562104477Ssam HIFN_D_MASKDONEIRQ); 1563104477Ssam HIFN_DSTR_SYNC(sc, idx, 1564104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1565104477Ssam idx = 0; 1566104477Ssam } 1567104477Ssam 1568104477Ssam dma->dsti = idx; 1569104477Ssam dma->dstu += used; 1570104477Ssam return (idx); 1571104477Ssam} 1572104477Ssam 1573104477Ssamstatic int 1574104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1575104477Ssam{ 1576104477Ssam struct hifn_dma *dma = sc->sc_dma; 1577104477Ssam struct hifn_operand *src = &cmd->src; 1578104477Ssam int idx, i; 1579104477Ssam u_int32_t last = 0; 1580104477Ssam 1581104477Ssam idx = dma->srci; 1582104477Ssam for (i = 0; i < src->nsegs; i++) { 1583104477Ssam if (i == src->nsegs - 1) 1584104477Ssam last = HIFN_D_LAST; 1585104477Ssam 1586104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1587104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1588104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1589104477Ssam HIFN_SRCR_SYNC(sc, idx, 1590104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1591104477Ssam 1592104477Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1593104477Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1594104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1595104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1596104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1597104477Ssam idx = 0; 1598104477Ssam } 1599104477Ssam } 1600104477Ssam dma->srci = idx; 1601104477Ssam dma->srcu += src->nsegs; 1602104477Ssam return (idx); 1603104477Ssam} 1604104477Ssam 1605104477Ssamstatic void 1606104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1607104477Ssam{ 1608104477Ssam struct hifn_operand *op = arg; 1609104477Ssam 1610104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1611104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1612104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1613104477Ssam op->mapsize = mapsize; 1614104477Ssam op->nsegs = nsegs; 1615104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1616104477Ssam} 1617104477Ssam 1618104477Ssamstatic int 1619104477Ssamhifn_crypto( 1620104477Ssam struct hifn_softc *sc, 1621104477Ssam struct hifn_command *cmd, 1622104477Ssam struct cryptop *crp, 1623104477Ssam int hint) 1624104477Ssam{ 1625104477Ssam struct hifn_dma *dma = sc->sc_dma; 1626104477Ssam u_int32_t cmdlen; 1627104477Ssam int cmdi, resi, err = 0; 1628104477Ssam 1629104477Ssam /* 1630104477Ssam * need 1 cmd, and 1 res 1631104477Ssam * 1632104477Ssam * NB: check this first since it's easy. 1633104477Ssam */ 1634115748Ssam HIFN_LOCK(sc); 1635104477Ssam if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1636104477Ssam (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1637104477Ssam#ifdef HIFN_DEBUG 1638104477Ssam if (hifn_debug) { 1639104477Ssam device_printf(sc->sc_dev, 1640104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1641104477Ssam dma->cmdu, dma->resu); 1642104477Ssam } 1643104477Ssam#endif 1644104477Ssam hifnstats.hst_nomem_cr++; 1645115748Ssam HIFN_UNLOCK(sc); 1646104477Ssam return (ERESTART); 1647104477Ssam } 1648104477Ssam 1649104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1650104477Ssam hifnstats.hst_nomem_map++; 1651115748Ssam HIFN_UNLOCK(sc); 1652104477Ssam return (ENOMEM); 1653104477Ssam } 1654104477Ssam 1655104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1656104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1657104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1658104477Ssam hifnstats.hst_nomem_load++; 1659104477Ssam err = ENOMEM; 1660104477Ssam goto err_srcmap1; 1661104477Ssam } 1662104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1663104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1664104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1665104477Ssam hifnstats.hst_nomem_load++; 1666104477Ssam err = ENOMEM; 1667104477Ssam goto err_srcmap1; 1668104477Ssam } 1669104477Ssam } else { 1670104477Ssam err = EINVAL; 1671104477Ssam goto err_srcmap1; 1672104477Ssam } 1673104477Ssam 1674104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1675104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1676104477Ssam cmd->dst = cmd->src; 1677104477Ssam } else { 1678104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1679104477Ssam err = EINVAL; 1680104477Ssam goto err_srcmap; 1681104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1682104477Ssam int totlen, len; 1683104477Ssam struct mbuf *m, *m0, *mlast; 1684104477Ssam 1685104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1686104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1687104477Ssam hifnstats.hst_unaligned++; 1688104477Ssam /* 1689104477Ssam * Source is not aligned on a longword boundary. 1690104477Ssam * Copy the data to insure alignment. If we fail 1691104477Ssam * to allocate mbufs or clusters while doing this 1692104477Ssam * we return ERESTART so the operation is requeued 1693104477Ssam * at the crypto later, but only if there are 1694104477Ssam * ops already posted to the hardware; otherwise we 1695104477Ssam * have no guarantee that we'll be re-entered. 1696104477Ssam */ 1697104477Ssam totlen = cmd->src_mapsize; 1698104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1699104477Ssam len = MHLEN; 1700111119Simp MGETHDR(m0, M_DONTWAIT, MT_DATA); 1701111119Simp if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1702108466Ssam m_free(m0); 1703108466Ssam m0 = NULL; 1704108466Ssam } 1705104477Ssam } else { 1706104477Ssam len = MLEN; 1707111119Simp MGET(m0, M_DONTWAIT, MT_DATA); 1708104477Ssam } 1709104477Ssam if (m0 == NULL) { 1710104477Ssam hifnstats.hst_nomem_mbuf++; 1711104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1712104477Ssam goto err_srcmap; 1713104477Ssam } 1714104477Ssam if (totlen >= MINCLSIZE) { 1715111119Simp MCLGET(m0, M_DONTWAIT); 1716104477Ssam if ((m0->m_flags & M_EXT) == 0) { 1717104477Ssam hifnstats.hst_nomem_mcl++; 1718104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1719104477Ssam m_freem(m0); 1720104477Ssam goto err_srcmap; 1721104477Ssam } 1722104477Ssam len = MCLBYTES; 1723104477Ssam } 1724104477Ssam totlen -= len; 1725104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1726104477Ssam mlast = m0; 1727104477Ssam 1728104477Ssam while (totlen > 0) { 1729111119Simp MGET(m, M_DONTWAIT, MT_DATA); 1730104477Ssam if (m == NULL) { 1731104477Ssam hifnstats.hst_nomem_mbuf++; 1732104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1733104477Ssam m_freem(m0); 1734104477Ssam goto err_srcmap; 1735104477Ssam } 1736104477Ssam len = MLEN; 1737104477Ssam if (totlen >= MINCLSIZE) { 1738111119Simp MCLGET(m, M_DONTWAIT); 1739104477Ssam if ((m->m_flags & M_EXT) == 0) { 1740104477Ssam hifnstats.hst_nomem_mcl++; 1741104477Ssam err = dma->cmdu ? ERESTART : ENOMEM; 1742104477Ssam mlast->m_next = m; 1743104477Ssam m_freem(m0); 1744104477Ssam goto err_srcmap; 1745104477Ssam } 1746104477Ssam len = MCLBYTES; 1747104477Ssam } 1748104477Ssam 1749104477Ssam m->m_len = len; 1750104477Ssam m0->m_pkthdr.len += len; 1751104477Ssam totlen -= len; 1752104477Ssam 1753104477Ssam mlast->m_next = m; 1754104477Ssam mlast = m; 1755104477Ssam } 1756104477Ssam cmd->dst_m = m0; 1757104477Ssam } 1758104477Ssam } 1759104477Ssam 1760104477Ssam if (cmd->dst_map == NULL) { 1761104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1762104477Ssam hifnstats.hst_nomem_map++; 1763104477Ssam err = ENOMEM; 1764104477Ssam goto err_srcmap; 1765104477Ssam } 1766104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1767104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1768104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1769104477Ssam hifnstats.hst_nomem_map++; 1770104477Ssam err = ENOMEM; 1771104477Ssam goto err_dstmap1; 1772104477Ssam } 1773104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1774104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1775104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1776104477Ssam hifnstats.hst_nomem_load++; 1777104477Ssam err = ENOMEM; 1778104477Ssam goto err_dstmap1; 1779104477Ssam } 1780104477Ssam } 1781104477Ssam } 1782104477Ssam 1783104477Ssam#ifdef HIFN_DEBUG 1784104477Ssam if (hifn_debug) { 1785104477Ssam device_printf(sc->sc_dev, 1786104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1787104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1788104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1789104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1790104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1791104477Ssam } 1792104477Ssam#endif 1793104477Ssam 1794104477Ssam if (cmd->src_map == cmd->dst_map) { 1795104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1796104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1797104477Ssam } else { 1798104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1799104477Ssam BUS_DMASYNC_PREWRITE); 1800104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1801104477Ssam BUS_DMASYNC_PREREAD); 1802104477Ssam } 1803104477Ssam 1804104477Ssam /* 1805104477Ssam * need N src, and N dst 1806104477Ssam */ 1807104477Ssam if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1808104477Ssam (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1809104477Ssam#ifdef HIFN_DEBUG 1810104477Ssam if (hifn_debug) { 1811104477Ssam device_printf(sc->sc_dev, 1812104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1813104477Ssam dma->srcu, cmd->src_nsegs, 1814104477Ssam dma->dstu, cmd->dst_nsegs); 1815104477Ssam } 1816104477Ssam#endif 1817104477Ssam hifnstats.hst_nomem_sd++; 1818104477Ssam err = ERESTART; 1819104477Ssam goto err_dstmap; 1820104477Ssam } 1821104477Ssam 1822104477Ssam if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1823104477Ssam dma->cmdi = 0; 1824104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1825104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1826104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1827104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1828104477Ssam } 1829104477Ssam cmdi = dma->cmdi++; 1830104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1831104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1832104477Ssam 1833104477Ssam /* .p for command/result already set */ 1834104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1835104477Ssam HIFN_D_MASKDONEIRQ); 1836104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 1837104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1838104477Ssam dma->cmdu++; 1839104477Ssam if (sc->sc_c_busy == 0) { 1840104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1841104477Ssam sc->sc_c_busy = 1; 1842104477Ssam } 1843104477Ssam 1844104477Ssam /* 1845104477Ssam * We don't worry about missing an interrupt (which a "command wait" 1846104477Ssam * interrupt salvages us from), unless there is more than one command 1847104477Ssam * in the queue. 1848104477Ssam */ 1849104477Ssam if (dma->cmdu > 1) { 1850104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1851104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1852104477Ssam } 1853104477Ssam 1854104477Ssam hifnstats.hst_ipackets++; 1855104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 1856104477Ssam 1857104477Ssam hifn_dmamap_load_src(sc, cmd); 1858104477Ssam if (sc->sc_s_busy == 0) { 1859104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1860104477Ssam sc->sc_s_busy = 1; 1861104477Ssam } 1862104477Ssam 1863104477Ssam /* 1864104477Ssam * Unlike other descriptors, we don't mask done interrupt from 1865104477Ssam * result descriptor. 1866104477Ssam */ 1867104477Ssam#ifdef HIFN_DEBUG 1868104477Ssam if (hifn_debug) 1869104477Ssam printf("load res\n"); 1870104477Ssam#endif 1871104477Ssam if (dma->resi == HIFN_D_RES_RSIZE) { 1872104477Ssam dma->resi = 0; 1873104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1874104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1875104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1876104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1877104477Ssam } 1878104477Ssam resi = dma->resi++; 1879104477Ssam KASSERT(dma->hifn_commands[resi] == NULL, 1880104477Ssam ("hifn_crypto: command slot %u busy", resi)); 1881104477Ssam dma->hifn_commands[resi] = cmd; 1882104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1883104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1884104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1885104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1886104477Ssam sc->sc_curbatch++; 1887104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1888104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 1889104477Ssam hifnstats.hst_totbatch++; 1890104477Ssam } else { 1891104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1892104477Ssam HIFN_D_VALID | HIFN_D_LAST); 1893104477Ssam sc->sc_curbatch = 0; 1894104477Ssam } 1895104477Ssam HIFN_RESR_SYNC(sc, resi, 1896104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1897104477Ssam dma->resu++; 1898104477Ssam if (sc->sc_r_busy == 0) { 1899104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1900104477Ssam sc->sc_r_busy = 1; 1901104477Ssam } 1902104477Ssam 1903104477Ssam if (cmd->sloplen) 1904104477Ssam cmd->slopidx = resi; 1905104477Ssam 1906104477Ssam hifn_dmamap_load_dst(sc, cmd); 1907104477Ssam 1908104477Ssam if (sc->sc_d_busy == 0) { 1909104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1910104477Ssam sc->sc_d_busy = 1; 1911104477Ssam } 1912104477Ssam 1913104477Ssam#ifdef HIFN_DEBUG 1914104477Ssam if (hifn_debug) { 1915104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1916104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1917104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 1918104477Ssam } 1919104477Ssam#endif 1920104477Ssam 1921104477Ssam sc->sc_active = 5; 1922115748Ssam HIFN_UNLOCK(sc); 1923104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1924104477Ssam return (err); /* success */ 1925104477Ssam 1926104477Ssamerr_dstmap: 1927104477Ssam if (cmd->src_map != cmd->dst_map) 1928104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1929104477Ssamerr_dstmap1: 1930104477Ssam if (cmd->src_map != cmd->dst_map) 1931104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1932104477Ssamerr_srcmap: 1933104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1934104477Ssam if (cmd->src_m != cmd->dst_m) 1935104477Ssam m_freem(cmd->dst_m); 1936104477Ssam } 1937104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1938104477Ssamerr_srcmap1: 1939104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1940115748Ssam HIFN_UNLOCK(sc); 1941104477Ssam return (err); 1942104477Ssam} 1943104477Ssam 1944104477Ssamstatic void 1945104477Ssamhifn_tick(void* vsc) 1946104477Ssam{ 1947104477Ssam struct hifn_softc *sc = vsc; 1948104477Ssam 1949104477Ssam HIFN_LOCK(sc); 1950104477Ssam if (sc->sc_active == 0) { 1951104477Ssam struct hifn_dma *dma = sc->sc_dma; 1952104477Ssam u_int32_t r = 0; 1953104477Ssam 1954104477Ssam if (dma->cmdu == 0 && sc->sc_c_busy) { 1955104477Ssam sc->sc_c_busy = 0; 1956104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 1957104477Ssam } 1958104477Ssam if (dma->srcu == 0 && sc->sc_s_busy) { 1959104477Ssam sc->sc_s_busy = 0; 1960104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 1961104477Ssam } 1962104477Ssam if (dma->dstu == 0 && sc->sc_d_busy) { 1963104477Ssam sc->sc_d_busy = 0; 1964104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 1965104477Ssam } 1966104477Ssam if (dma->resu == 0 && sc->sc_r_busy) { 1967104477Ssam sc->sc_r_busy = 0; 1968104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 1969104477Ssam } 1970104477Ssam if (r) 1971104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1972104477Ssam } else 1973104477Ssam sc->sc_active--; 1974104477Ssam HIFN_UNLOCK(sc); 1975104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1976104477Ssam} 1977104477Ssam 1978104477Ssamstatic void 1979104477Ssamhifn_intr(void *arg) 1980104477Ssam{ 1981104477Ssam struct hifn_softc *sc = arg; 1982104477Ssam struct hifn_dma *dma; 1983104477Ssam u_int32_t dmacsr, restart; 1984104477Ssam int i, u; 1985104477Ssam 1986115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1987115748Ssam 1988115748Ssam /* Nothing in the DMA unit interrupted */ 1989115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 1990115748Ssam return; 1991115748Ssam 1992104477Ssam HIFN_LOCK(sc); 1993115748Ssam 1994104477Ssam dma = sc->sc_dma; 1995104477Ssam 1996104477Ssam#ifdef HIFN_DEBUG 1997104477Ssam if (hifn_debug) { 1998104477Ssam device_printf(sc->sc_dev, 1999104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2000104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2001104477Ssam dma->cmdi, dma->srci, dma->dsti, dma->resi, 2002104477Ssam dma->cmdk, dma->srck, dma->dstk, dma->resk, 2003104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2004104477Ssam } 2005104477Ssam#endif 2006104477Ssam 2007104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2008104477Ssam 2009104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2010104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2011104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2012104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2013104477Ssam 2014104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2015104477Ssam if (restart) 2016104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2017104477Ssam 2018104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2019104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2020104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2021104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2022104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2023104477Ssam } 2024104477Ssam 2025104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2026104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2027104477Ssam if (restart) { 2028104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2029104477Ssam hifnstats.hst_abort++; 2030104477Ssam hifn_abort(sc); 2031104477Ssam HIFN_UNLOCK(sc); 2032104477Ssam return; 2033104477Ssam } 2034104477Ssam 2035104477Ssam if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2036104477Ssam /* 2037104477Ssam * If no slots to process and we receive a "waiting on 2038104477Ssam * command" interrupt, we disable the "waiting on command" 2039104477Ssam * (by clearing it). 2040104477Ssam */ 2041104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2042104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2043104477Ssam } 2044104477Ssam 2045104477Ssam /* clear the rings */ 2046104477Ssam i = dma->resk; u = dma->resu; 2047104477Ssam while (u != 0) { 2048104477Ssam HIFN_RESR_SYNC(sc, i, 2049104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2050104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2051104477Ssam HIFN_RESR_SYNC(sc, i, 2052104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2053104477Ssam break; 2054104477Ssam } 2055104477Ssam 2056104477Ssam if (i != HIFN_D_RES_RSIZE) { 2057104477Ssam struct hifn_command *cmd; 2058104477Ssam u_int8_t *macbuf = NULL; 2059104477Ssam 2060104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2061104477Ssam cmd = dma->hifn_commands[i]; 2062104477Ssam KASSERT(cmd != NULL, 2063104477Ssam ("hifn_intr: null command slot %u", i)); 2064104477Ssam dma->hifn_commands[i] = NULL; 2065104477Ssam 2066104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2067104477Ssam macbuf = dma->result_bufs[i]; 2068104477Ssam macbuf += 12; 2069104477Ssam } 2070104477Ssam 2071104477Ssam hifn_callback(sc, cmd, macbuf); 2072104477Ssam hifnstats.hst_opackets++; 2073104477Ssam u--; 2074104477Ssam } 2075104477Ssam 2076104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2077104477Ssam i = 0; 2078104477Ssam } 2079104477Ssam dma->resk = i; dma->resu = u; 2080104477Ssam 2081104477Ssam i = dma->srck; u = dma->srcu; 2082104477Ssam while (u != 0) { 2083104477Ssam if (i == HIFN_D_SRC_RSIZE) 2084104477Ssam i = 0; 2085104477Ssam HIFN_SRCR_SYNC(sc, i, 2086104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2087104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2088104477Ssam HIFN_SRCR_SYNC(sc, i, 2089104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2090104477Ssam break; 2091104477Ssam } 2092104477Ssam i++, u--; 2093104477Ssam } 2094104477Ssam dma->srck = i; dma->srcu = u; 2095104477Ssam 2096104477Ssam i = dma->cmdk; u = dma->cmdu; 2097104477Ssam while (u != 0) { 2098104477Ssam HIFN_CMDR_SYNC(sc, i, 2099104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2100104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2101104477Ssam HIFN_CMDR_SYNC(sc, i, 2102104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2103104477Ssam break; 2104104477Ssam } 2105104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2106104477Ssam u--; 2107104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2108104477Ssam } 2109104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2110104477Ssam i = 0; 2111104477Ssam } 2112104477Ssam dma->cmdk = i; dma->cmdu = u; 2113104477Ssam 2114115748Ssam HIFN_UNLOCK(sc); 2115115748Ssam 2116104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2117104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2118104477Ssam#ifdef HIFN_DEBUG 2119104477Ssam if (hifn_debug) 2120104477Ssam device_printf(sc->sc_dev, 2121104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2122104477Ssam sc->sc_needwakeup, 2123104477Ssam dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2124104477Ssam#endif 2125104477Ssam sc->sc_needwakeup &= ~wakeup; 2126104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2127104477Ssam } 2128104477Ssam} 2129104477Ssam 2130104477Ssam/* 2131104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2132104477Ssam * contains our registration id, and should contain an encoded session 2133104477Ssam * id on successful allocation. 2134104477Ssam */ 2135104477Ssamstatic int 2136104477Ssamhifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2137104477Ssam{ 2138104477Ssam struct cryptoini *c; 2139104477Ssam struct hifn_softc *sc = arg; 2140104477Ssam int i, mac = 0, cry = 0; 2141104477Ssam 2142104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2143104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2144104477Ssam return (EINVAL); 2145104477Ssam 2146104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2147104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2148104477Ssam break; 2149104477Ssam if (i == sc->sc_maxses) 2150104477Ssam return (ENOMEM); 2151104477Ssam 2152104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2153104477Ssam switch (c->cri_alg) { 2154104477Ssam case CRYPTO_MD5: 2155104477Ssam case CRYPTO_SHA1: 2156104477Ssam case CRYPTO_MD5_HMAC: 2157104477Ssam case CRYPTO_SHA1_HMAC: 2158104477Ssam if (mac) 2159104477Ssam return (EINVAL); 2160104477Ssam mac = 1; 2161104477Ssam break; 2162104477Ssam case CRYPTO_DES_CBC: 2163104477Ssam case CRYPTO_3DES_CBC: 2164104477Ssam /* XXX this may read fewer, does it matter? */ 2165104477Ssam read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2166104477Ssam /*FALLTHROUGH*/ 2167104477Ssam case CRYPTO_ARC4: 2168104477Ssam if (cry) 2169104477Ssam return (EINVAL); 2170104477Ssam cry = 1; 2171104477Ssam break; 2172104477Ssam default: 2173104477Ssam return (EINVAL); 2174104477Ssam } 2175104477Ssam } 2176104477Ssam if (mac == 0 && cry == 0) 2177104477Ssam return (EINVAL); 2178104477Ssam 2179104477Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2180104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2181104477Ssam 2182104477Ssam return (0); 2183104477Ssam} 2184104477Ssam 2185104477Ssam/* 2186104477Ssam * Deallocate a session. 2187104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2188104477Ssam * XXX to blow away any keys already stored there. 2189104477Ssam */ 2190104477Ssamstatic int 2191104477Ssamhifn_freesession(void *arg, u_int64_t tid) 2192104477Ssam{ 2193104477Ssam struct hifn_softc *sc = arg; 2194104477Ssam int session; 2195116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2196104477Ssam 2197104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2198104477Ssam if (sc == NULL) 2199104477Ssam return (EINVAL); 2200104477Ssam 2201104477Ssam session = HIFN_SESSION(sid); 2202104477Ssam if (session >= sc->sc_maxses) 2203104477Ssam return (EINVAL); 2204104477Ssam 2205104477Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2206104477Ssam return (0); 2207104477Ssam} 2208104477Ssam 2209104477Ssamstatic int 2210104477Ssamhifn_process(void *arg, struct cryptop *crp, int hint) 2211104477Ssam{ 2212104477Ssam struct hifn_softc *sc = arg; 2213104477Ssam struct hifn_command *cmd = NULL; 2214104477Ssam int session, err; 2215104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2216104477Ssam 2217104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2218104477Ssam hifnstats.hst_invalid++; 2219104477Ssam return (EINVAL); 2220104477Ssam } 2221104477Ssam session = HIFN_SESSION(crp->crp_sid); 2222104477Ssam 2223104477Ssam if (sc == NULL || session >= sc->sc_maxses) { 2224104477Ssam err = EINVAL; 2225104477Ssam goto errout; 2226104477Ssam } 2227104477Ssam 2228104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2229104477Ssam if (cmd == NULL) { 2230104477Ssam hifnstats.hst_nomem++; 2231104477Ssam err = ENOMEM; 2232104477Ssam goto errout; 2233104477Ssam } 2234104477Ssam 2235104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2236104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2237104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2238104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2239104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2240104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2241104477Ssam } else { 2242104477Ssam err = EINVAL; 2243104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2244104477Ssam } 2245104477Ssam 2246104477Ssam crd1 = crp->crp_desc; 2247104477Ssam if (crd1 == NULL) { 2248104477Ssam err = EINVAL; 2249104477Ssam goto errout; 2250104477Ssam } 2251104477Ssam crd2 = crd1->crd_next; 2252104477Ssam 2253104477Ssam if (crd2 == NULL) { 2254104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2255104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2256104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2257104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2258104477Ssam maccrd = crd1; 2259104477Ssam enccrd = NULL; 2260104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2261104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2262104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2263104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2264104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2265104477Ssam maccrd = NULL; 2266104477Ssam enccrd = crd1; 2267104477Ssam } else { 2268104477Ssam err = EINVAL; 2269104477Ssam goto errout; 2270104477Ssam } 2271104477Ssam } else { 2272104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2273104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2274104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2275104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2276104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2277104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2278104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2279104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2280104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2281104477Ssam maccrd = crd1; 2282104477Ssam enccrd = crd2; 2283104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2284104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2285104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC) && 2286104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2287104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2288104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2289104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2290104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2291104477Ssam enccrd = crd1; 2292104477Ssam maccrd = crd2; 2293104477Ssam } else { 2294104477Ssam /* 2295104477Ssam * We cannot order the 7751 as requested 2296104477Ssam */ 2297104477Ssam err = EINVAL; 2298104477Ssam goto errout; 2299104477Ssam } 2300104477Ssam } 2301104477Ssam 2302104477Ssam if (enccrd) { 2303104477Ssam cmd->enccrd = enccrd; 2304104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2305104477Ssam switch (enccrd->crd_alg) { 2306104477Ssam case CRYPTO_ARC4: 2307104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2308104477Ssam if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2309104477Ssam != sc->sc_sessions[session].hs_prev_op) 2310104477Ssam sc->sc_sessions[session].hs_state = 2311104477Ssam HS_STATE_USED; 2312104477Ssam break; 2313104477Ssam case CRYPTO_DES_CBC: 2314104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2315104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2316104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2317104477Ssam break; 2318104477Ssam case CRYPTO_3DES_CBC: 2319104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2320104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2321104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2322104477Ssam break; 2323104477Ssam default: 2324104477Ssam err = EINVAL; 2325104477Ssam goto errout; 2326104477Ssam } 2327104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2328104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2329104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2330104477Ssam bcopy(enccrd->crd_iv, cmd->iv, 2331104477Ssam HIFN_IV_LENGTH); 2332104477Ssam else 2333104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2334104477Ssam cmd->iv, HIFN_IV_LENGTH); 2335104477Ssam 2336104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2337104477Ssam == 0) { 2338104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2339104477Ssam m_copyback(cmd->src_m, 2340104477Ssam enccrd->crd_inject, 2341104477Ssam HIFN_IV_LENGTH, cmd->iv); 2342104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2343104477Ssam cuio_copyback(cmd->src_io, 2344104477Ssam enccrd->crd_inject, 2345104477Ssam HIFN_IV_LENGTH, cmd->iv); 2346104477Ssam } 2347104477Ssam } else { 2348104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2349104477Ssam bcopy(enccrd->crd_iv, cmd->iv, 2350104477Ssam HIFN_IV_LENGTH); 2351104477Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 2352104477Ssam m_copydata(cmd->src_m, 2353104477Ssam enccrd->crd_inject, 2354104477Ssam HIFN_IV_LENGTH, cmd->iv); 2355104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2356104477Ssam cuio_copydata(cmd->src_io, 2357104477Ssam enccrd->crd_inject, 2358104477Ssam HIFN_IV_LENGTH, cmd->iv); 2359104477Ssam } 2360104477Ssam } 2361104477Ssam 2362104477Ssam cmd->ck = enccrd->crd_key; 2363104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2364104477Ssam 2365104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2366104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2367104477Ssam } 2368104477Ssam 2369104477Ssam if (maccrd) { 2370104477Ssam cmd->maccrd = maccrd; 2371104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2372104477Ssam 2373104477Ssam switch (maccrd->crd_alg) { 2374104477Ssam case CRYPTO_MD5: 2375104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2376104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2377104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2378104477Ssam break; 2379104477Ssam case CRYPTO_MD5_HMAC: 2380104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2381104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2382104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2383104477Ssam break; 2384104477Ssam case CRYPTO_SHA1: 2385104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2386104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2387104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2388104477Ssam break; 2389104477Ssam case CRYPTO_SHA1_HMAC: 2390104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2391104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2392104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2393104477Ssam break; 2394104477Ssam } 2395104477Ssam 2396104477Ssam if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2397104477Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2398104477Ssam sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2399104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2400104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2401104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2402104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2403104477Ssam } 2404104477Ssam } 2405104477Ssam 2406104477Ssam cmd->crp = crp; 2407104477Ssam cmd->session_num = session; 2408104477Ssam cmd->softc = sc; 2409104477Ssam 2410104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2411104477Ssam if (!err) { 2412104477Ssam if (enccrd) 2413104477Ssam sc->sc_sessions[session].hs_prev_op = 2414104477Ssam enccrd->crd_flags & CRD_F_ENCRYPT; 2415104477Ssam if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2416104477Ssam sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2417104477Ssam return 0; 2418104477Ssam } else if (err == ERESTART) { 2419104477Ssam /* 2420104477Ssam * There weren't enough resources to dispatch the request 2421104477Ssam * to the part. Notify the caller so they'll requeue this 2422104477Ssam * request and resubmit it again soon. 2423104477Ssam */ 2424104477Ssam#ifdef HIFN_DEBUG 2425104477Ssam if (hifn_debug) 2426104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2427104477Ssam#endif 2428104477Ssam free(cmd, M_DEVBUF); 2429104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2430104477Ssam return (err); 2431104477Ssam } 2432104477Ssam 2433104477Ssamerrout: 2434104477Ssam if (cmd != NULL) 2435104477Ssam free(cmd, M_DEVBUF); 2436104477Ssam if (err == EINVAL) 2437104477Ssam hifnstats.hst_invalid++; 2438104477Ssam else 2439104477Ssam hifnstats.hst_nomem++; 2440104477Ssam crp->crp_etype = err; 2441104477Ssam crypto_done(crp); 2442104477Ssam return (err); 2443104477Ssam} 2444104477Ssam 2445104477Ssamstatic void 2446104477Ssamhifn_abort(struct hifn_softc *sc) 2447104477Ssam{ 2448104477Ssam struct hifn_dma *dma = sc->sc_dma; 2449104477Ssam struct hifn_command *cmd; 2450104477Ssam struct cryptop *crp; 2451104477Ssam int i, u; 2452104477Ssam 2453104477Ssam i = dma->resk; u = dma->resu; 2454104477Ssam while (u != 0) { 2455104477Ssam cmd = dma->hifn_commands[i]; 2456104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2457104477Ssam dma->hifn_commands[i] = NULL; 2458104477Ssam crp = cmd->crp; 2459104477Ssam 2460104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2461104477Ssam /* Salvage what we can. */ 2462104477Ssam u_int8_t *macbuf; 2463104477Ssam 2464104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2465104477Ssam macbuf = dma->result_bufs[i]; 2466104477Ssam macbuf += 12; 2467104477Ssam } else 2468104477Ssam macbuf = NULL; 2469104477Ssam hifnstats.hst_opackets++; 2470104477Ssam hifn_callback(sc, cmd, macbuf); 2471104477Ssam } else { 2472104477Ssam if (cmd->src_map == cmd->dst_map) { 2473104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2474104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2475104477Ssam } else { 2476104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2477104477Ssam BUS_DMASYNC_POSTWRITE); 2478104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2479104477Ssam BUS_DMASYNC_POSTREAD); 2480104477Ssam } 2481104477Ssam 2482104477Ssam if (cmd->src_m != cmd->dst_m) { 2483104477Ssam m_freem(cmd->src_m); 2484104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2485104477Ssam } 2486104477Ssam 2487104477Ssam /* non-shared buffers cannot be restarted */ 2488104477Ssam if (cmd->src_map != cmd->dst_map) { 2489104477Ssam /* 2490104477Ssam * XXX should be EAGAIN, delayed until 2491104477Ssam * after the reset. 2492104477Ssam */ 2493104477Ssam crp->crp_etype = ENOMEM; 2494104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2495104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2496104477Ssam } else 2497104477Ssam crp->crp_etype = ENOMEM; 2498104477Ssam 2499104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2500104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2501104477Ssam 2502104477Ssam free(cmd, M_DEVBUF); 2503104477Ssam if (crp->crp_etype != EAGAIN) 2504104477Ssam crypto_done(crp); 2505104477Ssam } 2506104477Ssam 2507104477Ssam if (++i == HIFN_D_RES_RSIZE) 2508104477Ssam i = 0; 2509104477Ssam u--; 2510104477Ssam } 2511104477Ssam dma->resk = i; dma->resu = u; 2512104477Ssam 2513104477Ssam /* Force upload of key next time */ 2514104477Ssam for (i = 0; i < sc->sc_maxses; i++) 2515104477Ssam if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2516104477Ssam sc->sc_sessions[i].hs_state = HS_STATE_USED; 2517104477Ssam 2518104477Ssam hifn_reset_board(sc, 1); 2519104477Ssam hifn_init_dma(sc); 2520104477Ssam hifn_init_pci_registers(sc); 2521104477Ssam} 2522104477Ssam 2523104477Ssamstatic void 2524104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2525104477Ssam{ 2526104477Ssam struct hifn_dma *dma = sc->sc_dma; 2527104477Ssam struct cryptop *crp = cmd->crp; 2528104477Ssam struct cryptodesc *crd; 2529104477Ssam struct mbuf *m; 2530104477Ssam int totlen, i, u; 2531104477Ssam 2532104477Ssam if (cmd->src_map == cmd->dst_map) { 2533104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2534104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2535104477Ssam } else { 2536104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2537104477Ssam BUS_DMASYNC_POSTWRITE); 2538104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2539104477Ssam BUS_DMASYNC_POSTREAD); 2540104477Ssam } 2541104477Ssam 2542104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2543104477Ssam if (cmd->src_m != cmd->dst_m) { 2544104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2545104477Ssam totlen = cmd->src_mapsize; 2546104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2547104477Ssam if (totlen < m->m_len) { 2548104477Ssam m->m_len = totlen; 2549104477Ssam totlen = 0; 2550104477Ssam } else 2551104477Ssam totlen -= m->m_len; 2552104477Ssam } 2553104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2554104477Ssam m_freem(cmd->src_m); 2555104477Ssam } 2556104477Ssam } 2557104477Ssam 2558104477Ssam if (cmd->sloplen != 0) { 2559104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2560104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2561104477Ssam cmd->src_mapsize - cmd->sloplen, 2562104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2563104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 2564104477Ssam cuio_copyback((struct uio *)crp->crp_buf, 2565104477Ssam cmd->src_mapsize - cmd->sloplen, 2566104477Ssam cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2567104477Ssam } 2568104477Ssam 2569104477Ssam i = dma->dstk; u = dma->dstu; 2570104477Ssam while (u != 0) { 2571104477Ssam if (i == HIFN_D_DST_RSIZE) 2572104477Ssam i = 0; 2573104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2574104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2575104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2576104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2577104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2578104477Ssam break; 2579104477Ssam } 2580104477Ssam i++, u--; 2581104477Ssam } 2582104477Ssam dma->dstk = i; dma->dstu = u; 2583104477Ssam 2584104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2585104477Ssam 2586104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2587104477Ssam HIFN_BASE_CMD_CRYPT) { 2588104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2589104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2590104477Ssam crd->crd_alg != CRYPTO_3DES_CBC) 2591104477Ssam continue; 2592104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2593104477Ssam m_copydata((struct mbuf *)crp->crp_buf, 2594104477Ssam crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2595104477Ssam HIFN_IV_LENGTH, 2596104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2597104477Ssam else if (crp->crp_flags & CRYPTO_F_IOV) { 2598104477Ssam cuio_copydata((struct uio *)crp->crp_buf, 2599104477Ssam crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2600104477Ssam HIFN_IV_LENGTH, 2601104477Ssam cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2602104477Ssam } 2603104477Ssam break; 2604104477Ssam } 2605104477Ssam } 2606104477Ssam 2607104477Ssam if (macbuf != NULL) { 2608104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2609105275Ssam int len; 2610104477Ssam 2611105275Ssam if (crd->crd_alg == CRYPTO_MD5) 2612105275Ssam len = 16; 2613105275Ssam else if (crd->crd_alg == CRYPTO_SHA1) 2614105275Ssam len = 20; 2615105275Ssam else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2616105275Ssam crd->crd_alg == CRYPTO_SHA1_HMAC) 2617105275Ssam len = 12; 2618105275Ssam else 2619104477Ssam continue; 2620104477Ssam 2621104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 2622104477Ssam m_copyback((struct mbuf *)crp->crp_buf, 2623104477Ssam crd->crd_inject, len, macbuf); 2624104477Ssam else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2625104477Ssam bcopy((caddr_t)macbuf, crp->crp_mac, len); 2626104477Ssam break; 2627104477Ssam } 2628104477Ssam } 2629104477Ssam 2630104477Ssam if (cmd->src_map != cmd->dst_map) { 2631104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2632104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2633104477Ssam } 2634104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2635104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2636104477Ssam free(cmd, M_DEVBUF); 2637104477Ssam crypto_done(crp); 2638104477Ssam} 2639104477Ssam 2640104477Ssam/* 2641104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2642104477Ssam * and Group 1 registers; avoid conditions that could create 2643104477Ssam * burst writes by doing a read in between the writes. 2644104477Ssam * 2645104477Ssam * NB: The read we interpose is always to the same register; 2646104477Ssam * we do this because reading from an arbitrary (e.g. last) 2647104477Ssam * register may not always work. 2648104477Ssam */ 2649104477Ssamstatic void 2650104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2651104477Ssam{ 2652104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2653104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2654104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2655104477Ssam sc->sc_bar0_lastreg = reg; 2656104477Ssam } 2657104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2658104477Ssam} 2659104477Ssam 2660104477Ssamstatic void 2661104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2662104477Ssam{ 2663104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2664104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2665104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2666104477Ssam sc->sc_bar1_lastreg = reg; 2667104477Ssam } 2668104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2669104477Ssam} 2670