hifn7751.c revision 119690
1/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2 3/* 4 * Invertex AEON / Hifn 7751 driver 5 * Copyright (c) 1999 Invertex Inc. All rights reserved. 6 * Copyright (c) 1999 Theo de Raadt 7 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8 * http://www.netsec.net 9 * 10 * This driver is based on a previous driver by Invertex, for which they 11 * requested: Please send any comments, feedback, bug-fixes, or feature 12 * requests to software@invertex.com. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 */ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: head/sys/dev/hifn/hifn7751.c 119690 2003-09-02 17:30:40Z jhb $"); 44 45/* 46 * Driver for the Hifn 7751 encryption processor. 47 */ 48#include "opt_hifn.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/mbuf.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/sysctl.h> 60 61#include <vm/vm.h> 62#include <vm/pmap.h> 63 64#include <machine/clock.h> 65#include <machine/bus.h> 66#include <machine/resource.h> 67#include <sys/bus.h> 68#include <sys/rman.h> 69 70#include <opencrypto/cryptodev.h> 71#include <sys/random.h> 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> 75 76#ifdef HIFN_RNDTEST 77#include <dev/rndtest/rndtest.h> 78#endif 79#include <dev/hifn/hifn7751reg.h> 80#include <dev/hifn/hifn7751var.h> 81 82/* 83 * Prototypes and count for the pci_device structure 84 */ 85static int hifn_probe(device_t); 86static int hifn_attach(device_t); 87static int hifn_detach(device_t); 88static int hifn_suspend(device_t); 89static int hifn_resume(device_t); 90static void hifn_shutdown(device_t); 91 92static device_method_t hifn_methods[] = { 93 /* Device interface */ 94 DEVMETHOD(device_probe, hifn_probe), 95 DEVMETHOD(device_attach, hifn_attach), 96 DEVMETHOD(device_detach, hifn_detach), 97 DEVMETHOD(device_suspend, hifn_suspend), 98 DEVMETHOD(device_resume, hifn_resume), 99 DEVMETHOD(device_shutdown, hifn_shutdown), 100 101 /* bus interface */ 102 DEVMETHOD(bus_print_child, bus_generic_print_child), 103 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 104 105 { 0, 0 } 106}; 107static driver_t hifn_driver = { 108 "hifn", 109 hifn_methods, 110 sizeof (struct hifn_softc) 111}; 112static devclass_t hifn_devclass; 113 114DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 115MODULE_DEPEND(hifn, crypto, 1, 1, 1); 116#ifdef HIFN_RNDTEST 117MODULE_DEPEND(hifn, rndtest, 1, 1, 1); 118#endif 119 120static void hifn_reset_board(struct hifn_softc *, int); 121static void hifn_reset_puc(struct hifn_softc *); 122static void hifn_puc_wait(struct hifn_softc *); 123static int hifn_enable_crypto(struct hifn_softc *); 124static void hifn_set_retry(struct hifn_softc *sc); 125static void hifn_init_dma(struct hifn_softc *); 126static void hifn_init_pci_registers(struct hifn_softc *); 127static int hifn_sramsize(struct hifn_softc *); 128static int hifn_dramsize(struct hifn_softc *); 129static int hifn_ramtype(struct hifn_softc *); 130static void hifn_sessions(struct hifn_softc *); 131static void hifn_intr(void *); 132static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 133static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 134static int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 135static int hifn_freesession(void *, u_int64_t); 136static int hifn_process(void *, struct cryptop *, int); 137static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 138static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 139static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 140static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 141static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 142static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 143static int hifn_init_pubrng(struct hifn_softc *); 144static void hifn_rng(void *); 145static void hifn_tick(void *); 146static void hifn_abort(struct hifn_softc *); 147static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 148 149static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 150static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 151 152static __inline__ u_int32_t 153READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 154{ 155 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 156 sc->sc_bar0_lastreg = (bus_size_t) -1; 157 return (v); 158} 159#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 160 161static __inline__ u_int32_t 162READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 163{ 164 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 165 sc->sc_bar1_lastreg = (bus_size_t) -1; 166 return (v); 167} 168#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 169 170SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 171 172#ifdef HIFN_DEBUG 173static int hifn_debug = 0; 174SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 175 0, "control debugging msgs"); 176#endif 177 178static struct hifn_stats hifnstats; 179SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 180 hifn_stats, "driver statistics"); 181static int hifn_maxbatch = 1; 182SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 183 0, "max ops to batch w/o interrupt"); 184 185/* 186 * Probe for a supported device. The PCI vendor and device 187 * IDs are used to detect devices we know how to handle. 188 */ 189static int 190hifn_probe(device_t dev) 191{ 192 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 193 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 194 return (0); 195 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 196 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 197 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 198 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 199 return (0); 200 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 201 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 202 return (0); 203 return (ENXIO); 204} 205 206static void 207hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 208{ 209 bus_addr_t *paddr = (bus_addr_t*) arg; 210 *paddr = segs->ds_addr; 211} 212 213static const char* 214hifn_partname(struct hifn_softc *sc) 215{ 216 /* XXX sprintf numbers when not decoded */ 217 switch (pci_get_vendor(sc->sc_dev)) { 218 case PCI_VENDOR_HIFN: 219 switch (pci_get_device(sc->sc_dev)) { 220 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 221 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 222 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 223 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 224 } 225 return "Hifn unknown-part"; 226 case PCI_VENDOR_INVERTEX: 227 switch (pci_get_device(sc->sc_dev)) { 228 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 229 } 230 return "Invertex unknown-part"; 231 case PCI_VENDOR_NETSEC: 232 switch (pci_get_device(sc->sc_dev)) { 233 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 234 } 235 return "NetSec unknown-part"; 236 } 237 return "Unknown-vendor unknown-part"; 238} 239 240static void 241default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 242{ 243 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 244} 245 246/* 247 * Attach an interface that successfully probed. 248 */ 249static int 250hifn_attach(device_t dev) 251{ 252 struct hifn_softc *sc = device_get_softc(dev); 253 u_int32_t cmd; 254 caddr_t kva; 255 int rseg, rid; 256 char rbase; 257 u_int16_t ena, rev; 258 259 KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 260 bzero(sc, sizeof (*sc)); 261 sc->sc_dev = dev; 262 263 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 264 265 /* XXX handle power management */ 266 267 /* 268 * The 7951 has a random number generator and 269 * public key support; note this. 270 */ 271 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 272 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 273 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 274 /* 275 * The 7811 has a random number generator and 276 * we also note it's identity 'cuz of some quirks. 277 */ 278 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 279 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 280 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 281 282 /* 283 * Configure support for memory-mapped access to 284 * registers and for DMA operations. 285 */ 286#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 287 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 288 cmd |= PCIM_ENA; 289 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 290 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 291 if ((cmd & PCIM_ENA) != PCIM_ENA) { 292 device_printf(dev, "failed to enable %s\n", 293 (cmd & PCIM_ENA) == 0 ? 294 "memory mapping & bus mastering" : 295 (cmd & PCIM_CMD_MEMEN) == 0 ? 296 "memory mapping" : "bus mastering"); 297 goto fail_pci; 298 } 299#undef PCIM_ENA 300 301 /* 302 * Setup PCI resources. Note that we record the bus 303 * tag and handle for each register mapping, this is 304 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 305 * and WRITE_REG_1 macros throughout the driver. 306 */ 307 rid = HIFN_BAR0; 308 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 309 0, ~0, 1, RF_ACTIVE); 310 if (sc->sc_bar0res == NULL) { 311 device_printf(dev, "cannot map bar%d register space\n", 0); 312 goto fail_pci; 313 } 314 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 315 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 316 sc->sc_bar0_lastreg = (bus_size_t) -1; 317 318 rid = HIFN_BAR1; 319 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 320 0, ~0, 1, RF_ACTIVE); 321 if (sc->sc_bar1res == NULL) { 322 device_printf(dev, "cannot map bar%d register space\n", 1); 323 goto fail_io0; 324 } 325 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 326 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 327 sc->sc_bar1_lastreg = (bus_size_t) -1; 328 329 hifn_set_retry(sc); 330 331 /* 332 * Setup the area where the Hifn DMA's descriptors 333 * and associated data structures. 334 */ 335 if (bus_dma_tag_create(NULL, /* parent */ 336 1, 0, /* alignment,boundary */ 337 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 338 BUS_SPACE_MAXADDR, /* highaddr */ 339 NULL, NULL, /* filter, filterarg */ 340 HIFN_MAX_DMALEN, /* maxsize */ 341 MAX_SCATTER, /* nsegments */ 342 HIFN_MAX_SEGLEN, /* maxsegsize */ 343 BUS_DMA_ALLOCNOW, /* flags */ 344 NULL, /* lockfunc */ 345 NULL, /* lockarg */ 346 &sc->sc_dmat)) { 347 device_printf(dev, "cannot allocate DMA tag\n"); 348 goto fail_io1; 349 } 350 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 351 device_printf(dev, "cannot create dma map\n"); 352 bus_dma_tag_destroy(sc->sc_dmat); 353 goto fail_io1; 354 } 355 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 356 device_printf(dev, "cannot alloc dma buffer\n"); 357 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 358 bus_dma_tag_destroy(sc->sc_dmat); 359 goto fail_io1; 360 } 361 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 362 sizeof (*sc->sc_dma), 363 hifn_dmamap_cb, &sc->sc_dma_physaddr, 364 BUS_DMA_NOWAIT)) { 365 device_printf(dev, "cannot load dma map\n"); 366 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 367 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 368 bus_dma_tag_destroy(sc->sc_dmat); 369 goto fail_io1; 370 } 371 sc->sc_dma = (struct hifn_dma *)kva; 372 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 373 374 KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 375 KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 376 KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 377 KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 378 379 /* 380 * Reset the board and do the ``secret handshake'' 381 * to enable the crypto support. Then complete the 382 * initialization procedure by setting up the interrupt 383 * and hooking in to the system crypto support so we'll 384 * get used for system services like the crypto device, 385 * IPsec, RNG device, etc. 386 */ 387 hifn_reset_board(sc, 0); 388 389 if (hifn_enable_crypto(sc) != 0) { 390 device_printf(dev, "crypto enabling failed\n"); 391 goto fail_mem; 392 } 393 hifn_reset_puc(sc); 394 395 hifn_init_dma(sc); 396 hifn_init_pci_registers(sc); 397 398 if (hifn_ramtype(sc)) 399 goto fail_mem; 400 401 if (sc->sc_drammodel == 0) 402 hifn_sramsize(sc); 403 else 404 hifn_dramsize(sc); 405 406 /* 407 * Workaround for NetSec 7751 rev A: half ram size because two 408 * of the address lines were left floating 409 */ 410 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 411 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 412 pci_get_revid(dev) == 0x61) /*XXX???*/ 413 sc->sc_ramsize >>= 1; 414 415 /* 416 * Arrange the interrupt line. 417 */ 418 rid = 0; 419 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 420 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 421 if (sc->sc_irq == NULL) { 422 device_printf(dev, "could not map interrupt\n"); 423 goto fail_mem; 424 } 425 /* 426 * NB: Network code assumes we are blocked with splimp() 427 * so make sure the IRQ is marked appropriately. 428 */ 429 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 430 hifn_intr, sc, &sc->sc_intrhand)) { 431 device_printf(dev, "could not setup interrupt\n"); 432 goto fail_intr2; 433 } 434 435 hifn_sessions(sc); 436 437 /* 438 * NB: Keep only the low 16 bits; this masks the chip id 439 * from the 7951. 440 */ 441 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 442 443 rseg = sc->sc_ramsize / 1024; 444 rbase = 'K'; 445 if (sc->sc_ramsize >= (1024 * 1024)) { 446 rbase = 'M'; 447 rseg /= 1024; 448 } 449 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 450 hifn_partname(sc), rev, 451 rseg, rbase, sc->sc_drammodel ? 'd' : 's', 452 sc->sc_maxses); 453 454 sc->sc_cid = crypto_get_driverid(0); 455 if (sc->sc_cid < 0) { 456 device_printf(dev, "could not get crypto driver id\n"); 457 goto fail_intr; 458 } 459 460 WRITE_REG_0(sc, HIFN_0_PUCNFG, 461 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 462 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 463 464 switch (ena) { 465 case HIFN_PUSTAT_ENA_2: 466 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 467 hifn_newsession, hifn_freesession, hifn_process, sc); 468 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 469 hifn_newsession, hifn_freesession, hifn_process, sc); 470 /*FALLTHROUGH*/ 471 case HIFN_PUSTAT_ENA_1: 472 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 473 hifn_newsession, hifn_freesession, hifn_process, sc); 474 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 475 hifn_newsession, hifn_freesession, hifn_process, sc); 476 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 477 hifn_newsession, hifn_freesession, hifn_process, sc); 478 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 479 hifn_newsession, hifn_freesession, hifn_process, sc); 480 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 481 hifn_newsession, hifn_freesession, hifn_process, sc); 482 break; 483 } 484 485 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 486 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 487 488 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 489 hifn_init_pubrng(sc); 490 491 callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 492 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 493 494 return (0); 495 496fail_intr: 497 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 498fail_intr2: 499 /* XXX don't store rid */ 500 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 501fail_mem: 502 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 503 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 504 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 505 bus_dma_tag_destroy(sc->sc_dmat); 506 507 /* Turn off DMA polling */ 508 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 509 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 510fail_io1: 511 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 512fail_io0: 513 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 514fail_pci: 515 mtx_destroy(&sc->sc_mtx); 516 return (ENXIO); 517} 518 519/* 520 * Detach an interface that successfully probed. 521 */ 522static int 523hifn_detach(device_t dev) 524{ 525 struct hifn_softc *sc = device_get_softc(dev); 526 527 KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 528 529 /* disable interrupts */ 530 WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 531 532 /*XXX other resources */ 533 callout_stop(&sc->sc_tickto); 534 callout_stop(&sc->sc_rngto); 535#ifdef HIFN_RNDTEST 536 if (sc->sc_rndtest) 537 rndtest_detach(sc->sc_rndtest); 538#endif 539 540 /* Turn off DMA polling */ 541 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 542 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 543 544 crypto_unregister_all(sc->sc_cid); 545 546 bus_generic_detach(dev); /*XXX should be no children, right? */ 547 548 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 549 /* XXX don't store rid */ 550 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 551 552 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 553 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 554 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 555 bus_dma_tag_destroy(sc->sc_dmat); 556 557 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 558 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 559 560 mtx_destroy(&sc->sc_mtx); 561 562 return (0); 563} 564 565/* 566 * Stop all chip I/O so that the kernel's probe routines don't 567 * get confused by errant DMAs when rebooting. 568 */ 569static void 570hifn_shutdown(device_t dev) 571{ 572#ifdef notyet 573 hifn_stop(device_get_softc(dev)); 574#endif 575} 576 577/* 578 * Device suspend routine. Stop the interface and save some PCI 579 * settings in case the BIOS doesn't restore them properly on 580 * resume. 581 */ 582static int 583hifn_suspend(device_t dev) 584{ 585 struct hifn_softc *sc = device_get_softc(dev); 586#ifdef notyet 587 int i; 588 589 hifn_stop(sc); 590 for (i = 0; i < 5; i++) 591 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 592 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 593 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 594 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 595 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 596#endif 597 sc->sc_suspended = 1; 598 599 return (0); 600} 601 602/* 603 * Device resume routine. Restore some PCI settings in case the BIOS 604 * doesn't, re-enable busmastering, and restart the interface if 605 * appropriate. 606 */ 607static int 608hifn_resume(device_t dev) 609{ 610 struct hifn_softc *sc = device_get_softc(dev); 611#ifdef notyet 612 int i; 613 614 /* better way to do this? */ 615 for (i = 0; i < 5; i++) 616 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 617 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 618 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 619 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 620 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 621 622 /* reenable busmastering */ 623 pci_enable_busmaster(dev); 624 pci_enable_io(dev, HIFN_RES); 625 626 /* reinitialize interface if necessary */ 627 if (ifp->if_flags & IFF_UP) 628 rl_init(sc); 629#endif 630 sc->sc_suspended = 0; 631 632 return (0); 633} 634 635static int 636hifn_init_pubrng(struct hifn_softc *sc) 637{ 638 u_int32_t r; 639 int i; 640 641#ifdef HIFN_RNDTEST 642 sc->sc_rndtest = rndtest_attach(sc->sc_dev); 643 if (sc->sc_rndtest) 644 sc->sc_harvest = rndtest_harvest; 645 else 646 sc->sc_harvest = default_harvest; 647#else 648 sc->sc_harvest = default_harvest; 649#endif 650 if ((sc->sc_flags & HIFN_IS_7811) == 0) { 651 /* Reset 7951 public key/rng engine */ 652 WRITE_REG_1(sc, HIFN_1_PUB_RESET, 653 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 654 655 for (i = 0; i < 100; i++) { 656 DELAY(1000); 657 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 658 HIFN_PUBRST_RESET) == 0) 659 break; 660 } 661 662 if (i == 100) { 663 device_printf(sc->sc_dev, "public key init failed\n"); 664 return (1); 665 } 666 } 667 668 /* Enable the rng, if available */ 669 if (sc->sc_flags & HIFN_HAS_RNG) { 670 if (sc->sc_flags & HIFN_IS_7811) { 671 r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 672 if (r & HIFN_7811_RNGENA_ENA) { 673 r &= ~HIFN_7811_RNGENA_ENA; 674 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 675 } 676 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 677 HIFN_7811_RNGCFG_DEFL); 678 r |= HIFN_7811_RNGENA_ENA; 679 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 680 } else 681 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 682 READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 683 HIFN_RNGCFG_ENA); 684 685 sc->sc_rngfirst = 1; 686 if (hz >= 100) 687 sc->sc_rnghz = hz / 100; 688 else 689 sc->sc_rnghz = 1; 690 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 691 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 692 } 693 694 /* Enable public key engine, if available */ 695 if (sc->sc_flags & HIFN_HAS_PUBLIC) { 696 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 697 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 698 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 699 } 700 701 return (0); 702} 703 704static void 705hifn_rng(void *vsc) 706{ 707#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 708 struct hifn_softc *sc = vsc; 709 u_int32_t sts, num[2]; 710 int i; 711 712 if (sc->sc_flags & HIFN_IS_7811) { 713 for (i = 0; i < 5; i++) { 714 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 715 if (sts & HIFN_7811_RNGSTS_UFL) { 716 device_printf(sc->sc_dev, 717 "RNG underflow: disabling\n"); 718 return; 719 } 720 if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 721 break; 722 723 /* 724 * There are at least two words in the RNG FIFO 725 * at this point. 726 */ 727 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 728 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 729 /* NB: discard first data read */ 730 if (sc->sc_rngfirst) 731 sc->sc_rngfirst = 0; 732 else 733 (*sc->sc_harvest)(sc->sc_rndtest, 734 num, sizeof (num)); 735 } 736 } else { 737 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 738 739 /* NB: discard first data read */ 740 if (sc->sc_rngfirst) 741 sc->sc_rngfirst = 0; 742 else 743 (*sc->sc_harvest)(sc->sc_rndtest, 744 num, sizeof (num[0])); 745 } 746 747 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 748#undef RANDOM_BITS 749} 750 751static void 752hifn_puc_wait(struct hifn_softc *sc) 753{ 754 int i; 755 756 for (i = 5000; i > 0; i--) { 757 DELAY(1); 758 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 759 break; 760 } 761 if (!i) 762 device_printf(sc->sc_dev, "proc unit did not reset\n"); 763} 764 765/* 766 * Reset the processing unit. 767 */ 768static void 769hifn_reset_puc(struct hifn_softc *sc) 770{ 771 /* Reset processing unit */ 772 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 773 hifn_puc_wait(sc); 774} 775 776/* 777 * Set the Retry and TRDY registers; note that we set them to 778 * zero because the 7811 locks up when forced to retry (section 779 * 3.6 of "Specification Update SU-0014-04". Not clear if we 780 * should do this for all Hifn parts, but it doesn't seem to hurt. 781 */ 782static void 783hifn_set_retry(struct hifn_softc *sc) 784{ 785 /* NB: RETRY only responds to 8-bit reads/writes */ 786 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 787 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 788} 789 790/* 791 * Resets the board. Values in the regesters are left as is 792 * from the reset (i.e. initial values are assigned elsewhere). 793 */ 794static void 795hifn_reset_board(struct hifn_softc *sc, int full) 796{ 797 u_int32_t reg; 798 799 /* 800 * Set polling in the DMA configuration register to zero. 0x7 avoids 801 * resetting the board and zeros out the other fields. 802 */ 803 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 804 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 805 806 /* 807 * Now that polling has been disabled, we have to wait 1 ms 808 * before resetting the board. 809 */ 810 DELAY(1000); 811 812 /* Reset the DMA unit */ 813 if (full) { 814 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 815 DELAY(1000); 816 } else { 817 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 818 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 819 hifn_reset_puc(sc); 820 } 821 822 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 823 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 824 825 /* Bring dma unit out of reset */ 826 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 827 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 828 829 hifn_puc_wait(sc); 830 hifn_set_retry(sc); 831 832 if (sc->sc_flags & HIFN_IS_7811) { 833 for (reg = 0; reg < 1000; reg++) { 834 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 835 HIFN_MIPSRST_CRAMINIT) 836 break; 837 DELAY(1000); 838 } 839 if (reg == 1000) 840 printf(": cram init timeout\n"); 841 } 842} 843 844static u_int32_t 845hifn_next_signature(u_int32_t a, u_int cnt) 846{ 847 int i; 848 u_int32_t v; 849 850 for (i = 0; i < cnt; i++) { 851 852 /* get the parity */ 853 v = a & 0x80080125; 854 v ^= v >> 16; 855 v ^= v >> 8; 856 v ^= v >> 4; 857 v ^= v >> 2; 858 v ^= v >> 1; 859 860 a = (v & 1) ^ (a << 1); 861 } 862 863 return a; 864} 865 866struct pci2id { 867 u_short pci_vendor; 868 u_short pci_prod; 869 char card_id[13]; 870}; 871static struct pci2id pci2id[] = { 872 { 873 PCI_VENDOR_HIFN, 874 PCI_PRODUCT_HIFN_7951, 875 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 876 0x00, 0x00, 0x00, 0x00, 0x00 } 877 }, { 878 PCI_VENDOR_NETSEC, 879 PCI_PRODUCT_NETSEC_7751, 880 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 881 0x00, 0x00, 0x00, 0x00, 0x00 } 882 }, { 883 PCI_VENDOR_INVERTEX, 884 PCI_PRODUCT_INVERTEX_AEON, 885 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 886 0x00, 0x00, 0x00, 0x00, 0x00 } 887 }, { 888 PCI_VENDOR_HIFN, 889 PCI_PRODUCT_HIFN_7811, 890 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 891 0x00, 0x00, 0x00, 0x00, 0x00 } 892 }, { 893 /* 894 * Other vendors share this PCI ID as well, such as 895 * http://www.powercrypt.com, and obviously they also 896 * use the same key. 897 */ 898 PCI_VENDOR_HIFN, 899 PCI_PRODUCT_HIFN_7751, 900 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 901 0x00, 0x00, 0x00, 0x00, 0x00 } 902 }, 903}; 904 905/* 906 * Checks to see if crypto is already enabled. If crypto isn't enable, 907 * "hifn_enable_crypto" is called to enable it. The check is important, 908 * as enabling crypto twice will lock the board. 909 */ 910static int 911hifn_enable_crypto(struct hifn_softc *sc) 912{ 913 u_int32_t dmacfg, ramcfg, encl, addr, i; 914 char *offtbl = NULL; 915 916 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 917 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 918 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 919 offtbl = pci2id[i].card_id; 920 break; 921 } 922 } 923 if (offtbl == NULL) { 924 device_printf(sc->sc_dev, "Unknown card!\n"); 925 return (1); 926 } 927 928 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 929 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 930 931 /* 932 * The RAM config register's encrypt level bit needs to be set before 933 * every read performed on the encryption level register. 934 */ 935 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 936 937 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 938 939 /* 940 * Make sure we don't re-unlock. Two unlocks kills chip until the 941 * next reboot. 942 */ 943 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 944#ifdef HIFN_DEBUG 945 if (hifn_debug) 946 device_printf(sc->sc_dev, 947 "Strong crypto already enabled!\n"); 948#endif 949 goto report; 950 } 951 952 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 953#ifdef HIFN_DEBUG 954 if (hifn_debug) 955 device_printf(sc->sc_dev, 956 "Unknown encryption level 0x%x\n", encl); 957#endif 958 return 1; 959 } 960 961 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 962 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 963 DELAY(1000); 964 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 965 DELAY(1000); 966 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 967 DELAY(1000); 968 969 for (i = 0; i <= 12; i++) { 970 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 971 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 972 973 DELAY(1000); 974 } 975 976 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 977 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 978 979#ifdef HIFN_DEBUG 980 if (hifn_debug) { 981 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 982 device_printf(sc->sc_dev, "Engine is permanently " 983 "locked until next system reset!\n"); 984 else 985 device_printf(sc->sc_dev, "Engine enabled " 986 "successfully!\n"); 987 } 988#endif 989 990report: 991 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 992 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 993 994 switch (encl) { 995 case HIFN_PUSTAT_ENA_1: 996 case HIFN_PUSTAT_ENA_2: 997 break; 998 case HIFN_PUSTAT_ENA_0: 999 default: 1000 device_printf(sc->sc_dev, "disabled"); 1001 break; 1002 } 1003 1004 return 0; 1005} 1006 1007/* 1008 * Give initial values to the registers listed in the "Register Space" 1009 * section of the HIFN Software Development reference manual. 1010 */ 1011static void 1012hifn_init_pci_registers(struct hifn_softc *sc) 1013{ 1014 /* write fixed values needed by the Initialization registers */ 1015 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1016 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1017 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1018 1019 /* write all 4 ring address registers */ 1020 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1021 offsetof(struct hifn_dma, cmdr[0])); 1022 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1023 offsetof(struct hifn_dma, srcr[0])); 1024 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1025 offsetof(struct hifn_dma, dstr[0])); 1026 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1027 offsetof(struct hifn_dma, resr[0])); 1028 1029 DELAY(2000); 1030 1031 /* write status register */ 1032 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1033 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1034 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1035 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1036 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1037 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1038 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1039 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1040 HIFN_DMACSR_S_WAIT | 1041 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1042 HIFN_DMACSR_C_WAIT | 1043 HIFN_DMACSR_ENGINE | 1044 ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1045 HIFN_DMACSR_PUBDONE : 0) | 1046 ((sc->sc_flags & HIFN_IS_7811) ? 1047 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1048 1049 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1050 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1051 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1052 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1053 ((sc->sc_flags & HIFN_IS_7811) ? 1054 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1055 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1056 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1057 1058 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1059 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1060 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1061 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1062 1063 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1064 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1065 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1066 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1067 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1068} 1069 1070/* 1071 * The maximum number of sessions supported by the card 1072 * is dependent on the amount of context ram, which 1073 * encryption algorithms are enabled, and how compression 1074 * is configured. This should be configured before this 1075 * routine is called. 1076 */ 1077static void 1078hifn_sessions(struct hifn_softc *sc) 1079{ 1080 u_int32_t pucnfg; 1081 int ctxsize; 1082 1083 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1084 1085 if (pucnfg & HIFN_PUCNFG_COMPSING) { 1086 if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1087 ctxsize = 128; 1088 else 1089 ctxsize = 512; 1090 sc->sc_maxses = 1 + 1091 ((sc->sc_ramsize - 32768) / ctxsize); 1092 } else 1093 sc->sc_maxses = sc->sc_ramsize / 16384; 1094 1095 if (sc->sc_maxses > 2048) 1096 sc->sc_maxses = 2048; 1097} 1098 1099/* 1100 * Determine ram type (sram or dram). Board should be just out of a reset 1101 * state when this is called. 1102 */ 1103static int 1104hifn_ramtype(struct hifn_softc *sc) 1105{ 1106 u_int8_t data[8], dataexpect[8]; 1107 int i; 1108 1109 for (i = 0; i < sizeof(data); i++) 1110 data[i] = dataexpect[i] = 0x55; 1111 if (hifn_writeramaddr(sc, 0, data)) 1112 return (-1); 1113 if (hifn_readramaddr(sc, 0, data)) 1114 return (-1); 1115 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1116 sc->sc_drammodel = 1; 1117 return (0); 1118 } 1119 1120 for (i = 0; i < sizeof(data); i++) 1121 data[i] = dataexpect[i] = 0xaa; 1122 if (hifn_writeramaddr(sc, 0, data)) 1123 return (-1); 1124 if (hifn_readramaddr(sc, 0, data)) 1125 return (-1); 1126 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1127 sc->sc_drammodel = 1; 1128 return (0); 1129 } 1130 1131 return (0); 1132} 1133 1134#define HIFN_SRAM_MAX (32 << 20) 1135#define HIFN_SRAM_STEP_SIZE 16384 1136#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1137 1138static int 1139hifn_sramsize(struct hifn_softc *sc) 1140{ 1141 u_int32_t a; 1142 u_int8_t data[8]; 1143 u_int8_t dataexpect[sizeof(data)]; 1144 int32_t i; 1145 1146 for (i = 0; i < sizeof(data); i++) 1147 data[i] = dataexpect[i] = i ^ 0x5a; 1148 1149 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1150 a = i * HIFN_SRAM_STEP_SIZE; 1151 bcopy(&i, data, sizeof(i)); 1152 hifn_writeramaddr(sc, a, data); 1153 } 1154 1155 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1156 a = i * HIFN_SRAM_STEP_SIZE; 1157 bcopy(&i, dataexpect, sizeof(i)); 1158 if (hifn_readramaddr(sc, a, data) < 0) 1159 return (0); 1160 if (bcmp(data, dataexpect, sizeof(data)) != 0) 1161 return (0); 1162 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1163 } 1164 1165 return (0); 1166} 1167 1168/* 1169 * XXX For dram boards, one should really try all of the 1170 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1171 * is already set up correctly. 1172 */ 1173static int 1174hifn_dramsize(struct hifn_softc *sc) 1175{ 1176 u_int32_t cnfg; 1177 1178 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1179 HIFN_PUCNFG_DRAMMASK; 1180 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1181 return (0); 1182} 1183 1184static void 1185hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1186{ 1187 struct hifn_dma *dma = sc->sc_dma; 1188 1189 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1190 dma->cmdi = 0; 1191 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1192 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1193 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1194 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1195 } 1196 *cmdp = dma->cmdi++; 1197 dma->cmdk = dma->cmdi; 1198 1199 if (dma->srci == HIFN_D_SRC_RSIZE) { 1200 dma->srci = 0; 1201 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1202 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1203 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1204 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1205 } 1206 *srcp = dma->srci++; 1207 dma->srck = dma->srci; 1208 1209 if (dma->dsti == HIFN_D_DST_RSIZE) { 1210 dma->dsti = 0; 1211 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1212 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1213 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1214 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1215 } 1216 *dstp = dma->dsti++; 1217 dma->dstk = dma->dsti; 1218 1219 if (dma->resi == HIFN_D_RES_RSIZE) { 1220 dma->resi = 0; 1221 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1222 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1223 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1225 } 1226 *resp = dma->resi++; 1227 dma->resk = dma->resi; 1228} 1229 1230static int 1231hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1232{ 1233 struct hifn_dma *dma = sc->sc_dma; 1234 hifn_base_command_t wc; 1235 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1236 int r, cmdi, resi, srci, dsti; 1237 1238 wc.masks = htole16(3 << 13); 1239 wc.session_num = htole16(addr >> 14); 1240 wc.total_source_count = htole16(8); 1241 wc.total_dest_count = htole16(addr & 0x3fff); 1242 1243 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1244 1245 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1246 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1247 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1248 1249 /* build write command */ 1250 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1251 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1252 bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1253 1254 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1255 + offsetof(struct hifn_dma, test_src)); 1256 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1257 + offsetof(struct hifn_dma, test_dst)); 1258 1259 dma->cmdr[cmdi].l = htole32(16 | masks); 1260 dma->srcr[srci].l = htole32(8 | masks); 1261 dma->dstr[dsti].l = htole32(4 | masks); 1262 dma->resr[resi].l = htole32(4 | masks); 1263 1264 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1266 1267 for (r = 10000; r >= 0; r--) { 1268 DELAY(10); 1269 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1270 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1271 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1272 break; 1273 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1274 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1275 } 1276 if (r == 0) { 1277 device_printf(sc->sc_dev, "writeramaddr -- " 1278 "result[%d](addr %d) still valid\n", resi, addr); 1279 r = -1; 1280 return (-1); 1281 } else 1282 r = 0; 1283 1284 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1285 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1286 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1287 1288 return (r); 1289} 1290 1291static int 1292hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1293{ 1294 struct hifn_dma *dma = sc->sc_dma; 1295 hifn_base_command_t rc; 1296 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1297 int r, cmdi, srci, dsti, resi; 1298 1299 rc.masks = htole16(2 << 13); 1300 rc.session_num = htole16(addr >> 14); 1301 rc.total_source_count = htole16(addr & 0x3fff); 1302 rc.total_dest_count = htole16(8); 1303 1304 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1305 1306 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1307 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1308 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1309 1310 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1311 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1312 1313 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1314 offsetof(struct hifn_dma, test_src)); 1315 dma->test_src = 0; 1316 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1317 offsetof(struct hifn_dma, test_dst)); 1318 dma->test_dst = 0; 1319 dma->cmdr[cmdi].l = htole32(8 | masks); 1320 dma->srcr[srci].l = htole32(8 | masks); 1321 dma->dstr[dsti].l = htole32(8 | masks); 1322 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1323 1324 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1325 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1326 1327 for (r = 10000; r >= 0; r--) { 1328 DELAY(10); 1329 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1330 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1331 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1332 break; 1333 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1335 } 1336 if (r == 0) { 1337 device_printf(sc->sc_dev, "readramaddr -- " 1338 "result[%d](addr %d) still valid\n", resi, addr); 1339 r = -1; 1340 } else { 1341 r = 0; 1342 bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1343 } 1344 1345 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1346 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1347 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1348 1349 return (r); 1350} 1351 1352/* 1353 * Initialize the descriptor rings. 1354 */ 1355static void 1356hifn_init_dma(struct hifn_softc *sc) 1357{ 1358 struct hifn_dma *dma = sc->sc_dma; 1359 int i; 1360 1361 hifn_set_retry(sc); 1362 1363 /* initialize static pointer values */ 1364 for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1365 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1366 offsetof(struct hifn_dma, command_bufs[i][0])); 1367 for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1368 dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1369 offsetof(struct hifn_dma, result_bufs[i][0])); 1370 1371 dma->cmdr[HIFN_D_CMD_RSIZE].p = 1372 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1373 dma->srcr[HIFN_D_SRC_RSIZE].p = 1374 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1375 dma->dstr[HIFN_D_DST_RSIZE].p = 1376 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1377 dma->resr[HIFN_D_RES_RSIZE].p = 1378 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1379 1380 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1381 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1382 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1383} 1384 1385/* 1386 * Writes out the raw command buffer space. Returns the 1387 * command buffer size. 1388 */ 1389static u_int 1390hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1391{ 1392 u_int8_t *buf_pos; 1393 hifn_base_command_t *base_cmd; 1394 hifn_mac_command_t *mac_cmd; 1395 hifn_crypt_command_t *cry_cmd; 1396 int using_mac, using_crypt, len; 1397 u_int32_t dlen, slen; 1398 1399 buf_pos = buf; 1400 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1401 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1402 1403 base_cmd = (hifn_base_command_t *)buf_pos; 1404 base_cmd->masks = htole16(cmd->base_masks); 1405 slen = cmd->src_mapsize; 1406 if (cmd->sloplen) 1407 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1408 else 1409 dlen = cmd->dst_mapsize; 1410 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1411 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1412 dlen >>= 16; 1413 slen >>= 16; 1414 base_cmd->session_num = htole16(cmd->session_num | 1415 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1416 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1417 buf_pos += sizeof(hifn_base_command_t); 1418 1419 if (using_mac) { 1420 mac_cmd = (hifn_mac_command_t *)buf_pos; 1421 dlen = cmd->maccrd->crd_len; 1422 mac_cmd->source_count = htole16(dlen & 0xffff); 1423 dlen >>= 16; 1424 mac_cmd->masks = htole16(cmd->mac_masks | 1425 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1426 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1427 mac_cmd->reserved = 0; 1428 buf_pos += sizeof(hifn_mac_command_t); 1429 } 1430 1431 if (using_crypt) { 1432 cry_cmd = (hifn_crypt_command_t *)buf_pos; 1433 dlen = cmd->enccrd->crd_len; 1434 cry_cmd->source_count = htole16(dlen & 0xffff); 1435 dlen >>= 16; 1436 cry_cmd->masks = htole16(cmd->cry_masks | 1437 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1438 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1439 cry_cmd->reserved = 0; 1440 buf_pos += sizeof(hifn_crypt_command_t); 1441 } 1442 1443 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1444 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1445 buf_pos += HIFN_MAC_KEY_LENGTH; 1446 } 1447 1448 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1449 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1450 case HIFN_CRYPT_CMD_ALG_3DES: 1451 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1452 buf_pos += HIFN_3DES_KEY_LENGTH; 1453 break; 1454 case HIFN_CRYPT_CMD_ALG_DES: 1455 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1456 buf_pos += cmd->cklen; 1457 break; 1458 case HIFN_CRYPT_CMD_ALG_RC4: 1459 len = 256; 1460 do { 1461 int clen; 1462 1463 clen = MIN(cmd->cklen, len); 1464 bcopy(cmd->ck, buf_pos, clen); 1465 len -= clen; 1466 buf_pos += clen; 1467 } while (len > 0); 1468 bzero(buf_pos, 4); 1469 buf_pos += 4; 1470 break; 1471 } 1472 } 1473 1474 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1475 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1476 buf_pos += HIFN_IV_LENGTH; 1477 } 1478 1479 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1480 bzero(buf_pos, 8); 1481 buf_pos += 8; 1482 } 1483 1484 return (buf_pos - buf); 1485} 1486 1487static int 1488hifn_dmamap_aligned(struct hifn_operand *op) 1489{ 1490 int i; 1491 1492 for (i = 0; i < op->nsegs; i++) { 1493 if (op->segs[i].ds_addr & 3) 1494 return (0); 1495 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1496 return (0); 1497 } 1498 return (1); 1499} 1500 1501static int 1502hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1503{ 1504 struct hifn_dma *dma = sc->sc_dma; 1505 struct hifn_operand *dst = &cmd->dst; 1506 u_int32_t p, l; 1507 int idx, used = 0, i; 1508 1509 idx = dma->dsti; 1510 for (i = 0; i < dst->nsegs - 1; i++) { 1511 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1512 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1513 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1514 HIFN_DSTR_SYNC(sc, idx, 1515 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1516 used++; 1517 1518 if (++idx == HIFN_D_DST_RSIZE) { 1519 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1520 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1521 HIFN_DSTR_SYNC(sc, idx, 1522 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1523 idx = 0; 1524 } 1525 } 1526 1527 if (cmd->sloplen == 0) { 1528 p = dst->segs[i].ds_addr; 1529 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1530 dst->segs[i].ds_len; 1531 } else { 1532 p = sc->sc_dma_physaddr + 1533 offsetof(struct hifn_dma, slop[cmd->slopidx]); 1534 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1535 sizeof(u_int32_t); 1536 1537 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1538 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1539 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1540 HIFN_D_MASKDONEIRQ | 1541 (dst->segs[i].ds_len - cmd->sloplen)); 1542 HIFN_DSTR_SYNC(sc, idx, 1543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1544 used++; 1545 1546 if (++idx == HIFN_D_DST_RSIZE) { 1547 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1548 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1549 HIFN_DSTR_SYNC(sc, idx, 1550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1551 idx = 0; 1552 } 1553 } 1554 } 1555 dma->dstr[idx].p = htole32(p); 1556 dma->dstr[idx].l = htole32(l); 1557 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1558 used++; 1559 1560 if (++idx == HIFN_D_DST_RSIZE) { 1561 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1562 HIFN_D_MASKDONEIRQ); 1563 HIFN_DSTR_SYNC(sc, idx, 1564 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1565 idx = 0; 1566 } 1567 1568 dma->dsti = idx; 1569 dma->dstu += used; 1570 return (idx); 1571} 1572 1573static int 1574hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1575{ 1576 struct hifn_dma *dma = sc->sc_dma; 1577 struct hifn_operand *src = &cmd->src; 1578 int idx, i; 1579 u_int32_t last = 0; 1580 1581 idx = dma->srci; 1582 for (i = 0; i < src->nsegs; i++) { 1583 if (i == src->nsegs - 1) 1584 last = HIFN_D_LAST; 1585 1586 dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1587 dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1588 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1589 HIFN_SRCR_SYNC(sc, idx, 1590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1591 1592 if (++idx == HIFN_D_SRC_RSIZE) { 1593 dma->srcr[idx].l = htole32(HIFN_D_VALID | 1594 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1595 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1597 idx = 0; 1598 } 1599 } 1600 dma->srci = idx; 1601 dma->srcu += src->nsegs; 1602 return (idx); 1603} 1604 1605static void 1606hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1607{ 1608 struct hifn_operand *op = arg; 1609 1610 KASSERT(nsegs <= MAX_SCATTER, 1611 ("hifn_op_cb: too many DMA segments (%u > %u) " 1612 "returned when mapping operand", nsegs, MAX_SCATTER)); 1613 op->mapsize = mapsize; 1614 op->nsegs = nsegs; 1615 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1616} 1617 1618static int 1619hifn_crypto( 1620 struct hifn_softc *sc, 1621 struct hifn_command *cmd, 1622 struct cryptop *crp, 1623 int hint) 1624{ 1625 struct hifn_dma *dma = sc->sc_dma; 1626 u_int32_t cmdlen; 1627 int cmdi, resi, err = 0; 1628 1629 /* 1630 * need 1 cmd, and 1 res 1631 * 1632 * NB: check this first since it's easy. 1633 */ 1634 HIFN_LOCK(sc); 1635 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1636 (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1637#ifdef HIFN_DEBUG 1638 if (hifn_debug) { 1639 device_printf(sc->sc_dev, 1640 "cmd/result exhaustion, cmdu %u resu %u\n", 1641 dma->cmdu, dma->resu); 1642 } 1643#endif 1644 hifnstats.hst_nomem_cr++; 1645 HIFN_UNLOCK(sc); 1646 return (ERESTART); 1647 } 1648 1649 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1650 hifnstats.hst_nomem_map++; 1651 HIFN_UNLOCK(sc); 1652 return (ENOMEM); 1653 } 1654 1655 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1656 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1657 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1658 hifnstats.hst_nomem_load++; 1659 err = ENOMEM; 1660 goto err_srcmap1; 1661 } 1662 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1663 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1664 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1665 hifnstats.hst_nomem_load++; 1666 err = ENOMEM; 1667 goto err_srcmap1; 1668 } 1669 } else { 1670 err = EINVAL; 1671 goto err_srcmap1; 1672 } 1673 1674 if (hifn_dmamap_aligned(&cmd->src)) { 1675 cmd->sloplen = cmd->src_mapsize & 3; 1676 cmd->dst = cmd->src; 1677 } else { 1678 if (crp->crp_flags & CRYPTO_F_IOV) { 1679 err = EINVAL; 1680 goto err_srcmap; 1681 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1682 int totlen, len; 1683 struct mbuf *m, *m0, *mlast; 1684 1685 KASSERT(cmd->dst_m == cmd->src_m, 1686 ("hifn_crypto: dst_m initialized improperly")); 1687 hifnstats.hst_unaligned++; 1688 /* 1689 * Source is not aligned on a longword boundary. 1690 * Copy the data to insure alignment. If we fail 1691 * to allocate mbufs or clusters while doing this 1692 * we return ERESTART so the operation is requeued 1693 * at the crypto later, but only if there are 1694 * ops already posted to the hardware; otherwise we 1695 * have no guarantee that we'll be re-entered. 1696 */ 1697 totlen = cmd->src_mapsize; 1698 if (cmd->src_m->m_flags & M_PKTHDR) { 1699 len = MHLEN; 1700 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1701 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1702 m_free(m0); 1703 m0 = NULL; 1704 } 1705 } else { 1706 len = MLEN; 1707 MGET(m0, M_DONTWAIT, MT_DATA); 1708 } 1709 if (m0 == NULL) { 1710 hifnstats.hst_nomem_mbuf++; 1711 err = dma->cmdu ? ERESTART : ENOMEM; 1712 goto err_srcmap; 1713 } 1714 if (totlen >= MINCLSIZE) { 1715 MCLGET(m0, M_DONTWAIT); 1716 if ((m0->m_flags & M_EXT) == 0) { 1717 hifnstats.hst_nomem_mcl++; 1718 err = dma->cmdu ? ERESTART : ENOMEM; 1719 m_freem(m0); 1720 goto err_srcmap; 1721 } 1722 len = MCLBYTES; 1723 } 1724 totlen -= len; 1725 m0->m_pkthdr.len = m0->m_len = len; 1726 mlast = m0; 1727 1728 while (totlen > 0) { 1729 MGET(m, M_DONTWAIT, MT_DATA); 1730 if (m == NULL) { 1731 hifnstats.hst_nomem_mbuf++; 1732 err = dma->cmdu ? ERESTART : ENOMEM; 1733 m_freem(m0); 1734 goto err_srcmap; 1735 } 1736 len = MLEN; 1737 if (totlen >= MINCLSIZE) { 1738 MCLGET(m, M_DONTWAIT); 1739 if ((m->m_flags & M_EXT) == 0) { 1740 hifnstats.hst_nomem_mcl++; 1741 err = dma->cmdu ? ERESTART : ENOMEM; 1742 mlast->m_next = m; 1743 m_freem(m0); 1744 goto err_srcmap; 1745 } 1746 len = MCLBYTES; 1747 } 1748 1749 m->m_len = len; 1750 m0->m_pkthdr.len += len; 1751 totlen -= len; 1752 1753 mlast->m_next = m; 1754 mlast = m; 1755 } 1756 cmd->dst_m = m0; 1757 } 1758 } 1759 1760 if (cmd->dst_map == NULL) { 1761 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1762 hifnstats.hst_nomem_map++; 1763 err = ENOMEM; 1764 goto err_srcmap; 1765 } 1766 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1767 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1768 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1769 hifnstats.hst_nomem_map++; 1770 err = ENOMEM; 1771 goto err_dstmap1; 1772 } 1773 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1774 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1775 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1776 hifnstats.hst_nomem_load++; 1777 err = ENOMEM; 1778 goto err_dstmap1; 1779 } 1780 } 1781 } 1782 1783#ifdef HIFN_DEBUG 1784 if (hifn_debug) { 1785 device_printf(sc->sc_dev, 1786 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1787 READ_REG_1(sc, HIFN_1_DMA_CSR), 1788 READ_REG_1(sc, HIFN_1_DMA_IER), 1789 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1790 cmd->src_nsegs, cmd->dst_nsegs); 1791 } 1792#endif 1793 1794 if (cmd->src_map == cmd->dst_map) { 1795 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1796 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1797 } else { 1798 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1799 BUS_DMASYNC_PREWRITE); 1800 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1801 BUS_DMASYNC_PREREAD); 1802 } 1803 1804 /* 1805 * need N src, and N dst 1806 */ 1807 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1808 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1809#ifdef HIFN_DEBUG 1810 if (hifn_debug) { 1811 device_printf(sc->sc_dev, 1812 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1813 dma->srcu, cmd->src_nsegs, 1814 dma->dstu, cmd->dst_nsegs); 1815 } 1816#endif 1817 hifnstats.hst_nomem_sd++; 1818 err = ERESTART; 1819 goto err_dstmap; 1820 } 1821 1822 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1823 dma->cmdi = 0; 1824 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1825 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1826 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1827 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1828 } 1829 cmdi = dma->cmdi++; 1830 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1831 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1832 1833 /* .p for command/result already set */ 1834 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1835 HIFN_D_MASKDONEIRQ); 1836 HIFN_CMDR_SYNC(sc, cmdi, 1837 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1838 dma->cmdu++; 1839 if (sc->sc_c_busy == 0) { 1840 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1841 sc->sc_c_busy = 1; 1842 } 1843 1844 /* 1845 * We don't worry about missing an interrupt (which a "command wait" 1846 * interrupt salvages us from), unless there is more than one command 1847 * in the queue. 1848 */ 1849 if (dma->cmdu > 1) { 1850 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1851 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1852 } 1853 1854 hifnstats.hst_ipackets++; 1855 hifnstats.hst_ibytes += cmd->src_mapsize; 1856 1857 hifn_dmamap_load_src(sc, cmd); 1858 if (sc->sc_s_busy == 0) { 1859 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1860 sc->sc_s_busy = 1; 1861 } 1862 1863 /* 1864 * Unlike other descriptors, we don't mask done interrupt from 1865 * result descriptor. 1866 */ 1867#ifdef HIFN_DEBUG 1868 if (hifn_debug) 1869 printf("load res\n"); 1870#endif 1871 if (dma->resi == HIFN_D_RES_RSIZE) { 1872 dma->resi = 0; 1873 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1874 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1875 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1877 } 1878 resi = dma->resi++; 1879 KASSERT(dma->hifn_commands[resi] == NULL, 1880 ("hifn_crypto: command slot %u busy", resi)); 1881 dma->hifn_commands[resi] = cmd; 1882 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1883 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1884 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1885 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1886 sc->sc_curbatch++; 1887 if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1888 hifnstats.hst_maxbatch = sc->sc_curbatch; 1889 hifnstats.hst_totbatch++; 1890 } else { 1891 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1892 HIFN_D_VALID | HIFN_D_LAST); 1893 sc->sc_curbatch = 0; 1894 } 1895 HIFN_RESR_SYNC(sc, resi, 1896 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1897 dma->resu++; 1898 if (sc->sc_r_busy == 0) { 1899 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1900 sc->sc_r_busy = 1; 1901 } 1902 1903 if (cmd->sloplen) 1904 cmd->slopidx = resi; 1905 1906 hifn_dmamap_load_dst(sc, cmd); 1907 1908 if (sc->sc_d_busy == 0) { 1909 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1910 sc->sc_d_busy = 1; 1911 } 1912 1913#ifdef HIFN_DEBUG 1914 if (hifn_debug) { 1915 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1916 READ_REG_1(sc, HIFN_1_DMA_CSR), 1917 READ_REG_1(sc, HIFN_1_DMA_IER)); 1918 } 1919#endif 1920 1921 sc->sc_active = 5; 1922 HIFN_UNLOCK(sc); 1923 KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1924 return (err); /* success */ 1925 1926err_dstmap: 1927 if (cmd->src_map != cmd->dst_map) 1928 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1929err_dstmap1: 1930 if (cmd->src_map != cmd->dst_map) 1931 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1932err_srcmap: 1933 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1934 if (cmd->src_m != cmd->dst_m) 1935 m_freem(cmd->dst_m); 1936 } 1937 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1938err_srcmap1: 1939 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1940 HIFN_UNLOCK(sc); 1941 return (err); 1942} 1943 1944static void 1945hifn_tick(void* vsc) 1946{ 1947 struct hifn_softc *sc = vsc; 1948 1949 HIFN_LOCK(sc); 1950 if (sc->sc_active == 0) { 1951 struct hifn_dma *dma = sc->sc_dma; 1952 u_int32_t r = 0; 1953 1954 if (dma->cmdu == 0 && sc->sc_c_busy) { 1955 sc->sc_c_busy = 0; 1956 r |= HIFN_DMACSR_C_CTRL_DIS; 1957 } 1958 if (dma->srcu == 0 && sc->sc_s_busy) { 1959 sc->sc_s_busy = 0; 1960 r |= HIFN_DMACSR_S_CTRL_DIS; 1961 } 1962 if (dma->dstu == 0 && sc->sc_d_busy) { 1963 sc->sc_d_busy = 0; 1964 r |= HIFN_DMACSR_D_CTRL_DIS; 1965 } 1966 if (dma->resu == 0 && sc->sc_r_busy) { 1967 sc->sc_r_busy = 0; 1968 r |= HIFN_DMACSR_R_CTRL_DIS; 1969 } 1970 if (r) 1971 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1972 } else 1973 sc->sc_active--; 1974 HIFN_UNLOCK(sc); 1975 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1976} 1977 1978static void 1979hifn_intr(void *arg) 1980{ 1981 struct hifn_softc *sc = arg; 1982 struct hifn_dma *dma; 1983 u_int32_t dmacsr, restart; 1984 int i, u; 1985 1986 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1987 1988 /* Nothing in the DMA unit interrupted */ 1989 if ((dmacsr & sc->sc_dmaier) == 0) 1990 return; 1991 1992 HIFN_LOCK(sc); 1993 1994 dma = sc->sc_dma; 1995 1996#ifdef HIFN_DEBUG 1997 if (hifn_debug) { 1998 device_printf(sc->sc_dev, 1999 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2000 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2001 dma->cmdi, dma->srci, dma->dsti, dma->resi, 2002 dma->cmdk, dma->srck, dma->dstk, dma->resk, 2003 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2004 } 2005#endif 2006 2007 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2008 2009 if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2010 (dmacsr & HIFN_DMACSR_PUBDONE)) 2011 WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2012 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2013 2014 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2015 if (restart) 2016 device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2017 2018 if (sc->sc_flags & HIFN_IS_7811) { 2019 if (dmacsr & HIFN_DMACSR_ILLR) 2020 device_printf(sc->sc_dev, "illegal read\n"); 2021 if (dmacsr & HIFN_DMACSR_ILLW) 2022 device_printf(sc->sc_dev, "illegal write\n"); 2023 } 2024 2025 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2026 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2027 if (restart) { 2028 device_printf(sc->sc_dev, "abort, resetting.\n"); 2029 hifnstats.hst_abort++; 2030 hifn_abort(sc); 2031 HIFN_UNLOCK(sc); 2032 return; 2033 } 2034 2035 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2036 /* 2037 * If no slots to process and we receive a "waiting on 2038 * command" interrupt, we disable the "waiting on command" 2039 * (by clearing it). 2040 */ 2041 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2042 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2043 } 2044 2045 /* clear the rings */ 2046 i = dma->resk; u = dma->resu; 2047 while (u != 0) { 2048 HIFN_RESR_SYNC(sc, i, 2049 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2050 if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2051 HIFN_RESR_SYNC(sc, i, 2052 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2053 break; 2054 } 2055 2056 if (i != HIFN_D_RES_RSIZE) { 2057 struct hifn_command *cmd; 2058 u_int8_t *macbuf = NULL; 2059 2060 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2061 cmd = dma->hifn_commands[i]; 2062 KASSERT(cmd != NULL, 2063 ("hifn_intr: null command slot %u", i)); 2064 dma->hifn_commands[i] = NULL; 2065 2066 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2067 macbuf = dma->result_bufs[i]; 2068 macbuf += 12; 2069 } 2070 2071 hifn_callback(sc, cmd, macbuf); 2072 hifnstats.hst_opackets++; 2073 u--; 2074 } 2075 2076 if (++i == (HIFN_D_RES_RSIZE + 1)) 2077 i = 0; 2078 } 2079 dma->resk = i; dma->resu = u; 2080 2081 i = dma->srck; u = dma->srcu; 2082 while (u != 0) { 2083 if (i == HIFN_D_SRC_RSIZE) 2084 i = 0; 2085 HIFN_SRCR_SYNC(sc, i, 2086 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2087 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2088 HIFN_SRCR_SYNC(sc, i, 2089 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2090 break; 2091 } 2092 i++, u--; 2093 } 2094 dma->srck = i; dma->srcu = u; 2095 2096 i = dma->cmdk; u = dma->cmdu; 2097 while (u != 0) { 2098 HIFN_CMDR_SYNC(sc, i, 2099 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2100 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2101 HIFN_CMDR_SYNC(sc, i, 2102 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2103 break; 2104 } 2105 if (i != HIFN_D_CMD_RSIZE) { 2106 u--; 2107 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2108 } 2109 if (++i == (HIFN_D_CMD_RSIZE + 1)) 2110 i = 0; 2111 } 2112 dma->cmdk = i; dma->cmdu = u; 2113 2114 HIFN_UNLOCK(sc); 2115 2116 if (sc->sc_needwakeup) { /* XXX check high watermark */ 2117 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2118#ifdef HIFN_DEBUG 2119 if (hifn_debug) 2120 device_printf(sc->sc_dev, 2121 "wakeup crypto (%x) u %d/%d/%d/%d\n", 2122 sc->sc_needwakeup, 2123 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2124#endif 2125 sc->sc_needwakeup &= ~wakeup; 2126 crypto_unblock(sc->sc_cid, wakeup); 2127 } 2128} 2129 2130/* 2131 * Allocate a new 'session' and return an encoded session id. 'sidp' 2132 * contains our registration id, and should contain an encoded session 2133 * id on successful allocation. 2134 */ 2135static int 2136hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2137{ 2138 struct cryptoini *c; 2139 struct hifn_softc *sc = arg; 2140 int i, mac = 0, cry = 0; 2141 2142 KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2143 if (sidp == NULL || cri == NULL || sc == NULL) 2144 return (EINVAL); 2145 2146 for (i = 0; i < sc->sc_maxses; i++) 2147 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2148 break; 2149 if (i == sc->sc_maxses) 2150 return (ENOMEM); 2151 2152 for (c = cri; c != NULL; c = c->cri_next) { 2153 switch (c->cri_alg) { 2154 case CRYPTO_MD5: 2155 case CRYPTO_SHA1: 2156 case CRYPTO_MD5_HMAC: 2157 case CRYPTO_SHA1_HMAC: 2158 if (mac) 2159 return (EINVAL); 2160 mac = 1; 2161 break; 2162 case CRYPTO_DES_CBC: 2163 case CRYPTO_3DES_CBC: 2164 /* XXX this may read fewer, does it matter? */ 2165 read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2166 /*FALLTHROUGH*/ 2167 case CRYPTO_ARC4: 2168 if (cry) 2169 return (EINVAL); 2170 cry = 1; 2171 break; 2172 default: 2173 return (EINVAL); 2174 } 2175 } 2176 if (mac == 0 && cry == 0) 2177 return (EINVAL); 2178 2179 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2180 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2181 2182 return (0); 2183} 2184 2185/* 2186 * Deallocate a session. 2187 * XXX this routine should run a zero'd mac/encrypt key into context ram. 2188 * XXX to blow away any keys already stored there. 2189 */ 2190static int 2191hifn_freesession(void *arg, u_int64_t tid) 2192{ 2193 struct hifn_softc *sc = arg; 2194 int session; 2195 u_int32_t sid = CRYPTO_SESID2LID(tid); 2196 2197 KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2198 if (sc == NULL) 2199 return (EINVAL); 2200 2201 session = HIFN_SESSION(sid); 2202 if (session >= sc->sc_maxses) 2203 return (EINVAL); 2204 2205 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2206 return (0); 2207} 2208 2209static int 2210hifn_process(void *arg, struct cryptop *crp, int hint) 2211{ 2212 struct hifn_softc *sc = arg; 2213 struct hifn_command *cmd = NULL; 2214 int session, err; 2215 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2216 2217 if (crp == NULL || crp->crp_callback == NULL) { 2218 hifnstats.hst_invalid++; 2219 return (EINVAL); 2220 } 2221 session = HIFN_SESSION(crp->crp_sid); 2222 2223 if (sc == NULL || session >= sc->sc_maxses) { 2224 err = EINVAL; 2225 goto errout; 2226 } 2227 2228 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2229 if (cmd == NULL) { 2230 hifnstats.hst_nomem++; 2231 err = ENOMEM; 2232 goto errout; 2233 } 2234 2235 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2236 cmd->src_m = (struct mbuf *)crp->crp_buf; 2237 cmd->dst_m = (struct mbuf *)crp->crp_buf; 2238 } else if (crp->crp_flags & CRYPTO_F_IOV) { 2239 cmd->src_io = (struct uio *)crp->crp_buf; 2240 cmd->dst_io = (struct uio *)crp->crp_buf; 2241 } else { 2242 err = EINVAL; 2243 goto errout; /* XXX we don't handle contiguous buffers! */ 2244 } 2245 2246 crd1 = crp->crp_desc; 2247 if (crd1 == NULL) { 2248 err = EINVAL; 2249 goto errout; 2250 } 2251 crd2 = crd1->crd_next; 2252 2253 if (crd2 == NULL) { 2254 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2255 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2256 crd1->crd_alg == CRYPTO_SHA1 || 2257 crd1->crd_alg == CRYPTO_MD5) { 2258 maccrd = crd1; 2259 enccrd = NULL; 2260 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2261 crd1->crd_alg == CRYPTO_3DES_CBC || 2262 crd1->crd_alg == CRYPTO_ARC4) { 2263 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2264 cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2265 maccrd = NULL; 2266 enccrd = crd1; 2267 } else { 2268 err = EINVAL; 2269 goto errout; 2270 } 2271 } else { 2272 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2273 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2274 crd1->crd_alg == CRYPTO_MD5 || 2275 crd1->crd_alg == CRYPTO_SHA1) && 2276 (crd2->crd_alg == CRYPTO_DES_CBC || 2277 crd2->crd_alg == CRYPTO_3DES_CBC || 2278 crd2->crd_alg == CRYPTO_ARC4) && 2279 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2280 cmd->base_masks = HIFN_BASE_CMD_DECODE; 2281 maccrd = crd1; 2282 enccrd = crd2; 2283 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2284 crd1->crd_alg == CRYPTO_ARC4 || 2285 crd1->crd_alg == CRYPTO_3DES_CBC) && 2286 (crd2->crd_alg == CRYPTO_MD5_HMAC || 2287 crd2->crd_alg == CRYPTO_SHA1_HMAC || 2288 crd2->crd_alg == CRYPTO_MD5 || 2289 crd2->crd_alg == CRYPTO_SHA1) && 2290 (crd1->crd_flags & CRD_F_ENCRYPT)) { 2291 enccrd = crd1; 2292 maccrd = crd2; 2293 } else { 2294 /* 2295 * We cannot order the 7751 as requested 2296 */ 2297 err = EINVAL; 2298 goto errout; 2299 } 2300 } 2301 2302 if (enccrd) { 2303 cmd->enccrd = enccrd; 2304 cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2305 switch (enccrd->crd_alg) { 2306 case CRYPTO_ARC4: 2307 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2308 if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2309 != sc->sc_sessions[session].hs_prev_op) 2310 sc->sc_sessions[session].hs_state = 2311 HS_STATE_USED; 2312 break; 2313 case CRYPTO_DES_CBC: 2314 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2315 HIFN_CRYPT_CMD_MODE_CBC | 2316 HIFN_CRYPT_CMD_NEW_IV; 2317 break; 2318 case CRYPTO_3DES_CBC: 2319 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2320 HIFN_CRYPT_CMD_MODE_CBC | 2321 HIFN_CRYPT_CMD_NEW_IV; 2322 break; 2323 default: 2324 err = EINVAL; 2325 goto errout; 2326 } 2327 if (enccrd->crd_alg != CRYPTO_ARC4) { 2328 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2329 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2330 bcopy(enccrd->crd_iv, cmd->iv, 2331 HIFN_IV_LENGTH); 2332 else 2333 bcopy(sc->sc_sessions[session].hs_iv, 2334 cmd->iv, HIFN_IV_LENGTH); 2335 2336 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2337 == 0) { 2338 if (crp->crp_flags & CRYPTO_F_IMBUF) 2339 m_copyback(cmd->src_m, 2340 enccrd->crd_inject, 2341 HIFN_IV_LENGTH, cmd->iv); 2342 else if (crp->crp_flags & CRYPTO_F_IOV) 2343 cuio_copyback(cmd->src_io, 2344 enccrd->crd_inject, 2345 HIFN_IV_LENGTH, cmd->iv); 2346 } 2347 } else { 2348 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2349 bcopy(enccrd->crd_iv, cmd->iv, 2350 HIFN_IV_LENGTH); 2351 else if (crp->crp_flags & CRYPTO_F_IMBUF) 2352 m_copydata(cmd->src_m, 2353 enccrd->crd_inject, 2354 HIFN_IV_LENGTH, cmd->iv); 2355 else if (crp->crp_flags & CRYPTO_F_IOV) 2356 cuio_copydata(cmd->src_io, 2357 enccrd->crd_inject, 2358 HIFN_IV_LENGTH, cmd->iv); 2359 } 2360 } 2361 2362 cmd->ck = enccrd->crd_key; 2363 cmd->cklen = enccrd->crd_klen >> 3; 2364 2365 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2366 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2367 } 2368 2369 if (maccrd) { 2370 cmd->maccrd = maccrd; 2371 cmd->base_masks |= HIFN_BASE_CMD_MAC; 2372 2373 switch (maccrd->crd_alg) { 2374 case CRYPTO_MD5: 2375 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2376 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2377 HIFN_MAC_CMD_POS_IPSEC; 2378 break; 2379 case CRYPTO_MD5_HMAC: 2380 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2381 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2382 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2383 break; 2384 case CRYPTO_SHA1: 2385 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2386 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2387 HIFN_MAC_CMD_POS_IPSEC; 2388 break; 2389 case CRYPTO_SHA1_HMAC: 2390 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2391 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2392 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2393 break; 2394 } 2395 2396 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2397 maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2398 sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2399 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2400 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2401 bzero(cmd->mac + (maccrd->crd_klen >> 3), 2402 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2403 } 2404 } 2405 2406 cmd->crp = crp; 2407 cmd->session_num = session; 2408 cmd->softc = sc; 2409 2410 err = hifn_crypto(sc, cmd, crp, hint); 2411 if (!err) { 2412 if (enccrd) 2413 sc->sc_sessions[session].hs_prev_op = 2414 enccrd->crd_flags & CRD_F_ENCRYPT; 2415 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2416 sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2417 return 0; 2418 } else if (err == ERESTART) { 2419 /* 2420 * There weren't enough resources to dispatch the request 2421 * to the part. Notify the caller so they'll requeue this 2422 * request and resubmit it again soon. 2423 */ 2424#ifdef HIFN_DEBUG 2425 if (hifn_debug) 2426 device_printf(sc->sc_dev, "requeue request\n"); 2427#endif 2428 free(cmd, M_DEVBUF); 2429 sc->sc_needwakeup |= CRYPTO_SYMQ; 2430 return (err); 2431 } 2432 2433errout: 2434 if (cmd != NULL) 2435 free(cmd, M_DEVBUF); 2436 if (err == EINVAL) 2437 hifnstats.hst_invalid++; 2438 else 2439 hifnstats.hst_nomem++; 2440 crp->crp_etype = err; 2441 crypto_done(crp); 2442 return (err); 2443} 2444 2445static void 2446hifn_abort(struct hifn_softc *sc) 2447{ 2448 struct hifn_dma *dma = sc->sc_dma; 2449 struct hifn_command *cmd; 2450 struct cryptop *crp; 2451 int i, u; 2452 2453 i = dma->resk; u = dma->resu; 2454 while (u != 0) { 2455 cmd = dma->hifn_commands[i]; 2456 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2457 dma->hifn_commands[i] = NULL; 2458 crp = cmd->crp; 2459 2460 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2461 /* Salvage what we can. */ 2462 u_int8_t *macbuf; 2463 2464 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2465 macbuf = dma->result_bufs[i]; 2466 macbuf += 12; 2467 } else 2468 macbuf = NULL; 2469 hifnstats.hst_opackets++; 2470 hifn_callback(sc, cmd, macbuf); 2471 } else { 2472 if (cmd->src_map == cmd->dst_map) { 2473 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2474 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2475 } else { 2476 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2477 BUS_DMASYNC_POSTWRITE); 2478 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2479 BUS_DMASYNC_POSTREAD); 2480 } 2481 2482 if (cmd->src_m != cmd->dst_m) { 2483 m_freem(cmd->src_m); 2484 crp->crp_buf = (caddr_t)cmd->dst_m; 2485 } 2486 2487 /* non-shared buffers cannot be restarted */ 2488 if (cmd->src_map != cmd->dst_map) { 2489 /* 2490 * XXX should be EAGAIN, delayed until 2491 * after the reset. 2492 */ 2493 crp->crp_etype = ENOMEM; 2494 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2495 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2496 } else 2497 crp->crp_etype = ENOMEM; 2498 2499 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2500 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2501 2502 free(cmd, M_DEVBUF); 2503 if (crp->crp_etype != EAGAIN) 2504 crypto_done(crp); 2505 } 2506 2507 if (++i == HIFN_D_RES_RSIZE) 2508 i = 0; 2509 u--; 2510 } 2511 dma->resk = i; dma->resu = u; 2512 2513 /* Force upload of key next time */ 2514 for (i = 0; i < sc->sc_maxses; i++) 2515 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2516 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2517 2518 hifn_reset_board(sc, 1); 2519 hifn_init_dma(sc); 2520 hifn_init_pci_registers(sc); 2521} 2522 2523static void 2524hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2525{ 2526 struct hifn_dma *dma = sc->sc_dma; 2527 struct cryptop *crp = cmd->crp; 2528 struct cryptodesc *crd; 2529 struct mbuf *m; 2530 int totlen, i, u; 2531 2532 if (cmd->src_map == cmd->dst_map) { 2533 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2534 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2535 } else { 2536 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2537 BUS_DMASYNC_POSTWRITE); 2538 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2539 BUS_DMASYNC_POSTREAD); 2540 } 2541 2542 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2543 if (cmd->src_m != cmd->dst_m) { 2544 crp->crp_buf = (caddr_t)cmd->dst_m; 2545 totlen = cmd->src_mapsize; 2546 for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2547 if (totlen < m->m_len) { 2548 m->m_len = totlen; 2549 totlen = 0; 2550 } else 2551 totlen -= m->m_len; 2552 } 2553 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2554 m_freem(cmd->src_m); 2555 } 2556 } 2557 2558 if (cmd->sloplen != 0) { 2559 if (crp->crp_flags & CRYPTO_F_IMBUF) 2560 m_copyback((struct mbuf *)crp->crp_buf, 2561 cmd->src_mapsize - cmd->sloplen, 2562 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2563 else if (crp->crp_flags & CRYPTO_F_IOV) 2564 cuio_copyback((struct uio *)crp->crp_buf, 2565 cmd->src_mapsize - cmd->sloplen, 2566 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2567 } 2568 2569 i = dma->dstk; u = dma->dstu; 2570 while (u != 0) { 2571 if (i == HIFN_D_DST_RSIZE) 2572 i = 0; 2573 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2574 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2575 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2576 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2577 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2578 break; 2579 } 2580 i++, u--; 2581 } 2582 dma->dstk = i; dma->dstu = u; 2583 2584 hifnstats.hst_obytes += cmd->dst_mapsize; 2585 2586 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2587 HIFN_BASE_CMD_CRYPT) { 2588 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2589 if (crd->crd_alg != CRYPTO_DES_CBC && 2590 crd->crd_alg != CRYPTO_3DES_CBC) 2591 continue; 2592 if (crp->crp_flags & CRYPTO_F_IMBUF) 2593 m_copydata((struct mbuf *)crp->crp_buf, 2594 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2595 HIFN_IV_LENGTH, 2596 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2597 else if (crp->crp_flags & CRYPTO_F_IOV) { 2598 cuio_copydata((struct uio *)crp->crp_buf, 2599 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2600 HIFN_IV_LENGTH, 2601 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2602 } 2603 break; 2604 } 2605 } 2606 2607 if (macbuf != NULL) { 2608 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2609 int len; 2610 2611 if (crd->crd_alg == CRYPTO_MD5) 2612 len = 16; 2613 else if (crd->crd_alg == CRYPTO_SHA1) 2614 len = 20; 2615 else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2616 crd->crd_alg == CRYPTO_SHA1_HMAC) 2617 len = 12; 2618 else 2619 continue; 2620 2621 if (crp->crp_flags & CRYPTO_F_IMBUF) 2622 m_copyback((struct mbuf *)crp->crp_buf, 2623 crd->crd_inject, len, macbuf); 2624 else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2625 bcopy((caddr_t)macbuf, crp->crp_mac, len); 2626 break; 2627 } 2628 } 2629 2630 if (cmd->src_map != cmd->dst_map) { 2631 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2632 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2633 } 2634 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2635 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2636 free(cmd, M_DEVBUF); 2637 crypto_done(crp); 2638} 2639 2640/* 2641 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2642 * and Group 1 registers; avoid conditions that could create 2643 * burst writes by doing a read in between the writes. 2644 * 2645 * NB: The read we interpose is always to the same register; 2646 * we do this because reading from an arbitrary (e.g. last) 2647 * register may not always work. 2648 */ 2649static void 2650hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2651{ 2652 if (sc->sc_flags & HIFN_IS_7811) { 2653 if (sc->sc_bar0_lastreg == reg - 4) 2654 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2655 sc->sc_bar0_lastreg = reg; 2656 } 2657 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2658} 2659 2660static void 2661hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2662{ 2663 if (sc->sc_flags & HIFN_IS_7811) { 2664 if (sc->sc_bar1_lastreg == reg - 4) 2665 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2666 sc->sc_bar1_lastreg = reg; 2667 } 2668 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2669} 2670