1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp 28 * 29 * $FreeBSD$ 30 */ 31 32#ifndef _IF_GEMREG_H 33#define _IF_GEMREG_H 34 35/* register definitions for Apple GMAC, Sun ERI and Sun GEM */ 36 37/* 38 * First bank: these registers live at the start of the PCI 39 * mapping, and at the start of the second bank of the SBus 40 * version. 41 */ 42#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 43#define GEM_CONFIG 0x0004 /* config reg */ 44#define GEM_STATUS 0x000c /* status reg */ 45/* Note: Reading the status reg clears bits 0-6. */ 46#define GEM_INTMASK 0x0010 47#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 48#define GEM_STATUS_ALIAS 0x001c 49 50/* Bits in GEM_SEB register */ 51#define GEM_SEB_ARB 0x00000002 /* Arbitration status */ 52#define GEM_SEB_RXWON 0x00000004 53 54/* Bits in GEM_CONFIG register */ 55#define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */ 56#define GEM_CONFIG_BURST_INF 0x00000001 /* infinite for entire packet */ 57#define GEM_CONFIG_TXDMA_LIMIT 0x0000003e 58#define GEM_CONFIG_RXDMA_LIMIT 0x000007c0 59/* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 60#define GEM_CONFIG_RONPAULBIT 0x00000800 /* after infinite burst use */ 61 /* memory read multiple for */ 62 /* PCI commands */ 63#define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */ 64 65#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 66#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 67 68/* Top part of GEM_STATUS has TX completion information */ 69#define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */ 70#define GEM_STATUS_TX_COMPLETION_SHFT 19 71 72/* 73 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs 74 * Bits 0-6 auto-clear when read. 75 */ 76#define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */ 77#define GEM_INTR_TX_EMPTY 0x00000002 /* TX ring empty */ 78#define GEM_INTR_TX_DONE 0x00000004 /* TX complete */ 79#define GEM_INTR_RX_DONE 0x00000010 /* Got a packet */ 80#define GEM_INTR_RX_NOBUF 0x00000020 81#define GEM_INTR_RX_TAG_ERR 0x00000040 82#define GEM_INTR_PERR 0x00000080 /* Parity error */ 83#define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */ 84#define GEM_INTR_TX_MAC 0x00004000 85#define GEM_INTR_RX_MAC 0x00008000 86#define GEM_INTR_MAC_CONTROL 0x00010000 /* MAC control interrupt */ 87#define GEM_INTR_MIF 0x00020000 88#define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */ 89#define GEM_INTR_BITS "\177\020" \ 90 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 91 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 92 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 93 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 94 95/* 96 * Second bank: these registers live at offset 0x1000 of the PCI 97 * mapping, and at the start of the first bank of the SBus 98 * version. 99 */ 100#define GEM_PCI_BANK2_OFFSET 0x1000 101#define GEM_PCI_BANK2_SIZE 0x14 102/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 103#define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */ 104#define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */ 105#define GEM_PCI_BIF_CONFIG 0x0008 /* PCI BIF configuration */ 106#define GEM_PCI_BIF_DIAG 0x000c /* PCI BIF diagnostic */ 107 108#define GEM_SBUS_BIF_RESET 0x0000 /* SBus BIF only software reset */ 109#define GEM_SBUS_CONFIG 0x0004 /* SBus IO configuration */ 110#define GEM_SBUS_STATUS 0x0008 /* SBus IO status */ 111#define GEM_SBUS_REVISION 0x000c /* SBus revision ID */ 112 113#define GEM_RESET 0x0010 /* software reset */ 114 115/* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */ 116#define GEM_PCI_ERR_STAT_BADACK 0x00000001 /* No ACK64# */ 117#define GEM_PCI_ERR_STAT_DTRTO 0x00000002 /* Delayed xaction timeout */ 118#define GEM_PCI_ERR_STAT_OTHERS 0x00000004 119#define GEM_PCI_ERR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 120 121/* GEM_PCI_BIF_CONFIG register bits */ 122#define GEM_PCI_BIF_CNF_SLOWCLK 0x00000001 /* Parity error timing */ 123#define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */ 124#define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */ 125#define GEM_PCI_BIF_CNF_M66EN 0x00000008 126#define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 127 "b\2B64DIS\0b\3M66EN\0\0" 128 129/* GEM_PCI_BIF_DIAG register bits */ 130#define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */ 131#define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */ 132 133/* Bits in GEM_SBUS_CONFIG register */ 134#define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */ 135#define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */ 136#define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */ 137#define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */ 138#define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */ 139 140/* GEM_SBUS_STATUS register bits */ 141#define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */ 142#define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */ 143#define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */ 144#define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */ 145 146/* GEM_RESET register bits -- TX and RX self clear when complete. */ 147#define GEM_RESET_TX 0x00000001 /* Reset TX half. */ 148#define GEM_RESET_RX 0x00000002 /* Reset RX half. */ 149#define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ 150#define GEM_RESET_CLSZ_MASK 0x00ff0000 /* ERI cache line size */ 151#define GEM_RESET_CLSZ_SHFT 16 152 153/* The rest of the registers live in the first bank again. */ 154 155/* TX DMA registers */ 156#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 157#define GEM_TX_CONFIG 0x2004 158#define GEM_TX_RING_PTR_LO 0x2008 159#define GEM_TX_RING_PTR_HI 0x200c 160 161#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 162#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 163#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 164#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 165#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 166 167#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 168#define GEM_TX_DATA_PTR_LO 0x2030 169#define GEM_TX_DATA_PTR_HI 0x2034 170 171#define GEM_TX_COMPLETION 0x2100 172#define GEM_TX_FIFO_ADDRESS 0x2104 173#define GEM_TX_FIFO_TAG 0x2108 174#define GEM_TX_FIFO_DATA_LO 0x210c 175#define GEM_TX_FIFO_DATA_HI_T1 0x2110 176#define GEM_TX_FIFO_DATA_HI_T0 0x2114 177#define GEM_TX_FIFO_SIZE 0x2118 178#define GEM_TX_DEBUG 0x3028 179 180/* GEM_TX_CONFIG register bits */ 181#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 182#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 183#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 184#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 185 186#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 187#define GEM_RING_SZ_64 (1<<1) 188#define GEM_RING_SZ_128 (2<<1) 189#define GEM_RING_SZ_256 (3<<1) 190#define GEM_RING_SZ_512 (4<<1) 191#define GEM_RING_SZ_1024 (5<<1) 192#define GEM_RING_SZ_2048 (6<<1) 193#define GEM_RING_SZ_4096 (7<<1) 194#define GEM_RING_SZ_8192 (8<<1) 195 196/* GEM_TX_COMPLETION register bits */ 197#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 198 199/* RX DMA registers */ 200#define GEM_RX_CONFIG 0x4000 201#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 202#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 203 204#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 205#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 206#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 207#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 208 209#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 210#define GEM_RX_PAUSE_THRESH 0x4020 211 212#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 213#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 214 215#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 216#define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 217#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 218 219#define GEM_RX_FIFO_ADDRESS 0x410c 220#define GEM_RX_FIFO_TAG 0x4110 221#define GEM_RX_FIFO_DATA_LO 0x4114 222#define GEM_RX_FIFO_DATA_HI_T1 0x4118 223#define GEM_RX_FIFO_DATA_HI_T0 0x411c 224#define GEM_RX_FIFO_SIZE 0x4120 225 226/* GEM_RX_CONFIG register bits */ 227#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 228#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 229#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 230#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 231#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 232#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 233 234#define GEM_THRSH_64 0 235#define GEM_THRSH_128 1 236#define GEM_THRSH_256 2 237#define GEM_THRSH_512 3 238#define GEM_THRSH_1024 4 239#define GEM_THRSH_2048 5 240 241#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 242#define GEM_RX_CONFIG_FBOFF_SHFT 10 243#define GEM_RX_CONFIG_CXM_START_SHFT 13 244 245/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 246#define GEM_RX_PTH_XOFF_THRESH 0x000001ff 247#define GEM_RX_PTH_XON_THRESH 0x001ff000 248 249/* GEM_RX_BLANKING register bits */ 250#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 251#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 252#define GEM_RX_BLANKING_TIME_SHIFT 12 253/* One tick is 2048 PCI clocks, or 16us at 66MHz */ 254 255/* GEM_MAC registers */ 256#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 257#define GEM_MAC_RXRESET 0x6004 /* ditto */ 258#define GEM_MAC_SEND_PAUSE_CMD 0x6008 259#define GEM_MAC_TX_STATUS 0x6010 260#define GEM_MAC_RX_STATUS 0x6014 261#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 262#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 263#define GEM_MAC_RX_MASK 0x6024 264#define GEM_MAC_CONTROL_MASK 0x6028 265#define GEM_MAC_TX_CONFIG 0x6030 266#define GEM_MAC_RX_CONFIG 0x6034 267#define GEM_MAC_CONTROL_CONFIG 0x6038 268#define GEM_MAC_XIF_CONFIG 0x603c 269#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 270#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 271#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 272#define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 273#define GEM_MAC_MAC_MIN_FRAME 0x6050 274#define GEM_MAC_MAC_MAX_FRAME 0x6054 275#define GEM_MAC_PREAMBLE_LEN 0x6058 276#define GEM_MAC_JAM_SIZE 0x605c 277#define GEM_MAC_ATTEMPT_LIMIT 0x6060 278#define GEM_MAC_CONTROL_TYPE 0x6064 279 280#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 281#define GEM_MAC_ADDR1 0x6084 282#define GEM_MAC_ADDR2 0x6088 283#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 284#define GEM_MAC_ADDR4 0x6090 285#define GEM_MAC_ADDR5 0x6094 286#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 287#define GEM_MAC_ADDR7 0x609c 288#define GEM_MAC_ADDR8 0x60a0 289 290#define GEM_MAC_ADDR_FILTER0 0x60a4 291#define GEM_MAC_ADDR_FILTER1 0x60a8 292#define GEM_MAC_ADDR_FILTER2 0x60ac 293#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 294#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 295 296#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 297#define GEM_MAC_HASH1 0x60c4 298#define GEM_MAC_HASH2 0x60c8 299#define GEM_MAC_HASH3 0x60cc 300#define GEM_MAC_HASH4 0x60d0 301#define GEM_MAC_HASH5 0x60d4 302#define GEM_MAC_HASH6 0x60d8 303#define GEM_MAC_HASH7 0x60dc 304#define GEM_MAC_HASH8 0x60e0 305#define GEM_MAC_HASH9 0x60e4 306#define GEM_MAC_HASH10 0x60e8 307#define GEM_MAC_HASH11 0x60ec 308#define GEM_MAC_HASH12 0x60f0 309#define GEM_MAC_HASH13 0x60f4 310#define GEM_MAC_HASH14 0x60f8 311#define GEM_MAC_HASH15 0x60fc 312 313#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 314#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 315#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 316#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 317#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 318#define GEM_MAC_PEAK_ATTEMPTS 0x6114 319#define GEM_MAC_RX_FRAME_COUNT 0x6118 320#define GEM_MAC_RX_LEN_ERR_CNT 0x611c 321#define GEM_MAC_RX_ALIGN_ERR 0x6120 322#define GEM_MAC_RX_CRC_ERR_CNT 0x6124 323#define GEM_MAC_RX_CODE_VIOL 0x6128 324#define GEM_MAC_RANDOM_SEED 0x6130 325#define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */ 326 327/* GEM_MAC_SEND_PAUSE_CMD register bits */ 328#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 329#define GEM_MAC_PAUSE_CMD_SEND 0x00010000 330 331/* GEM_MAC_TX_STATUS and _MASK register bits */ 332#define GEM_MAC_TX_XMIT_DONE 0x00000001 333#define GEM_MAC_TX_UNDERRUN 0x00000002 334#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 335#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 336#define GEM_MAC_TX_ECC_EXP 0x00000010 337#define GEM_MAC_TX_LCC_EXP 0x00000020 338#define GEM_MAC_TX_FCC_EXP 0x00000040 339#define GEM_MAC_TX_DEFER_EXP 0x00000080 340#define GEM_MAC_TX_PEAK_EXP 0x00000100 341 342/* GEM_MAC_RX_STATUS and _MASK register bits */ 343#define GEM_MAC_RX_DONE 0x00000001 344#define GEM_MAC_RX_OVERFLOW 0x00000002 345#define GEM_MAC_RX_FRAME_CNT 0x00000004 346#define GEM_MAC_RX_ALIGN_EXP 0x00000008 347#define GEM_MAC_RX_CRC_EXP 0x00000010 348#define GEM_MAC_RX_LEN_EXP 0x00000020 349#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 350 351/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 352#define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 353#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 354#define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 355#define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */ 356#define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 357 358#define GEM_MAC_PAUSE_TIME_SHFT 16 359#define GEM_MAC_PAUSE_TIME(x) \ 360 (((x) & GEM_MAC_PAUSE_TIME_SLTS) >> GEM_MAC_PAUSE_TIME_SHFT) 361 362/* GEM_MAC_XIF_CONFIG register bits */ 363#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 364#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 365#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 366#define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 367#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 368#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 369#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 370#define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 371 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 372 "b\6FDLED\0\0" 373 374/* 375 * GEM_MAC_SLOT_TIME register 376 * The slot time is used as PAUSE time unit, value depends on whether carrier 377 * extension is enabled. 378 */ 379#define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 380#define GEM_MAC_SLOT_TIME_NORMAL 0x40 381 382/* GEM_MAC_TX_CONFIG register bits */ 383#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 384#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 385#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 386#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ 387#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 388#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 389#define GEM_MAC_TX_NO_BACKOFF 0x00000040 390#define GEM_MAC_TX_SLOWDOWN 0x00000080 391#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 392#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 393/* Carrier Extension is required for half duplex Gbps operation. */ 394#define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 395 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 396 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 397 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 398 "b\x9TXCARREXT\0\0" 399 400/* GEM_MAC_RX_CONFIG register bits */ 401#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 402#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 403#define GEM_MAC_RX_STRIP_CRC 0x00000004 404#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 405#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 406#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 407#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 408#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 409#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 410/* 411 * Carrier Extension enables reception of packet bursts generated by 412 * senders with carrier extension enabled. 413 */ 414#define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 415 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 416 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 417 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 418 419/* GEM_MAC_CONTROL_CONFIG bits */ 420#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 421#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 422#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 423#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 424 425/* 426 * MIF registers 427 * Bit bang registers use low bit only. 428 */ 429#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 430#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 431#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 432#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 433#define GEM_MIF_CONFIG 0x6210 434#define GEM_MIF_MASK 0x6214 435#define GEM_MIF_STATUS 0x6218 436#define GEM_MIF_STATE_MACHINE 0x621c 437 438/* GEM_MIF_FRAME bits */ 439#define GEM_MIF_FRAME_DATA 0x0000ffff 440#define GEM_MIF_FRAME_TA0 0x00010000 /* TA LSB, 1 for completion */ 441#define GEM_MIF_FRAME_TA1 0x00020000 /* TA MSB, 1 for instruction */ 442#define GEM_MIF_FRAME_REG_ADDR 0x007c0000 443#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address */ 444#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 445#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 446 447#define GEM_MIF_FRAME_READ 0x60020000 448#define GEM_MIF_FRAME_WRITE 0x50020000 449 450#define GEM_MIF_REG_SHIFT 18 451#define GEM_MIF_PHY_SHIFT 23 452 453/* GEM_MIF_CONFIG register bits */ 454#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0: MDIO_0 */ 455#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 456#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 457#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 458#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 attached/data */ 459#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 attached/data */ 460#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 461/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ 462#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 463 "b\x8MDIO0\0b\x9MDIO1\0\0" 464 465/* GEM_MIF_STATUS and GEM_MIF_MASK bits */ 466#define GEM_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */ 467#define GEM_MIF_POLL_STATUS_SHFT 0 468#define GEM_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */ 469#define GEM_MIF_POLL_DATA_SHFT 8 470/* 471 * The Basic part is the last value read in the POLL field of the config 472 * register. 473 * The status part indicates the bits that have changed. 474 */ 475 476/* GEM PCS/Serial link registers */ 477/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 478#define GEM_MII_CONTROL 0x9000 479#define GEM_MII_STATUS 0x9004 480#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 481#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 482#define GEM_MII_CONFIG 0x9010 483#define GEM_MII_STATE_MACHINE 0x9014 484#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 485#define GEM_MII_DATAPATH_MODE 0x9050 486#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 487#define GEM_MII_OUTPUT_SELECT 0x9058 488#define GEM_MII_SLINK_STATUS 0x905c /* Serialink status */ 489 490/* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */ 491#define GEM_MII_CONTROL_1000M 0x00000040 /* 1000Mbps speed select */ 492#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 493#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */ 494#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */ 495#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY from MII */ 496#define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down */ 497#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */ 498#define GEM_MII_CONTROL_10_100M 0x00002000 /* 10/100Mbps speed select */ 499#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 500#define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS. */ 501#define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 502 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 503 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 504 505/* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 506#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability */ 507#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 508#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 509#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */ 510#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 511#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */ 512#define GEM_MII_STATUS_EXTENDED 0x00000100 /* extended status */ 513#define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 514 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0\0" 515 516/* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 517#define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */ 518#define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */ 519#define GEM_MII_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */ 520#define GEM_MII_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */ 521#define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */ 522#define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */ 523#define GEM_MII_ANEG_RFLT_MASK \ 524(CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF) 525#define GEM_MII_ANEG_ACK 0x00004000 /* acknowledge */ 526#define GEM_MII_ANEG_NP 0x00008000 /* next page */ 527#define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 528 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 529 "\b\xfNPBIT\0\0" 530 531/* GEM_MII_CONFIG reg */ 532#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS. */ 533#define GEM_MII_CONFIG_SDO 0x00000002 /* signal detect override */ 534#define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */ 535#define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */ 536#define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */ 537#define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */ 538#define GEM_MII_CONFIG_JS_MASK \ 539 (GEM_MII_CONFIG_JS_HF | GEM_MII_CONFIG_JS_LF) 540#define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */ 541#define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 542 543/* 544 * GEM_MII_INTERRUP_STATUS reg 545 * No mask register; mask with the global interrupt mask register. 546 */ 547#define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 548 549/* GEM_MII_DATAPATH_MODE reg */ 550#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serialink */ 551#define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */ 552#define GEM_MII_DATAPATH_MII 0x00000004 /* GMII/MII */ 553#define GEM_MII_DATAPATH_GMIIOE 0x00000008 /* serial output on GMII en. */ 554#define GEM_MII_DATAPATH_BITS "\177\020" \ 555 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3GMIIOE\0\0" 556 557/* GEM_MII_SLINK_CONTROL reg */ 558#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at SL, logic 559 * reversed for SERDES */ 560#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 561#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock to reference clock */ 562#define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */ 563#define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */ 564#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink. */ 565#define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink. */ 566#define GEM_MII_SLINK_RX_POLE 0x00003000 /* PLL input to Serialink. */ 567#define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink. */ 568#define GEM_MII_SLINK_TX_POLE 0x00030000 /* PLL input to Serialink. */ 569#define GEM_MII_SLINK_CONTROL_BITS \ 570 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 571 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" 572 573/* GEM_MII_SLINK_STATUS reg */ 574#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 575#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us w/ lockrefn */ 576#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 577#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 578 579/* 580 * PCI Expansion ROM runtime access 581 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 582 * of the first register bank, although they only support up to 64KB ROMs. 583 */ 584#define GEM_PCI_ROM_OFFSET 0x100000 585#define GEM_PCI_ROM_SIZE 0x10000 586 587/* Wired PHY addresses */ 588#define GEM_PHYAD_INTERNAL 1 589#define GEM_PHYAD_EXTERNAL 0 590 591/* Miscellaneous */ 592#define GEM_ERI_CACHE_LINE_SIZE 16 593#define GEM_ERI_LATENCY_TIMER 64 594 595/* 596 * descriptor table structures 597 */ 598struct gem_desc { 599 uint64_t gd_flags; 600 uint64_t gd_addr; 601}; 602 603/* 604 * Transmit flags 605 * GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_START, GEM_TD_CXSUM_STUFF and 606 * GEM_TD_INTERRUPT_ME only need to be set in the first descriptor of a group. 607 */ 608#define GEM_TD_BUFSIZE 0x0000000000007fffULL 609#define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */ 610#define GEM_TD_CXSUM_STARTSHFT 15 611#define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */ 612#define GEM_TD_CXSUM_STUFFSHFT 21 613#define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */ 614#define GEM_TD_END_OF_PACKET 0x0000000040000000ULL 615#define GEM_TD_START_OF_PACKET 0x0000000080000000ULL 616#define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */ 617#define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */ 618 619/* Receive flags */ 620#define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */ 621#define GEM_RD_BUFSIZE 0x000000007fff0000ULL 622#define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */ 623#define GEM_RD_HASHVAL 0x0ffff00000000000ULL 624#define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 625#define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */ 626#define GEM_RD_BAD_CRC 0x4000000000000000ULL 627#define GEM_RD_BUFSHIFT 16 628#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 629 630#endif 631