if_fxp.c revision 90168
150479Speter/*- 22536Spst * Copyright (c) 1995, David Greenman 3265420Simp * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4156813Sru * All rights reserved. 5116015Smarkm * 6156813Sru * Redistribution and use in source and binary forms, with or without 7116015Smarkm * modification, are permitted provided that the following conditions 8156813Sru * are met: 999430Sdes * 1. Redistributions of source code must retain the above copyright 1057437Smarkm * notice unmodified, this list of conditions, and the following 1157841Skris * disclaimer. 122536Spst * 2. Redistributions in binary form must reproduce the above copyright 13264741Sjmmv * notice, this list of conditions and the following disclaimer in the 14264741Sjmmv * documentation and/or other materials provided with the distribution. 15264741Sjmmv * 16264741Sjmmv * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 172536Spst * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 90168 2002-02-04 03:15:27Z silby $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/sysctl.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <net/ethernet.h> 61#include <net/if_arp.h> 62 63#include <vm/vm.h> /* for vtophys */ 64#include <vm/pmap.h> /* for vtophys */ 65#include <machine/clock.h> /* for DELAY */ 66 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73#include <dev/mii/mii.h> 74#include <dev/mii/miivar.h> 75 76#include <dev/fxp/if_fxpreg.h> 77#include <dev/fxp/if_fxpvar.h> 78#include <dev/fxp/rcvbundl.h> 79 80MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81#include "miibus_if.h" 82 83/* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92#define RFA_ALIGNMENT_FUDGE 2 93 94/* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99static int tx_threshold = 64; 100 101/* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135}; 136 137struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140}; 141 142/* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0, NULL }, 163}; 164 165static int fxp_probe(device_t dev); 166static int fxp_attach(device_t dev); 167static int fxp_detach(device_t dev); 168static int fxp_shutdown(device_t dev); 169static int fxp_suspend(device_t dev); 170static int fxp_resume(device_t dev); 171 172static void fxp_intr(void *xsc); 173static void fxp_init(void *xsc); 174static void fxp_tick(void *xsc); 175static void fxp_powerstate_d0(device_t dev); 176static void fxp_start(struct ifnet *ifp); 177static void fxp_stop(struct fxp_softc *sc); 178static void fxp_release(struct fxp_softc *sc); 179static int fxp_ioctl(struct ifnet *ifp, u_long command, 180 caddr_t data); 181static void fxp_watchdog(struct ifnet *ifp); 182static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 183static int fxp_mc_addrs(struct fxp_softc *sc); 184static void fxp_mc_setup(struct fxp_softc *sc); 185static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 186 int autosize); 187static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 188 u_int16_t data); 189static void fxp_autosize_eeprom(struct fxp_softc *sc); 190static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 191 int offset, int words); 192static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 193 int offset, int words); 194static int fxp_ifmedia_upd(struct ifnet *ifp); 195static void fxp_ifmedia_sts(struct ifnet *ifp, 196 struct ifmediareq *ifmr); 197static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 198static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 199 struct ifmediareq *ifmr); 200static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 201static void fxp_miibus_writereg(device_t dev, int phy, int reg, 202 int value); 203static void fxp_load_ucode(struct fxp_softc *sc); 204static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 205 int low, int high); 206static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 207static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 208static __inline void fxp_lwcopy(volatile u_int32_t *src, 209 volatile u_int32_t *dst); 210static __inline void fxp_scb_wait(struct fxp_softc *sc); 211static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 212static __inline void fxp_dma_wait(volatile u_int16_t *status, 213 struct fxp_softc *sc); 214 215static device_method_t fxp_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_probe, fxp_probe), 218 DEVMETHOD(device_attach, fxp_attach), 219 DEVMETHOD(device_detach, fxp_detach), 220 DEVMETHOD(device_shutdown, fxp_shutdown), 221 DEVMETHOD(device_suspend, fxp_suspend), 222 DEVMETHOD(device_resume, fxp_resume), 223 224 /* MII interface */ 225 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 226 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 227 228 { 0, 0 } 229}; 230 231static driver_t fxp_driver = { 232 "fxp", 233 fxp_methods, 234 sizeof(struct fxp_softc), 235}; 236 237static devclass_t fxp_devclass; 238 239DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 240DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 241DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 242 243/* 244 * Inline function to copy a 16-bit aligned 32-bit quantity. 245 */ 246static __inline void 247fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 248{ 249#ifdef __i386__ 250 *dst = *src; 251#else 252 volatile u_int16_t *a = (volatile u_int16_t *)src; 253 volatile u_int16_t *b = (volatile u_int16_t *)dst; 254 255 b[0] = a[0]; 256 b[1] = a[1]; 257#endif 258} 259 260/* 261 * Wait for the previous command to be accepted (but not necessarily 262 * completed). 263 */ 264static __inline void 265fxp_scb_wait(struct fxp_softc *sc) 266{ 267 int i = 10000; 268 269 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 270 DELAY(2); 271 if (i == 0) 272 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 273 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 274 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 275 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 276 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 277} 278 279static __inline void 280fxp_scb_cmd(struct fxp_softc *sc, int cmd) 281{ 282 283 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 284 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 285 fxp_scb_wait(sc); 286 } 287 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 288} 289 290static __inline void 291fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 292{ 293 int i = 10000; 294 295 while (!(*status & FXP_CB_STATUS_C) && --i) 296 DELAY(2); 297 if (i == 0) 298 device_printf(sc->dev, "DMA timeout\n"); 299} 300 301/* 302 * Return identification string if this is device is ours. 303 */ 304static int 305fxp_probe(device_t dev) 306{ 307 u_int16_t devid; 308 struct fxp_ident *ident; 309 310 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 311 devid = pci_get_device(dev); 312 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 313 if (ident->devid == devid) { 314 device_set_desc(dev, ident->name); 315 return (0); 316 } 317 } 318 } 319 return (ENXIO); 320} 321 322static void 323fxp_powerstate_d0(device_t dev) 324{ 325#if __FreeBSD_version >= 430002 326 u_int32_t iobase, membase, irq; 327 328 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 329 /* Save important PCI config data. */ 330 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 331 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 332 irq = pci_read_config(dev, PCIR_INTLINE, 4); 333 334 /* Reset the power state. */ 335 device_printf(dev, "chip is in D%d power mode " 336 "-- setting to D0\n", pci_get_powerstate(dev)); 337 338 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 339 340 /* Restore PCI config data. */ 341 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 342 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 343 pci_write_config(dev, PCIR_INTLINE, irq, 4); 344 } 345#endif 346} 347 348static int 349fxp_attach(device_t dev) 350{ 351 int error = 0; 352 struct fxp_softc *sc = device_get_softc(dev); 353 struct ifnet *ifp; 354 u_int32_t val; 355 u_int16_t data; 356 int i, rid, m1, m2, prefer_iomap; 357 int s; 358 359 bzero(sc, sizeof(*sc)); 360 sc->dev = dev; 361 callout_handle_init(&sc->stat_ch); 362 sysctl_ctx_init(&sc->sysctl_ctx); 363 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 364 365 s = splimp(); 366 367 /* 368 * Enable bus mastering. Enable memory space too, in case 369 * BIOS/Prom forgot about it. 370 */ 371 val = pci_read_config(dev, PCIR_COMMAND, 2); 372 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 373 pci_write_config(dev, PCIR_COMMAND, val, 2); 374 val = pci_read_config(dev, PCIR_COMMAND, 2); 375 376 fxp_powerstate_d0(dev); 377 378 /* 379 * Figure out which we should try first - memory mapping or i/o mapping? 380 * We default to memory mapping. Then we accept an override from the 381 * command line. Then we check to see which one is enabled. 382 */ 383 m1 = PCIM_CMD_MEMEN; 384 m2 = PCIM_CMD_PORTEN; 385 prefer_iomap = 0; 386 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 387 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 388 m1 = PCIM_CMD_PORTEN; 389 m2 = PCIM_CMD_MEMEN; 390 } 391 392 if (val & m1) { 393 sc->rtp = 394 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 395 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 396 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 397 0, ~0, 1, RF_ACTIVE); 398 } 399 if (sc->mem == NULL && (val & m2)) { 400 sc->rtp = 401 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 402 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 403 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 404 0, ~0, 1, RF_ACTIVE); 405 } 406 407 if (!sc->mem) { 408 device_printf(dev, "could not map device registers\n"); 409 error = ENXIO; 410 goto fail; 411 } 412 if (bootverbose) { 413 device_printf(dev, "using %s space register mapping\n", 414 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 415 } 416 417 sc->sc_st = rman_get_bustag(sc->mem); 418 sc->sc_sh = rman_get_bushandle(sc->mem); 419 420 /* 421 * Allocate our interrupt. 422 */ 423 rid = 0; 424 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 425 RF_SHAREABLE | RF_ACTIVE); 426 if (sc->irq == NULL) { 427 device_printf(dev, "could not map interrupt\n"); 428 error = ENXIO; 429 goto fail; 430 } 431 432 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 433 fxp_intr, sc, &sc->ih); 434 if (error) { 435 device_printf(dev, "could not setup irq\n"); 436 goto fail; 437 } 438 439 /* 440 * Reset to a stable state. 441 */ 442 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 443 DELAY(10); 444 445 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 446 M_DEVBUF, M_NOWAIT | M_ZERO); 447 if (sc->cbl_base == NULL) 448 goto failmem; 449 450 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 451 M_NOWAIT | M_ZERO); 452 if (sc->fxp_stats == NULL) 453 goto failmem; 454 455 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 456 if (sc->mcsp == NULL) 457 goto failmem; 458 459 /* 460 * Pre-allocate our receive buffers. 461 */ 462 for (i = 0; i < FXP_NRFABUFS; i++) { 463 if (fxp_add_rfabuf(sc, NULL) != 0) { 464 goto failmem; 465 } 466 } 467 468 /* 469 * Find out how large of an SEEPROM we have. 470 */ 471 fxp_autosize_eeprom(sc); 472 473 /* 474 * Determine whether we must use the 503 serial interface. 475 */ 476 fxp_read_eeprom(sc, &data, 6, 1); 477 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 478 (data & FXP_PHY_SERIAL_ONLY)) 479 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 480 481 /* 482 * Create the sysctl tree 483 */ 484 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 485 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 486 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 487 if (sc->sysctl_tree == NULL) 488 goto fail; 489 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 490 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 491 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 492 "FXP driver receive interrupt microcode bundling delay"); 493 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 494 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 495 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 496 "FXP driver receive interrupt microcode bundle size limit"); 497 498 /* 499 * Pull in device tunables. 500 */ 501 sc->tunable_int_delay = TUNABLE_INT_DELAY; 502 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 503 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 504 "int_delay", &sc->tunable_int_delay); 505 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 506 "bundle_max", &sc->tunable_bundle_max); 507 508 /* 509 * Find out the chip revision; lump all 82557 revs together. 510 */ 511 fxp_read_eeprom(sc, &data, 5, 1); 512 if ((data >> 8) == 1) 513 sc->revision = FXP_REV_82557; 514 else 515 sc->revision = pci_get_revid(dev); 516 517 /* 518 * Enable workarounds for certain chip revision deficiencies. 519 * 520 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 521 * some systems based a normal 82559 design, have a defect where 522 * the chip can cause a PCI protocol violation if it receives 523 * a CU_RESUME command when it is entering the IDLE state. The 524 * workaround is to disable Dynamic Standby Mode, so the chip never 525 * deasserts CLKRUN#, and always remains in an active state. 526 * 527 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 528 */ 529 i = pci_get_device(dev); 530 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 531 sc->revision >= FXP_REV_82559_A0) { 532 fxp_read_eeprom(sc, &data, 10, 1); 533 if (data & 0x02) { /* STB enable */ 534 u_int16_t cksum; 535 int i; 536 537 device_printf(dev, 538 "Disabling dynamic standby mode in EEPROM\n"); 539 data &= ~0x02; 540 fxp_write_eeprom(sc, &data, 10, 1); 541 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 542 cksum = 0; 543 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 544 fxp_read_eeprom(sc, &data, i, 1); 545 cksum += data; 546 } 547 i = (1 << sc->eeprom_size) - 1; 548 cksum = 0xBABA - cksum; 549 fxp_read_eeprom(sc, &data, i, 1); 550 fxp_write_eeprom(sc, &cksum, i, 1); 551 device_printf(dev, 552 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 553 i, data, cksum); 554#if 1 555 /* 556 * If the user elects to continue, try the software 557 * workaround, as it is better than nothing. 558 */ 559 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 560#endif 561 } 562 } 563 564 /* 565 * If we are not a 82557 chip, we can enable extended features. 566 */ 567 if (sc->revision != FXP_REV_82557) { 568 /* 569 * If MWI is enabled in the PCI configuration, and there 570 * is a valid cacheline size (8 or 16 dwords), then tell 571 * the board to turn on MWI. 572 */ 573 if (val & PCIM_CMD_MWRICEN && 574 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 575 sc->flags |= FXP_FLAG_MWI_ENABLE; 576 577 /* turn on the extended TxCB feature */ 578 sc->flags |= FXP_FLAG_EXT_TXCB; 579 580 /* enable reception of long frames for VLAN */ 581 sc->flags |= FXP_FLAG_LONG_PKT_EN; 582 } 583 584 /* 585 * Read MAC address. 586 */ 587 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 588 device_printf(dev, "Ethernet address %6D%s\n", 589 sc->arpcom.ac_enaddr, ":", 590 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 591 if (bootverbose) { 592 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 593 pci_get_vendor(dev), pci_get_device(dev), 594 pci_get_subvendor(dev), pci_get_subdevice(dev), 595 pci_get_revid(dev)); 596 fxp_read_eeprom(sc, &data, 10, 1); 597 device_printf(dev, "Dynamic Standby mode is %s\n", 598 data & 0x02 ? "enabled" : "disabled"); 599 } 600 601 /* 602 * If this is only a 10Mbps device, then there is no MII, and 603 * the PHY will use a serial interface instead. 604 * 605 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 606 * doesn't have a programming interface of any sort. The 607 * media is sensed automatically based on how the link partner 608 * is configured. This is, in essence, manual configuration. 609 */ 610 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 611 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 612 fxp_serial_ifmedia_sts); 613 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 614 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 615 } else { 616 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 617 fxp_ifmedia_sts)) { 618 device_printf(dev, "MII without any PHY!\n"); 619 error = ENXIO; 620 goto fail; 621 } 622 } 623 624 ifp = &sc->arpcom.ac_if; 625 ifp->if_unit = device_get_unit(dev); 626 ifp->if_name = "fxp"; 627 ifp->if_output = ether_output; 628 ifp->if_baudrate = 100000000; 629 ifp->if_init = fxp_init; 630 ifp->if_softc = sc; 631 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 632 ifp->if_ioctl = fxp_ioctl; 633 ifp->if_start = fxp_start; 634 ifp->if_watchdog = fxp_watchdog; 635 636 /* 637 * Attach the interface. 638 */ 639 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 640 641 /* 642 * Tell the upper layer(s) we support long frames. 643 */ 644 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 645 646 /* 647 * Let the system queue as many packets as we have available 648 * TX descriptors. 649 */ 650 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 651 652 splx(s); 653 return (0); 654 655failmem: 656 device_printf(dev, "Failed to malloc memory\n"); 657 error = ENOMEM; 658fail: 659 splx(s); 660 fxp_release(sc); 661 return (error); 662} 663 664/* 665 * release all resources 666 */ 667static void 668fxp_release(struct fxp_softc *sc) 669{ 670 671 bus_generic_detach(sc->dev); 672 if (sc->miibus) 673 device_delete_child(sc->dev, sc->miibus); 674 675 if (sc->cbl_base) 676 free(sc->cbl_base, M_DEVBUF); 677 if (sc->fxp_stats) 678 free(sc->fxp_stats, M_DEVBUF); 679 if (sc->mcsp) 680 free(sc->mcsp, M_DEVBUF); 681 if (sc->rfa_headm) 682 m_freem(sc->rfa_headm); 683 684 if (sc->ih) 685 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 686 if (sc->irq) 687 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 688 if (sc->mem) 689 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 690 691 sysctl_ctx_free(&sc->sysctl_ctx); 692 693 mtx_destroy(&sc->sc_mtx); 694} 695 696/* 697 * Detach interface. 698 */ 699static int 700fxp_detach(device_t dev) 701{ 702 struct fxp_softc *sc = device_get_softc(dev); 703 int s; 704 705 /* disable interrupts */ 706 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 707 708 s = splimp(); 709 710 /* 711 * Stop DMA and drop transmit queue. 712 */ 713 fxp_stop(sc); 714 715 /* 716 * Close down routes etc. 717 */ 718 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 719 720 /* 721 * Free all media structures. 722 */ 723 ifmedia_removeall(&sc->sc_media); 724 725 splx(s); 726 727 /* Release our allocated resources. */ 728 fxp_release(sc); 729 730 return (0); 731} 732 733/* 734 * Device shutdown routine. Called at system shutdown after sync. The 735 * main purpose of this routine is to shut off receiver DMA so that 736 * kernel memory doesn't get clobbered during warmboot. 737 */ 738static int 739fxp_shutdown(device_t dev) 740{ 741 /* 742 * Make sure that DMA is disabled prior to reboot. Not doing 743 * do could allow DMA to corrupt kernel memory during the 744 * reboot before the driver initializes. 745 */ 746 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 747 return (0); 748} 749 750/* 751 * Device suspend routine. Stop the interface and save some PCI 752 * settings in case the BIOS doesn't restore them properly on 753 * resume. 754 */ 755static int 756fxp_suspend(device_t dev) 757{ 758 struct fxp_softc *sc = device_get_softc(dev); 759 int i, s; 760 761 s = splimp(); 762 763 fxp_stop(sc); 764 765 for (i = 0; i < 5; i++) 766 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 767 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 768 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 769 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 770 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 771 772 sc->suspended = 1; 773 774 splx(s); 775 return (0); 776} 777 778/* 779 * Device resume routine. Restore some PCI settings in case the BIOS 780 * doesn't, re-enable busmastering, and restart the interface if 781 * appropriate. 782 */ 783static int 784fxp_resume(device_t dev) 785{ 786 struct fxp_softc *sc = device_get_softc(dev); 787 struct ifnet *ifp = &sc->sc_if; 788 u_int16_t pci_command; 789 int i, s; 790 791 s = splimp(); 792 793 fxp_powerstate_d0(dev); 794 795 /* better way to do this? */ 796 for (i = 0; i < 5; i++) 797 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 798 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 799 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 800 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 801 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 802 803 /* reenable busmastering */ 804 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 805 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 806 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 807 808 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 809 DELAY(10); 810 811 /* reinitialize interface if necessary */ 812 if (ifp->if_flags & IFF_UP) 813 fxp_init(sc); 814 815 sc->suspended = 0; 816 817 splx(s); 818 return (0); 819} 820 821static void 822fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 823{ 824 u_int16_t reg; 825 int x; 826 827 /* 828 * Shift in data. 829 */ 830 for (x = 1 << (length - 1); x; x >>= 1) { 831 if (data & x) 832 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 833 else 834 reg = FXP_EEPROM_EECS; 835 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 836 DELAY(1); 837 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 838 DELAY(1); 839 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 840 DELAY(1); 841 } 842} 843 844/* 845 * Read from the serial EEPROM. Basically, you manually shift in 846 * the read opcode (one bit at a time) and then shift in the address, 847 * and then you shift out the data (all of this one bit at a time). 848 * The word size is 16 bits, so you have to provide the address for 849 * every 16 bits of data. 850 */ 851static u_int16_t 852fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 853{ 854 u_int16_t reg, data; 855 int x; 856 857 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 858 /* 859 * Shift in read opcode. 860 */ 861 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 862 /* 863 * Shift in address. 864 */ 865 data = 0; 866 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 867 if (offset & x) 868 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 869 else 870 reg = FXP_EEPROM_EECS; 871 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 872 DELAY(1); 873 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 874 DELAY(1); 875 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 876 DELAY(1); 877 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 878 data++; 879 if (autosize && reg == 0) { 880 sc->eeprom_size = data; 881 break; 882 } 883 } 884 /* 885 * Shift out data. 886 */ 887 data = 0; 888 reg = FXP_EEPROM_EECS; 889 for (x = 1 << 15; x; x >>= 1) { 890 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 891 DELAY(1); 892 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 893 data |= x; 894 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 895 DELAY(1); 896 } 897 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 898 DELAY(1); 899 900 return (data); 901} 902 903static void 904fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 905{ 906 int i; 907 908 /* 909 * Erase/write enable. 910 */ 911 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 912 fxp_eeprom_shiftin(sc, 0x4, 3); 913 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 915 DELAY(1); 916 /* 917 * Shift in write opcode, address, data. 918 */ 919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 920 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 921 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 922 fxp_eeprom_shiftin(sc, data, 16); 923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 924 DELAY(1); 925 /* 926 * Wait for EEPROM to finish up. 927 */ 928 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 929 DELAY(1); 930 for (i = 0; i < 1000; i++) { 931 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 932 break; 933 DELAY(50); 934 } 935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 936 DELAY(1); 937 /* 938 * Erase/write disable. 939 */ 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 941 fxp_eeprom_shiftin(sc, 0x4, 3); 942 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 944 DELAY(1); 945} 946 947/* 948 * From NetBSD: 949 * 950 * Figure out EEPROM size. 951 * 952 * 559's can have either 64-word or 256-word EEPROMs, the 558 953 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 954 * talks about the existance of 16 to 256 word EEPROMs. 955 * 956 * The only known sizes are 64 and 256, where the 256 version is used 957 * by CardBus cards to store CIS information. 958 * 959 * The address is shifted in msb-to-lsb, and after the last 960 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 961 * after which follows the actual data. We try to detect this zero, by 962 * probing the data-out bit in the EEPROM control register just after 963 * having shifted in a bit. If the bit is zero, we assume we've 964 * shifted enough address bits. The data-out should be tri-state, 965 * before this, which should translate to a logical one. 966 */ 967static void 968fxp_autosize_eeprom(struct fxp_softc *sc) 969{ 970 971 /* guess maximum size of 256 words */ 972 sc->eeprom_size = 8; 973 974 /* autosize */ 975 (void) fxp_eeprom_getword(sc, 0, 1); 976} 977 978static void 979fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 980{ 981 int i; 982 983 for (i = 0; i < words; i++) 984 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 985} 986 987static void 988fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 989{ 990 int i; 991 992 for (i = 0; i < words; i++) 993 fxp_eeprom_putword(sc, offset + i, data[i]); 994} 995 996/* 997 * Start packet transmission on the interface. 998 */ 999static void 1000fxp_start(struct ifnet *ifp) 1001{ 1002 struct fxp_softc *sc = ifp->if_softc; 1003 struct fxp_cb_tx *txp; 1004 1005 /* 1006 * See if we need to suspend xmit until the multicast filter 1007 * has been reprogrammed (which can only be done at the head 1008 * of the command chain). 1009 */ 1010 if (sc->need_mcsetup) { 1011 return; 1012 } 1013 1014 txp = NULL; 1015 1016 /* 1017 * We're finished if there is nothing more to add to the list or if 1018 * we're all filled up with buffers to transmit. 1019 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1020 * a NOP command when needed. 1021 */ 1022 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1023 struct mbuf *m, *mb_head; 1024 int segment; 1025 1026 /* 1027 * Grab a packet to transmit. 1028 */ 1029 IF_DEQUEUE(&ifp->if_snd, mb_head); 1030 1031 /* 1032 * Get pointer to next available tx desc. 1033 */ 1034 txp = sc->cbl_last->next; 1035 1036 /* 1037 * Go through each of the mbufs in the chain and initialize 1038 * the transmit buffer descriptors with the physical address 1039 * and size of the mbuf. 1040 */ 1041tbdinit: 1042 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1043 if (m->m_len != 0) { 1044 if (segment == FXP_NTXSEG) 1045 break; 1046 txp->tbd[segment].tb_addr = 1047 vtophys(mtod(m, vm_offset_t)); 1048 txp->tbd[segment].tb_size = m->m_len; 1049 segment++; 1050 } 1051 } 1052 if (m != NULL) { 1053 struct mbuf *mn; 1054 1055 /* 1056 * We ran out of segments. We have to recopy this 1057 * mbuf chain first. Bail out if we can't get the 1058 * new buffers. 1059 */ 1060 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1061 if (mn == NULL) { 1062 m_freem(mb_head); 1063 break; 1064 } 1065 if (mb_head->m_pkthdr.len > MHLEN) { 1066 MCLGET(mn, M_DONTWAIT); 1067 if ((mn->m_flags & M_EXT) == 0) { 1068 m_freem(mn); 1069 m_freem(mb_head); 1070 break; 1071 } 1072 } 1073 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1074 mtod(mn, caddr_t)); 1075 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1076 m_freem(mb_head); 1077 mb_head = mn; 1078 goto tbdinit; 1079 } 1080 1081 txp->tbd_number = segment; 1082 txp->mb_head = mb_head; 1083 txp->cb_status = 0; 1084 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1085 txp->cb_command = 1086 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1087 FXP_CB_COMMAND_S; 1088 } else { 1089 txp->cb_command = 1090 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1091 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1092 /* 1093 * Set a 5 second timer just in case we don't hear 1094 * from the card again. 1095 */ 1096 ifp->if_timer = 5; 1097 } 1098 txp->tx_threshold = tx_threshold; 1099 1100 /* 1101 * Advance the end of list forward. 1102 */ 1103 1104#ifdef __alpha__ 1105 /* 1106 * On platforms which can't access memory in 16-bit 1107 * granularities, we must prevent the card from DMA'ing 1108 * up the status while we update the command field. 1109 * This could cause us to overwrite the completion status. 1110 */ 1111 atomic_clear_short(&sc->cbl_last->cb_command, 1112 FXP_CB_COMMAND_S); 1113#else 1114 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1115#endif /*__alpha__*/ 1116 sc->cbl_last = txp; 1117 1118 /* 1119 * Advance the beginning of the list forward if there are 1120 * no other packets queued (when nothing is queued, cbl_first 1121 * sits on the last TxCB that was sent out). 1122 */ 1123 if (sc->tx_queued == 0) 1124 sc->cbl_first = txp; 1125 1126 sc->tx_queued++; 1127 1128 /* 1129 * Pass packet to bpf if there is a listener. 1130 */ 1131 if (ifp->if_bpf) 1132 bpf_mtap(ifp, mb_head); 1133 } 1134 1135 /* 1136 * We're finished. If we added to the list, issue a RESUME to get DMA 1137 * going again if suspended. 1138 */ 1139 if (txp != NULL) { 1140 fxp_scb_wait(sc); 1141 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1142 } 1143} 1144 1145static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1146 1147#ifdef DEVICE_POLLING 1148static poll_handler_t fxp_poll; 1149 1150static void 1151fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1152{ 1153 struct fxp_softc *sc = ifp->if_softc; 1154 u_int8_t statack; 1155 1156 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1157 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1158 return; 1159 } 1160 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1161 FXP_SCB_STATACK_FR; 1162 if (cmd == POLL_AND_CHECK_STATUS) { 1163 u_int8_t tmp; 1164 1165 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1166 if (tmp == 0xff || tmp == 0) 1167 return; /* nothing to do */ 1168 tmp &= ~statack; 1169 /* ack what we can */ 1170 if (tmp != 0) 1171 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1172 statack |= tmp; 1173 } 1174 fxp_intr_body(sc, statack, count); 1175} 1176#endif /* DEVICE_POLLING */ 1177 1178/* 1179 * Process interface interrupts. 1180 */ 1181static void 1182fxp_intr(void *xsc) 1183{ 1184 struct fxp_softc *sc = xsc; 1185 u_int8_t statack; 1186 1187#ifdef DEVICE_POLLING 1188 struct ifnet *ifp = &sc->sc_if; 1189 1190 if (ifp->if_ipending & IFF_POLLING) 1191 return; 1192 if (ether_poll_register(fxp_poll, ifp)) { 1193 /* disable interrupts */ 1194 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1195 fxp_poll(ifp, 0, 1); 1196 return; 1197 } 1198#endif 1199 1200 if (sc->suspended) { 1201 return; 1202 } 1203 1204 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1205 /* 1206 * It should not be possible to have all bits set; the 1207 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1208 * all bits are set, this may indicate that the card has 1209 * been physically ejected, so ignore it. 1210 */ 1211 if (statack == 0xff) 1212 return; 1213 1214 /* 1215 * First ACK all the interrupts in this pass. 1216 */ 1217 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1218 fxp_intr_body(sc, statack, -1); 1219 } 1220} 1221 1222static void 1223fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1224{ 1225 struct ifnet *ifp = &sc->sc_if; 1226 1227 /* 1228 * Free any finished transmit mbuf chains. 1229 * 1230 * Handle the CNA event likt a CXTNO event. It used to 1231 * be that this event (control unit not ready) was not 1232 * encountered, but it is now with the SMPng modifications. 1233 * The exact sequence of events that occur when the interface 1234 * is brought up are different now, and if this event 1235 * goes unhandled, the configuration/rxfilter setup sequence 1236 * can stall for several seconds. The result is that no 1237 * packets go out onto the wire for about 5 to 10 seconds 1238 * after the interface is ifconfig'ed for the first time. 1239 */ 1240 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1241 struct fxp_cb_tx *txp; 1242 1243 for (txp = sc->cbl_first; sc->tx_queued && 1244 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1245 txp = txp->next) { 1246 if (txp->mb_head != NULL) { 1247 m_freem(txp->mb_head); 1248 txp->mb_head = NULL; 1249 } 1250 sc->tx_queued--; 1251 } 1252 sc->cbl_first = txp; 1253 ifp->if_timer = 0; 1254 if (sc->tx_queued == 0) { 1255 if (sc->need_mcsetup) 1256 fxp_mc_setup(sc); 1257 } 1258 /* 1259 * Try to start more packets transmitting. 1260 */ 1261 if (ifp->if_snd.ifq_head != NULL) 1262 fxp_start(ifp); 1263 } 1264 /* 1265 * Process receiver interrupts. If a no-resource (RNR) 1266 * condition exists, get whatever packets we can and 1267 * re-start the receiver. 1268 */ 1269 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1270 struct mbuf *m; 1271 struct fxp_rfa *rfa; 1272rcvloop: 1273 m = sc->rfa_headm; 1274 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1275 RFA_ALIGNMENT_FUDGE); 1276 1277#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1278 if (count < 0 || count-- > 0) 1279#endif 1280 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1281 /* 1282 * Remove first packet from the chain. 1283 */ 1284 sc->rfa_headm = m->m_next; 1285 m->m_next = NULL; 1286 1287 /* 1288 * Add a new buffer to the receive chain. 1289 * If this fails, the old buffer is recycled 1290 * instead. 1291 */ 1292 if (fxp_add_rfabuf(sc, m) == 0) { 1293 struct ether_header *eh; 1294 int total_len; 1295 1296 total_len = rfa->actual_size & 1297 (MCLBYTES - 1); 1298 if (total_len < 1299 sizeof(struct ether_header)) { 1300 m_freem(m); 1301 goto rcvloop; 1302 } 1303 1304 /* 1305 * Drop the packet if it has CRC 1306 * errors. This test is only needed 1307 * when doing 802.1q VLAN on the 82557 1308 * chip. 1309 */ 1310 if (rfa->rfa_status & 1311 FXP_RFA_STATUS_CRC) { 1312 m_freem(m); 1313 goto rcvloop; 1314 } 1315 1316 m->m_pkthdr.rcvif = ifp; 1317 m->m_pkthdr.len = m->m_len = total_len; 1318 eh = mtod(m, struct ether_header *); 1319 m->m_data += 1320 sizeof(struct ether_header); 1321 m->m_len -= 1322 sizeof(struct ether_header); 1323 m->m_pkthdr.len = m->m_len; 1324 ether_input(ifp, eh, m); 1325 } 1326 goto rcvloop; 1327 } 1328 if (statack & FXP_SCB_STATACK_RNR) { 1329 fxp_scb_wait(sc); 1330 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1331 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1332 RFA_ALIGNMENT_FUDGE); 1333 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1334 } 1335 } 1336} 1337 1338/* 1339 * Update packet in/out/collision statistics. The i82557 doesn't 1340 * allow you to access these counters without doing a fairly 1341 * expensive DMA to get _all_ of the statistics it maintains, so 1342 * we do this operation here only once per second. The statistics 1343 * counters in the kernel are updated from the previous dump-stats 1344 * DMA and then a new dump-stats DMA is started. The on-chip 1345 * counters are zeroed when the DMA completes. If we can't start 1346 * the DMA immediately, we don't wait - we just prepare to read 1347 * them again next time. 1348 */ 1349static void 1350fxp_tick(void *xsc) 1351{ 1352 struct fxp_softc *sc = xsc; 1353 struct ifnet *ifp = &sc->sc_if; 1354 struct fxp_stats *sp = sc->fxp_stats; 1355 struct fxp_cb_tx *txp; 1356 int s; 1357 1358 ifp->if_opackets += sp->tx_good; 1359 ifp->if_collisions += sp->tx_total_collisions; 1360 if (sp->rx_good) { 1361 ifp->if_ipackets += sp->rx_good; 1362 sc->rx_idle_secs = 0; 1363 } else { 1364 /* 1365 * Receiver's been idle for another second. 1366 */ 1367 sc->rx_idle_secs++; 1368 } 1369 ifp->if_ierrors += 1370 sp->rx_crc_errors + 1371 sp->rx_alignment_errors + 1372 sp->rx_rnr_errors + 1373 sp->rx_overrun_errors; 1374 /* 1375 * If any transmit underruns occured, bump up the transmit 1376 * threshold by another 512 bytes (64 * 8). 1377 */ 1378 if (sp->tx_underruns) { 1379 ifp->if_oerrors += sp->tx_underruns; 1380 if (tx_threshold < 192) 1381 tx_threshold += 64; 1382 } 1383 s = splimp(); 1384 /* 1385 * Release any xmit buffers that have completed DMA. This isn't 1386 * strictly necessary to do here, but it's advantagous for mbufs 1387 * with external storage to be released in a timely manner rather 1388 * than being defered for a potentially long time. This limits 1389 * the delay to a maximum of one second. 1390 */ 1391 for (txp = sc->cbl_first; sc->tx_queued && 1392 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1393 txp = txp->next) { 1394 if (txp->mb_head != NULL) { 1395 m_freem(txp->mb_head); 1396 txp->mb_head = NULL; 1397 } 1398 sc->tx_queued--; 1399 } 1400 sc->cbl_first = txp; 1401 /* 1402 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1403 * then assume the receiver has locked up and attempt to clear 1404 * the condition by reprogramming the multicast filter. This is 1405 * a work-around for a bug in the 82557 where the receiver locks 1406 * up if it gets certain types of garbage in the syncronization 1407 * bits prior to the packet header. This bug is supposed to only 1408 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1409 * mode as well (perhaps due to a 10/100 speed transition). 1410 */ 1411 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1412 sc->rx_idle_secs = 0; 1413 fxp_mc_setup(sc); 1414 } 1415 /* 1416 * If there is no pending command, start another stats 1417 * dump. Otherwise punt for now. 1418 */ 1419 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1420 /* 1421 * Start another stats dump. 1422 */ 1423 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1424 } else { 1425 /* 1426 * A previous command is still waiting to be accepted. 1427 * Just zero our copy of the stats and wait for the 1428 * next timer event to update them. 1429 */ 1430 sp->tx_good = 0; 1431 sp->tx_underruns = 0; 1432 sp->tx_total_collisions = 0; 1433 1434 sp->rx_good = 0; 1435 sp->rx_crc_errors = 0; 1436 sp->rx_alignment_errors = 0; 1437 sp->rx_rnr_errors = 0; 1438 sp->rx_overrun_errors = 0; 1439 } 1440 if (sc->miibus != NULL) 1441 mii_tick(device_get_softc(sc->miibus)); 1442 splx(s); 1443 /* 1444 * Schedule another timeout one second from now. 1445 */ 1446 sc->stat_ch = timeout(fxp_tick, sc, hz); 1447} 1448 1449/* 1450 * Stop the interface. Cancels the statistics updater and resets 1451 * the interface. 1452 */ 1453static void 1454fxp_stop(struct fxp_softc *sc) 1455{ 1456 struct ifnet *ifp = &sc->sc_if; 1457 struct fxp_cb_tx *txp; 1458 int i; 1459 1460 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1461 ifp->if_timer = 0; 1462 1463#ifdef DEVICE_POLLING 1464 ether_poll_deregister(ifp); 1465#endif 1466 /* 1467 * Cancel stats updater. 1468 */ 1469 untimeout(fxp_tick, sc, sc->stat_ch); 1470 1471 /* 1472 * Issue software reset, which also unloads the microcode. 1473 */ 1474 sc->flags &= ~FXP_FLAG_UCODE; 1475 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1476 DELAY(50); 1477 1478 /* 1479 * Release any xmit buffers. 1480 */ 1481 txp = sc->cbl_base; 1482 if (txp != NULL) { 1483 for (i = 0; i < FXP_NTXCB; i++) { 1484 if (txp[i].mb_head != NULL) { 1485 m_freem(txp[i].mb_head); 1486 txp[i].mb_head = NULL; 1487 } 1488 } 1489 } 1490 sc->tx_queued = 0; 1491 1492 /* 1493 * Free all the receive buffers then reallocate/reinitialize 1494 */ 1495 if (sc->rfa_headm != NULL) 1496 m_freem(sc->rfa_headm); 1497 sc->rfa_headm = NULL; 1498 sc->rfa_tailm = NULL; 1499 for (i = 0; i < FXP_NRFABUFS; i++) { 1500 if (fxp_add_rfabuf(sc, NULL) != 0) { 1501 /* 1502 * This "can't happen" - we're at splimp() 1503 * and we just freed all the buffers we need 1504 * above. 1505 */ 1506 panic("fxp_stop: no buffers!"); 1507 } 1508 } 1509} 1510 1511/* 1512 * Watchdog/transmission transmit timeout handler. Called when a 1513 * transmission is started on the interface, but no interrupt is 1514 * received before the timeout. This usually indicates that the 1515 * card has wedged for some reason. 1516 */ 1517static void 1518fxp_watchdog(struct ifnet *ifp) 1519{ 1520 struct fxp_softc *sc = ifp->if_softc; 1521 1522 device_printf(sc->dev, "device timeout\n"); 1523 ifp->if_oerrors++; 1524 1525 fxp_init(sc); 1526} 1527 1528static void 1529fxp_init(void *xsc) 1530{ 1531 struct fxp_softc *sc = xsc; 1532 struct ifnet *ifp = &sc->sc_if; 1533 struct fxp_cb_config *cbp; 1534 struct fxp_cb_ias *cb_ias; 1535 struct fxp_cb_tx *txp; 1536 struct fxp_cb_mcs *mcsp; 1537 int i, prm, s; 1538 1539 s = splimp(); 1540 /* 1541 * Cancel any pending I/O 1542 */ 1543 fxp_stop(sc); 1544 1545 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1546 1547 /* 1548 * Initialize base of CBL and RFA memory. Loading with zero 1549 * sets it up for regular linear addressing. 1550 */ 1551 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1552 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1553 1554 fxp_scb_wait(sc); 1555 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1556 1557 /* 1558 * Initialize base of dump-stats buffer. 1559 */ 1560 fxp_scb_wait(sc); 1561 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1562 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1563 1564 /* 1565 * Attempt to load microcode if requested. 1566 */ 1567 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1568 fxp_load_ucode(sc); 1569 1570 /* 1571 * Initialize the multicast address list. 1572 */ 1573 if (fxp_mc_addrs(sc)) { 1574 mcsp = sc->mcsp; 1575 mcsp->cb_status = 0; 1576 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1577 mcsp->link_addr = -1; 1578 /* 1579 * Start the multicast setup command. 1580 */ 1581 fxp_scb_wait(sc); 1582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1584 /* ...and wait for it to complete. */ 1585 fxp_dma_wait(&mcsp->cb_status, sc); 1586 } 1587 1588 /* 1589 * We temporarily use memory that contains the TxCB list to 1590 * construct the config CB. The TxCB list memory is rebuilt 1591 * later. 1592 */ 1593 cbp = (struct fxp_cb_config *) sc->cbl_base; 1594 1595 /* 1596 * This bcopy is kind of disgusting, but there are a bunch of must be 1597 * zero and must be one bits in this structure and this is the easiest 1598 * way to initialize them all to proper values. 1599 */ 1600 bcopy(fxp_cb_config_template, 1601 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1602 sizeof(fxp_cb_config_template)); 1603 1604 cbp->cb_status = 0; 1605 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1606 cbp->link_addr = -1; /* (no) next command */ 1607 cbp->byte_count = 22; /* (22) bytes to config */ 1608 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1609 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1610 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1611 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1612 cbp->type_enable = 0; /* actually reserved */ 1613 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1614 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1615 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1616 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1617 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1618 cbp->late_scb = 0; /* (don't) defer SCB update */ 1619 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1620 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1621 cbp->ci_int = 1; /* interrupt on CU idle */ 1622 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1623 cbp->ext_stats_dis = 1; /* disable extended counters */ 1624 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1625 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1626 cbp->disc_short_rx = !prm; /* discard short packets */ 1627 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1628 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1629 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1630 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1631 cbp->csma_dis = 0; /* (don't) disable link */ 1632 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1633 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1634 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1635 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1636 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1637 cbp->nsai = 1; /* (don't) disable source addr insert */ 1638 cbp->preamble_length = 2; /* (7 byte) preamble */ 1639 cbp->loopback = 0; /* (don't) loopback */ 1640 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1641 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1642 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1643 cbp->promiscuous = prm; /* promiscuous mode */ 1644 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1645 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1646 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1647 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1648 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1649 1650 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1651 cbp->padding = 1; /* (do) pad short tx packets */ 1652 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1653 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1654 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1655 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1656 /* must set wake_en in PMCSR also */ 1657 cbp->force_fdx = 0; /* (don't) force full duplex */ 1658 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1659 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1660 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1661 1662 if (sc->revision == FXP_REV_82557) { 1663 /* 1664 * The 82557 has no hardware flow control, the values 1665 * below are the defaults for the chip. 1666 */ 1667 cbp->fc_delay_lsb = 0; 1668 cbp->fc_delay_msb = 0x40; 1669 cbp->pri_fc_thresh = 3; 1670 cbp->tx_fc_dis = 0; 1671 cbp->rx_fc_restop = 0; 1672 cbp->rx_fc_restart = 0; 1673 cbp->fc_filter = 0; 1674 cbp->pri_fc_loc = 1; 1675 } else { 1676 cbp->fc_delay_lsb = 0x1f; 1677 cbp->fc_delay_msb = 0x01; 1678 cbp->pri_fc_thresh = 3; 1679 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1680 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1681 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1682 cbp->fc_filter = !prm; /* drop FC frames to host */ 1683 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1684 } 1685 1686 /* 1687 * Start the config command/DMA. 1688 */ 1689 fxp_scb_wait(sc); 1690 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1691 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1692 /* ...and wait for it to complete. */ 1693 fxp_dma_wait(&cbp->cb_status, sc); 1694 1695 /* 1696 * Now initialize the station address. Temporarily use the TxCB 1697 * memory area like we did above for the config CB. 1698 */ 1699 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1700 cb_ias->cb_status = 0; 1701 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1702 cb_ias->link_addr = -1; 1703 bcopy(sc->arpcom.ac_enaddr, 1704 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1705 sizeof(sc->arpcom.ac_enaddr)); 1706 1707 /* 1708 * Start the IAS (Individual Address Setup) command/DMA. 1709 */ 1710 fxp_scb_wait(sc); 1711 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1712 /* ...and wait for it to complete. */ 1713 fxp_dma_wait(&cb_ias->cb_status, sc); 1714 1715 /* 1716 * Initialize transmit control block (TxCB) list. 1717 */ 1718 1719 txp = sc->cbl_base; 1720 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1721 for (i = 0; i < FXP_NTXCB; i++) { 1722 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1723 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1724 txp[i].link_addr = 1725 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1726 if (sc->flags & FXP_FLAG_EXT_TXCB) 1727 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1728 else 1729 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1730 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1731 } 1732 /* 1733 * Set the suspend flag on the first TxCB and start the control 1734 * unit. It will execute the NOP and then suspend. 1735 */ 1736 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1737 sc->cbl_first = sc->cbl_last = txp; 1738 sc->tx_queued = 1; 1739 1740 fxp_scb_wait(sc); 1741 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1742 1743 /* 1744 * Initialize receiver buffer area - RFA. 1745 */ 1746 fxp_scb_wait(sc); 1747 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1748 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1749 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1750 1751 /* 1752 * Set current media. 1753 */ 1754 if (sc->miibus != NULL) 1755 mii_mediachg(device_get_softc(sc->miibus)); 1756 1757 ifp->if_flags |= IFF_RUNNING; 1758 ifp->if_flags &= ~IFF_OACTIVE; 1759 1760 /* 1761 * Enable interrupts. 1762 */ 1763 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1764 splx(s); 1765 1766 /* 1767 * Start stats updater. 1768 */ 1769 sc->stat_ch = timeout(fxp_tick, sc, hz); 1770} 1771 1772static int 1773fxp_serial_ifmedia_upd(struct ifnet *ifp) 1774{ 1775 1776 return (0); 1777} 1778 1779static void 1780fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1781{ 1782 1783 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1784} 1785 1786/* 1787 * Change media according to request. 1788 */ 1789static int 1790fxp_ifmedia_upd(struct ifnet *ifp) 1791{ 1792 struct fxp_softc *sc = ifp->if_softc; 1793 struct mii_data *mii; 1794 1795 mii = device_get_softc(sc->miibus); 1796 mii_mediachg(mii); 1797 return (0); 1798} 1799 1800/* 1801 * Notify the world which media we're using. 1802 */ 1803static void 1804fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1805{ 1806 struct fxp_softc *sc = ifp->if_softc; 1807 struct mii_data *mii; 1808 1809 mii = device_get_softc(sc->miibus); 1810 mii_pollstat(mii); 1811 ifmr->ifm_active = mii->mii_media_active; 1812 ifmr->ifm_status = mii->mii_media_status; 1813 1814 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1815 sc->cu_resume_bug = 1; 1816 else 1817 sc->cu_resume_bug = 0; 1818} 1819 1820/* 1821 * Add a buffer to the end of the RFA buffer list. 1822 * Return 0 if successful, 1 for failure. A failure results in 1823 * adding the 'oldm' (if non-NULL) on to the end of the list - 1824 * tossing out its old contents and recycling it. 1825 * The RFA struct is stuck at the beginning of mbuf cluster and the 1826 * data pointer is fixed up to point just past it. 1827 */ 1828static int 1829fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1830{ 1831 u_int32_t v; 1832 struct mbuf *m; 1833 struct fxp_rfa *rfa, *p_rfa; 1834 1835 MGETHDR(m, M_DONTWAIT, MT_DATA); 1836 if (m != NULL) { 1837 MCLGET(m, M_DONTWAIT); 1838 if ((m->m_flags & M_EXT) == 0) { 1839 m_freem(m); 1840 if (oldm == NULL) 1841 return 1; 1842 m = oldm; 1843 m->m_data = m->m_ext.ext_buf; 1844 } 1845 } else { 1846 if (oldm == NULL) 1847 return 1; 1848 m = oldm; 1849 m->m_data = m->m_ext.ext_buf; 1850 } 1851 1852 /* 1853 * Move the data pointer up so that the incoming data packet 1854 * will be 32-bit aligned. 1855 */ 1856 m->m_data += RFA_ALIGNMENT_FUDGE; 1857 1858 /* 1859 * Get a pointer to the base of the mbuf cluster and move 1860 * data start past it. 1861 */ 1862 rfa = mtod(m, struct fxp_rfa *); 1863 m->m_data += sizeof(struct fxp_rfa); 1864 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1865 1866 /* 1867 * Initialize the rest of the RFA. Note that since the RFA 1868 * is misaligned, we cannot store values directly. Instead, 1869 * we use an optimized, inline copy. 1870 */ 1871 1872 rfa->rfa_status = 0; 1873 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1874 rfa->actual_size = 0; 1875 1876 v = -1; 1877 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1878 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1879 1880 /* 1881 * If there are other buffers already on the list, attach this 1882 * one to the end by fixing up the tail to point to this one. 1883 */ 1884 if (sc->rfa_headm != NULL) { 1885 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1886 RFA_ALIGNMENT_FUDGE); 1887 sc->rfa_tailm->m_next = m; 1888 v = vtophys(rfa); 1889 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1890 p_rfa->rfa_control = 0; 1891 } else { 1892 sc->rfa_headm = m; 1893 } 1894 sc->rfa_tailm = m; 1895 1896 return (m == oldm); 1897} 1898 1899static volatile int 1900fxp_miibus_readreg(device_t dev, int phy, int reg) 1901{ 1902 struct fxp_softc *sc = device_get_softc(dev); 1903 int count = 10000; 1904 int value; 1905 1906 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1907 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1908 1909 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1910 && count--) 1911 DELAY(10); 1912 1913 if (count <= 0) 1914 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1915 1916 return (value & 0xffff); 1917} 1918 1919static void 1920fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1921{ 1922 struct fxp_softc *sc = device_get_softc(dev); 1923 int count = 10000; 1924 1925 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1926 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1927 (value & 0xffff)); 1928 1929 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1930 count--) 1931 DELAY(10); 1932 1933 if (count <= 0) 1934 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1935} 1936 1937static int 1938fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1939{ 1940 struct fxp_softc *sc = ifp->if_softc; 1941 struct ifreq *ifr = (struct ifreq *)data; 1942 struct mii_data *mii; 1943 int s, error = 0; 1944 1945 s = splimp(); 1946 1947 switch (command) { 1948 case SIOCSIFADDR: 1949 case SIOCGIFADDR: 1950 case SIOCSIFMTU: 1951 error = ether_ioctl(ifp, command, data); 1952 break; 1953 1954 case SIOCSIFFLAGS: 1955 if (ifp->if_flags & IFF_ALLMULTI) 1956 sc->flags |= FXP_FLAG_ALL_MCAST; 1957 else 1958 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1959 1960 /* 1961 * If interface is marked up and not running, then start it. 1962 * If it is marked down and running, stop it. 1963 * XXX If it's up then re-initialize it. This is so flags 1964 * such as IFF_PROMISC are handled. 1965 */ 1966 if (ifp->if_flags & IFF_UP) { 1967 fxp_init(sc); 1968 } else { 1969 if (ifp->if_flags & IFF_RUNNING) 1970 fxp_stop(sc); 1971 } 1972 break; 1973 1974 case SIOCADDMULTI: 1975 case SIOCDELMULTI: 1976 if (ifp->if_flags & IFF_ALLMULTI) 1977 sc->flags |= FXP_FLAG_ALL_MCAST; 1978 else 1979 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1980 /* 1981 * Multicast list has changed; set the hardware filter 1982 * accordingly. 1983 */ 1984 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1985 fxp_mc_setup(sc); 1986 /* 1987 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1988 * again rather than else {}. 1989 */ 1990 if (sc->flags & FXP_FLAG_ALL_MCAST) 1991 fxp_init(sc); 1992 error = 0; 1993 break; 1994 1995 case SIOCSIFMEDIA: 1996 case SIOCGIFMEDIA: 1997 if (sc->miibus != NULL) { 1998 mii = device_get_softc(sc->miibus); 1999 error = ifmedia_ioctl(ifp, ifr, 2000 &mii->mii_media, command); 2001 } else { 2002 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2003 } 2004 break; 2005 2006 default: 2007 error = EINVAL; 2008 } 2009 splx(s); 2010 return (error); 2011} 2012 2013/* 2014 * Fill in the multicast address list and return number of entries. 2015 */ 2016static int 2017fxp_mc_addrs(struct fxp_softc *sc) 2018{ 2019 struct fxp_cb_mcs *mcsp = sc->mcsp; 2020 struct ifnet *ifp = &sc->sc_if; 2021 struct ifmultiaddr *ifma; 2022 int nmcasts; 2023 2024 nmcasts = 0; 2025 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2026#if __FreeBSD_version < 500000 2027 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2028#else 2029 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2030#endif 2031 if (ifma->ifma_addr->sa_family != AF_LINK) 2032 continue; 2033 if (nmcasts >= MAXMCADDR) { 2034 sc->flags |= FXP_FLAG_ALL_MCAST; 2035 nmcasts = 0; 2036 break; 2037 } 2038 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2039 (void *)(uintptr_t)(volatile void *) 2040 &sc->mcsp->mc_addr[nmcasts][0], 6); 2041 nmcasts++; 2042 } 2043 } 2044 mcsp->mc_cnt = nmcasts * 6; 2045 return (nmcasts); 2046} 2047 2048/* 2049 * Program the multicast filter. 2050 * 2051 * We have an artificial restriction that the multicast setup command 2052 * must be the first command in the chain, so we take steps to ensure 2053 * this. By requiring this, it allows us to keep up the performance of 2054 * the pre-initialized command ring (esp. link pointers) by not actually 2055 * inserting the mcsetup command in the ring - i.e. its link pointer 2056 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2057 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2058 * lead into the regular TxCB ring when it completes. 2059 * 2060 * This function must be called at splimp. 2061 */ 2062static void 2063fxp_mc_setup(struct fxp_softc *sc) 2064{ 2065 struct fxp_cb_mcs *mcsp = sc->mcsp; 2066 struct ifnet *ifp = &sc->sc_if; 2067 int count; 2068 2069 /* 2070 * If there are queued commands, we must wait until they are all 2071 * completed. If we are already waiting, then add a NOP command 2072 * with interrupt option so that we're notified when all commands 2073 * have been completed - fxp_start() ensures that no additional 2074 * TX commands will be added when need_mcsetup is true. 2075 */ 2076 if (sc->tx_queued) { 2077 struct fxp_cb_tx *txp; 2078 2079 /* 2080 * need_mcsetup will be true if we are already waiting for the 2081 * NOP command to be completed (see below). In this case, bail. 2082 */ 2083 if (sc->need_mcsetup) 2084 return; 2085 sc->need_mcsetup = 1; 2086 2087 /* 2088 * Add a NOP command with interrupt so that we are notified 2089 * when all TX commands have been processed. 2090 */ 2091 txp = sc->cbl_last->next; 2092 txp->mb_head = NULL; 2093 txp->cb_status = 0; 2094 txp->cb_command = FXP_CB_COMMAND_NOP | 2095 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2096 /* 2097 * Advance the end of list forward. 2098 */ 2099 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2100 sc->cbl_last = txp; 2101 sc->tx_queued++; 2102 /* 2103 * Issue a resume in case the CU has just suspended. 2104 */ 2105 fxp_scb_wait(sc); 2106 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2107 /* 2108 * Set a 5 second timer just in case we don't hear from the 2109 * card again. 2110 */ 2111 ifp->if_timer = 5; 2112 2113 return; 2114 } 2115 sc->need_mcsetup = 0; 2116 2117 /* 2118 * Initialize multicast setup descriptor. 2119 */ 2120 mcsp->next = sc->cbl_base; 2121 mcsp->mb_head = NULL; 2122 mcsp->cb_status = 0; 2123 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2124 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2125 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2126 (void) fxp_mc_addrs(sc); 2127 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2128 sc->tx_queued = 1; 2129 2130 /* 2131 * Wait until command unit is not active. This should never 2132 * be the case when nothing is queued, but make sure anyway. 2133 */ 2134 count = 100; 2135 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2136 FXP_SCB_CUS_ACTIVE && --count) 2137 DELAY(10); 2138 if (count == 0) { 2139 device_printf(sc->dev, "command queue timeout\n"); 2140 return; 2141 } 2142 2143 /* 2144 * Start the multicast setup command. 2145 */ 2146 fxp_scb_wait(sc); 2147 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2149 2150 ifp->if_timer = 2; 2151 return; 2152} 2153 2154static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2155static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2156static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2157static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2158static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2159static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2160 2161#define UCODE(x) x, sizeof(x) 2162 2163struct ucode { 2164 u_int32_t revision; 2165 u_int32_t *ucode; 2166 int length; 2167 u_short int_delay_offset; 2168 u_short bundle_max_offset; 2169} ucode_table[] = { 2170 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2171 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2172 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2173 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2174 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2175 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2176 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2177 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2178 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2179 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2180 { 0, NULL, 0, 0, 0 } 2181}; 2182 2183static void 2184fxp_load_ucode(struct fxp_softc *sc) 2185{ 2186 struct ucode *uc; 2187 struct fxp_cb_ucode *cbp; 2188 2189 for (uc = ucode_table; uc->ucode != NULL; uc++) 2190 if (sc->revision == uc->revision) 2191 break; 2192 if (uc->ucode == NULL) 2193 return; 2194 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2195 cbp->cb_status = 0; 2196 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2197 cbp->link_addr = -1; /* (no) next command */ 2198 memcpy(cbp->ucode, uc->ucode, uc->length); 2199 if (uc->int_delay_offset) 2200 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2201 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2202 if (uc->bundle_max_offset) 2203 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2204 sc->tunable_bundle_max; 2205 /* 2206 * Download the ucode to the chip. 2207 */ 2208 fxp_scb_wait(sc); 2209 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2210 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2211 /* ...and wait for it to complete. */ 2212 fxp_dma_wait(&cbp->cb_status, sc); 2213 device_printf(sc->dev, 2214 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2215 sc->tunable_int_delay, 2216 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2217 sc->flags |= FXP_FLAG_UCODE; 2218} 2219 2220static int 2221sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2222{ 2223 int error, value; 2224 2225 value = *(int *)arg1; 2226 error = sysctl_handle_int(oidp, &value, 0, req); 2227 if (error || !req->newptr) 2228 return (error); 2229 if (value < low || value > high) 2230 return (EINVAL); 2231 *(int *)arg1 = value; 2232 return (0); 2233} 2234 2235/* 2236 * Interrupt delay is expressed in microseconds, a multiplier is used 2237 * to convert this to the appropriate clock ticks before using. 2238 */ 2239static int 2240sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2241{ 2242 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2243} 2244 2245static int 2246sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2247{ 2248 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2249} 2250