1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/fxp/if_fxp.c 345186 2019-03-15 15:16:31Z markj $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#ifdef HAVE_KERNEL_OPTION_HEADERS 38#include "opt_device_polling.h" 39#endif 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/mbuf.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/rman.h> 52#include <sys/socket.h> 53#include <sys/sockio.h> 54#include <sys/sysctl.h> 55 56#include <net/bpf.h> 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_var.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_media.h> 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <netinet/tcp.h> 70#include <netinet/udp.h> 71 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74#include <machine/resource.h> 75 76#include <dev/pci/pcivar.h> 77#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 78 79#include <dev/mii/mii.h> 80#include <dev/mii/miivar.h> 81 82#include <dev/fxp/if_fxpreg.h> 83#include <dev/fxp/if_fxpvar.h> 84#include <dev/fxp/rcvbundl.h> 85 86MODULE_DEPEND(fxp, pci, 1, 1, 1); 87MODULE_DEPEND(fxp, ether, 1, 1, 1); 88MODULE_DEPEND(fxp, miibus, 1, 1, 1); 89#include "miibus_if.h" 90 91/* 92 * NOTE! On !x86 we typically have an alignment constraint. The 93 * card DMAs the packet immediately following the RFA. However, 94 * the first thing in the packet is a 14-byte Ethernet header. 95 * This means that the packet is misaligned. To compensate, 96 * we actually offset the RFA 2 bytes into the cluster. This 97 * alignes the packet after the Ethernet header at a 32-bit 98 * boundary. HOWEVER! This means that the RFA is misaligned! 99 */ 100#define RFA_ALIGNMENT_FUDGE 2 101 102/* 103 * Set initial transmit threshold at 64 (512 bytes). This is 104 * increased by 64 (512 bytes) at a time, to maximum of 192 105 * (1536 bytes), if an underrun occurs. 106 */ 107static int tx_threshold = 64; 108 109/* 110 * The configuration byte map has several undefined fields which 111 * must be one or must be zero. Set up a template for these bits. 112 * The actual configuration is performed in fxp_init_body. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116static const u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5, /* 21 */ 142 0x0, /* 22 */ 143 0x0, /* 23 */ 144 0x0, /* 24 */ 145 0x0, /* 25 */ 146 0x0, /* 26 */ 147 0x0, /* 27 */ 148 0x0, /* 28 */ 149 0x0, /* 29 */ 150 0x0, /* 30 */ 151 0x0 /* 31 */ 152}; 153 154/* 155 * Claim various Intel PCI device identifiers for this driver. The 156 * sub-vendor and sub-device field are extensively used to identify 157 * particular variants, but we don't currently differentiate between 158 * them. 159 */ 160static const struct fxp_ident fxp_ident_table[] = { 161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 167 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 169 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 170 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 171 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 172 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 173 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 174 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 175 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 176 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 177 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 178 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 179 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 180 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 181 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 182 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 183 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 184 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 185 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 186 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 187 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 188 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 189 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 190 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 191 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 192 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 193 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 194 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 195 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 196 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 197 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 198 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 199 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" }, 200 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 201 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 202 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 203 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 204 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 205 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 206 { 0, 0, -1, 0, NULL }, 207}; 208 209#ifdef FXP_IP_CSUM_WAR 210#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 211#else 212#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 213#endif 214 215static int fxp_probe(device_t dev); 216static int fxp_attach(device_t dev); 217static int fxp_detach(device_t dev); 218static int fxp_shutdown(device_t dev); 219static int fxp_suspend(device_t dev); 220static int fxp_resume(device_t dev); 221 222static const struct fxp_ident *fxp_find_ident(device_t dev); 223static void fxp_intr(void *xsc); 224static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp, 225 struct mbuf *m, uint16_t status, int pos); 226static int fxp_intr_body(struct fxp_softc *sc, if_t ifp, 227 uint8_t statack, int count); 228static void fxp_init(void *xsc); 229static void fxp_init_body(struct fxp_softc *sc, int); 230static void fxp_tick(void *xsc); 231static void fxp_start(if_t ifp); 232static void fxp_start_body(if_t ifp); 233static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 234static void fxp_txeof(struct fxp_softc *sc); 235static void fxp_stop(struct fxp_softc *sc); 236static void fxp_release(struct fxp_softc *sc); 237static int fxp_ioctl(if_t ifp, u_long command, 238 caddr_t data); 239static void fxp_watchdog(struct fxp_softc *sc); 240static void fxp_add_rfabuf(struct fxp_softc *sc, 241 struct fxp_rx *rxp); 242static void fxp_discard_rfabuf(struct fxp_softc *sc, 243 struct fxp_rx *rxp); 244static int fxp_new_rfabuf(struct fxp_softc *sc, 245 struct fxp_rx *rxp); 246static int fxp_mc_addrs(struct fxp_softc *sc); 247static void fxp_mc_setup(struct fxp_softc *sc); 248static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 249 int autosize); 250static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 251 uint16_t data); 252static void fxp_autosize_eeprom(struct fxp_softc *sc); 253static void fxp_load_eeprom(struct fxp_softc *sc); 254static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 255 int offset, int words); 256static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 257 int offset, int words); 258static int fxp_ifmedia_upd(if_t ifp); 259static void fxp_ifmedia_sts(if_t ifp, 260 struct ifmediareq *ifmr); 261static int fxp_serial_ifmedia_upd(if_t ifp); 262static void fxp_serial_ifmedia_sts(if_t ifp, 263 struct ifmediareq *ifmr); 264static int fxp_miibus_readreg(device_t dev, int phy, int reg); 265static int fxp_miibus_writereg(device_t dev, int phy, int reg, 266 int value); 267static void fxp_miibus_statchg(device_t dev); 268static void fxp_load_ucode(struct fxp_softc *sc); 269static void fxp_update_stats(struct fxp_softc *sc); 270static void fxp_sysctl_node(struct fxp_softc *sc); 271static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 272 int low, int high); 273static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 274static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 275static void fxp_scb_wait(struct fxp_softc *sc); 276static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 277static void fxp_dma_wait(struct fxp_softc *sc, 278 volatile uint16_t *status, bus_dma_tag_t dmat, 279 bus_dmamap_t map); 280 281static device_method_t fxp_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, fxp_probe), 284 DEVMETHOD(device_attach, fxp_attach), 285 DEVMETHOD(device_detach, fxp_detach), 286 DEVMETHOD(device_shutdown, fxp_shutdown), 287 DEVMETHOD(device_suspend, fxp_suspend), 288 DEVMETHOD(device_resume, fxp_resume), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 292 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 293 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 294 295 DEVMETHOD_END 296}; 297 298static driver_t fxp_driver = { 299 "fxp", 300 fxp_methods, 301 sizeof(struct fxp_softc), 302}; 303 304static devclass_t fxp_devclass; 305 306DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL, 307 SI_ORDER_ANY); 308DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL); 309 310static struct resource_spec fxp_res_spec_mem[] = { 311 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 312 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 313 { -1, 0 } 314}; 315 316static struct resource_spec fxp_res_spec_io[] = { 317 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 318 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 319 { -1, 0 } 320}; 321 322/* 323 * Wait for the previous command to be accepted (but not necessarily 324 * completed). 325 */ 326static void 327fxp_scb_wait(struct fxp_softc *sc) 328{ 329 union { 330 uint16_t w; 331 uint8_t b[2]; 332 } flowctl; 333 int i = 10000; 334 335 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 336 DELAY(2); 337 if (i == 0) { 338 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 339 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 340 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 341 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 342 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 343 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 344 } 345} 346 347static void 348fxp_scb_cmd(struct fxp_softc *sc, int cmd) 349{ 350 351 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 352 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 353 fxp_scb_wait(sc); 354 } 355 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 356} 357 358static void 359fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 360 bus_dma_tag_t dmat, bus_dmamap_t map) 361{ 362 int i; 363 364 for (i = 10000; i > 0; i--) { 365 DELAY(2); 366 bus_dmamap_sync(dmat, map, 367 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 368 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 369 break; 370 } 371 if (i == 0) 372 device_printf(sc->dev, "DMA timeout\n"); 373} 374 375static const struct fxp_ident * 376fxp_find_ident(device_t dev) 377{ 378 uint16_t vendor; 379 uint16_t device; 380 uint8_t revid; 381 const struct fxp_ident *ident; 382 383 vendor = pci_get_vendor(dev); 384 device = pci_get_device(dev); 385 revid = pci_get_revid(dev); 386 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 387 if (ident->vendor == vendor && ident->device == device && 388 (ident->revid == revid || ident->revid == -1)) { 389 return (ident); 390 } 391 } 392 return (NULL); 393} 394 395/* 396 * Return identification string if this device is ours. 397 */ 398static int 399fxp_probe(device_t dev) 400{ 401 const struct fxp_ident *ident; 402 403 ident = fxp_find_ident(dev); 404 if (ident != NULL) { 405 device_set_desc(dev, ident->name); 406 return (BUS_PROBE_DEFAULT); 407 } 408 return (ENXIO); 409} 410 411static void 412fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 413{ 414 uint32_t *addr; 415 416 if (error) 417 return; 418 419 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 420 addr = arg; 421 *addr = segs->ds_addr; 422} 423 424static int 425fxp_attach(device_t dev) 426{ 427 struct fxp_softc *sc; 428 struct fxp_cb_tx *tcbp; 429 struct fxp_tx *txp; 430 struct fxp_rx *rxp; 431 if_t ifp; 432 uint32_t val; 433 uint16_t data; 434 u_char eaddr[ETHER_ADDR_LEN]; 435 int error, flags, i, pmc, prefer_iomap; 436 437 error = 0; 438 sc = device_get_softc(dev); 439 sc->dev = dev; 440 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 441 MTX_DEF); 442 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 443 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 444 fxp_serial_ifmedia_sts); 445 446 ifp = sc->ifp = if_gethandle(IFT_ETHER); 447 if (ifp == (void *)NULL) { 448 device_printf(dev, "can not if_alloc()\n"); 449 error = ENOSPC; 450 goto fail; 451 } 452 453 /* 454 * Enable bus mastering. 455 */ 456 pci_enable_busmaster(dev); 457 458 /* 459 * Figure out which we should try first - memory mapping or i/o mapping? 460 * We default to memory mapping. Then we accept an override from the 461 * command line. Then we check to see which one is enabled. 462 */ 463 prefer_iomap = 0; 464 resource_int_value(device_get_name(dev), device_get_unit(dev), 465 "prefer_iomap", &prefer_iomap); 466 if (prefer_iomap) 467 sc->fxp_spec = fxp_res_spec_io; 468 else 469 sc->fxp_spec = fxp_res_spec_mem; 470 471 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 472 if (error) { 473 if (sc->fxp_spec == fxp_res_spec_mem) 474 sc->fxp_spec = fxp_res_spec_io; 475 else 476 sc->fxp_spec = fxp_res_spec_mem; 477 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 478 } 479 if (error) { 480 device_printf(dev, "could not allocate resources\n"); 481 error = ENXIO; 482 goto fail; 483 } 484 485 if (bootverbose) { 486 device_printf(dev, "using %s space register mapping\n", 487 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 488 } 489 490 /* 491 * Put CU/RU idle state and prepare full reset. 492 */ 493 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 494 DELAY(10); 495 /* Full reset and disable interrupts. */ 496 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 497 DELAY(10); 498 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 499 500 /* 501 * Find out how large of an SEEPROM we have. 502 */ 503 fxp_autosize_eeprom(sc); 504 fxp_load_eeprom(sc); 505 506 /* 507 * Find out the chip revision; lump all 82557 revs together. 508 */ 509 sc->ident = fxp_find_ident(dev); 510 if (sc->ident->ich > 0) { 511 /* Assume ICH controllers are 82559. */ 512 sc->revision = FXP_REV_82559_A0; 513 } else { 514 data = sc->eeprom[FXP_EEPROM_MAP_CNTR]; 515 if ((data >> 8) == 1) 516 sc->revision = FXP_REV_82557; 517 else 518 sc->revision = pci_get_revid(dev); 519 } 520 521 /* 522 * Check availability of WOL. 82559ER does not support WOL. 523 */ 524 if (sc->revision >= FXP_REV_82558_A4 && 525 sc->revision != FXP_REV_82559S_A) { 526 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 527 if ((data & 0x20) != 0 && 528 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 529 sc->flags |= FXP_FLAG_WOLCAP; 530 } 531 532 if (sc->revision == FXP_REV_82550_C) { 533 /* 534 * 82550C with server extension requires microcode to 535 * receive fragmented UDP datagrams. However if the 536 * microcode is used for client-only featured 82550C 537 * it locks up controller. 538 */ 539 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 540 if ((data & 0x0400) == 0) 541 sc->flags |= FXP_FLAG_NO_UCODE; 542 } 543 544 /* Receiver lock-up workaround detection. */ 545 if (sc->revision < FXP_REV_82558_A4) { 546 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 547 if ((data & 0x03) != 0x03) { 548 sc->flags |= FXP_FLAG_RXBUG; 549 device_printf(dev, "Enabling Rx lock-up workaround\n"); 550 } 551 } 552 553 /* 554 * Determine whether we must use the 503 serial interface. 555 */ 556 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY]; 557 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 558 && (data & FXP_PHY_SERIAL_ONLY)) 559 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 560 561 fxp_sysctl_node(sc); 562 /* 563 * Enable workarounds for certain chip revision deficiencies. 564 * 565 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 566 * some systems based a normal 82559 design, have a defect where 567 * the chip can cause a PCI protocol violation if it receives 568 * a CU_RESUME command when it is entering the IDLE state. The 569 * workaround is to disable Dynamic Standby Mode, so the chip never 570 * deasserts CLKRUN#, and always remains in an active state. 571 * 572 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 573 */ 574 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 575 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 576 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 577 if (data & 0x02) { /* STB enable */ 578 uint16_t cksum; 579 int i; 580 581 device_printf(dev, 582 "Disabling dynamic standby mode in EEPROM\n"); 583 data &= ~0x02; 584 sc->eeprom[FXP_EEPROM_MAP_ID] = data; 585 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1); 586 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 587 cksum = 0; 588 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 589 cksum += sc->eeprom[i]; 590 i = (1 << sc->eeprom_size) - 1; 591 cksum = 0xBABA - cksum; 592 fxp_write_eeprom(sc, &cksum, i, 1); 593 device_printf(dev, 594 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 595 i, sc->eeprom[i], cksum); 596 sc->eeprom[i] = cksum; 597 /* 598 * If the user elects to continue, try the software 599 * workaround, as it is better than nothing. 600 */ 601 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 602 } 603 } 604 605 /* 606 * If we are not a 82557 chip, we can enable extended features. 607 */ 608 if (sc->revision != FXP_REV_82557) { 609 /* 610 * If MWI is enabled in the PCI configuration, and there 611 * is a valid cacheline size (8 or 16 dwords), then tell 612 * the board to turn on MWI. 613 */ 614 val = pci_read_config(dev, PCIR_COMMAND, 2); 615 if (val & PCIM_CMD_MWRICEN && 616 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 617 sc->flags |= FXP_FLAG_MWI_ENABLE; 618 619 /* turn on the extended TxCB feature */ 620 sc->flags |= FXP_FLAG_EXT_TXCB; 621 622 /* enable reception of long frames for VLAN */ 623 sc->flags |= FXP_FLAG_LONG_PKT_EN; 624 } else { 625 /* a hack to get long VLAN frames on a 82557 */ 626 sc->flags |= FXP_FLAG_SAVE_BAD; 627 } 628 629 /* For 82559 or later chips, Rx checksum offload is supported. */ 630 if (sc->revision >= FXP_REV_82559_A0) { 631 /* 82559ER does not support Rx checksum offloading. */ 632 if (sc->ident->device != 0x1209) 633 sc->flags |= FXP_FLAG_82559_RXCSUM; 634 } 635 /* 636 * Enable use of extended RFDs and TCBs for 82550 637 * and later chips. Note: we need extended TXCB support 638 * too, but that's already enabled by the code above. 639 * Be careful to do this only on the right devices. 640 */ 641 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 642 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 643 || sc->revision == FXP_REV_82551_10) { 644 sc->rfa_size = sizeof (struct fxp_rfa); 645 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 646 sc->flags |= FXP_FLAG_EXT_RFA; 647 /* Use extended RFA instead of 82559 checksum mode. */ 648 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 649 } else { 650 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 651 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 652 } 653 654 /* 655 * Allocate DMA tags and DMA safe memory. 656 */ 657 sc->maxtxseg = FXP_NTXSEG; 658 sc->maxsegsize = MCLBYTES; 659 if (sc->flags & FXP_FLAG_EXT_RFA) { 660 sc->maxtxseg--; 661 sc->maxsegsize = FXP_TSO_SEGSIZE; 662 } 663 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 664 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 665 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 666 sc->maxtxseg, sc->maxsegsize, 0, 667 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 668 if (error) { 669 device_printf(dev, "could not create TX DMA tag\n"); 670 goto fail; 671 } 672 673 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 674 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 675 MCLBYTES, 1, MCLBYTES, 0, 676 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 677 if (error) { 678 device_printf(dev, "could not create RX DMA tag\n"); 679 goto fail; 680 } 681 682 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 683 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 684 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 685 busdma_lock_mutex, &Giant, &sc->fxp_stag); 686 if (error) { 687 device_printf(dev, "could not create stats DMA tag\n"); 688 goto fail; 689 } 690 691 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 692 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 693 if (error) { 694 device_printf(dev, "could not allocate stats DMA memory\n"); 695 goto fail; 696 } 697 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 698 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 699 BUS_DMA_NOWAIT); 700 if (error) { 701 device_printf(dev, "could not load the stats DMA buffer\n"); 702 goto fail; 703 } 704 705 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 706 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 707 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 708 busdma_lock_mutex, &Giant, &sc->cbl_tag); 709 if (error) { 710 device_printf(dev, "could not create TxCB DMA tag\n"); 711 goto fail; 712 } 713 714 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 715 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 716 if (error) { 717 device_printf(dev, "could not allocate TxCB DMA memory\n"); 718 goto fail; 719 } 720 721 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 722 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 723 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT); 724 if (error) { 725 device_printf(dev, "could not load TxCB DMA buffer\n"); 726 goto fail; 727 } 728 729 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 730 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 731 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 732 busdma_lock_mutex, &Giant, &sc->mcs_tag); 733 if (error) { 734 device_printf(dev, 735 "could not create multicast setup DMA tag\n"); 736 goto fail; 737 } 738 739 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 740 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 741 if (error) { 742 device_printf(dev, 743 "could not allocate multicast setup DMA memory\n"); 744 goto fail; 745 } 746 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 747 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 748 BUS_DMA_NOWAIT); 749 if (error) { 750 device_printf(dev, 751 "can't load the multicast setup DMA buffer\n"); 752 goto fail; 753 } 754 755 /* 756 * Pre-allocate the TX DMA maps and setup the pointers to 757 * the TX command blocks. 758 */ 759 txp = sc->fxp_desc.tx_list; 760 tcbp = sc->fxp_desc.cbl_list; 761 for (i = 0; i < FXP_NTXCB; i++) { 762 txp[i].tx_cb = tcbp + i; 763 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 764 if (error) { 765 device_printf(dev, "can't create DMA map for TX\n"); 766 goto fail; 767 } 768 } 769 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 770 if (error) { 771 device_printf(dev, "can't create spare DMA map\n"); 772 goto fail; 773 } 774 775 /* 776 * Pre-allocate our receive buffers. 777 */ 778 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 779 for (i = 0; i < FXP_NRFABUFS; i++) { 780 rxp = &sc->fxp_desc.rx_list[i]; 781 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 782 if (error) { 783 device_printf(dev, "can't create DMA map for RX\n"); 784 goto fail; 785 } 786 if (fxp_new_rfabuf(sc, rxp) != 0) { 787 error = ENOMEM; 788 goto fail; 789 } 790 fxp_add_rfabuf(sc, rxp); 791 } 792 793 /* 794 * Read MAC address. 795 */ 796 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff; 797 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8; 798 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff; 799 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8; 800 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff; 801 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8; 802 if (bootverbose) { 803 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 804 pci_get_vendor(dev), pci_get_device(dev), 805 pci_get_subvendor(dev), pci_get_subdevice(dev), 806 pci_get_revid(dev)); 807 device_printf(dev, "Dynamic Standby mode is %s\n", 808 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" : 809 "disabled"); 810 } 811 812 /* 813 * If this is only a 10Mbps device, then there is no MII, and 814 * the PHY will use a serial interface instead. 815 * 816 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 817 * doesn't have a programming interface of any sort. The 818 * media is sensed automatically based on how the link partner 819 * is configured. This is, in essence, manual configuration. 820 */ 821 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 822 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 823 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 824 } else { 825 /* 826 * i82557 wedge when isolating all of their PHYs. 827 */ 828 flags = MIIF_NOISOLATE; 829 if (sc->revision >= FXP_REV_82558_A4) 830 flags |= MIIF_DOPAUSE; 831 error = mii_attach(dev, &sc->miibus, ifp, 832 (ifm_change_cb_t)fxp_ifmedia_upd, 833 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK, 834 MII_PHY_ANY, MII_OFFSET_ANY, flags); 835 if (error != 0) { 836 device_printf(dev, "attaching PHYs failed\n"); 837 goto fail; 838 } 839 } 840 841 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 842 if_setdev(ifp, dev); 843 if_setinitfn(ifp, fxp_init); 844 if_setsoftc(ifp, sc); 845 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 846 if_setioctlfn(ifp, fxp_ioctl); 847 if_setstartfn(ifp, fxp_start); 848 849 if_setcapabilities(ifp, 0); 850 if_setcapenable(ifp, 0); 851 852 /* Enable checksum offload/TSO for 82550 or better chips */ 853 if (sc->flags & FXP_FLAG_EXT_RFA) { 854 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO); 855 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 856 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 857 } 858 859 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 860 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 861 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0); 862 } 863 864 if (sc->flags & FXP_FLAG_WOLCAP) { 865 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 866 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0); 867 } 868 869#ifdef DEVICE_POLLING 870 /* Inform the world we support polling. */ 871 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 872#endif 873 874 /* 875 * Attach the interface. 876 */ 877 ether_ifattach(ifp, eaddr); 878 879 /* 880 * Tell the upper layer(s) we support long frames. 881 * Must appear after the call to ether_ifattach() because 882 * ether_ifattach() sets ifi_hdrlen to the default value. 883 */ 884 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 885 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 886 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 887 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 888 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | 889 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 890 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING | 891 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 892 } 893 894 /* 895 * Let the system queue as many packets as we have available 896 * TX descriptors. 897 */ 898 if_setsendqlen(ifp, FXP_NTXCB - 1); 899 if_setsendqready(ifp); 900 901 /* 902 * Hook our interrupt after all initialization is complete. 903 */ 904 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 905 NULL, fxp_intr, sc, &sc->ih); 906 if (error) { 907 device_printf(dev, "could not setup irq\n"); 908 ether_ifdetach(sc->ifp); 909 goto fail; 910 } 911 912 /* 913 * Configure hardware to reject magic frames otherwise 914 * system will hang on recipt of magic frames. 915 */ 916 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 917 FXP_LOCK(sc); 918 /* Clear wakeup events. */ 919 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 920 fxp_init_body(sc, 0); 921 fxp_stop(sc); 922 FXP_UNLOCK(sc); 923 } 924 925fail: 926 if (error) 927 fxp_release(sc); 928 return (error); 929} 930 931/* 932 * Release all resources. The softc lock should not be held and the 933 * interrupt should already be torn down. 934 */ 935static void 936fxp_release(struct fxp_softc *sc) 937{ 938 struct fxp_rx *rxp; 939 struct fxp_tx *txp; 940 int i; 941 942 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 943 KASSERT(sc->ih == NULL, 944 ("fxp_release() called with intr handle still active")); 945 if (sc->miibus) 946 device_delete_child(sc->dev, sc->miibus); 947 bus_generic_detach(sc->dev); 948 ifmedia_removeall(&sc->sc_media); 949 if (sc->fxp_desc.cbl_list) { 950 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 951 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 952 sc->cbl_map); 953 } 954 if (sc->fxp_stats) { 955 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 956 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 957 } 958 if (sc->mcsp) { 959 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 960 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 961 } 962 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 963 if (sc->fxp_rxmtag) { 964 for (i = 0; i < FXP_NRFABUFS; i++) { 965 rxp = &sc->fxp_desc.rx_list[i]; 966 if (rxp->rx_mbuf != NULL) { 967 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 968 BUS_DMASYNC_POSTREAD); 969 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 970 m_freem(rxp->rx_mbuf); 971 } 972 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 973 } 974 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 975 bus_dma_tag_destroy(sc->fxp_rxmtag); 976 } 977 if (sc->fxp_txmtag) { 978 for (i = 0; i < FXP_NTXCB; i++) { 979 txp = &sc->fxp_desc.tx_list[i]; 980 if (txp->tx_mbuf != NULL) { 981 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 982 BUS_DMASYNC_POSTWRITE); 983 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 984 m_freem(txp->tx_mbuf); 985 } 986 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 987 } 988 bus_dma_tag_destroy(sc->fxp_txmtag); 989 } 990 if (sc->fxp_stag) 991 bus_dma_tag_destroy(sc->fxp_stag); 992 if (sc->cbl_tag) 993 bus_dma_tag_destroy(sc->cbl_tag); 994 if (sc->mcs_tag) 995 bus_dma_tag_destroy(sc->mcs_tag); 996 if (sc->ifp) 997 if_free(sc->ifp); 998 999 mtx_destroy(&sc->sc_mtx); 1000} 1001 1002/* 1003 * Detach interface. 1004 */ 1005static int 1006fxp_detach(device_t dev) 1007{ 1008 struct fxp_softc *sc = device_get_softc(dev); 1009 1010#ifdef DEVICE_POLLING 1011 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) 1012 ether_poll_deregister(sc->ifp); 1013#endif 1014 1015 FXP_LOCK(sc); 1016 /* 1017 * Stop DMA and drop transmit queue, but disable interrupts first. 1018 */ 1019 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1020 fxp_stop(sc); 1021 FXP_UNLOCK(sc); 1022 callout_drain(&sc->stat_ch); 1023 1024 /* 1025 * Close down routes etc. 1026 */ 1027 ether_ifdetach(sc->ifp); 1028 1029 /* 1030 * Unhook interrupt before dropping lock. This is to prevent 1031 * races with fxp_intr(). 1032 */ 1033 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1034 sc->ih = NULL; 1035 1036 /* Release our allocated resources. */ 1037 fxp_release(sc); 1038 return (0); 1039} 1040 1041/* 1042 * Device shutdown routine. Called at system shutdown after sync. The 1043 * main purpose of this routine is to shut off receiver DMA so that 1044 * kernel memory doesn't get clobbered during warmboot. 1045 */ 1046static int 1047fxp_shutdown(device_t dev) 1048{ 1049 1050 /* 1051 * Make sure that DMA is disabled prior to reboot. Not doing 1052 * do could allow DMA to corrupt kernel memory during the 1053 * reboot before the driver initializes. 1054 */ 1055 return (fxp_suspend(dev)); 1056} 1057 1058/* 1059 * Device suspend routine. Stop the interface and save some PCI 1060 * settings in case the BIOS doesn't restore them properly on 1061 * resume. 1062 */ 1063static int 1064fxp_suspend(device_t dev) 1065{ 1066 struct fxp_softc *sc = device_get_softc(dev); 1067 if_t ifp; 1068 int pmc; 1069 uint16_t pmstat; 1070 1071 FXP_LOCK(sc); 1072 1073 ifp = sc->ifp; 1074 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1075 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1076 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1077 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1078 /* Request PME. */ 1079 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1080 sc->flags |= FXP_FLAG_WOL; 1081 /* Reconfigure hardware to accept magic frames. */ 1082 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1083 fxp_init_body(sc, 0); 1084 } 1085 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1086 } 1087 fxp_stop(sc); 1088 1089 sc->suspended = 1; 1090 1091 FXP_UNLOCK(sc); 1092 return (0); 1093} 1094 1095/* 1096 * Device resume routine. re-enable busmastering, and restart the interface if 1097 * appropriate. 1098 */ 1099static int 1100fxp_resume(device_t dev) 1101{ 1102 struct fxp_softc *sc = device_get_softc(dev); 1103 if_t ifp = sc->ifp; 1104 int pmc; 1105 uint16_t pmstat; 1106 1107 FXP_LOCK(sc); 1108 1109 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1110 sc->flags &= ~FXP_FLAG_WOL; 1111 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1112 /* Disable PME and clear PME status. */ 1113 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1114 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1115 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1116 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1117 CSR_READ_1(sc, FXP_CSR_PMDR)); 1118 } 1119 1120 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1121 DELAY(10); 1122 1123 /* reinitialize interface if necessary */ 1124 if (if_getflags(ifp) & IFF_UP) 1125 fxp_init_body(sc, 1); 1126 1127 sc->suspended = 0; 1128 1129 FXP_UNLOCK(sc); 1130 return (0); 1131} 1132 1133static void 1134fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1135{ 1136 uint16_t reg; 1137 int x; 1138 1139 /* 1140 * Shift in data. 1141 */ 1142 for (x = 1 << (length - 1); x; x >>= 1) { 1143 if (data & x) 1144 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1145 else 1146 reg = FXP_EEPROM_EECS; 1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1148 DELAY(1); 1149 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1150 DELAY(1); 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1152 DELAY(1); 1153 } 1154} 1155 1156/* 1157 * Read from the serial EEPROM. Basically, you manually shift in 1158 * the read opcode (one bit at a time) and then shift in the address, 1159 * and then you shift out the data (all of this one bit at a time). 1160 * The word size is 16 bits, so you have to provide the address for 1161 * every 16 bits of data. 1162 */ 1163static uint16_t 1164fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1165{ 1166 uint16_t reg, data; 1167 int x; 1168 1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1170 /* 1171 * Shift in read opcode. 1172 */ 1173 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1174 /* 1175 * Shift in address. 1176 */ 1177 data = 0; 1178 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1179 if (offset & x) 1180 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1181 else 1182 reg = FXP_EEPROM_EECS; 1183 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1184 DELAY(1); 1185 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1186 DELAY(1); 1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1188 DELAY(1); 1189 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1190 data++; 1191 if (autosize && reg == 0) { 1192 sc->eeprom_size = data; 1193 break; 1194 } 1195 } 1196 /* 1197 * Shift out data. 1198 */ 1199 data = 0; 1200 reg = FXP_EEPROM_EECS; 1201 for (x = 1 << 15; x; x >>= 1) { 1202 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1203 DELAY(1); 1204 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1205 data |= x; 1206 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1207 DELAY(1); 1208 } 1209 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1210 DELAY(1); 1211 1212 return (data); 1213} 1214 1215static void 1216fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1217{ 1218 int i; 1219 1220 /* 1221 * Erase/write enable. 1222 */ 1223 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1224 fxp_eeprom_shiftin(sc, 0x4, 3); 1225 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1226 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1227 DELAY(1); 1228 /* 1229 * Shift in write opcode, address, data. 1230 */ 1231 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1232 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1233 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1234 fxp_eeprom_shiftin(sc, data, 16); 1235 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1236 DELAY(1); 1237 /* 1238 * Wait for EEPROM to finish up. 1239 */ 1240 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1241 DELAY(1); 1242 for (i = 0; i < 1000; i++) { 1243 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1244 break; 1245 DELAY(50); 1246 } 1247 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1248 DELAY(1); 1249 /* 1250 * Erase/write disable. 1251 */ 1252 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1253 fxp_eeprom_shiftin(sc, 0x4, 3); 1254 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1255 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1256 DELAY(1); 1257} 1258 1259/* 1260 * From NetBSD: 1261 * 1262 * Figure out EEPROM size. 1263 * 1264 * 559's can have either 64-word or 256-word EEPROMs, the 558 1265 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1266 * talks about the existence of 16 to 256 word EEPROMs. 1267 * 1268 * The only known sizes are 64 and 256, where the 256 version is used 1269 * by CardBus cards to store CIS information. 1270 * 1271 * The address is shifted in msb-to-lsb, and after the last 1272 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1273 * after which follows the actual data. We try to detect this zero, by 1274 * probing the data-out bit in the EEPROM control register just after 1275 * having shifted in a bit. If the bit is zero, we assume we've 1276 * shifted enough address bits. The data-out should be tri-state, 1277 * before this, which should translate to a logical one. 1278 */ 1279static void 1280fxp_autosize_eeprom(struct fxp_softc *sc) 1281{ 1282 1283 /* guess maximum size of 256 words */ 1284 sc->eeprom_size = 8; 1285 1286 /* autosize */ 1287 (void) fxp_eeprom_getword(sc, 0, 1); 1288} 1289 1290static void 1291fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1292{ 1293 int i; 1294 1295 for (i = 0; i < words; i++) 1296 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1297} 1298 1299static void 1300fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1301{ 1302 int i; 1303 1304 for (i = 0; i < words; i++) 1305 fxp_eeprom_putword(sc, offset + i, data[i]); 1306} 1307 1308static void 1309fxp_load_eeprom(struct fxp_softc *sc) 1310{ 1311 int i; 1312 uint16_t cksum; 1313 1314 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size); 1315 cksum = 0; 1316 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 1317 cksum += sc->eeprom[i]; 1318 cksum = 0xBABA - cksum; 1319 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1]) 1320 device_printf(sc->dev, 1321 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n", 1322 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]); 1323} 1324 1325/* 1326 * Grab the softc lock and call the real fxp_start_body() routine 1327 */ 1328static void 1329fxp_start(if_t ifp) 1330{ 1331 struct fxp_softc *sc = if_getsoftc(ifp); 1332 1333 FXP_LOCK(sc); 1334 fxp_start_body(ifp); 1335 FXP_UNLOCK(sc); 1336} 1337 1338/* 1339 * Start packet transmission on the interface. 1340 * This routine must be called with the softc lock held, and is an 1341 * internal entry point only. 1342 */ 1343static void 1344fxp_start_body(if_t ifp) 1345{ 1346 struct fxp_softc *sc = if_getsoftc(ifp); 1347 struct mbuf *mb_head; 1348 int txqueued; 1349 1350 FXP_LOCK_ASSERT(sc, MA_OWNED); 1351 1352 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1353 IFF_DRV_RUNNING) 1354 return; 1355 1356 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1357 fxp_txeof(sc); 1358 /* 1359 * We're finished if there is nothing more to add to the list or if 1360 * we're all filled up with buffers to transmit. 1361 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1362 * a NOP command when needed. 1363 */ 1364 txqueued = 0; 1365 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) { 1366 1367 /* 1368 * Grab a packet to transmit. 1369 */ 1370 mb_head = if_dequeue(ifp); 1371 if (mb_head == NULL) 1372 break; 1373 1374 if (fxp_encap(sc, &mb_head)) { 1375 if (mb_head == NULL) 1376 break; 1377 if_sendq_prepend(ifp, mb_head); 1378 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1379 } 1380 txqueued++; 1381 /* 1382 * Pass packet to bpf if there is a listener. 1383 */ 1384 if_bpfmtap(ifp, mb_head); 1385 } 1386 1387 /* 1388 * We're finished. If we added to the list, issue a RESUME to get DMA 1389 * going again if suspended. 1390 */ 1391 if (txqueued > 0) { 1392 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1394 fxp_scb_wait(sc); 1395 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1396 /* 1397 * Set a 5 second timer just in case we don't hear 1398 * from the card again. 1399 */ 1400 sc->watchdog_timer = 5; 1401 } 1402} 1403 1404static int 1405fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1406{ 1407 if_t ifp; 1408 struct mbuf *m; 1409 struct fxp_tx *txp; 1410 struct fxp_cb_tx *cbp; 1411 struct tcphdr *tcp; 1412 bus_dma_segment_t segs[FXP_NTXSEG]; 1413 int error, i, nseg, tcp_payload; 1414 1415 FXP_LOCK_ASSERT(sc, MA_OWNED); 1416 ifp = sc->ifp; 1417 1418 tcp_payload = 0; 1419 tcp = NULL; 1420 /* 1421 * Get pointer to next available tx desc. 1422 */ 1423 txp = sc->fxp_desc.tx_last->tx_next; 1424 1425 /* 1426 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1427 * Ethernet Controller Family Open Source Software 1428 * Developer Manual says: 1429 * Using software parsing is only allowed with legal 1430 * TCP/IP or UDP/IP packets. 1431 * ... 1432 * For all other datagrams, hardware parsing must 1433 * be used. 1434 * Software parsing appears to truncate ICMP and 1435 * fragmented UDP packets that contain one to three 1436 * bytes in the second (and final) mbuf of the packet. 1437 */ 1438 if (sc->flags & FXP_FLAG_EXT_RFA) 1439 txp->tx_cb->ipcb_ip_activation_high = 1440 FXP_IPCB_HARDWAREPARSING_ENABLE; 1441 1442 m = *m_head; 1443 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1444 /* 1445 * 82550/82551 requires ethernet/IP/TCP headers must be 1446 * contained in the first active transmit buffer. 1447 */ 1448 struct ether_header *eh; 1449 struct ip *ip; 1450 uint32_t ip_off, poff; 1451 1452 if (M_WRITABLE(*m_head) == 0) { 1453 /* Get a writable copy. */ 1454 m = m_dup(*m_head, M_NOWAIT); 1455 m_freem(*m_head); 1456 if (m == NULL) { 1457 *m_head = NULL; 1458 return (ENOBUFS); 1459 } 1460 *m_head = m; 1461 } 1462 ip_off = sizeof(struct ether_header); 1463 m = m_pullup(*m_head, ip_off); 1464 if (m == NULL) { 1465 *m_head = NULL; 1466 return (ENOBUFS); 1467 } 1468 eh = mtod(m, struct ether_header *); 1469 /* Check the existence of VLAN tag. */ 1470 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1471 ip_off = sizeof(struct ether_vlan_header); 1472 m = m_pullup(m, ip_off); 1473 if (m == NULL) { 1474 *m_head = NULL; 1475 return (ENOBUFS); 1476 } 1477 } 1478 m = m_pullup(m, ip_off + sizeof(struct ip)); 1479 if (m == NULL) { 1480 *m_head = NULL; 1481 return (ENOBUFS); 1482 } 1483 ip = (struct ip *)(mtod(m, char *) + ip_off); 1484 poff = ip_off + (ip->ip_hl << 2); 1485 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1486 if (m == NULL) { 1487 *m_head = NULL; 1488 return (ENOBUFS); 1489 } 1490 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1491 m = m_pullup(m, poff + (tcp->th_off << 2)); 1492 if (m == NULL) { 1493 *m_head = NULL; 1494 return (ENOBUFS); 1495 } 1496 1497 /* 1498 * Since 82550/82551 doesn't modify IP length and pseudo 1499 * checksum in the first frame driver should compute it. 1500 */ 1501 ip = (struct ip *)(mtod(m, char *) + ip_off); 1502 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1503 ip->ip_sum = 0; 1504 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1505 (tcp->th_off << 2)); 1506 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1507 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1508 m->m_pkthdr.tso_segsz)); 1509 /* Compute total TCP payload. */ 1510 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1511 tcp_payload -= tcp->th_off << 2; 1512 *m_head = m; 1513 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1514 /* 1515 * Deal with TCP/IP checksum offload. Note that 1516 * in order for TCP checksum offload to work, 1517 * the pseudo header checksum must have already 1518 * been computed and stored in the checksum field 1519 * in the TCP header. The stack should have 1520 * already done this for us. 1521 */ 1522 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1523 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1524 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1525 1526#ifdef FXP_IP_CSUM_WAR 1527 /* 1528 * XXX The 82550 chip appears to have trouble 1529 * dealing with IP header checksums in very small 1530 * datagrams, namely fragments from 1 to 3 bytes 1531 * in size. For example, say you want to transmit 1532 * a UDP packet of 1473 bytes. The packet will be 1533 * fragmented over two IP datagrams, the latter 1534 * containing only one byte of data. The 82550 will 1535 * botch the header checksum on the 1-byte fragment. 1536 * As long as the datagram contains 4 or more bytes 1537 * of data, you're ok. 1538 * 1539 * The following code attempts to work around this 1540 * problem: if the datagram is less than 38 bytes 1541 * in size (14 bytes ether header, 20 bytes IP header, 1542 * plus 4 bytes of data), we punt and compute the IP 1543 * header checksum by hand. This workaround doesn't 1544 * work very well, however, since it can be fooled 1545 * by things like VLAN tags and IP options that make 1546 * the header sizes/offsets vary. 1547 */ 1548 1549 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1550 if (m->m_pkthdr.len < 38) { 1551 struct ip *ip; 1552 m->m_data += ETHER_HDR_LEN; 1553 ip = mtod(m, struct ip *); 1554 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1555 m->m_data -= ETHER_HDR_LEN; 1556 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1557 } else { 1558 txp->tx_cb->ipcb_ip_activation_high = 1559 FXP_IPCB_HARDWAREPARSING_ENABLE; 1560 txp->tx_cb->ipcb_ip_schedule |= 1561 FXP_IPCB_IP_CHECKSUM_ENABLE; 1562 } 1563 } 1564#endif 1565 } 1566 1567 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1568 segs, &nseg, 0); 1569 if (error == EFBIG) { 1570 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg); 1571 if (m == NULL) { 1572 m_freem(*m_head); 1573 *m_head = NULL; 1574 return (ENOMEM); 1575 } 1576 *m_head = m; 1577 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1578 *m_head, segs, &nseg, 0); 1579 if (error != 0) { 1580 m_freem(*m_head); 1581 *m_head = NULL; 1582 return (ENOMEM); 1583 } 1584 } else if (error != 0) 1585 return (error); 1586 if (nseg == 0) { 1587 m_freem(*m_head); 1588 *m_head = NULL; 1589 return (EIO); 1590 } 1591 1592 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1593 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1594 1595 cbp = txp->tx_cb; 1596 for (i = 0; i < nseg; i++) { 1597 /* 1598 * If this is an 82550/82551, then we're using extended 1599 * TxCBs _and_ we're using checksum offload. This means 1600 * that the TxCB is really an IPCB. One major difference 1601 * between the two is that with plain extended TxCBs, 1602 * the bottom half of the TxCB contains two entries from 1603 * the TBD array, whereas IPCBs contain just one entry: 1604 * one entry (8 bytes) has been sacrificed for the TCP/IP 1605 * checksum offload control bits. So to make things work 1606 * right, we have to start filling in the TBD array 1607 * starting from a different place depending on whether 1608 * the chip is an 82550/82551 or not. 1609 */ 1610 if (sc->flags & FXP_FLAG_EXT_RFA) { 1611 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1612 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1613 } else { 1614 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1615 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1616 } 1617 } 1618 if (sc->flags & FXP_FLAG_EXT_RFA) { 1619 /* Configure dynamic TBD for 82550/82551. */ 1620 cbp->tbd_number = 0xFF; 1621 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1622 } else 1623 cbp->tbd_number = nseg; 1624 /* Configure TSO. */ 1625 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1626 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1627 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1628 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1629 FXP_IPCB_IP_CHECKSUM_ENABLE | 1630 FXP_IPCB_TCP_PACKET | 1631 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1632 } 1633 /* Configure VLAN hardware tag insertion. */ 1634 if ((m->m_flags & M_VLANTAG) != 0) { 1635 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1636 txp->tx_cb->ipcb_ip_activation_high |= 1637 FXP_IPCB_INSERTVLAN_ENABLE; 1638 } 1639 1640 txp->tx_mbuf = m; 1641 txp->tx_cb->cb_status = 0; 1642 txp->tx_cb->byte_count = 0; 1643 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1644 txp->tx_cb->cb_command = 1645 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1646 FXP_CB_COMMAND_S); 1647 else 1648 txp->tx_cb->cb_command = 1649 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1650 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1651 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1652 txp->tx_cb->tx_threshold = tx_threshold; 1653 1654 /* 1655 * Advance the end of list forward. 1656 */ 1657 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1658 sc->fxp_desc.tx_last = txp; 1659 1660 /* 1661 * Advance the beginning of the list forward if there are 1662 * no other packets queued (when nothing is queued, tx_first 1663 * sits on the last TxCB that was sent out). 1664 */ 1665 if (sc->tx_queued == 0) 1666 sc->fxp_desc.tx_first = txp; 1667 1668 sc->tx_queued++; 1669 1670 return (0); 1671} 1672 1673#ifdef DEVICE_POLLING 1674static poll_handler_t fxp_poll; 1675 1676static int 1677fxp_poll(if_t ifp, enum poll_cmd cmd, int count) 1678{ 1679 struct fxp_softc *sc = if_getsoftc(ifp); 1680 uint8_t statack; 1681 int rx_npkts = 0; 1682 1683 FXP_LOCK(sc); 1684 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1685 FXP_UNLOCK(sc); 1686 return (rx_npkts); 1687 } 1688 1689 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1690 FXP_SCB_STATACK_FR; 1691 if (cmd == POLL_AND_CHECK_STATUS) { 1692 uint8_t tmp; 1693 1694 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1695 if (tmp == 0xff || tmp == 0) { 1696 FXP_UNLOCK(sc); 1697 return (rx_npkts); /* nothing to do */ 1698 } 1699 tmp &= ~statack; 1700 /* ack what we can */ 1701 if (tmp != 0) 1702 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1703 statack |= tmp; 1704 } 1705 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1706 FXP_UNLOCK(sc); 1707 return (rx_npkts); 1708} 1709#endif /* DEVICE_POLLING */ 1710 1711/* 1712 * Process interface interrupts. 1713 */ 1714static void 1715fxp_intr(void *xsc) 1716{ 1717 struct fxp_softc *sc = xsc; 1718 if_t ifp = sc->ifp; 1719 uint8_t statack; 1720 1721 FXP_LOCK(sc); 1722 if (sc->suspended) { 1723 FXP_UNLOCK(sc); 1724 return; 1725 } 1726 1727#ifdef DEVICE_POLLING 1728 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1729 FXP_UNLOCK(sc); 1730 return; 1731 } 1732#endif 1733 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1734 /* 1735 * It should not be possible to have all bits set; the 1736 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1737 * all bits are set, this may indicate that the card has 1738 * been physically ejected, so ignore it. 1739 */ 1740 if (statack == 0xff) { 1741 FXP_UNLOCK(sc); 1742 return; 1743 } 1744 1745 /* 1746 * First ACK all the interrupts in this pass. 1747 */ 1748 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1749 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1750 fxp_intr_body(sc, ifp, statack, -1); 1751 } 1752 FXP_UNLOCK(sc); 1753} 1754 1755static void 1756fxp_txeof(struct fxp_softc *sc) 1757{ 1758 if_t ifp; 1759 struct fxp_tx *txp; 1760 1761 ifp = sc->ifp; 1762 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1763 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1764 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1765 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1766 txp = txp->tx_next) { 1767 if (txp->tx_mbuf != NULL) { 1768 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1769 BUS_DMASYNC_POSTWRITE); 1770 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1771 m_freem(txp->tx_mbuf); 1772 txp->tx_mbuf = NULL; 1773 /* clear this to reset csum offload bits */ 1774 txp->tx_cb->tbd[0].tb_addr = 0; 1775 } 1776 sc->tx_queued--; 1777 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1778 } 1779 sc->fxp_desc.tx_first = txp; 1780 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1781 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1782 if (sc->tx_queued == 0) 1783 sc->watchdog_timer = 0; 1784} 1785 1786static void 1787fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m, 1788 uint16_t status, int pos) 1789{ 1790 struct ether_header *eh; 1791 struct ip *ip; 1792 struct udphdr *uh; 1793 int32_t hlen, len, pktlen, temp32; 1794 uint16_t csum, *opts; 1795 1796 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1797 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1798 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1799 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1800 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1801 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1802 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1803 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1804 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1805 CSUM_PSEUDO_HDR; 1806 m->m_pkthdr.csum_data = 0xffff; 1807 } 1808 } 1809 return; 1810 } 1811 1812 pktlen = m->m_pkthdr.len; 1813 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1814 return; 1815 eh = mtod(m, struct ether_header *); 1816 if (eh->ether_type != htons(ETHERTYPE_IP)) 1817 return; 1818 ip = (struct ip *)(eh + 1); 1819 if (ip->ip_v != IPVERSION) 1820 return; 1821 1822 hlen = ip->ip_hl << 2; 1823 pktlen -= sizeof(struct ether_header); 1824 if (hlen < sizeof(struct ip)) 1825 return; 1826 if (ntohs(ip->ip_len) < hlen) 1827 return; 1828 if (ntohs(ip->ip_len) != pktlen) 1829 return; 1830 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1831 return; /* can't handle fragmented packet */ 1832 1833 switch (ip->ip_p) { 1834 case IPPROTO_TCP: 1835 if (pktlen < (hlen + sizeof(struct tcphdr))) 1836 return; 1837 break; 1838 case IPPROTO_UDP: 1839 if (pktlen < (hlen + sizeof(struct udphdr))) 1840 return; 1841 uh = (struct udphdr *)((caddr_t)ip + hlen); 1842 if (uh->uh_sum == 0) 1843 return; /* no checksum */ 1844 break; 1845 default: 1846 return; 1847 } 1848 /* Extract computed checksum. */ 1849 csum = be16dec(mtod(m, char *) + pos); 1850 /* checksum fixup for IP options */ 1851 len = hlen - sizeof(struct ip); 1852 if (len > 0) { 1853 opts = (uint16_t *)(ip + 1); 1854 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1855 temp32 = csum - *opts; 1856 temp32 = (temp32 >> 16) + (temp32 & 65535); 1857 csum = temp32 & 65535; 1858 } 1859 } 1860 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1861 m->m_pkthdr.csum_data = csum; 1862} 1863 1864static int 1865fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack, 1866 int count) 1867{ 1868 struct mbuf *m; 1869 struct fxp_rx *rxp; 1870 struct fxp_rfa *rfa; 1871 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1872 int rx_npkts; 1873 uint16_t status; 1874 1875 rx_npkts = 0; 1876 FXP_LOCK_ASSERT(sc, MA_OWNED); 1877 1878 if (rnr) 1879 sc->rnr++; 1880#ifdef DEVICE_POLLING 1881 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1882 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1883 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1884 rnr = 1; 1885 } 1886#endif 1887 1888 /* 1889 * Free any finished transmit mbuf chains. 1890 * 1891 * Handle the CNA event likt a CXTNO event. It used to 1892 * be that this event (control unit not ready) was not 1893 * encountered, but it is now with the SMPng modifications. 1894 * The exact sequence of events that occur when the interface 1895 * is brought up are different now, and if this event 1896 * goes unhandled, the configuration/rxfilter setup sequence 1897 * can stall for several seconds. The result is that no 1898 * packets go out onto the wire for about 5 to 10 seconds 1899 * after the interface is ifconfig'ed for the first time. 1900 */ 1901 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1902 fxp_txeof(sc); 1903 1904 /* 1905 * Try to start more packets transmitting. 1906 */ 1907 if (!if_sendq_empty(ifp)) 1908 fxp_start_body(ifp); 1909 1910 /* 1911 * Just return if nothing happened on the receive side. 1912 */ 1913 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1914 return (rx_npkts); 1915 1916 /* 1917 * Process receiver interrupts. If a no-resource (RNR) 1918 * condition exists, get whatever packets we can and 1919 * re-start the receiver. 1920 * 1921 * When using polling, we do not process the list to completion, 1922 * so when we get an RNR interrupt we must defer the restart 1923 * until we hit the last buffer with the C bit set. 1924 * If we run out of cycles and rfa_headm has the C bit set, 1925 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1926 * that the info will be used in the subsequent polling cycle. 1927 */ 1928 for (;;) { 1929 rxp = sc->fxp_desc.rx_head; 1930 m = rxp->rx_mbuf; 1931 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1932 RFA_ALIGNMENT_FUDGE); 1933 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1934 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1935 1936#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1937 if (count >= 0 && count-- == 0) { 1938 if (rnr) { 1939 /* Defer RNR processing until the next time. */ 1940 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1941 rnr = 0; 1942 } 1943 break; 1944 } 1945#endif /* DEVICE_POLLING */ 1946 1947 status = le16toh(rfa->rfa_status); 1948 if ((status & FXP_RFA_STATUS_C) == 0) 1949 break; 1950 1951 if ((status & FXP_RFA_STATUS_RNR) != 0) 1952 rnr++; 1953 /* 1954 * Advance head forward. 1955 */ 1956 sc->fxp_desc.rx_head = rxp->rx_next; 1957 1958 /* 1959 * Add a new buffer to the receive chain. 1960 * If this fails, the old buffer is recycled 1961 * instead. 1962 */ 1963 if (fxp_new_rfabuf(sc, rxp) == 0) { 1964 int total_len; 1965 1966 /* 1967 * Fetch packet length (the top 2 bits of 1968 * actual_size are flags set by the controller 1969 * upon completion), and drop the packet in case 1970 * of bogus length or CRC errors. 1971 */ 1972 total_len = le16toh(rfa->actual_size) & 0x3fff; 1973 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1974 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1975 /* Adjust for appended checksum bytes. */ 1976 total_len -= 2; 1977 } 1978 if (total_len < (int)sizeof(struct ether_header) || 1979 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1980 sc->rfa_size) || 1981 status & (FXP_RFA_STATUS_CRC | 1982 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1983 m_freem(m); 1984 fxp_add_rfabuf(sc, rxp); 1985 continue; 1986 } 1987 1988 m->m_pkthdr.len = m->m_len = total_len; 1989 if_setrcvif(m, ifp); 1990 1991 /* Do IP checksum checking. */ 1992 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1993 fxp_rxcsum(sc, ifp, m, status, total_len); 1994 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1995 (status & FXP_RFA_STATUS_VLAN) != 0) { 1996 m->m_pkthdr.ether_vtag = 1997 ntohs(rfa->rfax_vlan_id); 1998 m->m_flags |= M_VLANTAG; 1999 } 2000 /* 2001 * Drop locks before calling if_input() since it 2002 * may re-enter fxp_start() in the netisr case. 2003 * This would result in a lock reversal. Better 2004 * performance might be obtained by chaining all 2005 * packets received, dropping the lock, and then 2006 * calling if_input() on each one. 2007 */ 2008 FXP_UNLOCK(sc); 2009 if_input(ifp, m); 2010 FXP_LOCK(sc); 2011 rx_npkts++; 2012 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2013 return (rx_npkts); 2014 } else { 2015 /* Reuse RFA and loaded DMA map. */ 2016 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2017 fxp_discard_rfabuf(sc, rxp); 2018 } 2019 fxp_add_rfabuf(sc, rxp); 2020 } 2021 if (rnr) { 2022 fxp_scb_wait(sc); 2023 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2024 sc->fxp_desc.rx_head->rx_addr); 2025 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2026 } 2027 return (rx_npkts); 2028} 2029 2030static void 2031fxp_update_stats(struct fxp_softc *sc) 2032{ 2033 if_t ifp = sc->ifp; 2034 struct fxp_stats *sp = sc->fxp_stats; 2035 struct fxp_hwstats *hsp; 2036 uint32_t *status; 2037 2038 FXP_LOCK_ASSERT(sc, MA_OWNED); 2039 2040 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2041 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2042 /* Update statistical counters. */ 2043 if (sc->revision >= FXP_REV_82559_A0) 2044 status = &sp->completion_status; 2045 else if (sc->revision >= FXP_REV_82558_A4) 2046 status = (uint32_t *)&sp->tx_tco; 2047 else 2048 status = &sp->tx_pause; 2049 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2050 hsp = &sc->fxp_hwstats; 2051 hsp->tx_good += le32toh(sp->tx_good); 2052 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2053 hsp->tx_latecols += le32toh(sp->tx_latecols); 2054 hsp->tx_underruns += le32toh(sp->tx_underruns); 2055 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2056 hsp->tx_deffered += le32toh(sp->tx_deffered); 2057 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2058 hsp->tx_multiple_collisions += 2059 le32toh(sp->tx_multiple_collisions); 2060 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2061 hsp->rx_good += le32toh(sp->rx_good); 2062 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2063 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2064 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2065 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2066 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2067 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2068 hsp->tx_pause += le32toh(sp->tx_pause); 2069 hsp->rx_pause += le32toh(sp->rx_pause); 2070 hsp->rx_controls += le32toh(sp->rx_controls); 2071 hsp->tx_tco += le16toh(sp->tx_tco); 2072 hsp->rx_tco += le16toh(sp->rx_tco); 2073 2074 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good)); 2075 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2076 le32toh(sp->tx_total_collisions)); 2077 if (sp->rx_good) { 2078 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 2079 le32toh(sp->rx_good)); 2080 sc->rx_idle_secs = 0; 2081 } else if (sc->flags & FXP_FLAG_RXBUG) { 2082 /* 2083 * Receiver's been idle for another second. 2084 */ 2085 sc->rx_idle_secs++; 2086 } 2087 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2088 le32toh(sp->rx_crc_errors) + 2089 le32toh(sp->rx_alignment_errors) + 2090 le32toh(sp->rx_rnr_errors) + 2091 le32toh(sp->rx_overrun_errors)); 2092 /* 2093 * If any transmit underruns occurred, bump up the transmit 2094 * threshold by another 512 bytes (64 * 8). 2095 */ 2096 if (sp->tx_underruns) { 2097 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2098 le32toh(sp->tx_underruns)); 2099 if (tx_threshold < 192) 2100 tx_threshold += 64; 2101 } 2102 *status = 0; 2103 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2104 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2105 } 2106} 2107 2108/* 2109 * Update packet in/out/collision statistics. The i82557 doesn't 2110 * allow you to access these counters without doing a fairly 2111 * expensive DMA to get _all_ of the statistics it maintains, so 2112 * we do this operation here only once per second. The statistics 2113 * counters in the kernel are updated from the previous dump-stats 2114 * DMA and then a new dump-stats DMA is started. The on-chip 2115 * counters are zeroed when the DMA completes. If we can't start 2116 * the DMA immediately, we don't wait - we just prepare to read 2117 * them again next time. 2118 */ 2119static void 2120fxp_tick(void *xsc) 2121{ 2122 struct fxp_softc *sc = xsc; 2123 if_t ifp = sc->ifp; 2124 2125 FXP_LOCK_ASSERT(sc, MA_OWNED); 2126 2127 /* Update statistical counters. */ 2128 fxp_update_stats(sc); 2129 2130 /* 2131 * Release any xmit buffers that have completed DMA. This isn't 2132 * strictly necessary to do here, but it's advantagous for mbufs 2133 * with external storage to be released in a timely manner rather 2134 * than being defered for a potentially long time. This limits 2135 * the delay to a maximum of one second. 2136 */ 2137 fxp_txeof(sc); 2138 2139 /* 2140 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2141 * then assume the receiver has locked up and attempt to clear 2142 * the condition by reprogramming the multicast filter. This is 2143 * a work-around for a bug in the 82557 where the receiver locks 2144 * up if it gets certain types of garbage in the synchronization 2145 * bits prior to the packet header. This bug is supposed to only 2146 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2147 * mode as well (perhaps due to a 10/100 speed transition). 2148 */ 2149 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2150 sc->rx_idle_secs = 0; 2151 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2152 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2153 fxp_init_body(sc, 1); 2154 } 2155 return; 2156 } 2157 /* 2158 * If there is no pending command, start another stats 2159 * dump. Otherwise punt for now. 2160 */ 2161 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2162 /* 2163 * Start another stats dump. 2164 */ 2165 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2166 } 2167 if (sc->miibus != NULL) 2168 mii_tick(device_get_softc(sc->miibus)); 2169 2170 /* 2171 * Check that chip hasn't hung. 2172 */ 2173 fxp_watchdog(sc); 2174 2175 /* 2176 * Schedule another timeout one second from now. 2177 */ 2178 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2179} 2180 2181/* 2182 * Stop the interface. Cancels the statistics updater and resets 2183 * the interface. 2184 */ 2185static void 2186fxp_stop(struct fxp_softc *sc) 2187{ 2188 if_t ifp = sc->ifp; 2189 struct fxp_tx *txp; 2190 int i; 2191 2192 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2193 sc->watchdog_timer = 0; 2194 2195 /* 2196 * Cancel stats updater. 2197 */ 2198 callout_stop(&sc->stat_ch); 2199 2200 /* 2201 * Preserve PCI configuration, configure, IA/multicast 2202 * setup and put RU and CU into idle state. 2203 */ 2204 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2205 DELAY(50); 2206 /* Disable interrupts. */ 2207 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2208 2209 fxp_update_stats(sc); 2210 2211 /* 2212 * Release any xmit buffers. 2213 */ 2214 txp = sc->fxp_desc.tx_list; 2215 if (txp != NULL) { 2216 for (i = 0; i < FXP_NTXCB; i++) { 2217 if (txp[i].tx_mbuf != NULL) { 2218 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2219 BUS_DMASYNC_POSTWRITE); 2220 bus_dmamap_unload(sc->fxp_txmtag, 2221 txp[i].tx_map); 2222 m_freem(txp[i].tx_mbuf); 2223 txp[i].tx_mbuf = NULL; 2224 /* clear this to reset csum offload bits */ 2225 txp[i].tx_cb->tbd[0].tb_addr = 0; 2226 } 2227 } 2228 } 2229 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2230 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2231 sc->tx_queued = 0; 2232} 2233 2234/* 2235 * Watchdog/transmission transmit timeout handler. Called when a 2236 * transmission is started on the interface, but no interrupt is 2237 * received before the timeout. This usually indicates that the 2238 * card has wedged for some reason. 2239 */ 2240static void 2241fxp_watchdog(struct fxp_softc *sc) 2242{ 2243 if_t ifp = sc->ifp; 2244 2245 FXP_LOCK_ASSERT(sc, MA_OWNED); 2246 2247 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2248 return; 2249 2250 device_printf(sc->dev, "device timeout\n"); 2251 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2252 2253 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2254 fxp_init_body(sc, 1); 2255} 2256 2257/* 2258 * Acquire locks and then call the real initialization function. This 2259 * is necessary because ether_ioctl() calls if_init() and this would 2260 * result in mutex recursion if the mutex was held. 2261 */ 2262static void 2263fxp_init(void *xsc) 2264{ 2265 struct fxp_softc *sc = xsc; 2266 2267 FXP_LOCK(sc); 2268 fxp_init_body(sc, 1); 2269 FXP_UNLOCK(sc); 2270} 2271 2272/* 2273 * Perform device initialization. This routine must be called with the 2274 * softc lock held. 2275 */ 2276static void 2277fxp_init_body(struct fxp_softc *sc, int setmedia) 2278{ 2279 if_t ifp = sc->ifp; 2280 struct mii_data *mii; 2281 struct fxp_cb_config *cbp; 2282 struct fxp_cb_ias *cb_ias; 2283 struct fxp_cb_tx *tcbp; 2284 struct fxp_tx *txp; 2285 int i, prm; 2286 2287 FXP_LOCK_ASSERT(sc, MA_OWNED); 2288 2289 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2290 return; 2291 2292 /* 2293 * Cancel any pending I/O 2294 */ 2295 fxp_stop(sc); 2296 2297 /* 2298 * Issue software reset, which also unloads the microcode. 2299 */ 2300 sc->flags &= ~FXP_FLAG_UCODE; 2301 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2302 DELAY(50); 2303 2304 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0; 2305 2306 /* 2307 * Initialize base of CBL and RFA memory. Loading with zero 2308 * sets it up for regular linear addressing. 2309 */ 2310 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2311 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2312 2313 fxp_scb_wait(sc); 2314 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2315 2316 /* 2317 * Initialize base of dump-stats buffer. 2318 */ 2319 fxp_scb_wait(sc); 2320 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2321 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2323 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2324 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2325 2326 /* 2327 * Attempt to load microcode if requested. 2328 * For ICH based controllers do not load microcode. 2329 */ 2330 if (sc->ident->ich == 0) { 2331 if (if_getflags(ifp) & IFF_LINK0 && 2332 (sc->flags & FXP_FLAG_UCODE) == 0) 2333 fxp_load_ucode(sc); 2334 } 2335 2336 /* 2337 * Set IFF_ALLMULTI status. It's needed in configure action 2338 * command. 2339 */ 2340 fxp_mc_addrs(sc); 2341 2342 /* 2343 * We temporarily use memory that contains the TxCB list to 2344 * construct the config CB. The TxCB list memory is rebuilt 2345 * later. 2346 */ 2347 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2348 2349 /* 2350 * This bcopy is kind of disgusting, but there are a bunch of must be 2351 * zero and must be one bits in this structure and this is the easiest 2352 * way to initialize them all to proper values. 2353 */ 2354 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2355 2356 cbp->cb_status = 0; 2357 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2358 FXP_CB_COMMAND_EL); 2359 cbp->link_addr = 0xffffffff; /* (no) next command */ 2360 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2361 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2362 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2363 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2364 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2365 cbp->type_enable = 0; /* actually reserved */ 2366 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2367 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2368 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2369 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2370 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2371 cbp->late_scb = 0; /* (don't) defer SCB update */ 2372 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2373 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2374 cbp->ci_int = 1; /* interrupt on CU idle */ 2375 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2376 cbp->ext_stats_dis = 1; /* disable extended counters */ 2377 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2378 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2379 cbp->disc_short_rx = !prm; /* discard short packets */ 2380 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2381 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2382 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2383 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2384 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2385 cbp->csma_dis = 0; /* (don't) disable link */ 2386 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2387 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0; 2388 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2389 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2390 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2391 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2392 cbp->nsai = 1; /* (don't) disable source addr insert */ 2393 cbp->preamble_length = 2; /* (7 byte) preamble */ 2394 cbp->loopback = 0; /* (don't) loopback */ 2395 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2396 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2397 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2398 cbp->promiscuous = prm; /* promiscuous mode */ 2399 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2400 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2401 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2402 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2403 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2404 2405 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2406 cbp->padding = 1; /* (do) pad short tx packets */ 2407 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2408 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2409 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2410 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2411 cbp->force_fdx = 0; /* (don't) force full duplex */ 2412 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2413 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2414 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm; 2415 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2416 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2417 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2418 2419 if (sc->revision == FXP_REV_82557) { 2420 /* 2421 * The 82557 has no hardware flow control, the values 2422 * below are the defaults for the chip. 2423 */ 2424 cbp->fc_delay_lsb = 0; 2425 cbp->fc_delay_msb = 0x40; 2426 cbp->pri_fc_thresh = 3; 2427 cbp->tx_fc_dis = 0; 2428 cbp->rx_fc_restop = 0; 2429 cbp->rx_fc_restart = 0; 2430 cbp->fc_filter = 0; 2431 cbp->pri_fc_loc = 1; 2432 } else { 2433 /* Set pause RX FIFO threshold to 1KB. */ 2434 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2435 /* Set pause time. */ 2436 cbp->fc_delay_lsb = 0xff; 2437 cbp->fc_delay_msb = 0xff; 2438 cbp->pri_fc_thresh = 3; 2439 mii = device_get_softc(sc->miibus); 2440 if ((IFM_OPTIONS(mii->mii_media_active) & 2441 IFM_ETH_TXPAUSE) != 0) 2442 /* enable transmit FC */ 2443 cbp->tx_fc_dis = 0; 2444 else 2445 /* disable transmit FC */ 2446 cbp->tx_fc_dis = 1; 2447 if ((IFM_OPTIONS(mii->mii_media_active) & 2448 IFM_ETH_RXPAUSE) != 0) { 2449 /* enable FC restart/restop frames */ 2450 cbp->rx_fc_restart = 1; 2451 cbp->rx_fc_restop = 1; 2452 } else { 2453 /* disable FC restart/restop frames */ 2454 cbp->rx_fc_restart = 0; 2455 cbp->rx_fc_restop = 0; 2456 } 2457 cbp->fc_filter = !prm; /* drop FC frames to host */ 2458 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2459 } 2460 2461 /* Enable 82558 and 82559 extended statistics functionality. */ 2462 if (sc->revision >= FXP_REV_82558_A4) { 2463 if (sc->revision >= FXP_REV_82559_A0) { 2464 /* 2465 * Extend configuration table size to 32 2466 * to include TCO configuration. 2467 */ 2468 cbp->byte_count = 32; 2469 cbp->ext_stats_dis = 1; 2470 /* Enable TCO stats. */ 2471 cbp->tno_int_or_tco_en = 1; 2472 cbp->gamla_rx = 1; 2473 } else 2474 cbp->ext_stats_dis = 0; 2475 } 2476 2477 /* 2478 * Start the config command/DMA. 2479 */ 2480 fxp_scb_wait(sc); 2481 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2482 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2483 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2484 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2485 /* ...and wait for it to complete. */ 2486 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2487 2488 /* 2489 * Now initialize the station address. Temporarily use the TxCB 2490 * memory area like we did above for the config CB. 2491 */ 2492 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2493 cb_ias->cb_status = 0; 2494 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2495 cb_ias->link_addr = 0xffffffff; 2496 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2497 2498 /* 2499 * Start the IAS (Individual Address Setup) command/DMA. 2500 */ 2501 fxp_scb_wait(sc); 2502 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2503 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2504 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2505 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2506 /* ...and wait for it to complete. */ 2507 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2508 2509 /* 2510 * Initialize the multicast address list. 2511 */ 2512 fxp_mc_setup(sc); 2513 2514 /* 2515 * Initialize transmit control block (TxCB) list. 2516 */ 2517 txp = sc->fxp_desc.tx_list; 2518 tcbp = sc->fxp_desc.cbl_list; 2519 bzero(tcbp, FXP_TXCB_SZ); 2520 for (i = 0; i < FXP_NTXCB; i++) { 2521 txp[i].tx_mbuf = NULL; 2522 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2523 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2524 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2525 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2526 if (sc->flags & FXP_FLAG_EXT_TXCB) 2527 tcbp[i].tbd_array_addr = 2528 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2529 else 2530 tcbp[i].tbd_array_addr = 2531 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2532 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2533 } 2534 /* 2535 * Set the suspend flag on the first TxCB and start the control 2536 * unit. It will execute the NOP and then suspend. 2537 */ 2538 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2539 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2540 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2541 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2542 sc->tx_queued = 1; 2543 2544 fxp_scb_wait(sc); 2545 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2546 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2547 2548 /* 2549 * Initialize receiver buffer area - RFA. 2550 */ 2551 fxp_scb_wait(sc); 2552 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2553 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2554 2555 if (sc->miibus != NULL && setmedia != 0) 2556 mii_mediachg(device_get_softc(sc->miibus)); 2557 2558 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2559 2560 /* 2561 * Enable interrupts. 2562 */ 2563#ifdef DEVICE_POLLING 2564 /* 2565 * ... but only do that if we are not polling. And because (presumably) 2566 * the default is interrupts on, we need to disable them explicitly! 2567 */ 2568 if (if_getcapenable(ifp) & IFCAP_POLLING ) 2569 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2570 else 2571#endif /* DEVICE_POLLING */ 2572 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2573 2574 /* 2575 * Start stats updater. 2576 */ 2577 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2578} 2579 2580static int 2581fxp_serial_ifmedia_upd(if_t ifp) 2582{ 2583 2584 return (0); 2585} 2586 2587static void 2588fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2589{ 2590 2591 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2592} 2593 2594/* 2595 * Change media according to request. 2596 */ 2597static int 2598fxp_ifmedia_upd(if_t ifp) 2599{ 2600 struct fxp_softc *sc = if_getsoftc(ifp); 2601 struct mii_data *mii; 2602 struct mii_softc *miisc; 2603 2604 mii = device_get_softc(sc->miibus); 2605 FXP_LOCK(sc); 2606 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2607 PHY_RESET(miisc); 2608 mii_mediachg(mii); 2609 FXP_UNLOCK(sc); 2610 return (0); 2611} 2612 2613/* 2614 * Notify the world which media we're using. 2615 */ 2616static void 2617fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2618{ 2619 struct fxp_softc *sc = if_getsoftc(ifp); 2620 struct mii_data *mii; 2621 2622 mii = device_get_softc(sc->miibus); 2623 FXP_LOCK(sc); 2624 mii_pollstat(mii); 2625 ifmr->ifm_active = mii->mii_media_active; 2626 ifmr->ifm_status = mii->mii_media_status; 2627 FXP_UNLOCK(sc); 2628} 2629 2630/* 2631 * Add a buffer to the end of the RFA buffer list. 2632 * Return 0 if successful, 1 for failure. A failure results in 2633 * reusing the RFA buffer. 2634 * The RFA struct is stuck at the beginning of mbuf cluster and the 2635 * data pointer is fixed up to point just past it. 2636 */ 2637static int 2638fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2639{ 2640 struct mbuf *m; 2641 struct fxp_rfa *rfa; 2642 bus_dmamap_t tmp_map; 2643 int error; 2644 2645 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2646 if (m == NULL) 2647 return (ENOBUFS); 2648 2649 /* 2650 * Move the data pointer up so that the incoming data packet 2651 * will be 32-bit aligned. 2652 */ 2653 m->m_data += RFA_ALIGNMENT_FUDGE; 2654 2655 /* 2656 * Get a pointer to the base of the mbuf cluster and move 2657 * data start past it. 2658 */ 2659 rfa = mtod(m, struct fxp_rfa *); 2660 m->m_data += sc->rfa_size; 2661 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2662 2663 rfa->rfa_status = 0; 2664 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2665 rfa->actual_size = 0; 2666 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2667 sc->rfa_size; 2668 2669 /* 2670 * Initialize the rest of the RFA. Note that since the RFA 2671 * is misaligned, we cannot store values directly. We're thus 2672 * using the le32enc() function which handles endianness and 2673 * is also alignment-safe. 2674 */ 2675 le32enc(&rfa->link_addr, 0xffffffff); 2676 le32enc(&rfa->rbd_addr, 0xffffffff); 2677 2678 /* Map the RFA into DMA memory. */ 2679 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2680 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2681 &rxp->rx_addr, BUS_DMA_NOWAIT); 2682 if (error) { 2683 m_freem(m); 2684 return (error); 2685 } 2686 2687 if (rxp->rx_mbuf != NULL) 2688 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2689 tmp_map = sc->spare_map; 2690 sc->spare_map = rxp->rx_map; 2691 rxp->rx_map = tmp_map; 2692 rxp->rx_mbuf = m; 2693 2694 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2695 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2696 return (0); 2697} 2698 2699static void 2700fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2701{ 2702 struct fxp_rfa *p_rfa; 2703 struct fxp_rx *p_rx; 2704 2705 /* 2706 * If there are other buffers already on the list, attach this 2707 * one to the end by fixing up the tail to point to this one. 2708 */ 2709 if (sc->fxp_desc.rx_head != NULL) { 2710 p_rx = sc->fxp_desc.rx_tail; 2711 p_rfa = (struct fxp_rfa *) 2712 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2713 p_rx->rx_next = rxp; 2714 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2715 p_rfa->rfa_control = 0; 2716 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2718 } else { 2719 rxp->rx_next = NULL; 2720 sc->fxp_desc.rx_head = rxp; 2721 } 2722 sc->fxp_desc.rx_tail = rxp; 2723} 2724 2725static void 2726fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2727{ 2728 struct mbuf *m; 2729 struct fxp_rfa *rfa; 2730 2731 m = rxp->rx_mbuf; 2732 m->m_data = m->m_ext.ext_buf; 2733 /* 2734 * Move the data pointer up so that the incoming data packet 2735 * will be 32-bit aligned. 2736 */ 2737 m->m_data += RFA_ALIGNMENT_FUDGE; 2738 2739 /* 2740 * Get a pointer to the base of the mbuf cluster and move 2741 * data start past it. 2742 */ 2743 rfa = mtod(m, struct fxp_rfa *); 2744 m->m_data += sc->rfa_size; 2745 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2746 2747 rfa->rfa_status = 0; 2748 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2749 rfa->actual_size = 0; 2750 2751 /* 2752 * Initialize the rest of the RFA. Note that since the RFA 2753 * is misaligned, we cannot store values directly. We're thus 2754 * using the le32enc() function which handles endianness and 2755 * is also alignment-safe. 2756 */ 2757 le32enc(&rfa->link_addr, 0xffffffff); 2758 le32enc(&rfa->rbd_addr, 0xffffffff); 2759 2760 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2761 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2762} 2763 2764static int 2765fxp_miibus_readreg(device_t dev, int phy, int reg) 2766{ 2767 struct fxp_softc *sc = device_get_softc(dev); 2768 int count = 10000; 2769 int value; 2770 2771 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2772 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2773 2774 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2775 && count--) 2776 DELAY(10); 2777 2778 if (count <= 0) 2779 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2780 2781 return (value & 0xffff); 2782} 2783 2784static int 2785fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2786{ 2787 struct fxp_softc *sc = device_get_softc(dev); 2788 int count = 10000; 2789 2790 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2791 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2792 (value & 0xffff)); 2793 2794 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2795 count--) 2796 DELAY(10); 2797 2798 if (count <= 0) 2799 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2800 return (0); 2801} 2802 2803static void 2804fxp_miibus_statchg(device_t dev) 2805{ 2806 struct fxp_softc *sc; 2807 struct mii_data *mii; 2808 if_t ifp; 2809 2810 sc = device_get_softc(dev); 2811 mii = device_get_softc(sc->miibus); 2812 ifp = sc->ifp; 2813 if (mii == NULL || ifp == (void *)NULL || 2814 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 2815 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2816 (IFM_AVALID | IFM_ACTIVE)) 2817 return; 2818 2819 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T && 2820 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2821 sc->cu_resume_bug = 1; 2822 else 2823 sc->cu_resume_bug = 0; 2824 /* 2825 * Call fxp_init_body in order to adjust the flow control settings. 2826 * Note that the 82557 doesn't support hardware flow control. 2827 */ 2828 if (sc->revision == FXP_REV_82557) 2829 return; 2830 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2831 fxp_init_body(sc, 0); 2832} 2833 2834static int 2835fxp_ioctl(if_t ifp, u_long command, caddr_t data) 2836{ 2837 struct fxp_softc *sc = if_getsoftc(ifp); 2838 struct ifreq *ifr = (struct ifreq *)data; 2839 struct mii_data *mii; 2840 int flag, mask, error = 0, reinit; 2841 2842 switch (command) { 2843 case SIOCSIFFLAGS: 2844 FXP_LOCK(sc); 2845 /* 2846 * If interface is marked up and not running, then start it. 2847 * If it is marked down and running, stop it. 2848 * XXX If it's up then re-initialize it. This is so flags 2849 * such as IFF_PROMISC are handled. 2850 */ 2851 if (if_getflags(ifp) & IFF_UP) { 2852 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) && 2853 ((if_getflags(ifp) ^ sc->if_flags) & 2854 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) { 2855 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2856 fxp_init_body(sc, 0); 2857 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2858 fxp_init_body(sc, 1); 2859 } else { 2860 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2861 fxp_stop(sc); 2862 } 2863 sc->if_flags = if_getflags(ifp); 2864 FXP_UNLOCK(sc); 2865 break; 2866 2867 case SIOCADDMULTI: 2868 case SIOCDELMULTI: 2869 FXP_LOCK(sc); 2870 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2871 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2872 fxp_init_body(sc, 0); 2873 } 2874 FXP_UNLOCK(sc); 2875 break; 2876 2877 case SIOCSIFMEDIA: 2878 case SIOCGIFMEDIA: 2879 if (sc->miibus != NULL) { 2880 mii = device_get_softc(sc->miibus); 2881 error = ifmedia_ioctl(ifp, ifr, 2882 &mii->mii_media, command); 2883 } else { 2884 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2885 } 2886 break; 2887 2888 case SIOCSIFCAP: 2889 reinit = 0; 2890 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 2891#ifdef DEVICE_POLLING 2892 if (mask & IFCAP_POLLING) { 2893 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2894 error = ether_poll_register(fxp_poll, ifp); 2895 if (error) 2896 return(error); 2897 FXP_LOCK(sc); 2898 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2899 FXP_SCB_INTR_DISABLE); 2900 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2901 FXP_UNLOCK(sc); 2902 } else { 2903 error = ether_poll_deregister(ifp); 2904 /* Enable interrupts in any case */ 2905 FXP_LOCK(sc); 2906 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2907 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2908 FXP_UNLOCK(sc); 2909 } 2910 } 2911#endif 2912 FXP_LOCK(sc); 2913 if ((mask & IFCAP_TXCSUM) != 0 && 2914 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2915 if_togglecapenable(ifp, IFCAP_TXCSUM); 2916 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2917 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0); 2918 else 2919 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES); 2920 } 2921 if ((mask & IFCAP_RXCSUM) != 0 && 2922 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 2923 if_togglecapenable(ifp, IFCAP_RXCSUM); 2924 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2925 reinit++; 2926 } 2927 if ((mask & IFCAP_TSO4) != 0 && 2928 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2929 if_togglecapenable(ifp, IFCAP_TSO4); 2930 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2931 if_sethwassistbits(ifp, CSUM_TSO, 0); 2932 else 2933 if_sethwassistbits(ifp, 0, CSUM_TSO); 2934 } 2935 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2936 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2937 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2938 if ((mask & IFCAP_VLAN_MTU) != 0 && 2939 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) { 2940 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2941 if (sc->revision != FXP_REV_82557) 2942 flag = FXP_FLAG_LONG_PKT_EN; 2943 else /* a hack to get long frames on the old chip */ 2944 flag = FXP_FLAG_SAVE_BAD; 2945 sc->flags ^= flag; 2946 if (if_getflags(ifp) & IFF_UP) 2947 reinit++; 2948 } 2949 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2950 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2951 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2952 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2953 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2954 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2955 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2956 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2957 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2958 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2959 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO | 2960 IFCAP_VLAN_HWCSUM); 2961 reinit++; 2962 } 2963 if (reinit > 0 && 2964 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2965 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2966 fxp_init_body(sc, 0); 2967 } 2968 FXP_UNLOCK(sc); 2969 if_vlancap(ifp); 2970 break; 2971 2972 default: 2973 error = ether_ioctl(ifp, command, data); 2974 } 2975 return (error); 2976} 2977 2978/* 2979 * Fill in the multicast address list and return number of entries. 2980 */ 2981static int 2982fxp_mc_addrs(struct fxp_softc *sc) 2983{ 2984 struct fxp_cb_mcs *mcsp = sc->mcsp; 2985 if_t ifp = sc->ifp; 2986 int nmcasts = 0; 2987 2988 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) { 2989 if_maddr_rlock(ifp); 2990 if_setupmultiaddr(ifp, mcsp->mc_addr, &nmcasts, MAXMCADDR); 2991 if (nmcasts >= MAXMCADDR) { 2992 if_setflagbits(ifp, IFF_ALLMULTI, 0); 2993 nmcasts = 0; 2994 } 2995 if_maddr_runlock(ifp); 2996 } 2997 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2998 return (nmcasts); 2999} 3000 3001/* 3002 * Program the multicast filter. 3003 * 3004 * We have an artificial restriction that the multicast setup command 3005 * must be the first command in the chain, so we take steps to ensure 3006 * this. By requiring this, it allows us to keep up the performance of 3007 * the pre-initialized command ring (esp. link pointers) by not actually 3008 * inserting the mcsetup command in the ring - i.e. its link pointer 3009 * points to the TxCB ring, but the mcsetup descriptor itself is not part 3010 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 3011 * lead into the regular TxCB ring when it completes. 3012 */ 3013static void 3014fxp_mc_setup(struct fxp_softc *sc) 3015{ 3016 struct fxp_cb_mcs *mcsp; 3017 int count; 3018 3019 FXP_LOCK_ASSERT(sc, MA_OWNED); 3020 3021 mcsp = sc->mcsp; 3022 mcsp->cb_status = 0; 3023 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 3024 mcsp->link_addr = 0xffffffff; 3025 fxp_mc_addrs(sc); 3026 3027 /* 3028 * Wait until command unit is idle. This should never be the 3029 * case when nothing is queued, but make sure anyway. 3030 */ 3031 count = 100; 3032 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 3033 FXP_SCB_CUS_IDLE && --count) 3034 DELAY(10); 3035 if (count == 0) { 3036 device_printf(sc->dev, "command queue timeout\n"); 3037 return; 3038 } 3039 3040 /* 3041 * Start the multicast setup command. 3042 */ 3043 fxp_scb_wait(sc); 3044 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3046 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3047 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3048 /* ...and wait for it to complete. */ 3049 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3050} 3051 3052static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3053static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3054static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3055static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3056static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3057static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3058static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3059 3060#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3061 3062static const struct ucode { 3063 uint32_t revision; 3064 uint32_t *ucode; 3065 int length; 3066 u_short int_delay_offset; 3067 u_short bundle_max_offset; 3068} ucode_table[] = { 3069 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3070 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3071 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3072 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3073 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3074 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3075 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3076 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3077 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3078 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3079 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3080 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3081 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 3082 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3083 { 0, NULL, 0, 0, 0 } 3084}; 3085 3086static void 3087fxp_load_ucode(struct fxp_softc *sc) 3088{ 3089 const struct ucode *uc; 3090 struct fxp_cb_ucode *cbp; 3091 int i; 3092 3093 if (sc->flags & FXP_FLAG_NO_UCODE) 3094 return; 3095 3096 for (uc = ucode_table; uc->ucode != NULL; uc++) 3097 if (sc->revision == uc->revision) 3098 break; 3099 if (uc->ucode == NULL) 3100 return; 3101 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3102 cbp->cb_status = 0; 3103 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3104 cbp->link_addr = 0xffffffff; /* (no) next command */ 3105 for (i = 0; i < uc->length; i++) 3106 cbp->ucode[i] = htole32(uc->ucode[i]); 3107 if (uc->int_delay_offset) 3108 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3109 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3110 if (uc->bundle_max_offset) 3111 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3112 htole16(sc->tunable_bundle_max); 3113 /* 3114 * Download the ucode to the chip. 3115 */ 3116 fxp_scb_wait(sc); 3117 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3118 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3119 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3120 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3121 /* ...and wait for it to complete. */ 3122 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3123 device_printf(sc->dev, 3124 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3125 sc->tunable_int_delay, 3126 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3127 sc->flags |= FXP_FLAG_UCODE; 3128 bzero(cbp, FXP_TXCB_SZ); 3129} 3130 3131#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3132 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3133 3134static void 3135fxp_sysctl_node(struct fxp_softc *sc) 3136{ 3137 struct sysctl_ctx_list *ctx; 3138 struct sysctl_oid_list *child, *parent; 3139 struct sysctl_oid *tree; 3140 struct fxp_hwstats *hsp; 3141 3142 ctx = device_get_sysctl_ctx(sc->dev); 3143 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3144 3145 SYSCTL_ADD_PROC(ctx, child, 3146 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 3147 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3148 "FXP driver receive interrupt microcode bundling delay"); 3149 SYSCTL_ADD_PROC(ctx, child, 3150 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 3151 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3152 "FXP driver receive interrupt microcode bundle size limit"); 3153 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3154 "FXP RNR events"); 3155 3156 /* 3157 * Pull in device tunables. 3158 */ 3159 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3160 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3161 (void) resource_int_value(device_get_name(sc->dev), 3162 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3163 (void) resource_int_value(device_get_name(sc->dev), 3164 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3165 sc->rnr = 0; 3166 3167 hsp = &sc->fxp_hwstats; 3168 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3169 NULL, "FXP statistics"); 3170 parent = SYSCTL_CHILDREN(tree); 3171 3172 /* Rx MAC statistics. */ 3173 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3174 NULL, "Rx MAC statistics"); 3175 child = SYSCTL_CHILDREN(tree); 3176 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3177 &hsp->rx_good, "Good frames"); 3178 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3179 &hsp->rx_crc_errors, "CRC errors"); 3180 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3181 &hsp->rx_alignment_errors, "Alignment errors"); 3182 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3183 &hsp->rx_rnr_errors, "RNR errors"); 3184 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3185 &hsp->rx_overrun_errors, "Overrun errors"); 3186 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3187 &hsp->rx_cdt_errors, "Collision detect errors"); 3188 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3189 &hsp->rx_shortframes, "Short frame errors"); 3190 if (sc->revision >= FXP_REV_82558_A4) { 3191 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3192 &hsp->rx_pause, "Pause frames"); 3193 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3194 &hsp->rx_controls, "Unsupported control frames"); 3195 } 3196 if (sc->revision >= FXP_REV_82559_A0) 3197 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3198 &hsp->rx_tco, "TCO frames"); 3199 3200 /* Tx MAC statistics. */ 3201 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3202 NULL, "Tx MAC statistics"); 3203 child = SYSCTL_CHILDREN(tree); 3204 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3205 &hsp->tx_good, "Good frames"); 3206 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3207 &hsp->tx_maxcols, "Maximum collisions errors"); 3208 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3209 &hsp->tx_latecols, "Late collisions errors"); 3210 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3211 &hsp->tx_underruns, "Underrun errors"); 3212 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3213 &hsp->tx_lostcrs, "Lost carrier sense"); 3214 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3215 &hsp->tx_deffered, "Deferred"); 3216 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3217 &hsp->tx_single_collisions, "Single collisions"); 3218 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3219 &hsp->tx_multiple_collisions, "Multiple collisions"); 3220 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3221 &hsp->tx_total_collisions, "Total collisions"); 3222 if (sc->revision >= FXP_REV_82558_A4) 3223 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3224 &hsp->tx_pause, "Pause frames"); 3225 if (sc->revision >= FXP_REV_82559_A0) 3226 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3227 &hsp->tx_tco, "TCO frames"); 3228} 3229 3230#undef FXP_SYSCTL_STAT_ADD 3231 3232static int 3233sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3234{ 3235 int error, value; 3236 3237 value = *(int *)arg1; 3238 error = sysctl_handle_int(oidp, &value, 0, req); 3239 if (error || !req->newptr) 3240 return (error); 3241 if (value < low || value > high) 3242 return (EINVAL); 3243 *(int *)arg1 = value; 3244 return (0); 3245} 3246 3247/* 3248 * Interrupt delay is expressed in microseconds, a multiplier is used 3249 * to convert this to the appropriate clock ticks before using. 3250 */ 3251static int 3252sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3253{ 3254 3255 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3256} 3257 3258static int 3259sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3260{ 3261 3262 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3263} 3264