if_fxp.c revision 87972
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 87972 2001-12-15 02:41:52Z peter $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/sysctl.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <net/ethernet.h> 61#include <net/if_arp.h> 62 63#include <vm/vm.h> /* for vtophys */ 64#include <vm/pmap.h> /* for vtophys */ 65#include <machine/clock.h> /* for DELAY */ 66 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73#include <dev/mii/mii.h> 74#include <dev/mii/miivar.h> 75 76#include <dev/fxp/if_fxpreg.h> 77#include <dev/fxp/if_fxpvar.h> 78#include <dev/fxp/rcvbundl.h> 79 80MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81#include "miibus_if.h" 82 83/* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92#define RFA_ALIGNMENT_FUDGE 2 93 94/* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99static int tx_threshold = 64; 100 101/* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135}; 136 137struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140}; 141 142/* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0, NULL }, 163}; 164 165static int fxp_probe(device_t dev); 166static int fxp_attach(device_t dev); 167static int fxp_detach(device_t dev); 168static int fxp_shutdown(device_t dev); 169static int fxp_suspend(device_t dev); 170static int fxp_resume(device_t dev); 171 172static void fxp_intr(void *xsc); 173static void fxp_init(void *xsc); 174static void fxp_tick(void *xsc); 175static void fxp_powerstate_d0(device_t dev); 176static void fxp_start(struct ifnet *ifp); 177static void fxp_stop(struct fxp_softc *sc); 178static void fxp_release(struct fxp_softc *sc); 179static int fxp_ioctl(struct ifnet *ifp, u_long command, 180 caddr_t data); 181static void fxp_watchdog(struct ifnet *ifp); 182static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 183static void fxp_mc_setup(struct fxp_softc *sc); 184static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 185 int autosize); 186static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 187 u_int16_t data); 188static void fxp_autosize_eeprom(struct fxp_softc *sc); 189static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 190 int offset, int words); 191static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 192 int offset, int words); 193static int fxp_ifmedia_upd(struct ifnet *ifp); 194static void fxp_ifmedia_sts(struct ifnet *ifp, 195 struct ifmediareq *ifmr); 196static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 197static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 198 struct ifmediareq *ifmr); 199static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 200static void fxp_miibus_writereg(device_t dev, int phy, int reg, 201 int value); 202static void fxp_load_ucode(struct fxp_softc *sc); 203static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 204 int low, int high); 205static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 206static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 207static __inline void fxp_lwcopy(volatile u_int32_t *src, 208 volatile u_int32_t *dst); 209static __inline void fxp_scb_wait(struct fxp_softc *sc); 210static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 211static __inline void fxp_dma_wait(volatile u_int16_t *status, 212 struct fxp_softc *sc); 213 214static device_method_t fxp_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, fxp_probe), 217 DEVMETHOD(device_attach, fxp_attach), 218 DEVMETHOD(device_detach, fxp_detach), 219 DEVMETHOD(device_shutdown, fxp_shutdown), 220 DEVMETHOD(device_suspend, fxp_suspend), 221 DEVMETHOD(device_resume, fxp_resume), 222 223 /* MII interface */ 224 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 225 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 226 227 { 0, 0 } 228}; 229 230static driver_t fxp_driver = { 231 "fxp", 232 fxp_methods, 233 sizeof(struct fxp_softc), 234}; 235 236static devclass_t fxp_devclass; 237 238DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 239DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 240DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 241 242/* 243 * Inline function to copy a 16-bit aligned 32-bit quantity. 244 */ 245static __inline void 246fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 247{ 248#ifdef __i386__ 249 *dst = *src; 250#else 251 volatile u_int16_t *a = (volatile u_int16_t *)src; 252 volatile u_int16_t *b = (volatile u_int16_t *)dst; 253 254 b[0] = a[0]; 255 b[1] = a[1]; 256#endif 257} 258 259/* 260 * Wait for the previous command to be accepted (but not necessarily 261 * completed). 262 */ 263static __inline void 264fxp_scb_wait(struct fxp_softc *sc) 265{ 266 int i = 10000; 267 268 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 269 DELAY(2); 270 if (i == 0) 271 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 272 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 273 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 274 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 275 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 276} 277 278static __inline void 279fxp_scb_cmd(struct fxp_softc *sc, int cmd) 280{ 281 282 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 283 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 284 fxp_scb_wait(sc); 285 } 286 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 287} 288 289static __inline void 290fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 291{ 292 int i = 10000; 293 294 while (!(*status & FXP_CB_STATUS_C) && --i) 295 DELAY(2); 296 if (i == 0) 297 device_printf(sc->dev, "DMA timeout\n"); 298} 299 300/* 301 * Return identification string if this is device is ours. 302 */ 303static int 304fxp_probe(device_t dev) 305{ 306 u_int16_t devid; 307 struct fxp_ident *ident; 308 309 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 310 devid = pci_get_device(dev); 311 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 312 if (ident->devid == devid) { 313 device_set_desc(dev, ident->name); 314 return (0); 315 } 316 } 317 } 318 return (ENXIO); 319} 320 321static void 322fxp_powerstate_d0(device_t dev) 323{ 324#if __FreeBSD_version >= 430002 325 u_int32_t iobase, membase, irq; 326 327 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 328 /* Save important PCI config data. */ 329 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 330 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 331 irq = pci_read_config(dev, PCIR_INTLINE, 4); 332 333 /* Reset the power state. */ 334 device_printf(dev, "chip is in D%d power mode " 335 "-- setting to D0\n", pci_get_powerstate(dev)); 336 337 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 338 339 /* Restore PCI config data. */ 340 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 341 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 342 pci_write_config(dev, PCIR_INTLINE, irq, 4); 343 } 344#endif 345} 346 347static int 348fxp_attach(device_t dev) 349{ 350 int error = 0; 351 struct fxp_softc *sc = device_get_softc(dev); 352 struct ifnet *ifp; 353 u_int32_t val; 354 u_int16_t data; 355 int i, rid, m1, m2, prefer_iomap; 356 int s; 357 358 bzero(sc, sizeof(*sc)); 359 sc->dev = dev; 360 callout_handle_init(&sc->stat_ch); 361 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 362 363 s = splimp(); 364 365 /* 366 * Enable bus mastering. Enable memory space too, in case 367 * BIOS/Prom forgot about it. 368 */ 369 val = pci_read_config(dev, PCIR_COMMAND, 2); 370 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 371 pci_write_config(dev, PCIR_COMMAND, val, 2); 372 val = pci_read_config(dev, PCIR_COMMAND, 2); 373 374 fxp_powerstate_d0(dev); 375 376 /* 377 * Figure out which we should try first - memory mapping or i/o mapping? 378 * We default to memory mapping. Then we accept an override from the 379 * command line. Then we check to see which one is enabled. 380 */ 381 m1 = PCIM_CMD_MEMEN; 382 m2 = PCIM_CMD_PORTEN; 383 prefer_iomap = 0; 384 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 385 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 386 m1 = PCIM_CMD_PORTEN; 387 m2 = PCIM_CMD_MEMEN; 388 } 389 390 if (val & m1) { 391 sc->rtp = 392 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 393 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 394 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 395 0, ~0, 1, RF_ACTIVE); 396 } 397 if (sc->mem == NULL && (val & m2)) { 398 sc->rtp = 399 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 400 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 401 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 402 0, ~0, 1, RF_ACTIVE); 403 } 404 405 if (!sc->mem) { 406 device_printf(dev, "could not map device registers\n"); 407 error = ENXIO; 408 goto fail; 409 } 410 if (bootverbose) { 411 device_printf(dev, "using %s space register mapping\n", 412 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 413 } 414 415 sc->sc_st = rman_get_bustag(sc->mem); 416 sc->sc_sh = rman_get_bushandle(sc->mem); 417 418 /* 419 * Allocate our interrupt. 420 */ 421 rid = 0; 422 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 423 RF_SHAREABLE | RF_ACTIVE); 424 if (sc->irq == NULL) { 425 device_printf(dev, "could not map interrupt\n"); 426 error = ENXIO; 427 goto fail; 428 } 429 430 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 431 fxp_intr, sc, &sc->ih); 432 if (error) { 433 device_printf(dev, "could not setup irq\n"); 434 goto fail; 435 } 436 437 /* 438 * Reset to a stable state. 439 */ 440 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 441 DELAY(10); 442 443 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 444 M_DEVBUF, M_NOWAIT | M_ZERO); 445 if (sc->cbl_base == NULL) 446 goto failmem; 447 448 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 449 M_NOWAIT | M_ZERO); 450 if (sc->fxp_stats == NULL) 451 goto failmem; 452 453 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 454 if (sc->mcsp == NULL) 455 goto failmem; 456 457 /* 458 * Pre-allocate our receive buffers. 459 */ 460 for (i = 0; i < FXP_NRFABUFS; i++) { 461 if (fxp_add_rfabuf(sc, NULL) != 0) { 462 goto failmem; 463 } 464 } 465 466 /* 467 * Find out how large of an SEEPROM we have. 468 */ 469 fxp_autosize_eeprom(sc); 470 471 /* 472 * Determine whether we must use the 503 serial interface. 473 */ 474 fxp_read_eeprom(sc, &data, 6, 1); 475 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 476 (data & FXP_PHY_SERIAL_ONLY)) 477 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 478 479 /* 480 * Create the sysctl tree 481 */ 482 sysctl_ctx_init(&sc->sysctl_ctx); 483 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 484 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 485 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 486 if (sc->sysctl_tree == NULL) 487 goto fail; 488 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 489 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 490 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 491 "FXP driver receive interrupt microcode bundling delay"); 492 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 493 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 494 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 495 "FXP driver receive interrupt microcode bundle size limit"); 496 497 /* 498 * Pull in device tunables. 499 */ 500 sc->tunable_int_delay = TUNABLE_INT_DELAY; 501 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 502 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 503 "int_delay", &sc->tunable_int_delay); 504 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 505 "bundle_max", &sc->tunable_bundle_max); 506 507 /* 508 * Find out the chip revision; lump all 82557 revs together. 509 */ 510 fxp_read_eeprom(sc, &data, 5, 1); 511 if ((data >> 8) == 1) 512 sc->revision = FXP_REV_82557; 513 else 514 sc->revision = pci_get_revid(dev); 515 516 /* 517 * Enable workarounds for certain chip revision deficiencies. 518 * 519 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 520 * some systems based a normal 82559 design, have a defect where 521 * the chip can cause a PCI protocol violation if it receives 522 * a CU_RESUME command when it is entering the IDLE state. The 523 * workaround is to disable Dynamic Standby Mode, so the chip never 524 * deasserts CLKRUN#, and always remains in an active state. 525 * 526 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 527 */ 528 i = pci_get_device(dev); 529 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 530 sc->revision >= FXP_REV_82559_A0) { 531 fxp_read_eeprom(sc, &data, 10, 1); 532 if (data & 0x02) { /* STB enable */ 533 u_int16_t cksum; 534 int i; 535 536 device_printf(dev, 537 "Disabling dynamic standby mode in EEPROM\n"); 538 data &= ~0x02; 539 fxp_write_eeprom(sc, &data, 10, 1); 540 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 541 cksum = 0; 542 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 543 fxp_read_eeprom(sc, &data, i, 1); 544 cksum += data; 545 } 546 i = (1 << sc->eeprom_size) - 1; 547 cksum = 0xBABA - cksum; 548 fxp_read_eeprom(sc, &data, i, 1); 549 fxp_write_eeprom(sc, &cksum, i, 1); 550 device_printf(dev, 551 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 552 i, data, cksum); 553#if 1 554 /* 555 * If the user elects to continue, try the software 556 * workaround, as it is better than nothing. 557 */ 558 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 559#endif 560 } 561 } 562 563 /* 564 * If we are not a 82557 chip, we can enable extended features. 565 */ 566 if (sc->revision != FXP_REV_82557) { 567 /* 568 * If MWI is enabled in the PCI configuration, and there 569 * is a valid cacheline size (8 or 16 dwords), then tell 570 * the board to turn on MWI. 571 */ 572 if (val & PCIM_CMD_MWRICEN && 573 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 574 sc->flags |= FXP_FLAG_MWI_ENABLE; 575 576 /* turn on the extended TxCB feature */ 577 sc->flags |= FXP_FLAG_EXT_TXCB; 578 579 /* enable reception of long frames for VLAN */ 580 sc->flags |= FXP_FLAG_LONG_PKT_EN; 581 } 582 583 /* 584 * Read MAC address. 585 */ 586 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 587 device_printf(dev, "Ethernet address %6D%s\n", 588 sc->arpcom.ac_enaddr, ":", 589 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 590 if (bootverbose) { 591 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 592 pci_get_vendor(dev), pci_get_device(dev), 593 pci_get_subvendor(dev), pci_get_subdevice(dev), 594 pci_get_revid(dev)); 595 fxp_read_eeprom(sc, &data, 10, 1); 596 device_printf(dev, "Dynamic Standby mode is %s\n", 597 data & 0x02 ? "enabled" : "disabled"); 598 } 599 600 /* 601 * If this is only a 10Mbps device, then there is no MII, and 602 * the PHY will use a serial interface instead. 603 * 604 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 605 * doesn't have a programming interface of any sort. The 606 * media is sensed automatically based on how the link partner 607 * is configured. This is, in essence, manual configuration. 608 */ 609 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 610 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 611 fxp_serial_ifmedia_sts); 612 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 613 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 614 } else { 615 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 616 fxp_ifmedia_sts)) { 617 device_printf(dev, "MII without any PHY!\n"); 618 error = ENXIO; 619 goto fail; 620 } 621 } 622 623 ifp = &sc->arpcom.ac_if; 624 ifp->if_unit = device_get_unit(dev); 625 ifp->if_name = "fxp"; 626 ifp->if_output = ether_output; 627 ifp->if_baudrate = 100000000; 628 ifp->if_init = fxp_init; 629 ifp->if_softc = sc; 630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 631 ifp->if_ioctl = fxp_ioctl; 632 ifp->if_start = fxp_start; 633 ifp->if_watchdog = fxp_watchdog; 634 635 /* 636 * Attach the interface. 637 */ 638 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 639 640 /* 641 * Tell the upper layer(s) we support long frames. 642 */ 643 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 644 645 /* 646 * Let the system queue as many packets as we have available 647 * TX descriptors. 648 */ 649 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 650 651 splx(s); 652 return (0); 653 654failmem: 655 device_printf(dev, "Failed to malloc memory\n"); 656 error = ENOMEM; 657fail: 658 splx(s); 659 fxp_release(sc); 660 return (error); 661} 662 663/* 664 * release all resources 665 */ 666static void 667fxp_release(struct fxp_softc *sc) 668{ 669 670 bus_generic_detach(sc->dev); 671 if (sc->miibus) 672 device_delete_child(sc->dev, sc->miibus); 673 674 if (sc->cbl_base) 675 free(sc->cbl_base, M_DEVBUF); 676 if (sc->fxp_stats) 677 free(sc->fxp_stats, M_DEVBUF); 678 if (sc->mcsp) 679 free(sc->mcsp, M_DEVBUF); 680 if (sc->rfa_headm) 681 m_freem(sc->rfa_headm); 682 683 if (sc->ih) 684 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 685 if (sc->irq) 686 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 687 if (sc->mem) 688 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 689 690 sysctl_ctx_free(&sc->sysctl_ctx); 691 692 mtx_destroy(&sc->sc_mtx); 693} 694 695/* 696 * Detach interface. 697 */ 698static int 699fxp_detach(device_t dev) 700{ 701 struct fxp_softc *sc = device_get_softc(dev); 702 int s; 703 704 /* disable interrupts */ 705 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 706 707 s = splimp(); 708 709 /* 710 * Stop DMA and drop transmit queue. 711 */ 712 fxp_stop(sc); 713 714 /* 715 * Close down routes etc. 716 */ 717 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 718 719 /* 720 * Free all media structures. 721 */ 722 ifmedia_removeall(&sc->sc_media); 723 724 splx(s); 725 726 /* Release our allocated resources. */ 727 fxp_release(sc); 728 729 return (0); 730} 731 732/* 733 * Device shutdown routine. Called at system shutdown after sync. The 734 * main purpose of this routine is to shut off receiver DMA so that 735 * kernel memory doesn't get clobbered during warmboot. 736 */ 737static int 738fxp_shutdown(device_t dev) 739{ 740 /* 741 * Make sure that DMA is disabled prior to reboot. Not doing 742 * do could allow DMA to corrupt kernel memory during the 743 * reboot before the driver initializes. 744 */ 745 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 746 return (0); 747} 748 749/* 750 * Device suspend routine. Stop the interface and save some PCI 751 * settings in case the BIOS doesn't restore them properly on 752 * resume. 753 */ 754static int 755fxp_suspend(device_t dev) 756{ 757 struct fxp_softc *sc = device_get_softc(dev); 758 int i, s; 759 760 s = splimp(); 761 762 fxp_stop(sc); 763 764 for (i = 0; i < 5; i++) 765 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 766 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 767 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 768 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 769 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 770 771 sc->suspended = 1; 772 773 splx(s); 774 return (0); 775} 776 777/* 778 * Device resume routine. Restore some PCI settings in case the BIOS 779 * doesn't, re-enable busmastering, and restart the interface if 780 * appropriate. 781 */ 782static int 783fxp_resume(device_t dev) 784{ 785 struct fxp_softc *sc = device_get_softc(dev); 786 struct ifnet *ifp = &sc->sc_if; 787 u_int16_t pci_command; 788 int i, s; 789 790 s = splimp(); 791 792 fxp_powerstate_d0(dev); 793 794 /* better way to do this? */ 795 for (i = 0; i < 5; i++) 796 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 797 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 798 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 799 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 800 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 801 802 /* reenable busmastering */ 803 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 804 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 805 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 806 807 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 808 DELAY(10); 809 810 /* reinitialize interface if necessary */ 811 if (ifp->if_flags & IFF_UP) 812 fxp_init(sc); 813 814 sc->suspended = 0; 815 816 splx(s); 817 return (0); 818} 819 820static void 821fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 822{ 823 u_int16_t reg; 824 int x; 825 826 /* 827 * Shift in data. 828 */ 829 for (x = 1 << (length - 1); x; x >>= 1) { 830 if (data & x) 831 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 832 else 833 reg = FXP_EEPROM_EECS; 834 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 835 DELAY(1); 836 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 837 DELAY(1); 838 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 839 DELAY(1); 840 } 841} 842 843/* 844 * Read from the serial EEPROM. Basically, you manually shift in 845 * the read opcode (one bit at a time) and then shift in the address, 846 * and then you shift out the data (all of this one bit at a time). 847 * The word size is 16 bits, so you have to provide the address for 848 * every 16 bits of data. 849 */ 850static u_int16_t 851fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 852{ 853 u_int16_t reg, data; 854 int x; 855 856 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 857 /* 858 * Shift in read opcode. 859 */ 860 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 861 /* 862 * Shift in address. 863 */ 864 data = 0; 865 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 866 if (offset & x) 867 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 868 else 869 reg = FXP_EEPROM_EECS; 870 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 871 DELAY(1); 872 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 873 DELAY(1); 874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 875 DELAY(1); 876 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 877 data++; 878 if (autosize && reg == 0) { 879 sc->eeprom_size = data; 880 break; 881 } 882 } 883 /* 884 * Shift out data. 885 */ 886 data = 0; 887 reg = FXP_EEPROM_EECS; 888 for (x = 1 << 15; x; x >>= 1) { 889 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 890 DELAY(1); 891 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 892 data |= x; 893 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 894 DELAY(1); 895 } 896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 897 DELAY(1); 898 899 return (data); 900} 901 902static void 903fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 904{ 905 int i; 906 907 /* 908 * Erase/write enable. 909 */ 910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 911 fxp_eeprom_shiftin(sc, 0x4, 3); 912 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 913 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 914 DELAY(1); 915 /* 916 * Shift in write opcode, address, data. 917 */ 918 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 919 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 920 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 921 fxp_eeprom_shiftin(sc, data, 16); 922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 923 DELAY(1); 924 /* 925 * Wait for EEPROM to finish up. 926 */ 927 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 928 DELAY(1); 929 for (i = 0; i < 1000; i++) { 930 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 931 break; 932 DELAY(50); 933 } 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 935 DELAY(1); 936 /* 937 * Erase/write disable. 938 */ 939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 940 fxp_eeprom_shiftin(sc, 0x4, 3); 941 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 943 DELAY(1); 944} 945 946/* 947 * From NetBSD: 948 * 949 * Figure out EEPROM size. 950 * 951 * 559's can have either 64-word or 256-word EEPROMs, the 558 952 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 953 * talks about the existance of 16 to 256 word EEPROMs. 954 * 955 * The only known sizes are 64 and 256, where the 256 version is used 956 * by CardBus cards to store CIS information. 957 * 958 * The address is shifted in msb-to-lsb, and after the last 959 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 960 * after which follows the actual data. We try to detect this zero, by 961 * probing the data-out bit in the EEPROM control register just after 962 * having shifted in a bit. If the bit is zero, we assume we've 963 * shifted enough address bits. The data-out should be tri-state, 964 * before this, which should translate to a logical one. 965 */ 966static void 967fxp_autosize_eeprom(struct fxp_softc *sc) 968{ 969 970 /* guess maximum size of 256 words */ 971 sc->eeprom_size = 8; 972 973 /* autosize */ 974 (void) fxp_eeprom_getword(sc, 0, 1); 975} 976 977static void 978fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 979{ 980 int i; 981 982 for (i = 0; i < words; i++) 983 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 984} 985 986static void 987fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 988{ 989 int i; 990 991 for (i = 0; i < words; i++) 992 fxp_eeprom_putword(sc, offset + i, data[i]); 993} 994 995/* 996 * Start packet transmission on the interface. 997 */ 998static void 999fxp_start(struct ifnet *ifp) 1000{ 1001 struct fxp_softc *sc = ifp->if_softc; 1002 struct fxp_cb_tx *txp; 1003 1004 /* 1005 * See if we need to suspend xmit until the multicast filter 1006 * has been reprogrammed (which can only be done at the head 1007 * of the command chain). 1008 */ 1009 if (sc->need_mcsetup) { 1010 return; 1011 } 1012 1013 txp = NULL; 1014 1015 /* 1016 * We're finished if there is nothing more to add to the list or if 1017 * we're all filled up with buffers to transmit. 1018 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1019 * a NOP command when needed. 1020 */ 1021 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1022 struct mbuf *m, *mb_head; 1023 int segment; 1024 1025 /* 1026 * Grab a packet to transmit. 1027 */ 1028 IF_DEQUEUE(&ifp->if_snd, mb_head); 1029 1030 /* 1031 * Get pointer to next available tx desc. 1032 */ 1033 txp = sc->cbl_last->next; 1034 1035 /* 1036 * Go through each of the mbufs in the chain and initialize 1037 * the transmit buffer descriptors with the physical address 1038 * and size of the mbuf. 1039 */ 1040tbdinit: 1041 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1042 if (m->m_len != 0) { 1043 if (segment == FXP_NTXSEG) 1044 break; 1045 txp->tbd[segment].tb_addr = 1046 vtophys(mtod(m, vm_offset_t)); 1047 txp->tbd[segment].tb_size = m->m_len; 1048 segment++; 1049 } 1050 } 1051 if (m != NULL) { 1052 struct mbuf *mn; 1053 1054 /* 1055 * We ran out of segments. We have to recopy this 1056 * mbuf chain first. Bail out if we can't get the 1057 * new buffers. 1058 */ 1059 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1060 if (mn == NULL) { 1061 m_freem(mb_head); 1062 break; 1063 } 1064 if (mb_head->m_pkthdr.len > MHLEN) { 1065 MCLGET(mn, M_DONTWAIT); 1066 if ((mn->m_flags & M_EXT) == 0) { 1067 m_freem(mn); 1068 m_freem(mb_head); 1069 break; 1070 } 1071 } 1072 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1073 mtod(mn, caddr_t)); 1074 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1075 m_freem(mb_head); 1076 mb_head = mn; 1077 goto tbdinit; 1078 } 1079 1080 txp->tbd_number = segment; 1081 txp->mb_head = mb_head; 1082 txp->cb_status = 0; 1083 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1084 txp->cb_command = 1085 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1086 FXP_CB_COMMAND_S; 1087 } else { 1088 txp->cb_command = 1089 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1090 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1091 /* 1092 * Set a 5 second timer just in case we don't hear 1093 * from the card again. 1094 */ 1095 ifp->if_timer = 5; 1096 } 1097 txp->tx_threshold = tx_threshold; 1098 1099 /* 1100 * Advance the end of list forward. 1101 */ 1102 1103#ifdef __alpha__ 1104 /* 1105 * On platforms which can't access memory in 16-bit 1106 * granularities, we must prevent the card from DMA'ing 1107 * up the status while we update the command field. 1108 * This could cause us to overwrite the completion status. 1109 */ 1110 atomic_clear_short(&sc->cbl_last->cb_command, 1111 FXP_CB_COMMAND_S); 1112#else 1113 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1114#endif /*__alpha__*/ 1115 sc->cbl_last = txp; 1116 1117 /* 1118 * Advance the beginning of the list forward if there are 1119 * no other packets queued (when nothing is queued, cbl_first 1120 * sits on the last TxCB that was sent out). 1121 */ 1122 if (sc->tx_queued == 0) 1123 sc->cbl_first = txp; 1124 1125 sc->tx_queued++; 1126 1127 /* 1128 * Pass packet to bpf if there is a listener. 1129 */ 1130 if (ifp->if_bpf) 1131 bpf_mtap(ifp, mb_head); 1132 } 1133 1134 /* 1135 * We're finished. If we added to the list, issue a RESUME to get DMA 1136 * going again if suspended. 1137 */ 1138 if (txp != NULL) { 1139 fxp_scb_wait(sc); 1140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1141 } 1142} 1143 1144static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1145 1146#ifdef DEVICE_POLLING 1147static poll_handler_t fxp_poll; 1148 1149static void 1150fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1151{ 1152 struct fxp_softc *sc = ifp->if_softc; 1153 u_int8_t statack; 1154 1155 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1156 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1157 return; 1158 } 1159 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1160 FXP_SCB_STATACK_FR; 1161 if (cmd == POLL_AND_CHECK_STATUS) { 1162 u_int8_t tmp; 1163 1164 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1165 if (tmp == 0xff || tmp == 0) 1166 return; /* nothing to do */ 1167 tmp &= ~statack; 1168 /* ack what we can */ 1169 if (tmp != 0) 1170 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1171 statack |= tmp; 1172 } 1173 fxp_intr_body(sc, statack, count); 1174} 1175#endif /* DEVICE_POLLING */ 1176 1177/* 1178 * Process interface interrupts. 1179 */ 1180static void 1181fxp_intr(void *xsc) 1182{ 1183 struct fxp_softc *sc = xsc; 1184 u_int8_t statack; 1185 1186#ifdef DEVICE_POLLING 1187 struct ifnet *ifp = &sc->sc_if; 1188 1189 if (ifp->if_ipending & IFF_POLLING) 1190 return; 1191 if (ether_poll_register(fxp_poll, ifp)) { 1192 /* disable interrupts */ 1193 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1194 fxp_poll(ifp, 0, 1); 1195 return; 1196 } 1197#endif 1198 1199 if (sc->suspended) { 1200 return; 1201 } 1202 1203 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1204 /* 1205 * It should not be possible to have all bits set; the 1206 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1207 * all bits are set, this may indicate that the card has 1208 * been physically ejected, so ignore it. 1209 */ 1210 if (statack == 0xff) 1211 return; 1212 1213 /* 1214 * First ACK all the interrupts in this pass. 1215 */ 1216 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1217 fxp_intr_body(sc, statack, -1); 1218 } 1219} 1220 1221static void 1222fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1223{ 1224 struct ifnet *ifp = &sc->sc_if; 1225 1226 /* 1227 * Free any finished transmit mbuf chains. 1228 * 1229 * Handle the CNA event likt a CXTNO event. It used to 1230 * be that this event (control unit not ready) was not 1231 * encountered, but it is now with the SMPng modifications. 1232 * The exact sequence of events that occur when the interface 1233 * is brought up are different now, and if this event 1234 * goes unhandled, the configuration/rxfilter setup sequence 1235 * can stall for several seconds. The result is that no 1236 * packets go out onto the wire for about 5 to 10 seconds 1237 * after the interface is ifconfig'ed for the first time. 1238 */ 1239 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1240 struct fxp_cb_tx *txp; 1241 1242 for (txp = sc->cbl_first; sc->tx_queued && 1243 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1244 txp = txp->next) { 1245 if (txp->mb_head != NULL) { 1246 m_freem(txp->mb_head); 1247 txp->mb_head = NULL; 1248 } 1249 sc->tx_queued--; 1250 } 1251 sc->cbl_first = txp; 1252 ifp->if_timer = 0; 1253 if (sc->tx_queued == 0) { 1254 if (sc->need_mcsetup) 1255 fxp_mc_setup(sc); 1256 } 1257 /* 1258 * Try to start more packets transmitting. 1259 */ 1260 if (ifp->if_snd.ifq_head != NULL) 1261 fxp_start(ifp); 1262 } 1263 /* 1264 * Process receiver interrupts. If a no-resource (RNR) 1265 * condition exists, get whatever packets we can and 1266 * re-start the receiver. 1267 */ 1268 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1269 struct mbuf *m; 1270 struct fxp_rfa *rfa; 1271rcvloop: 1272 m = sc->rfa_headm; 1273 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1274 RFA_ALIGNMENT_FUDGE); 1275 1276#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1277 if (count < 0 || count-- > 0) 1278#endif 1279 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1280 /* 1281 * Remove first packet from the chain. 1282 */ 1283 sc->rfa_headm = m->m_next; 1284 m->m_next = NULL; 1285 1286 /* 1287 * Add a new buffer to the receive chain. 1288 * If this fails, the old buffer is recycled 1289 * instead. 1290 */ 1291 if (fxp_add_rfabuf(sc, m) == 0) { 1292 struct ether_header *eh; 1293 int total_len; 1294 1295 total_len = rfa->actual_size & 1296 (MCLBYTES - 1); 1297 if (total_len < 1298 sizeof(struct ether_header)) { 1299 m_freem(m); 1300 goto rcvloop; 1301 } 1302 1303 /* 1304 * Drop the packet if it has CRC 1305 * errors. This test is only needed 1306 * when doing 802.1q VLAN on the 82557 1307 * chip. 1308 */ 1309 if (rfa->rfa_status & 1310 FXP_RFA_STATUS_CRC) { 1311 m_freem(m); 1312 goto rcvloop; 1313 } 1314 1315 m->m_pkthdr.rcvif = ifp; 1316 m->m_pkthdr.len = m->m_len = total_len; 1317 eh = mtod(m, struct ether_header *); 1318 m->m_data += 1319 sizeof(struct ether_header); 1320 m->m_len -= 1321 sizeof(struct ether_header); 1322 m->m_pkthdr.len = m->m_len; 1323 ether_input(ifp, eh, m); 1324 } 1325 goto rcvloop; 1326 } 1327 if (statack & FXP_SCB_STATACK_RNR) { 1328 fxp_scb_wait(sc); 1329 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1330 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1331 RFA_ALIGNMENT_FUDGE); 1332 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1333 } 1334 } 1335} 1336 1337/* 1338 * Update packet in/out/collision statistics. The i82557 doesn't 1339 * allow you to access these counters without doing a fairly 1340 * expensive DMA to get _all_ of the statistics it maintains, so 1341 * we do this operation here only once per second. The statistics 1342 * counters in the kernel are updated from the previous dump-stats 1343 * DMA and then a new dump-stats DMA is started. The on-chip 1344 * counters are zeroed when the DMA completes. If we can't start 1345 * the DMA immediately, we don't wait - we just prepare to read 1346 * them again next time. 1347 */ 1348static void 1349fxp_tick(void *xsc) 1350{ 1351 struct fxp_softc *sc = xsc; 1352 struct ifnet *ifp = &sc->sc_if; 1353 struct fxp_stats *sp = sc->fxp_stats; 1354 struct fxp_cb_tx *txp; 1355 int s; 1356 1357 ifp->if_opackets += sp->tx_good; 1358 ifp->if_collisions += sp->tx_total_collisions; 1359 if (sp->rx_good) { 1360 ifp->if_ipackets += sp->rx_good; 1361 sc->rx_idle_secs = 0; 1362 } else { 1363 /* 1364 * Receiver's been idle for another second. 1365 */ 1366 sc->rx_idle_secs++; 1367 } 1368 ifp->if_ierrors += 1369 sp->rx_crc_errors + 1370 sp->rx_alignment_errors + 1371 sp->rx_rnr_errors + 1372 sp->rx_overrun_errors; 1373 /* 1374 * If any transmit underruns occured, bump up the transmit 1375 * threshold by another 512 bytes (64 * 8). 1376 */ 1377 if (sp->tx_underruns) { 1378 ifp->if_oerrors += sp->tx_underruns; 1379 if (tx_threshold < 192) 1380 tx_threshold += 64; 1381 } 1382 s = splimp(); 1383 /* 1384 * Release any xmit buffers that have completed DMA. This isn't 1385 * strictly necessary to do here, but it's advantagous for mbufs 1386 * with external storage to be released in a timely manner rather 1387 * than being defered for a potentially long time. This limits 1388 * the delay to a maximum of one second. 1389 */ 1390 for (txp = sc->cbl_first; sc->tx_queued && 1391 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1392 txp = txp->next) { 1393 if (txp->mb_head != NULL) { 1394 m_freem(txp->mb_head); 1395 txp->mb_head = NULL; 1396 } 1397 sc->tx_queued--; 1398 } 1399 sc->cbl_first = txp; 1400 /* 1401 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1402 * then assume the receiver has locked up and attempt to clear 1403 * the condition by reprogramming the multicast filter. This is 1404 * a work-around for a bug in the 82557 where the receiver locks 1405 * up if it gets certain types of garbage in the syncronization 1406 * bits prior to the packet header. This bug is supposed to only 1407 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1408 * mode as well (perhaps due to a 10/100 speed transition). 1409 */ 1410 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1411 sc->rx_idle_secs = 0; 1412 fxp_mc_setup(sc); 1413 } 1414 /* 1415 * If there is no pending command, start another stats 1416 * dump. Otherwise punt for now. 1417 */ 1418 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1419 /* 1420 * Start another stats dump. 1421 */ 1422 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1423 } else { 1424 /* 1425 * A previous command is still waiting to be accepted. 1426 * Just zero our copy of the stats and wait for the 1427 * next timer event to update them. 1428 */ 1429 sp->tx_good = 0; 1430 sp->tx_underruns = 0; 1431 sp->tx_total_collisions = 0; 1432 1433 sp->rx_good = 0; 1434 sp->rx_crc_errors = 0; 1435 sp->rx_alignment_errors = 0; 1436 sp->rx_rnr_errors = 0; 1437 sp->rx_overrun_errors = 0; 1438 } 1439 if (sc->miibus != NULL) 1440 mii_tick(device_get_softc(sc->miibus)); 1441 splx(s); 1442 /* 1443 * Schedule another timeout one second from now. 1444 */ 1445 sc->stat_ch = timeout(fxp_tick, sc, hz); 1446} 1447 1448/* 1449 * Stop the interface. Cancels the statistics updater and resets 1450 * the interface. 1451 */ 1452static void 1453fxp_stop(struct fxp_softc *sc) 1454{ 1455 struct ifnet *ifp = &sc->sc_if; 1456 struct fxp_cb_tx *txp; 1457 int i; 1458 1459 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1460 ifp->if_timer = 0; 1461 1462#ifdef DEVICE_POLLING 1463 ether_poll_deregister(ifp); 1464#endif 1465 /* 1466 * Cancel stats updater. 1467 */ 1468 untimeout(fxp_tick, sc, sc->stat_ch); 1469 1470 /* 1471 * Issue software reset, which also unloads the microcode. 1472 */ 1473 sc->flags &= ~FXP_FLAG_UCODE; 1474 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1475 DELAY(50); 1476 1477 /* 1478 * Release any xmit buffers. 1479 */ 1480 txp = sc->cbl_base; 1481 if (txp != NULL) { 1482 for (i = 0; i < FXP_NTXCB; i++) { 1483 if (txp[i].mb_head != NULL) { 1484 m_freem(txp[i].mb_head); 1485 txp[i].mb_head = NULL; 1486 } 1487 } 1488 } 1489 sc->tx_queued = 0; 1490 1491 /* 1492 * Free all the receive buffers then reallocate/reinitialize 1493 */ 1494 if (sc->rfa_headm != NULL) 1495 m_freem(sc->rfa_headm); 1496 sc->rfa_headm = NULL; 1497 sc->rfa_tailm = NULL; 1498 for (i = 0; i < FXP_NRFABUFS; i++) { 1499 if (fxp_add_rfabuf(sc, NULL) != 0) { 1500 /* 1501 * This "can't happen" - we're at splimp() 1502 * and we just freed all the buffers we need 1503 * above. 1504 */ 1505 panic("fxp_stop: no buffers!"); 1506 } 1507 } 1508} 1509 1510/* 1511 * Watchdog/transmission transmit timeout handler. Called when a 1512 * transmission is started on the interface, but no interrupt is 1513 * received before the timeout. This usually indicates that the 1514 * card has wedged for some reason. 1515 */ 1516static void 1517fxp_watchdog(struct ifnet *ifp) 1518{ 1519 struct fxp_softc *sc = ifp->if_softc; 1520 1521 device_printf(sc->dev, "device timeout\n"); 1522 ifp->if_oerrors++; 1523 1524 fxp_init(sc); 1525} 1526 1527static void 1528fxp_init(void *xsc) 1529{ 1530 struct fxp_softc *sc = xsc; 1531 struct ifnet *ifp = &sc->sc_if; 1532 struct fxp_cb_config *cbp; 1533 struct fxp_cb_ias *cb_ias; 1534 struct fxp_cb_tx *txp; 1535 int i, prm, s; 1536 1537 s = splimp(); 1538 /* 1539 * Cancel any pending I/O 1540 */ 1541 fxp_stop(sc); 1542 1543 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1544 1545 /* 1546 * Initialize base of CBL and RFA memory. Loading with zero 1547 * sets it up for regular linear addressing. 1548 */ 1549 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1550 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1551 1552 fxp_scb_wait(sc); 1553 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1554 1555 /* 1556 * Initialize base of dump-stats buffer. 1557 */ 1558 fxp_scb_wait(sc); 1559 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1560 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1561 1562 /* 1563 * Attempt to load microcode if requested. 1564 */ 1565 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1566 fxp_load_ucode(sc); 1567 1568 /* 1569 * We temporarily use memory that contains the TxCB list to 1570 * construct the config CB. The TxCB list memory is rebuilt 1571 * later. 1572 */ 1573 cbp = (struct fxp_cb_config *) sc->cbl_base; 1574 1575 /* 1576 * This bcopy is kind of disgusting, but there are a bunch of must be 1577 * zero and must be one bits in this structure and this is the easiest 1578 * way to initialize them all to proper values. 1579 */ 1580 bcopy(fxp_cb_config_template, 1581 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1582 sizeof(fxp_cb_config_template)); 1583 1584 cbp->cb_status = 0; 1585 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1586 cbp->link_addr = -1; /* (no) next command */ 1587 cbp->byte_count = 22; /* (22) bytes to config */ 1588 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1589 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1590 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1591 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1592 cbp->type_enable = 0; /* actually reserved */ 1593 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1594 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1595 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1596 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1597 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1598 cbp->late_scb = 0; /* (don't) defer SCB update */ 1599 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1600 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1601 cbp->ci_int = 1; /* interrupt on CU idle */ 1602 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1603 cbp->ext_stats_dis = 1; /* disable extended counters */ 1604 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1605 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1606 cbp->disc_short_rx = !prm; /* discard short packets */ 1607 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1608 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1609 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1610 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1611 cbp->csma_dis = 0; /* (don't) disable link */ 1612 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1613 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1614 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1615 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1616 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1617 cbp->nsai = 1; /* (don't) disable source addr insert */ 1618 cbp->preamble_length = 2; /* (7 byte) preamble */ 1619 cbp->loopback = 0; /* (don't) loopback */ 1620 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1621 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1622 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1623 cbp->promiscuous = prm; /* promiscuous mode */ 1624 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1625 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1626 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1627 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1628 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1629 1630 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1631 cbp->padding = 1; /* (do) pad short tx packets */ 1632 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1633 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1634 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1635 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1636 /* must set wake_en in PMCSR also */ 1637 cbp->force_fdx = 0; /* (don't) force full duplex */ 1638 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1639 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1640 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1641 1642 if (sc->revision == FXP_REV_82557) { 1643 /* 1644 * The 82557 has no hardware flow control, the values 1645 * below are the defaults for the chip. 1646 */ 1647 cbp->fc_delay_lsb = 0; 1648 cbp->fc_delay_msb = 0x40; 1649 cbp->pri_fc_thresh = 3; 1650 cbp->tx_fc_dis = 0; 1651 cbp->rx_fc_restop = 0; 1652 cbp->rx_fc_restart = 0; 1653 cbp->fc_filter = 0; 1654 cbp->pri_fc_loc = 1; 1655 } else { 1656 cbp->fc_delay_lsb = 0x1f; 1657 cbp->fc_delay_msb = 0x01; 1658 cbp->pri_fc_thresh = 3; 1659 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1660 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1661 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1662 cbp->fc_filter = !prm; /* drop FC frames to host */ 1663 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1664 } 1665 1666 /* 1667 * Start the config command/DMA. 1668 */ 1669 fxp_scb_wait(sc); 1670 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1671 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1672 /* ...and wait for it to complete. */ 1673 fxp_dma_wait(&cbp->cb_status, sc); 1674 1675 /* 1676 * Now initialize the station address. Temporarily use the TxCB 1677 * memory area like we did above for the config CB. 1678 */ 1679 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1680 cb_ias->cb_status = 0; 1681 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1682 cb_ias->link_addr = -1; 1683 bcopy(sc->arpcom.ac_enaddr, 1684 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1685 sizeof(sc->arpcom.ac_enaddr)); 1686 1687 /* 1688 * Start the IAS (Individual Address Setup) command/DMA. 1689 */ 1690 fxp_scb_wait(sc); 1691 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1692 /* ...and wait for it to complete. */ 1693 fxp_dma_wait(&cb_ias->cb_status, sc); 1694 1695 /* 1696 * Initialize transmit control block (TxCB) list. 1697 */ 1698 1699 txp = sc->cbl_base; 1700 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1701 for (i = 0; i < FXP_NTXCB; i++) { 1702 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1703 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1704 txp[i].link_addr = 1705 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1706 if (sc->flags & FXP_FLAG_EXT_TXCB) 1707 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1708 else 1709 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1710 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1711 } 1712 /* 1713 * Set the suspend flag on the first TxCB and start the control 1714 * unit. It will execute the NOP and then suspend. 1715 */ 1716 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1717 sc->cbl_first = sc->cbl_last = txp; 1718 sc->tx_queued = 1; 1719 1720 fxp_scb_wait(sc); 1721 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1722 1723 /* 1724 * Initialize receiver buffer area - RFA. 1725 */ 1726 fxp_scb_wait(sc); 1727 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1728 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1729 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1730 1731 /* 1732 * Set current media. 1733 */ 1734 if (sc->miibus != NULL) 1735 mii_mediachg(device_get_softc(sc->miibus)); 1736 1737 ifp->if_flags |= IFF_RUNNING; 1738 ifp->if_flags &= ~IFF_OACTIVE; 1739 1740 /* 1741 * Enable interrupts. 1742 */ 1743 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1744 splx(s); 1745 1746 /* 1747 * Start stats updater. 1748 */ 1749 sc->stat_ch = timeout(fxp_tick, sc, hz); 1750} 1751 1752static int 1753fxp_serial_ifmedia_upd(struct ifnet *ifp) 1754{ 1755 1756 return (0); 1757} 1758 1759static void 1760fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1761{ 1762 1763 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1764} 1765 1766/* 1767 * Change media according to request. 1768 */ 1769static int 1770fxp_ifmedia_upd(struct ifnet *ifp) 1771{ 1772 struct fxp_softc *sc = ifp->if_softc; 1773 struct mii_data *mii; 1774 1775 mii = device_get_softc(sc->miibus); 1776 mii_mediachg(mii); 1777 return (0); 1778} 1779 1780/* 1781 * Notify the world which media we're using. 1782 */ 1783static void 1784fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1785{ 1786 struct fxp_softc *sc = ifp->if_softc; 1787 struct mii_data *mii; 1788 1789 mii = device_get_softc(sc->miibus); 1790 mii_pollstat(mii); 1791 ifmr->ifm_active = mii->mii_media_active; 1792 ifmr->ifm_status = mii->mii_media_status; 1793 1794 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1795 sc->cu_resume_bug = 1; 1796 else 1797 sc->cu_resume_bug = 0; 1798} 1799 1800/* 1801 * Add a buffer to the end of the RFA buffer list. 1802 * Return 0 if successful, 1 for failure. A failure results in 1803 * adding the 'oldm' (if non-NULL) on to the end of the list - 1804 * tossing out its old contents and recycling it. 1805 * The RFA struct is stuck at the beginning of mbuf cluster and the 1806 * data pointer is fixed up to point just past it. 1807 */ 1808static int 1809fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1810{ 1811 u_int32_t v; 1812 struct mbuf *m; 1813 struct fxp_rfa *rfa, *p_rfa; 1814 1815 MGETHDR(m, M_DONTWAIT, MT_DATA); 1816 if (m != NULL) { 1817 MCLGET(m, M_DONTWAIT); 1818 if ((m->m_flags & M_EXT) == 0) { 1819 device_printf(sc->dev, 1820 "cluster allocation failed, packet dropped!\n"); 1821 m_freem(m); 1822 if (oldm == NULL) 1823 return 1; 1824 m = oldm; 1825 m->m_data = m->m_ext.ext_buf; 1826 } 1827 } else { 1828 device_printf(sc->dev, 1829 "mbuf allocation failed, packet dropped!\n"); 1830 if (oldm == NULL) 1831 return 1; 1832 m = oldm; 1833 m->m_data = m->m_ext.ext_buf; 1834 } 1835 1836 /* 1837 * Move the data pointer up so that the incoming data packet 1838 * will be 32-bit aligned. 1839 */ 1840 m->m_data += RFA_ALIGNMENT_FUDGE; 1841 1842 /* 1843 * Get a pointer to the base of the mbuf cluster and move 1844 * data start past it. 1845 */ 1846 rfa = mtod(m, struct fxp_rfa *); 1847 m->m_data += sizeof(struct fxp_rfa); 1848 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1849 1850 /* 1851 * Initialize the rest of the RFA. Note that since the RFA 1852 * is misaligned, we cannot store values directly. Instead, 1853 * we use an optimized, inline copy. 1854 */ 1855 1856 rfa->rfa_status = 0; 1857 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1858 rfa->actual_size = 0; 1859 1860 v = -1; 1861 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1862 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1863 1864 /* 1865 * If there are other buffers already on the list, attach this 1866 * one to the end by fixing up the tail to point to this one. 1867 */ 1868 if (sc->rfa_headm != NULL) { 1869 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1870 RFA_ALIGNMENT_FUDGE); 1871 sc->rfa_tailm->m_next = m; 1872 v = vtophys(rfa); 1873 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1874 p_rfa->rfa_control = 0; 1875 } else { 1876 sc->rfa_headm = m; 1877 } 1878 sc->rfa_tailm = m; 1879 1880 return (m == oldm); 1881} 1882 1883static volatile int 1884fxp_miibus_readreg(device_t dev, int phy, int reg) 1885{ 1886 struct fxp_softc *sc = device_get_softc(dev); 1887 int count = 10000; 1888 int value; 1889 1890 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1891 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1892 1893 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1894 && count--) 1895 DELAY(10); 1896 1897 if (count <= 0) 1898 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1899 1900 return (value & 0xffff); 1901} 1902 1903static void 1904fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1905{ 1906 struct fxp_softc *sc = device_get_softc(dev); 1907 int count = 10000; 1908 1909 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1910 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1911 (value & 0xffff)); 1912 1913 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1914 count--) 1915 DELAY(10); 1916 1917 if (count <= 0) 1918 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1919} 1920 1921static int 1922fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1923{ 1924 struct fxp_softc *sc = ifp->if_softc; 1925 struct ifreq *ifr = (struct ifreq *)data; 1926 struct mii_data *mii; 1927 int s, error = 0; 1928 1929 s = splimp(); 1930 1931 switch (command) { 1932 case SIOCSIFADDR: 1933 case SIOCGIFADDR: 1934 case SIOCSIFMTU: 1935 error = ether_ioctl(ifp, command, data); 1936 break; 1937 1938 case SIOCSIFFLAGS: 1939 if (ifp->if_flags & IFF_ALLMULTI) 1940 sc->flags |= FXP_FLAG_ALL_MCAST; 1941 else 1942 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1943 1944 /* 1945 * If interface is marked up and not running, then start it. 1946 * If it is marked down and running, stop it. 1947 * XXX If it's up then re-initialize it. This is so flags 1948 * such as IFF_PROMISC are handled. 1949 */ 1950 if (ifp->if_flags & IFF_UP) { 1951 fxp_init(sc); 1952 } else { 1953 if (ifp->if_flags & IFF_RUNNING) 1954 fxp_stop(sc); 1955 } 1956 break; 1957 1958 case SIOCADDMULTI: 1959 case SIOCDELMULTI: 1960 if (ifp->if_flags & IFF_ALLMULTI) 1961 sc->flags |= FXP_FLAG_ALL_MCAST; 1962 else 1963 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1964 /* 1965 * Multicast list has changed; set the hardware filter 1966 * accordingly. 1967 */ 1968 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1969 fxp_mc_setup(sc); 1970 /* 1971 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1972 * again rather than else {}. 1973 */ 1974 if (sc->flags & FXP_FLAG_ALL_MCAST) 1975 fxp_init(sc); 1976 error = 0; 1977 break; 1978 1979 case SIOCSIFMEDIA: 1980 case SIOCGIFMEDIA: 1981 if (sc->miibus != NULL) { 1982 mii = device_get_softc(sc->miibus); 1983 error = ifmedia_ioctl(ifp, ifr, 1984 &mii->mii_media, command); 1985 } else { 1986 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1987 } 1988 break; 1989 1990 default: 1991 error = EINVAL; 1992 } 1993 splx(s); 1994 return (error); 1995} 1996 1997/* 1998 * Program the multicast filter. 1999 * 2000 * We have an artificial restriction that the multicast setup command 2001 * must be the first command in the chain, so we take steps to ensure 2002 * this. By requiring this, it allows us to keep up the performance of 2003 * the pre-initialized command ring (esp. link pointers) by not actually 2004 * inserting the mcsetup command in the ring - i.e. its link pointer 2005 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2006 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2007 * lead into the regular TxCB ring when it completes. 2008 * 2009 * This function must be called at splimp. 2010 */ 2011static void 2012fxp_mc_setup(struct fxp_softc *sc) 2013{ 2014 struct fxp_cb_mcs *mcsp = sc->mcsp; 2015 struct ifnet *ifp = &sc->sc_if; 2016 struct ifmultiaddr *ifma; 2017 int nmcasts; 2018 int count; 2019 2020 /* 2021 * If there are queued commands, we must wait until they are all 2022 * completed. If we are already waiting, then add a NOP command 2023 * with interrupt option so that we're notified when all commands 2024 * have been completed - fxp_start() ensures that no additional 2025 * TX commands will be added when need_mcsetup is true. 2026 */ 2027 if (sc->tx_queued) { 2028 struct fxp_cb_tx *txp; 2029 2030 /* 2031 * need_mcsetup will be true if we are already waiting for the 2032 * NOP command to be completed (see below). In this case, bail. 2033 */ 2034 if (sc->need_mcsetup) 2035 return; 2036 sc->need_mcsetup = 1; 2037 2038 /* 2039 * Add a NOP command with interrupt so that we are notified 2040 * when all TX commands have been processed. 2041 */ 2042 txp = sc->cbl_last->next; 2043 txp->mb_head = NULL; 2044 txp->cb_status = 0; 2045 txp->cb_command = FXP_CB_COMMAND_NOP | 2046 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2047 /* 2048 * Advance the end of list forward. 2049 */ 2050 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2051 sc->cbl_last = txp; 2052 sc->tx_queued++; 2053 /* 2054 * Issue a resume in case the CU has just suspended. 2055 */ 2056 fxp_scb_wait(sc); 2057 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2058 /* 2059 * Set a 5 second timer just in case we don't hear from the 2060 * card again. 2061 */ 2062 ifp->if_timer = 5; 2063 2064 return; 2065 } 2066 sc->need_mcsetup = 0; 2067 2068 /* 2069 * Initialize multicast setup descriptor. 2070 */ 2071 mcsp->next = sc->cbl_base; 2072 mcsp->mb_head = NULL; 2073 mcsp->cb_status = 0; 2074 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2075 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2076 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2077 2078 nmcasts = 0; 2079 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2080#if __FreeBSD_version < 500000 2081 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2082#else 2083 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2084#endif 2085 if (ifma->ifma_addr->sa_family != AF_LINK) 2086 continue; 2087 if (nmcasts >= MAXMCADDR) { 2088 sc->flags |= FXP_FLAG_ALL_MCAST; 2089 nmcasts = 0; 2090 break; 2091 } 2092 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2093 (void *)(uintptr_t)(volatile void *) 2094 &sc->mcsp->mc_addr[nmcasts][0], 6); 2095 nmcasts++; 2096 } 2097 } 2098 mcsp->mc_cnt = nmcasts * 6; 2099 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2100 sc->tx_queued = 1; 2101 2102 /* 2103 * Wait until command unit is not active. This should never 2104 * be the case when nothing is queued, but make sure anyway. 2105 */ 2106 count = 100; 2107 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2108 FXP_SCB_CUS_ACTIVE && --count) 2109 DELAY(10); 2110 if (count == 0) { 2111 device_printf(sc->dev, "command queue timeout\n"); 2112 return; 2113 } 2114 2115 /* 2116 * Start the multicast setup command. 2117 */ 2118 fxp_scb_wait(sc); 2119 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2120 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2121 2122 ifp->if_timer = 2; 2123 return; 2124} 2125 2126static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2127static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2128static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2129static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2130static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2131static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2132 2133#define UCODE(x) x, sizeof(x) 2134 2135struct ucode { 2136 u_int32_t revision; 2137 u_int32_t *ucode; 2138 int length; 2139 u_short int_delay_offset; 2140 u_short bundle_max_offset; 2141} ucode_table[] = { 2142 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2143 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2144 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2145 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2146 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2147 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2148 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2149 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2150 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2151 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2152 { 0, NULL, 0, 0, 0 } 2153}; 2154 2155static void 2156fxp_load_ucode(struct fxp_softc *sc) 2157{ 2158 struct ucode *uc; 2159 struct fxp_cb_ucode *cbp; 2160 2161 for (uc = ucode_table; uc->ucode != NULL; uc++) 2162 if (sc->revision == uc->revision) 2163 break; 2164 if (uc->ucode == NULL) 2165 return; 2166 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2167 cbp->cb_status = 0; 2168 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2169 cbp->link_addr = -1; /* (no) next command */ 2170 memcpy(cbp->ucode, uc->ucode, uc->length); 2171 if (uc->int_delay_offset) 2172 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2173 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2174 if (uc->bundle_max_offset) 2175 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2176 sc->tunable_bundle_max; 2177 /* 2178 * Download the ucode to the chip. 2179 */ 2180 fxp_scb_wait(sc); 2181 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2182 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2183 /* ...and wait for it to complete. */ 2184 fxp_dma_wait(&cbp->cb_status, sc); 2185 device_printf(sc->dev, 2186 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2187 sc->tunable_int_delay, 2188 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2189 sc->flags |= FXP_FLAG_UCODE; 2190} 2191 2192static int 2193sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2194{ 2195 int error, value; 2196 2197 value = *(int *)arg1; 2198 error = sysctl_handle_int(oidp, &value, 0, req); 2199 if (error || !req->newptr) 2200 return (error); 2201 if (value < low || value > high) 2202 return (EINVAL); 2203 *(int *)arg1 = value; 2204 return (0); 2205} 2206 2207/* 2208 * Interrupt delay is expressed in microseconds, a multiplier is used 2209 * to convert this to the appropriate clock ticks before using. 2210 */ 2211static int 2212sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2213{ 2214 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2215} 2216 2217static int 2218sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2219{ 2220 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2221} 2222