if_fxp.c revision 76545
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 76545 2001-05-13 05:38:59Z jlemon $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include "vlan.h" 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44 45#include <net/if.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#ifdef NS 50#include <netns/ns.h> 51#include <netns/ns_if.h> 52#endif 53 54#include <net/bpf.h> 55#include <sys/sockio.h> 56#include <sys/bus.h> 57#include <machine/bus.h> 58#include <sys/rman.h> 59#include <machine/resource.h> 60 61#include <net/ethernet.h> 62#include <net/if_arp.h> 63 64#include <vm/vm.h> /* for vtophys */ 65#include <vm/pmap.h> /* for vtophys */ 66#include <machine/clock.h> /* for DELAY */ 67 68#if NVLAN > 0 69#include <net/if_types.h> 70#include <net/if_vlan_var.h> 71#endif 72 73#include <pci/pcivar.h> 74#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81 82MODULE_DEPEND(fxp, miibus, 1, 1, 1); 83#include "miibus_if.h" 84 85/* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94#define RFA_ALIGNMENT_FUDGE 2 95 96/* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101static int tx_threshold = 64; 102 103/* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137}; 138 139struct fxp_ident { 140 u_int16_t devid; 141 char *name; 142}; 143 144/* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150static struct fxp_ident fxp_ident_table[] = { 151 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 152 { 0x2449, "Intel Pro/100 Ethernet" }, 153 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 154 { 0x1029, "Intel Pro/100 Ethernet" }, 155 { 0x1030, "Intel Pro/100 Ethernet" }, 156 { 0x1031, "Intel Pro/100 Ethernet" }, 157 { 0x1032, "Intel Pro/100 Ethernet" }, 158 { 0x1033, "Intel Pro/100 Ethernet" }, 159 { 0x1034, "Intel Pro/100 Ethernet" }, 160 { 0x1035, "Intel Pro/100 Ethernet" }, 161 { 0x1036, "Intel Pro/100 Ethernet" }, 162 { 0x1037, "Intel Pro/100 Ethernet" }, 163 { 0x1038, "Intel Pro/100 Ethernet" }, 164 { 0, NULL }, 165}; 166 167static int fxp_probe(device_t dev); 168static int fxp_attach(device_t dev); 169static int fxp_detach(device_t dev); 170static int fxp_shutdown(device_t dev); 171static int fxp_suspend(device_t dev); 172static int fxp_resume(device_t dev); 173 174static void fxp_intr(void *xsc); 175static void fxp_init(void *xsc); 176static void fxp_tick(void *xsc); 177static void fxp_start(struct ifnet *ifp); 178static void fxp_stop(struct fxp_softc *sc); 179static void fxp_release(struct fxp_softc *sc); 180static int fxp_ioctl(struct ifnet *ifp, u_long command, 181 caddr_t data); 182static void fxp_watchdog(struct ifnet *ifp); 183static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 184static void fxp_mc_setup(struct fxp_softc *sc); 185static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 186 int autosize); 187static void fxp_autosize_eeprom(struct fxp_softc *sc); 188static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 189 int offset, int words); 190static int fxp_ifmedia_upd(struct ifnet *ifp); 191static void fxp_ifmedia_sts(struct ifnet *ifp, 192 struct ifmediareq *ifmr); 193static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 194static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 195 struct ifmediareq *ifmr); 196static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 197static void fxp_miibus_writereg(device_t dev, int phy, int reg, 198 int value); 199static __inline void fxp_lwcopy(volatile u_int32_t *src, 200 volatile u_int32_t *dst); 201static __inline void fxp_scb_wait(struct fxp_softc *sc); 202static __inline void fxp_dma_wait(volatile u_int16_t *status, 203 struct fxp_softc *sc); 204 205static device_method_t fxp_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_probe, fxp_probe), 208 DEVMETHOD(device_attach, fxp_attach), 209 DEVMETHOD(device_detach, fxp_detach), 210 DEVMETHOD(device_shutdown, fxp_shutdown), 211 DEVMETHOD(device_suspend, fxp_suspend), 212 DEVMETHOD(device_resume, fxp_resume), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 216 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 217 218 { 0, 0 } 219}; 220 221static driver_t fxp_driver = { 222 "fxp", 223 fxp_methods, 224 sizeof(struct fxp_softc), 225}; 226 227static devclass_t fxp_devclass; 228 229DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 230DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 231DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 232 233/* 234 * Inline function to copy a 16-bit aligned 32-bit quantity. 235 */ 236static __inline void 237fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 238{ 239#ifdef __i386__ 240 *dst = *src; 241#else 242 volatile u_int16_t *a = (volatile u_int16_t *)src; 243 volatile u_int16_t *b = (volatile u_int16_t *)dst; 244 245 b[0] = a[0]; 246 b[1] = a[1]; 247#endif 248} 249 250/* 251 * Wait for the previous command to be accepted (but not necessarily 252 * completed). 253 */ 254static __inline void 255fxp_scb_wait(struct fxp_softc *sc) 256{ 257 int i = 10000; 258 259 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 260 DELAY(2); 261 if (i == 0) 262 device_printf(sc->dev, "SCB timeout: 0x%x, 0x%x, 0x%x 0x%x\n", 263 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 264 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 265 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 266 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 267} 268 269static __inline void 270fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 271{ 272 int i = 10000; 273 274 while (!(*status & FXP_CB_STATUS_C) && --i) 275 DELAY(2); 276 if (i == 0) 277 device_printf(sc->dev, "DMA timeout\n"); 278} 279 280/* 281 * Return identification string if this is device is ours. 282 */ 283static int 284fxp_probe(device_t dev) 285{ 286 u_int16_t devid; 287 struct fxp_ident *ident; 288 289 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 290 devid = pci_get_device(dev); 291 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 292 if (ident->devid == devid) { 293 device_set_desc(dev, ident->name); 294 return (0); 295 } 296 } 297 } 298 return (ENXIO); 299} 300 301static int 302fxp_attach(device_t dev) 303{ 304 int error = 0; 305 struct fxp_softc *sc = device_get_softc(dev); 306 struct ifnet *ifp; 307 u_int32_t val; 308 u_int16_t data; 309 int i, rid, m1, m2, prefer_iomap; 310 int s; 311 312 bzero(sc, sizeof(*sc)); 313 sc->dev = dev; 314 callout_handle_init(&sc->stat_ch); 315 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 316 317 s = splimp(); 318 319 /* 320 * Enable bus mastering. Enable memory space too, in case 321 * BIOS/Prom forgot about it. 322 */ 323 val = pci_read_config(dev, PCIR_COMMAND, 2); 324 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 325 pci_write_config(dev, PCIR_COMMAND, val, 2); 326 val = pci_read_config(dev, PCIR_COMMAND, 2); 327 328#if __FreeBSD_version >= 500000 329 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 330 u_int32_t iobase, membase, irq; 331 332 /* Save important PCI config data. */ 333 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 334 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 335 irq = pci_read_config(dev, PCIR_INTLINE, 4); 336 337 /* Reset the power state. */ 338 device_printf(dev, "chip is in D%d power mode " 339 "-- setting to D0\n", pci_get_powerstate(dev)); 340 341 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 342 343 /* Restore PCI config data. */ 344 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 345 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 346 pci_write_config(dev, PCIR_INTLINE, irq, 4); 347 } 348#endif 349 350 /* 351 * Figure out which we should try first - memory mapping or i/o mapping? 352 * We default to memory mapping. Then we accept an override from the 353 * command line. Then we check to see which one is enabled. 354 */ 355 m1 = PCIM_CMD_MEMEN; 356 m2 = PCIM_CMD_PORTEN; 357 prefer_iomap = 0; 358 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 359 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 360 m1 = PCIM_CMD_PORTEN; 361 m2 = PCIM_CMD_MEMEN; 362 } 363 364 if (val & m1) { 365 sc->rtp = 366 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 367 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 368 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 369 0, ~0, 1, RF_ACTIVE); 370 } 371 if (sc->mem == NULL && (val & m2)) { 372 sc->rtp = 373 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 374 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 375 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 376 0, ~0, 1, RF_ACTIVE); 377 } 378 379 if (!sc->mem) { 380 device_printf(dev, "could not map device registers\n"); 381 error = ENXIO; 382 goto fail; 383 } 384 if (bootverbose) { 385 device_printf(dev, "using %s space register mapping\n", 386 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 387 } 388 389 sc->sc_st = rman_get_bustag(sc->mem); 390 sc->sc_sh = rman_get_bushandle(sc->mem); 391 392 /* 393 * Allocate our interrupt. 394 */ 395 rid = 0; 396 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 397 RF_SHAREABLE | RF_ACTIVE); 398 if (sc->irq == NULL) { 399 device_printf(dev, "could not map interrupt\n"); 400 error = ENXIO; 401 goto fail; 402 } 403 404 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 405 fxp_intr, sc, &sc->ih); 406 if (error) { 407 device_printf(dev, "could not setup irq\n"); 408 goto fail; 409 } 410 411 /* 412 * Reset to a stable state. 413 */ 414 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 415 DELAY(10); 416 417 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 418 M_DEVBUF, M_NOWAIT | M_ZERO); 419 if (sc->cbl_base == NULL) 420 goto failmem; 421 422 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 423 M_NOWAIT | M_ZERO); 424 if (sc->fxp_stats == NULL) 425 goto failmem; 426 427 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 428 if (sc->mcsp == NULL) 429 goto failmem; 430 431 /* 432 * Pre-allocate our receive buffers. 433 */ 434 for (i = 0; i < FXP_NRFABUFS; i++) { 435 if (fxp_add_rfabuf(sc, NULL) != 0) { 436 goto failmem; 437 } 438 } 439 440 /* 441 * Find out how large of an SEEPROM we have. 442 */ 443 fxp_autosize_eeprom(sc); 444 445 /* 446 * Determine whether we must use the 503 serial interface. 447 */ 448 fxp_read_eeprom(sc, &data, 6, 1); 449 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 450 (data & FXP_PHY_SERIAL_ONLY)) 451 sc->flags &= FXP_FLAG_SERIAL_MEDIA; 452 453 /* 454 * Find out the basic controller type; we currently only 455 * differentiate between a 82557 and greater. 456 */ 457 fxp_read_eeprom(sc, &data, 5, 1); 458 if ((data >> 8) == 1) 459 sc->chip = FXP_CHIP_82557; 460 461 /* 462 * If we are not a 82557 chip, we can enable extended features. 463 */ 464 if (sc->chip != FXP_CHIP_82557) { 465 /* 466 * If there is a valid cacheline size (8 or 16 dwords), 467 * then turn on MWI. 468 */ 469 if (pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 470 sc->flags |= FXP_FLAG_MWI_ENABLE; 471 472 /* turn on the extended TxCB feature */ 473 sc->flags |= FXP_FLAG_EXT_TXCB; 474#if NVLAN > 0 475 /* enable reception of long frames for VLAN */ 476 sc->flags |= FXP_FLAG_LONG_PKT_EN; 477#endif 478 } 479 480 /* 481 * Read MAC address. 482 */ 483 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 484 device_printf(dev, "Ethernet address %6D%s\n", 485 sc->arpcom.ac_enaddr, ":", 486 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 487 if (bootverbose) { 488 device_printf(dev, "PCI IDs: %04x %04x %04x %04x\n", 489 pci_get_vendor(dev), pci_get_device(dev), 490 pci_get_subvendor(dev), pci_get_subdevice(dev)); 491 device_printf(dev, "Chip Type: %d\n", sc->chip); 492 } 493 494 /* 495 * If this is only a 10Mbps device, then there is no MII, and 496 * the PHY will use a serial interface instead. 497 * 498 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 499 * doesn't have a programming interface of any sort. The 500 * media is sensed automatically based on how the link partner 501 * is configured. This is, in essence, manual configuration. 502 */ 503 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 504 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 505 fxp_serial_ifmedia_sts); 506 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 507 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 508 } else { 509 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 510 fxp_ifmedia_sts)) { 511 device_printf(dev, "MII without any PHY!\n"); 512 error = ENXIO; 513 goto fail; 514 } 515 } 516 517 ifp = &sc->arpcom.ac_if; 518 ifp->if_unit = device_get_unit(dev); 519 ifp->if_name = "fxp"; 520 ifp->if_output = ether_output; 521 ifp->if_baudrate = 100000000; 522 ifp->if_init = fxp_init; 523 ifp->if_softc = sc; 524 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 525 ifp->if_ioctl = fxp_ioctl; 526 ifp->if_start = fxp_start; 527 ifp->if_watchdog = fxp_watchdog; 528 529 /* 530 * Attach the interface. 531 */ 532 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 533 534#if NVLAN > 0 535 /* 536 * Tell the upper layer(s) we support long frames. 537 */ 538 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 539#endif 540 541 /* 542 * Let the system queue as many packets as we have available 543 * TX descriptors. 544 */ 545 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 546 547 splx(s); 548 return (0); 549 550failmem: 551 device_printf(dev, "Failed to malloc memory\n"); 552 error = ENOMEM; 553fail: 554 splx(s); 555 fxp_release(sc); 556 return (error); 557} 558 559/* 560 * release all resources 561 */ 562static void 563fxp_release(struct fxp_softc *sc) 564{ 565 566 bus_generic_detach(sc->dev); 567 if (sc->miibus) 568 device_delete_child(sc->dev, sc->miibus); 569 570 if (sc->cbl_base) 571 free(sc->cbl_base, M_DEVBUF); 572 if (sc->fxp_stats) 573 free(sc->fxp_stats, M_DEVBUF); 574 if (sc->mcsp) 575 free(sc->mcsp, M_DEVBUF); 576 if (sc->rfa_headm) 577 m_freem(sc->rfa_headm); 578 579 if (sc->ih) 580 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 581 if (sc->irq) 582 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 583 if (sc->mem) 584 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 585 mtx_destroy(&sc->sc_mtx); 586} 587 588/* 589 * Detach interface. 590 */ 591static int 592fxp_detach(device_t dev) 593{ 594 struct fxp_softc *sc = device_get_softc(dev); 595 int s; 596 597 s = splimp(); 598 599 /* 600 * Stop DMA and drop transmit queue. 601 */ 602 fxp_stop(sc); 603 604 /* 605 * Close down routes etc. 606 */ 607 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 608 609 /* 610 * Free all media structures. 611 */ 612 ifmedia_removeall(&sc->sc_media); 613 614 splx(s); 615 616 /* Release our allocated resources. */ 617 fxp_release(sc); 618 619 return (0); 620} 621 622/* 623 * Device shutdown routine. Called at system shutdown after sync. The 624 * main purpose of this routine is to shut off receiver DMA so that 625 * kernel memory doesn't get clobbered during warmboot. 626 */ 627static int 628fxp_shutdown(device_t dev) 629{ 630 /* 631 * Make sure that DMA is disabled prior to reboot. Not doing 632 * do could allow DMA to corrupt kernel memory during the 633 * reboot before the driver initializes. 634 */ 635 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 636 return (0); 637} 638 639/* 640 * Device suspend routine. Stop the interface and save some PCI 641 * settings in case the BIOS doesn't restore them properly on 642 * resume. 643 */ 644static int 645fxp_suspend(device_t dev) 646{ 647 struct fxp_softc *sc = device_get_softc(dev); 648 int i, s; 649 650 s = splimp(); 651 652 fxp_stop(sc); 653 654 for (i=0; i<5; i++) 655 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 656 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 657 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 658 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 659 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 660 661 sc->suspended = 1; 662 663 splx(s); 664 return (0); 665} 666 667/* 668 * Device resume routine. Restore some PCI settings in case the BIOS 669 * doesn't, re-enable busmastering, and restart the interface if 670 * appropriate. 671 */ 672static int 673fxp_resume(device_t dev) 674{ 675 struct fxp_softc *sc = device_get_softc(dev); 676 struct ifnet *ifp = &sc->sc_if; 677 u_int16_t pci_command; 678 int i, s; 679 680 s = splimp(); 681 682 /* better way to do this? */ 683 for (i=0; i<5; i++) 684 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 685 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 686 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 687 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 688 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 689 690 /* reenable busmastering */ 691 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 692 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 693 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 694 695 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 696 DELAY(10); 697 698 /* reinitialize interface if necessary */ 699 if (ifp->if_flags & IFF_UP) 700 fxp_init(sc); 701 702 sc->suspended = 0; 703 704 splx(s); 705 return (0); 706} 707 708/* 709 * Read from the serial EEPROM. Basically, you manually shift in 710 * the read opcode (one bit at a time) and then shift in the address, 711 * and then you shift out the data (all of this one bit at a time). 712 * The word size is 16 bits, so you have to provide the address for 713 * every 16 bits of data. 714 */ 715static u_int16_t 716fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 717{ 718 u_int16_t reg, data; 719 int x; 720 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 722 /* 723 * Shift in read opcode. 724 */ 725 for (x = 1 << 2; x; x >>= 1) { 726 if (FXP_EEPROM_OPC_READ & x) 727 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 728 else 729 reg = FXP_EEPROM_EECS; 730 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 731 DELAY(1); 732 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 733 DELAY(1); 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 735 DELAY(1); 736 } 737 /* 738 * Shift in address. 739 */ 740 data = 0; 741 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 742 if (offset & x) 743 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 744 else 745 reg = FXP_EEPROM_EECS; 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 747 DELAY(1); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 749 DELAY(1); 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 751 DELAY(1); 752 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 753 data++; 754 if (autosize && reg == 0) { 755 sc->eeprom_size = data; 756 break; 757 } 758 } 759 /* 760 * Shift out data. 761 */ 762 data = 0; 763 reg = FXP_EEPROM_EECS; 764 for (x = 1 << 15; x; x >>= 1) { 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 766 DELAY(1); 767 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 768 data |= x; 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 770 DELAY(1); 771 } 772 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 773 DELAY(1); 774 775 return (data); 776} 777 778/* 779 * From NetBSD: 780 * 781 * Figure out EEPROM size. 782 * 783 * 559's can have either 64-word or 256-word EEPROMs, the 558 784 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 785 * talks about the existance of 16 to 256 word EEPROMs. 786 * 787 * The only known sizes are 64 and 256, where the 256 version is used 788 * by CardBus cards to store CIS information. 789 * 790 * The address is shifted in msb-to-lsb, and after the last 791 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 792 * after which follows the actual data. We try to detect this zero, by 793 * probing the data-out bit in the EEPROM control register just after 794 * having shifted in a bit. If the bit is zero, we assume we've 795 * shifted enough address bits. The data-out should be tri-state, 796 * before this, which should translate to a logical one. 797 * 798 * Other ways to do this would be to try to read a register with known 799 * contents with a varying number of address bits, but no such 800 * register seem to be available. The high bits of register 10 are 01 801 * on the 558 and 559, but apparently not on the 557. 802 * 803 * The Linux driver computes a checksum on the EEPROM data, but the 804 * value of this checksum is not very well documented. 805 */ 806static void 807fxp_autosize_eeprom(struct fxp_softc *sc) 808{ 809 810 /* guess maximum size of 256 words */ 811 sc->eeprom_size = 8; 812 813 /* autosize */ 814 (void) fxp_eeprom_getword(sc, 0, 1); 815} 816 817static void 818fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 819{ 820 int i; 821 822 for (i = 0; i < words; i++) 823 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 824} 825 826/* 827 * Start packet transmission on the interface. 828 */ 829static void 830fxp_start(struct ifnet *ifp) 831{ 832 struct fxp_softc *sc = ifp->if_softc; 833 struct fxp_cb_tx *txp; 834 835 /* 836 * See if we need to suspend xmit until the multicast filter 837 * has been reprogrammed (which can only be done at the head 838 * of the command chain). 839 */ 840 if (sc->need_mcsetup) { 841 return; 842 } 843 844 txp = NULL; 845 846 /* 847 * We're finished if there is nothing more to add to the list or if 848 * we're all filled up with buffers to transmit. 849 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 850 * a NOP command when needed. 851 */ 852 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 853 struct mbuf *m, *mb_head; 854 int segment; 855 856 /* 857 * Grab a packet to transmit. 858 */ 859 IF_DEQUEUE(&ifp->if_snd, mb_head); 860 861 /* 862 * Get pointer to next available tx desc. 863 */ 864 txp = sc->cbl_last->next; 865 866 /* 867 * Go through each of the mbufs in the chain and initialize 868 * the transmit buffer descriptors with the physical address 869 * and size of the mbuf. 870 */ 871tbdinit: 872 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 873 if (m->m_len != 0) { 874 if (segment == FXP_NTXSEG) 875 break; 876 txp->tbd[segment].tb_addr = 877 vtophys(mtod(m, vm_offset_t)); 878 txp->tbd[segment].tb_size = m->m_len; 879 segment++; 880 } 881 } 882 if (m != NULL) { 883 struct mbuf *mn; 884 885 /* 886 * We ran out of segments. We have to recopy this 887 * mbuf chain first. Bail out if we can't get the 888 * new buffers. 889 */ 890 MGETHDR(mn, M_DONTWAIT, MT_DATA); 891 if (mn == NULL) { 892 m_freem(mb_head); 893 break; 894 } 895 if (mb_head->m_pkthdr.len > MHLEN) { 896 MCLGET(mn, M_DONTWAIT); 897 if ((mn->m_flags & M_EXT) == 0) { 898 m_freem(mn); 899 m_freem(mb_head); 900 break; 901 } 902 } 903 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 904 mtod(mn, caddr_t)); 905 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 906 m_freem(mb_head); 907 mb_head = mn; 908 goto tbdinit; 909 } 910 911 txp->tbd_number = segment; 912 txp->mb_head = mb_head; 913 txp->cb_status = 0; 914 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 915 txp->cb_command = 916 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 917 FXP_CB_COMMAND_S; 918 } else { 919 txp->cb_command = 920 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 921 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 922 /* 923 * Set a 5 second timer just in case we don't hear 924 * from the card again. 925 */ 926 ifp->if_timer = 5; 927 } 928 txp->tx_threshold = tx_threshold; 929 930 /* 931 * Advance the end of list forward. 932 */ 933 934#ifdef __alpha__ 935 /* 936 * On platforms which can't access memory in 16-bit 937 * granularities, we must prevent the card from DMA'ing 938 * up the status while we update the command field. 939 * This could cause us to overwrite the completion status. 940 */ 941 atomic_clear_short(&sc->cbl_last->cb_command, 942 FXP_CB_COMMAND_S); 943#else 944 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 945#endif /*__alpha__*/ 946 sc->cbl_last = txp; 947 948 /* 949 * Advance the beginning of the list forward if there are 950 * no other packets queued (when nothing is queued, cbl_first 951 * sits on the last TxCB that was sent out). 952 */ 953 if (sc->tx_queued == 0) 954 sc->cbl_first = txp; 955 956 sc->tx_queued++; 957 958 /* 959 * Pass packet to bpf if there is a listener. 960 */ 961 if (ifp->if_bpf) 962 bpf_mtap(ifp, mb_head); 963 } 964 965 /* 966 * We're finished. If we added to the list, issue a RESUME to get DMA 967 * going again if suspended. 968 */ 969 if (txp != NULL) { 970 fxp_scb_wait(sc); 971 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 972 } 973} 974 975/* 976 * Process interface interrupts. 977 */ 978static void 979fxp_intr(void *xsc) 980{ 981 struct fxp_softc *sc = xsc; 982 struct ifnet *ifp = &sc->sc_if; 983 u_int8_t statack; 984 985 986 if (sc->suspended) { 987 return; 988 } 989 990 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 991 /* 992 * First ACK all the interrupts in this pass. 993 */ 994 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 995 996 /* 997 * Free any finished transmit mbuf chains. 998 * 999 * Handle the CNA event likt a CXTNO event. It used to 1000 * be that this event (control unit not ready) was not 1001 * encountered, but it is now with the SMPng modifications. 1002 * The exact sequence of events that occur when the interface 1003 * is brought up are different now, and if this event 1004 * goes unhandled, the configuration/rxfilter setup sequence 1005 * can stall for several seconds. The result is that no 1006 * packets go out onto the wire for about 5 to 10 seconds 1007 * after the interface is ifconfig'ed for the first time. 1008 */ 1009 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1010 struct fxp_cb_tx *txp; 1011 1012 for (txp = sc->cbl_first; sc->tx_queued && 1013 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1014 txp = txp->next) { 1015 if (txp->mb_head != NULL) { 1016 m_freem(txp->mb_head); 1017 txp->mb_head = NULL; 1018 } 1019 sc->tx_queued--; 1020 } 1021 sc->cbl_first = txp; 1022 ifp->if_timer = 0; 1023 if (sc->tx_queued == 0) { 1024 if (sc->need_mcsetup) 1025 fxp_mc_setup(sc); 1026 } 1027 /* 1028 * Try to start more packets transmitting. 1029 */ 1030 if (ifp->if_snd.ifq_head != NULL) 1031 fxp_start(ifp); 1032 } 1033 /* 1034 * Process receiver interrupts. If a no-resource (RNR) 1035 * condition exists, get whatever packets we can and 1036 * re-start the receiver. 1037 */ 1038 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1039 struct mbuf *m; 1040 struct fxp_rfa *rfa; 1041rcvloop: 1042 m = sc->rfa_headm; 1043 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1044 RFA_ALIGNMENT_FUDGE); 1045 1046 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1047 /* 1048 * Remove first packet from the chain. 1049 */ 1050 sc->rfa_headm = m->m_next; 1051 m->m_next = NULL; 1052 1053 /* 1054 * Add a new buffer to the receive chain. 1055 * If this fails, the old buffer is recycled 1056 * instead. 1057 */ 1058 if (fxp_add_rfabuf(sc, m) == 0) { 1059 struct ether_header *eh; 1060 int total_len; 1061 1062 total_len = rfa->actual_size & 1063 (MCLBYTES - 1); 1064 if (total_len < 1065 sizeof(struct ether_header)) { 1066 m_freem(m); 1067 goto rcvloop; 1068 } 1069#if NVLAN > 0 1070 /* 1071 * Drop the packet if it has CRC 1072 * errors. This test is only needed 1073 * when doing 802.1q VLAN on the 82557 1074 * chip. 1075 */ 1076 if (rfa->rfa_status & 1077 FXP_RFA_STATUS_CRC) { 1078 m_freem(m); 1079 goto rcvloop; 1080 } 1081#endif 1082 m->m_pkthdr.rcvif = ifp; 1083 m->m_pkthdr.len = m->m_len = total_len; 1084 eh = mtod(m, struct ether_header *); 1085 m->m_data += 1086 sizeof(struct ether_header); 1087 m->m_len -= 1088 sizeof(struct ether_header); 1089 m->m_pkthdr.len = m->m_len; 1090 ether_input(ifp, eh, m); 1091 } 1092 goto rcvloop; 1093 } 1094 if (statack & FXP_SCB_STATACK_RNR) { 1095 fxp_scb_wait(sc); 1096 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1097 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1098 RFA_ALIGNMENT_FUDGE); 1099 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1100 FXP_SCB_COMMAND_RU_START); 1101 } 1102 } 1103 } 1104} 1105 1106/* 1107 * Update packet in/out/collision statistics. The i82557 doesn't 1108 * allow you to access these counters without doing a fairly 1109 * expensive DMA to get _all_ of the statistics it maintains, so 1110 * we do this operation here only once per second. The statistics 1111 * counters in the kernel are updated from the previous dump-stats 1112 * DMA and then a new dump-stats DMA is started. The on-chip 1113 * counters are zeroed when the DMA completes. If we can't start 1114 * the DMA immediately, we don't wait - we just prepare to read 1115 * them again next time. 1116 */ 1117static void 1118fxp_tick(void *xsc) 1119{ 1120 struct fxp_softc *sc = xsc; 1121 struct ifnet *ifp = &sc->sc_if; 1122 struct fxp_stats *sp = sc->fxp_stats; 1123 struct fxp_cb_tx *txp; 1124 int s; 1125 1126 ifp->if_opackets += sp->tx_good; 1127 ifp->if_collisions += sp->tx_total_collisions; 1128 if (sp->rx_good) { 1129 ifp->if_ipackets += sp->rx_good; 1130 sc->rx_idle_secs = 0; 1131 } else { 1132 /* 1133 * Receiver's been idle for another second. 1134 */ 1135 sc->rx_idle_secs++; 1136 } 1137 ifp->if_ierrors += 1138 sp->rx_crc_errors + 1139 sp->rx_alignment_errors + 1140 sp->rx_rnr_errors + 1141 sp->rx_overrun_errors; 1142 /* 1143 * If any transmit underruns occured, bump up the transmit 1144 * threshold by another 512 bytes (64 * 8). 1145 */ 1146 if (sp->tx_underruns) { 1147 ifp->if_oerrors += sp->tx_underruns; 1148 if (tx_threshold < 192) 1149 tx_threshold += 64; 1150 } 1151 s = splimp(); 1152 /* 1153 * Release any xmit buffers that have completed DMA. This isn't 1154 * strictly necessary to do here, but it's advantagous for mbufs 1155 * with external storage to be released in a timely manner rather 1156 * than being defered for a potentially long time. This limits 1157 * the delay to a maximum of one second. 1158 */ 1159 for (txp = sc->cbl_first; sc->tx_queued && 1160 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1161 txp = txp->next) { 1162 if (txp->mb_head != NULL) { 1163 m_freem(txp->mb_head); 1164 txp->mb_head = NULL; 1165 } 1166 sc->tx_queued--; 1167 } 1168 sc->cbl_first = txp; 1169 /* 1170 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1171 * then assume the receiver has locked up and attempt to clear 1172 * the condition by reprogramming the multicast filter. This is 1173 * a work-around for a bug in the 82557 where the receiver locks 1174 * up if it gets certain types of garbage in the syncronization 1175 * bits prior to the packet header. This bug is supposed to only 1176 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1177 * mode as well (perhaps due to a 10/100 speed transition). 1178 */ 1179 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1180 sc->rx_idle_secs = 0; 1181 fxp_mc_setup(sc); 1182 } 1183 /* 1184 * If there is no pending command, start another stats 1185 * dump. Otherwise punt for now. 1186 */ 1187 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1188 /* 1189 * Start another stats dump. 1190 */ 1191 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1192 FXP_SCB_COMMAND_CU_DUMPRESET); 1193 } else { 1194 /* 1195 * A previous command is still waiting to be accepted. 1196 * Just zero our copy of the stats and wait for the 1197 * next timer event to update them. 1198 */ 1199 sp->tx_good = 0; 1200 sp->tx_underruns = 0; 1201 sp->tx_total_collisions = 0; 1202 1203 sp->rx_good = 0; 1204 sp->rx_crc_errors = 0; 1205 sp->rx_alignment_errors = 0; 1206 sp->rx_rnr_errors = 0; 1207 sp->rx_overrun_errors = 0; 1208 } 1209 1210 if (sc->miibus != NULL) 1211 mii_tick(device_get_softc(sc->miibus)); 1212 1213 /* 1214 * Schedule another timeout one second from now. 1215 */ 1216 sc->stat_ch = timeout(fxp_tick, sc, hz); 1217} 1218 1219/* 1220 * Stop the interface. Cancels the statistics updater and resets 1221 * the interface. 1222 */ 1223static void 1224fxp_stop(struct fxp_softc *sc) 1225{ 1226 struct ifnet *ifp = &sc->sc_if; 1227 struct fxp_cb_tx *txp; 1228 int i; 1229 1230 1231 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1232 ifp->if_timer = 0; 1233 1234 /* 1235 * Cancel stats updater. 1236 */ 1237 untimeout(fxp_tick, sc, sc->stat_ch); 1238 1239 /* 1240 * Issue software reset 1241 */ 1242 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1243 DELAY(10); 1244 1245 /* 1246 * Release any xmit buffers. 1247 */ 1248 txp = sc->cbl_base; 1249 if (txp != NULL) { 1250 for (i = 0; i < FXP_NTXCB; i++) { 1251 if (txp[i].mb_head != NULL) { 1252 m_freem(txp[i].mb_head); 1253 txp[i].mb_head = NULL; 1254 } 1255 } 1256 } 1257 sc->tx_queued = 0; 1258 1259 /* 1260 * Free all the receive buffers then reallocate/reinitialize 1261 */ 1262 if (sc->rfa_headm != NULL) 1263 m_freem(sc->rfa_headm); 1264 sc->rfa_headm = NULL; 1265 sc->rfa_tailm = NULL; 1266 for (i = 0; i < FXP_NRFABUFS; i++) { 1267 if (fxp_add_rfabuf(sc, NULL) != 0) { 1268 /* 1269 * This "can't happen" - we're at splimp() 1270 * and we just freed all the buffers we need 1271 * above. 1272 */ 1273 panic("fxp_stop: no buffers!"); 1274 } 1275 } 1276} 1277 1278/* 1279 * Watchdog/transmission transmit timeout handler. Called when a 1280 * transmission is started on the interface, but no interrupt is 1281 * received before the timeout. This usually indicates that the 1282 * card has wedged for some reason. 1283 */ 1284static void 1285fxp_watchdog(struct ifnet *ifp) 1286{ 1287 struct fxp_softc *sc = ifp->if_softc; 1288 1289 device_printf(sc->dev, "device timeout\n"); 1290 ifp->if_oerrors++; 1291 1292 fxp_init(sc); 1293} 1294 1295static void 1296fxp_init(void *xsc) 1297{ 1298 struct fxp_softc *sc = xsc; 1299 struct ifnet *ifp = &sc->sc_if; 1300 struct fxp_cb_config *cbp; 1301 struct fxp_cb_ias *cb_ias; 1302 struct fxp_cb_tx *txp; 1303 int i, prm, s; 1304 1305 s = splimp(); 1306 /* 1307 * Cancel any pending I/O 1308 */ 1309 fxp_stop(sc); 1310 1311 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1312 1313 /* 1314 * Initialize base of CBL and RFA memory. Loading with zero 1315 * sets it up for regular linear addressing. 1316 */ 1317 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1319 1320 fxp_scb_wait(sc); 1321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1322 1323 /* 1324 * Initialize base of dump-stats buffer. 1325 */ 1326 fxp_scb_wait(sc); 1327 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1328 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1329 1330 /* 1331 * We temporarily use memory that contains the TxCB list to 1332 * construct the config CB. The TxCB list memory is rebuilt 1333 * later. 1334 */ 1335 cbp = (struct fxp_cb_config *) sc->cbl_base; 1336 1337 /* 1338 * This bcopy is kind of disgusting, but there are a bunch of must be 1339 * zero and must be one bits in this structure and this is the easiest 1340 * way to initialize them all to proper values. 1341 */ 1342 bcopy(fxp_cb_config_template, 1343 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1344 sizeof(fxp_cb_config_template)); 1345 1346 cbp->cb_status = 0; 1347 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1348 cbp->link_addr = -1; /* (no) next command */ 1349 cbp->byte_count = 22; /* (22) bytes to config */ 1350 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1351 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1352 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1353 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1354 cbp->type_enable = 0; /* actually reserved */ 1355 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1356 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1357 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1358 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1359 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1360 cbp->late_scb = 0; /* (don't) defer SCB update */ 1361 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1362 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1363 cbp->ci_int = 1; /* interrupt on CU idle */ 1364 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1365 cbp->ext_stats_dis = 1; /* disable extended counters */ 1366 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1367#if NVLAN > 0 1368 cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm; 1369#else 1370 cbp->save_bf = prm; /* save bad frames */ 1371#endif 1372 cbp->disc_short_rx = !prm; /* discard short packets */ 1373 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1374 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1375 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1376 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1377 cbp->csma_dis = 0; /* (don't) disable link */ 1378 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1379 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1380 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1381 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1382 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1383 cbp->nsai = 1; /* (don't) disable source addr insert */ 1384 cbp->preamble_length = 2; /* (7 byte) preamble */ 1385 cbp->loopback = 0; /* (don't) loopback */ 1386 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1387 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1388 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1389 cbp->promiscuous = prm; /* promiscuous mode */ 1390 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1391 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1392 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1393 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1394 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1395 1396 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1397 cbp->padding = 1; /* (do) pad short tx packets */ 1398 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1399 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1400 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1401 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1402 /* must set wake_en in PMCSR also */ 1403 cbp->force_fdx = 0; /* (don't) force full duplex */ 1404 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1405 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1406 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1407 1408 if (sc->chip == FXP_CHIP_82557) { 1409 /* 1410 * The 82557 has no hardware flow control, the values 1411 * below are the defaults for the chip. 1412 */ 1413 cbp->fc_delay_lsb = 0; 1414 cbp->fc_delay_msb = 0x40; 1415 cbp->pri_fc_thresh = 3; 1416 cbp->tx_fc_dis = 0; 1417 cbp->rx_fc_restop = 0; 1418 cbp->rx_fc_restart = 0; 1419 cbp->fc_filter = 0; 1420 cbp->pri_fc_loc = 1; 1421 } else { 1422 cbp->fc_delay_lsb = 0x1f; 1423 cbp->fc_delay_msb = 0x01; 1424 cbp->pri_fc_thresh = 3; 1425 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1426 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1427 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1428 cbp->fc_filter = !prm; /* drop FC frames to host */ 1429 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1430 } 1431 1432 /* 1433 * Start the config command/DMA. 1434 */ 1435 fxp_scb_wait(sc); 1436 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1437 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1438 /* ...and wait for it to complete. */ 1439 fxp_dma_wait(&cbp->cb_status, sc); 1440 1441 /* 1442 * Now initialize the station address. Temporarily use the TxCB 1443 * memory area like we did above for the config CB. 1444 */ 1445 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1446 cb_ias->cb_status = 0; 1447 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1448 cb_ias->link_addr = -1; 1449 bcopy(sc->arpcom.ac_enaddr, 1450 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1451 sizeof(sc->arpcom.ac_enaddr)); 1452 1453 /* 1454 * Start the IAS (Individual Address Setup) command/DMA. 1455 */ 1456 fxp_scb_wait(sc); 1457 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1458 /* ...and wait for it to complete. */ 1459 fxp_dma_wait(&cb_ias->cb_status, sc); 1460 1461 /* 1462 * Initialize transmit control block (TxCB) list. 1463 */ 1464 1465 txp = sc->cbl_base; 1466 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1467 for (i = 0; i < FXP_NTXCB; i++) { 1468 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1469 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1470 txp[i].link_addr = 1471 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1472 if (sc->flags & FXP_FLAG_EXT_TXCB) 1473 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1474 else 1475 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1476 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1477 } 1478 /* 1479 * Set the suspend flag on the first TxCB and start the control 1480 * unit. It will execute the NOP and then suspend. 1481 */ 1482 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1483 sc->cbl_first = sc->cbl_last = txp; 1484 sc->tx_queued = 1; 1485 1486 fxp_scb_wait(sc); 1487 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1488 1489 /* 1490 * Initialize receiver buffer area - RFA. 1491 */ 1492 fxp_scb_wait(sc); 1493 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1494 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1495 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1496 1497 /* 1498 * Set current media. 1499 */ 1500 if (sc->miibus != NULL) 1501 mii_mediachg(device_get_softc(sc->miibus)); 1502 1503 ifp->if_flags |= IFF_RUNNING; 1504 ifp->if_flags &= ~IFF_OACTIVE; 1505 1506 /* 1507 * Enable interrupts. 1508 */ 1509 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1510 splx(s); 1511 1512 /* 1513 * Start stats updater. 1514 */ 1515 sc->stat_ch = timeout(fxp_tick, sc, hz); 1516} 1517 1518static int 1519fxp_serial_ifmedia_upd(struct ifnet *ifp) 1520{ 1521 1522 return (0); 1523} 1524 1525static void 1526fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1527{ 1528 1529 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1530} 1531 1532/* 1533 * Change media according to request. 1534 */ 1535static int 1536fxp_ifmedia_upd(struct ifnet *ifp) 1537{ 1538 struct fxp_softc *sc = ifp->if_softc; 1539 struct mii_data *mii; 1540 1541 mii = device_get_softc(sc->miibus); 1542 mii_mediachg(mii); 1543 return (0); 1544} 1545 1546/* 1547 * Notify the world which media we're using. 1548 */ 1549static void 1550fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1551{ 1552 struct fxp_softc *sc = ifp->if_softc; 1553 struct mii_data *mii; 1554 1555 mii = device_get_softc(sc->miibus); 1556 mii_pollstat(mii); 1557 ifmr->ifm_active = mii->mii_media_active; 1558 ifmr->ifm_status = mii->mii_media_status; 1559} 1560 1561/* 1562 * Add a buffer to the end of the RFA buffer list. 1563 * Return 0 if successful, 1 for failure. A failure results in 1564 * adding the 'oldm' (if non-NULL) on to the end of the list - 1565 * tossing out its old contents and recycling it. 1566 * The RFA struct is stuck at the beginning of mbuf cluster and the 1567 * data pointer is fixed up to point just past it. 1568 */ 1569static int 1570fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1571{ 1572 u_int32_t v; 1573 struct mbuf *m; 1574 struct fxp_rfa *rfa, *p_rfa; 1575 1576 MGETHDR(m, M_DONTWAIT, MT_DATA); 1577 if (m != NULL) { 1578 MCLGET(m, M_DONTWAIT); 1579 if ((m->m_flags & M_EXT) == 0) { 1580 m_freem(m); 1581 if (oldm == NULL) 1582 return 1; 1583 m = oldm; 1584 m->m_data = m->m_ext.ext_buf; 1585 } 1586 } else { 1587 if (oldm == NULL) 1588 return 1; 1589 m = oldm; 1590 m->m_data = m->m_ext.ext_buf; 1591 } 1592 1593 /* 1594 * Move the data pointer up so that the incoming data packet 1595 * will be 32-bit aligned. 1596 */ 1597 m->m_data += RFA_ALIGNMENT_FUDGE; 1598 1599 /* 1600 * Get a pointer to the base of the mbuf cluster and move 1601 * data start past it. 1602 */ 1603 rfa = mtod(m, struct fxp_rfa *); 1604 m->m_data += sizeof(struct fxp_rfa); 1605 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1606 1607 /* 1608 * Initialize the rest of the RFA. Note that since the RFA 1609 * is misaligned, we cannot store values directly. Instead, 1610 * we use an optimized, inline copy. 1611 */ 1612 1613 rfa->rfa_status = 0; 1614 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1615 rfa->actual_size = 0; 1616 1617 v = -1; 1618 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1619 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1620 1621 /* 1622 * If there are other buffers already on the list, attach this 1623 * one to the end by fixing up the tail to point to this one. 1624 */ 1625 if (sc->rfa_headm != NULL) { 1626 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1627 RFA_ALIGNMENT_FUDGE); 1628 sc->rfa_tailm->m_next = m; 1629 v = vtophys(rfa); 1630 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1631 p_rfa->rfa_control = 0; 1632 } else { 1633 sc->rfa_headm = m; 1634 } 1635 sc->rfa_tailm = m; 1636 1637 return (m == oldm); 1638} 1639 1640static volatile int 1641fxp_miibus_readreg(device_t dev, int phy, int reg) 1642{ 1643 struct fxp_softc *sc = device_get_softc(dev); 1644 int count = 10000; 1645 int value; 1646 1647 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1648 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1649 1650 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1651 && count--) 1652 DELAY(10); 1653 1654 if (count <= 0) 1655 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1656 1657 return (value & 0xffff); 1658} 1659 1660static void 1661fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1662{ 1663 struct fxp_softc *sc = device_get_softc(dev); 1664 int count = 10000; 1665 1666 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1667 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1668 (value & 0xffff)); 1669 1670 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1671 count--) 1672 DELAY(10); 1673 1674 if (count <= 0) 1675 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1676} 1677 1678static int 1679fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1680{ 1681 struct fxp_softc *sc = ifp->if_softc; 1682 struct ifreq *ifr = (struct ifreq *)data; 1683 struct mii_data *mii; 1684 int s, error = 0; 1685 1686 s = splimp(); 1687 1688 switch (command) { 1689 case SIOCSIFADDR: 1690 case SIOCGIFADDR: 1691 case SIOCSIFMTU: 1692 error = ether_ioctl(ifp, command, data); 1693 break; 1694 1695 case SIOCSIFFLAGS: 1696 if (ifp->if_flags & IFF_ALLMULTI) 1697 sc->flags |= FXP_FLAG_ALL_MCAST; 1698 else 1699 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1700 1701 /* 1702 * If interface is marked up and not running, then start it. 1703 * If it is marked down and running, stop it. 1704 * XXX If it's up then re-initialize it. This is so flags 1705 * such as IFF_PROMISC are handled. 1706 */ 1707 if (ifp->if_flags & IFF_UP) { 1708 fxp_init(sc); 1709 } else { 1710 if (ifp->if_flags & IFF_RUNNING) 1711 fxp_stop(sc); 1712 } 1713 break; 1714 1715 case SIOCADDMULTI: 1716 case SIOCDELMULTI: 1717 if (ifp->if_flags & IFF_ALLMULTI) 1718 sc->flags |= FXP_FLAG_ALL_MCAST; 1719 else 1720 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1721 /* 1722 * Multicast list has changed; set the hardware filter 1723 * accordingly. 1724 */ 1725 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1726 fxp_mc_setup(sc); 1727 /* 1728 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1729 * again rather than else {}. 1730 */ 1731 if (sc->flags & FXP_FLAG_ALL_MCAST) 1732 fxp_init(sc); 1733 error = 0; 1734 break; 1735 1736 case SIOCSIFMEDIA: 1737 case SIOCGIFMEDIA: 1738 if (sc->miibus != NULL) { 1739 mii = device_get_softc(sc->miibus); 1740 error = ifmedia_ioctl(ifp, ifr, 1741 &mii->mii_media, command); 1742 } else { 1743 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1744 } 1745 break; 1746 1747 default: 1748 error = EINVAL; 1749 } 1750 splx(s); 1751 return (error); 1752} 1753 1754/* 1755 * Program the multicast filter. 1756 * 1757 * We have an artificial restriction that the multicast setup command 1758 * must be the first command in the chain, so we take steps to ensure 1759 * this. By requiring this, it allows us to keep up the performance of 1760 * the pre-initialized command ring (esp. link pointers) by not actually 1761 * inserting the mcsetup command in the ring - i.e. its link pointer 1762 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1763 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1764 * lead into the regular TxCB ring when it completes. 1765 * 1766 * This function must be called at splimp. 1767 */ 1768static void 1769fxp_mc_setup(struct fxp_softc *sc) 1770{ 1771 struct fxp_cb_mcs *mcsp = sc->mcsp; 1772 struct ifnet *ifp = &sc->sc_if; 1773 struct ifmultiaddr *ifma; 1774 int nmcasts; 1775 int count; 1776 1777 /* 1778 * If there are queued commands, we must wait until they are all 1779 * completed. If we are already waiting, then add a NOP command 1780 * with interrupt option so that we're notified when all commands 1781 * have been completed - fxp_start() ensures that no additional 1782 * TX commands will be added when need_mcsetup is true. 1783 */ 1784 if (sc->tx_queued) { 1785 struct fxp_cb_tx *txp; 1786 1787 /* 1788 * need_mcsetup will be true if we are already waiting for the 1789 * NOP command to be completed (see below). In this case, bail. 1790 */ 1791 if (sc->need_mcsetup) 1792 return; 1793 sc->need_mcsetup = 1; 1794 1795 /* 1796 * Add a NOP command with interrupt so that we are notified when all 1797 * TX commands have been processed. 1798 */ 1799 txp = sc->cbl_last->next; 1800 txp->mb_head = NULL; 1801 txp->cb_status = 0; 1802 txp->cb_command = FXP_CB_COMMAND_NOP | 1803 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1804 /* 1805 * Advance the end of list forward. 1806 */ 1807 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1808 sc->cbl_last = txp; 1809 sc->tx_queued++; 1810 /* 1811 * Issue a resume in case the CU has just suspended. 1812 */ 1813 fxp_scb_wait(sc); 1814 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1815 /* 1816 * Set a 5 second timer just in case we don't hear from the 1817 * card again. 1818 */ 1819 ifp->if_timer = 5; 1820 1821 return; 1822 } 1823 sc->need_mcsetup = 0; 1824 1825 /* 1826 * Initialize multicast setup descriptor. 1827 */ 1828 mcsp->next = sc->cbl_base; 1829 mcsp->mb_head = NULL; 1830 mcsp->cb_status = 0; 1831 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 1832 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1833 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1834 1835 nmcasts = 0; 1836 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 1837#if __FreeBSD_version < 500000 1838 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1839#else 1840 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1841#endif 1842 if (ifma->ifma_addr->sa_family != AF_LINK) 1843 continue; 1844 if (nmcasts >= MAXMCADDR) { 1845 sc->flags |= FXP_FLAG_ALL_MCAST; 1846 nmcasts = 0; 1847 break; 1848 } 1849 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1850 (void *)(uintptr_t)(volatile void *) 1851 &sc->mcsp->mc_addr[nmcasts][0], 6); 1852 nmcasts++; 1853 } 1854 } 1855 mcsp->mc_cnt = nmcasts * 6; 1856 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1857 sc->tx_queued = 1; 1858 1859 /* 1860 * Wait until command unit is not active. This should never 1861 * be the case when nothing is queued, but make sure anyway. 1862 */ 1863 count = 100; 1864 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1865 FXP_SCB_CUS_ACTIVE && --count) 1866 DELAY(10); 1867 if (count == 0) { 1868 device_printf(sc->dev, "command queue timeout\n"); 1869 return; 1870 } 1871 1872 /* 1873 * Start the multicast setup command. 1874 */ 1875 fxp_scb_wait(sc); 1876 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1877 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1878 1879 ifp->if_timer = 2; 1880 return; 1881} 1882