if_fxp.c revision 74178
1/*- 2 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 3 * Copyright (c) 1995, David Greenman 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 74178 2001-03-12 21:30:52Z jlemon $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_dl.h> 45#include <net/if_media.h> 46 47#ifdef NS 48#include <netns/ns.h> 49#include <netns/ns_if.h> 50#endif 51 52#include <net/bpf.h> 53#include <sys/sockio.h> 54#include <sys/bus.h> 55#include <machine/bus.h> 56#include <sys/rman.h> 57#include <machine/resource.h> 58 59#include <net/ethernet.h> 60#include <net/if_arp.h> 61 62#include <vm/vm.h> /* for vtophys */ 63#include <vm/pmap.h> /* for vtophys */ 64#include <machine/clock.h> /* for DELAY */ 65 66#include <pci/pcivar.h> 67#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include <dev/fxp/if_fxpreg.h> 73#include <dev/fxp/if_fxpvar.h> 74 75MODULE_DEPEND(fxp, miibus, 1, 1, 1); 76#include "miibus_if.h" 77 78/* 79 * NOTE! On the Alpha, we have an alignment constraint. The 80 * card DMAs the packet immediately following the RFA. However, 81 * the first thing in the packet is a 14-byte Ethernet header. 82 * This means that the packet is misaligned. To compensate, 83 * we actually offset the RFA 2 bytes into the cluster. This 84 * alignes the packet after the Ethernet header at a 32-bit 85 * boundary. HOWEVER! This means that the RFA is misaligned! 86 */ 87#define RFA_ALIGNMENT_FUDGE 2 88 89/* 90 * Set initial transmit threshold at 64 (512 bytes). This is 91 * increased by 64 (512 bytes) at a time, to maximum of 192 92 * (1536 bytes), if an underrun occurs. 93 */ 94static int tx_threshold = 64; 95 96/* 97 * The configuration byte map has several undefined fields which 98 * must be one or must be zero. Set up a template for these bits 99 * only, (assuming a 82557 chip) leaving the actual configuration 100 * to fxp_init. 101 * 102 * See struct fxp_cb_config for the bit definitions. 103 */ 104static u_char fxp_cb_config_template[] = { 105 0x0, 0x0, /* cb_status */ 106 0x0, 0x0, /* cb_command */ 107 0x0, 0x0, 0x0, 0x0, /* link_addr */ 108 0x0, /* 0 */ 109 0x0, /* 1 */ 110 0x0, /* 2 */ 111 0x0, /* 3 */ 112 0x0, /* 4 */ 113 0x0, /* 5 */ 114 0x32, /* 6 */ 115 0x0, /* 7 */ 116 0x0, /* 8 */ 117 0x0, /* 9 */ 118 0x6, /* 10 */ 119 0x0, /* 11 */ 120 0x0, /* 12 */ 121 0x0, /* 13 */ 122 0xf2, /* 14 */ 123 0x48, /* 15 */ 124 0x0, /* 16 */ 125 0x40, /* 17 */ 126 0xf0, /* 18 */ 127 0x0, /* 19 */ 128 0x3f, /* 20 */ 129 0x5 /* 21 */ 130}; 131 132struct fxp_ident { 133 u_int16_t devid; 134 char *name; 135}; 136 137/* 138 * Claim various Intel PCI device identifiers for this driver. The 139 * sub-vendor and sub-device field are extensively used to identify 140 * particular variants, but we don't currently differentiate between 141 * them. 142 */ 143static struct fxp_ident fxp_ident_table[] = { 144 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 145 { 0x2449, "Intel Pro/100 Ethernet" }, 146 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 147 { 0x1029, "Intel Pro/100 Ethernet" }, 148 { 0x1030, "Intel Pro/100 Ethernet" }, 149 { 0x1031, "Intel Pro/100 Ethernet" }, 150 { 0x1032, "Intel Pro/100 Ethernet" }, 151 { 0x1033, "Intel Pro/100 Ethernet" }, 152 { 0x1034, "Intel Pro/100 Ethernet" }, 153 { 0x1035, "Intel Pro/100 Ethernet" }, 154 { 0x1036, "Intel Pro/100 Ethernet" }, 155 { 0x1037, "Intel Pro/100 Ethernet" }, 156 { 0x1038, "Intel Pro/100 Ethernet" }, 157 { 0, NULL }, 158}; 159 160static int fxp_probe(device_t dev); 161static int fxp_attach(device_t dev); 162static int fxp_detach(device_t dev); 163static int fxp_shutdown(device_t dev); 164static int fxp_suspend(device_t dev); 165static int fxp_resume(device_t dev); 166 167static void fxp_intr(void *xsc); 168static void fxp_init(void *xsc); 169static void fxp_tick(void *xsc); 170static void fxp_start(struct ifnet *ifp); 171static void fxp_stop(struct fxp_softc *sc); 172static void fxp_release(struct fxp_softc *sc); 173static int fxp_ioctl(struct ifnet *ifp, u_long command, 174 caddr_t data); 175static void fxp_watchdog(struct ifnet *ifp); 176static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 177static void fxp_mc_setup(struct fxp_softc *sc); 178static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 179 int autosize); 180static void fxp_autosize_eeprom(struct fxp_softc *sc); 181static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 182 int offset, int words); 183static int fxp_ifmedia_upd(struct ifnet *ifp); 184static void fxp_ifmedia_sts(struct ifnet *ifp, 185 struct ifmediareq *ifmr); 186static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 187static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 188 struct ifmediareq *ifmr); 189static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 190static void fxp_miibus_writereg(device_t dev, int phy, int reg, 191 int value); 192static __inline void fxp_lwcopy(volatile u_int32_t *src, 193 volatile u_int32_t *dst); 194static __inline void fxp_scb_wait(struct fxp_softc *sc); 195static __inline void fxp_dma_wait(volatile u_int16_t *status, 196 struct fxp_softc *sc); 197 198static device_method_t fxp_methods[] = { 199 /* Device interface */ 200 DEVMETHOD(device_probe, fxp_probe), 201 DEVMETHOD(device_attach, fxp_attach), 202 DEVMETHOD(device_detach, fxp_detach), 203 DEVMETHOD(device_shutdown, fxp_shutdown), 204 DEVMETHOD(device_suspend, fxp_suspend), 205 DEVMETHOD(device_resume, fxp_resume), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 209 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 210 211 { 0, 0 } 212}; 213 214static driver_t fxp_driver = { 215 "fxp", 216 fxp_methods, 217 sizeof(struct fxp_softc), 218}; 219 220static devclass_t fxp_devclass; 221 222DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 223DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 224DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 225 226/* 227 * Inline function to copy a 16-bit aligned 32-bit quantity. 228 */ 229static __inline void 230fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 231{ 232#ifdef __i386__ 233 *dst = *src; 234#else 235 volatile u_int16_t *a = (volatile u_int16_t *)src; 236 volatile u_int16_t *b = (volatile u_int16_t *)dst; 237 238 b[0] = a[0]; 239 b[1] = a[1]; 240#endif 241} 242 243/* 244 * Wait for the previous command to be accepted (but not necessarily 245 * completed). 246 */ 247static __inline void 248fxp_scb_wait(struct fxp_softc *sc) 249{ 250 int i = 10000; 251 252 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 253 DELAY(2); 254 if (i == 0) 255 device_printf(sc->dev, "SCB timeout\n"); 256} 257 258static __inline void 259fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 260{ 261 int i = 10000; 262 263 while (!(*status & FXP_CB_STATUS_C) && --i) 264 DELAY(2); 265 if (i == 0) 266 device_printf(sc->dev, "DMA timeout\n"); 267} 268 269/* 270 * Return identification string if this is device is ours. 271 */ 272static int 273fxp_probe(device_t dev) 274{ 275 u_int16_t devid; 276 struct fxp_ident *ident; 277 278 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 279 devid = pci_get_device(dev); 280 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 281 if (ident->devid == devid) { 282 device_set_desc(dev, ident->name); 283 return (0); 284 } 285 } 286 } 287 return (ENXIO); 288} 289 290static int 291fxp_attach(device_t dev) 292{ 293 int error = 0; 294 struct fxp_softc *sc = device_get_softc(dev); 295 struct ifnet *ifp; 296 u_int32_t val; 297 u_int16_t data; 298 int i, rid, m1, m2, prefer_iomap; 299 int s; 300 301 bzero(sc, sizeof(*sc)); 302 sc->dev = dev; 303 callout_handle_init(&sc->stat_ch); 304 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 305 306 s = splimp(); 307 308 /* 309 * Enable bus mastering. Enable memory space too, in case 310 * BIOS/Prom forgot about it. 311 */ 312 val = pci_read_config(dev, PCIR_COMMAND, 2); 313 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 314 pci_write_config(dev, PCIR_COMMAND, val, 2); 315 val = pci_read_config(dev, PCIR_COMMAND, 2); 316 317#if __FreeBSD_version >= 500000 318 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 319 u_int32_t iobase, membase, irq; 320 321 /* Save important PCI config data. */ 322 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 323 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 324 irq = pci_read_config(dev, PCIR_INTLINE, 4); 325 326 /* Reset the power state. */ 327 device_printf(dev, "chip is in D%d power mode " 328 "-- setting to D0\n", pci_get_powerstate(dev)); 329 330 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 331 332 /* Restore PCI config data. */ 333 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 334 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 335 pci_write_config(dev, PCIR_INTLINE, irq, 4); 336 } 337#endif 338 339 /* 340 * Figure out which we should try first - memory mapping or i/o mapping? 341 * We default to memory mapping. Then we accept an override from the 342 * command line. Then we check to see which one is enabled. 343 */ 344 m1 = PCIM_CMD_MEMEN; 345 m2 = PCIM_CMD_PORTEN; 346 prefer_iomap = 0; 347 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 348 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 349 m1 = PCIM_CMD_PORTEN; 350 m2 = PCIM_CMD_MEMEN; 351 } 352 353 if (val & m1) { 354 sc->rtp = 355 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 356 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 357 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 358 0, ~0, 1, RF_ACTIVE); 359 } 360 if (sc->mem == NULL && (val & m2)) { 361 sc->rtp = 362 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 363 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 364 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 365 0, ~0, 1, RF_ACTIVE); 366 } 367 368 if (!sc->mem) { 369 device_printf(dev, "could not map device registers\n"); 370 error = ENXIO; 371 goto fail; 372 } 373 if (bootverbose) { 374 device_printf(dev, "using %s space register mapping\n", 375 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 376 } 377 378 sc->sc_st = rman_get_bustag(sc->mem); 379 sc->sc_sh = rman_get_bushandle(sc->mem); 380 381 /* 382 * Allocate our interrupt. 383 */ 384 rid = 0; 385 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 386 RF_SHAREABLE | RF_ACTIVE); 387 if (sc->irq == NULL) { 388 device_printf(dev, "could not map interrupt\n"); 389 error = ENXIO; 390 goto fail; 391 } 392 393 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 394 fxp_intr, sc, &sc->ih); 395 if (error) { 396 device_printf(dev, "could not setup irq\n"); 397 goto fail; 398 } 399 400 /* 401 * Reset to a stable state. 402 */ 403 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 404 DELAY(10); 405 406 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 407 M_DEVBUF, M_NOWAIT | M_ZERO); 408 if (sc->cbl_base == NULL) 409 goto failmem; 410 411 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 412 M_NOWAIT | M_ZERO); 413 if (sc->fxp_stats == NULL) 414 goto failmem; 415 416 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 417 if (sc->mcsp == NULL) 418 goto failmem; 419 420 /* 421 * Pre-allocate our receive buffers. 422 */ 423 for (i = 0; i < FXP_NRFABUFS; i++) { 424 if (fxp_add_rfabuf(sc, NULL) != 0) { 425 goto failmem; 426 } 427 } 428 429 /* 430 * Find out how large of an SEEPROM we have. 431 */ 432 fxp_autosize_eeprom(sc); 433 434 /* 435 * Determine in whether we must use the 503 serial interface. 436 */ 437 fxp_read_eeprom(sc, &data, 6, 1); 438 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 439 (data & FXP_PHY_SERIAL_ONLY)) 440 sc->flags &= FXP_FLAG_SERIAL_MEDIA; 441 442 /* 443 * Read MAC address. 444 */ 445 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 446 device_printf(dev, "Ethernet address %6D%s\n", 447 sc->arpcom.ac_enaddr, ":", 448 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 449 if (bootverbose) { 450 device_printf(dev, "PCI IDs: %04x %04x %04x %04x\n", 451 pci_get_vendor(dev), pci_get_device(dev), 452 pci_get_subvendor(dev), pci_get_subdevice(dev)); 453 } 454 455 /* 456 * If this is only a 10Mbps device, then there is no MII, and 457 * the PHY will use a serial interface instead. 458 * 459 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 460 * doesn't have a programming interface of any sort. The 461 * media is sensed automatically based on how the link partner 462 * is configured. This is, in essence, manual configuration. 463 */ 464 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 465 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 466 fxp_serial_ifmedia_sts); 467 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 468 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 469 } else { 470 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 471 fxp_ifmedia_sts)) { 472 device_printf(dev, "MII without any PHY!\n"); 473 error = ENXIO; 474 goto fail; 475 } 476 } 477 478 ifp = &sc->arpcom.ac_if; 479 ifp->if_unit = device_get_unit(dev); 480 ifp->if_name = "fxp"; 481 ifp->if_output = ether_output; 482 ifp->if_baudrate = 100000000; 483 ifp->if_init = fxp_init; 484 ifp->if_softc = sc; 485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 486 ifp->if_ioctl = fxp_ioctl; 487 ifp->if_start = fxp_start; 488 ifp->if_watchdog = fxp_watchdog; 489 490 /* 491 * Attach the interface. 492 */ 493 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 494 495 /* 496 * Let the system queue as many packets as we have available 497 * TX descriptors. 498 */ 499 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 500 501 splx(s); 502 return (0); 503 504failmem: 505 device_printf(dev, "Failed to malloc memory\n"); 506 error = ENOMEM; 507fail: 508 splx(s); 509 fxp_release(sc); 510 return (error); 511} 512 513/* 514 * release all resources 515 */ 516static void 517fxp_release(struct fxp_softc *sc) 518{ 519 520 if (sc->miibus) { 521 bus_generic_detach(sc->dev); 522 device_delete_child(sc->dev, sc->miibus); 523 } 524 525 if (sc->cbl_base) 526 free(sc->cbl_base, M_DEVBUF); 527 if (sc->fxp_stats) 528 free(sc->fxp_stats, M_DEVBUF); 529 if (sc->mcsp) 530 free(sc->mcsp, M_DEVBUF); 531 if (sc->rfa_headm) 532 m_freem(sc->rfa_headm); 533 534 if (sc->ih) 535 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 536 if (sc->irq) 537 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 538 if (sc->mem) 539 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 540 mtx_destroy(&sc->sc_mtx); 541} 542 543/* 544 * Detach interface. 545 */ 546static int 547fxp_detach(device_t dev) 548{ 549 struct fxp_softc *sc = device_get_softc(dev); 550 int s; 551 552 s = splimp(); 553 554 /* 555 * Stop DMA and drop transmit queue. 556 */ 557 fxp_stop(sc); 558 559 /* 560 * Close down routes etc. 561 */ 562 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 563 564 /* 565 * Free all media structures. 566 */ 567 ifmedia_removeall(&sc->sc_media); 568 569 splx(s); 570 571 /* Release our allocated resources. */ 572 fxp_release(sc); 573 574 return (0); 575} 576 577/* 578 * Device shutdown routine. Called at system shutdown after sync. The 579 * main purpose of this routine is to shut off receiver DMA so that 580 * kernel memory doesn't get clobbered during warmboot. 581 */ 582static int 583fxp_shutdown(device_t dev) 584{ 585 /* 586 * Make sure that DMA is disabled prior to reboot. Not doing 587 * do could allow DMA to corrupt kernel memory during the 588 * reboot before the driver initializes. 589 */ 590 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 591 return (0); 592} 593 594/* 595 * Device suspend routine. Stop the interface and save some PCI 596 * settings in case the BIOS doesn't restore them properly on 597 * resume. 598 */ 599static int 600fxp_suspend(device_t dev) 601{ 602 struct fxp_softc *sc = device_get_softc(dev); 603 int i, s; 604 605 s = splimp(); 606 607 fxp_stop(sc); 608 609 for (i=0; i<5; i++) 610 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 611 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 612 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 613 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 614 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 615 616 sc->suspended = 1; 617 618 splx(s); 619 return (0); 620} 621 622/* 623 * Device resume routine. Restore some PCI settings in case the BIOS 624 * doesn't, re-enable busmastering, and restart the interface if 625 * appropriate. 626 */ 627static int 628fxp_resume(device_t dev) 629{ 630 struct fxp_softc *sc = device_get_softc(dev); 631 struct ifnet *ifp = &sc->sc_if; 632 u_int16_t pci_command; 633 int i, s; 634 635 s = splimp(); 636 637 /* better way to do this? */ 638 for (i=0; i<5; i++) 639 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 640 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 641 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 642 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 643 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 644 645 /* reenable busmastering */ 646 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 647 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 648 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 649 650 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 651 DELAY(10); 652 653 /* reinitialize interface if necessary */ 654 if (ifp->if_flags & IFF_UP) 655 fxp_init(sc); 656 657 sc->suspended = 0; 658 659 splx(s); 660 return (0); 661} 662 663/* 664 * Read from the serial EEPROM. Basically, you manually shift in 665 * the read opcode (one bit at a time) and then shift in the address, 666 * and then you shift out the data (all of this one bit at a time). 667 * The word size is 16 bits, so you have to provide the address for 668 * every 16 bits of data. 669 */ 670static u_int16_t 671fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 672{ 673 u_int16_t reg, data; 674 int x; 675 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 677 /* 678 * Shift in read opcode. 679 */ 680 for (x = 1 << 2; x; x >>= 1) { 681 if (FXP_EEPROM_OPC_READ & x) 682 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 683 else 684 reg = FXP_EEPROM_EECS; 685 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 686 DELAY(1); 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 688 DELAY(1); 689 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 690 DELAY(1); 691 } 692 /* 693 * Shift in address. 694 */ 695 data = 0; 696 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 697 if (offset & x) 698 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 699 else 700 reg = FXP_EEPROM_EECS; 701 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 702 DELAY(1); 703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 704 DELAY(1); 705 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 706 DELAY(1); 707 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 708 data++; 709 if (autosize && reg == 0) { 710 sc->eeprom_size = data; 711 break; 712 } 713 } 714 /* 715 * Shift out data. 716 */ 717 data = 0; 718 reg = FXP_EEPROM_EECS; 719 for (x = 1 << 15; x; x >>= 1) { 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 721 DELAY(1); 722 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 723 data |= x; 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 725 DELAY(1); 726 } 727 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 728 DELAY(1); 729 730 return (data); 731} 732 733/* 734 * From NetBSD: 735 * 736 * Figure out EEPROM size. 737 * 738 * 559's can have either 64-word or 256-word EEPROMs, the 558 739 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 740 * talks about the existance of 16 to 256 word EEPROMs. 741 * 742 * The only known sizes are 64 and 256, where the 256 version is used 743 * by CardBus cards to store CIS information. 744 * 745 * The address is shifted in msb-to-lsb, and after the last 746 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 747 * after which follows the actual data. We try to detect this zero, by 748 * probing the data-out bit in the EEPROM control register just after 749 * having shifted in a bit. If the bit is zero, we assume we've 750 * shifted enough address bits. The data-out should be tri-state, 751 * before this, which should translate to a logical one. 752 * 753 * Other ways to do this would be to try to read a register with known 754 * contents with a varying number of address bits, but no such 755 * register seem to be available. The high bits of register 10 are 01 756 * on the 558 and 559, but apparently not on the 557. 757 * 758 * The Linux driver computes a checksum on the EEPROM data, but the 759 * value of this checksum is not very well documented. 760 */ 761static void 762fxp_autosize_eeprom(struct fxp_softc *sc) 763{ 764 765 /* guess maximum size of 256 words */ 766 sc->eeprom_size = 8; 767 768 /* autosize */ 769 (void) fxp_eeprom_getword(sc, 0, 1); 770} 771 772static void 773fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 774{ 775 int i; 776 777 for (i = 0; i < words; i++) 778 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 779} 780 781/* 782 * Start packet transmission on the interface. 783 */ 784static void 785fxp_start(struct ifnet *ifp) 786{ 787 struct fxp_softc *sc = ifp->if_softc; 788 struct fxp_cb_tx *txp; 789 790 /* 791 * See if we need to suspend xmit until the multicast filter 792 * has been reprogrammed (which can only be done at the head 793 * of the command chain). 794 */ 795 if (sc->need_mcsetup) { 796 return; 797 } 798 799 txp = NULL; 800 801 /* 802 * We're finished if there is nothing more to add to the list or if 803 * we're all filled up with buffers to transmit. 804 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 805 * a NOP command when needed. 806 */ 807 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 808 struct mbuf *m, *mb_head; 809 int segment; 810 811 /* 812 * Grab a packet to transmit. 813 */ 814 IF_DEQUEUE(&ifp->if_snd, mb_head); 815 816 /* 817 * Get pointer to next available tx desc. 818 */ 819 txp = sc->cbl_last->next; 820 821 /* 822 * Go through each of the mbufs in the chain and initialize 823 * the transmit buffer descriptors with the physical address 824 * and size of the mbuf. 825 */ 826tbdinit: 827 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 828 if (m->m_len != 0) { 829 if (segment == FXP_NTXSEG) 830 break; 831 txp->tbd[segment].tb_addr = 832 vtophys(mtod(m, vm_offset_t)); 833 txp->tbd[segment].tb_size = m->m_len; 834 segment++; 835 } 836 } 837 if (m != NULL) { 838 struct mbuf *mn; 839 840 /* 841 * We ran out of segments. We have to recopy this mbuf 842 * chain first. Bail out if we can't get the new buffers. 843 */ 844 MGETHDR(mn, M_DONTWAIT, MT_DATA); 845 if (mn == NULL) { 846 m_freem(mb_head); 847 break; 848 } 849 if (mb_head->m_pkthdr.len > MHLEN) { 850 MCLGET(mn, M_DONTWAIT); 851 if ((mn->m_flags & M_EXT) == 0) { 852 m_freem(mn); 853 m_freem(mb_head); 854 break; 855 } 856 } 857 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 858 mtod(mn, caddr_t)); 859 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 860 m_freem(mb_head); 861 mb_head = mn; 862 goto tbdinit; 863 } 864 865 txp->tbd_number = segment; 866 txp->mb_head = mb_head; 867 txp->cb_status = 0; 868 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 869 txp->cb_command = 870 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 871 } else { 872 txp->cb_command = 873 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 874 /* 875 * Set a 5 second timer just in case we don't hear from the 876 * card again. 877 */ 878 ifp->if_timer = 5; 879 } 880 txp->tx_threshold = tx_threshold; 881 882 /* 883 * Advance the end of list forward. 884 */ 885 886#ifdef __alpha__ 887 /* 888 * On platforms which can't access memory in 16-bit 889 * granularities, we must prevent the card from DMA'ing 890 * up the status while we update the command field. 891 * This could cause us to overwrite the completion status. 892 */ 893 atomic_clear_short(&sc->cbl_last->cb_command, 894 FXP_CB_COMMAND_S); 895#else 896 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 897#endif /*__alpha__*/ 898 sc->cbl_last = txp; 899 900 /* 901 * Advance the beginning of the list forward if there are 902 * no other packets queued (when nothing is queued, cbl_first 903 * sits on the last TxCB that was sent out). 904 */ 905 if (sc->tx_queued == 0) 906 sc->cbl_first = txp; 907 908 sc->tx_queued++; 909 910 /* 911 * Pass packet to bpf if there is a listener. 912 */ 913 if (ifp->if_bpf) 914 bpf_mtap(ifp, mb_head); 915 } 916 917 /* 918 * We're finished. If we added to the list, issue a RESUME to get DMA 919 * going again if suspended. 920 */ 921 if (txp != NULL) { 922 fxp_scb_wait(sc); 923 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 924 } 925} 926 927/* 928 * Process interface interrupts. 929 */ 930static void 931fxp_intr(void *xsc) 932{ 933 struct fxp_softc *sc = xsc; 934 struct ifnet *ifp = &sc->sc_if; 935 u_int8_t statack; 936 937 938 if (sc->suspended) { 939 return; 940 } 941 942 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 943 /* 944 * First ACK all the interrupts in this pass. 945 */ 946 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 947 948 /* 949 * Free any finished transmit mbuf chains. 950 * 951 * Handle the CNA event likt a CXTNO event. It used to 952 * be that this event (control unit not ready) was not 953 * encountered, but it is now with the SMPng modifications. 954 * The exact sequence of events that occur when the interface 955 * is brought up are different now, and if this event 956 * goes unhandled, the configuration/rxfilter setup sequence 957 * can stall for several seconds. The result is that no 958 * packets go out onto the wire for about 5 to 10 seconds 959 * after the interface is ifconfig'ed for the first time. 960 */ 961 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 962 struct fxp_cb_tx *txp; 963 964 for (txp = sc->cbl_first; sc->tx_queued && 965 (txp->cb_status & FXP_CB_STATUS_C) != 0; 966 txp = txp->next) { 967 if (txp->mb_head != NULL) { 968 m_freem(txp->mb_head); 969 txp->mb_head = NULL; 970 } 971 sc->tx_queued--; 972 } 973 sc->cbl_first = txp; 974 ifp->if_timer = 0; 975 if (sc->tx_queued == 0) { 976 if (sc->need_mcsetup) 977 fxp_mc_setup(sc); 978 } 979 /* 980 * Try to start more packets transmitting. 981 */ 982 if (ifp->if_snd.ifq_head != NULL) 983 fxp_start(ifp); 984 } 985 /* 986 * Process receiver interrupts. If a no-resource (RNR) 987 * condition exists, get whatever packets we can and 988 * re-start the receiver. 989 */ 990 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 991 struct mbuf *m; 992 struct fxp_rfa *rfa; 993rcvloop: 994 m = sc->rfa_headm; 995 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 996 RFA_ALIGNMENT_FUDGE); 997 998 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 999 /* 1000 * Remove first packet from the chain. 1001 */ 1002 sc->rfa_headm = m->m_next; 1003 m->m_next = NULL; 1004 1005 /* 1006 * Add a new buffer to the receive chain. 1007 * If this fails, the old buffer is recycled 1008 * instead. 1009 */ 1010 if (fxp_add_rfabuf(sc, m) == 0) { 1011 struct ether_header *eh; 1012 int total_len; 1013 1014 total_len = rfa->actual_size & 1015 (MCLBYTES - 1); 1016 if (total_len < 1017 sizeof(struct ether_header)) { 1018 m_freem(m); 1019 goto rcvloop; 1020 } 1021 m->m_pkthdr.rcvif = ifp; 1022 m->m_pkthdr.len = m->m_len = total_len; 1023 eh = mtod(m, struct ether_header *); 1024 m->m_data += 1025 sizeof(struct ether_header); 1026 m->m_len -= 1027 sizeof(struct ether_header); 1028 m->m_pkthdr.len = m->m_len; 1029 ether_input(ifp, eh, m); 1030 } 1031 goto rcvloop; 1032 } 1033 if (statack & FXP_SCB_STATACK_RNR) { 1034 fxp_scb_wait(sc); 1035 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1036 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1037 RFA_ALIGNMENT_FUDGE); 1038 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1039 FXP_SCB_COMMAND_RU_START); 1040 } 1041 } 1042 } 1043} 1044 1045/* 1046 * Update packet in/out/collision statistics. The i82557 doesn't 1047 * allow you to access these counters without doing a fairly 1048 * expensive DMA to get _all_ of the statistics it maintains, so 1049 * we do this operation here only once per second. The statistics 1050 * counters in the kernel are updated from the previous dump-stats 1051 * DMA and then a new dump-stats DMA is started. The on-chip 1052 * counters are zeroed when the DMA completes. If we can't start 1053 * the DMA immediately, we don't wait - we just prepare to read 1054 * them again next time. 1055 */ 1056static void 1057fxp_tick(void *xsc) 1058{ 1059 struct fxp_softc *sc = xsc; 1060 struct ifnet *ifp = &sc->sc_if; 1061 struct fxp_stats *sp = sc->fxp_stats; 1062 struct fxp_cb_tx *txp; 1063 int s; 1064 1065 ifp->if_opackets += sp->tx_good; 1066 ifp->if_collisions += sp->tx_total_collisions; 1067 if (sp->rx_good) { 1068 ifp->if_ipackets += sp->rx_good; 1069 sc->rx_idle_secs = 0; 1070 } else { 1071 /* 1072 * Receiver's been idle for another second. 1073 */ 1074 sc->rx_idle_secs++; 1075 } 1076 ifp->if_ierrors += 1077 sp->rx_crc_errors + 1078 sp->rx_alignment_errors + 1079 sp->rx_rnr_errors + 1080 sp->rx_overrun_errors; 1081 /* 1082 * If any transmit underruns occured, bump up the transmit 1083 * threshold by another 512 bytes (64 * 8). 1084 */ 1085 if (sp->tx_underruns) { 1086 ifp->if_oerrors += sp->tx_underruns; 1087 if (tx_threshold < 192) 1088 tx_threshold += 64; 1089 } 1090 s = splimp(); 1091 /* 1092 * Release any xmit buffers that have completed DMA. This isn't 1093 * strictly necessary to do here, but it's advantagous for mbufs 1094 * with external storage to be released in a timely manner rather 1095 * than being defered for a potentially long time. This limits 1096 * the delay to a maximum of one second. 1097 */ 1098 for (txp = sc->cbl_first; sc->tx_queued && 1099 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1100 txp = txp->next) { 1101 if (txp->mb_head != NULL) { 1102 m_freem(txp->mb_head); 1103 txp->mb_head = NULL; 1104 } 1105 sc->tx_queued--; 1106 } 1107 sc->cbl_first = txp; 1108 /* 1109 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1110 * then assume the receiver has locked up and attempt to clear 1111 * the condition by reprogramming the multicast filter. This is 1112 * a work-around for a bug in the 82557 where the receiver locks 1113 * up if it gets certain types of garbage in the syncronization 1114 * bits prior to the packet header. This bug is supposed to only 1115 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1116 * mode as well (perhaps due to a 10/100 speed transition). 1117 */ 1118 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1119 sc->rx_idle_secs = 0; 1120 fxp_mc_setup(sc); 1121 } 1122 /* 1123 * If there is no pending command, start another stats 1124 * dump. Otherwise punt for now. 1125 */ 1126 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1127 /* 1128 * Start another stats dump. 1129 */ 1130 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1131 FXP_SCB_COMMAND_CU_DUMPRESET); 1132 } else { 1133 /* 1134 * A previous command is still waiting to be accepted. 1135 * Just zero our copy of the stats and wait for the 1136 * next timer event to update them. 1137 */ 1138 sp->tx_good = 0; 1139 sp->tx_underruns = 0; 1140 sp->tx_total_collisions = 0; 1141 1142 sp->rx_good = 0; 1143 sp->rx_crc_errors = 0; 1144 sp->rx_alignment_errors = 0; 1145 sp->rx_rnr_errors = 0; 1146 sp->rx_overrun_errors = 0; 1147 } 1148 1149 if (sc->miibus != NULL) 1150 mii_tick(device_get_softc(sc->miibus)); 1151 1152 /* 1153 * Schedule another timeout one second from now. 1154 */ 1155 sc->stat_ch = timeout(fxp_tick, sc, hz); 1156} 1157 1158/* 1159 * Stop the interface. Cancels the statistics updater and resets 1160 * the interface. 1161 */ 1162static void 1163fxp_stop(struct fxp_softc *sc) 1164{ 1165 struct ifnet *ifp = &sc->sc_if; 1166 struct fxp_cb_tx *txp; 1167 int i; 1168 1169 1170 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1171 ifp->if_timer = 0; 1172 1173 /* 1174 * Cancel stats updater. 1175 */ 1176 untimeout(fxp_tick, sc, sc->stat_ch); 1177 1178 /* 1179 * Issue software reset 1180 */ 1181 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1182 DELAY(10); 1183 1184 /* 1185 * Release any xmit buffers. 1186 */ 1187 txp = sc->cbl_base; 1188 if (txp != NULL) { 1189 for (i = 0; i < FXP_NTXCB; i++) { 1190 if (txp[i].mb_head != NULL) { 1191 m_freem(txp[i].mb_head); 1192 txp[i].mb_head = NULL; 1193 } 1194 } 1195 } 1196 sc->tx_queued = 0; 1197 1198 /* 1199 * Free all the receive buffers then reallocate/reinitialize 1200 */ 1201 if (sc->rfa_headm != NULL) 1202 m_freem(sc->rfa_headm); 1203 sc->rfa_headm = NULL; 1204 sc->rfa_tailm = NULL; 1205 for (i = 0; i < FXP_NRFABUFS; i++) { 1206 if (fxp_add_rfabuf(sc, NULL) != 0) { 1207 /* 1208 * This "can't happen" - we're at splimp() 1209 * and we just freed all the buffers we need 1210 * above. 1211 */ 1212 panic("fxp_stop: no buffers!"); 1213 } 1214 } 1215} 1216 1217/* 1218 * Watchdog/transmission transmit timeout handler. Called when a 1219 * transmission is started on the interface, but no interrupt is 1220 * received before the timeout. This usually indicates that the 1221 * card has wedged for some reason. 1222 */ 1223static void 1224fxp_watchdog(struct ifnet *ifp) 1225{ 1226 struct fxp_softc *sc = ifp->if_softc; 1227 1228 device_printf(sc->dev, "device timeout\n"); 1229 ifp->if_oerrors++; 1230 1231 fxp_init(sc); 1232} 1233 1234static void 1235fxp_init(void *xsc) 1236{ 1237 struct fxp_softc *sc = xsc; 1238 struct ifnet *ifp = &sc->sc_if; 1239 struct fxp_cb_config *cbp; 1240 struct fxp_cb_ias *cb_ias; 1241 struct fxp_cb_tx *txp; 1242 int i, prm, s; 1243 1244 s = splimp(); 1245 /* 1246 * Cancel any pending I/O 1247 */ 1248 fxp_stop(sc); 1249 1250 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1251 1252 /* 1253 * Initialize base of CBL and RFA memory. Loading with zero 1254 * sets it up for regular linear addressing. 1255 */ 1256 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1258 1259 fxp_scb_wait(sc); 1260 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1261 1262 /* 1263 * Initialize base of dump-stats buffer. 1264 */ 1265 fxp_scb_wait(sc); 1266 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1267 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1268 1269 /* 1270 * We temporarily use memory that contains the TxCB list to 1271 * construct the config CB. The TxCB list memory is rebuilt 1272 * later. 1273 */ 1274 cbp = (struct fxp_cb_config *) sc->cbl_base; 1275 1276 /* 1277 * This bcopy is kind of disgusting, but there are a bunch of must be 1278 * zero and must be one bits in this structure and this is the easiest 1279 * way to initialize them all to proper values. 1280 */ 1281 bcopy(fxp_cb_config_template, 1282 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1283 sizeof(fxp_cb_config_template)); 1284 1285 cbp->cb_status = 0; 1286 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1287 cbp->link_addr = -1; /* (no) next command */ 1288 cbp->byte_count = 22; /* (22) bytes to config */ 1289 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1290 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1291 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1292 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1293 cbp->type_enable = 0; /* actually reserved */ 1294 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1295 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1296 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1297 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1298 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1299 cbp->late_scb = 0; /* (don't) defer SCB update */ 1300 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1301 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1302 cbp->ci_int = 1; /* interrupt on CU idle */ 1303 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1304 cbp->ext_stats_dis = 1; /* disable extended counters */ 1305 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1306 cbp->save_bf = prm; /* save bad frames */ 1307 cbp->disc_short_rx = !prm; /* discard short packets */ 1308 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1309 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1310 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1311 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1312 cbp->csma_dis = 0; /* (don't) disable link */ 1313 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1314 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1315 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1316 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1317 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1318 cbp->nsai = 1; /* (don't) disable source addr insert */ 1319 cbp->preamble_length = 2; /* (7 byte) preamble */ 1320 cbp->loopback = 0; /* (don't) loopback */ 1321 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1322 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1323 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1324 cbp->promiscuous = prm; /* promiscuous mode */ 1325 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1326 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1327 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1328 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1329 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1330 1331 /* 1332 * we may want to move all FC stuff to a separate section. 1333 * the values here are 82557 compatible. 1334 */ 1335 cbp->fc_delay_lsb = 0; 1336 cbp->fc_delay_msb = 0x40; 1337 cbp->pri_fc_thresh = 0x03; 1338 cbp->tx_fc_dis = 0; /* (don't) disable transmit FC */ 1339 cbp->rx_fc_restop = 0; /* (don't) enable FC stop frame */ 1340 cbp->rx_fc_restart = 0; /* (don't) enable FC start frame */ 1341 cbp->fc_filter = 0; /* (do) pass FC frames to host */ 1342 cbp->pri_fc_loc = 1; /* location of priority in FC frame */ 1343 1344 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1345 cbp->padding = 1; /* (do) pad short tx packets */ 1346 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1347 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1348 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1349 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1350 /* must set wake_en in PMCSR also */ 1351 cbp->force_fdx = 0; /* (don't) force full duplex */ 1352 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1353 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1354 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1355 1356 /* 1357 * Start the config command/DMA. 1358 */ 1359 fxp_scb_wait(sc); 1360 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1361 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1362 /* ...and wait for it to complete. */ 1363 fxp_dma_wait(&cbp->cb_status, sc); 1364 1365 /* 1366 * Now initialize the station address. Temporarily use the TxCB 1367 * memory area like we did above for the config CB. 1368 */ 1369 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1370 cb_ias->cb_status = 0; 1371 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1372 cb_ias->link_addr = -1; 1373 bcopy(sc->arpcom.ac_enaddr, 1374 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1375 sizeof(sc->arpcom.ac_enaddr)); 1376 1377 /* 1378 * Start the IAS (Individual Address Setup) command/DMA. 1379 */ 1380 fxp_scb_wait(sc); 1381 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1382 /* ...and wait for it to complete. */ 1383 fxp_dma_wait(&cb_ias->cb_status, sc); 1384 1385 /* 1386 * Initialize transmit control block (TxCB) list. 1387 */ 1388 1389 txp = sc->cbl_base; 1390 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1391 for (i = 0; i < FXP_NTXCB; i++) { 1392 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1393 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1394 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1395 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1396 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1397 } 1398 /* 1399 * Set the suspend flag on the first TxCB and start the control 1400 * unit. It will execute the NOP and then suspend. 1401 */ 1402 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1403 sc->cbl_first = sc->cbl_last = txp; 1404 sc->tx_queued = 1; 1405 1406 fxp_scb_wait(sc); 1407 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1408 1409 /* 1410 * Initialize receiver buffer area - RFA. 1411 */ 1412 fxp_scb_wait(sc); 1413 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1414 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1415 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1416 1417 /* 1418 * Set current media. 1419 */ 1420 if (sc->miibus != NULL) 1421 mii_mediachg(device_get_softc(sc->miibus)); 1422 1423 ifp->if_flags |= IFF_RUNNING; 1424 ifp->if_flags &= ~IFF_OACTIVE; 1425 splx(s); 1426 1427 /* 1428 * Start stats updater. 1429 */ 1430 sc->stat_ch = timeout(fxp_tick, sc, hz); 1431} 1432 1433static int 1434fxp_serial_ifmedia_upd(struct ifnet *ifp) 1435{ 1436 1437 return (0); 1438} 1439 1440static void 1441fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1442{ 1443 1444 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1445} 1446 1447/* 1448 * Change media according to request. 1449 */ 1450static int 1451fxp_ifmedia_upd(struct ifnet *ifp) 1452{ 1453 struct fxp_softc *sc = ifp->if_softc; 1454 struct mii_data *mii; 1455 1456 mii = device_get_softc(sc->miibus); 1457 mii_mediachg(mii); 1458 return (0); 1459} 1460 1461/* 1462 * Notify the world which media we're using. 1463 */ 1464static void 1465fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1466{ 1467 struct fxp_softc *sc = ifp->if_softc; 1468 struct mii_data *mii; 1469 1470 mii = device_get_softc(sc->miibus); 1471 mii_pollstat(mii); 1472 ifmr->ifm_active = mii->mii_media_active; 1473 ifmr->ifm_status = mii->mii_media_status; 1474} 1475 1476/* 1477 * Add a buffer to the end of the RFA buffer list. 1478 * Return 0 if successful, 1 for failure. A failure results in 1479 * adding the 'oldm' (if non-NULL) on to the end of the list - 1480 * tossing out its old contents and recycling it. 1481 * The RFA struct is stuck at the beginning of mbuf cluster and the 1482 * data pointer is fixed up to point just past it. 1483 */ 1484static int 1485fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1486{ 1487 u_int32_t v; 1488 struct mbuf *m; 1489 struct fxp_rfa *rfa, *p_rfa; 1490 1491 MGETHDR(m, M_DONTWAIT, MT_DATA); 1492 if (m != NULL) { 1493 MCLGET(m, M_DONTWAIT); 1494 if ((m->m_flags & M_EXT) == 0) { 1495 m_freem(m); 1496 if (oldm == NULL) 1497 return 1; 1498 m = oldm; 1499 m->m_data = m->m_ext.ext_buf; 1500 } 1501 } else { 1502 if (oldm == NULL) 1503 return 1; 1504 m = oldm; 1505 m->m_data = m->m_ext.ext_buf; 1506 } 1507 1508 /* 1509 * Move the data pointer up so that the incoming data packet 1510 * will be 32-bit aligned. 1511 */ 1512 m->m_data += RFA_ALIGNMENT_FUDGE; 1513 1514 /* 1515 * Get a pointer to the base of the mbuf cluster and move 1516 * data start past it. 1517 */ 1518 rfa = mtod(m, struct fxp_rfa *); 1519 m->m_data += sizeof(struct fxp_rfa); 1520 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1521 1522 /* 1523 * Initialize the rest of the RFA. Note that since the RFA 1524 * is misaligned, we cannot store values directly. Instead, 1525 * we use an optimized, inline copy. 1526 */ 1527 1528 rfa->rfa_status = 0; 1529 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1530 rfa->actual_size = 0; 1531 1532 v = -1; 1533 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1534 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1535 1536 /* 1537 * If there are other buffers already on the list, attach this 1538 * one to the end by fixing up the tail to point to this one. 1539 */ 1540 if (sc->rfa_headm != NULL) { 1541 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1542 RFA_ALIGNMENT_FUDGE); 1543 sc->rfa_tailm->m_next = m; 1544 v = vtophys(rfa); 1545 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1546 p_rfa->rfa_control = 0; 1547 } else { 1548 sc->rfa_headm = m; 1549 } 1550 sc->rfa_tailm = m; 1551 1552 return (m == oldm); 1553} 1554 1555static volatile int 1556fxp_miibus_readreg(device_t dev, int phy, int reg) 1557{ 1558 struct fxp_softc *sc = device_get_softc(dev); 1559 int count = 10000; 1560 int value; 1561 1562 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1563 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1564 1565 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1566 && count--) 1567 DELAY(10); 1568 1569 if (count <= 0) 1570 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1571 1572 return (value & 0xffff); 1573} 1574 1575static void 1576fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1577{ 1578 struct fxp_softc *sc = device_get_softc(dev); 1579 int count = 10000; 1580 1581 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1582 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1583 (value & 0xffff)); 1584 1585 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1586 count--) 1587 DELAY(10); 1588 1589 if (count <= 0) 1590 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1591} 1592 1593static int 1594fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1595{ 1596 struct fxp_softc *sc = ifp->if_softc; 1597 struct ifreq *ifr = (struct ifreq *)data; 1598 struct mii_data *mii; 1599 int s, error = 0; 1600 1601 s = splimp(); 1602 1603 switch (command) { 1604 case SIOCSIFADDR: 1605 case SIOCGIFADDR: 1606 case SIOCSIFMTU: 1607 error = ether_ioctl(ifp, command, data); 1608 break; 1609 1610 case SIOCSIFFLAGS: 1611 if (ifp->if_flags & IFF_ALLMULTI) 1612 sc->flags |= FXP_FLAG_ALL_MCAST; 1613 else 1614 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1615 1616 /* 1617 * If interface is marked up and not running, then start it. 1618 * If it is marked down and running, stop it. 1619 * XXX If it's up then re-initialize it. This is so flags 1620 * such as IFF_PROMISC are handled. 1621 */ 1622 if (ifp->if_flags & IFF_UP) { 1623 fxp_init(sc); 1624 } else { 1625 if (ifp->if_flags & IFF_RUNNING) 1626 fxp_stop(sc); 1627 } 1628 break; 1629 1630 case SIOCADDMULTI: 1631 case SIOCDELMULTI: 1632 if (ifp->if_flags & IFF_ALLMULTI) 1633 sc->flags |= FXP_FLAG_ALL_MCAST; 1634 else 1635 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1636 /* 1637 * Multicast list has changed; set the hardware filter 1638 * accordingly. 1639 */ 1640 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1641 fxp_mc_setup(sc); 1642 /* 1643 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1644 * again rather than else {}. 1645 */ 1646 if (sc->flags & FXP_FLAG_ALL_MCAST) 1647 fxp_init(sc); 1648 error = 0; 1649 break; 1650 1651 case SIOCSIFMEDIA: 1652 case SIOCGIFMEDIA: 1653 if (sc->miibus != NULL) { 1654 mii = device_get_softc(sc->miibus); 1655 error = ifmedia_ioctl(ifp, ifr, 1656 &mii->mii_media, command); 1657 } else { 1658 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1659 } 1660 break; 1661 1662 default: 1663 error = EINVAL; 1664 } 1665 splx(s); 1666 return (error); 1667} 1668 1669/* 1670 * Program the multicast filter. 1671 * 1672 * We have an artificial restriction that the multicast setup command 1673 * must be the first command in the chain, so we take steps to ensure 1674 * this. By requiring this, it allows us to keep up the performance of 1675 * the pre-initialized command ring (esp. link pointers) by not actually 1676 * inserting the mcsetup command in the ring - i.e. its link pointer 1677 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1678 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1679 * lead into the regular TxCB ring when it completes. 1680 * 1681 * This function must be called at splimp. 1682 */ 1683static void 1684fxp_mc_setup(struct fxp_softc *sc) 1685{ 1686 struct fxp_cb_mcs *mcsp = sc->mcsp; 1687 struct ifnet *ifp = &sc->sc_if; 1688 struct ifmultiaddr *ifma; 1689 int nmcasts; 1690 int count; 1691 1692 /* 1693 * If there are queued commands, we must wait until they are all 1694 * completed. If we are already waiting, then add a NOP command 1695 * with interrupt option so that we're notified when all commands 1696 * have been completed - fxp_start() ensures that no additional 1697 * TX commands will be added when need_mcsetup is true. 1698 */ 1699 if (sc->tx_queued) { 1700 struct fxp_cb_tx *txp; 1701 1702 /* 1703 * need_mcsetup will be true if we are already waiting for the 1704 * NOP command to be completed (see below). In this case, bail. 1705 */ 1706 if (sc->need_mcsetup) 1707 return; 1708 sc->need_mcsetup = 1; 1709 1710 /* 1711 * Add a NOP command with interrupt so that we are notified when all 1712 * TX commands have been processed. 1713 */ 1714 txp = sc->cbl_last->next; 1715 txp->mb_head = NULL; 1716 txp->cb_status = 0; 1717 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1718 /* 1719 * Advance the end of list forward. 1720 */ 1721 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1722 sc->cbl_last = txp; 1723 sc->tx_queued++; 1724 /* 1725 * Issue a resume in case the CU has just suspended. 1726 */ 1727 fxp_scb_wait(sc); 1728 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1729 /* 1730 * Set a 5 second timer just in case we don't hear from the 1731 * card again. 1732 */ 1733 ifp->if_timer = 5; 1734 1735 return; 1736 } 1737 sc->need_mcsetup = 0; 1738 1739 /* 1740 * Initialize multicast setup descriptor. 1741 */ 1742 mcsp->next = sc->cbl_base; 1743 mcsp->mb_head = NULL; 1744 mcsp->cb_status = 0; 1745 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1746 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1747 1748 nmcasts = 0; 1749 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 1750#if __FreeBSD_version < 500000 1751 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1752#else 1753 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1754#endif 1755 if (ifma->ifma_addr->sa_family != AF_LINK) 1756 continue; 1757 if (nmcasts >= MAXMCADDR) { 1758 sc->flags |= FXP_FLAG_ALL_MCAST; 1759 nmcasts = 0; 1760 break; 1761 } 1762 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1763 (void *)(uintptr_t)(volatile void *) 1764 &sc->mcsp->mc_addr[nmcasts][0], 6); 1765 nmcasts++; 1766 } 1767 } 1768 mcsp->mc_cnt = nmcasts * 6; 1769 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1770 sc->tx_queued = 1; 1771 1772 /* 1773 * Wait until command unit is not active. This should never 1774 * be the case when nothing is queued, but make sure anyway. 1775 */ 1776 count = 100; 1777 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1778 FXP_SCB_CUS_ACTIVE && --count) 1779 DELAY(10); 1780 if (count == 0) { 1781 device_printf(sc->dev, "command queue timeout\n"); 1782 return; 1783 } 1784 1785 /* 1786 * Start the multicast setup command. 1787 */ 1788 fxp_scb_wait(sc); 1789 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1790 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1791 1792 ifp->if_timer = 2; 1793 return; 1794} 1795