if_fxp.c revision 67090
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Modifications to support media selection: 6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 67090 2000-10-13 18:59:29Z cp $ 31 */ 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59#include <machine/mutex.h> 60 61#include <net/ethernet.h> 62#include <net/if_arp.h> 63 64#include <vm/vm.h> /* for vtophys */ 65#include <vm/pmap.h> /* for vtophys */ 66#include <machine/clock.h> /* for DELAY */ 67 68#include <pci/pcivar.h> 69#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 70#include <pci/if_fxpreg.h> 71#include <pci/if_fxpvar.h> 72 73#ifdef __alpha__ /* XXX */ 74/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 75#undef vtophys 76#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 77#endif /* __alpha__ */ 78 79/* 80 * NOTE! On the Alpha, we have an alignment constraint. The 81 * card DMAs the packet immediately following the RFA. However, 82 * the first thing in the packet is a 14-byte Ethernet header. 83 * This means that the packet is misaligned. To compensate, 84 * we actually offset the RFA 2 bytes into the cluster. This 85 * alignes the packet after the Ethernet header at a 32-bit 86 * boundary. HOWEVER! This means that the RFA is misaligned! 87 */ 88#define RFA_ALIGNMENT_FUDGE 2 89 90/* 91 * Inline function to copy a 16-bit aligned 32-bit quantity. 92 */ 93static __inline void fxp_lwcopy __P((volatile u_int32_t *, 94 volatile u_int32_t *)); 95static __inline void 96fxp_lwcopy(src, dst) 97 volatile u_int32_t *src, *dst; 98{ 99#ifdef __i386__ 100 *dst = *src; 101#else 102 volatile u_int16_t *a = (volatile u_int16_t *)src; 103 volatile u_int16_t *b = (volatile u_int16_t *)dst; 104 105 b[0] = a[0]; 106 b[1] = a[1]; 107#endif 108} 109 110/* 111 * Template for default configuration parameters. 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x80, 0x2, /* cb_command */ 117 0xff, 0xff, 0xff, 0xff, /* link_addr */ 118 0x16, /* 0 */ 119 0x8, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x80, /* 5 */ 124 0xb2, /* 6 */ 125 0x3, /* 7 */ 126 0x1, /* 8 */ 127 0x0, /* 9 */ 128 0x26, /* 10 */ 129 0x0, /* 11 */ 130 0x60, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf3, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142/* Supported media types. */ 143struct fxp_supported_media { 144 const int fsm_phy; /* PHY type */ 145 const int *fsm_media; /* the media array */ 146 const int fsm_nmedia; /* the number of supported media */ 147 const int fsm_defmedia; /* default media for this PHY */ 148}; 149 150static const int fxp_media_standard[] = { 151 IFM_ETHER|IFM_10_T, 152 IFM_ETHER|IFM_10_T|IFM_FDX, 153 IFM_ETHER|IFM_100_TX, 154 IFM_ETHER|IFM_100_TX|IFM_FDX, 155 IFM_ETHER|IFM_AUTO, 156}; 157#define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO) 158 159static const int fxp_media_default[] = { 160 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */ 161}; 162#define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL) 163 164static const struct fxp_supported_media fxp_media[] = { 165 { FXP_PHY_DP83840, fxp_media_standard, 166 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 167 FXP_MEDIA_STANDARD_DEFMEDIA }, 168 { FXP_PHY_DP83840A, fxp_media_standard, 169 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 170 FXP_MEDIA_STANDARD_DEFMEDIA }, 171 { FXP_PHY_82553A, fxp_media_standard, 172 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 173 FXP_MEDIA_STANDARD_DEFMEDIA }, 174 { FXP_PHY_82553C, fxp_media_standard, 175 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 176 FXP_MEDIA_STANDARD_DEFMEDIA }, 177 { FXP_PHY_82555, fxp_media_standard, 178 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 179 FXP_MEDIA_STANDARD_DEFMEDIA }, 180 { FXP_PHY_82555B, fxp_media_standard, 181 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 182 FXP_MEDIA_STANDARD_DEFMEDIA }, 183 { FXP_PHY_80C24, fxp_media_default, 184 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]), 185 FXP_MEDIA_DEFAULT_DEFMEDIA }, 186}; 187#define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0])) 188 189static int fxp_mediachange __P((struct ifnet *)); 190static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *)); 191static void fxp_set_media __P((struct fxp_softc *, int)); 192static __inline void fxp_scb_wait __P((struct fxp_softc *)); 193static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc)); 194static void fxp_intr __P((void *)); 195static void fxp_start __P((struct ifnet *)); 196static int fxp_ioctl __P((struct ifnet *, 197 u_long, caddr_t)); 198static void fxp_init __P((void *)); 199static void fxp_stop __P((struct fxp_softc *)); 200static void fxp_watchdog __P((struct ifnet *)); 201static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *)); 202static int fxp_mdi_read __P((struct fxp_softc *, int, int)); 203static void fxp_mdi_write __P((struct fxp_softc *, int, int, int)); 204static void fxp_autosize_eeprom __P((struct fxp_softc *)); 205static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, 206 int, int)); 207static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *)); 208static void fxp_stats_update __P((void *)); 209static void fxp_mc_setup __P((struct fxp_softc *)); 210 211/* 212 * Set initial transmit threshold at 64 (512 bytes). This is 213 * increased by 64 (512 bytes) at a time, to maximum of 192 214 * (1536 bytes), if an underrun occurs. 215 */ 216static int tx_threshold = 64; 217 218/* 219 * Number of transmit control blocks. This determines the number 220 * of transmit buffers that can be chained in the CB list. 221 * This must be a power of two. 222 */ 223#define FXP_NTXCB 128 224 225/* 226 * Number of completed TX commands at which point an interrupt 227 * will be generated to garbage collect the attached buffers. 228 * Must be at least one less than FXP_NTXCB, and should be 229 * enough less so that the transmitter doesn't becomes idle 230 * during the buffer rundown (which would reduce performance). 231 */ 232#define FXP_CXINT_THRESH 120 233 234/* 235 * TxCB list index mask. This is used to do list wrap-around. 236 */ 237#define FXP_TXCB_MASK (FXP_NTXCB - 1) 238 239/* 240 * Number of receive frame area buffers. These are large so chose 241 * wisely. 242 */ 243#define FXP_NRFABUFS 64 244 245/* 246 * Maximum number of seconds that the receiver can be idle before we 247 * assume it's dead and attempt to reset it by reprogramming the 248 * multicast filter. This is part of a work-around for a bug in the 249 * NIC. See fxp_stats_update(). 250 */ 251#define FXP_MAX_RX_IDLE 15 252 253/* 254 * Wait for the previous command to be accepted (but not necessarily 255 * completed). 256 */ 257static __inline void 258fxp_scb_wait(sc) 259 struct fxp_softc *sc; 260{ 261 int i = 10000; 262 263 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 264 DELAY(2); 265 if (i == 0) 266 printf("fxp%d: SCB timeout\n", FXP_UNIT(sc)); 267} 268 269static __inline void 270fxp_dma_wait(status, sc) 271 volatile u_int16_t *status; 272 struct fxp_softc *sc; 273{ 274 int i = 10000; 275 276 while (!(*status & FXP_CB_STATUS_C) && --i) 277 DELAY(2); 278 if (i == 0) 279 printf("fxp%d: DMA timeout\n", FXP_UNIT(sc)); 280} 281 282/* 283 * Return identification string if this is device is ours. 284 */ 285static int 286fxp_probe(device_t dev) 287{ 288 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 289 switch (pci_get_device(dev)) { 290 291 case FXP_DEVICEID_i82557: 292 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet"); 293 return 0; 294 case FXP_DEVICEID_i82559: 295 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet"); 296 return 0; 297 case FXP_DEVICEID_i82559ER: 298 device_set_desc(dev, "Intel Embedded 10/100 Ethernet"); 299 return 0; 300 case FXP_DEVICEID_i82562: 301 device_set_desc(dev, "Intel PLC 10/100 Ethernet"); 302 return 0; 303 default: 304 break; 305 } 306 } 307 308 return ENXIO; 309} 310 311static int 312fxp_attach(device_t dev) 313{ 314 int error = 0; 315 struct fxp_softc *sc = device_get_softc(dev); 316 struct ifnet *ifp; 317 u_long val; 318 int rid; 319 320 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF); 321 callout_handle_init(&sc->stat_ch); 322 323 FXP_LOCK(sc); 324 325 /* 326 * Enable bus mastering. 327 */ 328 val = pci_read_config(dev, PCIR_COMMAND, 2); 329 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 330 pci_write_config(dev, PCIR_COMMAND, val, 2); 331 332 /* 333 * Map control/status registers. 334 */ 335 rid = FXP_PCI_MMBA; 336 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 337 0, ~0, 1, RF_ACTIVE); 338 if (!sc->mem) { 339 device_printf(dev, "could not map memory\n"); 340 error = ENXIO; 341 goto fail; 342 } 343 344 sc->sc_st = rman_get_bustag(sc->mem); 345 sc->sc_sh = rman_get_bushandle(sc->mem); 346 347 /* 348 * Allocate our interrupt. 349 */ 350 rid = 0; 351 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 352 RF_SHAREABLE | RF_ACTIVE); 353 if (sc->irq == NULL) { 354 device_printf(dev, "could not map interrupt\n"); 355 error = ENXIO; 356 goto fail; 357 } 358 359 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 360 fxp_intr, sc, &sc->ih); 361 if (error) { 362 device_printf(dev, "could not setup irq\n"); 363 goto fail; 364 } 365 366 /* Do generic parts of attach. */ 367 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) { 368 /* Failed! */ 369 bus_teardown_intr(dev, sc->irq, sc->ih); 370 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 371 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 372 error = ENXIO; 373 goto fail; 374 } 375 376 device_printf(dev, "Ethernet address %6D%s\n", 377 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : ""); 378 379 ifp = &sc->arpcom.ac_if; 380 ifp->if_unit = device_get_unit(dev); 381 ifp->if_name = "fxp"; 382 ifp->if_output = ether_output; 383 ifp->if_baudrate = 100000000; 384 ifp->if_init = fxp_init; 385 ifp->if_softc = sc; 386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 387 ifp->if_ioctl = fxp_ioctl; 388 ifp->if_start = fxp_start; 389 ifp->if_watchdog = fxp_watchdog; 390 391 /* 392 * Attach the interface. 393 */ 394 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 395 /* 396 * Let the system queue as many packets as we have available 397 * TX descriptors. 398 */ 399 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 400 401 FXP_UNLOCK(sc); 402 return 0; 403 404 fail: 405 FXP_UNLOCK(sc); 406 mtx_destroy(&sc->sc_mtx); 407 return error; 408} 409 410/* 411 * Detach interface. 412 */ 413static int 414fxp_detach(device_t dev) 415{ 416 struct fxp_softc *sc = device_get_softc(dev); 417 418 FXP_LOCK(sc); 419 420 /* 421 * Close down routes etc. 422 */ 423 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 424 425 /* 426 * Stop DMA and drop transmit queue. 427 */ 428 fxp_stop(sc); 429 430 /* 431 * Deallocate resources. 432 */ 433 bus_teardown_intr(dev, sc->irq, sc->ih); 434 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 435 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 436 437 /* 438 * Free all the receive buffers. 439 */ 440 if (sc->rfa_headm != NULL) 441 m_freem(sc->rfa_headm); 442 443 /* 444 * Free all media structures. 445 */ 446 ifmedia_removeall(&sc->sc_media); 447 448 /* 449 * Free anciliary structures. 450 */ 451 free(sc->cbl_base, M_DEVBUF); 452 free(sc->fxp_stats, M_DEVBUF); 453 free(sc->mcsp, M_DEVBUF); 454 455 FXP_UNLOCK(sc); 456 mtx_destroy(&sc->sc_mtx); 457 458 return 0; 459} 460 461/* 462 * Device shutdown routine. Called at system shutdown after sync. The 463 * main purpose of this routine is to shut off receiver DMA so that 464 * kernel memory doesn't get clobbered during warmboot. 465 */ 466static int 467fxp_shutdown(device_t dev) 468{ 469 /* 470 * Make sure that DMA is disabled prior to reboot. Not doing 471 * do could allow DMA to corrupt kernel memory during the 472 * reboot before the driver initializes. 473 */ 474 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 475 return 0; 476} 477 478/* 479 * Device suspend routine. Stop the interface and save some PCI 480 * settings in case the BIOS doesn't restore them properly on 481 * resume. 482 */ 483static int 484fxp_suspend(device_t dev) 485{ 486 struct fxp_softc *sc = device_get_softc(dev); 487 int i; 488 489 FXP_LOCK(sc); 490 491 fxp_stop(sc); 492 493 for (i=0; i<5; i++) 494 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 495 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 496 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 497 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 498 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 499 500 sc->suspended = 1; 501 502 FXP_UNLOCK(sc); 503 504 return 0; 505} 506 507/* 508 * Device resume routine. Restore some PCI settings in case the BIOS 509 * doesn't, re-enable busmastering, and restart the interface if 510 * appropriate. 511 */ 512static int 513fxp_resume(device_t dev) 514{ 515 struct fxp_softc *sc = device_get_softc(dev); 516 struct ifnet *ifp = &sc->sc_if; 517 u_int16_t pci_command; 518 int i; 519 520 FXP_LOCK(sc); 521 522 /* better way to do this? */ 523 for (i=0; i<5; i++) 524 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 525 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 526 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 527 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 528 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 529 530 /* reenable busmastering */ 531 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 532 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 533 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 534 535 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 536 DELAY(10); 537 538 /* reinitialize interface if necessary */ 539 if (ifp->if_flags & IFF_UP) 540 fxp_init(sc); 541 542 sc->suspended = 0; 543 544 FXP_UNLOCK(sc); 545 546 return 0; 547} 548 549static device_method_t fxp_methods[] = { 550 /* Device interface */ 551 DEVMETHOD(device_probe, fxp_probe), 552 DEVMETHOD(device_attach, fxp_attach), 553 DEVMETHOD(device_detach, fxp_detach), 554 DEVMETHOD(device_shutdown, fxp_shutdown), 555 DEVMETHOD(device_suspend, fxp_suspend), 556 DEVMETHOD(device_resume, fxp_resume), 557 558 { 0, 0 } 559}; 560 561static driver_t fxp_driver = { 562 "fxp", 563 fxp_methods, 564 sizeof(struct fxp_softc), 565}; 566 567static devclass_t fxp_devclass; 568 569DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 570 571/* 572 * Do generic parts of attach. 573 */ 574static int 575fxp_attach_common(sc, enaddr) 576 struct fxp_softc *sc; 577 u_int8_t *enaddr; 578{ 579 u_int16_t data; 580 int i, nmedia, defmedia; 581 const int *media; 582 583 /* 584 * Reset to a stable state. 585 */ 586 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 587 DELAY(10); 588 589 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 590 M_DEVBUF, M_NOWAIT); 591 if (sc->cbl_base == NULL) 592 goto fail; 593 bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 594 595 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT); 596 if (sc->fxp_stats == NULL) 597 goto fail; 598 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 599 600 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 601 if (sc->mcsp == NULL) 602 goto fail; 603 604 /* 605 * Pre-allocate our receive buffers. 606 */ 607 for (i = 0; i < FXP_NRFABUFS; i++) { 608 if (fxp_add_rfabuf(sc, NULL) != 0) { 609 goto fail; 610 } 611 } 612 613 /* 614 * Find out how large of an SEEPROM we have. 615 */ 616 fxp_autosize_eeprom(sc); 617 618 /* 619 * Get info about the primary PHY 620 */ 621 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1); 622 sc->phy_primary_addr = data & 0xff; 623 sc->phy_primary_device = (data >> 8) & 0x3f; 624 sc->phy_10Mbps_only = data >> 15; 625 626 /* 627 * Read MAC address. 628 */ 629 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3); 630 631 /* 632 * Initialize the media structures. 633 */ 634 635 media = fxp_media_default; 636 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]); 637 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA; 638 639 for (i = 0; i < NFXPMEDIA; i++) { 640 if (sc->phy_primary_device == fxp_media[i].fsm_phy) { 641 media = fxp_media[i].fsm_media; 642 nmedia = fxp_media[i].fsm_nmedia; 643 defmedia = fxp_media[i].fsm_defmedia; 644 } 645 } 646 647 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus); 648 for (i = 0; i < nmedia; i++) { 649 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only) 650 continue; 651 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 652 } 653 ifmedia_set(&sc->sc_media, defmedia); 654 655 return (0); 656 657 fail: 658 printf("fxp%d: Failed to malloc memory\n", FXP_UNIT(sc)); 659 if (sc->cbl_base) 660 free(sc->cbl_base, M_DEVBUF); 661 if (sc->fxp_stats) 662 free(sc->fxp_stats, M_DEVBUF); 663 if (sc->mcsp) 664 free(sc->mcsp, M_DEVBUF); 665 /* frees entire chain */ 666 if (sc->rfa_headm) 667 m_freem(sc->rfa_headm); 668 669 return (ENOMEM); 670} 671 672/* 673 * From NetBSD: 674 * 675 * Figure out EEPROM size. 676 * 677 * 559's can have either 64-word or 256-word EEPROMs, the 558 678 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 679 * talks about the existance of 16 to 256 word EEPROMs. 680 * 681 * The only known sizes are 64 and 256, where the 256 version is used 682 * by CardBus cards to store CIS information. 683 * 684 * The address is shifted in msb-to-lsb, and after the last 685 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 686 * after which follows the actual data. We try to detect this zero, by 687 * probing the data-out bit in the EEPROM control register just after 688 * having shifted in a bit. If the bit is zero, we assume we've 689 * shifted enough address bits. The data-out should be tri-state, 690 * before this, which should translate to a logical one. 691 * 692 * Other ways to do this would be to try to read a register with known 693 * contents with a varying number of address bits, but no such 694 * register seem to be available. The high bits of register 10 are 01 695 * on the 558 and 559, but apparently not on the 557. 696 * 697 * The Linux driver computes a checksum on the EEPROM data, but the 698 * value of this checksum is not very well documented. 699 */ 700static void 701fxp_autosize_eeprom(sc) 702 struct fxp_softc *sc; 703{ 704 u_int16_t reg; 705 int x; 706 707 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 708 /* 709 * Shift in read opcode. 710 */ 711 for (x = 3; x > 0; x--) { 712 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 713 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 714 } else { 715 reg = FXP_EEPROM_EECS; 716 } 717 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 718 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 719 reg | FXP_EEPROM_EESK); 720 DELAY(1); 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 722 DELAY(1); 723 } 724 /* 725 * Shift in address. 726 * Wait for the dummy zero following a correct address shift. 727 */ 728 for (x = 1; x <= 8; x++) { 729 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 730 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 731 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 732 DELAY(1); 733 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0) 734 break; 735 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 736 DELAY(1); 737 } 738 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 739 DELAY(1); 740 sc->eeprom_size = x; 741} 742/* 743 * Read from the serial EEPROM. Basically, you manually shift in 744 * the read opcode (one bit at a time) and then shift in the address, 745 * and then you shift out the data (all of this one bit at a time). 746 * The word size is 16 bits, so you have to provide the address for 747 * every 16 bits of data. 748 */ 749static void 750fxp_read_eeprom(sc, data, offset, words) 751 struct fxp_softc *sc; 752 u_short *data; 753 int offset; 754 int words; 755{ 756 u_int16_t reg; 757 int i, x; 758 759 for (i = 0; i < words; i++) { 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 761 /* 762 * Shift in read opcode. 763 */ 764 for (x = 3; x > 0; x--) { 765 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 766 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 767 } else { 768 reg = FXP_EEPROM_EECS; 769 } 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 772 reg | FXP_EEPROM_EESK); 773 DELAY(1); 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 775 DELAY(1); 776 } 777 /* 778 * Shift in address. 779 */ 780 for (x = sc->eeprom_size; x > 0; x--) { 781 if ((i + offset) & (1 << (x - 1))) { 782 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 783 } else { 784 reg = FXP_EEPROM_EECS; 785 } 786 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 787 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 788 reg | FXP_EEPROM_EESK); 789 DELAY(1); 790 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 791 DELAY(1); 792 } 793 reg = FXP_EEPROM_EECS; 794 data[i] = 0; 795 /* 796 * Shift out data. 797 */ 798 for (x = 16; x > 0; x--) { 799 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 800 reg | FXP_EEPROM_EESK); 801 DELAY(1); 802 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 803 FXP_EEPROM_EEDO) 804 data[i] |= (1 << (x - 1)); 805 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 806 DELAY(1); 807 } 808 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 809 DELAY(1); 810 } 811} 812 813/* 814 * Start packet transmission on the interface. 815 */ 816static void 817fxp_start(ifp) 818 struct ifnet *ifp; 819{ 820 struct fxp_softc *sc = ifp->if_softc; 821 struct fxp_cb_tx *txp; 822 823 FXP_LOCK(sc); 824 /* 825 * See if we need to suspend xmit until the multicast filter 826 * has been reprogrammed (which can only be done at the head 827 * of the command chain). 828 */ 829 if (sc->need_mcsetup) { 830 FXP_UNLOCK(sc); 831 return; 832 } 833 834 txp = NULL; 835 836 /* 837 * We're finished if there is nothing more to add to the list or if 838 * we're all filled up with buffers to transmit. 839 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 840 * a NOP command when needed. 841 */ 842 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 843 struct mbuf *m, *mb_head; 844 int segment; 845 846 /* 847 * Grab a packet to transmit. 848 */ 849 IF_DEQUEUE(&ifp->if_snd, mb_head); 850 851 /* 852 * Get pointer to next available tx desc. 853 */ 854 txp = sc->cbl_last->next; 855 856 /* 857 * Go through each of the mbufs in the chain and initialize 858 * the transmit buffer descriptors with the physical address 859 * and size of the mbuf. 860 */ 861tbdinit: 862 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 863 if (m->m_len != 0) { 864 if (segment == FXP_NTXSEG) 865 break; 866 txp->tbd[segment].tb_addr = 867 vtophys(mtod(m, vm_offset_t)); 868 txp->tbd[segment].tb_size = m->m_len; 869 segment++; 870 } 871 } 872 if (m != NULL) { 873 struct mbuf *mn; 874 875 /* 876 * We ran out of segments. We have to recopy this mbuf 877 * chain first. Bail out if we can't get the new buffers. 878 */ 879 MGETHDR(mn, M_DONTWAIT, MT_DATA); 880 if (mn == NULL) { 881 m_freem(mb_head); 882 break; 883 } 884 if (mb_head->m_pkthdr.len > MHLEN) { 885 MCLGET(mn, M_DONTWAIT); 886 if ((mn->m_flags & M_EXT) == 0) { 887 m_freem(mn); 888 m_freem(mb_head); 889 break; 890 } 891 } 892 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 893 mtod(mn, caddr_t)); 894 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 895 m_freem(mb_head); 896 mb_head = mn; 897 goto tbdinit; 898 } 899 900 txp->tbd_number = segment; 901 txp->mb_head = mb_head; 902 txp->cb_status = 0; 903 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 904 txp->cb_command = 905 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 906 } else { 907 txp->cb_command = 908 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 909 /* 910 * Set a 5 second timer just in case we don't hear from the 911 * card again. 912 */ 913 ifp->if_timer = 5; 914 } 915 txp->tx_threshold = tx_threshold; 916 917 /* 918 * Advance the end of list forward. 919 */ 920 921#ifdef __alpha__ 922 /* 923 * On platforms which can't access memory in 16-bit 924 * granularities, we must prevent the card from DMA'ing 925 * up the status while we update the command field. 926 * This could cause us to overwrite the completion status. 927 */ 928 atomic_clear_short(&sc->cbl_last->cb_command, 929 FXP_CB_COMMAND_S); 930#else 931 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 932#endif /*__alpha__*/ 933 sc->cbl_last = txp; 934 935 /* 936 * Advance the beginning of the list forward if there are 937 * no other packets queued (when nothing is queued, cbl_first 938 * sits on the last TxCB that was sent out). 939 */ 940 if (sc->tx_queued == 0) 941 sc->cbl_first = txp; 942 943 sc->tx_queued++; 944 945 /* 946 * Pass packet to bpf if there is a listener. 947 */ 948 if (ifp->if_bpf) 949 bpf_mtap(ifp, mb_head); 950 } 951 952 /* 953 * We're finished. If we added to the list, issue a RESUME to get DMA 954 * going again if suspended. 955 */ 956 if (txp != NULL) { 957 fxp_scb_wait(sc); 958 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 959 } 960 FXP_UNLOCK(sc); 961} 962 963/* 964 * Process interface interrupts. 965 */ 966static void 967fxp_intr(arg) 968 void *arg; 969{ 970 struct fxp_softc *sc = arg; 971 struct ifnet *ifp = &sc->sc_if; 972 u_int8_t statack; 973 974 FXP_LOCK(sc); 975 976 if (sc->suspended) { 977 FXP_UNLOCK(sc); 978 return; 979 } 980 981 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 982 /* 983 * First ACK all the interrupts in this pass. 984 */ 985 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 986 987 /* 988 * Free any finished transmit mbuf chains. 989 * 990 * Handle the CNA event likt a CXTNO event. It used to 991 * be that this event (control unit not ready) was not 992 * encountered, but it is now with the SMPng modifications. 993 * The exact sequence of events that occur when the interface 994 * is brought up are different now, and if this event 995 * goes unhandled, the configuration/rxfilter setup sequence 996 * can stall for several seconds. The result is that no 997 * packets go out onto the wire for about 5 to 10 seconds 998 * after the interface is ifconfig'ed for the first time. 999 */ 1000 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1001 struct fxp_cb_tx *txp; 1002 1003 for (txp = sc->cbl_first; sc->tx_queued && 1004 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1005 txp = txp->next) { 1006 if (txp->mb_head != NULL) { 1007 m_freem(txp->mb_head); 1008 txp->mb_head = NULL; 1009 } 1010 sc->tx_queued--; 1011 } 1012 sc->cbl_first = txp; 1013 ifp->if_timer = 0; 1014 if (sc->tx_queued == 0) { 1015 if (sc->need_mcsetup) 1016 fxp_mc_setup(sc); 1017 } 1018 /* 1019 * Try to start more packets transmitting. 1020 */ 1021 if (ifp->if_snd.ifq_head != NULL) 1022 fxp_start(ifp); 1023 } 1024 /* 1025 * Process receiver interrupts. If a no-resource (RNR) 1026 * condition exists, get whatever packets we can and 1027 * re-start the receiver. 1028 */ 1029 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1030 struct mbuf *m; 1031 struct fxp_rfa *rfa; 1032rcvloop: 1033 m = sc->rfa_headm; 1034 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1035 RFA_ALIGNMENT_FUDGE); 1036 1037 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1038 /* 1039 * Remove first packet from the chain. 1040 */ 1041 sc->rfa_headm = m->m_next; 1042 m->m_next = NULL; 1043 1044 /* 1045 * Add a new buffer to the receive chain. 1046 * If this fails, the old buffer is recycled 1047 * instead. 1048 */ 1049 if (fxp_add_rfabuf(sc, m) == 0) { 1050 struct ether_header *eh; 1051 int total_len; 1052 1053 total_len = rfa->actual_size & 1054 (MCLBYTES - 1); 1055 if (total_len < 1056 sizeof(struct ether_header)) { 1057 m_freem(m); 1058 goto rcvloop; 1059 } 1060 m->m_pkthdr.rcvif = ifp; 1061 m->m_pkthdr.len = m->m_len = total_len; 1062 eh = mtod(m, struct ether_header *); 1063 m->m_data += 1064 sizeof(struct ether_header); 1065 m->m_len -= 1066 sizeof(struct ether_header); 1067 m->m_pkthdr.len = m->m_len; 1068 ether_input(ifp, eh, m); 1069 } 1070 goto rcvloop; 1071 } 1072 if (statack & FXP_SCB_STATACK_RNR) { 1073 fxp_scb_wait(sc); 1074 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1075 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1076 RFA_ALIGNMENT_FUDGE); 1077 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1078 FXP_SCB_COMMAND_RU_START); 1079 } 1080 } 1081 } 1082 FXP_UNLOCK(sc); 1083} 1084 1085/* 1086 * Update packet in/out/collision statistics. The i82557 doesn't 1087 * allow you to access these counters without doing a fairly 1088 * expensive DMA to get _all_ of the statistics it maintains, so 1089 * we do this operation here only once per second. The statistics 1090 * counters in the kernel are updated from the previous dump-stats 1091 * DMA and then a new dump-stats DMA is started. The on-chip 1092 * counters are zeroed when the DMA completes. If we can't start 1093 * the DMA immediately, we don't wait - we just prepare to read 1094 * them again next time. 1095 */ 1096static void 1097fxp_stats_update(arg) 1098 void *arg; 1099{ 1100 struct fxp_softc *sc = arg; 1101 struct ifnet *ifp = &sc->sc_if; 1102 struct fxp_stats *sp = sc->fxp_stats; 1103 struct fxp_cb_tx *txp; 1104 1105 ifp->if_opackets += sp->tx_good; 1106 ifp->if_collisions += sp->tx_total_collisions; 1107 if (sp->rx_good) { 1108 ifp->if_ipackets += sp->rx_good; 1109 sc->rx_idle_secs = 0; 1110 } else { 1111 /* 1112 * Receiver's been idle for another second. 1113 */ 1114 sc->rx_idle_secs++; 1115 } 1116 ifp->if_ierrors += 1117 sp->rx_crc_errors + 1118 sp->rx_alignment_errors + 1119 sp->rx_rnr_errors + 1120 sp->rx_overrun_errors; 1121 /* 1122 * If any transmit underruns occured, bump up the transmit 1123 * threshold by another 512 bytes (64 * 8). 1124 */ 1125 if (sp->tx_underruns) { 1126 ifp->if_oerrors += sp->tx_underruns; 1127 if (tx_threshold < 192) 1128 tx_threshold += 64; 1129 } 1130 FXP_LOCK(sc); 1131 /* 1132 * Release any xmit buffers that have completed DMA. This isn't 1133 * strictly necessary to do here, but it's advantagous for mbufs 1134 * with external storage to be released in a timely manner rather 1135 * than being defered for a potentially long time. This limits 1136 * the delay to a maximum of one second. 1137 */ 1138 for (txp = sc->cbl_first; sc->tx_queued && 1139 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1140 txp = txp->next) { 1141 if (txp->mb_head != NULL) { 1142 m_freem(txp->mb_head); 1143 txp->mb_head = NULL; 1144 } 1145 sc->tx_queued--; 1146 } 1147 sc->cbl_first = txp; 1148 /* 1149 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1150 * then assume the receiver has locked up and attempt to clear 1151 * the condition by reprogramming the multicast filter. This is 1152 * a work-around for a bug in the 82557 where the receiver locks 1153 * up if it gets certain types of garbage in the syncronization 1154 * bits prior to the packet header. This bug is supposed to only 1155 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1156 * mode as well (perhaps due to a 10/100 speed transition). 1157 */ 1158 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1159 sc->rx_idle_secs = 0; 1160 fxp_mc_setup(sc); 1161 } 1162 /* 1163 * If there is no pending command, start another stats 1164 * dump. Otherwise punt for now. 1165 */ 1166 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1167 /* 1168 * Start another stats dump. 1169 */ 1170 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1171 FXP_SCB_COMMAND_CU_DUMPRESET); 1172 } else { 1173 /* 1174 * A previous command is still waiting to be accepted. 1175 * Just zero our copy of the stats and wait for the 1176 * next timer event to update them. 1177 */ 1178 sp->tx_good = 0; 1179 sp->tx_underruns = 0; 1180 sp->tx_total_collisions = 0; 1181 1182 sp->rx_good = 0; 1183 sp->rx_crc_errors = 0; 1184 sp->rx_alignment_errors = 0; 1185 sp->rx_rnr_errors = 0; 1186 sp->rx_overrun_errors = 0; 1187 } 1188 FXP_UNLOCK(sc); 1189 /* 1190 * Schedule another timeout one second from now. 1191 */ 1192 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1193} 1194 1195/* 1196 * Stop the interface. Cancels the statistics updater and resets 1197 * the interface. 1198 */ 1199static void 1200fxp_stop(sc) 1201 struct fxp_softc *sc; 1202{ 1203 struct ifnet *ifp = &sc->sc_if; 1204 struct fxp_cb_tx *txp; 1205 int i; 1206 1207 FXP_LOCK(sc); 1208 1209 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1210 ifp->if_timer = 0; 1211 1212 /* 1213 * Cancel stats updater. 1214 */ 1215 untimeout(fxp_stats_update, sc, sc->stat_ch); 1216 1217 /* 1218 * Issue software reset 1219 */ 1220 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1221 DELAY(10); 1222 1223 /* 1224 * Release any xmit buffers. 1225 */ 1226 txp = sc->cbl_base; 1227 if (txp != NULL) { 1228 for (i = 0; i < FXP_NTXCB; i++) { 1229 if (txp[i].mb_head != NULL) { 1230 m_freem(txp[i].mb_head); 1231 txp[i].mb_head = NULL; 1232 } 1233 } 1234 } 1235 sc->tx_queued = 0; 1236 1237 /* 1238 * Free all the receive buffers then reallocate/reinitialize 1239 */ 1240 if (sc->rfa_headm != NULL) 1241 m_freem(sc->rfa_headm); 1242 sc->rfa_headm = NULL; 1243 sc->rfa_tailm = NULL; 1244 for (i = 0; i < FXP_NRFABUFS; i++) { 1245 if (fxp_add_rfabuf(sc, NULL) != 0) { 1246 /* 1247 * This "can't happen" - we're at splimp() 1248 * and we just freed all the buffers we need 1249 * above. 1250 */ 1251 panic("fxp_stop: no buffers!"); 1252 } 1253 } 1254 1255 FXP_UNLOCK(sc); 1256} 1257 1258/* 1259 * Watchdog/transmission transmit timeout handler. Called when a 1260 * transmission is started on the interface, but no interrupt is 1261 * received before the timeout. This usually indicates that the 1262 * card has wedged for some reason. 1263 */ 1264static void 1265fxp_watchdog(ifp) 1266 struct ifnet *ifp; 1267{ 1268 struct fxp_softc *sc = ifp->if_softc; 1269 1270 printf("fxp%d: device timeout\n", FXP_UNIT(sc)); 1271 ifp->if_oerrors++; 1272 1273 fxp_init(sc); 1274} 1275 1276static void 1277fxp_init(xsc) 1278 void *xsc; 1279{ 1280 struct fxp_softc *sc = xsc; 1281 struct ifnet *ifp = &sc->sc_if; 1282 struct fxp_cb_config *cbp; 1283 struct fxp_cb_ias *cb_ias; 1284 struct fxp_cb_tx *txp; 1285 int i, prm; 1286 1287 FXP_LOCK(sc); 1288 /* 1289 * Cancel any pending I/O 1290 */ 1291 fxp_stop(sc); 1292 1293 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1294 1295 /* 1296 * Initialize base of CBL and RFA memory. Loading with zero 1297 * sets it up for regular linear addressing. 1298 */ 1299 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1300 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1301 1302 fxp_scb_wait(sc); 1303 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1304 1305 /* 1306 * Initialize base of dump-stats buffer. 1307 */ 1308 fxp_scb_wait(sc); 1309 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1310 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1311 1312 /* 1313 * We temporarily use memory that contains the TxCB list to 1314 * construct the config CB. The TxCB list memory is rebuilt 1315 * later. 1316 */ 1317 cbp = (struct fxp_cb_config *) sc->cbl_base; 1318 1319 /* 1320 * This bcopy is kind of disgusting, but there are a bunch of must be 1321 * zero and must be one bits in this structure and this is the easiest 1322 * way to initialize them all to proper values. 1323 */ 1324 bcopy(fxp_cb_config_template, 1325 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1326 sizeof(fxp_cb_config_template)); 1327 1328 cbp->cb_status = 0; 1329 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1330 cbp->link_addr = -1; /* (no) next command */ 1331 cbp->byte_count = 22; /* (22) bytes to config */ 1332 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1333 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1334 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1335 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1336 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1337 cbp->dma_bce = 0; /* (disable) dma max counters */ 1338 cbp->late_scb = 0; /* (don't) defer SCB update */ 1339 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1340 cbp->ci_int = 1; /* interrupt on CU idle */ 1341 cbp->save_bf = prm; /* save bad frames */ 1342 cbp->disc_short_rx = !prm; /* discard short packets */ 1343 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1344 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1345 cbp->nsai = 1; /* (don't) disable source addr insert */ 1346 cbp->preamble_length = 2; /* (7 byte) preamble */ 1347 cbp->loopback = 0; /* (don't) loopback */ 1348 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1349 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1350 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1351 cbp->promiscuous = prm; /* promiscuous mode */ 1352 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1353 cbp->crscdt = 0; /* (CRS only) */ 1354 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1355 cbp->padding = 1; /* (do) pad short tx packets */ 1356 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1357 cbp->force_fdx = 0; /* (don't) force full duplex */ 1358 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1359 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1360 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */ 1361 1362 /* 1363 * Start the config command/DMA. 1364 */ 1365 fxp_scb_wait(sc); 1366 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1367 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1368 /* ...and wait for it to complete. */ 1369 fxp_dma_wait(&cbp->cb_status, sc); 1370 1371 /* 1372 * Now initialize the station address. Temporarily use the TxCB 1373 * memory area like we did above for the config CB. 1374 */ 1375 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1376 cb_ias->cb_status = 0; 1377 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1378 cb_ias->link_addr = -1; 1379 bcopy(sc->arpcom.ac_enaddr, 1380 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1381 sizeof(sc->arpcom.ac_enaddr)); 1382 1383 /* 1384 * Start the IAS (Individual Address Setup) command/DMA. 1385 */ 1386 fxp_scb_wait(sc); 1387 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1388 /* ...and wait for it to complete. */ 1389 fxp_dma_wait(&cb_ias->cb_status, sc); 1390 1391 /* 1392 * Initialize transmit control block (TxCB) list. 1393 */ 1394 1395 txp = sc->cbl_base; 1396 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1397 for (i = 0; i < FXP_NTXCB; i++) { 1398 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1399 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1400 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1401 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1402 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1403 } 1404 /* 1405 * Set the suspend flag on the first TxCB and start the control 1406 * unit. It will execute the NOP and then suspend. 1407 */ 1408 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1409 sc->cbl_first = sc->cbl_last = txp; 1410 sc->tx_queued = 1; 1411 1412 fxp_scb_wait(sc); 1413 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1414 1415 /* 1416 * Initialize receiver buffer area - RFA. 1417 */ 1418 fxp_scb_wait(sc); 1419 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1420 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1421 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1422 1423 /* 1424 * Set current media. 1425 */ 1426 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 1427 1428 ifp->if_flags |= IFF_RUNNING; 1429 ifp->if_flags &= ~IFF_OACTIVE; 1430 FXP_UNLOCK(sc); 1431 1432 /* 1433 * Start stats updater. 1434 */ 1435 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1436} 1437 1438static void 1439fxp_set_media(sc, media) 1440 struct fxp_softc *sc; 1441 int media; 1442{ 1443 1444 switch (sc->phy_primary_device) { 1445 case FXP_PHY_DP83840: 1446 case FXP_PHY_DP83840A: 1447 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR, 1448 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) | 1449 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */ 1450 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */ 1451 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */ 1452 /* fall through */ 1453 case FXP_PHY_82553A: 1454 case FXP_PHY_82553C: /* untested */ 1455 case FXP_PHY_82555: 1456 case FXP_PHY_82555B: 1457 if (IFM_SUBTYPE(media) != IFM_AUTO) { 1458 int flags; 1459 1460 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ? 1461 FXP_PHY_BMCR_SPEED_100M : 0; 1462 flags |= (media & IFM_FDX) ? 1463 FXP_PHY_BMCR_FULLDUPLEX : 0; 1464 fxp_mdi_write(sc, sc->phy_primary_addr, 1465 FXP_PHY_BMCR, 1466 (fxp_mdi_read(sc, sc->phy_primary_addr, 1467 FXP_PHY_BMCR) & 1468 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M | 1469 FXP_PHY_BMCR_FULLDUPLEX)) | flags); 1470 } else { 1471 fxp_mdi_write(sc, sc->phy_primary_addr, 1472 FXP_PHY_BMCR, 1473 (fxp_mdi_read(sc, sc->phy_primary_addr, 1474 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN)); 1475 } 1476 break; 1477 /* 1478 * The Seeq 80c24 doesn't have a PHY programming interface, so do 1479 * nothing. 1480 */ 1481 case FXP_PHY_80C24: 1482 break; 1483 default: 1484 printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n", 1485 FXP_UNIT(sc), sc->phy_primary_device, 1486 sc->phy_primary_addr); 1487 } 1488} 1489 1490/* 1491 * Change media according to request. 1492 */ 1493int 1494fxp_mediachange(ifp) 1495 struct ifnet *ifp; 1496{ 1497 struct fxp_softc *sc = ifp->if_softc; 1498 struct ifmedia *ifm = &sc->sc_media; 1499 1500 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1501 return (EINVAL); 1502 1503 fxp_set_media(sc, ifm->ifm_media); 1504 return (0); 1505} 1506 1507/* 1508 * Notify the world which media we're using. 1509 */ 1510void 1511fxp_mediastatus(ifp, ifmr) 1512 struct ifnet *ifp; 1513 struct ifmediareq *ifmr; 1514{ 1515 struct fxp_softc *sc = ifp->if_softc; 1516 int flags, stsflags; 1517 1518 switch (sc->phy_primary_device) { 1519 case FXP_PHY_82555: 1520 case FXP_PHY_82555B: 1521 case FXP_PHY_DP83840: 1522 case FXP_PHY_DP83840A: 1523 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */ 1524 ifmr->ifm_active = IFM_ETHER; 1525 /* 1526 * the following is not an error. 1527 * You need to read this register twice to get current 1528 * status. This is correct documented behaviour, the 1529 * first read gets latched values. 1530 */ 1531 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1532 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1533 if (stsflags & FXP_PHY_STS_LINK_STS) 1534 ifmr->ifm_status |= IFM_ACTIVE; 1535 1536 /* 1537 * If we are in auto mode, then try report the result. 1538 */ 1539 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR); 1540 if (flags & FXP_PHY_BMCR_AUTOEN) { 1541 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */ 1542 if (stsflags & FXP_PHY_STS_AUTO_DONE) { 1543 /* 1544 * Intel and National parts report 1545 * differently on what they found. 1546 */ 1547 if ((sc->phy_primary_device == FXP_PHY_82555) 1548 || (sc->phy_primary_device == FXP_PHY_82555B)) { 1549 flags = fxp_mdi_read(sc, 1550 sc->phy_primary_addr, 1551 FXP_PHY_USC); 1552 1553 if (flags & FXP_PHY_USC_SPEED) 1554 ifmr->ifm_active |= IFM_100_TX; 1555 else 1556 ifmr->ifm_active |= IFM_10_T; 1557 1558 if (flags & FXP_PHY_USC_DUPLEX) 1559 ifmr->ifm_active |= IFM_FDX; 1560 } else { /* it's National. only know speed */ 1561 flags = fxp_mdi_read(sc, 1562 sc->phy_primary_addr, 1563 FXP_DP83840_PAR); 1564 1565 if (flags & FXP_DP83840_PAR_SPEED_10) 1566 ifmr->ifm_active |= IFM_10_T; 1567 else 1568 ifmr->ifm_active |= IFM_100_TX; 1569 } 1570 } 1571 } else { /* in manual mode.. just report what we were set to */ 1572 if (flags & FXP_PHY_BMCR_SPEED_100M) 1573 ifmr->ifm_active |= IFM_100_TX; 1574 else 1575 ifmr->ifm_active |= IFM_10_T; 1576 1577 if (flags & FXP_PHY_BMCR_FULLDUPLEX) 1578 ifmr->ifm_active |= IFM_FDX; 1579 } 1580 break; 1581 1582 case FXP_PHY_80C24: 1583 default: 1584 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */ 1585 } 1586} 1587 1588/* 1589 * Add a buffer to the end of the RFA buffer list. 1590 * Return 0 if successful, 1 for failure. A failure results in 1591 * adding the 'oldm' (if non-NULL) on to the end of the list - 1592 * tossing out its old contents and recycling it. 1593 * The RFA struct is stuck at the beginning of mbuf cluster and the 1594 * data pointer is fixed up to point just past it. 1595 */ 1596static int 1597fxp_add_rfabuf(sc, oldm) 1598 struct fxp_softc *sc; 1599 struct mbuf *oldm; 1600{ 1601 u_int32_t v; 1602 struct mbuf *m; 1603 struct fxp_rfa *rfa, *p_rfa; 1604 1605 MGETHDR(m, M_DONTWAIT, MT_DATA); 1606 if (m != NULL) { 1607 MCLGET(m, M_DONTWAIT); 1608 if ((m->m_flags & M_EXT) == 0) { 1609 m_freem(m); 1610 if (oldm == NULL) 1611 return 1; 1612 m = oldm; 1613 m->m_data = m->m_ext.ext_buf; 1614 } 1615 } else { 1616 if (oldm == NULL) 1617 return 1; 1618 m = oldm; 1619 m->m_data = m->m_ext.ext_buf; 1620 } 1621 1622 /* 1623 * Move the data pointer up so that the incoming data packet 1624 * will be 32-bit aligned. 1625 */ 1626 m->m_data += RFA_ALIGNMENT_FUDGE; 1627 1628 /* 1629 * Get a pointer to the base of the mbuf cluster and move 1630 * data start past it. 1631 */ 1632 rfa = mtod(m, struct fxp_rfa *); 1633 m->m_data += sizeof(struct fxp_rfa); 1634 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1635 1636 /* 1637 * Initialize the rest of the RFA. Note that since the RFA 1638 * is misaligned, we cannot store values directly. Instead, 1639 * we use an optimized, inline copy. 1640 */ 1641 1642 rfa->rfa_status = 0; 1643 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1644 rfa->actual_size = 0; 1645 1646 v = -1; 1647 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1648 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1649 1650 /* 1651 * If there are other buffers already on the list, attach this 1652 * one to the end by fixing up the tail to point to this one. 1653 */ 1654 if (sc->rfa_headm != NULL) { 1655 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1656 RFA_ALIGNMENT_FUDGE); 1657 sc->rfa_tailm->m_next = m; 1658 v = vtophys(rfa); 1659 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1660 p_rfa->rfa_control = 0; 1661 } else { 1662 sc->rfa_headm = m; 1663 } 1664 sc->rfa_tailm = m; 1665 1666 return (m == oldm); 1667} 1668 1669static volatile int 1670fxp_mdi_read(sc, phy, reg) 1671 struct fxp_softc *sc; 1672 int phy; 1673 int reg; 1674{ 1675 int count = 10000; 1676 int value; 1677 1678 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1679 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1680 1681 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1682 && count--) 1683 DELAY(10); 1684 1685 if (count <= 0) 1686 printf("fxp%d: fxp_mdi_read: timed out\n", FXP_UNIT(sc)); 1687 1688 return (value & 0xffff); 1689} 1690 1691static void 1692fxp_mdi_write(sc, phy, reg, value) 1693 struct fxp_softc *sc; 1694 int phy; 1695 int reg; 1696 int value; 1697{ 1698 int count = 10000; 1699 1700 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1701 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1702 (value & 0xffff)); 1703 1704 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1705 count--) 1706 DELAY(10); 1707 1708 if (count <= 0) 1709 printf("fxp%d: fxp_mdi_write: timed out\n", FXP_UNIT(sc)); 1710} 1711 1712static int 1713fxp_ioctl(ifp, command, data) 1714 struct ifnet *ifp; 1715 u_long command; 1716 caddr_t data; 1717{ 1718 struct fxp_softc *sc = ifp->if_softc; 1719 struct ifreq *ifr = (struct ifreq *)data; 1720 int error = 0; 1721 1722 FXP_LOCK(sc); 1723 1724 switch (command) { 1725 1726 case SIOCSIFADDR: 1727 case SIOCGIFADDR: 1728 case SIOCSIFMTU: 1729 error = ether_ioctl(ifp, command, data); 1730 break; 1731 1732 case SIOCSIFFLAGS: 1733 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1734 1735 /* 1736 * If interface is marked up and not running, then start it. 1737 * If it is marked down and running, stop it. 1738 * XXX If it's up then re-initialize it. This is so flags 1739 * such as IFF_PROMISC are handled. 1740 */ 1741 if (ifp->if_flags & IFF_UP) { 1742 fxp_init(sc); 1743 } else { 1744 if (ifp->if_flags & IFF_RUNNING) 1745 fxp_stop(sc); 1746 } 1747 break; 1748 1749 case SIOCADDMULTI: 1750 case SIOCDELMULTI: 1751 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1752 /* 1753 * Multicast list has changed; set the hardware filter 1754 * accordingly. 1755 */ 1756 if (!sc->all_mcasts) 1757 fxp_mc_setup(sc); 1758 /* 1759 * fxp_mc_setup() can turn on sc->all_mcasts, so check it 1760 * again rather than else {}. 1761 */ 1762 if (sc->all_mcasts) 1763 fxp_init(sc); 1764 error = 0; 1765 break; 1766 1767 case SIOCSIFMEDIA: 1768 case SIOCGIFMEDIA: 1769 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1770 break; 1771 1772 default: 1773 error = EINVAL; 1774 } 1775 FXP_UNLOCK(sc); 1776 return (error); 1777} 1778 1779/* 1780 * Program the multicast filter. 1781 * 1782 * We have an artificial restriction that the multicast setup command 1783 * must be the first command in the chain, so we take steps to ensure 1784 * this. By requiring this, it allows us to keep up the performance of 1785 * the pre-initialized command ring (esp. link pointers) by not actually 1786 * inserting the mcsetup command in the ring - i.e. its link pointer 1787 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1788 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1789 * lead into the regular TxCB ring when it completes. 1790 * 1791 * This function must be called at splimp. 1792 */ 1793static void 1794fxp_mc_setup(sc) 1795 struct fxp_softc *sc; 1796{ 1797 struct fxp_cb_mcs *mcsp = sc->mcsp; 1798 struct ifnet *ifp = &sc->sc_if; 1799 struct ifmultiaddr *ifma; 1800 int nmcasts; 1801 int count; 1802 1803 /* 1804 * If there are queued commands, we must wait until they are all 1805 * completed. If we are already waiting, then add a NOP command 1806 * with interrupt option so that we're notified when all commands 1807 * have been completed - fxp_start() ensures that no additional 1808 * TX commands will be added when need_mcsetup is true. 1809 */ 1810 if (sc->tx_queued) { 1811 struct fxp_cb_tx *txp; 1812 1813 /* 1814 * need_mcsetup will be true if we are already waiting for the 1815 * NOP command to be completed (see below). In this case, bail. 1816 */ 1817 if (sc->need_mcsetup) 1818 return; 1819 sc->need_mcsetup = 1; 1820 1821 /* 1822 * Add a NOP command with interrupt so that we are notified when all 1823 * TX commands have been processed. 1824 */ 1825 txp = sc->cbl_last->next; 1826 txp->mb_head = NULL; 1827 txp->cb_status = 0; 1828 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1829 /* 1830 * Advance the end of list forward. 1831 */ 1832 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1833 sc->cbl_last = txp; 1834 sc->tx_queued++; 1835 /* 1836 * Issue a resume in case the CU has just suspended. 1837 */ 1838 fxp_scb_wait(sc); 1839 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1840 /* 1841 * Set a 5 second timer just in case we don't hear from the 1842 * card again. 1843 */ 1844 ifp->if_timer = 5; 1845 1846 return; 1847 } 1848 sc->need_mcsetup = 0; 1849 1850 /* 1851 * Initialize multicast setup descriptor. 1852 */ 1853 mcsp->next = sc->cbl_base; 1854 mcsp->mb_head = NULL; 1855 mcsp->cb_status = 0; 1856 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1857 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1858 1859 nmcasts = 0; 1860 if (!sc->all_mcasts) { 1861 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1862 ifma = ifma->ifma_link.le_next) { 1863 if (ifma->ifma_addr->sa_family != AF_LINK) 1864 continue; 1865 if (nmcasts >= MAXMCADDR) { 1866 sc->all_mcasts = 1; 1867 nmcasts = 0; 1868 break; 1869 } 1870 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1871 (void *)(uintptr_t)(volatile void *) 1872 &sc->mcsp->mc_addr[nmcasts][0], 6); 1873 nmcasts++; 1874 } 1875 } 1876 mcsp->mc_cnt = nmcasts * 6; 1877 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1878 sc->tx_queued = 1; 1879 1880 /* 1881 * Wait until command unit is not active. This should never 1882 * be the case when nothing is queued, but make sure anyway. 1883 */ 1884 count = 100; 1885 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1886 FXP_SCB_CUS_ACTIVE && --count) 1887 DELAY(10); 1888 if (count == 0) { 1889 printf("fxp%d: command queue timeout\n", FXP_UNIT(sc)); 1890 return; 1891 } 1892 1893 /* 1894 * Start the multicast setup command. 1895 */ 1896 fxp_scb_wait(sc); 1897 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1898 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1899 1900 ifp->if_timer = 2; 1901 return; 1902} 1903