if_fxp.c revision 66281
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Modifications to support media selection: 6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 66281 2000-09-23 00:01:37Z jasone $ 31 */ 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59#include <machine/mutex.h> 60 61#include <net/ethernet.h> 62#include <net/if_arp.h> 63 64#include <vm/vm.h> /* for vtophys */ 65#include <vm/pmap.h> /* for vtophys */ 66#include <machine/clock.h> /* for DELAY */ 67 68#include <pci/pcivar.h> 69#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 70#include <pci/if_fxpreg.h> 71#include <pci/if_fxpvar.h> 72 73#ifdef __alpha__ /* XXX */ 74/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 75#undef vtophys 76#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 77#endif /* __alpha__ */ 78 79/* 80 * NOTE! On the Alpha, we have an alignment constraint. The 81 * card DMAs the packet immediately following the RFA. However, 82 * the first thing in the packet is a 14-byte Ethernet header. 83 * This means that the packet is misaligned. To compensate, 84 * we actually offset the RFA 2 bytes into the cluster. This 85 * alignes the packet after the Ethernet header at a 32-bit 86 * boundary. HOWEVER! This means that the RFA is misaligned! 87 */ 88#define RFA_ALIGNMENT_FUDGE 2 89 90/* 91 * Inline function to copy a 16-bit aligned 32-bit quantity. 92 */ 93static __inline void fxp_lwcopy __P((volatile u_int32_t *, 94 volatile u_int32_t *)); 95static __inline void 96fxp_lwcopy(src, dst) 97 volatile u_int32_t *src, *dst; 98{ 99#ifdef __i386__ 100 *dst = *src; 101#else 102 volatile u_int16_t *a = (volatile u_int16_t *)src; 103 volatile u_int16_t *b = (volatile u_int16_t *)dst; 104 105 b[0] = a[0]; 106 b[1] = a[1]; 107#endif 108} 109 110/* 111 * Template for default configuration parameters. 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x80, 0x2, /* cb_command */ 117 0xff, 0xff, 0xff, 0xff, /* link_addr */ 118 0x16, /* 0 */ 119 0x8, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x80, /* 5 */ 124 0xb2, /* 6 */ 125 0x3, /* 7 */ 126 0x1, /* 8 */ 127 0x0, /* 9 */ 128 0x26, /* 10 */ 129 0x0, /* 11 */ 130 0x60, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf3, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142/* Supported media types. */ 143struct fxp_supported_media { 144 const int fsm_phy; /* PHY type */ 145 const int *fsm_media; /* the media array */ 146 const int fsm_nmedia; /* the number of supported media */ 147 const int fsm_defmedia; /* default media for this PHY */ 148}; 149 150static const int fxp_media_standard[] = { 151 IFM_ETHER|IFM_10_T, 152 IFM_ETHER|IFM_10_T|IFM_FDX, 153 IFM_ETHER|IFM_100_TX, 154 IFM_ETHER|IFM_100_TX|IFM_FDX, 155 IFM_ETHER|IFM_AUTO, 156}; 157#define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO) 158 159static const int fxp_media_default[] = { 160 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */ 161}; 162#define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL) 163 164static const struct fxp_supported_media fxp_media[] = { 165 { FXP_PHY_DP83840, fxp_media_standard, 166 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 167 FXP_MEDIA_STANDARD_DEFMEDIA }, 168 { FXP_PHY_DP83840A, fxp_media_standard, 169 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 170 FXP_MEDIA_STANDARD_DEFMEDIA }, 171 { FXP_PHY_82553A, fxp_media_standard, 172 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 173 FXP_MEDIA_STANDARD_DEFMEDIA }, 174 { FXP_PHY_82553C, fxp_media_standard, 175 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 176 FXP_MEDIA_STANDARD_DEFMEDIA }, 177 { FXP_PHY_82555, fxp_media_standard, 178 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 179 FXP_MEDIA_STANDARD_DEFMEDIA }, 180 { FXP_PHY_82555B, fxp_media_standard, 181 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 182 FXP_MEDIA_STANDARD_DEFMEDIA }, 183 { FXP_PHY_80C24, fxp_media_default, 184 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]), 185 FXP_MEDIA_DEFAULT_DEFMEDIA }, 186}; 187#define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0])) 188 189static int fxp_mediachange __P((struct ifnet *)); 190static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *)); 191static void fxp_set_media __P((struct fxp_softc *, int)); 192static __inline void fxp_scb_wait __P((struct fxp_softc *)); 193static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc)); 194static void fxp_intr __P((void *)); 195static void fxp_start __P((struct ifnet *)); 196static int fxp_ioctl __P((struct ifnet *, 197 u_long, caddr_t)); 198static void fxp_init __P((void *)); 199static void fxp_stop __P((struct fxp_softc *)); 200static void fxp_watchdog __P((struct ifnet *)); 201static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *)); 202static int fxp_mdi_read __P((struct fxp_softc *, int, int)); 203static void fxp_mdi_write __P((struct fxp_softc *, int, int, int)); 204static void fxp_autosize_eeprom __P((struct fxp_softc *)); 205static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, 206 int, int)); 207static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *)); 208static void fxp_stats_update __P((void *)); 209static void fxp_mc_setup __P((struct fxp_softc *)); 210 211/* 212 * Set initial transmit threshold at 64 (512 bytes). This is 213 * increased by 64 (512 bytes) at a time, to maximum of 192 214 * (1536 bytes), if an underrun occurs. 215 */ 216static int tx_threshold = 64; 217 218/* 219 * Number of transmit control blocks. This determines the number 220 * of transmit buffers that can be chained in the CB list. 221 * This must be a power of two. 222 */ 223#define FXP_NTXCB 128 224 225/* 226 * Number of completed TX commands at which point an interrupt 227 * will be generated to garbage collect the attached buffers. 228 * Must be at least one less than FXP_NTXCB, and should be 229 * enough less so that the transmitter doesn't becomes idle 230 * during the buffer rundown (which would reduce performance). 231 */ 232#define FXP_CXINT_THRESH 120 233 234/* 235 * TxCB list index mask. This is used to do list wrap-around. 236 */ 237#define FXP_TXCB_MASK (FXP_NTXCB - 1) 238 239/* 240 * Number of receive frame area buffers. These are large so chose 241 * wisely. 242 */ 243#define FXP_NRFABUFS 64 244 245/* 246 * Maximum number of seconds that the receiver can be idle before we 247 * assume it's dead and attempt to reset it by reprogramming the 248 * multicast filter. This is part of a work-around for a bug in the 249 * NIC. See fxp_stats_update(). 250 */ 251#define FXP_MAX_RX_IDLE 15 252 253/* 254 * Wait for the previous command to be accepted (but not necessarily 255 * completed). 256 */ 257static __inline void 258fxp_scb_wait(sc) 259 struct fxp_softc *sc; 260{ 261 int i = 10000; 262 263 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 264 DELAY(2); 265 if (i == 0) 266 printf("fxp%d: SCB timeout\n", FXP_UNIT(sc)); 267} 268 269static __inline void 270fxp_dma_wait(status, sc) 271 volatile u_int16_t *status; 272 struct fxp_softc *sc; 273{ 274 int i = 10000; 275 276 while (!(*status & FXP_CB_STATUS_C) && --i) 277 DELAY(2); 278 if (i == 0) 279 printf("fxp%d: DMA timeout\n", FXP_UNIT(sc)); 280} 281 282/* 283 * Return identification string if this is device is ours. 284 */ 285static int 286fxp_probe(device_t dev) 287{ 288 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 289 switch (pci_get_device(dev)) { 290 291 case FXP_DEVICEID_i82557: 292 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet"); 293 return 0; 294 case FXP_DEVICEID_i82559: 295 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet"); 296 return 0; 297 case FXP_DEVICEID_i82559ER: 298 device_set_desc(dev, "Intel Embedded 10/100 Ethernet"); 299 return 0; 300 case FXP_DEVICEID_i82562: 301 device_set_desc(dev, "Intel PLC 10/100 Ethernet"); 302 return 0; 303 default: 304 break; 305 } 306 } 307 308 return ENXIO; 309} 310 311static int 312fxp_attach(device_t dev) 313{ 314 int error = 0; 315 struct fxp_softc *sc = device_get_softc(dev); 316 struct ifnet *ifp; 317 u_long val; 318 int rid; 319 320 mtx_init(&sc->sc_mtx, "fxp", MTX_DEF); 321 callout_handle_init(&sc->stat_ch); 322 323 FXP_LOCK(sc); 324 325 /* 326 * Enable bus mastering. 327 */ 328 val = pci_read_config(dev, PCIR_COMMAND, 2); 329 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 330 pci_write_config(dev, PCIR_COMMAND, val, 2); 331 332 /* 333 * Map control/status registers. 334 */ 335 rid = FXP_PCI_MMBA; 336 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 337 0, ~0, 1, RF_ACTIVE); 338 if (!sc->mem) { 339 device_printf(dev, "could not map memory\n"); 340 error = ENXIO; 341 goto fail; 342 } 343 344 sc->sc_st = rman_get_bustag(sc->mem); 345 sc->sc_sh = rman_get_bushandle(sc->mem); 346 347 /* 348 * Allocate our interrupt. 349 */ 350 rid = 0; 351 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 352 RF_SHAREABLE | RF_ACTIVE); 353 if (sc->irq == NULL) { 354 device_printf(dev, "could not map interrupt\n"); 355 error = ENXIO; 356 goto fail; 357 } 358 359 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 360 fxp_intr, sc, &sc->ih); 361 if (error) { 362 device_printf(dev, "could not setup irq\n"); 363 goto fail; 364 } 365 366 /* Do generic parts of attach. */ 367 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) { 368 /* Failed! */ 369 bus_teardown_intr(dev, sc->irq, sc->ih); 370 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 371 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 372 error = ENXIO; 373 goto fail; 374 } 375 376 device_printf(dev, "Ethernet address %6D%s\n", 377 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : ""); 378 379 ifp = &sc->arpcom.ac_if; 380 ifp->if_unit = device_get_unit(dev); 381 ifp->if_name = "fxp"; 382 ifp->if_output = ether_output; 383 ifp->if_baudrate = 100000000; 384 ifp->if_init = fxp_init; 385 ifp->if_softc = sc; 386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 387 ifp->if_ioctl = fxp_ioctl; 388 ifp->if_start = fxp_start; 389 ifp->if_watchdog = fxp_watchdog; 390 391 /* 392 * Attach the interface. 393 */ 394 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 395 /* 396 * Let the system queue as many packets as we have available 397 * TX descriptors. 398 */ 399 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 400 401 FXP_UNLOCK(sc); 402 return 0; 403 404 fail: 405 FXP_UNLOCK(sc); 406 mtx_destroy(&sc->sc_mtx); 407 return error; 408} 409 410/* 411 * Detach interface. 412 */ 413static int 414fxp_detach(device_t dev) 415{ 416 struct fxp_softc *sc = device_get_softc(dev); 417 418 FXP_LOCK(sc); 419 420 /* 421 * Close down routes etc. 422 */ 423 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 424 425 /* 426 * Stop DMA and drop transmit queue. 427 */ 428 fxp_stop(sc); 429 430 /* 431 * Deallocate resources. 432 */ 433 bus_teardown_intr(dev, sc->irq, sc->ih); 434 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 435 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 436 437 /* 438 * Free all the receive buffers. 439 */ 440 if (sc->rfa_headm != NULL) 441 m_freem(sc->rfa_headm); 442 443 /* 444 * Free all media structures. 445 */ 446 ifmedia_removeall(&sc->sc_media); 447 448 /* 449 * Free anciliary structures. 450 */ 451 free(sc->cbl_base, M_DEVBUF); 452 free(sc->fxp_stats, M_DEVBUF); 453 free(sc->mcsp, M_DEVBUF); 454 455 FXP_UNLOCK(sc); 456 457 return 0; 458} 459 460/* 461 * Device shutdown routine. Called at system shutdown after sync. The 462 * main purpose of this routine is to shut off receiver DMA so that 463 * kernel memory doesn't get clobbered during warmboot. 464 */ 465static int 466fxp_shutdown(device_t dev) 467{ 468 /* 469 * Make sure that DMA is disabled prior to reboot. Not doing 470 * do could allow DMA to corrupt kernel memory during the 471 * reboot before the driver initializes. 472 */ 473 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 474 return 0; 475} 476 477/* 478 * Device suspend routine. Stop the interface and save some PCI 479 * settings in case the BIOS doesn't restore them properly on 480 * resume. 481 */ 482static int 483fxp_suspend(device_t dev) 484{ 485 struct fxp_softc *sc = device_get_softc(dev); 486 int i; 487 488 FXP_LOCK(sc); 489 490 fxp_stop(sc); 491 492 for (i=0; i<5; i++) 493 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 494 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 495 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 496 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 497 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 498 499 sc->suspended = 1; 500 501 FXP_UNLOCK(sc); 502 503 return 0; 504} 505 506/* 507 * Device resume routine. Restore some PCI settings in case the BIOS 508 * doesn't, re-enable busmastering, and restart the interface if 509 * appropriate. 510 */ 511static int 512fxp_resume(device_t dev) 513{ 514 struct fxp_softc *sc = device_get_softc(dev); 515 struct ifnet *ifp = &sc->sc_if; 516 u_int16_t pci_command; 517 int i; 518 519 FXP_LOCK(sc); 520 521 /* better way to do this? */ 522 for (i=0; i<5; i++) 523 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 524 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 525 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 526 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 527 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 528 529 /* reenable busmastering */ 530 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 531 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 532 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 533 534 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 535 DELAY(10); 536 537 /* reinitialize interface if necessary */ 538 if (ifp->if_flags & IFF_UP) 539 fxp_init(sc); 540 541 sc->suspended = 0; 542 543 FXP_UNLOCK(sc); 544 545 return 0; 546} 547 548static device_method_t fxp_methods[] = { 549 /* Device interface */ 550 DEVMETHOD(device_probe, fxp_probe), 551 DEVMETHOD(device_attach, fxp_attach), 552 DEVMETHOD(device_detach, fxp_detach), 553 DEVMETHOD(device_shutdown, fxp_shutdown), 554 DEVMETHOD(device_suspend, fxp_suspend), 555 DEVMETHOD(device_resume, fxp_resume), 556 557 { 0, 0 } 558}; 559 560static driver_t fxp_driver = { 561 "fxp", 562 fxp_methods, 563 sizeof(struct fxp_softc), 564}; 565 566static devclass_t fxp_devclass; 567 568DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 569 570/* 571 * Do generic parts of attach. 572 */ 573static int 574fxp_attach_common(sc, enaddr) 575 struct fxp_softc *sc; 576 u_int8_t *enaddr; 577{ 578 u_int16_t data; 579 int i, nmedia, defmedia; 580 const int *media; 581 582 /* 583 * Reset to a stable state. 584 */ 585 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 586 DELAY(10); 587 588 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 589 M_DEVBUF, M_NOWAIT); 590 if (sc->cbl_base == NULL) 591 goto fail; 592 bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 593 594 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT); 595 if (sc->fxp_stats == NULL) 596 goto fail; 597 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 598 599 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 600 if (sc->mcsp == NULL) 601 goto fail; 602 603 /* 604 * Pre-allocate our receive buffers. 605 */ 606 for (i = 0; i < FXP_NRFABUFS; i++) { 607 if (fxp_add_rfabuf(sc, NULL) != 0) { 608 goto fail; 609 } 610 } 611 612 /* 613 * Find out how large of an SEEPROM we have. 614 */ 615 fxp_autosize_eeprom(sc); 616 617 /* 618 * Get info about the primary PHY 619 */ 620 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1); 621 sc->phy_primary_addr = data & 0xff; 622 sc->phy_primary_device = (data >> 8) & 0x3f; 623 sc->phy_10Mbps_only = data >> 15; 624 625 /* 626 * Read MAC address. 627 */ 628 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3); 629 630 /* 631 * Initialize the media structures. 632 */ 633 634 media = fxp_media_default; 635 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]); 636 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA; 637 638 for (i = 0; i < NFXPMEDIA; i++) { 639 if (sc->phy_primary_device == fxp_media[i].fsm_phy) { 640 media = fxp_media[i].fsm_media; 641 nmedia = fxp_media[i].fsm_nmedia; 642 defmedia = fxp_media[i].fsm_defmedia; 643 } 644 } 645 646 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus); 647 for (i = 0; i < nmedia; i++) { 648 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only) 649 continue; 650 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 651 } 652 ifmedia_set(&sc->sc_media, defmedia); 653 654 return (0); 655 656 fail: 657 printf("fxp%d: Failed to malloc memory\n", FXP_UNIT(sc)); 658 if (sc->cbl_base) 659 free(sc->cbl_base, M_DEVBUF); 660 if (sc->fxp_stats) 661 free(sc->fxp_stats, M_DEVBUF); 662 if (sc->mcsp) 663 free(sc->mcsp, M_DEVBUF); 664 /* frees entire chain */ 665 if (sc->rfa_headm) 666 m_freem(sc->rfa_headm); 667 668 return (ENOMEM); 669} 670 671/* 672 * From NetBSD: 673 * 674 * Figure out EEPROM size. 675 * 676 * 559's can have either 64-word or 256-word EEPROMs, the 558 677 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 678 * talks about the existance of 16 to 256 word EEPROMs. 679 * 680 * The only known sizes are 64 and 256, where the 256 version is used 681 * by CardBus cards to store CIS information. 682 * 683 * The address is shifted in msb-to-lsb, and after the last 684 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 685 * after which follows the actual data. We try to detect this zero, by 686 * probing the data-out bit in the EEPROM control register just after 687 * having shifted in a bit. If the bit is zero, we assume we've 688 * shifted enough address bits. The data-out should be tri-state, 689 * before this, which should translate to a logical one. 690 * 691 * Other ways to do this would be to try to read a register with known 692 * contents with a varying number of address bits, but no such 693 * register seem to be available. The high bits of register 10 are 01 694 * on the 558 and 559, but apparently not on the 557. 695 * 696 * The Linux driver computes a checksum on the EEPROM data, but the 697 * value of this checksum is not very well documented. 698 */ 699static void 700fxp_autosize_eeprom(sc) 701 struct fxp_softc *sc; 702{ 703 u_int16_t reg; 704 int x; 705 706 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 707 /* 708 * Shift in read opcode. 709 */ 710 for (x = 3; x > 0; x--) { 711 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 712 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 713 } else { 714 reg = FXP_EEPROM_EECS; 715 } 716 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 717 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 718 reg | FXP_EEPROM_EESK); 719 DELAY(1); 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 721 DELAY(1); 722 } 723 /* 724 * Shift in address. 725 * Wait for the dummy zero following a correct address shift. 726 */ 727 for (x = 1; x <= 8; x++) { 728 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 729 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 730 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 731 DELAY(1); 732 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0) 733 break; 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 735 DELAY(1); 736 } 737 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 738 DELAY(1); 739 sc->eeprom_size = x; 740} 741/* 742 * Read from the serial EEPROM. Basically, you manually shift in 743 * the read opcode (one bit at a time) and then shift in the address, 744 * and then you shift out the data (all of this one bit at a time). 745 * The word size is 16 bits, so you have to provide the address for 746 * every 16 bits of data. 747 */ 748static void 749fxp_read_eeprom(sc, data, offset, words) 750 struct fxp_softc *sc; 751 u_short *data; 752 int offset; 753 int words; 754{ 755 u_int16_t reg; 756 int i, x; 757 758 for (i = 0; i < words; i++) { 759 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 760 /* 761 * Shift in read opcode. 762 */ 763 for (x = 3; x > 0; x--) { 764 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 765 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 766 } else { 767 reg = FXP_EEPROM_EECS; 768 } 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 771 reg | FXP_EEPROM_EESK); 772 DELAY(1); 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 774 DELAY(1); 775 } 776 /* 777 * Shift in address. 778 */ 779 for (x = sc->eeprom_size; x > 0; x--) { 780 if ((i + offset) & (1 << (x - 1))) { 781 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 782 } else { 783 reg = FXP_EEPROM_EECS; 784 } 785 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 786 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 787 reg | FXP_EEPROM_EESK); 788 DELAY(1); 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 790 DELAY(1); 791 } 792 reg = FXP_EEPROM_EECS; 793 data[i] = 0; 794 /* 795 * Shift out data. 796 */ 797 for (x = 16; x > 0; x--) { 798 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 799 reg | FXP_EEPROM_EESK); 800 DELAY(1); 801 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 802 FXP_EEPROM_EEDO) 803 data[i] |= (1 << (x - 1)); 804 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 805 DELAY(1); 806 } 807 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 808 DELAY(1); 809 } 810} 811 812/* 813 * Start packet transmission on the interface. 814 */ 815static void 816fxp_start(ifp) 817 struct ifnet *ifp; 818{ 819 struct fxp_softc *sc = ifp->if_softc; 820 struct fxp_cb_tx *txp; 821 822 FXP_LOCK(sc); 823 /* 824 * See if we need to suspend xmit until the multicast filter 825 * has been reprogrammed (which can only be done at the head 826 * of the command chain). 827 */ 828 if (sc->need_mcsetup) { 829 FXP_UNLOCK(sc); 830 return; 831 } 832 833 txp = NULL; 834 835 /* 836 * We're finished if there is nothing more to add to the list or if 837 * we're all filled up with buffers to transmit. 838 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 839 * a NOP command when needed. 840 */ 841 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 842 struct mbuf *m, *mb_head; 843 int segment; 844 845 /* 846 * Grab a packet to transmit. 847 */ 848 IF_DEQUEUE(&ifp->if_snd, mb_head); 849 850 /* 851 * Get pointer to next available tx desc. 852 */ 853 txp = sc->cbl_last->next; 854 855 /* 856 * Go through each of the mbufs in the chain and initialize 857 * the transmit buffer descriptors with the physical address 858 * and size of the mbuf. 859 */ 860tbdinit: 861 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 862 if (m->m_len != 0) { 863 if (segment == FXP_NTXSEG) 864 break; 865 txp->tbd[segment].tb_addr = 866 vtophys(mtod(m, vm_offset_t)); 867 txp->tbd[segment].tb_size = m->m_len; 868 segment++; 869 } 870 } 871 if (m != NULL) { 872 struct mbuf *mn; 873 874 /* 875 * We ran out of segments. We have to recopy this mbuf 876 * chain first. Bail out if we can't get the new buffers. 877 */ 878 MGETHDR(mn, M_DONTWAIT, MT_DATA); 879 if (mn == NULL) { 880 m_freem(mb_head); 881 break; 882 } 883 if (mb_head->m_pkthdr.len > MHLEN) { 884 MCLGET(mn, M_DONTWAIT); 885 if ((mn->m_flags & M_EXT) == 0) { 886 m_freem(mn); 887 m_freem(mb_head); 888 break; 889 } 890 } 891 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 892 mtod(mn, caddr_t)); 893 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 894 m_freem(mb_head); 895 mb_head = mn; 896 goto tbdinit; 897 } 898 899 txp->tbd_number = segment; 900 txp->mb_head = mb_head; 901 txp->cb_status = 0; 902 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 903 txp->cb_command = 904 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 905 } else { 906 txp->cb_command = 907 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 908 /* 909 * Set a 5 second timer just in case we don't hear from the 910 * card again. 911 */ 912 ifp->if_timer = 5; 913 } 914 txp->tx_threshold = tx_threshold; 915 916 /* 917 * Advance the end of list forward. 918 */ 919 920#ifdef __alpha__ 921 /* 922 * On platforms which can't access memory in 16-bit 923 * granularities, we must prevent the card from DMA'ing 924 * up the status while we update the command field. 925 * This could cause us to overwrite the completion status. 926 */ 927 atomic_clear_short(&sc->cbl_last->cb_command, 928 FXP_CB_COMMAND_S); 929#else 930 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 931#endif /*__alpha__*/ 932 sc->cbl_last = txp; 933 934 /* 935 * Advance the beginning of the list forward if there are 936 * no other packets queued (when nothing is queued, cbl_first 937 * sits on the last TxCB that was sent out). 938 */ 939 if (sc->tx_queued == 0) 940 sc->cbl_first = txp; 941 942 sc->tx_queued++; 943 944 /* 945 * Pass packet to bpf if there is a listener. 946 */ 947 if (ifp->if_bpf) 948 bpf_mtap(ifp, mb_head); 949 } 950 951 /* 952 * We're finished. If we added to the list, issue a RESUME to get DMA 953 * going again if suspended. 954 */ 955 if (txp != NULL) { 956 fxp_scb_wait(sc); 957 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 958 } 959 FXP_UNLOCK(sc); 960} 961 962/* 963 * Process interface interrupts. 964 */ 965static void 966fxp_intr(arg) 967 void *arg; 968{ 969 struct fxp_softc *sc = arg; 970 struct ifnet *ifp = &sc->sc_if; 971 u_int8_t statack; 972 973 FXP_LOCK(sc); 974 975 if (sc->suspended) { 976 FXP_UNLOCK(sc); 977 return; 978 } 979 980 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 981 /* 982 * First ACK all the interrupts in this pass. 983 */ 984 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 985 986 /* 987 * Free any finished transmit mbuf chains. 988 * 989 * Handle the CNA event likt a CXTNO event. It used to 990 * be that this event (control unit not ready) was not 991 * encountered, but it is now with the SMPng modifications. 992 * The exact sequence of events that occur when the interface 993 * is brought up are different now, and if this event 994 * goes unhandled, the configuration/rxfilter setup sequence 995 * can stall for several seconds. The result is that no 996 * packets go out onto the wire for about 5 to 10 seconds 997 * after the interface is ifconfig'ed for the first time. 998 */ 999 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1000 struct fxp_cb_tx *txp; 1001 1002 for (txp = sc->cbl_first; sc->tx_queued && 1003 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1004 txp = txp->next) { 1005 if (txp->mb_head != NULL) { 1006 m_freem(txp->mb_head); 1007 txp->mb_head = NULL; 1008 } 1009 sc->tx_queued--; 1010 } 1011 sc->cbl_first = txp; 1012 ifp->if_timer = 0; 1013 if (sc->tx_queued == 0) { 1014 if (sc->need_mcsetup) 1015 fxp_mc_setup(sc); 1016 } 1017 /* 1018 * Try to start more packets transmitting. 1019 */ 1020 if (ifp->if_snd.ifq_head != NULL) 1021 fxp_start(ifp); 1022 } 1023 /* 1024 * Process receiver interrupts. If a no-resource (RNR) 1025 * condition exists, get whatever packets we can and 1026 * re-start the receiver. 1027 */ 1028 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1029 struct mbuf *m; 1030 struct fxp_rfa *rfa; 1031rcvloop: 1032 m = sc->rfa_headm; 1033 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1034 RFA_ALIGNMENT_FUDGE); 1035 1036 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1037 /* 1038 * Remove first packet from the chain. 1039 */ 1040 sc->rfa_headm = m->m_next; 1041 m->m_next = NULL; 1042 1043 /* 1044 * Add a new buffer to the receive chain. 1045 * If this fails, the old buffer is recycled 1046 * instead. 1047 */ 1048 if (fxp_add_rfabuf(sc, m) == 0) { 1049 struct ether_header *eh; 1050 int total_len; 1051 1052 total_len = rfa->actual_size & 1053 (MCLBYTES - 1); 1054 if (total_len < 1055 sizeof(struct ether_header)) { 1056 m_freem(m); 1057 goto rcvloop; 1058 } 1059 m->m_pkthdr.rcvif = ifp; 1060 m->m_pkthdr.len = m->m_len = total_len; 1061 eh = mtod(m, struct ether_header *); 1062 m->m_data += 1063 sizeof(struct ether_header); 1064 m->m_len -= 1065 sizeof(struct ether_header); 1066 m->m_pkthdr.len = m->m_len; 1067 ether_input(ifp, eh, m); 1068 } 1069 goto rcvloop; 1070 } 1071 if (statack & FXP_SCB_STATACK_RNR) { 1072 fxp_scb_wait(sc); 1073 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1074 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1075 RFA_ALIGNMENT_FUDGE); 1076 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1077 FXP_SCB_COMMAND_RU_START); 1078 } 1079 } 1080 } 1081 FXP_UNLOCK(sc); 1082} 1083 1084/* 1085 * Update packet in/out/collision statistics. The i82557 doesn't 1086 * allow you to access these counters without doing a fairly 1087 * expensive DMA to get _all_ of the statistics it maintains, so 1088 * we do this operation here only once per second. The statistics 1089 * counters in the kernel are updated from the previous dump-stats 1090 * DMA and then a new dump-stats DMA is started. The on-chip 1091 * counters are zeroed when the DMA completes. If we can't start 1092 * the DMA immediately, we don't wait - we just prepare to read 1093 * them again next time. 1094 */ 1095static void 1096fxp_stats_update(arg) 1097 void *arg; 1098{ 1099 struct fxp_softc *sc = arg; 1100 struct ifnet *ifp = &sc->sc_if; 1101 struct fxp_stats *sp = sc->fxp_stats; 1102 struct fxp_cb_tx *txp; 1103 1104 ifp->if_opackets += sp->tx_good; 1105 ifp->if_collisions += sp->tx_total_collisions; 1106 if (sp->rx_good) { 1107 ifp->if_ipackets += sp->rx_good; 1108 sc->rx_idle_secs = 0; 1109 } else { 1110 /* 1111 * Receiver's been idle for another second. 1112 */ 1113 sc->rx_idle_secs++; 1114 } 1115 ifp->if_ierrors += 1116 sp->rx_crc_errors + 1117 sp->rx_alignment_errors + 1118 sp->rx_rnr_errors + 1119 sp->rx_overrun_errors; 1120 /* 1121 * If any transmit underruns occured, bump up the transmit 1122 * threshold by another 512 bytes (64 * 8). 1123 */ 1124 if (sp->tx_underruns) { 1125 ifp->if_oerrors += sp->tx_underruns; 1126 if (tx_threshold < 192) 1127 tx_threshold += 64; 1128 } 1129 FXP_LOCK(sc); 1130 /* 1131 * Release any xmit buffers that have completed DMA. This isn't 1132 * strictly necessary to do here, but it's advantagous for mbufs 1133 * with external storage to be released in a timely manner rather 1134 * than being defered for a potentially long time. This limits 1135 * the delay to a maximum of one second. 1136 */ 1137 for (txp = sc->cbl_first; sc->tx_queued && 1138 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1139 txp = txp->next) { 1140 if (txp->mb_head != NULL) { 1141 m_freem(txp->mb_head); 1142 txp->mb_head = NULL; 1143 } 1144 sc->tx_queued--; 1145 } 1146 sc->cbl_first = txp; 1147 /* 1148 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1149 * then assume the receiver has locked up and attempt to clear 1150 * the condition by reprogramming the multicast filter. This is 1151 * a work-around for a bug in the 82557 where the receiver locks 1152 * up if it gets certain types of garbage in the syncronization 1153 * bits prior to the packet header. This bug is supposed to only 1154 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1155 * mode as well (perhaps due to a 10/100 speed transition). 1156 */ 1157 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1158 sc->rx_idle_secs = 0; 1159 fxp_mc_setup(sc); 1160 } 1161 /* 1162 * If there is no pending command, start another stats 1163 * dump. Otherwise punt for now. 1164 */ 1165 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1166 /* 1167 * Start another stats dump. 1168 */ 1169 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1170 FXP_SCB_COMMAND_CU_DUMPRESET); 1171 } else { 1172 /* 1173 * A previous command is still waiting to be accepted. 1174 * Just zero our copy of the stats and wait for the 1175 * next timer event to update them. 1176 */ 1177 sp->tx_good = 0; 1178 sp->tx_underruns = 0; 1179 sp->tx_total_collisions = 0; 1180 1181 sp->rx_good = 0; 1182 sp->rx_crc_errors = 0; 1183 sp->rx_alignment_errors = 0; 1184 sp->rx_rnr_errors = 0; 1185 sp->rx_overrun_errors = 0; 1186 } 1187 FXP_UNLOCK(sc); 1188 /* 1189 * Schedule another timeout one second from now. 1190 */ 1191 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1192} 1193 1194/* 1195 * Stop the interface. Cancels the statistics updater and resets 1196 * the interface. 1197 */ 1198static void 1199fxp_stop(sc) 1200 struct fxp_softc *sc; 1201{ 1202 struct ifnet *ifp = &sc->sc_if; 1203 struct fxp_cb_tx *txp; 1204 int i; 1205 1206 FXP_LOCK(sc); 1207 1208 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1209 ifp->if_timer = 0; 1210 1211 /* 1212 * Cancel stats updater. 1213 */ 1214 untimeout(fxp_stats_update, sc, sc->stat_ch); 1215 1216 /* 1217 * Issue software reset 1218 */ 1219 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1220 DELAY(10); 1221 1222 /* 1223 * Release any xmit buffers. 1224 */ 1225 txp = sc->cbl_base; 1226 if (txp != NULL) { 1227 for (i = 0; i < FXP_NTXCB; i++) { 1228 if (txp[i].mb_head != NULL) { 1229 m_freem(txp[i].mb_head); 1230 txp[i].mb_head = NULL; 1231 } 1232 } 1233 } 1234 sc->tx_queued = 0; 1235 1236 /* 1237 * Free all the receive buffers then reallocate/reinitialize 1238 */ 1239 if (sc->rfa_headm != NULL) 1240 m_freem(sc->rfa_headm); 1241 sc->rfa_headm = NULL; 1242 sc->rfa_tailm = NULL; 1243 for (i = 0; i < FXP_NRFABUFS; i++) { 1244 if (fxp_add_rfabuf(sc, NULL) != 0) { 1245 /* 1246 * This "can't happen" - we're at splimp() 1247 * and we just freed all the buffers we need 1248 * above. 1249 */ 1250 panic("fxp_stop: no buffers!"); 1251 } 1252 } 1253 1254 FXP_UNLOCK(sc); 1255} 1256 1257/* 1258 * Watchdog/transmission transmit timeout handler. Called when a 1259 * transmission is started on the interface, but no interrupt is 1260 * received before the timeout. This usually indicates that the 1261 * card has wedged for some reason. 1262 */ 1263static void 1264fxp_watchdog(ifp) 1265 struct ifnet *ifp; 1266{ 1267 struct fxp_softc *sc = ifp->if_softc; 1268 1269 printf("fxp%d: device timeout\n", FXP_UNIT(sc)); 1270 ifp->if_oerrors++; 1271 1272 fxp_init(sc); 1273} 1274 1275static void 1276fxp_init(xsc) 1277 void *xsc; 1278{ 1279 struct fxp_softc *sc = xsc; 1280 struct ifnet *ifp = &sc->sc_if; 1281 struct fxp_cb_config *cbp; 1282 struct fxp_cb_ias *cb_ias; 1283 struct fxp_cb_tx *txp; 1284 int i, prm; 1285 1286 FXP_LOCK(sc); 1287 /* 1288 * Cancel any pending I/O 1289 */ 1290 fxp_stop(sc); 1291 1292 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1293 1294 /* 1295 * Initialize base of CBL and RFA memory. Loading with zero 1296 * sets it up for regular linear addressing. 1297 */ 1298 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1299 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1300 1301 fxp_scb_wait(sc); 1302 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1303 1304 /* 1305 * Initialize base of dump-stats buffer. 1306 */ 1307 fxp_scb_wait(sc); 1308 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1309 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1310 1311 /* 1312 * We temporarily use memory that contains the TxCB list to 1313 * construct the config CB. The TxCB list memory is rebuilt 1314 * later. 1315 */ 1316 cbp = (struct fxp_cb_config *) sc->cbl_base; 1317 1318 /* 1319 * This bcopy is kind of disgusting, but there are a bunch of must be 1320 * zero and must be one bits in this structure and this is the easiest 1321 * way to initialize them all to proper values. 1322 */ 1323 bcopy(fxp_cb_config_template, 1324 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1325 sizeof(fxp_cb_config_template)); 1326 1327 cbp->cb_status = 0; 1328 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1329 cbp->link_addr = -1; /* (no) next command */ 1330 cbp->byte_count = 22; /* (22) bytes to config */ 1331 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1332 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1333 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1334 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1335 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1336 cbp->dma_bce = 0; /* (disable) dma max counters */ 1337 cbp->late_scb = 0; /* (don't) defer SCB update */ 1338 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1339 cbp->ci_int = 1; /* interrupt on CU idle */ 1340 cbp->save_bf = prm; /* save bad frames */ 1341 cbp->disc_short_rx = !prm; /* discard short packets */ 1342 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1343 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1344 cbp->nsai = 1; /* (don't) disable source addr insert */ 1345 cbp->preamble_length = 2; /* (7 byte) preamble */ 1346 cbp->loopback = 0; /* (don't) loopback */ 1347 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1348 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1349 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1350 cbp->promiscuous = prm; /* promiscuous mode */ 1351 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1352 cbp->crscdt = 0; /* (CRS only) */ 1353 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1354 cbp->padding = 1; /* (do) pad short tx packets */ 1355 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1356 cbp->force_fdx = 0; /* (don't) force full duplex */ 1357 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1358 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1359 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */ 1360 1361 /* 1362 * Start the config command/DMA. 1363 */ 1364 fxp_scb_wait(sc); 1365 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1366 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1367 /* ...and wait for it to complete. */ 1368 fxp_dma_wait(&cbp->cb_status, sc); 1369 1370 /* 1371 * Now initialize the station address. Temporarily use the TxCB 1372 * memory area like we did above for the config CB. 1373 */ 1374 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1375 cb_ias->cb_status = 0; 1376 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1377 cb_ias->link_addr = -1; 1378 bcopy(sc->arpcom.ac_enaddr, 1379 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1380 sizeof(sc->arpcom.ac_enaddr)); 1381 1382 /* 1383 * Start the IAS (Individual Address Setup) command/DMA. 1384 */ 1385 fxp_scb_wait(sc); 1386 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1387 /* ...and wait for it to complete. */ 1388 fxp_dma_wait(&cb_ias->cb_status, sc); 1389 1390 /* 1391 * Initialize transmit control block (TxCB) list. 1392 */ 1393 1394 txp = sc->cbl_base; 1395 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1396 for (i = 0; i < FXP_NTXCB; i++) { 1397 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1398 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1399 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1400 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1401 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1402 } 1403 /* 1404 * Set the suspend flag on the first TxCB and start the control 1405 * unit. It will execute the NOP and then suspend. 1406 */ 1407 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1408 sc->cbl_first = sc->cbl_last = txp; 1409 sc->tx_queued = 1; 1410 1411 fxp_scb_wait(sc); 1412 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1413 1414 /* 1415 * Initialize receiver buffer area - RFA. 1416 */ 1417 fxp_scb_wait(sc); 1418 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1419 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1420 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1421 1422 /* 1423 * Set current media. 1424 */ 1425 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 1426 1427 ifp->if_flags |= IFF_RUNNING; 1428 ifp->if_flags &= ~IFF_OACTIVE; 1429 FXP_UNLOCK(sc); 1430 1431 /* 1432 * Start stats updater. 1433 */ 1434 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1435} 1436 1437static void 1438fxp_set_media(sc, media) 1439 struct fxp_softc *sc; 1440 int media; 1441{ 1442 1443 switch (sc->phy_primary_device) { 1444 case FXP_PHY_DP83840: 1445 case FXP_PHY_DP83840A: 1446 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR, 1447 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) | 1448 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */ 1449 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */ 1450 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */ 1451 /* fall through */ 1452 case FXP_PHY_82553A: 1453 case FXP_PHY_82553C: /* untested */ 1454 case FXP_PHY_82555: 1455 case FXP_PHY_82555B: 1456 if (IFM_SUBTYPE(media) != IFM_AUTO) { 1457 int flags; 1458 1459 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ? 1460 FXP_PHY_BMCR_SPEED_100M : 0; 1461 flags |= (media & IFM_FDX) ? 1462 FXP_PHY_BMCR_FULLDUPLEX : 0; 1463 fxp_mdi_write(sc, sc->phy_primary_addr, 1464 FXP_PHY_BMCR, 1465 (fxp_mdi_read(sc, sc->phy_primary_addr, 1466 FXP_PHY_BMCR) & 1467 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M | 1468 FXP_PHY_BMCR_FULLDUPLEX)) | flags); 1469 } else { 1470 fxp_mdi_write(sc, sc->phy_primary_addr, 1471 FXP_PHY_BMCR, 1472 (fxp_mdi_read(sc, sc->phy_primary_addr, 1473 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN)); 1474 } 1475 break; 1476 /* 1477 * The Seeq 80c24 doesn't have a PHY programming interface, so do 1478 * nothing. 1479 */ 1480 case FXP_PHY_80C24: 1481 break; 1482 default: 1483 printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n", 1484 FXP_UNIT(sc), sc->phy_primary_device, 1485 sc->phy_primary_addr); 1486 } 1487} 1488 1489/* 1490 * Change media according to request. 1491 */ 1492int 1493fxp_mediachange(ifp) 1494 struct ifnet *ifp; 1495{ 1496 struct fxp_softc *sc = ifp->if_softc; 1497 struct ifmedia *ifm = &sc->sc_media; 1498 1499 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1500 return (EINVAL); 1501 1502 fxp_set_media(sc, ifm->ifm_media); 1503 return (0); 1504} 1505 1506/* 1507 * Notify the world which media we're using. 1508 */ 1509void 1510fxp_mediastatus(ifp, ifmr) 1511 struct ifnet *ifp; 1512 struct ifmediareq *ifmr; 1513{ 1514 struct fxp_softc *sc = ifp->if_softc; 1515 int flags, stsflags; 1516 1517 switch (sc->phy_primary_device) { 1518 case FXP_PHY_82555: 1519 case FXP_PHY_82555B: 1520 case FXP_PHY_DP83840: 1521 case FXP_PHY_DP83840A: 1522 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */ 1523 ifmr->ifm_active = IFM_ETHER; 1524 /* 1525 * the following is not an error. 1526 * You need to read this register twice to get current 1527 * status. This is correct documented behaviour, the 1528 * first read gets latched values. 1529 */ 1530 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1531 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1532 if (stsflags & FXP_PHY_STS_LINK_STS) 1533 ifmr->ifm_status |= IFM_ACTIVE; 1534 1535 /* 1536 * If we are in auto mode, then try report the result. 1537 */ 1538 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR); 1539 if (flags & FXP_PHY_BMCR_AUTOEN) { 1540 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */ 1541 if (stsflags & FXP_PHY_STS_AUTO_DONE) { 1542 /* 1543 * Intel and National parts report 1544 * differently on what they found. 1545 */ 1546 if ((sc->phy_primary_device == FXP_PHY_82555) 1547 || (sc->phy_primary_device == FXP_PHY_82555B)) { 1548 flags = fxp_mdi_read(sc, 1549 sc->phy_primary_addr, 1550 FXP_PHY_USC); 1551 1552 if (flags & FXP_PHY_USC_SPEED) 1553 ifmr->ifm_active |= IFM_100_TX; 1554 else 1555 ifmr->ifm_active |= IFM_10_T; 1556 1557 if (flags & FXP_PHY_USC_DUPLEX) 1558 ifmr->ifm_active |= IFM_FDX; 1559 } else { /* it's National. only know speed */ 1560 flags = fxp_mdi_read(sc, 1561 sc->phy_primary_addr, 1562 FXP_DP83840_PAR); 1563 1564 if (flags & FXP_DP83840_PAR_SPEED_10) 1565 ifmr->ifm_active |= IFM_10_T; 1566 else 1567 ifmr->ifm_active |= IFM_100_TX; 1568 } 1569 } 1570 } else { /* in manual mode.. just report what we were set to */ 1571 if (flags & FXP_PHY_BMCR_SPEED_100M) 1572 ifmr->ifm_active |= IFM_100_TX; 1573 else 1574 ifmr->ifm_active |= IFM_10_T; 1575 1576 if (flags & FXP_PHY_BMCR_FULLDUPLEX) 1577 ifmr->ifm_active |= IFM_FDX; 1578 } 1579 break; 1580 1581 case FXP_PHY_80C24: 1582 default: 1583 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */ 1584 } 1585} 1586 1587/* 1588 * Add a buffer to the end of the RFA buffer list. 1589 * Return 0 if successful, 1 for failure. A failure results in 1590 * adding the 'oldm' (if non-NULL) on to the end of the list - 1591 * tossing out its old contents and recycling it. 1592 * The RFA struct is stuck at the beginning of mbuf cluster and the 1593 * data pointer is fixed up to point just past it. 1594 */ 1595static int 1596fxp_add_rfabuf(sc, oldm) 1597 struct fxp_softc *sc; 1598 struct mbuf *oldm; 1599{ 1600 u_int32_t v; 1601 struct mbuf *m; 1602 struct fxp_rfa *rfa, *p_rfa; 1603 1604 MGETHDR(m, M_DONTWAIT, MT_DATA); 1605 if (m != NULL) { 1606 MCLGET(m, M_DONTWAIT); 1607 if ((m->m_flags & M_EXT) == 0) { 1608 m_freem(m); 1609 if (oldm == NULL) 1610 return 1; 1611 m = oldm; 1612 m->m_data = m->m_ext.ext_buf; 1613 } 1614 } else { 1615 if (oldm == NULL) 1616 return 1; 1617 m = oldm; 1618 m->m_data = m->m_ext.ext_buf; 1619 } 1620 1621 /* 1622 * Move the data pointer up so that the incoming data packet 1623 * will be 32-bit aligned. 1624 */ 1625 m->m_data += RFA_ALIGNMENT_FUDGE; 1626 1627 /* 1628 * Get a pointer to the base of the mbuf cluster and move 1629 * data start past it. 1630 */ 1631 rfa = mtod(m, struct fxp_rfa *); 1632 m->m_data += sizeof(struct fxp_rfa); 1633 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1634 1635 /* 1636 * Initialize the rest of the RFA. Note that since the RFA 1637 * is misaligned, we cannot store values directly. Instead, 1638 * we use an optimized, inline copy. 1639 */ 1640 1641 rfa->rfa_status = 0; 1642 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1643 rfa->actual_size = 0; 1644 1645 v = -1; 1646 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1647 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1648 1649 /* 1650 * If there are other buffers already on the list, attach this 1651 * one to the end by fixing up the tail to point to this one. 1652 */ 1653 if (sc->rfa_headm != NULL) { 1654 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1655 RFA_ALIGNMENT_FUDGE); 1656 sc->rfa_tailm->m_next = m; 1657 v = vtophys(rfa); 1658 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1659 p_rfa->rfa_control = 0; 1660 } else { 1661 sc->rfa_headm = m; 1662 } 1663 sc->rfa_tailm = m; 1664 1665 return (m == oldm); 1666} 1667 1668static volatile int 1669fxp_mdi_read(sc, phy, reg) 1670 struct fxp_softc *sc; 1671 int phy; 1672 int reg; 1673{ 1674 int count = 10000; 1675 int value; 1676 1677 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1678 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1679 1680 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1681 && count--) 1682 DELAY(10); 1683 1684 if (count <= 0) 1685 printf("fxp%d: fxp_mdi_read: timed out\n", FXP_UNIT(sc)); 1686 1687 return (value & 0xffff); 1688} 1689 1690static void 1691fxp_mdi_write(sc, phy, reg, value) 1692 struct fxp_softc *sc; 1693 int phy; 1694 int reg; 1695 int value; 1696{ 1697 int count = 10000; 1698 1699 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1700 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1701 (value & 0xffff)); 1702 1703 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1704 count--) 1705 DELAY(10); 1706 1707 if (count <= 0) 1708 printf("fxp%d: fxp_mdi_write: timed out\n", FXP_UNIT(sc)); 1709} 1710 1711static int 1712fxp_ioctl(ifp, command, data) 1713 struct ifnet *ifp; 1714 u_long command; 1715 caddr_t data; 1716{ 1717 struct fxp_softc *sc = ifp->if_softc; 1718 struct ifreq *ifr = (struct ifreq *)data; 1719 int error = 0; 1720 1721 FXP_LOCK(sc); 1722 1723 switch (command) { 1724 1725 case SIOCSIFADDR: 1726 case SIOCGIFADDR: 1727 case SIOCSIFMTU: 1728 error = ether_ioctl(ifp, command, data); 1729 break; 1730 1731 case SIOCSIFFLAGS: 1732 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1733 1734 /* 1735 * If interface is marked up and not running, then start it. 1736 * If it is marked down and running, stop it. 1737 * XXX If it's up then re-initialize it. This is so flags 1738 * such as IFF_PROMISC are handled. 1739 */ 1740 if (ifp->if_flags & IFF_UP) { 1741 fxp_init(sc); 1742 } else { 1743 if (ifp->if_flags & IFF_RUNNING) 1744 fxp_stop(sc); 1745 } 1746 break; 1747 1748 case SIOCADDMULTI: 1749 case SIOCDELMULTI: 1750 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1751 /* 1752 * Multicast list has changed; set the hardware filter 1753 * accordingly. 1754 */ 1755 if (!sc->all_mcasts) 1756 fxp_mc_setup(sc); 1757 /* 1758 * fxp_mc_setup() can turn on sc->all_mcasts, so check it 1759 * again rather than else {}. 1760 */ 1761 if (sc->all_mcasts) 1762 fxp_init(sc); 1763 error = 0; 1764 break; 1765 1766 case SIOCSIFMEDIA: 1767 case SIOCGIFMEDIA: 1768 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1769 break; 1770 1771 default: 1772 error = EINVAL; 1773 } 1774 FXP_UNLOCK(sc); 1775 return (error); 1776} 1777 1778/* 1779 * Program the multicast filter. 1780 * 1781 * We have an artificial restriction that the multicast setup command 1782 * must be the first command in the chain, so we take steps to ensure 1783 * this. By requiring this, it allows us to keep up the performance of 1784 * the pre-initialized command ring (esp. link pointers) by not actually 1785 * inserting the mcsetup command in the ring - i.e. its link pointer 1786 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1787 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1788 * lead into the regular TxCB ring when it completes. 1789 * 1790 * This function must be called at splimp. 1791 */ 1792static void 1793fxp_mc_setup(sc) 1794 struct fxp_softc *sc; 1795{ 1796 struct fxp_cb_mcs *mcsp = sc->mcsp; 1797 struct ifnet *ifp = &sc->sc_if; 1798 struct ifmultiaddr *ifma; 1799 int nmcasts; 1800 int count; 1801 1802 /* 1803 * If there are queued commands, we must wait until they are all 1804 * completed. If we are already waiting, then add a NOP command 1805 * with interrupt option so that we're notified when all commands 1806 * have been completed - fxp_start() ensures that no additional 1807 * TX commands will be added when need_mcsetup is true. 1808 */ 1809 if (sc->tx_queued) { 1810 struct fxp_cb_tx *txp; 1811 1812 /* 1813 * need_mcsetup will be true if we are already waiting for the 1814 * NOP command to be completed (see below). In this case, bail. 1815 */ 1816 if (sc->need_mcsetup) 1817 return; 1818 sc->need_mcsetup = 1; 1819 1820 /* 1821 * Add a NOP command with interrupt so that we are notified when all 1822 * TX commands have been processed. 1823 */ 1824 txp = sc->cbl_last->next; 1825 txp->mb_head = NULL; 1826 txp->cb_status = 0; 1827 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1828 /* 1829 * Advance the end of list forward. 1830 */ 1831 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1832 sc->cbl_last = txp; 1833 sc->tx_queued++; 1834 /* 1835 * Issue a resume in case the CU has just suspended. 1836 */ 1837 fxp_scb_wait(sc); 1838 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1839 /* 1840 * Set a 5 second timer just in case we don't hear from the 1841 * card again. 1842 */ 1843 ifp->if_timer = 5; 1844 1845 return; 1846 } 1847 sc->need_mcsetup = 0; 1848 1849 /* 1850 * Initialize multicast setup descriptor. 1851 */ 1852 mcsp->next = sc->cbl_base; 1853 mcsp->mb_head = NULL; 1854 mcsp->cb_status = 0; 1855 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1856 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1857 1858 nmcasts = 0; 1859 if (!sc->all_mcasts) { 1860 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1861 ifma = ifma->ifma_link.le_next) { 1862 if (ifma->ifma_addr->sa_family != AF_LINK) 1863 continue; 1864 if (nmcasts >= MAXMCADDR) { 1865 sc->all_mcasts = 1; 1866 nmcasts = 0; 1867 break; 1868 } 1869 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1870 (void *)(uintptr_t)(volatile void *) 1871 &sc->mcsp->mc_addr[nmcasts][0], 6); 1872 nmcasts++; 1873 } 1874 } 1875 mcsp->mc_cnt = nmcasts * 6; 1876 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1877 sc->tx_queued = 1; 1878 1879 /* 1880 * Wait until command unit is not active. This should never 1881 * be the case when nothing is queued, but make sure anyway. 1882 */ 1883 count = 100; 1884 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1885 FXP_SCB_CUS_ACTIVE && --count) 1886 DELAY(10); 1887 if (count == 0) { 1888 printf("fxp%d: command queue timeout\n", FXP_UNIT(sc)); 1889 return; 1890 } 1891 1892 /* 1893 * Start the multicast setup command. 1894 */ 1895 fxp_scb_wait(sc); 1896 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1897 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1898 1899 ifp->if_timer = 2; 1900 return; 1901} 1902