if_fxp.c revision 66008
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Modifications to support NetBSD and media selection: 6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 66008 2000-09-17 22:20:33Z dg $ 31 */ 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54 55#if defined(__NetBSD__) 56 57#include <sys/ioctl.h> 58#include <sys/errno.h> 59#include <sys/device.h> 60 61#include <net/if_dl.h> 62#include <net/if_ether.h> 63 64#include <netinet/if_inarp.h> 65 66#include <vm/vm.h> 67 68#include <machine/cpu.h> 69#include <machine/bus.h> 70#include <machine/intr.h> 71 72#include <dev/pci/if_fxpreg.h> 73#include <dev/pci/if_fxpvar.h> 74 75#include <dev/pci/pcivar.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcidevs.h> 78 79 80#else /* __FreeBSD__ */ 81 82#include <sys/sockio.h> 83#include <sys/bus.h> 84#include <machine/bus.h> 85#include <sys/rman.h> 86#include <machine/resource.h> 87#include <sys/proc.h> 88#include <machine/mutex.h> 89 90#include <net/ethernet.h> 91#include <net/if_arp.h> 92 93#include <vm/vm.h> /* for vtophys */ 94#include <vm/pmap.h> /* for vtophys */ 95#include <machine/clock.h> /* for DELAY */ 96 97#include <pci/pcivar.h> 98#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 99#include <pci/if_fxpreg.h> 100#include <pci/if_fxpvar.h> 101 102#endif /* __NetBSD__ */ 103 104#ifdef __alpha__ /* XXX */ 105/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 106#undef vtophys 107#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 108#endif /* __alpha__ */ 109 110/* 111 * NOTE! On the Alpha, we have an alignment constraint. The 112 * card DMAs the packet immediately following the RFA. However, 113 * the first thing in the packet is a 14-byte Ethernet header. 114 * This means that the packet is misaligned. To compensate, 115 * we actually offset the RFA 2 bytes into the cluster. This 116 * alignes the packet after the Ethernet header at a 32-bit 117 * boundary. HOWEVER! This means that the RFA is misaligned! 118 */ 119#define RFA_ALIGNMENT_FUDGE 2 120 121/* 122 * Inline function to copy a 16-bit aligned 32-bit quantity. 123 */ 124static __inline void fxp_lwcopy __P((volatile u_int32_t *, 125 volatile u_int32_t *)); 126static __inline void 127fxp_lwcopy(src, dst) 128 volatile u_int32_t *src, *dst; 129{ 130#ifdef __i386__ 131 *dst = *src; 132#else 133 volatile u_int16_t *a = (volatile u_int16_t *)src; 134 volatile u_int16_t *b = (volatile u_int16_t *)dst; 135 136 b[0] = a[0]; 137 b[1] = a[1]; 138#endif 139} 140 141/* 142 * Template for default configuration parameters. 143 * See struct fxp_cb_config for the bit definitions. 144 */ 145static u_char fxp_cb_config_template[] = { 146 0x0, 0x0, /* cb_status */ 147 0x80, 0x2, /* cb_command */ 148 0xff, 0xff, 0xff, 0xff, /* link_addr */ 149 0x16, /* 0 */ 150 0x8, /* 1 */ 151 0x0, /* 2 */ 152 0x0, /* 3 */ 153 0x0, /* 4 */ 154 0x80, /* 5 */ 155 0xb2, /* 6 */ 156 0x3, /* 7 */ 157 0x1, /* 8 */ 158 0x0, /* 9 */ 159 0x26, /* 10 */ 160 0x0, /* 11 */ 161 0x60, /* 12 */ 162 0x0, /* 13 */ 163 0xf2, /* 14 */ 164 0x48, /* 15 */ 165 0x0, /* 16 */ 166 0x40, /* 17 */ 167 0xf3, /* 18 */ 168 0x0, /* 19 */ 169 0x3f, /* 20 */ 170 0x5 /* 21 */ 171}; 172 173/* Supported media types. */ 174struct fxp_supported_media { 175 const int fsm_phy; /* PHY type */ 176 const int *fsm_media; /* the media array */ 177 const int fsm_nmedia; /* the number of supported media */ 178 const int fsm_defmedia; /* default media for this PHY */ 179}; 180 181static const int fxp_media_standard[] = { 182 IFM_ETHER|IFM_10_T, 183 IFM_ETHER|IFM_10_T|IFM_FDX, 184 IFM_ETHER|IFM_100_TX, 185 IFM_ETHER|IFM_100_TX|IFM_FDX, 186 IFM_ETHER|IFM_AUTO, 187}; 188#define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO) 189 190static const int fxp_media_default[] = { 191 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */ 192}; 193#define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL) 194 195static const struct fxp_supported_media fxp_media[] = { 196 { FXP_PHY_DP83840, fxp_media_standard, 197 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 198 FXP_MEDIA_STANDARD_DEFMEDIA }, 199 { FXP_PHY_DP83840A, fxp_media_standard, 200 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 201 FXP_MEDIA_STANDARD_DEFMEDIA }, 202 { FXP_PHY_82553A, fxp_media_standard, 203 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 204 FXP_MEDIA_STANDARD_DEFMEDIA }, 205 { FXP_PHY_82553C, fxp_media_standard, 206 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 207 FXP_MEDIA_STANDARD_DEFMEDIA }, 208 { FXP_PHY_82555, fxp_media_standard, 209 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 210 FXP_MEDIA_STANDARD_DEFMEDIA }, 211 { FXP_PHY_82555B, fxp_media_standard, 212 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 213 FXP_MEDIA_STANDARD_DEFMEDIA }, 214 { FXP_PHY_80C24, fxp_media_default, 215 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]), 216 FXP_MEDIA_DEFAULT_DEFMEDIA }, 217}; 218#define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0])) 219 220static int fxp_mediachange __P((struct ifnet *)); 221static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *)); 222static void fxp_set_media __P((struct fxp_softc *, int)); 223static __inline void fxp_scb_wait __P((struct fxp_softc *)); 224static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc)); 225static FXP_INTR_TYPE fxp_intr __P((void *)); 226static void fxp_start __P((struct ifnet *)); 227static int fxp_ioctl __P((struct ifnet *, 228 FXP_IOCTLCMD_TYPE, caddr_t)); 229static void fxp_init __P((void *)); 230static void fxp_stop __P((struct fxp_softc *)); 231static void fxp_watchdog __P((struct ifnet *)); 232static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *)); 233static int fxp_mdi_read __P((struct fxp_softc *, int, int)); 234static void fxp_mdi_write __P((struct fxp_softc *, int, int, int)); 235static void fxp_autosize_eeprom __P((struct fxp_softc *)); 236static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, 237 int, int)); 238static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *)); 239static void fxp_stats_update __P((void *)); 240static void fxp_mc_setup __P((struct fxp_softc *)); 241 242/* 243 * Set initial transmit threshold at 64 (512 bytes). This is 244 * increased by 64 (512 bytes) at a time, to maximum of 192 245 * (1536 bytes), if an underrun occurs. 246 */ 247static int tx_threshold = 64; 248 249/* 250 * Number of transmit control blocks. This determines the number 251 * of transmit buffers that can be chained in the CB list. 252 * This must be a power of two. 253 */ 254#define FXP_NTXCB 128 255 256/* 257 * Number of completed TX commands at which point an interrupt 258 * will be generated to garbage collect the attached buffers. 259 * Must be at least one less than FXP_NTXCB, and should be 260 * enough less so that the transmitter doesn't becomes idle 261 * during the buffer rundown (which would reduce performance). 262 */ 263#define FXP_CXINT_THRESH 120 264 265/* 266 * TxCB list index mask. This is used to do list wrap-around. 267 */ 268#define FXP_TXCB_MASK (FXP_NTXCB - 1) 269 270/* 271 * Number of receive frame area buffers. These are large so chose 272 * wisely. 273 */ 274#define FXP_NRFABUFS 64 275 276/* 277 * Maximum number of seconds that the receiver can be idle before we 278 * assume it's dead and attempt to reset it by reprogramming the 279 * multicast filter. This is part of a work-around for a bug in the 280 * NIC. See fxp_stats_update(). 281 */ 282#define FXP_MAX_RX_IDLE 15 283 284/* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288static __inline void 289fxp_scb_wait(sc) 290 struct fxp_softc *sc; 291{ 292 int i = 10000; 293 294 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 295 DELAY(2); 296 if (i == 0) 297 printf(FXP_FORMAT ": SCB timeout\n", FXP_ARGS(sc)); 298} 299 300static __inline void 301fxp_dma_wait(status, sc) 302 volatile u_int16_t *status; 303 struct fxp_softc *sc; 304{ 305 int i = 10000; 306 307 while (!(*status & FXP_CB_STATUS_C) && --i) 308 DELAY(2); 309 if (i == 0) 310 printf(FXP_FORMAT ": DMA timeout\n", FXP_ARGS(sc)); 311} 312 313/************************************************************* 314 * Operating system-specific autoconfiguration glue 315 *************************************************************/ 316 317#if defined(__NetBSD__) 318 319#ifdef __BROKEN_INDIRECT_CONFIG 320static int fxp_match __P((struct device *, void *, void *)); 321#else 322static int fxp_match __P((struct device *, struct cfdata *, void *)); 323#endif 324static void fxp_attach __P((struct device *, struct device *, void *)); 325 326static void fxp_shutdown __P((void *)); 327 328/* Compensate for lack of a generic ether_ioctl() */ 329static int fxp_ether_ioctl __P((struct ifnet *, 330 FXP_IOCTLCMD_TYPE, caddr_t)); 331#define ether_ioctl fxp_ether_ioctl 332 333struct cfattach fxp_ca = { 334 sizeof(struct fxp_softc), fxp_match, fxp_attach 335}; 336 337struct cfdriver fxp_cd = { 338 NULL, "fxp", DV_IFNET 339}; 340 341/* 342 * Check if a device is an 82557. 343 */ 344static int 345fxp_match(parent, match, aux) 346 struct device *parent; 347#ifdef __BROKEN_INDIRECT_CONFIG 348 void *match; 349#else 350 struct cfdata *match; 351#endif 352 void *aux; 353{ 354 struct pci_attach_args *pa = aux; 355 356 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 357 return (0); 358 359 switch (PCI_PRODUCT(pa->pa_id)) { 360 case PCI_PRODUCT_INTEL_82557: 361 return (1); 362 } 363 364 return (0); 365} 366 367static void 368fxp_attach(parent, self, aux) 369 struct device *parent, *self; 370 void *aux; 371{ 372 struct fxp_softc *sc = (struct fxp_softc *)self; 373 struct pci_attach_args *pa = aux; 374 pci_chipset_tag_t pc = pa->pa_pc; 375 pci_intr_handle_t ih; 376 const char *intrstr = NULL; 377 u_int8_t enaddr[6]; 378 struct ifnet *ifp; 379 380 /* 381 * Map control/status registers. 382 */ 383 if (pci_mapreg_map(pa, FXP_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 384 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 385 printf(": can't map registers\n"); 386 return; 387 } 388 printf(": Intel EtherExpress Pro 10/100B Ethernet\n"); 389 390 /* 391 * Allocate our interrupt. 392 */ 393 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 394 pa->pa_intrline, &ih)) { 395 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 396 return; 397 } 398 intrstr = pci_intr_string(pc, ih); 399 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 400 if (sc->sc_ih == NULL) { 401 printf("%s: couldn't establish interrupt", 402 sc->sc_dev.dv_xname); 403 if (intrstr != NULL) 404 printf(" at %s", intrstr); 405 printf("\n"); 406 return; 407 } 408 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 409 410 /* Do generic parts of attach. */ 411 if (fxp_attach_common(sc, enaddr)) { 412 /* Failed! */ 413 return; 414 } 415 416 printf("%s: Ethernet address %s%s\n", sc->sc_dev.dv_xname, 417 ether_sprintf(enaddr), sc->phy_10Mbps_only ? ", 10Mbps" : ""); 418 419 ifp = &sc->sc_ethercom.ec_if; 420 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 421 ifp->if_softc = sc; 422 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 423 ifp->if_ioctl = fxp_ioctl; 424 ifp->if_start = fxp_start; 425 ifp->if_watchdog = fxp_watchdog; 426 427 /* 428 * Attach the interface. 429 */ 430 if_attach(ifp); 431 /* 432 * Let the system queue as many packets as we have available 433 * TX descriptors. 434 */ 435 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 436 ether_ifattach(ifp, enaddr); 437 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 438 sizeof(struct ether_header)); 439 440 /* 441 * Add shutdown hook so that DMA is disabled prior to reboot. Not 442 * doing do could allow DMA to corrupt kernel memory during the 443 * reboot before the driver initializes. 444 */ 445 shutdownhook_establish(fxp_shutdown, sc); 446} 447 448/* 449 * Device shutdown routine. Called at system shutdown after sync. The 450 * main purpose of this routine is to shut off receiver DMA so that 451 * kernel memory doesn't get clobbered during warmboot. 452 */ 453static void 454fxp_shutdown(sc) 455 void *sc; 456{ 457 fxp_stop((struct fxp_softc *) sc); 458} 459 460static int 461fxp_ether_ioctl(ifp, cmd, data) 462 struct ifnet *ifp; 463 FXP_IOCTLCMD_TYPE cmd; 464 caddr_t data; 465{ 466 struct ifaddr *ifa = (struct ifaddr *) data; 467 struct fxp_softc *sc = ifp->if_softc; 468 469 switch (cmd) { 470 case SIOCSIFADDR: 471 ifp->if_flags |= IFF_UP; 472 473 switch (ifa->ifa_addr->sa_family) { 474#ifdef INET 475 case AF_INET: 476 fxp_init(sc); 477 arp_ifinit(ifp, ifa); 478 break; 479#endif 480#ifdef NS 481 case AF_NS: 482 { 483 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 484 485 if (ns_nullhost(*ina)) 486 ina->x_host = *(union ns_host *) 487 LLADDR(ifp->if_sadl); 488 else 489 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 490 ifp->if_addrlen); 491 /* Set new address. */ 492 fxp_init(sc); 493 break; 494 } 495#endif 496 default: 497 fxp_init(sc); 498 break; 499 } 500 break; 501 502 default: 503 return (EINVAL); 504 } 505 506 return (0); 507} 508 509#else /* __FreeBSD__ */ 510 511/* 512 * Return identification string if this is device is ours. 513 */ 514static int 515fxp_probe(device_t dev) 516{ 517 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 518 switch (pci_get_device(dev)) { 519 520 case FXP_DEVICEID_i82557: 521 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet"); 522 return 0; 523 case FXP_DEVICEID_i82559: 524 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet"); 525 return 0; 526 case FXP_DEVICEID_i82559ER: 527 device_set_desc(dev, "Intel Embedded 10/100 Ethernet"); 528 return 0; 529 default: 530 break; 531 } 532 } 533 534 return ENXIO; 535} 536 537static int 538fxp_attach(device_t dev) 539{ 540 int error = 0; 541 struct fxp_softc *sc = device_get_softc(dev); 542 struct ifnet *ifp; 543 FXP_SPLVAR(s) 544 u_long val; 545 int rid; 546 547#if !defined(__NetBSD__) 548 mtx_init(&sc->sc_mtx, "fxp", MTX_DEF); 549#endif 550 callout_handle_init(&sc->stat_ch); 551 552 FXP_LOCK(sc, s); 553 554 /* 555 * Enable bus mastering. 556 */ 557 val = pci_read_config(dev, PCIR_COMMAND, 2); 558 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 559 pci_write_config(dev, PCIR_COMMAND, val, 2); 560 561 /* 562 * Map control/status registers. 563 */ 564 rid = FXP_PCI_MMBA; 565 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 566 0, ~0, 1, RF_ACTIVE); 567 if (!sc->mem) { 568 device_printf(dev, "could not map memory\n"); 569 error = ENXIO; 570 goto fail; 571 } 572 573 sc->sc_st = rman_get_bustag(sc->mem); 574 sc->sc_sh = rman_get_bushandle(sc->mem); 575 576 /* 577 * Allocate our interrupt. 578 */ 579 rid = 0; 580 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 581 RF_SHAREABLE | RF_ACTIVE); 582 if (sc->irq == NULL) { 583 device_printf(dev, "could not map interrupt\n"); 584 error = ENXIO; 585 goto fail; 586 } 587 588 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 589 fxp_intr, sc, &sc->ih); 590 if (error) { 591 device_printf(dev, "could not setup irq\n"); 592 goto fail; 593 } 594 595 /* Do generic parts of attach. */ 596 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) { 597 /* Failed! */ 598 bus_teardown_intr(dev, sc->irq, sc->ih); 599 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 600 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 601 error = ENXIO; 602 goto fail; 603 } 604 605 device_printf(dev, "Ethernet address %6D%s\n", 606 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : ""); 607 608 ifp = &sc->arpcom.ac_if; 609 ifp->if_unit = device_get_unit(dev); 610 ifp->if_name = "fxp"; 611 ifp->if_output = ether_output; 612 ifp->if_baudrate = 100000000; 613 ifp->if_init = fxp_init; 614 ifp->if_softc = sc; 615 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 616 ifp->if_ioctl = fxp_ioctl; 617 ifp->if_start = fxp_start; 618 ifp->if_watchdog = fxp_watchdog; 619 620 /* 621 * Attach the interface. 622 */ 623 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 624 /* 625 * Let the system queue as many packets as we have available 626 * TX descriptors. 627 */ 628 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 629 630 FXP_UNLOCK(sc, s); 631 return 0; 632 633 fail: 634 FXP_UNLOCK(sc, s); 635 mtx_destroy(&sc->sc_mtx); 636 return error; 637} 638 639/* 640 * Detach interface. 641 */ 642static int 643fxp_detach(device_t dev) 644{ 645 struct fxp_softc *sc = device_get_softc(dev); 646 FXP_SPLVAR(s) 647 648 FXP_LOCK(sc, s); 649 650 /* 651 * Close down routes etc. 652 */ 653 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 654 655 /* 656 * Stop DMA and drop transmit queue. 657 */ 658 fxp_stop(sc); 659 660 /* 661 * Deallocate resources. 662 */ 663 bus_teardown_intr(dev, sc->irq, sc->ih); 664 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 665 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 666 667 /* 668 * Free all the receive buffers. 669 */ 670 if (sc->rfa_headm != NULL) 671 m_freem(sc->rfa_headm); 672 673 /* 674 * Free all media structures. 675 */ 676 ifmedia_removeall(&sc->sc_media); 677 678 /* 679 * Free anciliary structures. 680 */ 681 free(sc->cbl_base, M_DEVBUF); 682 free(sc->fxp_stats, M_DEVBUF); 683 free(sc->mcsp, M_DEVBUF); 684 685 FXP_UNLOCK(sc, s); 686 687 return 0; 688} 689 690/* 691 * Device shutdown routine. Called at system shutdown after sync. The 692 * main purpose of this routine is to shut off receiver DMA so that 693 * kernel memory doesn't get clobbered during warmboot. 694 */ 695static int 696fxp_shutdown(device_t dev) 697{ 698 /* 699 * Make sure that DMA is disabled prior to reboot. Not doing 700 * do could allow DMA to corrupt kernel memory during the 701 * reboot before the driver initializes. 702 */ 703 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 704 return 0; 705} 706 707/* 708 * Device suspend routine. Stop the interface and save some PCI 709 * settings in case the BIOS doesn't restore them properly on 710 * resume. 711 */ 712static int 713fxp_suspend(device_t dev) 714{ 715 struct fxp_softc *sc = device_get_softc(dev); 716 int i; 717 FXP_SPLVAR(s) 718 719 FXP_LOCK(sc, s); 720 721 fxp_stop(sc); 722 723 for (i=0; i<5; i++) 724 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 725 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 726 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 727 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 728 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 729 730 sc->suspended = 1; 731 732 FXP_UNLOCK(sc, s); 733 734 return 0; 735} 736 737/* 738 * Device resume routine. Restore some PCI settings in case the BIOS 739 * doesn't, re-enable busmastering, and restart the interface if 740 * appropriate. 741 */ 742static int 743fxp_resume(device_t dev) 744{ 745 struct fxp_softc *sc = device_get_softc(dev); 746 struct ifnet *ifp = &sc->sc_if; 747 u_int16_t pci_command; 748 int i; 749 FXP_SPLVAR(s) 750 751 FXP_LOCK(sc, s); 752 753 /* better way to do this? */ 754 for (i=0; i<5; i++) 755 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 756 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 757 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 758 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 759 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 760 761 /* reenable busmastering */ 762 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 763 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 764 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 765 766 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 767 DELAY(10); 768 769 /* reinitialize interface if necessary */ 770 if (ifp->if_flags & IFF_UP) 771 fxp_init(sc); 772 773 sc->suspended = 0; 774 775 FXP_UNLOCK(sc, s); 776 777 return 0; 778} 779 780static device_method_t fxp_methods[] = { 781 /* Device interface */ 782 DEVMETHOD(device_probe, fxp_probe), 783 DEVMETHOD(device_attach, fxp_attach), 784 DEVMETHOD(device_detach, fxp_detach), 785 DEVMETHOD(device_shutdown, fxp_shutdown), 786 DEVMETHOD(device_suspend, fxp_suspend), 787 DEVMETHOD(device_resume, fxp_resume), 788 789 { 0, 0 } 790}; 791 792static driver_t fxp_driver = { 793 "fxp", 794 fxp_methods, 795 sizeof(struct fxp_softc), 796}; 797 798static devclass_t fxp_devclass; 799 800DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 801 802#endif /* __NetBSD__ */ 803 804/************************************************************* 805 * End of operating system-specific autoconfiguration glue 806 *************************************************************/ 807 808/* 809 * Do generic parts of attach. 810 */ 811static int 812fxp_attach_common(sc, enaddr) 813 struct fxp_softc *sc; 814 u_int8_t *enaddr; 815{ 816 u_int16_t data; 817 int i, nmedia, defmedia; 818 const int *media; 819 820 /* 821 * Reset to a stable state. 822 */ 823 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 824 DELAY(10); 825 826 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 827 M_DEVBUF, M_NOWAIT); 828 if (sc->cbl_base == NULL) 829 goto fail; 830 bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 831 832 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT); 833 if (sc->fxp_stats == NULL) 834 goto fail; 835 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 836 837 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 838 if (sc->mcsp == NULL) 839 goto fail; 840 841 /* 842 * Pre-allocate our receive buffers. 843 */ 844 for (i = 0; i < FXP_NRFABUFS; i++) { 845 if (fxp_add_rfabuf(sc, NULL) != 0) { 846 goto fail; 847 } 848 } 849 850 /* 851 * Find out how large of an SEEPROM we have. 852 */ 853 fxp_autosize_eeprom(sc); 854 855 /* 856 * Get info about the primary PHY 857 */ 858 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1); 859 sc->phy_primary_addr = data & 0xff; 860 sc->phy_primary_device = (data >> 8) & 0x3f; 861 sc->phy_10Mbps_only = data >> 15; 862 863 /* 864 * Read MAC address. 865 */ 866 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3); 867 868 /* 869 * Initialize the media structures. 870 */ 871 872 media = fxp_media_default; 873 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]); 874 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA; 875 876 for (i = 0; i < NFXPMEDIA; i++) { 877 if (sc->phy_primary_device == fxp_media[i].fsm_phy) { 878 media = fxp_media[i].fsm_media; 879 nmedia = fxp_media[i].fsm_nmedia; 880 defmedia = fxp_media[i].fsm_defmedia; 881 } 882 } 883 884 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus); 885 for (i = 0; i < nmedia; i++) { 886 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only) 887 continue; 888 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 889 } 890 ifmedia_set(&sc->sc_media, defmedia); 891 892 return (0); 893 894 fail: 895 printf(FXP_FORMAT ": Failed to malloc memory\n", FXP_ARGS(sc)); 896 if (sc->cbl_base) 897 free(sc->cbl_base, M_DEVBUF); 898 if (sc->fxp_stats) 899 free(sc->fxp_stats, M_DEVBUF); 900 if (sc->mcsp) 901 free(sc->mcsp, M_DEVBUF); 902 /* frees entire chain */ 903 if (sc->rfa_headm) 904 m_freem(sc->rfa_headm); 905 906 return (ENOMEM); 907} 908 909/* 910 * From NetBSD: 911 * 912 * Figure out EEPROM size. 913 * 914 * 559's can have either 64-word or 256-word EEPROMs, the 558 915 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 916 * talks about the existance of 16 to 256 word EEPROMs. 917 * 918 * The only known sizes are 64 and 256, where the 256 version is used 919 * by CardBus cards to store CIS information. 920 * 921 * The address is shifted in msb-to-lsb, and after the last 922 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 923 * after which follows the actual data. We try to detect this zero, by 924 * probing the data-out bit in the EEPROM control register just after 925 * having shifted in a bit. If the bit is zero, we assume we've 926 * shifted enough address bits. The data-out should be tri-state, 927 * before this, which should translate to a logical one. 928 * 929 * Other ways to do this would be to try to read a register with known 930 * contents with a varying number of address bits, but no such 931 * register seem to be available. The high bits of register 10 are 01 932 * on the 558 and 559, but apparently not on the 557. 933 * 934 * The Linux driver computes a checksum on the EEPROM data, but the 935 * value of this checksum is not very well documented. 936 */ 937static void 938fxp_autosize_eeprom(sc) 939 struct fxp_softc *sc; 940{ 941 u_int16_t reg; 942 int x; 943 944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 945 /* 946 * Shift in read opcode. 947 */ 948 for (x = 3; x > 0; x--) { 949 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 950 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 951 } else { 952 reg = FXP_EEPROM_EECS; 953 } 954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 956 reg | FXP_EEPROM_EESK); 957 DELAY(1); 958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 959 DELAY(1); 960 } 961 /* 962 * Shift in address. 963 * Wait for the dummy zero following a correct address shift. 964 */ 965 for (x = 1; x <= 8; x++) { 966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 967 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 968 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 969 DELAY(1); 970 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0) 971 break; 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 973 DELAY(1); 974 } 975 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 976 DELAY(1); 977 sc->eeprom_size = x; 978} 979/* 980 * Read from the serial EEPROM. Basically, you manually shift in 981 * the read opcode (one bit at a time) and then shift in the address, 982 * and then you shift out the data (all of this one bit at a time). 983 * The word size is 16 bits, so you have to provide the address for 984 * every 16 bits of data. 985 */ 986static void 987fxp_read_eeprom(sc, data, offset, words) 988 struct fxp_softc *sc; 989 u_short *data; 990 int offset; 991 int words; 992{ 993 u_int16_t reg; 994 int i, x; 995 996 for (i = 0; i < words; i++) { 997 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 998 /* 999 * Shift in read opcode. 1000 */ 1001 for (x = 3; x > 0; x--) { 1002 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 1003 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1004 } else { 1005 reg = FXP_EEPROM_EECS; 1006 } 1007 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1008 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 1009 reg | FXP_EEPROM_EESK); 1010 DELAY(1); 1011 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1012 DELAY(1); 1013 } 1014 /* 1015 * Shift in address. 1016 */ 1017 for (x = sc->eeprom_size; x > 0; x--) { 1018 if ((i + offset) & (1 << (x - 1))) { 1019 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1020 } else { 1021 reg = FXP_EEPROM_EECS; 1022 } 1023 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1024 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 1025 reg | FXP_EEPROM_EESK); 1026 DELAY(1); 1027 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1028 DELAY(1); 1029 } 1030 reg = FXP_EEPROM_EECS; 1031 data[i] = 0; 1032 /* 1033 * Shift out data. 1034 */ 1035 for (x = 16; x > 0; x--) { 1036 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 1037 reg | FXP_EEPROM_EESK); 1038 DELAY(1); 1039 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 1040 FXP_EEPROM_EEDO) 1041 data[i] |= (1 << (x - 1)); 1042 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1043 DELAY(1); 1044 } 1045 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1046 DELAY(1); 1047 } 1048} 1049 1050/* 1051 * Start packet transmission on the interface. 1052 */ 1053static void 1054fxp_start(ifp) 1055 struct ifnet *ifp; 1056{ 1057 struct fxp_softc *sc = ifp->if_softc; 1058 struct fxp_cb_tx *txp; 1059 1060#if !defined(__NetBSD__) 1061 FXP_LOCK(sc, s); 1062#endif 1063 /* 1064 * See if we need to suspend xmit until the multicast filter 1065 * has been reprogrammed (which can only be done at the head 1066 * of the command chain). 1067 */ 1068 if (sc->need_mcsetup) { 1069 FXP_UNLOCK(sc, s); 1070 return; 1071 } 1072 1073 txp = NULL; 1074 1075 /* 1076 * We're finished if there is nothing more to add to the list or if 1077 * we're all filled up with buffers to transmit. 1078 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1079 * a NOP command when needed. 1080 */ 1081 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1082 struct mbuf *m, *mb_head; 1083 int segment; 1084 1085 /* 1086 * Grab a packet to transmit. 1087 */ 1088 IF_DEQUEUE(&ifp->if_snd, mb_head); 1089 1090 /* 1091 * Get pointer to next available tx desc. 1092 */ 1093 txp = sc->cbl_last->next; 1094 1095 /* 1096 * Go through each of the mbufs in the chain and initialize 1097 * the transmit buffer descriptors with the physical address 1098 * and size of the mbuf. 1099 */ 1100tbdinit: 1101 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1102 if (m->m_len != 0) { 1103 if (segment == FXP_NTXSEG) 1104 break; 1105 txp->tbd[segment].tb_addr = 1106 vtophys(mtod(m, vm_offset_t)); 1107 txp->tbd[segment].tb_size = m->m_len; 1108 segment++; 1109 } 1110 } 1111 if (m != NULL) { 1112 struct mbuf *mn; 1113 1114 /* 1115 * We ran out of segments. We have to recopy this mbuf 1116 * chain first. Bail out if we can't get the new buffers. 1117 */ 1118 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1119 if (mn == NULL) { 1120 m_freem(mb_head); 1121 break; 1122 } 1123 if (mb_head->m_pkthdr.len > MHLEN) { 1124 MCLGET(mn, M_DONTWAIT); 1125 if ((mn->m_flags & M_EXT) == 0) { 1126 m_freem(mn); 1127 m_freem(mb_head); 1128 break; 1129 } 1130 } 1131 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1132 mtod(mn, caddr_t)); 1133 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1134 m_freem(mb_head); 1135 mb_head = mn; 1136 goto tbdinit; 1137 } 1138 1139 txp->tbd_number = segment; 1140 txp->mb_head = mb_head; 1141 txp->cb_status = 0; 1142 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1143 txp->cb_command = 1144 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 1145 } else { 1146 txp->cb_command = 1147 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1148 /* 1149 * Set a 5 second timer just in case we don't hear from the 1150 * card again. 1151 */ 1152 ifp->if_timer = 5; 1153 } 1154 txp->tx_threshold = tx_threshold; 1155 1156 /* 1157 * Advance the end of list forward. 1158 */ 1159 1160#ifdef __alpha__ 1161 /* 1162 * On platforms which can't access memory in 16-bit 1163 * granularities, we must prevent the card from DMA'ing 1164 * up the status while we update the command field. 1165 * This could cause us to overwrite the completion status. 1166 */ 1167 atomic_clear_short(&sc->cbl_last->cb_command, 1168 FXP_CB_COMMAND_S); 1169#else 1170 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1171#endif /*__alpha__*/ 1172 sc->cbl_last = txp; 1173 1174 /* 1175 * Advance the beginning of the list forward if there are 1176 * no other packets queued (when nothing is queued, cbl_first 1177 * sits on the last TxCB that was sent out). 1178 */ 1179 if (sc->tx_queued == 0) 1180 sc->cbl_first = txp; 1181 1182 sc->tx_queued++; 1183 1184 /* 1185 * Pass packet to bpf if there is a listener. 1186 */ 1187 if (ifp->if_bpf) 1188 bpf_mtap(FXP_BPFTAP_ARG(ifp), mb_head); 1189 } 1190 1191 /* 1192 * We're finished. If we added to the list, issue a RESUME to get DMA 1193 * going again if suspended. 1194 */ 1195 if (txp != NULL) { 1196 fxp_scb_wait(sc); 1197 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1198 } 1199#if !defined(__NetBSD__) 1200 FXP_UNLOCK(sc, s); 1201#endif 1202} 1203 1204/* 1205 * Process interface interrupts. 1206 */ 1207static FXP_INTR_TYPE 1208fxp_intr(arg) 1209 void *arg; 1210{ 1211 struct fxp_softc *sc = arg; 1212 struct ifnet *ifp = &sc->sc_if; 1213 u_int8_t statack; 1214#if defined(__NetBSD__) 1215 int claimed = 0; 1216#else 1217 1218 FXP_LOCK(sc, s); 1219#endif 1220 1221 while (!sc->suspended && (statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1222#if defined(__NetBSD__) 1223 claimed = 1; 1224#endif 1225 /* 1226 * First ACK all the interrupts in this pass. 1227 */ 1228 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1229 1230 /* 1231 * Free any finished transmit mbuf chains. 1232 * 1233 * Handle the CNA event likt a CXTNO event. It used to 1234 * be that this event (control unit not ready) was not 1235 * encountered, but it is now with the SMPng modifications. 1236 * The exact sequence of events that occur when the interface 1237 * is brought up are different now, and if this event 1238 * goes unhandled, the configuration/rxfilter setup sequence 1239 * can stall for several seconds. The result is that no 1240 * packets go out onto the wire for about 5 to 10 seconds 1241 * after the interface is ifconfig'ed for the first time. 1242 */ 1243 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1244 struct fxp_cb_tx *txp; 1245 1246 for (txp = sc->cbl_first; sc->tx_queued && 1247 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1248 txp = txp->next) { 1249 if (txp->mb_head != NULL) { 1250 m_freem(txp->mb_head); 1251 txp->mb_head = NULL; 1252 } 1253 sc->tx_queued--; 1254 } 1255 sc->cbl_first = txp; 1256 ifp->if_timer = 0; 1257 if (sc->tx_queued == 0) { 1258 if (sc->need_mcsetup) 1259 fxp_mc_setup(sc); 1260 } 1261 /* 1262 * Try to start more packets transmitting. 1263 */ 1264 if (ifp->if_snd.ifq_head != NULL) 1265 fxp_start(ifp); 1266 } 1267 /* 1268 * Process receiver interrupts. If a no-resource (RNR) 1269 * condition exists, get whatever packets we can and 1270 * re-start the receiver. 1271 */ 1272 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1273 struct mbuf *m; 1274 struct fxp_rfa *rfa; 1275rcvloop: 1276 m = sc->rfa_headm; 1277 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1278 RFA_ALIGNMENT_FUDGE); 1279 1280 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1281 /* 1282 * Remove first packet from the chain. 1283 */ 1284 sc->rfa_headm = m->m_next; 1285 m->m_next = NULL; 1286 1287 /* 1288 * Add a new buffer to the receive chain. 1289 * If this fails, the old buffer is recycled 1290 * instead. 1291 */ 1292 if (fxp_add_rfabuf(sc, m) == 0) { 1293 struct ether_header *eh; 1294 int total_len; 1295 1296 total_len = rfa->actual_size & 1297 (MCLBYTES - 1); 1298 if (total_len < 1299 sizeof(struct ether_header)) { 1300 m_freem(m); 1301 goto rcvloop; 1302 } 1303 m->m_pkthdr.rcvif = ifp; 1304 m->m_pkthdr.len = m->m_len = total_len; 1305 eh = mtod(m, struct ether_header *); 1306 m->m_data += 1307 sizeof(struct ether_header); 1308 m->m_len -= 1309 sizeof(struct ether_header); 1310 m->m_pkthdr.len = m->m_len; 1311 ether_input(ifp, eh, m); 1312 } 1313 goto rcvloop; 1314 } 1315 if (statack & FXP_SCB_STATACK_RNR) { 1316 fxp_scb_wait(sc); 1317 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1318 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1319 RFA_ALIGNMENT_FUDGE); 1320 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1321 FXP_SCB_COMMAND_RU_START); 1322 } 1323 } 1324 } 1325#if defined(__NetBSD__) 1326 return (claimed); 1327#else 1328 FXP_UNLOCK(sc, s); 1329#endif 1330} 1331 1332/* 1333 * Update packet in/out/collision statistics. The i82557 doesn't 1334 * allow you to access these counters without doing a fairly 1335 * expensive DMA to get _all_ of the statistics it maintains, so 1336 * we do this operation here only once per second. The statistics 1337 * counters in the kernel are updated from the previous dump-stats 1338 * DMA and then a new dump-stats DMA is started. The on-chip 1339 * counters are zeroed when the DMA completes. If we can't start 1340 * the DMA immediately, we don't wait - we just prepare to read 1341 * them again next time. 1342 */ 1343static void 1344fxp_stats_update(arg) 1345 void *arg; 1346{ 1347 struct fxp_softc *sc = arg; 1348 struct ifnet *ifp = &sc->sc_if; 1349 struct fxp_stats *sp = sc->fxp_stats; 1350 struct fxp_cb_tx *txp; 1351 FXP_SPLVAR(s) 1352 1353 ifp->if_opackets += sp->tx_good; 1354 ifp->if_collisions += sp->tx_total_collisions; 1355 if (sp->rx_good) { 1356 ifp->if_ipackets += sp->rx_good; 1357 sc->rx_idle_secs = 0; 1358 } else { 1359 /* 1360 * Receiver's been idle for another second. 1361 */ 1362 sc->rx_idle_secs++; 1363 } 1364 ifp->if_ierrors += 1365 sp->rx_crc_errors + 1366 sp->rx_alignment_errors + 1367 sp->rx_rnr_errors + 1368 sp->rx_overrun_errors; 1369 /* 1370 * If any transmit underruns occured, bump up the transmit 1371 * threshold by another 512 bytes (64 * 8). 1372 */ 1373 if (sp->tx_underruns) { 1374 ifp->if_oerrors += sp->tx_underruns; 1375 if (tx_threshold < 192) 1376 tx_threshold += 64; 1377 } 1378 FXP_LOCK(sc, s); 1379 /* 1380 * Release any xmit buffers that have completed DMA. This isn't 1381 * strictly necessary to do here, but it's advantagous for mbufs 1382 * with external storage to be released in a timely manner rather 1383 * than being defered for a potentially long time. This limits 1384 * the delay to a maximum of one second. 1385 */ 1386 for (txp = sc->cbl_first; sc->tx_queued && 1387 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1388 txp = txp->next) { 1389 if (txp->mb_head != NULL) { 1390 m_freem(txp->mb_head); 1391 txp->mb_head = NULL; 1392 } 1393 sc->tx_queued--; 1394 } 1395 sc->cbl_first = txp; 1396 /* 1397 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1398 * then assume the receiver has locked up and attempt to clear 1399 * the condition by reprogramming the multicast filter. This is 1400 * a work-around for a bug in the 82557 where the receiver locks 1401 * up if it gets certain types of garbage in the syncronization 1402 * bits prior to the packet header. This bug is supposed to only 1403 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1404 * mode as well (perhaps due to a 10/100 speed transition). 1405 */ 1406 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1407 sc->rx_idle_secs = 0; 1408 fxp_mc_setup(sc); 1409 } 1410 /* 1411 * If there is no pending command, start another stats 1412 * dump. Otherwise punt for now. 1413 */ 1414 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1415 /* 1416 * Start another stats dump. 1417 */ 1418 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1419 FXP_SCB_COMMAND_CU_DUMPRESET); 1420 } else { 1421 /* 1422 * A previous command is still waiting to be accepted. 1423 * Just zero our copy of the stats and wait for the 1424 * next timer event to update them. 1425 */ 1426 sp->tx_good = 0; 1427 sp->tx_underruns = 0; 1428 sp->tx_total_collisions = 0; 1429 1430 sp->rx_good = 0; 1431 sp->rx_crc_errors = 0; 1432 sp->rx_alignment_errors = 0; 1433 sp->rx_rnr_errors = 0; 1434 sp->rx_overrun_errors = 0; 1435 } 1436 FXP_UNLOCK(sc, s); 1437 /* 1438 * Schedule another timeout one second from now. 1439 */ 1440 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1441} 1442 1443/* 1444 * Stop the interface. Cancels the statistics updater and resets 1445 * the interface. 1446 */ 1447static void 1448fxp_stop(sc) 1449 struct fxp_softc *sc; 1450{ 1451 struct ifnet *ifp = &sc->sc_if; 1452 struct fxp_cb_tx *txp; 1453 int i; 1454 1455#if !defined(__NetBSD__) 1456 FXP_LOCK(sc, s); 1457#endif 1458 1459 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1460 ifp->if_timer = 0; 1461 1462 /* 1463 * Cancel stats updater. 1464 */ 1465 untimeout(fxp_stats_update, sc, sc->stat_ch); 1466 1467 /* 1468 * Issue software reset 1469 */ 1470 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1471 DELAY(10); 1472 1473 /* 1474 * Release any xmit buffers. 1475 */ 1476 txp = sc->cbl_base; 1477 if (txp != NULL) { 1478 for (i = 0; i < FXP_NTXCB; i++) { 1479 if (txp[i].mb_head != NULL) { 1480 m_freem(txp[i].mb_head); 1481 txp[i].mb_head = NULL; 1482 } 1483 } 1484 } 1485 sc->tx_queued = 0; 1486 1487 /* 1488 * Free all the receive buffers then reallocate/reinitialize 1489 */ 1490 if (sc->rfa_headm != NULL) 1491 m_freem(sc->rfa_headm); 1492 sc->rfa_headm = NULL; 1493 sc->rfa_tailm = NULL; 1494 for (i = 0; i < FXP_NRFABUFS; i++) { 1495 if (fxp_add_rfabuf(sc, NULL) != 0) { 1496 /* 1497 * This "can't happen" - we're at splimp() 1498 * and we just freed all the buffers we need 1499 * above. 1500 */ 1501 panic("fxp_stop: no buffers!"); 1502 } 1503 } 1504 1505#if !defined(__NetBSD__) 1506 FXP_UNLOCK(sc, s); 1507#endif 1508} 1509 1510/* 1511 * Watchdog/transmission transmit timeout handler. Called when a 1512 * transmission is started on the interface, but no interrupt is 1513 * received before the timeout. This usually indicates that the 1514 * card has wedged for some reason. 1515 */ 1516static void 1517fxp_watchdog(ifp) 1518 struct ifnet *ifp; 1519{ 1520 struct fxp_softc *sc = ifp->if_softc; 1521 1522 printf(FXP_FORMAT ": device timeout\n", FXP_ARGS(sc)); 1523 ifp->if_oerrors++; 1524 1525 fxp_init(sc); 1526} 1527 1528static void 1529fxp_init(xsc) 1530 void *xsc; 1531{ 1532 struct fxp_softc *sc = xsc; 1533 struct ifnet *ifp = &sc->sc_if; 1534 struct fxp_cb_config *cbp; 1535 struct fxp_cb_ias *cb_ias; 1536 struct fxp_cb_tx *txp; 1537 int i, prm; 1538 FXP_SPLVAR(s) 1539 1540 FXP_LOCK(sc, s); 1541 /* 1542 * Cancel any pending I/O 1543 */ 1544 fxp_stop(sc); 1545 1546 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1547 1548 /* 1549 * Initialize base of CBL and RFA memory. Loading with zero 1550 * sets it up for regular linear addressing. 1551 */ 1552 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1553 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1554 1555 fxp_scb_wait(sc); 1556 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1557 1558 /* 1559 * Initialize base of dump-stats buffer. 1560 */ 1561 fxp_scb_wait(sc); 1562 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1563 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1564 1565 /* 1566 * We temporarily use memory that contains the TxCB list to 1567 * construct the config CB. The TxCB list memory is rebuilt 1568 * later. 1569 */ 1570 cbp = (struct fxp_cb_config *) sc->cbl_base; 1571 1572 /* 1573 * This bcopy is kind of disgusting, but there are a bunch of must be 1574 * zero and must be one bits in this structure and this is the easiest 1575 * way to initialize them all to proper values. 1576 */ 1577 bcopy(fxp_cb_config_template, 1578 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1579 sizeof(fxp_cb_config_template)); 1580 1581 cbp->cb_status = 0; 1582 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1583 cbp->link_addr = -1; /* (no) next command */ 1584 cbp->byte_count = 22; /* (22) bytes to config */ 1585 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1586 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1587 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1588 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1589 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1590 cbp->dma_bce = 0; /* (disable) dma max counters */ 1591 cbp->late_scb = 0; /* (don't) defer SCB update */ 1592 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1593 cbp->ci_int = 1; /* interrupt on CU idle */ 1594 cbp->save_bf = prm; /* save bad frames */ 1595 cbp->disc_short_rx = !prm; /* discard short packets */ 1596 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1597 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1598 cbp->nsai = 1; /* (don't) disable source addr insert */ 1599 cbp->preamble_length = 2; /* (7 byte) preamble */ 1600 cbp->loopback = 0; /* (don't) loopback */ 1601 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1602 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1603 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1604 cbp->promiscuous = prm; /* promiscuous mode */ 1605 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1606 cbp->crscdt = 0; /* (CRS only) */ 1607 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1608 cbp->padding = 1; /* (do) pad short tx packets */ 1609 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1610 cbp->force_fdx = 0; /* (don't) force full duplex */ 1611 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1612 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1613 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */ 1614 1615 /* 1616 * Start the config command/DMA. 1617 */ 1618 fxp_scb_wait(sc); 1619 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1620 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1621 /* ...and wait for it to complete. */ 1622 fxp_dma_wait(&cbp->cb_status, sc); 1623 1624 /* 1625 * Now initialize the station address. Temporarily use the TxCB 1626 * memory area like we did above for the config CB. 1627 */ 1628 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1629 cb_ias->cb_status = 0; 1630 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1631 cb_ias->link_addr = -1; 1632#if defined(__NetBSD__) 1633 bcopy(LLADDR(ifp->if_sadl), (void *)cb_ias->macaddr, 6); 1634#else 1635 bcopy(sc->arpcom.ac_enaddr, 1636 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1637 sizeof(sc->arpcom.ac_enaddr)); 1638#endif /* __NetBSD__ */ 1639 1640 /* 1641 * Start the IAS (Individual Address Setup) command/DMA. 1642 */ 1643 fxp_scb_wait(sc); 1644 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1645 /* ...and wait for it to complete. */ 1646 fxp_dma_wait(&cb_ias->cb_status, sc); 1647 1648 /* 1649 * Initialize transmit control block (TxCB) list. 1650 */ 1651 1652 txp = sc->cbl_base; 1653 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1654 for (i = 0; i < FXP_NTXCB; i++) { 1655 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1656 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1657 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1658 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1659 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1660 } 1661 /* 1662 * Set the suspend flag on the first TxCB and start the control 1663 * unit. It will execute the NOP and then suspend. 1664 */ 1665 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1666 sc->cbl_first = sc->cbl_last = txp; 1667 sc->tx_queued = 1; 1668 1669 fxp_scb_wait(sc); 1670 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1671 1672 /* 1673 * Initialize receiver buffer area - RFA. 1674 */ 1675 fxp_scb_wait(sc); 1676 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1677 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1678 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1679 1680 /* 1681 * Set current media. 1682 */ 1683 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 1684 1685 ifp->if_flags |= IFF_RUNNING; 1686 ifp->if_flags &= ~IFF_OACTIVE; 1687 FXP_UNLOCK(sc, s); 1688 1689 /* 1690 * Start stats updater. 1691 */ 1692 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1693} 1694 1695static void 1696fxp_set_media(sc, media) 1697 struct fxp_softc *sc; 1698 int media; 1699{ 1700 1701 switch (sc->phy_primary_device) { 1702 case FXP_PHY_DP83840: 1703 case FXP_PHY_DP83840A: 1704 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR, 1705 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) | 1706 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */ 1707 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */ 1708 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */ 1709 /* fall through */ 1710 case FXP_PHY_82553A: 1711 case FXP_PHY_82553C: /* untested */ 1712 case FXP_PHY_82555: 1713 case FXP_PHY_82555B: 1714 if (IFM_SUBTYPE(media) != IFM_AUTO) { 1715 int flags; 1716 1717 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ? 1718 FXP_PHY_BMCR_SPEED_100M : 0; 1719 flags |= (media & IFM_FDX) ? 1720 FXP_PHY_BMCR_FULLDUPLEX : 0; 1721 fxp_mdi_write(sc, sc->phy_primary_addr, 1722 FXP_PHY_BMCR, 1723 (fxp_mdi_read(sc, sc->phy_primary_addr, 1724 FXP_PHY_BMCR) & 1725 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M | 1726 FXP_PHY_BMCR_FULLDUPLEX)) | flags); 1727 } else { 1728 fxp_mdi_write(sc, sc->phy_primary_addr, 1729 FXP_PHY_BMCR, 1730 (fxp_mdi_read(sc, sc->phy_primary_addr, 1731 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN)); 1732 } 1733 break; 1734 /* 1735 * The Seeq 80c24 doesn't have a PHY programming interface, so do 1736 * nothing. 1737 */ 1738 case FXP_PHY_80C24: 1739 break; 1740 default: 1741 printf(FXP_FORMAT 1742 ": warning: unsupported PHY, type = %d, addr = %d\n", 1743 FXP_ARGS(sc), sc->phy_primary_device, 1744 sc->phy_primary_addr); 1745 } 1746} 1747 1748/* 1749 * Change media according to request. 1750 */ 1751int 1752fxp_mediachange(ifp) 1753 struct ifnet *ifp; 1754{ 1755 struct fxp_softc *sc = ifp->if_softc; 1756 struct ifmedia *ifm = &sc->sc_media; 1757 1758 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1759 return (EINVAL); 1760 1761 fxp_set_media(sc, ifm->ifm_media); 1762 return (0); 1763} 1764 1765/* 1766 * Notify the world which media we're using. 1767 */ 1768void 1769fxp_mediastatus(ifp, ifmr) 1770 struct ifnet *ifp; 1771 struct ifmediareq *ifmr; 1772{ 1773 struct fxp_softc *sc = ifp->if_softc; 1774 int flags, stsflags; 1775 1776 switch (sc->phy_primary_device) { 1777 case FXP_PHY_82555: 1778 case FXP_PHY_82555B: 1779 case FXP_PHY_DP83840: 1780 case FXP_PHY_DP83840A: 1781 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */ 1782 ifmr->ifm_active = IFM_ETHER; 1783 /* 1784 * the following is not an error. 1785 * You need to read this register twice to get current 1786 * status. This is correct documented behaviour, the 1787 * first read gets latched values. 1788 */ 1789 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1790 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1791 if (stsflags & FXP_PHY_STS_LINK_STS) 1792 ifmr->ifm_status |= IFM_ACTIVE; 1793 1794 /* 1795 * If we are in auto mode, then try report the result. 1796 */ 1797 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR); 1798 if (flags & FXP_PHY_BMCR_AUTOEN) { 1799 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */ 1800 if (stsflags & FXP_PHY_STS_AUTO_DONE) { 1801 /* 1802 * Intel and National parts report 1803 * differently on what they found. 1804 */ 1805 if ((sc->phy_primary_device == FXP_PHY_82555) 1806 || (sc->phy_primary_device == FXP_PHY_82555B)) { 1807 flags = fxp_mdi_read(sc, 1808 sc->phy_primary_addr, 1809 FXP_PHY_USC); 1810 1811 if (flags & FXP_PHY_USC_SPEED) 1812 ifmr->ifm_active |= IFM_100_TX; 1813 else 1814 ifmr->ifm_active |= IFM_10_T; 1815 1816 if (flags & FXP_PHY_USC_DUPLEX) 1817 ifmr->ifm_active |= IFM_FDX; 1818 } else { /* it's National. only know speed */ 1819 flags = fxp_mdi_read(sc, 1820 sc->phy_primary_addr, 1821 FXP_DP83840_PAR); 1822 1823 if (flags & FXP_DP83840_PAR_SPEED_10) 1824 ifmr->ifm_active |= IFM_10_T; 1825 else 1826 ifmr->ifm_active |= IFM_100_TX; 1827 } 1828 } 1829 } else { /* in manual mode.. just report what we were set to */ 1830 if (flags & FXP_PHY_BMCR_SPEED_100M) 1831 ifmr->ifm_active |= IFM_100_TX; 1832 else 1833 ifmr->ifm_active |= IFM_10_T; 1834 1835 if (flags & FXP_PHY_BMCR_FULLDUPLEX) 1836 ifmr->ifm_active |= IFM_FDX; 1837 } 1838 break; 1839 1840 case FXP_PHY_80C24: 1841 default: 1842 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */ 1843 } 1844} 1845 1846/* 1847 * Add a buffer to the end of the RFA buffer list. 1848 * Return 0 if successful, 1 for failure. A failure results in 1849 * adding the 'oldm' (if non-NULL) on to the end of the list - 1850 * tossing out its old contents and recycling it. 1851 * The RFA struct is stuck at the beginning of mbuf cluster and the 1852 * data pointer is fixed up to point just past it. 1853 */ 1854static int 1855fxp_add_rfabuf(sc, oldm) 1856 struct fxp_softc *sc; 1857 struct mbuf *oldm; 1858{ 1859 u_int32_t v; 1860 struct mbuf *m; 1861 struct fxp_rfa *rfa, *p_rfa; 1862 1863 MGETHDR(m, M_DONTWAIT, MT_DATA); 1864 if (m != NULL) { 1865 MCLGET(m, M_DONTWAIT); 1866 if ((m->m_flags & M_EXT) == 0) { 1867 m_freem(m); 1868 if (oldm == NULL) 1869 return 1; 1870 m = oldm; 1871 m->m_data = m->m_ext.ext_buf; 1872 } 1873 } else { 1874 if (oldm == NULL) 1875 return 1; 1876 m = oldm; 1877 m->m_data = m->m_ext.ext_buf; 1878 } 1879 1880 /* 1881 * Move the data pointer up so that the incoming data packet 1882 * will be 32-bit aligned. 1883 */ 1884 m->m_data += RFA_ALIGNMENT_FUDGE; 1885 1886 /* 1887 * Get a pointer to the base of the mbuf cluster and move 1888 * data start past it. 1889 */ 1890 rfa = mtod(m, struct fxp_rfa *); 1891 m->m_data += sizeof(struct fxp_rfa); 1892 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1893 1894 /* 1895 * Initialize the rest of the RFA. Note that since the RFA 1896 * is misaligned, we cannot store values directly. Instead, 1897 * we use an optimized, inline copy. 1898 */ 1899 1900 rfa->rfa_status = 0; 1901 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1902 rfa->actual_size = 0; 1903 1904 v = -1; 1905 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1906 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1907 1908 /* 1909 * If there are other buffers already on the list, attach this 1910 * one to the end by fixing up the tail to point to this one. 1911 */ 1912 if (sc->rfa_headm != NULL) { 1913 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1914 RFA_ALIGNMENT_FUDGE); 1915 sc->rfa_tailm->m_next = m; 1916 v = vtophys(rfa); 1917 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1918 p_rfa->rfa_control = 0; 1919 } else { 1920 sc->rfa_headm = m; 1921 } 1922 sc->rfa_tailm = m; 1923 1924 return (m == oldm); 1925} 1926 1927static volatile int 1928fxp_mdi_read(sc, phy, reg) 1929 struct fxp_softc *sc; 1930 int phy; 1931 int reg; 1932{ 1933 int count = 10000; 1934 int value; 1935 1936 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1937 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1938 1939 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1940 && count--) 1941 DELAY(10); 1942 1943 if (count <= 0) 1944 printf(FXP_FORMAT ": fxp_mdi_read: timed out\n", 1945 FXP_ARGS(sc)); 1946 1947 return (value & 0xffff); 1948} 1949 1950static void 1951fxp_mdi_write(sc, phy, reg, value) 1952 struct fxp_softc *sc; 1953 int phy; 1954 int reg; 1955 int value; 1956{ 1957 int count = 10000; 1958 1959 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1960 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1961 (value & 0xffff)); 1962 1963 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1964 count--) 1965 DELAY(10); 1966 1967 if (count <= 0) 1968 printf(FXP_FORMAT ": fxp_mdi_write: timed out\n", 1969 FXP_ARGS(sc)); 1970} 1971 1972static int 1973fxp_ioctl(ifp, command, data) 1974 struct ifnet *ifp; 1975 FXP_IOCTLCMD_TYPE command; 1976 caddr_t data; 1977{ 1978 struct fxp_softc *sc = ifp->if_softc; 1979 struct ifreq *ifr = (struct ifreq *)data; 1980 FXP_SPLVAR(s) 1981 int error = 0; 1982 1983 FXP_LOCK(sc, s); 1984 1985 switch (command) { 1986 1987 case SIOCSIFADDR: 1988#if !defined(__NetBSD__) 1989 case SIOCGIFADDR: 1990 case SIOCSIFMTU: 1991#endif 1992 error = ether_ioctl(ifp, command, data); 1993 break; 1994 1995 case SIOCSIFFLAGS: 1996 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1997 1998 /* 1999 * If interface is marked up and not running, then start it. 2000 * If it is marked down and running, stop it. 2001 * XXX If it's up then re-initialize it. This is so flags 2002 * such as IFF_PROMISC are handled. 2003 */ 2004 if (ifp->if_flags & IFF_UP) { 2005 fxp_init(sc); 2006 } else { 2007 if (ifp->if_flags & IFF_RUNNING) 2008 fxp_stop(sc); 2009 } 2010 break; 2011 2012 case SIOCADDMULTI: 2013 case SIOCDELMULTI: 2014 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 2015#if defined(__NetBSD__) 2016 error = (command == SIOCADDMULTI) ? 2017 ether_addmulti(ifr, &sc->sc_ethercom) : 2018 ether_delmulti(ifr, &sc->sc_ethercom); 2019 2020 if (error == ENETRESET) { 2021 /* 2022 * Multicast list has changed; set the hardware 2023 * filter accordingly. 2024 */ 2025 if (!sc->all_mcasts) 2026 fxp_mc_setup(sc); 2027 /* 2028 * fxp_mc_setup() can turn on all_mcasts if we run 2029 * out of space, so check it again rather than else {}. 2030 */ 2031 if (sc->all_mcasts) 2032 fxp_init(sc); 2033 error = 0; 2034 } 2035#else /* __FreeBSD__ */ 2036 /* 2037 * Multicast list has changed; set the hardware filter 2038 * accordingly. 2039 */ 2040 if (!sc->all_mcasts) 2041 fxp_mc_setup(sc); 2042 /* 2043 * fxp_mc_setup() can turn on sc->all_mcasts, so check it 2044 * again rather than else {}. 2045 */ 2046 if (sc->all_mcasts) 2047 fxp_init(sc); 2048 error = 0; 2049#endif /* __NetBSD__ */ 2050 break; 2051 2052 case SIOCSIFMEDIA: 2053 case SIOCGIFMEDIA: 2054 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2055 break; 2056 2057 default: 2058 error = EINVAL; 2059 } 2060 FXP_UNLOCK(sc, s); 2061 return (error); 2062} 2063 2064/* 2065 * Program the multicast filter. 2066 * 2067 * We have an artificial restriction that the multicast setup command 2068 * must be the first command in the chain, so we take steps to ensure 2069 * this. By requiring this, it allows us to keep up the performance of 2070 * the pre-initialized command ring (esp. link pointers) by not actually 2071 * inserting the mcsetup command in the ring - i.e. its link pointer 2072 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2073 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2074 * lead into the regular TxCB ring when it completes. 2075 * 2076 * This function must be called at splimp. 2077 */ 2078static void 2079fxp_mc_setup(sc) 2080 struct fxp_softc *sc; 2081{ 2082 struct fxp_cb_mcs *mcsp = sc->mcsp; 2083 struct ifnet *ifp = &sc->sc_if; 2084 struct ifmultiaddr *ifma; 2085 int nmcasts; 2086 int count; 2087 2088 /* 2089 * If there are queued commands, we must wait until they are all 2090 * completed. If we are already waiting, then add a NOP command 2091 * with interrupt option so that we're notified when all commands 2092 * have been completed - fxp_start() ensures that no additional 2093 * TX commands will be added when need_mcsetup is true. 2094 */ 2095 if (sc->tx_queued) { 2096 struct fxp_cb_tx *txp; 2097 2098 /* 2099 * need_mcsetup will be true if we are already waiting for the 2100 * NOP command to be completed (see below). In this case, bail. 2101 */ 2102 if (sc->need_mcsetup) 2103 return; 2104 sc->need_mcsetup = 1; 2105 2106 /* 2107 * Add a NOP command with interrupt so that we are notified when all 2108 * TX commands have been processed. 2109 */ 2110 txp = sc->cbl_last->next; 2111 txp->mb_head = NULL; 2112 txp->cb_status = 0; 2113 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2114 /* 2115 * Advance the end of list forward. 2116 */ 2117 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2118 sc->cbl_last = txp; 2119 sc->tx_queued++; 2120 /* 2121 * Issue a resume in case the CU has just suspended. 2122 */ 2123 fxp_scb_wait(sc); 2124 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 2125 /* 2126 * Set a 5 second timer just in case we don't hear from the 2127 * card again. 2128 */ 2129 ifp->if_timer = 5; 2130 2131 return; 2132 } 2133 sc->need_mcsetup = 0; 2134 2135 /* 2136 * Initialize multicast setup descriptor. 2137 */ 2138 mcsp->next = sc->cbl_base; 2139 mcsp->mb_head = NULL; 2140 mcsp->cb_status = 0; 2141 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2142 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2143 2144 nmcasts = 0; 2145 if (!sc->all_mcasts) { 2146 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 2147 ifma = ifma->ifma_link.le_next) { 2148 if (ifma->ifma_addr->sa_family != AF_LINK) 2149 continue; 2150 if (nmcasts >= MAXMCADDR) { 2151 sc->all_mcasts = 1; 2152 nmcasts = 0; 2153 break; 2154 } 2155 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2156 (void *)(uintptr_t)(volatile void *) 2157 &sc->mcsp->mc_addr[nmcasts][0], 6); 2158 nmcasts++; 2159 } 2160 } 2161 mcsp->mc_cnt = nmcasts * 6; 2162 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2163 sc->tx_queued = 1; 2164 2165 /* 2166 * Wait until command unit is not active. This should never 2167 * be the case when nothing is queued, but make sure anyway. 2168 */ 2169 count = 100; 2170 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2171 FXP_SCB_CUS_ACTIVE && --count) 2172 DELAY(10); 2173 if (count == 0) { 2174 printf(FXP_FORMAT ": command queue timeout\n", FXP_ARGS(sc)); 2175 return; 2176 } 2177 2178 /* 2179 * Start the multicast setup command. 2180 */ 2181 fxp_scb_wait(sc); 2182 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2183 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 2184 2185 ifp->if_timer = 2; 2186 return; 2187} 2188