if_fxp.c revision 271782
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 271782 2014-09-18 15:56:14Z glebius $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#ifdef HAVE_KERNEL_OPTION_HEADERS 38#include "opt_device_polling.h" 39#endif 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/mbuf.h> 47#include <sys/lock.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_var.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_media.h> 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#include <netinet/in.h> 66#include <netinet/in_systm.h> 67#include <netinet/ip.h> 68#include <netinet/tcp.h> 69#include <netinet/udp.h> 70 71#include <machine/bus.h> 72#include <machine/in_cksum.h> 73#include <machine/resource.h> 74 75#include <dev/pci/pcivar.h> 76#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80 81#include <dev/fxp/if_fxpreg.h> 82#include <dev/fxp/if_fxpvar.h> 83#include <dev/fxp/rcvbundl.h> 84 85MODULE_DEPEND(fxp, pci, 1, 1, 1); 86MODULE_DEPEND(fxp, ether, 1, 1, 1); 87MODULE_DEPEND(fxp, miibus, 1, 1, 1); 88#include "miibus_if.h" 89 90/* 91 * NOTE! On !x86 we typically have an alignment constraint. The 92 * card DMAs the packet immediately following the RFA. However, 93 * the first thing in the packet is a 14-byte Ethernet header. 94 * This means that the packet is misaligned. To compensate, 95 * we actually offset the RFA 2 bytes into the cluster. This 96 * alignes the packet after the Ethernet header at a 32-bit 97 * boundary. HOWEVER! This means that the RFA is misaligned! 98 */ 99#define RFA_ALIGNMENT_FUDGE 2 100 101/* 102 * Set initial transmit threshold at 64 (512 bytes). This is 103 * increased by 64 (512 bytes) at a time, to maximum of 192 104 * (1536 bytes), if an underrun occurs. 105 */ 106static int tx_threshold = 64; 107 108/* 109 * The configuration byte map has several undefined fields which 110 * must be one or must be zero. Set up a template for these bits. 111 * The actual configuration is performed in fxp_init_body. 112 * 113 * See struct fxp_cb_config for the bit definitions. 114 */ 115static const u_char fxp_cb_config_template[] = { 116 0x0, 0x0, /* cb_status */ 117 0x0, 0x0, /* cb_command */ 118 0x0, 0x0, 0x0, 0x0, /* link_addr */ 119 0x0, /* 0 */ 120 0x0, /* 1 */ 121 0x0, /* 2 */ 122 0x0, /* 3 */ 123 0x0, /* 4 */ 124 0x0, /* 5 */ 125 0x32, /* 6 */ 126 0x0, /* 7 */ 127 0x0, /* 8 */ 128 0x0, /* 9 */ 129 0x6, /* 10 */ 130 0x0, /* 11 */ 131 0x0, /* 12 */ 132 0x0, /* 13 */ 133 0xf2, /* 14 */ 134 0x48, /* 15 */ 135 0x0, /* 16 */ 136 0x40, /* 17 */ 137 0xf0, /* 18 */ 138 0x0, /* 19 */ 139 0x3f, /* 20 */ 140 0x5, /* 21 */ 141 0x0, /* 22 */ 142 0x0, /* 23 */ 143 0x0, /* 24 */ 144 0x0, /* 25 */ 145 0x0, /* 26 */ 146 0x0, /* 27 */ 147 0x0, /* 28 */ 148 0x0, /* 29 */ 149 0x0, /* 30 */ 150 0x0 /* 31 */ 151}; 152 153/* 154 * Claim various Intel PCI device identifiers for this driver. The 155 * sub-vendor and sub-device field are extensively used to identify 156 * particular variants, but we don't currently differentiate between 157 * them. 158 */ 159static const struct fxp_ident fxp_ident_table[] = { 160 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 161 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 162 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 163 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 164 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 167 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 169 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 170 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 171 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 172 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 173 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 174 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 175 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 176 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 177 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 178 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 179 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 180 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 181 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 182 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 183 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 184 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 185 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 186 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 187 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 188 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 189 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 190 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 191 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 192 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 193 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 194 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 195 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 196 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 197 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 198 { 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" }, 199 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 200 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 201 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 202 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 203 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 204 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 205 { 0, -1, 0, NULL }, 206}; 207 208#ifdef FXP_IP_CSUM_WAR 209#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 210#else 211#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 212#endif 213 214static int fxp_probe(device_t dev); 215static int fxp_attach(device_t dev); 216static int fxp_detach(device_t dev); 217static int fxp_shutdown(device_t dev); 218static int fxp_suspend(device_t dev); 219static int fxp_resume(device_t dev); 220 221static const struct fxp_ident *fxp_find_ident(device_t dev); 222static void fxp_intr(void *xsc); 223static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp, 224 struct mbuf *m, uint16_t status, int pos); 225static int fxp_intr_body(struct fxp_softc *sc, if_t ifp, 226 uint8_t statack, int count); 227static void fxp_init(void *xsc); 228static void fxp_init_body(struct fxp_softc *sc, int); 229static void fxp_tick(void *xsc); 230static void fxp_start(if_t ifp); 231static void fxp_start_body(if_t ifp); 232static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 233static void fxp_txeof(struct fxp_softc *sc); 234static void fxp_stop(struct fxp_softc *sc); 235static void fxp_release(struct fxp_softc *sc); 236static int fxp_ioctl(if_t ifp, u_long command, 237 caddr_t data); 238static void fxp_watchdog(struct fxp_softc *sc); 239static void fxp_add_rfabuf(struct fxp_softc *sc, 240 struct fxp_rx *rxp); 241static void fxp_discard_rfabuf(struct fxp_softc *sc, 242 struct fxp_rx *rxp); 243static int fxp_new_rfabuf(struct fxp_softc *sc, 244 struct fxp_rx *rxp); 245static int fxp_mc_addrs(struct fxp_softc *sc); 246static void fxp_mc_setup(struct fxp_softc *sc); 247static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 248 int autosize); 249static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 250 uint16_t data); 251static void fxp_autosize_eeprom(struct fxp_softc *sc); 252static void fxp_load_eeprom(struct fxp_softc *sc); 253static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 254 int offset, int words); 255static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 256 int offset, int words); 257static int fxp_ifmedia_upd(if_t ifp); 258static void fxp_ifmedia_sts(if_t ifp, 259 struct ifmediareq *ifmr); 260static int fxp_serial_ifmedia_upd(if_t ifp); 261static void fxp_serial_ifmedia_sts(if_t ifp, 262 struct ifmediareq *ifmr); 263static int fxp_miibus_readreg(device_t dev, int phy, int reg); 264static int fxp_miibus_writereg(device_t dev, int phy, int reg, 265 int value); 266static void fxp_miibus_statchg(device_t dev); 267static void fxp_load_ucode(struct fxp_softc *sc); 268static void fxp_update_stats(struct fxp_softc *sc); 269static void fxp_sysctl_node(struct fxp_softc *sc); 270static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 271 int low, int high); 272static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 273static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 274static void fxp_scb_wait(struct fxp_softc *sc); 275static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 276static void fxp_dma_wait(struct fxp_softc *sc, 277 volatile uint16_t *status, bus_dma_tag_t dmat, 278 bus_dmamap_t map); 279 280static device_method_t fxp_methods[] = { 281 /* Device interface */ 282 DEVMETHOD(device_probe, fxp_probe), 283 DEVMETHOD(device_attach, fxp_attach), 284 DEVMETHOD(device_detach, fxp_detach), 285 DEVMETHOD(device_shutdown, fxp_shutdown), 286 DEVMETHOD(device_suspend, fxp_suspend), 287 DEVMETHOD(device_resume, fxp_resume), 288 289 /* MII interface */ 290 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 291 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 292 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 293 294 DEVMETHOD_END 295}; 296 297static driver_t fxp_driver = { 298 "fxp", 299 fxp_methods, 300 sizeof(struct fxp_softc), 301}; 302 303static devclass_t fxp_devclass; 304 305DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL, 306 SI_ORDER_ANY); 307DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL); 308 309static struct resource_spec fxp_res_spec_mem[] = { 310 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 312 { -1, 0 } 313}; 314 315static struct resource_spec fxp_res_spec_io[] = { 316 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 318 { -1, 0 } 319}; 320 321/* 322 * Wait for the previous command to be accepted (but not necessarily 323 * completed). 324 */ 325static void 326fxp_scb_wait(struct fxp_softc *sc) 327{ 328 union { 329 uint16_t w; 330 uint8_t b[2]; 331 } flowctl; 332 int i = 10000; 333 334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 335 DELAY(2); 336 if (i == 0) { 337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 343 } 344} 345 346static void 347fxp_scb_cmd(struct fxp_softc *sc, int cmd) 348{ 349 350 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 352 fxp_scb_wait(sc); 353 } 354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 355} 356 357static void 358fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 359 bus_dma_tag_t dmat, bus_dmamap_t map) 360{ 361 int i; 362 363 for (i = 10000; i > 0; i--) { 364 DELAY(2); 365 bus_dmamap_sync(dmat, map, 366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 368 break; 369 } 370 if (i == 0) 371 device_printf(sc->dev, "DMA timeout\n"); 372} 373 374static const struct fxp_ident * 375fxp_find_ident(device_t dev) 376{ 377 uint16_t devid; 378 uint8_t revid; 379 const struct fxp_ident *ident; 380 381 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 382 devid = pci_get_device(dev); 383 revid = pci_get_revid(dev); 384 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 385 if (ident->devid == devid && 386 (ident->revid == revid || ident->revid == -1)) { 387 return (ident); 388 } 389 } 390 } 391 return (NULL); 392} 393 394/* 395 * Return identification string if this device is ours. 396 */ 397static int 398fxp_probe(device_t dev) 399{ 400 const struct fxp_ident *ident; 401 402 ident = fxp_find_ident(dev); 403 if (ident != NULL) { 404 device_set_desc(dev, ident->name); 405 return (BUS_PROBE_DEFAULT); 406 } 407 return (ENXIO); 408} 409 410static void 411fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 412{ 413 uint32_t *addr; 414 415 if (error) 416 return; 417 418 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 419 addr = arg; 420 *addr = segs->ds_addr; 421} 422 423static int 424fxp_attach(device_t dev) 425{ 426 struct fxp_softc *sc; 427 struct fxp_cb_tx *tcbp; 428 struct fxp_tx *txp; 429 struct fxp_rx *rxp; 430 if_t ifp; 431 uint32_t val; 432 uint16_t data; 433 u_char eaddr[ETHER_ADDR_LEN]; 434 int error, flags, i, pmc, prefer_iomap; 435 436 error = 0; 437 sc = device_get_softc(dev); 438 sc->dev = dev; 439 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 440 MTX_DEF); 441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 443 fxp_serial_ifmedia_sts); 444 445 ifp = sc->ifp = if_gethandle(IFT_ETHER); 446 if (ifp == (void *)NULL) { 447 device_printf(dev, "can not if_alloc()\n"); 448 error = ENOSPC; 449 goto fail; 450 } 451 452 /* 453 * Enable bus mastering. 454 */ 455 pci_enable_busmaster(dev); 456 457 /* 458 * Figure out which we should try first - memory mapping or i/o mapping? 459 * We default to memory mapping. Then we accept an override from the 460 * command line. Then we check to see which one is enabled. 461 */ 462 prefer_iomap = 0; 463 resource_int_value(device_get_name(dev), device_get_unit(dev), 464 "prefer_iomap", &prefer_iomap); 465 if (prefer_iomap) 466 sc->fxp_spec = fxp_res_spec_io; 467 else 468 sc->fxp_spec = fxp_res_spec_mem; 469 470 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 471 if (error) { 472 if (sc->fxp_spec == fxp_res_spec_mem) 473 sc->fxp_spec = fxp_res_spec_io; 474 else 475 sc->fxp_spec = fxp_res_spec_mem; 476 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 477 } 478 if (error) { 479 device_printf(dev, "could not allocate resources\n"); 480 error = ENXIO; 481 goto fail; 482 } 483 484 if (bootverbose) { 485 device_printf(dev, "using %s space register mapping\n", 486 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 487 } 488 489 /* 490 * Put CU/RU idle state and prepare full reset. 491 */ 492 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 493 DELAY(10); 494 /* Full reset and disable interrupts. */ 495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 496 DELAY(10); 497 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 498 499 /* 500 * Find out how large of an SEEPROM we have. 501 */ 502 fxp_autosize_eeprom(sc); 503 fxp_load_eeprom(sc); 504 505 /* 506 * Find out the chip revision; lump all 82557 revs together. 507 */ 508 sc->ident = fxp_find_ident(dev); 509 if (sc->ident->ich > 0) { 510 /* Assume ICH controllers are 82559. */ 511 sc->revision = FXP_REV_82559_A0; 512 } else { 513 data = sc->eeprom[FXP_EEPROM_MAP_CNTR]; 514 if ((data >> 8) == 1) 515 sc->revision = FXP_REV_82557; 516 else 517 sc->revision = pci_get_revid(dev); 518 } 519 520 /* 521 * Check availability of WOL. 82559ER does not support WOL. 522 */ 523 if (sc->revision >= FXP_REV_82558_A4 && 524 sc->revision != FXP_REV_82559S_A) { 525 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 526 if ((data & 0x20) != 0 && 527 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 528 sc->flags |= FXP_FLAG_WOLCAP; 529 } 530 531 if (sc->revision == FXP_REV_82550_C) { 532 /* 533 * 82550C with server extension requires microcode to 534 * receive fragmented UDP datagrams. However if the 535 * microcode is used for client-only featured 82550C 536 * it locks up controller. 537 */ 538 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 539 if ((data & 0x0400) == 0) 540 sc->flags |= FXP_FLAG_NO_UCODE; 541 } 542 543 /* Receiver lock-up workaround detection. */ 544 if (sc->revision < FXP_REV_82558_A4) { 545 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT]; 546 if ((data & 0x03) != 0x03) { 547 sc->flags |= FXP_FLAG_RXBUG; 548 device_printf(dev, "Enabling Rx lock-up workaround\n"); 549 } 550 } 551 552 /* 553 * Determine whether we must use the 503 serial interface. 554 */ 555 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY]; 556 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 557 && (data & FXP_PHY_SERIAL_ONLY)) 558 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 559 560 fxp_sysctl_node(sc); 561 /* 562 * Enable workarounds for certain chip revision deficiencies. 563 * 564 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 565 * some systems based a normal 82559 design, have a defect where 566 * the chip can cause a PCI protocol violation if it receives 567 * a CU_RESUME command when it is entering the IDLE state. The 568 * workaround is to disable Dynamic Standby Mode, so the chip never 569 * deasserts CLKRUN#, and always remains in an active state. 570 * 571 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 572 */ 573 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 574 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 575 data = sc->eeprom[FXP_EEPROM_MAP_ID]; 576 if (data & 0x02) { /* STB enable */ 577 uint16_t cksum; 578 int i; 579 580 device_printf(dev, 581 "Disabling dynamic standby mode in EEPROM\n"); 582 data &= ~0x02; 583 sc->eeprom[FXP_EEPROM_MAP_ID] = data; 584 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1); 585 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 586 cksum = 0; 587 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 588 cksum += sc->eeprom[i]; 589 i = (1 << sc->eeprom_size) - 1; 590 cksum = 0xBABA - cksum; 591 fxp_write_eeprom(sc, &cksum, i, 1); 592 device_printf(dev, 593 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 594 i, sc->eeprom[i], cksum); 595 sc->eeprom[i] = cksum; 596 /* 597 * If the user elects to continue, try the software 598 * workaround, as it is better than nothing. 599 */ 600 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 601 } 602 } 603 604 /* 605 * If we are not a 82557 chip, we can enable extended features. 606 */ 607 if (sc->revision != FXP_REV_82557) { 608 /* 609 * If MWI is enabled in the PCI configuration, and there 610 * is a valid cacheline size (8 or 16 dwords), then tell 611 * the board to turn on MWI. 612 */ 613 val = pci_read_config(dev, PCIR_COMMAND, 2); 614 if (val & PCIM_CMD_MWRICEN && 615 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 616 sc->flags |= FXP_FLAG_MWI_ENABLE; 617 618 /* turn on the extended TxCB feature */ 619 sc->flags |= FXP_FLAG_EXT_TXCB; 620 621 /* enable reception of long frames for VLAN */ 622 sc->flags |= FXP_FLAG_LONG_PKT_EN; 623 } else { 624 /* a hack to get long VLAN frames on a 82557 */ 625 sc->flags |= FXP_FLAG_SAVE_BAD; 626 } 627 628 /* For 82559 or later chips, Rx checksum offload is supported. */ 629 if (sc->revision >= FXP_REV_82559_A0) { 630 /* 82559ER does not support Rx checksum offloading. */ 631 if (sc->ident->devid != 0x1209) 632 sc->flags |= FXP_FLAG_82559_RXCSUM; 633 } 634 /* 635 * Enable use of extended RFDs and TCBs for 82550 636 * and later chips. Note: we need extended TXCB support 637 * too, but that's already enabled by the code above. 638 * Be careful to do this only on the right devices. 639 */ 640 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 641 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 642 || sc->revision == FXP_REV_82551_10) { 643 sc->rfa_size = sizeof (struct fxp_rfa); 644 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 645 sc->flags |= FXP_FLAG_EXT_RFA; 646 /* Use extended RFA instead of 82559 checksum mode. */ 647 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 648 } else { 649 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 650 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 651 } 652 653 /* 654 * Allocate DMA tags and DMA safe memory. 655 */ 656 sc->maxtxseg = FXP_NTXSEG; 657 sc->maxsegsize = MCLBYTES; 658 if (sc->flags & FXP_FLAG_EXT_RFA) { 659 sc->maxtxseg--; 660 sc->maxsegsize = FXP_TSO_SEGSIZE; 661 } 662 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 663 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 664 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 665 sc->maxtxseg, sc->maxsegsize, 0, 666 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 667 if (error) { 668 device_printf(dev, "could not create TX DMA tag\n"); 669 goto fail; 670 } 671 672 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 673 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 674 MCLBYTES, 1, MCLBYTES, 0, 675 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 676 if (error) { 677 device_printf(dev, "could not create RX DMA tag\n"); 678 goto fail; 679 } 680 681 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 682 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 683 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 684 busdma_lock_mutex, &Giant, &sc->fxp_stag); 685 if (error) { 686 device_printf(dev, "could not create stats DMA tag\n"); 687 goto fail; 688 } 689 690 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 691 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 692 if (error) { 693 device_printf(dev, "could not allocate stats DMA memory\n"); 694 goto fail; 695 } 696 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 697 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 698 BUS_DMA_NOWAIT); 699 if (error) { 700 device_printf(dev, "could not load the stats DMA buffer\n"); 701 goto fail; 702 } 703 704 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 705 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 706 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 707 busdma_lock_mutex, &Giant, &sc->cbl_tag); 708 if (error) { 709 device_printf(dev, "could not create TxCB DMA tag\n"); 710 goto fail; 711 } 712 713 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 714 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 715 if (error) { 716 device_printf(dev, "could not allocate TxCB DMA memory\n"); 717 goto fail; 718 } 719 720 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 721 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 722 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT); 723 if (error) { 724 device_printf(dev, "could not load TxCB DMA buffer\n"); 725 goto fail; 726 } 727 728 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 729 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 730 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 731 busdma_lock_mutex, &Giant, &sc->mcs_tag); 732 if (error) { 733 device_printf(dev, 734 "could not create multicast setup DMA tag\n"); 735 goto fail; 736 } 737 738 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 739 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 740 if (error) { 741 device_printf(dev, 742 "could not allocate multicast setup DMA memory\n"); 743 goto fail; 744 } 745 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 746 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 747 BUS_DMA_NOWAIT); 748 if (error) { 749 device_printf(dev, 750 "can't load the multicast setup DMA buffer\n"); 751 goto fail; 752 } 753 754 /* 755 * Pre-allocate the TX DMA maps and setup the pointers to 756 * the TX command blocks. 757 */ 758 txp = sc->fxp_desc.tx_list; 759 tcbp = sc->fxp_desc.cbl_list; 760 for (i = 0; i < FXP_NTXCB; i++) { 761 txp[i].tx_cb = tcbp + i; 762 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 763 if (error) { 764 device_printf(dev, "can't create DMA map for TX\n"); 765 goto fail; 766 } 767 } 768 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 769 if (error) { 770 device_printf(dev, "can't create spare DMA map\n"); 771 goto fail; 772 } 773 774 /* 775 * Pre-allocate our receive buffers. 776 */ 777 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 778 for (i = 0; i < FXP_NRFABUFS; i++) { 779 rxp = &sc->fxp_desc.rx_list[i]; 780 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 781 if (error) { 782 device_printf(dev, "can't create DMA map for RX\n"); 783 goto fail; 784 } 785 if (fxp_new_rfabuf(sc, rxp) != 0) { 786 error = ENOMEM; 787 goto fail; 788 } 789 fxp_add_rfabuf(sc, rxp); 790 } 791 792 /* 793 * Read MAC address. 794 */ 795 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff; 796 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8; 797 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff; 798 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8; 799 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff; 800 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8; 801 if (bootverbose) { 802 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 803 pci_get_vendor(dev), pci_get_device(dev), 804 pci_get_subvendor(dev), pci_get_subdevice(dev), 805 pci_get_revid(dev)); 806 device_printf(dev, "Dynamic Standby mode is %s\n", 807 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" : 808 "disabled"); 809 } 810 811 /* 812 * If this is only a 10Mbps device, then there is no MII, and 813 * the PHY will use a serial interface instead. 814 * 815 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 816 * doesn't have a programming interface of any sort. The 817 * media is sensed automatically based on how the link partner 818 * is configured. This is, in essence, manual configuration. 819 */ 820 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 821 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 822 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 823 } else { 824 /* 825 * i82557 wedge when isolating all of their PHYs. 826 */ 827 flags = MIIF_NOISOLATE; 828 if (sc->revision >= FXP_REV_82558_A4) 829 flags |= MIIF_DOPAUSE; 830 error = mii_attach(dev, &sc->miibus, ifp, 831 (ifm_change_cb_t)fxp_ifmedia_upd, 832 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK, 833 MII_PHY_ANY, MII_OFFSET_ANY, flags); 834 if (error != 0) { 835 device_printf(dev, "attaching PHYs failed\n"); 836 goto fail; 837 } 838 } 839 840 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 841 if_setdev(ifp, dev); 842 if_setinitfn(ifp, fxp_init); 843 if_setsoftc(ifp, sc); 844 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 845 if_setioctlfn(ifp, fxp_ioctl); 846 if_setstartfn(ifp, fxp_start); 847 848 if_setcapabilities(ifp, 0); 849 if_setcapenable(ifp, 0); 850 851 /* Enable checksum offload/TSO for 82550 or better chips */ 852 if (sc->flags & FXP_FLAG_EXT_RFA) { 853 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO); 854 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 855 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 856 } 857 858 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 859 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 860 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0); 861 } 862 863 if (sc->flags & FXP_FLAG_WOLCAP) { 864 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 865 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0); 866 } 867 868#ifdef DEVICE_POLLING 869 /* Inform the world we support polling. */ 870 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 871#endif 872 873 /* 874 * Attach the interface. 875 */ 876 ether_ifattach(ifp, eaddr); 877 878 /* 879 * Tell the upper layer(s) we support long frames. 880 * Must appear after the call to ether_ifattach() because 881 * ether_ifattach() sets ifi_hdrlen to the default value. 882 */ 883 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 884 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 885 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 886 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 887 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | 888 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 889 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING | 890 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 891 } 892 893 /* 894 * Let the system queue as many packets as we have available 895 * TX descriptors. 896 */ 897 if_setsendqlen(ifp, FXP_NTXCB - 1); 898 if_setsendqready(ifp); 899 900 /* 901 * Hook our interrupt after all initialization is complete. 902 */ 903 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 904 NULL, fxp_intr, sc, &sc->ih); 905 if (error) { 906 device_printf(dev, "could not setup irq\n"); 907 ether_ifdetach(sc->ifp); 908 goto fail; 909 } 910 911 /* 912 * Configure hardware to reject magic frames otherwise 913 * system will hang on recipt of magic frames. 914 */ 915 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 916 FXP_LOCK(sc); 917 /* Clear wakeup events. */ 918 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 919 fxp_init_body(sc, 0); 920 fxp_stop(sc); 921 FXP_UNLOCK(sc); 922 } 923 924fail: 925 if (error) 926 fxp_release(sc); 927 return (error); 928} 929 930/* 931 * Release all resources. The softc lock should not be held and the 932 * interrupt should already be torn down. 933 */ 934static void 935fxp_release(struct fxp_softc *sc) 936{ 937 struct fxp_rx *rxp; 938 struct fxp_tx *txp; 939 int i; 940 941 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 942 KASSERT(sc->ih == NULL, 943 ("fxp_release() called with intr handle still active")); 944 if (sc->miibus) 945 device_delete_child(sc->dev, sc->miibus); 946 bus_generic_detach(sc->dev); 947 ifmedia_removeall(&sc->sc_media); 948 if (sc->fxp_desc.cbl_list) { 949 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 950 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 951 sc->cbl_map); 952 } 953 if (sc->fxp_stats) { 954 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 955 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 956 } 957 if (sc->mcsp) { 958 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 959 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 960 } 961 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 962 if (sc->fxp_rxmtag) { 963 for (i = 0; i < FXP_NRFABUFS; i++) { 964 rxp = &sc->fxp_desc.rx_list[i]; 965 if (rxp->rx_mbuf != NULL) { 966 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 967 BUS_DMASYNC_POSTREAD); 968 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 969 m_freem(rxp->rx_mbuf); 970 } 971 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 972 } 973 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 974 bus_dma_tag_destroy(sc->fxp_rxmtag); 975 } 976 if (sc->fxp_txmtag) { 977 for (i = 0; i < FXP_NTXCB; i++) { 978 txp = &sc->fxp_desc.tx_list[i]; 979 if (txp->tx_mbuf != NULL) { 980 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 981 BUS_DMASYNC_POSTWRITE); 982 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 983 m_freem(txp->tx_mbuf); 984 } 985 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 986 } 987 bus_dma_tag_destroy(sc->fxp_txmtag); 988 } 989 if (sc->fxp_stag) 990 bus_dma_tag_destroy(sc->fxp_stag); 991 if (sc->cbl_tag) 992 bus_dma_tag_destroy(sc->cbl_tag); 993 if (sc->mcs_tag) 994 bus_dma_tag_destroy(sc->mcs_tag); 995 if (sc->ifp) 996 if_free(sc->ifp); 997 998 mtx_destroy(&sc->sc_mtx); 999} 1000 1001/* 1002 * Detach interface. 1003 */ 1004static int 1005fxp_detach(device_t dev) 1006{ 1007 struct fxp_softc *sc = device_get_softc(dev); 1008 1009#ifdef DEVICE_POLLING 1010 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) 1011 ether_poll_deregister_drv(sc->ifp); 1012#endif 1013 1014 FXP_LOCK(sc); 1015 /* 1016 * Stop DMA and drop transmit queue, but disable interrupts first. 1017 */ 1018 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1019 fxp_stop(sc); 1020 FXP_UNLOCK(sc); 1021 callout_drain(&sc->stat_ch); 1022 1023 /* 1024 * Close down routes etc. 1025 */ 1026 ether_ifdetach(sc->ifp); 1027 1028 /* 1029 * Unhook interrupt before dropping lock. This is to prevent 1030 * races with fxp_intr(). 1031 */ 1032 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1033 sc->ih = NULL; 1034 1035 /* Release our allocated resources. */ 1036 fxp_release(sc); 1037 return (0); 1038} 1039 1040/* 1041 * Device shutdown routine. Called at system shutdown after sync. The 1042 * main purpose of this routine is to shut off receiver DMA so that 1043 * kernel memory doesn't get clobbered during warmboot. 1044 */ 1045static int 1046fxp_shutdown(device_t dev) 1047{ 1048 1049 /* 1050 * Make sure that DMA is disabled prior to reboot. Not doing 1051 * do could allow DMA to corrupt kernel memory during the 1052 * reboot before the driver initializes. 1053 */ 1054 return (fxp_suspend(dev)); 1055} 1056 1057/* 1058 * Device suspend routine. Stop the interface and save some PCI 1059 * settings in case the BIOS doesn't restore them properly on 1060 * resume. 1061 */ 1062static int 1063fxp_suspend(device_t dev) 1064{ 1065 struct fxp_softc *sc = device_get_softc(dev); 1066 if_t ifp; 1067 int pmc; 1068 uint16_t pmstat; 1069 1070 FXP_LOCK(sc); 1071 1072 ifp = sc->ifp; 1073 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1074 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1075 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1076 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1077 /* Request PME. */ 1078 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1079 sc->flags |= FXP_FLAG_WOL; 1080 /* Reconfigure hardware to accept magic frames. */ 1081 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1082 fxp_init_body(sc, 0); 1083 } 1084 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1085 } 1086 fxp_stop(sc); 1087 1088 sc->suspended = 1; 1089 1090 FXP_UNLOCK(sc); 1091 return (0); 1092} 1093 1094/* 1095 * Device resume routine. re-enable busmastering, and restart the interface if 1096 * appropriate. 1097 */ 1098static int 1099fxp_resume(device_t dev) 1100{ 1101 struct fxp_softc *sc = device_get_softc(dev); 1102 if_t ifp = sc->ifp; 1103 int pmc; 1104 uint16_t pmstat; 1105 1106 FXP_LOCK(sc); 1107 1108 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1109 sc->flags &= ~FXP_FLAG_WOL; 1110 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1111 /* Disable PME and clear PME status. */ 1112 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1113 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1114 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1115 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1116 CSR_READ_1(sc, FXP_CSR_PMDR)); 1117 } 1118 1119 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1120 DELAY(10); 1121 1122 /* reinitialize interface if necessary */ 1123 if (if_getflags(ifp) & IFF_UP) 1124 fxp_init_body(sc, 1); 1125 1126 sc->suspended = 0; 1127 1128 FXP_UNLOCK(sc); 1129 return (0); 1130} 1131 1132static void 1133fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1134{ 1135 uint16_t reg; 1136 int x; 1137 1138 /* 1139 * Shift in data. 1140 */ 1141 for (x = 1 << (length - 1); x; x >>= 1) { 1142 if (data & x) 1143 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1144 else 1145 reg = FXP_EEPROM_EECS; 1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1147 DELAY(1); 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1149 DELAY(1); 1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1151 DELAY(1); 1152 } 1153} 1154 1155/* 1156 * Read from the serial EEPROM. Basically, you manually shift in 1157 * the read opcode (one bit at a time) and then shift in the address, 1158 * and then you shift out the data (all of this one bit at a time). 1159 * The word size is 16 bits, so you have to provide the address for 1160 * every 16 bits of data. 1161 */ 1162static uint16_t 1163fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1164{ 1165 uint16_t reg, data; 1166 int x; 1167 1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1169 /* 1170 * Shift in read opcode. 1171 */ 1172 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1173 /* 1174 * Shift in address. 1175 */ 1176 data = 0; 1177 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1178 if (offset & x) 1179 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1180 else 1181 reg = FXP_EEPROM_EECS; 1182 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1183 DELAY(1); 1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1185 DELAY(1); 1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1187 DELAY(1); 1188 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1189 data++; 1190 if (autosize && reg == 0) { 1191 sc->eeprom_size = data; 1192 break; 1193 } 1194 } 1195 /* 1196 * Shift out data. 1197 */ 1198 data = 0; 1199 reg = FXP_EEPROM_EECS; 1200 for (x = 1 << 15; x; x >>= 1) { 1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1202 DELAY(1); 1203 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1204 data |= x; 1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1206 DELAY(1); 1207 } 1208 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1209 DELAY(1); 1210 1211 return (data); 1212} 1213 1214static void 1215fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1216{ 1217 int i; 1218 1219 /* 1220 * Erase/write enable. 1221 */ 1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1223 fxp_eeprom_shiftin(sc, 0x4, 3); 1224 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1225 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1226 DELAY(1); 1227 /* 1228 * Shift in write opcode, address, data. 1229 */ 1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1231 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1232 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1233 fxp_eeprom_shiftin(sc, data, 16); 1234 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1235 DELAY(1); 1236 /* 1237 * Wait for EEPROM to finish up. 1238 */ 1239 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1240 DELAY(1); 1241 for (i = 0; i < 1000; i++) { 1242 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1243 break; 1244 DELAY(50); 1245 } 1246 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1247 DELAY(1); 1248 /* 1249 * Erase/write disable. 1250 */ 1251 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1252 fxp_eeprom_shiftin(sc, 0x4, 3); 1253 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1254 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1255 DELAY(1); 1256} 1257 1258/* 1259 * From NetBSD: 1260 * 1261 * Figure out EEPROM size. 1262 * 1263 * 559's can have either 64-word or 256-word EEPROMs, the 558 1264 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1265 * talks about the existance of 16 to 256 word EEPROMs. 1266 * 1267 * The only known sizes are 64 and 256, where the 256 version is used 1268 * by CardBus cards to store CIS information. 1269 * 1270 * The address is shifted in msb-to-lsb, and after the last 1271 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1272 * after which follows the actual data. We try to detect this zero, by 1273 * probing the data-out bit in the EEPROM control register just after 1274 * having shifted in a bit. If the bit is zero, we assume we've 1275 * shifted enough address bits. The data-out should be tri-state, 1276 * before this, which should translate to a logical one. 1277 */ 1278static void 1279fxp_autosize_eeprom(struct fxp_softc *sc) 1280{ 1281 1282 /* guess maximum size of 256 words */ 1283 sc->eeprom_size = 8; 1284 1285 /* autosize */ 1286 (void) fxp_eeprom_getword(sc, 0, 1); 1287} 1288 1289static void 1290fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1291{ 1292 int i; 1293 1294 for (i = 0; i < words; i++) 1295 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1296} 1297 1298static void 1299fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1300{ 1301 int i; 1302 1303 for (i = 0; i < words; i++) 1304 fxp_eeprom_putword(sc, offset + i, data[i]); 1305} 1306 1307static void 1308fxp_load_eeprom(struct fxp_softc *sc) 1309{ 1310 int i; 1311 uint16_t cksum; 1312 1313 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size); 1314 cksum = 0; 1315 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) 1316 cksum += sc->eeprom[i]; 1317 cksum = 0xBABA - cksum; 1318 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1]) 1319 device_printf(sc->dev, 1320 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n", 1321 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]); 1322} 1323 1324/* 1325 * Grab the softc lock and call the real fxp_start_body() routine 1326 */ 1327static void 1328fxp_start(if_t ifp) 1329{ 1330 struct fxp_softc *sc = if_getsoftc(ifp); 1331 1332 FXP_LOCK(sc); 1333 fxp_start_body(ifp); 1334 FXP_UNLOCK(sc); 1335} 1336 1337/* 1338 * Start packet transmission on the interface. 1339 * This routine must be called with the softc lock held, and is an 1340 * internal entry point only. 1341 */ 1342static void 1343fxp_start_body(if_t ifp) 1344{ 1345 struct fxp_softc *sc = if_getsoftc(ifp); 1346 struct mbuf *mb_head; 1347 int txqueued; 1348 1349 FXP_LOCK_ASSERT(sc, MA_OWNED); 1350 1351 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1352 IFF_DRV_RUNNING) 1353 return; 1354 1355 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1356 fxp_txeof(sc); 1357 /* 1358 * We're finished if there is nothing more to add to the list or if 1359 * we're all filled up with buffers to transmit. 1360 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1361 * a NOP command when needed. 1362 */ 1363 txqueued = 0; 1364 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) { 1365 1366 /* 1367 * Grab a packet to transmit. 1368 */ 1369 mb_head = if_dequeue(ifp); 1370 if (mb_head == NULL) 1371 break; 1372 1373 if (fxp_encap(sc, &mb_head)) { 1374 if (mb_head == NULL) 1375 break; 1376 if_sendq_prepend(ifp, mb_head); 1377 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1378 } 1379 txqueued++; 1380 /* 1381 * Pass packet to bpf if there is a listener. 1382 */ 1383 if_bpfmtap(ifp, mb_head); 1384 } 1385 1386 /* 1387 * We're finished. If we added to the list, issue a RESUME to get DMA 1388 * going again if suspended. 1389 */ 1390 if (txqueued > 0) { 1391 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1393 fxp_scb_wait(sc); 1394 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1395 /* 1396 * Set a 5 second timer just in case we don't hear 1397 * from the card again. 1398 */ 1399 sc->watchdog_timer = 5; 1400 } 1401} 1402 1403static int 1404fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1405{ 1406 if_t ifp; 1407 struct mbuf *m; 1408 struct fxp_tx *txp; 1409 struct fxp_cb_tx *cbp; 1410 struct tcphdr *tcp; 1411 bus_dma_segment_t segs[FXP_NTXSEG]; 1412 int error, i, nseg, tcp_payload; 1413 1414 FXP_LOCK_ASSERT(sc, MA_OWNED); 1415 ifp = sc->ifp; 1416 1417 tcp_payload = 0; 1418 tcp = NULL; 1419 /* 1420 * Get pointer to next available tx desc. 1421 */ 1422 txp = sc->fxp_desc.tx_last->tx_next; 1423 1424 /* 1425 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1426 * Ethernet Controller Family Open Source Software 1427 * Developer Manual says: 1428 * Using software parsing is only allowed with legal 1429 * TCP/IP or UDP/IP packets. 1430 * ... 1431 * For all other datagrams, hardware parsing must 1432 * be used. 1433 * Software parsing appears to truncate ICMP and 1434 * fragmented UDP packets that contain one to three 1435 * bytes in the second (and final) mbuf of the packet. 1436 */ 1437 if (sc->flags & FXP_FLAG_EXT_RFA) 1438 txp->tx_cb->ipcb_ip_activation_high = 1439 FXP_IPCB_HARDWAREPARSING_ENABLE; 1440 1441 m = *m_head; 1442 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1443 /* 1444 * 82550/82551 requires ethernet/IP/TCP headers must be 1445 * contained in the first active transmit buffer. 1446 */ 1447 struct ether_header *eh; 1448 struct ip *ip; 1449 uint32_t ip_off, poff; 1450 1451 if (M_WRITABLE(*m_head) == 0) { 1452 /* Get a writable copy. */ 1453 m = m_dup(*m_head, M_NOWAIT); 1454 m_freem(*m_head); 1455 if (m == NULL) { 1456 *m_head = NULL; 1457 return (ENOBUFS); 1458 } 1459 *m_head = m; 1460 } 1461 ip_off = sizeof(struct ether_header); 1462 m = m_pullup(*m_head, ip_off); 1463 if (m == NULL) { 1464 *m_head = NULL; 1465 return (ENOBUFS); 1466 } 1467 eh = mtod(m, struct ether_header *); 1468 /* Check the existence of VLAN tag. */ 1469 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1470 ip_off = sizeof(struct ether_vlan_header); 1471 m = m_pullup(m, ip_off); 1472 if (m == NULL) { 1473 *m_head = NULL; 1474 return (ENOBUFS); 1475 } 1476 } 1477 m = m_pullup(m, ip_off + sizeof(struct ip)); 1478 if (m == NULL) { 1479 *m_head = NULL; 1480 return (ENOBUFS); 1481 } 1482 ip = (struct ip *)(mtod(m, char *) + ip_off); 1483 poff = ip_off + (ip->ip_hl << 2); 1484 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1485 if (m == NULL) { 1486 *m_head = NULL; 1487 return (ENOBUFS); 1488 } 1489 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1490 m = m_pullup(m, poff + (tcp->th_off << 2)); 1491 if (m == NULL) { 1492 *m_head = NULL; 1493 return (ENOBUFS); 1494 } 1495 1496 /* 1497 * Since 82550/82551 doesn't modify IP length and pseudo 1498 * checksum in the first frame driver should compute it. 1499 */ 1500 ip = (struct ip *)(mtod(m, char *) + ip_off); 1501 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1502 ip->ip_sum = 0; 1503 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1504 (tcp->th_off << 2)); 1505 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1506 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1507 m->m_pkthdr.tso_segsz)); 1508 /* Compute total TCP payload. */ 1509 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1510 tcp_payload -= tcp->th_off << 2; 1511 *m_head = m; 1512 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1513 /* 1514 * Deal with TCP/IP checksum offload. Note that 1515 * in order for TCP checksum offload to work, 1516 * the pseudo header checksum must have already 1517 * been computed and stored in the checksum field 1518 * in the TCP header. The stack should have 1519 * already done this for us. 1520 */ 1521 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1522 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1523 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1524 1525#ifdef FXP_IP_CSUM_WAR 1526 /* 1527 * XXX The 82550 chip appears to have trouble 1528 * dealing with IP header checksums in very small 1529 * datagrams, namely fragments from 1 to 3 bytes 1530 * in size. For example, say you want to transmit 1531 * a UDP packet of 1473 bytes. The packet will be 1532 * fragmented over two IP datagrams, the latter 1533 * containing only one byte of data. The 82550 will 1534 * botch the header checksum on the 1-byte fragment. 1535 * As long as the datagram contains 4 or more bytes 1536 * of data, you're ok. 1537 * 1538 * The following code attempts to work around this 1539 * problem: if the datagram is less than 38 bytes 1540 * in size (14 bytes ether header, 20 bytes IP header, 1541 * plus 4 bytes of data), we punt and compute the IP 1542 * header checksum by hand. This workaround doesn't 1543 * work very well, however, since it can be fooled 1544 * by things like VLAN tags and IP options that make 1545 * the header sizes/offsets vary. 1546 */ 1547 1548 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1549 if (m->m_pkthdr.len < 38) { 1550 struct ip *ip; 1551 m->m_data += ETHER_HDR_LEN; 1552 ip = mtod(m, struct ip *); 1553 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1554 m->m_data -= ETHER_HDR_LEN; 1555 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1556 } else { 1557 txp->tx_cb->ipcb_ip_activation_high = 1558 FXP_IPCB_HARDWAREPARSING_ENABLE; 1559 txp->tx_cb->ipcb_ip_schedule |= 1560 FXP_IPCB_IP_CHECKSUM_ENABLE; 1561 } 1562 } 1563#endif 1564 } 1565 1566 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1567 segs, &nseg, 0); 1568 if (error == EFBIG) { 1569 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg); 1570 if (m == NULL) { 1571 m_freem(*m_head); 1572 *m_head = NULL; 1573 return (ENOMEM); 1574 } 1575 *m_head = m; 1576 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1577 *m_head, segs, &nseg, 0); 1578 if (error != 0) { 1579 m_freem(*m_head); 1580 *m_head = NULL; 1581 return (ENOMEM); 1582 } 1583 } else if (error != 0) 1584 return (error); 1585 if (nseg == 0) { 1586 m_freem(*m_head); 1587 *m_head = NULL; 1588 return (EIO); 1589 } 1590 1591 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1592 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1593 1594 cbp = txp->tx_cb; 1595 for (i = 0; i < nseg; i++) { 1596 /* 1597 * If this is an 82550/82551, then we're using extended 1598 * TxCBs _and_ we're using checksum offload. This means 1599 * that the TxCB is really an IPCB. One major difference 1600 * between the two is that with plain extended TxCBs, 1601 * the bottom half of the TxCB contains two entries from 1602 * the TBD array, whereas IPCBs contain just one entry: 1603 * one entry (8 bytes) has been sacrificed for the TCP/IP 1604 * checksum offload control bits. So to make things work 1605 * right, we have to start filling in the TBD array 1606 * starting from a different place depending on whether 1607 * the chip is an 82550/82551 or not. 1608 */ 1609 if (sc->flags & FXP_FLAG_EXT_RFA) { 1610 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1611 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1612 } else { 1613 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1614 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1615 } 1616 } 1617 if (sc->flags & FXP_FLAG_EXT_RFA) { 1618 /* Configure dynamic TBD for 82550/82551. */ 1619 cbp->tbd_number = 0xFF; 1620 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1621 } else 1622 cbp->tbd_number = nseg; 1623 /* Configure TSO. */ 1624 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1625 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1626 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1627 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1628 FXP_IPCB_IP_CHECKSUM_ENABLE | 1629 FXP_IPCB_TCP_PACKET | 1630 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1631 } 1632 /* Configure VLAN hardware tag insertion. */ 1633 if ((m->m_flags & M_VLANTAG) != 0) { 1634 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1635 txp->tx_cb->ipcb_ip_activation_high |= 1636 FXP_IPCB_INSERTVLAN_ENABLE; 1637 } 1638 1639 txp->tx_mbuf = m; 1640 txp->tx_cb->cb_status = 0; 1641 txp->tx_cb->byte_count = 0; 1642 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1643 txp->tx_cb->cb_command = 1644 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1645 FXP_CB_COMMAND_S); 1646 else 1647 txp->tx_cb->cb_command = 1648 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1649 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1650 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1651 txp->tx_cb->tx_threshold = tx_threshold; 1652 1653 /* 1654 * Advance the end of list forward. 1655 */ 1656 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1657 sc->fxp_desc.tx_last = txp; 1658 1659 /* 1660 * Advance the beginning of the list forward if there are 1661 * no other packets queued (when nothing is queued, tx_first 1662 * sits on the last TxCB that was sent out). 1663 */ 1664 if (sc->tx_queued == 0) 1665 sc->fxp_desc.tx_first = txp; 1666 1667 sc->tx_queued++; 1668 1669 return (0); 1670} 1671 1672#ifdef DEVICE_POLLING 1673static poll_handler_drv_t fxp_poll; 1674 1675static int 1676fxp_poll(if_t ifp, enum poll_cmd cmd, int count) 1677{ 1678 struct fxp_softc *sc = if_getsoftc(ifp); 1679 uint8_t statack; 1680 int rx_npkts = 0; 1681 1682 FXP_LOCK(sc); 1683 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1684 FXP_UNLOCK(sc); 1685 return (rx_npkts); 1686 } 1687 1688 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1689 FXP_SCB_STATACK_FR; 1690 if (cmd == POLL_AND_CHECK_STATUS) { 1691 uint8_t tmp; 1692 1693 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1694 if (tmp == 0xff || tmp == 0) { 1695 FXP_UNLOCK(sc); 1696 return (rx_npkts); /* nothing to do */ 1697 } 1698 tmp &= ~statack; 1699 /* ack what we can */ 1700 if (tmp != 0) 1701 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1702 statack |= tmp; 1703 } 1704 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1705 FXP_UNLOCK(sc); 1706 return (rx_npkts); 1707} 1708#endif /* DEVICE_POLLING */ 1709 1710/* 1711 * Process interface interrupts. 1712 */ 1713static void 1714fxp_intr(void *xsc) 1715{ 1716 struct fxp_softc *sc = xsc; 1717 if_t ifp = sc->ifp; 1718 uint8_t statack; 1719 1720 FXP_LOCK(sc); 1721 if (sc->suspended) { 1722 FXP_UNLOCK(sc); 1723 return; 1724 } 1725 1726#ifdef DEVICE_POLLING 1727 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1728 FXP_UNLOCK(sc); 1729 return; 1730 } 1731#endif 1732 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1733 /* 1734 * It should not be possible to have all bits set; the 1735 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1736 * all bits are set, this may indicate that the card has 1737 * been physically ejected, so ignore it. 1738 */ 1739 if (statack == 0xff) { 1740 FXP_UNLOCK(sc); 1741 return; 1742 } 1743 1744 /* 1745 * First ACK all the interrupts in this pass. 1746 */ 1747 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1748 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1749 fxp_intr_body(sc, ifp, statack, -1); 1750 } 1751 FXP_UNLOCK(sc); 1752} 1753 1754static void 1755fxp_txeof(struct fxp_softc *sc) 1756{ 1757 if_t ifp; 1758 struct fxp_tx *txp; 1759 1760 ifp = sc->ifp; 1761 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1762 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1763 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1764 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1765 txp = txp->tx_next) { 1766 if (txp->tx_mbuf != NULL) { 1767 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1768 BUS_DMASYNC_POSTWRITE); 1769 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1770 m_freem(txp->tx_mbuf); 1771 txp->tx_mbuf = NULL; 1772 /* clear this to reset csum offload bits */ 1773 txp->tx_cb->tbd[0].tb_addr = 0; 1774 } 1775 sc->tx_queued--; 1776 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1777 } 1778 sc->fxp_desc.tx_first = txp; 1779 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1781 if (sc->tx_queued == 0) 1782 sc->watchdog_timer = 0; 1783} 1784 1785static void 1786fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m, 1787 uint16_t status, int pos) 1788{ 1789 struct ether_header *eh; 1790 struct ip *ip; 1791 struct udphdr *uh; 1792 int32_t hlen, len, pktlen, temp32; 1793 uint16_t csum, *opts; 1794 1795 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1796 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1797 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1798 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1799 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1800 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1801 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1802 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1803 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1804 CSUM_PSEUDO_HDR; 1805 m->m_pkthdr.csum_data = 0xffff; 1806 } 1807 } 1808 return; 1809 } 1810 1811 pktlen = m->m_pkthdr.len; 1812 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1813 return; 1814 eh = mtod(m, struct ether_header *); 1815 if (eh->ether_type != htons(ETHERTYPE_IP)) 1816 return; 1817 ip = (struct ip *)(eh + 1); 1818 if (ip->ip_v != IPVERSION) 1819 return; 1820 1821 hlen = ip->ip_hl << 2; 1822 pktlen -= sizeof(struct ether_header); 1823 if (hlen < sizeof(struct ip)) 1824 return; 1825 if (ntohs(ip->ip_len) < hlen) 1826 return; 1827 if (ntohs(ip->ip_len) != pktlen) 1828 return; 1829 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1830 return; /* can't handle fragmented packet */ 1831 1832 switch (ip->ip_p) { 1833 case IPPROTO_TCP: 1834 if (pktlen < (hlen + sizeof(struct tcphdr))) 1835 return; 1836 break; 1837 case IPPROTO_UDP: 1838 if (pktlen < (hlen + sizeof(struct udphdr))) 1839 return; 1840 uh = (struct udphdr *)((caddr_t)ip + hlen); 1841 if (uh->uh_sum == 0) 1842 return; /* no checksum */ 1843 break; 1844 default: 1845 return; 1846 } 1847 /* Extract computed checksum. */ 1848 csum = be16dec(mtod(m, char *) + pos); 1849 /* checksum fixup for IP options */ 1850 len = hlen - sizeof(struct ip); 1851 if (len > 0) { 1852 opts = (uint16_t *)(ip + 1); 1853 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1854 temp32 = csum - *opts; 1855 temp32 = (temp32 >> 16) + (temp32 & 65535); 1856 csum = temp32 & 65535; 1857 } 1858 } 1859 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1860 m->m_pkthdr.csum_data = csum; 1861} 1862 1863static int 1864fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack, 1865 int count) 1866{ 1867 struct mbuf *m; 1868 struct fxp_rx *rxp; 1869 struct fxp_rfa *rfa; 1870 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1871 int rx_npkts; 1872 uint16_t status; 1873 1874 rx_npkts = 0; 1875 FXP_LOCK_ASSERT(sc, MA_OWNED); 1876 1877 if (rnr) 1878 sc->rnr++; 1879#ifdef DEVICE_POLLING 1880 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1881 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1882 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1883 rnr = 1; 1884 } 1885#endif 1886 1887 /* 1888 * Free any finished transmit mbuf chains. 1889 * 1890 * Handle the CNA event likt a CXTNO event. It used to 1891 * be that this event (control unit not ready) was not 1892 * encountered, but it is now with the SMPng modifications. 1893 * The exact sequence of events that occur when the interface 1894 * is brought up are different now, and if this event 1895 * goes unhandled, the configuration/rxfilter setup sequence 1896 * can stall for several seconds. The result is that no 1897 * packets go out onto the wire for about 5 to 10 seconds 1898 * after the interface is ifconfig'ed for the first time. 1899 */ 1900 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1901 fxp_txeof(sc); 1902 1903 /* 1904 * Try to start more packets transmitting. 1905 */ 1906 if (!if_sendq_empty(ifp)) 1907 fxp_start_body(ifp); 1908 1909 /* 1910 * Just return if nothing happened on the receive side. 1911 */ 1912 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1913 return (rx_npkts); 1914 1915 /* 1916 * Process receiver interrupts. If a no-resource (RNR) 1917 * condition exists, get whatever packets we can and 1918 * re-start the receiver. 1919 * 1920 * When using polling, we do not process the list to completion, 1921 * so when we get an RNR interrupt we must defer the restart 1922 * until we hit the last buffer with the C bit set. 1923 * If we run out of cycles and rfa_headm has the C bit set, 1924 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1925 * that the info will be used in the subsequent polling cycle. 1926 */ 1927 for (;;) { 1928 rxp = sc->fxp_desc.rx_head; 1929 m = rxp->rx_mbuf; 1930 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1931 RFA_ALIGNMENT_FUDGE); 1932 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1934 1935#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1936 if (count >= 0 && count-- == 0) { 1937 if (rnr) { 1938 /* Defer RNR processing until the next time. */ 1939 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1940 rnr = 0; 1941 } 1942 break; 1943 } 1944#endif /* DEVICE_POLLING */ 1945 1946 status = le16toh(rfa->rfa_status); 1947 if ((status & FXP_RFA_STATUS_C) == 0) 1948 break; 1949 1950 if ((status & FXP_RFA_STATUS_RNR) != 0) 1951 rnr++; 1952 /* 1953 * Advance head forward. 1954 */ 1955 sc->fxp_desc.rx_head = rxp->rx_next; 1956 1957 /* 1958 * Add a new buffer to the receive chain. 1959 * If this fails, the old buffer is recycled 1960 * instead. 1961 */ 1962 if (fxp_new_rfabuf(sc, rxp) == 0) { 1963 int total_len; 1964 1965 /* 1966 * Fetch packet length (the top 2 bits of 1967 * actual_size are flags set by the controller 1968 * upon completion), and drop the packet in case 1969 * of bogus length or CRC errors. 1970 */ 1971 total_len = le16toh(rfa->actual_size) & 0x3fff; 1972 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1973 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1974 /* Adjust for appended checksum bytes. */ 1975 total_len -= 2; 1976 } 1977 if (total_len < (int)sizeof(struct ether_header) || 1978 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1979 sc->rfa_size) || 1980 status & (FXP_RFA_STATUS_CRC | 1981 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1982 m_freem(m); 1983 fxp_add_rfabuf(sc, rxp); 1984 continue; 1985 } 1986 1987 m->m_pkthdr.len = m->m_len = total_len; 1988 if_setrcvif(m, ifp); 1989 1990 /* Do IP checksum checking. */ 1991 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1992 fxp_rxcsum(sc, ifp, m, status, total_len); 1993 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1994 (status & FXP_RFA_STATUS_VLAN) != 0) { 1995 m->m_pkthdr.ether_vtag = 1996 ntohs(rfa->rfax_vlan_id); 1997 m->m_flags |= M_VLANTAG; 1998 } 1999 /* 2000 * Drop locks before calling if_input() since it 2001 * may re-enter fxp_start() in the netisr case. 2002 * This would result in a lock reversal. Better 2003 * performance might be obtained by chaining all 2004 * packets received, dropping the lock, and then 2005 * calling if_input() on each one. 2006 */ 2007 FXP_UNLOCK(sc); 2008 if_input(ifp, m); 2009 FXP_LOCK(sc); 2010 rx_npkts++; 2011 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2012 return (rx_npkts); 2013 } else { 2014 /* Reuse RFA and loaded DMA map. */ 2015 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2016 fxp_discard_rfabuf(sc, rxp); 2017 } 2018 fxp_add_rfabuf(sc, rxp); 2019 } 2020 if (rnr) { 2021 fxp_scb_wait(sc); 2022 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2023 sc->fxp_desc.rx_head->rx_addr); 2024 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2025 } 2026 return (rx_npkts); 2027} 2028 2029static void 2030fxp_update_stats(struct fxp_softc *sc) 2031{ 2032 if_t ifp = sc->ifp; 2033 struct fxp_stats *sp = sc->fxp_stats; 2034 struct fxp_hwstats *hsp; 2035 uint32_t *status; 2036 2037 FXP_LOCK_ASSERT(sc, MA_OWNED); 2038 2039 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2041 /* Update statistical counters. */ 2042 if (sc->revision >= FXP_REV_82559_A0) 2043 status = &sp->completion_status; 2044 else if (sc->revision >= FXP_REV_82558_A4) 2045 status = (uint32_t *)&sp->tx_tco; 2046 else 2047 status = &sp->tx_pause; 2048 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2049 hsp = &sc->fxp_hwstats; 2050 hsp->tx_good += le32toh(sp->tx_good); 2051 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2052 hsp->tx_latecols += le32toh(sp->tx_latecols); 2053 hsp->tx_underruns += le32toh(sp->tx_underruns); 2054 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2055 hsp->tx_deffered += le32toh(sp->tx_deffered); 2056 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2057 hsp->tx_multiple_collisions += 2058 le32toh(sp->tx_multiple_collisions); 2059 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2060 hsp->rx_good += le32toh(sp->rx_good); 2061 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2062 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2063 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2064 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2065 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2066 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2067 hsp->tx_pause += le32toh(sp->tx_pause); 2068 hsp->rx_pause += le32toh(sp->rx_pause); 2069 hsp->rx_controls += le32toh(sp->rx_controls); 2070 hsp->tx_tco += le16toh(sp->tx_tco); 2071 hsp->rx_tco += le16toh(sp->rx_tco); 2072 2073 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good)); 2074 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2075 le32toh(sp->tx_total_collisions)); 2076 if (sp->rx_good) { 2077 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 2078 le32toh(sp->rx_good)); 2079 sc->rx_idle_secs = 0; 2080 } else if (sc->flags & FXP_FLAG_RXBUG) { 2081 /* 2082 * Receiver's been idle for another second. 2083 */ 2084 sc->rx_idle_secs++; 2085 } 2086 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2087 le32toh(sp->rx_crc_errors) + 2088 le32toh(sp->rx_alignment_errors) + 2089 le32toh(sp->rx_rnr_errors) + 2090 le32toh(sp->rx_overrun_errors)); 2091 /* 2092 * If any transmit underruns occured, bump up the transmit 2093 * threshold by another 512 bytes (64 * 8). 2094 */ 2095 if (sp->tx_underruns) { 2096 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2097 le32toh(sp->tx_underruns)); 2098 if (tx_threshold < 192) 2099 tx_threshold += 64; 2100 } 2101 *status = 0; 2102 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2104 } 2105} 2106 2107/* 2108 * Update packet in/out/collision statistics. The i82557 doesn't 2109 * allow you to access these counters without doing a fairly 2110 * expensive DMA to get _all_ of the statistics it maintains, so 2111 * we do this operation here only once per second. The statistics 2112 * counters in the kernel are updated from the previous dump-stats 2113 * DMA and then a new dump-stats DMA is started. The on-chip 2114 * counters are zeroed when the DMA completes. If we can't start 2115 * the DMA immediately, we don't wait - we just prepare to read 2116 * them again next time. 2117 */ 2118static void 2119fxp_tick(void *xsc) 2120{ 2121 struct fxp_softc *sc = xsc; 2122 if_t ifp = sc->ifp; 2123 2124 FXP_LOCK_ASSERT(sc, MA_OWNED); 2125 2126 /* Update statistical counters. */ 2127 fxp_update_stats(sc); 2128 2129 /* 2130 * Release any xmit buffers that have completed DMA. This isn't 2131 * strictly necessary to do here, but it's advantagous for mbufs 2132 * with external storage to be released in a timely manner rather 2133 * than being defered for a potentially long time. This limits 2134 * the delay to a maximum of one second. 2135 */ 2136 fxp_txeof(sc); 2137 2138 /* 2139 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2140 * then assume the receiver has locked up and attempt to clear 2141 * the condition by reprogramming the multicast filter. This is 2142 * a work-around for a bug in the 82557 where the receiver locks 2143 * up if it gets certain types of garbage in the syncronization 2144 * bits prior to the packet header. This bug is supposed to only 2145 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2146 * mode as well (perhaps due to a 10/100 speed transition). 2147 */ 2148 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2149 sc->rx_idle_secs = 0; 2150 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2151 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2152 fxp_init_body(sc, 1); 2153 } 2154 return; 2155 } 2156 /* 2157 * If there is no pending command, start another stats 2158 * dump. Otherwise punt for now. 2159 */ 2160 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2161 /* 2162 * Start another stats dump. 2163 */ 2164 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2165 } 2166 if (sc->miibus != NULL) 2167 mii_tick(device_get_softc(sc->miibus)); 2168 2169 /* 2170 * Check that chip hasn't hung. 2171 */ 2172 fxp_watchdog(sc); 2173 2174 /* 2175 * Schedule another timeout one second from now. 2176 */ 2177 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2178} 2179 2180/* 2181 * Stop the interface. Cancels the statistics updater and resets 2182 * the interface. 2183 */ 2184static void 2185fxp_stop(struct fxp_softc *sc) 2186{ 2187 if_t ifp = sc->ifp; 2188 struct fxp_tx *txp; 2189 int i; 2190 2191 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2192 sc->watchdog_timer = 0; 2193 2194 /* 2195 * Cancel stats updater. 2196 */ 2197 callout_stop(&sc->stat_ch); 2198 2199 /* 2200 * Preserve PCI configuration, configure, IA/multicast 2201 * setup and put RU and CU into idle state. 2202 */ 2203 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2204 DELAY(50); 2205 /* Disable interrupts. */ 2206 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2207 2208 fxp_update_stats(sc); 2209 2210 /* 2211 * Release any xmit buffers. 2212 */ 2213 txp = sc->fxp_desc.tx_list; 2214 if (txp != NULL) { 2215 for (i = 0; i < FXP_NTXCB; i++) { 2216 if (txp[i].tx_mbuf != NULL) { 2217 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2218 BUS_DMASYNC_POSTWRITE); 2219 bus_dmamap_unload(sc->fxp_txmtag, 2220 txp[i].tx_map); 2221 m_freem(txp[i].tx_mbuf); 2222 txp[i].tx_mbuf = NULL; 2223 /* clear this to reset csum offload bits */ 2224 txp[i].tx_cb->tbd[0].tb_addr = 0; 2225 } 2226 } 2227 } 2228 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2230 sc->tx_queued = 0; 2231} 2232 2233/* 2234 * Watchdog/transmission transmit timeout handler. Called when a 2235 * transmission is started on the interface, but no interrupt is 2236 * received before the timeout. This usually indicates that the 2237 * card has wedged for some reason. 2238 */ 2239static void 2240fxp_watchdog(struct fxp_softc *sc) 2241{ 2242 if_t ifp = sc->ifp; 2243 2244 FXP_LOCK_ASSERT(sc, MA_OWNED); 2245 2246 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2247 return; 2248 2249 device_printf(sc->dev, "device timeout\n"); 2250 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2251 2252 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2253 fxp_init_body(sc, 1); 2254} 2255 2256/* 2257 * Acquire locks and then call the real initialization function. This 2258 * is necessary because ether_ioctl() calls if_init() and this would 2259 * result in mutex recursion if the mutex was held. 2260 */ 2261static void 2262fxp_init(void *xsc) 2263{ 2264 struct fxp_softc *sc = xsc; 2265 2266 FXP_LOCK(sc); 2267 fxp_init_body(sc, 1); 2268 FXP_UNLOCK(sc); 2269} 2270 2271/* 2272 * Perform device initialization. This routine must be called with the 2273 * softc lock held. 2274 */ 2275static void 2276fxp_init_body(struct fxp_softc *sc, int setmedia) 2277{ 2278 if_t ifp = sc->ifp; 2279 struct mii_data *mii; 2280 struct fxp_cb_config *cbp; 2281 struct fxp_cb_ias *cb_ias; 2282 struct fxp_cb_tx *tcbp; 2283 struct fxp_tx *txp; 2284 int i, prm; 2285 2286 FXP_LOCK_ASSERT(sc, MA_OWNED); 2287 2288 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2289 return; 2290 2291 /* 2292 * Cancel any pending I/O 2293 */ 2294 fxp_stop(sc); 2295 2296 /* 2297 * Issue software reset, which also unloads the microcode. 2298 */ 2299 sc->flags &= ~FXP_FLAG_UCODE; 2300 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2301 DELAY(50); 2302 2303 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0; 2304 2305 /* 2306 * Initialize base of CBL and RFA memory. Loading with zero 2307 * sets it up for regular linear addressing. 2308 */ 2309 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2311 2312 fxp_scb_wait(sc); 2313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2314 2315 /* 2316 * Initialize base of dump-stats buffer. 2317 */ 2318 fxp_scb_wait(sc); 2319 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2320 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2322 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2323 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2324 2325 /* 2326 * Attempt to load microcode if requested. 2327 * For ICH based controllers do not load microcode. 2328 */ 2329 if (sc->ident->ich == 0) { 2330 if (if_getflags(ifp) & IFF_LINK0 && 2331 (sc->flags & FXP_FLAG_UCODE) == 0) 2332 fxp_load_ucode(sc); 2333 } 2334 2335 /* 2336 * Set IFF_ALLMULTI status. It's needed in configure action 2337 * command. 2338 */ 2339 fxp_mc_addrs(sc); 2340 2341 /* 2342 * We temporarily use memory that contains the TxCB list to 2343 * construct the config CB. The TxCB list memory is rebuilt 2344 * later. 2345 */ 2346 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2347 2348 /* 2349 * This bcopy is kind of disgusting, but there are a bunch of must be 2350 * zero and must be one bits in this structure and this is the easiest 2351 * way to initialize them all to proper values. 2352 */ 2353 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2354 2355 cbp->cb_status = 0; 2356 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2357 FXP_CB_COMMAND_EL); 2358 cbp->link_addr = 0xffffffff; /* (no) next command */ 2359 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2360 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2361 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2362 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2363 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2364 cbp->type_enable = 0; /* actually reserved */ 2365 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2366 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2367 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2368 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2369 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2370 cbp->late_scb = 0; /* (don't) defer SCB update */ 2371 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2372 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2373 cbp->ci_int = 1; /* interrupt on CU idle */ 2374 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2375 cbp->ext_stats_dis = 1; /* disable extended counters */ 2376 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2377 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2378 cbp->disc_short_rx = !prm; /* discard short packets */ 2379 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2380 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2381 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2382 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2383 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2384 cbp->csma_dis = 0; /* (don't) disable link */ 2385 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2386 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0; 2387 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2388 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2389 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2390 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2391 cbp->nsai = 1; /* (don't) disable source addr insert */ 2392 cbp->preamble_length = 2; /* (7 byte) preamble */ 2393 cbp->loopback = 0; /* (don't) loopback */ 2394 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2395 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2396 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2397 cbp->promiscuous = prm; /* promiscuous mode */ 2398 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2399 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2400 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2401 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2402 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2403 2404 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2405 cbp->padding = 1; /* (do) pad short tx packets */ 2406 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2407 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2408 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2409 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2410 cbp->force_fdx = 0; /* (don't) force full duplex */ 2411 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2412 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2413 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm; 2414 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2415 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2416 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2417 2418 if (sc->revision == FXP_REV_82557) { 2419 /* 2420 * The 82557 has no hardware flow control, the values 2421 * below are the defaults for the chip. 2422 */ 2423 cbp->fc_delay_lsb = 0; 2424 cbp->fc_delay_msb = 0x40; 2425 cbp->pri_fc_thresh = 3; 2426 cbp->tx_fc_dis = 0; 2427 cbp->rx_fc_restop = 0; 2428 cbp->rx_fc_restart = 0; 2429 cbp->fc_filter = 0; 2430 cbp->pri_fc_loc = 1; 2431 } else { 2432 /* Set pause RX FIFO threshold to 1KB. */ 2433 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2434 /* Set pause time. */ 2435 cbp->fc_delay_lsb = 0xff; 2436 cbp->fc_delay_msb = 0xff; 2437 cbp->pri_fc_thresh = 3; 2438 mii = device_get_softc(sc->miibus); 2439 if ((IFM_OPTIONS(mii->mii_media_active) & 2440 IFM_ETH_TXPAUSE) != 0) 2441 /* enable transmit FC */ 2442 cbp->tx_fc_dis = 0; 2443 else 2444 /* disable transmit FC */ 2445 cbp->tx_fc_dis = 1; 2446 if ((IFM_OPTIONS(mii->mii_media_active) & 2447 IFM_ETH_RXPAUSE) != 0) { 2448 /* enable FC restart/restop frames */ 2449 cbp->rx_fc_restart = 1; 2450 cbp->rx_fc_restop = 1; 2451 } else { 2452 /* disable FC restart/restop frames */ 2453 cbp->rx_fc_restart = 0; 2454 cbp->rx_fc_restop = 0; 2455 } 2456 cbp->fc_filter = !prm; /* drop FC frames to host */ 2457 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2458 } 2459 2460 /* Enable 82558 and 82559 extended statistics functionality. */ 2461 if (sc->revision >= FXP_REV_82558_A4) { 2462 if (sc->revision >= FXP_REV_82559_A0) { 2463 /* 2464 * Extend configuration table size to 32 2465 * to include TCO configuration. 2466 */ 2467 cbp->byte_count = 32; 2468 cbp->ext_stats_dis = 1; 2469 /* Enable TCO stats. */ 2470 cbp->tno_int_or_tco_en = 1; 2471 cbp->gamla_rx = 1; 2472 } else 2473 cbp->ext_stats_dis = 0; 2474 } 2475 2476 /* 2477 * Start the config command/DMA. 2478 */ 2479 fxp_scb_wait(sc); 2480 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2481 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2482 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2483 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2484 /* ...and wait for it to complete. */ 2485 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2486 2487 /* 2488 * Now initialize the station address. Temporarily use the TxCB 2489 * memory area like we did above for the config CB. 2490 */ 2491 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2492 cb_ias->cb_status = 0; 2493 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2494 cb_ias->link_addr = 0xffffffff; 2495 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2496 2497 /* 2498 * Start the IAS (Individual Address Setup) command/DMA. 2499 */ 2500 fxp_scb_wait(sc); 2501 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2502 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2503 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2504 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2505 /* ...and wait for it to complete. */ 2506 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2507 2508 /* 2509 * Initialize the multicast address list. 2510 */ 2511 fxp_mc_setup(sc); 2512 2513 /* 2514 * Initialize transmit control block (TxCB) list. 2515 */ 2516 txp = sc->fxp_desc.tx_list; 2517 tcbp = sc->fxp_desc.cbl_list; 2518 bzero(tcbp, FXP_TXCB_SZ); 2519 for (i = 0; i < FXP_NTXCB; i++) { 2520 txp[i].tx_mbuf = NULL; 2521 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2522 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2523 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2524 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2525 if (sc->flags & FXP_FLAG_EXT_TXCB) 2526 tcbp[i].tbd_array_addr = 2527 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2528 else 2529 tcbp[i].tbd_array_addr = 2530 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2531 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2532 } 2533 /* 2534 * Set the suspend flag on the first TxCB and start the control 2535 * unit. It will execute the NOP and then suspend. 2536 */ 2537 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2538 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2540 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2541 sc->tx_queued = 1; 2542 2543 fxp_scb_wait(sc); 2544 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2545 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2546 2547 /* 2548 * Initialize receiver buffer area - RFA. 2549 */ 2550 fxp_scb_wait(sc); 2551 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2552 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2553 2554 if (sc->miibus != NULL && setmedia != 0) 2555 mii_mediachg(device_get_softc(sc->miibus)); 2556 2557 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2558 2559 /* 2560 * Enable interrupts. 2561 */ 2562#ifdef DEVICE_POLLING 2563 /* 2564 * ... but only do that if we are not polling. And because (presumably) 2565 * the default is interrupts on, we need to disable them explicitly! 2566 */ 2567 if (if_getcapenable(ifp) & IFCAP_POLLING ) 2568 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2569 else 2570#endif /* DEVICE_POLLING */ 2571 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2572 2573 /* 2574 * Start stats updater. 2575 */ 2576 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2577} 2578 2579static int 2580fxp_serial_ifmedia_upd(if_t ifp) 2581{ 2582 2583 return (0); 2584} 2585 2586static void 2587fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2588{ 2589 2590 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2591} 2592 2593/* 2594 * Change media according to request. 2595 */ 2596static int 2597fxp_ifmedia_upd(if_t ifp) 2598{ 2599 struct fxp_softc *sc = if_getsoftc(ifp); 2600 struct mii_data *mii; 2601 struct mii_softc *miisc; 2602 2603 mii = device_get_softc(sc->miibus); 2604 FXP_LOCK(sc); 2605 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2606 PHY_RESET(miisc); 2607 mii_mediachg(mii); 2608 FXP_UNLOCK(sc); 2609 return (0); 2610} 2611 2612/* 2613 * Notify the world which media we're using. 2614 */ 2615static void 2616fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2617{ 2618 struct fxp_softc *sc = if_getsoftc(ifp); 2619 struct mii_data *mii; 2620 2621 mii = device_get_softc(sc->miibus); 2622 FXP_LOCK(sc); 2623 mii_pollstat(mii); 2624 ifmr->ifm_active = mii->mii_media_active; 2625 ifmr->ifm_status = mii->mii_media_status; 2626 FXP_UNLOCK(sc); 2627} 2628 2629/* 2630 * Add a buffer to the end of the RFA buffer list. 2631 * Return 0 if successful, 1 for failure. A failure results in 2632 * reusing the RFA buffer. 2633 * The RFA struct is stuck at the beginning of mbuf cluster and the 2634 * data pointer is fixed up to point just past it. 2635 */ 2636static int 2637fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2638{ 2639 struct mbuf *m; 2640 struct fxp_rfa *rfa; 2641 bus_dmamap_t tmp_map; 2642 int error; 2643 2644 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2645 if (m == NULL) 2646 return (ENOBUFS); 2647 2648 /* 2649 * Move the data pointer up so that the incoming data packet 2650 * will be 32-bit aligned. 2651 */ 2652 m->m_data += RFA_ALIGNMENT_FUDGE; 2653 2654 /* 2655 * Get a pointer to the base of the mbuf cluster and move 2656 * data start past it. 2657 */ 2658 rfa = mtod(m, struct fxp_rfa *); 2659 m->m_data += sc->rfa_size; 2660 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2661 2662 rfa->rfa_status = 0; 2663 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2664 rfa->actual_size = 0; 2665 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2666 sc->rfa_size; 2667 2668 /* 2669 * Initialize the rest of the RFA. Note that since the RFA 2670 * is misaligned, we cannot store values directly. We're thus 2671 * using the le32enc() function which handles endianness and 2672 * is also alignment-safe. 2673 */ 2674 le32enc(&rfa->link_addr, 0xffffffff); 2675 le32enc(&rfa->rbd_addr, 0xffffffff); 2676 2677 /* Map the RFA into DMA memory. */ 2678 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2679 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2680 &rxp->rx_addr, BUS_DMA_NOWAIT); 2681 if (error) { 2682 m_freem(m); 2683 return (error); 2684 } 2685 2686 if (rxp->rx_mbuf != NULL) 2687 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2688 tmp_map = sc->spare_map; 2689 sc->spare_map = rxp->rx_map; 2690 rxp->rx_map = tmp_map; 2691 rxp->rx_mbuf = m; 2692 2693 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2695 return (0); 2696} 2697 2698static void 2699fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2700{ 2701 struct fxp_rfa *p_rfa; 2702 struct fxp_rx *p_rx; 2703 2704 /* 2705 * If there are other buffers already on the list, attach this 2706 * one to the end by fixing up the tail to point to this one. 2707 */ 2708 if (sc->fxp_desc.rx_head != NULL) { 2709 p_rx = sc->fxp_desc.rx_tail; 2710 p_rfa = (struct fxp_rfa *) 2711 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2712 p_rx->rx_next = rxp; 2713 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2714 p_rfa->rfa_control = 0; 2715 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2717 } else { 2718 rxp->rx_next = NULL; 2719 sc->fxp_desc.rx_head = rxp; 2720 } 2721 sc->fxp_desc.rx_tail = rxp; 2722} 2723 2724static void 2725fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2726{ 2727 struct mbuf *m; 2728 struct fxp_rfa *rfa; 2729 2730 m = rxp->rx_mbuf; 2731 m->m_data = m->m_ext.ext_buf; 2732 /* 2733 * Move the data pointer up so that the incoming data packet 2734 * will be 32-bit aligned. 2735 */ 2736 m->m_data += RFA_ALIGNMENT_FUDGE; 2737 2738 /* 2739 * Get a pointer to the base of the mbuf cluster and move 2740 * data start past it. 2741 */ 2742 rfa = mtod(m, struct fxp_rfa *); 2743 m->m_data += sc->rfa_size; 2744 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2745 2746 rfa->rfa_status = 0; 2747 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2748 rfa->actual_size = 0; 2749 2750 /* 2751 * Initialize the rest of the RFA. Note that since the RFA 2752 * is misaligned, we cannot store values directly. We're thus 2753 * using the le32enc() function which handles endianness and 2754 * is also alignment-safe. 2755 */ 2756 le32enc(&rfa->link_addr, 0xffffffff); 2757 le32enc(&rfa->rbd_addr, 0xffffffff); 2758 2759 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2761} 2762 2763static int 2764fxp_miibus_readreg(device_t dev, int phy, int reg) 2765{ 2766 struct fxp_softc *sc = device_get_softc(dev); 2767 int count = 10000; 2768 int value; 2769 2770 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2771 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2772 2773 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2774 && count--) 2775 DELAY(10); 2776 2777 if (count <= 0) 2778 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2779 2780 return (value & 0xffff); 2781} 2782 2783static int 2784fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2785{ 2786 struct fxp_softc *sc = device_get_softc(dev); 2787 int count = 10000; 2788 2789 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2790 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2791 (value & 0xffff)); 2792 2793 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2794 count--) 2795 DELAY(10); 2796 2797 if (count <= 0) 2798 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2799 return (0); 2800} 2801 2802static void 2803fxp_miibus_statchg(device_t dev) 2804{ 2805 struct fxp_softc *sc; 2806 struct mii_data *mii; 2807 if_t ifp; 2808 2809 sc = device_get_softc(dev); 2810 mii = device_get_softc(sc->miibus); 2811 ifp = sc->ifp; 2812 if (mii == NULL || ifp == (void *)NULL || 2813 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 2814 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2815 (IFM_AVALID | IFM_ACTIVE)) 2816 return; 2817 2818 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T && 2819 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2820 sc->cu_resume_bug = 1; 2821 else 2822 sc->cu_resume_bug = 0; 2823 /* 2824 * Call fxp_init_body in order to adjust the flow control settings. 2825 * Note that the 82557 doesn't support hardware flow control. 2826 */ 2827 if (sc->revision == FXP_REV_82557) 2828 return; 2829 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2830 fxp_init_body(sc, 0); 2831} 2832 2833static int 2834fxp_ioctl(if_t ifp, u_long command, caddr_t data) 2835{ 2836 struct fxp_softc *sc = if_getsoftc(ifp); 2837 struct ifreq *ifr = (struct ifreq *)data; 2838 struct mii_data *mii; 2839 int flag, mask, error = 0, reinit; 2840 2841 switch (command) { 2842 case SIOCSIFFLAGS: 2843 FXP_LOCK(sc); 2844 /* 2845 * If interface is marked up and not running, then start it. 2846 * If it is marked down and running, stop it. 2847 * XXX If it's up then re-initialize it. This is so flags 2848 * such as IFF_PROMISC are handled. 2849 */ 2850 if (if_getflags(ifp) & IFF_UP) { 2851 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) && 2852 ((if_getflags(ifp) ^ sc->if_flags) & 2853 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) { 2854 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2855 fxp_init_body(sc, 0); 2856 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2857 fxp_init_body(sc, 1); 2858 } else { 2859 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2860 fxp_stop(sc); 2861 } 2862 sc->if_flags = if_getflags(ifp); 2863 FXP_UNLOCK(sc); 2864 break; 2865 2866 case SIOCADDMULTI: 2867 case SIOCDELMULTI: 2868 FXP_LOCK(sc); 2869 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2870 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2871 fxp_init_body(sc, 0); 2872 } 2873 FXP_UNLOCK(sc); 2874 break; 2875 2876 case SIOCSIFMEDIA: 2877 case SIOCGIFMEDIA: 2878 if (sc->miibus != NULL) { 2879 mii = device_get_softc(sc->miibus); 2880 error = ifmedia_ioctl(ifp, ifr, 2881 &mii->mii_media, command); 2882 } else { 2883 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2884 } 2885 break; 2886 2887 case SIOCSIFCAP: 2888 reinit = 0; 2889 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 2890#ifdef DEVICE_POLLING 2891 if (mask & IFCAP_POLLING) { 2892 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2893 error = ether_poll_register_drv(fxp_poll, ifp); 2894 if (error) 2895 return(error); 2896 FXP_LOCK(sc); 2897 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2898 FXP_SCB_INTR_DISABLE); 2899 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2900 FXP_UNLOCK(sc); 2901 } else { 2902 error = ether_poll_deregister_drv(ifp); 2903 /* Enable interrupts in any case */ 2904 FXP_LOCK(sc); 2905 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2906 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2907 FXP_UNLOCK(sc); 2908 } 2909 } 2910#endif 2911 FXP_LOCK(sc); 2912 if ((mask & IFCAP_TXCSUM) != 0 && 2913 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2914 if_togglecapenable(ifp, IFCAP_TXCSUM); 2915 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2916 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0); 2917 else 2918 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES); 2919 } 2920 if ((mask & IFCAP_RXCSUM) != 0 && 2921 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 2922 if_togglecapenable(ifp, IFCAP_RXCSUM); 2923 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2924 reinit++; 2925 } 2926 if ((mask & IFCAP_TSO4) != 0 && 2927 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2928 if_togglecapenable(ifp, IFCAP_TSO4); 2929 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2930 if_sethwassistbits(ifp, CSUM_TSO, 0); 2931 else 2932 if_sethwassistbits(ifp, 0, CSUM_TSO); 2933 } 2934 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2935 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2936 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2937 if ((mask & IFCAP_VLAN_MTU) != 0 && 2938 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) { 2939 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2940 if (sc->revision != FXP_REV_82557) 2941 flag = FXP_FLAG_LONG_PKT_EN; 2942 else /* a hack to get long frames on the old chip */ 2943 flag = FXP_FLAG_SAVE_BAD; 2944 sc->flags ^= flag; 2945 if (if_getflags(ifp) & IFF_UP) 2946 reinit++; 2947 } 2948 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2949 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2950 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2951 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2952 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2953 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2954 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2955 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2956 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2957 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2958 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO | 2959 IFCAP_VLAN_HWCSUM); 2960 reinit++; 2961 } 2962 if (reinit > 0 && 2963 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2964 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2965 fxp_init_body(sc, 0); 2966 } 2967 FXP_UNLOCK(sc); 2968 if_vlancap(ifp); 2969 break; 2970 2971 default: 2972 error = ether_ioctl(ifp, command, data); 2973 } 2974 return (error); 2975} 2976 2977/* 2978 * Fill in the multicast address list and return number of entries. 2979 */ 2980static int 2981fxp_mc_addrs(struct fxp_softc *sc) 2982{ 2983 struct fxp_cb_mcs *mcsp = sc->mcsp; 2984 if_t ifp = sc->ifp; 2985 int nmcasts = 0; 2986 2987 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) { 2988 if_maddr_rlock(ifp); 2989 if_setupmultiaddr(ifp, mcsp->mc_addr, &nmcasts, MAXMCADDR); 2990 if (nmcasts >= MAXMCADDR) { 2991 if_setflagbits(ifp, IFF_ALLMULTI, 0); 2992 nmcasts = 0; 2993 } 2994 if_maddr_runlock(ifp); 2995 } 2996 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2997 return (nmcasts); 2998} 2999 3000/* 3001 * Program the multicast filter. 3002 * 3003 * We have an artificial restriction that the multicast setup command 3004 * must be the first command in the chain, so we take steps to ensure 3005 * this. By requiring this, it allows us to keep up the performance of 3006 * the pre-initialized command ring (esp. link pointers) by not actually 3007 * inserting the mcsetup command in the ring - i.e. its link pointer 3008 * points to the TxCB ring, but the mcsetup descriptor itself is not part 3009 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 3010 * lead into the regular TxCB ring when it completes. 3011 */ 3012static void 3013fxp_mc_setup(struct fxp_softc *sc) 3014{ 3015 struct fxp_cb_mcs *mcsp; 3016 int count; 3017 3018 FXP_LOCK_ASSERT(sc, MA_OWNED); 3019 3020 mcsp = sc->mcsp; 3021 mcsp->cb_status = 0; 3022 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 3023 mcsp->link_addr = 0xffffffff; 3024 fxp_mc_addrs(sc); 3025 3026 /* 3027 * Wait until command unit is idle. This should never be the 3028 * case when nothing is queued, but make sure anyway. 3029 */ 3030 count = 100; 3031 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 3032 FXP_SCB_CUS_IDLE && --count) 3033 DELAY(10); 3034 if (count == 0) { 3035 device_printf(sc->dev, "command queue timeout\n"); 3036 return; 3037 } 3038 3039 /* 3040 * Start the multicast setup command. 3041 */ 3042 fxp_scb_wait(sc); 3043 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3045 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3046 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3047 /* ...and wait for it to complete. */ 3048 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3049} 3050 3051static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3052static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3053static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3054static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3055static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3056static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3057static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3058 3059#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3060 3061static const struct ucode { 3062 uint32_t revision; 3063 uint32_t *ucode; 3064 int length; 3065 u_short int_delay_offset; 3066 u_short bundle_max_offset; 3067} ucode_table[] = { 3068 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3069 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3070 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3071 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3072 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3073 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3074 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3075 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3076 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3077 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3078 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3079 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3080 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 3081 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3082 { 0, NULL, 0, 0, 0 } 3083}; 3084 3085static void 3086fxp_load_ucode(struct fxp_softc *sc) 3087{ 3088 const struct ucode *uc; 3089 struct fxp_cb_ucode *cbp; 3090 int i; 3091 3092 if (sc->flags & FXP_FLAG_NO_UCODE) 3093 return; 3094 3095 for (uc = ucode_table; uc->ucode != NULL; uc++) 3096 if (sc->revision == uc->revision) 3097 break; 3098 if (uc->ucode == NULL) 3099 return; 3100 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3101 cbp->cb_status = 0; 3102 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3103 cbp->link_addr = 0xffffffff; /* (no) next command */ 3104 for (i = 0; i < uc->length; i++) 3105 cbp->ucode[i] = htole32(uc->ucode[i]); 3106 if (uc->int_delay_offset) 3107 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3108 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3109 if (uc->bundle_max_offset) 3110 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3111 htole16(sc->tunable_bundle_max); 3112 /* 3113 * Download the ucode to the chip. 3114 */ 3115 fxp_scb_wait(sc); 3116 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3118 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3119 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3120 /* ...and wait for it to complete. */ 3121 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3122 device_printf(sc->dev, 3123 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3124 sc->tunable_int_delay, 3125 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3126 sc->flags |= FXP_FLAG_UCODE; 3127 bzero(cbp, FXP_TXCB_SZ); 3128} 3129 3130#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3131 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3132 3133static void 3134fxp_sysctl_node(struct fxp_softc *sc) 3135{ 3136 struct sysctl_ctx_list *ctx; 3137 struct sysctl_oid_list *child, *parent; 3138 struct sysctl_oid *tree; 3139 struct fxp_hwstats *hsp; 3140 3141 ctx = device_get_sysctl_ctx(sc->dev); 3142 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3143 3144 SYSCTL_ADD_PROC(ctx, child, 3145 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 3146 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3147 "FXP driver receive interrupt microcode bundling delay"); 3148 SYSCTL_ADD_PROC(ctx, child, 3149 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 3150 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3151 "FXP driver receive interrupt microcode bundle size limit"); 3152 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3153 "FXP RNR events"); 3154 3155 /* 3156 * Pull in device tunables. 3157 */ 3158 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3159 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3160 (void) resource_int_value(device_get_name(sc->dev), 3161 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3162 (void) resource_int_value(device_get_name(sc->dev), 3163 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3164 sc->rnr = 0; 3165 3166 hsp = &sc->fxp_hwstats; 3167 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3168 NULL, "FXP statistics"); 3169 parent = SYSCTL_CHILDREN(tree); 3170 3171 /* Rx MAC statistics. */ 3172 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3173 NULL, "Rx MAC statistics"); 3174 child = SYSCTL_CHILDREN(tree); 3175 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3176 &hsp->rx_good, "Good frames"); 3177 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3178 &hsp->rx_crc_errors, "CRC errors"); 3179 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3180 &hsp->rx_alignment_errors, "Alignment errors"); 3181 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3182 &hsp->rx_rnr_errors, "RNR errors"); 3183 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3184 &hsp->rx_overrun_errors, "Overrun errors"); 3185 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3186 &hsp->rx_cdt_errors, "Collision detect errors"); 3187 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3188 &hsp->rx_shortframes, "Short frame errors"); 3189 if (sc->revision >= FXP_REV_82558_A4) { 3190 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3191 &hsp->rx_pause, "Pause frames"); 3192 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3193 &hsp->rx_controls, "Unsupported control frames"); 3194 } 3195 if (sc->revision >= FXP_REV_82559_A0) 3196 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3197 &hsp->rx_tco, "TCO frames"); 3198 3199 /* Tx MAC statistics. */ 3200 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3201 NULL, "Tx MAC statistics"); 3202 child = SYSCTL_CHILDREN(tree); 3203 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3204 &hsp->tx_good, "Good frames"); 3205 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3206 &hsp->tx_maxcols, "Maximum collisions errors"); 3207 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3208 &hsp->tx_latecols, "Late collisions errors"); 3209 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3210 &hsp->tx_underruns, "Underrun errors"); 3211 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3212 &hsp->tx_lostcrs, "Lost carrier sense"); 3213 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3214 &hsp->tx_deffered, "Deferred"); 3215 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3216 &hsp->tx_single_collisions, "Single collisions"); 3217 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3218 &hsp->tx_multiple_collisions, "Multiple collisions"); 3219 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3220 &hsp->tx_total_collisions, "Total collisions"); 3221 if (sc->revision >= FXP_REV_82558_A4) 3222 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3223 &hsp->tx_pause, "Pause frames"); 3224 if (sc->revision >= FXP_REV_82559_A0) 3225 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3226 &hsp->tx_tco, "TCO frames"); 3227} 3228 3229#undef FXP_SYSCTL_STAT_ADD 3230 3231static int 3232sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3233{ 3234 int error, value; 3235 3236 value = *(int *)arg1; 3237 error = sysctl_handle_int(oidp, &value, 0, req); 3238 if (error || !req->newptr) 3239 return (error); 3240 if (value < low || value > high) 3241 return (EINVAL); 3242 *(int *)arg1 = value; 3243 return (0); 3244} 3245 3246/* 3247 * Interrupt delay is expressed in microseconds, a multiplier is used 3248 * to convert this to the appropriate clock ticks before using. 3249 */ 3250static int 3251sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3252{ 3253 3254 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3255} 3256 3257static int 3258sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3259{ 3260 3261 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3262} 3263