if_fxp.c revision 233585
1/*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice unmodified, this list of conditions, and the following
11 *    disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 233585 2012-03-28 01:08:55Z yongari $");
32
33/*
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 */
36
37#ifdef HAVE_KERNEL_OPTION_HEADERS
38#include "opt_device_polling.h"
39#endif
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/bus.h>
44#include <sys/endian.h>
45#include <sys/kernel.h>
46#include <sys/mbuf.h>
47#include <sys/lock.h>
48#include <sys/module.h>
49#include <sys/mutex.h>
50#include <sys/rman.h>
51#include <sys/socket.h>
52#include <sys/sockio.h>
53#include <sys/sysctl.h>
54
55#include <net/bpf.h>
56#include <net/ethernet.h>
57#include <net/if.h>
58#include <net/if_arp.h>
59#include <net/if_dl.h>
60#include <net/if_media.h>
61#include <net/if_types.h>
62#include <net/if_vlan_var.h>
63
64#include <netinet/in.h>
65#include <netinet/in_systm.h>
66#include <netinet/ip.h>
67#include <netinet/tcp.h>
68#include <netinet/udp.h>
69
70#include <machine/bus.h>
71#include <machine/in_cksum.h>
72#include <machine/resource.h>
73
74#include <dev/pci/pcivar.h>
75#include <dev/pci/pcireg.h>		/* for PCIM_CMD_xxx */
76
77#include <dev/mii/mii.h>
78#include <dev/mii/miivar.h>
79
80#include <dev/fxp/if_fxpreg.h>
81#include <dev/fxp/if_fxpvar.h>
82#include <dev/fxp/rcvbundl.h>
83
84MODULE_DEPEND(fxp, pci, 1, 1, 1);
85MODULE_DEPEND(fxp, ether, 1, 1, 1);
86MODULE_DEPEND(fxp, miibus, 1, 1, 1);
87#include "miibus_if.h"
88
89/*
90 * NOTE!  On !x86 we typically have an alignment constraint.  The
91 * card DMAs the packet immediately following the RFA.  However,
92 * the first thing in the packet is a 14-byte Ethernet header.
93 * This means that the packet is misaligned.  To compensate,
94 * we actually offset the RFA 2 bytes into the cluster.  This
95 * alignes the packet after the Ethernet header at a 32-bit
96 * boundary.  HOWEVER!  This means that the RFA is misaligned!
97 */
98#define	RFA_ALIGNMENT_FUDGE	2
99
100/*
101 * Set initial transmit threshold at 64 (512 bytes). This is
102 * increased by 64 (512 bytes) at a time, to maximum of 192
103 * (1536 bytes), if an underrun occurs.
104 */
105static int tx_threshold = 64;
106
107/*
108 * The configuration byte map has several undefined fields which
109 * must be one or must be zero.  Set up a template for these bits.
110 * The actual configuration is performed in fxp_init_body.
111 *
112 * See struct fxp_cb_config for the bit definitions.
113 */
114static const u_char const fxp_cb_config_template[] = {
115	0x0, 0x0,		/* cb_status */
116	0x0, 0x0,		/* cb_command */
117	0x0, 0x0, 0x0, 0x0,	/* link_addr */
118	0x0,	/*  0 */
119	0x0,	/*  1 */
120	0x0,	/*  2 */
121	0x0,	/*  3 */
122	0x0,	/*  4 */
123	0x0,	/*  5 */
124	0x32,	/*  6 */
125	0x0,	/*  7 */
126	0x0,	/*  8 */
127	0x0,	/*  9 */
128	0x6,	/* 10 */
129	0x0,	/* 11 */
130	0x0,	/* 12 */
131	0x0,	/* 13 */
132	0xf2,	/* 14 */
133	0x48,	/* 15 */
134	0x0,	/* 16 */
135	0x40,	/* 17 */
136	0xf0,	/* 18 */
137	0x0,	/* 19 */
138	0x3f,	/* 20 */
139	0x5,	/* 21 */
140	0x0,	/* 22 */
141	0x0,	/* 23 */
142	0x0,	/* 24 */
143	0x0,	/* 25 */
144	0x0,	/* 26 */
145	0x0,	/* 27 */
146	0x0,	/* 28 */
147	0x0,	/* 29 */
148	0x0,	/* 30 */
149	0x0	/* 31 */
150};
151
152/*
153 * Claim various Intel PCI device identifiers for this driver.  The
154 * sub-vendor and sub-device field are extensively used to identify
155 * particular variants, but we don't currently differentiate between
156 * them.
157 */
158static const struct fxp_ident const fxp_ident_table[] = {
159    { 0x1029,	-1,	0, "Intel 82559 PCI/CardBus Pro/100" },
160    { 0x1030,	-1,	0, "Intel 82559 Pro/100 Ethernet" },
161    { 0x1031,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
162    { 0x1032,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
163    { 0x1033,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
164    { 0x1034,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165    { 0x1035,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166    { 0x1036,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167    { 0x1037,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168    { 0x1038,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169    { 0x1039,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
170    { 0x103A,	-1,	4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
171    { 0x103B,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
172    { 0x103C,	-1,	4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173    { 0x103D,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174    { 0x103E,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
175    { 0x1050,	-1,	5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
176    { 0x1051,	-1,	5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
177    { 0x1059,	-1,	0, "Intel 82551QM Pro/100 M Mobile Connection" },
178    { 0x1064,	-1,	6, "Intel 82562EZ (ICH6)" },
179    { 0x1065,	-1,	6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
180    { 0x1068,	-1,	6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
181    { 0x1069,	-1,	6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
182    { 0x1091,	-1,	7, "Intel 82562GX Pro/100 Ethernet" },
183    { 0x1092,	-1,	7, "Intel Pro/100 VE Network Connection" },
184    { 0x1093,	-1,	7, "Intel Pro/100 VM Network Connection" },
185    { 0x1094,	-1,	7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
186    { 0x1209,	-1,	0, "Intel 82559ER Embedded 10/100 Ethernet" },
187    { 0x1229,	0x01,	0, "Intel 82557 Pro/100 Ethernet" },
188    { 0x1229,	0x02,	0, "Intel 82557 Pro/100 Ethernet" },
189    { 0x1229,	0x03,	0, "Intel 82557 Pro/100 Ethernet" },
190    { 0x1229,	0x04,	0, "Intel 82558 Pro/100 Ethernet" },
191    { 0x1229,	0x05,	0, "Intel 82558 Pro/100 Ethernet" },
192    { 0x1229,	0x06,	0, "Intel 82559 Pro/100 Ethernet" },
193    { 0x1229,	0x07,	0, "Intel 82559 Pro/100 Ethernet" },
194    { 0x1229,	0x08,	0, "Intel 82559 Pro/100 Ethernet" },
195    { 0x1229,	0x09,	0, "Intel 82559ER Pro/100 Ethernet" },
196    { 0x1229,	0x0c,	0, "Intel 82550 Pro/100 Ethernet" },
197    { 0x1229,	0x0d,	0, "Intel 82550C Pro/100 Ethernet" },
198    { 0x1229,	0x0e,	0, "Intel 82550 Pro/100 Ethernet" },
199    { 0x1229,	0x0f,	0, "Intel 82551 Pro/100 Ethernet" },
200    { 0x1229,	0x10,	0, "Intel 82551 Pro/100 Ethernet" },
201    { 0x1229,	-1,	0, "Intel 82557/8/9 Pro/100 Ethernet" },
202    { 0x2449,	-1,	2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
203    { 0x27dc,	-1,	7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
204    { 0,	-1,	0, NULL },
205};
206
207#ifdef FXP_IP_CSUM_WAR
208#define FXP_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
209#else
210#define FXP_CSUM_FEATURES    (CSUM_TCP | CSUM_UDP)
211#endif
212
213static int		fxp_probe(device_t dev);
214static int		fxp_attach(device_t dev);
215static int		fxp_detach(device_t dev);
216static int		fxp_shutdown(device_t dev);
217static int		fxp_suspend(device_t dev);
218static int		fxp_resume(device_t dev);
219
220static const struct fxp_ident *fxp_find_ident(device_t dev);
221static void		fxp_intr(void *xsc);
222static void		fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
223			    struct mbuf *m, uint16_t status, int pos);
224static int		fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
225			    uint8_t statack, int count);
226static void 		fxp_init(void *xsc);
227static void 		fxp_init_body(struct fxp_softc *sc, int);
228static void 		fxp_tick(void *xsc);
229static void 		fxp_start(struct ifnet *ifp);
230static void 		fxp_start_body(struct ifnet *ifp);
231static int		fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
232static void		fxp_txeof(struct fxp_softc *sc);
233static void		fxp_stop(struct fxp_softc *sc);
234static void 		fxp_release(struct fxp_softc *sc);
235static int		fxp_ioctl(struct ifnet *ifp, u_long command,
236			    caddr_t data);
237static void 		fxp_watchdog(struct fxp_softc *sc);
238static void		fxp_add_rfabuf(struct fxp_softc *sc,
239			    struct fxp_rx *rxp);
240static void		fxp_discard_rfabuf(struct fxp_softc *sc,
241			    struct fxp_rx *rxp);
242static int		fxp_new_rfabuf(struct fxp_softc *sc,
243			    struct fxp_rx *rxp);
244static int		fxp_mc_addrs(struct fxp_softc *sc);
245static void		fxp_mc_setup(struct fxp_softc *sc);
246static uint16_t		fxp_eeprom_getword(struct fxp_softc *sc, int offset,
247			    int autosize);
248static void 		fxp_eeprom_putword(struct fxp_softc *sc, int offset,
249			    uint16_t data);
250static void		fxp_autosize_eeprom(struct fxp_softc *sc);
251static void		fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
252			    int offset, int words);
253static void		fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
254			    int offset, int words);
255static int		fxp_ifmedia_upd(struct ifnet *ifp);
256static void		fxp_ifmedia_sts(struct ifnet *ifp,
257			    struct ifmediareq *ifmr);
258static int		fxp_serial_ifmedia_upd(struct ifnet *ifp);
259static void		fxp_serial_ifmedia_sts(struct ifnet *ifp,
260			    struct ifmediareq *ifmr);
261static int		fxp_miibus_readreg(device_t dev, int phy, int reg);
262static int		fxp_miibus_writereg(device_t dev, int phy, int reg,
263			    int value);
264static void		fxp_miibus_statchg(device_t dev);
265static void		fxp_load_ucode(struct fxp_softc *sc);
266static void		fxp_update_stats(struct fxp_softc *sc);
267static void		fxp_sysctl_node(struct fxp_softc *sc);
268static int		sysctl_int_range(SYSCTL_HANDLER_ARGS,
269			    int low, int high);
270static int		sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
271static int		sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
272static void 		fxp_scb_wait(struct fxp_softc *sc);
273static void		fxp_scb_cmd(struct fxp_softc *sc, int cmd);
274static void		fxp_dma_wait(struct fxp_softc *sc,
275			    volatile uint16_t *status, bus_dma_tag_t dmat,
276			    bus_dmamap_t map);
277
278static device_method_t fxp_methods[] = {
279	/* Device interface */
280	DEVMETHOD(device_probe,		fxp_probe),
281	DEVMETHOD(device_attach,	fxp_attach),
282	DEVMETHOD(device_detach,	fxp_detach),
283	DEVMETHOD(device_shutdown,	fxp_shutdown),
284	DEVMETHOD(device_suspend,	fxp_suspend),
285	DEVMETHOD(device_resume,	fxp_resume),
286
287	/* MII interface */
288	DEVMETHOD(miibus_readreg,	fxp_miibus_readreg),
289	DEVMETHOD(miibus_writereg,	fxp_miibus_writereg),
290	DEVMETHOD(miibus_statchg,	fxp_miibus_statchg),
291
292	{ 0, 0 }
293};
294
295static driver_t fxp_driver = {
296	"fxp",
297	fxp_methods,
298	sizeof(struct fxp_softc),
299};
300
301static devclass_t fxp_devclass;
302
303DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
304DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
305
306static struct resource_spec fxp_res_spec_mem[] = {
307	{ SYS_RES_MEMORY,	FXP_PCI_MMBA,	RF_ACTIVE },
308	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
309	{ -1, 0 }
310};
311
312static struct resource_spec fxp_res_spec_io[] = {
313	{ SYS_RES_IOPORT,	FXP_PCI_IOBA,	RF_ACTIVE },
314	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
315	{ -1, 0 }
316};
317
318/*
319 * Wait for the previous command to be accepted (but not necessarily
320 * completed).
321 */
322static void
323fxp_scb_wait(struct fxp_softc *sc)
324{
325	union {
326		uint16_t w;
327		uint8_t b[2];
328	} flowctl;
329	int i = 10000;
330
331	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
332		DELAY(2);
333	if (i == 0) {
334		flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
335		flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
336		device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
337		    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
338		    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
339		    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
340	}
341}
342
343static void
344fxp_scb_cmd(struct fxp_softc *sc, int cmd)
345{
346
347	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
348		CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
349		fxp_scb_wait(sc);
350	}
351	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
352}
353
354static void
355fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
356    bus_dma_tag_t dmat, bus_dmamap_t map)
357{
358	int i;
359
360	for (i = 10000; i > 0; i--) {
361		DELAY(2);
362		bus_dmamap_sync(dmat, map,
363		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
364		if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
365			break;
366	}
367	if (i == 0)
368		device_printf(sc->dev, "DMA timeout\n");
369}
370
371static const struct fxp_ident *
372fxp_find_ident(device_t dev)
373{
374	uint16_t devid;
375	uint8_t revid;
376	const struct fxp_ident *ident;
377
378	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
379		devid = pci_get_device(dev);
380		revid = pci_get_revid(dev);
381		for (ident = fxp_ident_table; ident->name != NULL; ident++) {
382			if (ident->devid == devid &&
383			    (ident->revid == revid || ident->revid == -1)) {
384				return (ident);
385			}
386		}
387	}
388	return (NULL);
389}
390
391/*
392 * Return identification string if this device is ours.
393 */
394static int
395fxp_probe(device_t dev)
396{
397	const struct fxp_ident *ident;
398
399	ident = fxp_find_ident(dev);
400	if (ident != NULL) {
401		device_set_desc(dev, ident->name);
402		return (BUS_PROBE_DEFAULT);
403	}
404	return (ENXIO);
405}
406
407static void
408fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
409{
410	uint32_t *addr;
411
412	if (error)
413		return;
414
415	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
416	addr = arg;
417	*addr = segs->ds_addr;
418}
419
420static int
421fxp_attach(device_t dev)
422{
423	struct fxp_softc *sc;
424	struct fxp_cb_tx *tcbp;
425	struct fxp_tx *txp;
426	struct fxp_rx *rxp;
427	struct ifnet *ifp;
428	uint32_t val;
429	uint16_t data, myea[ETHER_ADDR_LEN / 2];
430	u_char eaddr[ETHER_ADDR_LEN];
431	int error, flags, i, pmc, prefer_iomap;
432
433	error = 0;
434	sc = device_get_softc(dev);
435	sc->dev = dev;
436	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
437	    MTX_DEF);
438	callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
439	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
440	    fxp_serial_ifmedia_sts);
441
442	ifp = sc->ifp = if_alloc(IFT_ETHER);
443	if (ifp == NULL) {
444		device_printf(dev, "can not if_alloc()\n");
445		error = ENOSPC;
446		goto fail;
447	}
448
449	/*
450	 * Enable bus mastering.
451	 */
452	pci_enable_busmaster(dev);
453	val = pci_read_config(dev, PCIR_COMMAND, 2);
454
455	/*
456	 * Figure out which we should try first - memory mapping or i/o mapping?
457	 * We default to memory mapping. Then we accept an override from the
458	 * command line. Then we check to see which one is enabled.
459	 */
460	prefer_iomap = 0;
461	resource_int_value(device_get_name(dev), device_get_unit(dev),
462	    "prefer_iomap", &prefer_iomap);
463	if (prefer_iomap)
464		sc->fxp_spec = fxp_res_spec_io;
465	else
466		sc->fxp_spec = fxp_res_spec_mem;
467
468	error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
469	if (error) {
470		if (sc->fxp_spec == fxp_res_spec_mem)
471			sc->fxp_spec = fxp_res_spec_io;
472		else
473			sc->fxp_spec = fxp_res_spec_mem;
474		error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
475	}
476	if (error) {
477		device_printf(dev, "could not allocate resources\n");
478		error = ENXIO;
479		goto fail;
480	}
481
482	if (bootverbose) {
483		device_printf(dev, "using %s space register mapping\n",
484		   sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
485	}
486
487	/*
488	 * Put CU/RU idle state and prepare full reset.
489	 */
490	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
491	DELAY(10);
492	/* Full reset and disable interrupts. */
493	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
494	DELAY(10);
495	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
496
497	/*
498	 * Find out how large of an SEEPROM we have.
499	 */
500	fxp_autosize_eeprom(sc);
501
502	/*
503	 * Find out the chip revision; lump all 82557 revs together.
504	 */
505	sc->ident = fxp_find_ident(dev);
506	if (sc->ident->ich > 0) {
507		/* Assume ICH controllers are 82559. */
508		sc->revision = FXP_REV_82559_A0;
509	} else {
510		fxp_read_eeprom(sc, &data, 5, 1);
511		if ((data >> 8) == 1)
512			sc->revision = FXP_REV_82557;
513		else
514			sc->revision = pci_get_revid(dev);
515	}
516
517	/*
518	 * Check availability of WOL. 82559ER does not support WOL.
519	 */
520	if (sc->revision >= FXP_REV_82558_A4 &&
521	    sc->revision != FXP_REV_82559S_A) {
522		fxp_read_eeprom(sc, &data, 10, 1);
523		if ((data & 0x20) != 0 &&
524		    pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
525			sc->flags |= FXP_FLAG_WOLCAP;
526	}
527
528	if (sc->revision == FXP_REV_82550_C) {
529		/*
530		 * 82550C with server extension requires microcode to
531		 * receive fragmented UDP datagrams.  However if the
532		 * microcode is used for client-only featured 82550C
533		 * it locks up controller.
534		 */
535		fxp_read_eeprom(sc, &data, 3, 1);
536		if ((data & 0x0400) == 0)
537			sc->flags |= FXP_FLAG_NO_UCODE;
538	}
539
540	/* Receiver lock-up workaround detection. */
541	if (sc->revision < FXP_REV_82558_A4) {
542		fxp_read_eeprom(sc, &data, 3, 1);
543		if ((data & 0x03) != 0x03) {
544			sc->flags |= FXP_FLAG_RXBUG;
545			device_printf(dev, "Enabling Rx lock-up workaround\n");
546		}
547	}
548
549	/*
550	 * Determine whether we must use the 503 serial interface.
551	 */
552	fxp_read_eeprom(sc, &data, 6, 1);
553	if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
554	    && (data & FXP_PHY_SERIAL_ONLY))
555		sc->flags |= FXP_FLAG_SERIAL_MEDIA;
556
557	fxp_sysctl_node(sc);
558	/*
559	 * Enable workarounds for certain chip revision deficiencies.
560	 *
561	 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
562	 * some systems based a normal 82559 design, have a defect where
563	 * the chip can cause a PCI protocol violation if it receives
564	 * a CU_RESUME command when it is entering the IDLE state.  The
565	 * workaround is to disable Dynamic Standby Mode, so the chip never
566	 * deasserts CLKRUN#, and always remains in an active state.
567	 *
568	 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
569	 */
570	if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
571	    (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
572		fxp_read_eeprom(sc, &data, 10, 1);
573		if (data & 0x02) {			/* STB enable */
574			uint16_t cksum;
575			int i;
576
577			device_printf(dev,
578			    "Disabling dynamic standby mode in EEPROM\n");
579			data &= ~0x02;
580			fxp_write_eeprom(sc, &data, 10, 1);
581			device_printf(dev, "New EEPROM ID: 0x%x\n", data);
582			cksum = 0;
583			for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
584				fxp_read_eeprom(sc, &data, i, 1);
585				cksum += data;
586			}
587			i = (1 << sc->eeprom_size) - 1;
588			cksum = 0xBABA - cksum;
589			fxp_read_eeprom(sc, &data, i, 1);
590			fxp_write_eeprom(sc, &cksum, i, 1);
591			device_printf(dev,
592			    "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
593			    i, data, cksum);
594#if 1
595			/*
596			 * If the user elects to continue, try the software
597			 * workaround, as it is better than nothing.
598			 */
599			sc->flags |= FXP_FLAG_CU_RESUME_BUG;
600#endif
601		}
602	}
603
604	/*
605	 * If we are not a 82557 chip, we can enable extended features.
606	 */
607	if (sc->revision != FXP_REV_82557) {
608		/*
609		 * If MWI is enabled in the PCI configuration, and there
610		 * is a valid cacheline size (8 or 16 dwords), then tell
611		 * the board to turn on MWI.
612		 */
613		if (val & PCIM_CMD_MWRICEN &&
614		    pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
615			sc->flags |= FXP_FLAG_MWI_ENABLE;
616
617		/* turn on the extended TxCB feature */
618		sc->flags |= FXP_FLAG_EXT_TXCB;
619
620		/* enable reception of long frames for VLAN */
621		sc->flags |= FXP_FLAG_LONG_PKT_EN;
622	} else {
623		/* a hack to get long VLAN frames on a 82557 */
624		sc->flags |= FXP_FLAG_SAVE_BAD;
625	}
626
627	/* For 82559 or later chips, Rx checksum offload is supported. */
628	if (sc->revision >= FXP_REV_82559_A0) {
629		/* 82559ER does not support Rx checksum offloading. */
630		if (sc->ident->devid != 0x1209)
631			sc->flags |= FXP_FLAG_82559_RXCSUM;
632	}
633	/*
634	 * Enable use of extended RFDs and TCBs for 82550
635	 * and later chips. Note: we need extended TXCB support
636	 * too, but that's already enabled by the code above.
637	 * Be careful to do this only on the right devices.
638	 */
639	if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
640	    sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
641	    || sc->revision == FXP_REV_82551_10) {
642		sc->rfa_size = sizeof (struct fxp_rfa);
643		sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
644		sc->flags |= FXP_FLAG_EXT_RFA;
645		/* Use extended RFA instead of 82559 checksum mode. */
646		sc->flags &= ~FXP_FLAG_82559_RXCSUM;
647	} else {
648		sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
649		sc->tx_cmd = FXP_CB_COMMAND_XMIT;
650	}
651
652	/*
653	 * Allocate DMA tags and DMA safe memory.
654	 */
655	sc->maxtxseg = FXP_NTXSEG;
656	sc->maxsegsize = MCLBYTES;
657	if (sc->flags & FXP_FLAG_EXT_RFA) {
658		sc->maxtxseg--;
659		sc->maxsegsize = FXP_TSO_SEGSIZE;
660	}
661	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
662	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
663	    sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
664	    sc->maxtxseg, sc->maxsegsize, 0,
665	    busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
666	if (error) {
667		device_printf(dev, "could not create TX DMA tag\n");
668		goto fail;
669	}
670
671	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
672	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
673	    MCLBYTES, 1, MCLBYTES, 0,
674	    busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
675	if (error) {
676		device_printf(dev, "could not create RX DMA tag\n");
677		goto fail;
678	}
679
680	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
681	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
682	    sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
683	    busdma_lock_mutex, &Giant, &sc->fxp_stag);
684	if (error) {
685		device_printf(dev, "could not create stats DMA tag\n");
686		goto fail;
687	}
688
689	error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
690	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
691	if (error) {
692		device_printf(dev, "could not allocate stats DMA memory\n");
693		goto fail;
694	}
695	error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
696	    sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
697	    BUS_DMA_NOWAIT);
698	if (error) {
699		device_printf(dev, "could not load the stats DMA buffer\n");
700		goto fail;
701	}
702
703	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
704	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
705	    FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
706	    busdma_lock_mutex, &Giant, &sc->cbl_tag);
707	if (error) {
708		device_printf(dev, "could not create TxCB DMA tag\n");
709		goto fail;
710	}
711
712	error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
713	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
714	if (error) {
715		device_printf(dev, "could not allocate TxCB DMA memory\n");
716		goto fail;
717	}
718
719	error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
720	    sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
721	    &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
722	if (error) {
723		device_printf(dev, "could not load TxCB DMA buffer\n");
724		goto fail;
725	}
726
727	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
728	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
729	    sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
730	    busdma_lock_mutex, &Giant, &sc->mcs_tag);
731	if (error) {
732		device_printf(dev,
733		    "could not create multicast setup DMA tag\n");
734		goto fail;
735	}
736
737	error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
738	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
739	if (error) {
740		device_printf(dev,
741		    "could not allocate multicast setup DMA memory\n");
742		goto fail;
743	}
744	error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
745	    sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
746	    BUS_DMA_NOWAIT);
747	if (error) {
748		device_printf(dev,
749		    "can't load the multicast setup DMA buffer\n");
750		goto fail;
751	}
752
753	/*
754	 * Pre-allocate the TX DMA maps and setup the pointers to
755	 * the TX command blocks.
756	 */
757	txp = sc->fxp_desc.tx_list;
758	tcbp = sc->fxp_desc.cbl_list;
759	for (i = 0; i < FXP_NTXCB; i++) {
760		txp[i].tx_cb = tcbp + i;
761		error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
762		if (error) {
763			device_printf(dev, "can't create DMA map for TX\n");
764			goto fail;
765		}
766	}
767	error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
768	if (error) {
769		device_printf(dev, "can't create spare DMA map\n");
770		goto fail;
771	}
772
773	/*
774	 * Pre-allocate our receive buffers.
775	 */
776	sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
777	for (i = 0; i < FXP_NRFABUFS; i++) {
778		rxp = &sc->fxp_desc.rx_list[i];
779		error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
780		if (error) {
781			device_printf(dev, "can't create DMA map for RX\n");
782			goto fail;
783		}
784		if (fxp_new_rfabuf(sc, rxp) != 0) {
785			error = ENOMEM;
786			goto fail;
787		}
788		fxp_add_rfabuf(sc, rxp);
789	}
790
791	/*
792	 * Read MAC address.
793	 */
794	fxp_read_eeprom(sc, myea, 0, 3);
795	eaddr[0] = myea[0] & 0xff;
796	eaddr[1] = myea[0] >> 8;
797	eaddr[2] = myea[1] & 0xff;
798	eaddr[3] = myea[1] >> 8;
799	eaddr[4] = myea[2] & 0xff;
800	eaddr[5] = myea[2] >> 8;
801	if (bootverbose) {
802		device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
803		    pci_get_vendor(dev), pci_get_device(dev),
804		    pci_get_subvendor(dev), pci_get_subdevice(dev),
805		    pci_get_revid(dev));
806		fxp_read_eeprom(sc, &data, 10, 1);
807		device_printf(dev, "Dynamic Standby mode is %s\n",
808		    data & 0x02 ? "enabled" : "disabled");
809	}
810
811	/*
812	 * If this is only a 10Mbps device, then there is no MII, and
813	 * the PHY will use a serial interface instead.
814	 *
815	 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
816	 * doesn't have a programming interface of any sort.  The
817	 * media is sensed automatically based on how the link partner
818	 * is configured.  This is, in essence, manual configuration.
819	 */
820	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
821		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
822		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
823	} else {
824		/*
825		 * i82557 wedge when isolating all of their PHYs.
826		 */
827		flags = MIIF_NOISOLATE;
828		if (sc->revision >= FXP_REV_82558_A4)
829			flags |= MIIF_DOPAUSE;
830		error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd,
831		    fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
832		    MII_OFFSET_ANY, flags);
833		if (error != 0) {
834			device_printf(dev, "attaching PHYs failed\n");
835			goto fail;
836		}
837	}
838
839	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
840	ifp->if_init = fxp_init;
841	ifp->if_softc = sc;
842	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
843	ifp->if_ioctl = fxp_ioctl;
844	ifp->if_start = fxp_start;
845
846	ifp->if_capabilities = ifp->if_capenable = 0;
847
848	/* Enable checksum offload/TSO for 82550 or better chips */
849	if (sc->flags & FXP_FLAG_EXT_RFA) {
850		ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
851		ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
852		ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
853	}
854
855	if (sc->flags & FXP_FLAG_82559_RXCSUM) {
856		ifp->if_capabilities |= IFCAP_RXCSUM;
857		ifp->if_capenable |= IFCAP_RXCSUM;
858	}
859
860	if (sc->flags & FXP_FLAG_WOLCAP) {
861		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
862		ifp->if_capenable |= IFCAP_WOL_MAGIC;
863	}
864
865#ifdef DEVICE_POLLING
866	/* Inform the world we support polling. */
867	ifp->if_capabilities |= IFCAP_POLLING;
868#endif
869
870	/*
871	 * Attach the interface.
872	 */
873	ether_ifattach(ifp, eaddr);
874
875	/*
876	 * Tell the upper layer(s) we support long frames.
877	 * Must appear after the call to ether_ifattach() because
878	 * ether_ifattach() sets ifi_hdrlen to the default value.
879	 */
880	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
881	ifp->if_capabilities |= IFCAP_VLAN_MTU;
882	ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
883	if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
884		ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
885		    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
886		ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
887		    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
888	}
889
890	/*
891	 * Let the system queue as many packets as we have available
892	 * TX descriptors.
893	 */
894	IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
895	ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
896	IFQ_SET_READY(&ifp->if_snd);
897
898	/*
899	 * Hook our interrupt after all initialization is complete.
900	 */
901	error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
902			       NULL, fxp_intr, sc, &sc->ih);
903	if (error) {
904		device_printf(dev, "could not setup irq\n");
905		ether_ifdetach(sc->ifp);
906		goto fail;
907	}
908
909	/*
910	 * Configure hardware to reject magic frames otherwise
911	 * system will hang on recipt of magic frames.
912	 */
913	if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
914		FXP_LOCK(sc);
915		/* Clear wakeup events. */
916		CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
917		fxp_init_body(sc, 0);
918		fxp_stop(sc);
919		FXP_UNLOCK(sc);
920	}
921
922fail:
923	if (error)
924		fxp_release(sc);
925	return (error);
926}
927
928/*
929 * Release all resources.  The softc lock should not be held and the
930 * interrupt should already be torn down.
931 */
932static void
933fxp_release(struct fxp_softc *sc)
934{
935	struct fxp_rx *rxp;
936	struct fxp_tx *txp;
937	int i;
938
939	FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
940	KASSERT(sc->ih == NULL,
941	    ("fxp_release() called with intr handle still active"));
942	if (sc->miibus)
943		device_delete_child(sc->dev, sc->miibus);
944	bus_generic_detach(sc->dev);
945	ifmedia_removeall(&sc->sc_media);
946	if (sc->fxp_desc.cbl_list) {
947		bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
948		bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
949		    sc->cbl_map);
950	}
951	if (sc->fxp_stats) {
952		bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
953		bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
954	}
955	if (sc->mcsp) {
956		bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
957		bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
958	}
959	bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
960	if (sc->fxp_rxmtag) {
961		for (i = 0; i < FXP_NRFABUFS; i++) {
962			rxp = &sc->fxp_desc.rx_list[i];
963			if (rxp->rx_mbuf != NULL) {
964				bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
965				    BUS_DMASYNC_POSTREAD);
966				bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
967				m_freem(rxp->rx_mbuf);
968			}
969			bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
970		}
971		bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
972		bus_dma_tag_destroy(sc->fxp_rxmtag);
973	}
974	if (sc->fxp_txmtag) {
975		for (i = 0; i < FXP_NTXCB; i++) {
976			txp = &sc->fxp_desc.tx_list[i];
977			if (txp->tx_mbuf != NULL) {
978				bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
979				    BUS_DMASYNC_POSTWRITE);
980				bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
981				m_freem(txp->tx_mbuf);
982			}
983			bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
984		}
985		bus_dma_tag_destroy(sc->fxp_txmtag);
986	}
987	if (sc->fxp_stag)
988		bus_dma_tag_destroy(sc->fxp_stag);
989	if (sc->cbl_tag)
990		bus_dma_tag_destroy(sc->cbl_tag);
991	if (sc->mcs_tag)
992		bus_dma_tag_destroy(sc->mcs_tag);
993	if (sc->ifp)
994		if_free(sc->ifp);
995
996	mtx_destroy(&sc->sc_mtx);
997}
998
999/*
1000 * Detach interface.
1001 */
1002static int
1003fxp_detach(device_t dev)
1004{
1005	struct fxp_softc *sc = device_get_softc(dev);
1006
1007#ifdef DEVICE_POLLING
1008	if (sc->ifp->if_capenable & IFCAP_POLLING)
1009		ether_poll_deregister(sc->ifp);
1010#endif
1011
1012	FXP_LOCK(sc);
1013	/*
1014	 * Stop DMA and drop transmit queue, but disable interrupts first.
1015	 */
1016	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1017	fxp_stop(sc);
1018	FXP_UNLOCK(sc);
1019	callout_drain(&sc->stat_ch);
1020
1021	/*
1022	 * Close down routes etc.
1023	 */
1024	ether_ifdetach(sc->ifp);
1025
1026	/*
1027	 * Unhook interrupt before dropping lock. This is to prevent
1028	 * races with fxp_intr().
1029	 */
1030	bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1031	sc->ih = NULL;
1032
1033	/* Release our allocated resources. */
1034	fxp_release(sc);
1035	return (0);
1036}
1037
1038/*
1039 * Device shutdown routine. Called at system shutdown after sync. The
1040 * main purpose of this routine is to shut off receiver DMA so that
1041 * kernel memory doesn't get clobbered during warmboot.
1042 */
1043static int
1044fxp_shutdown(device_t dev)
1045{
1046
1047	/*
1048	 * Make sure that DMA is disabled prior to reboot. Not doing
1049	 * do could allow DMA to corrupt kernel memory during the
1050	 * reboot before the driver initializes.
1051	 */
1052	return (fxp_suspend(dev));
1053}
1054
1055/*
1056 * Device suspend routine.  Stop the interface and save some PCI
1057 * settings in case the BIOS doesn't restore them properly on
1058 * resume.
1059 */
1060static int
1061fxp_suspend(device_t dev)
1062{
1063	struct fxp_softc *sc = device_get_softc(dev);
1064	struct ifnet *ifp;
1065	int pmc;
1066	uint16_t pmstat;
1067
1068	FXP_LOCK(sc);
1069
1070	ifp = sc->ifp;
1071	if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1072		pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1073		pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1074		if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1075			/* Request PME. */
1076			pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1077			sc->flags |= FXP_FLAG_WOL;
1078			/* Reconfigure hardware to accept magic frames. */
1079			fxp_init_body(sc, 1);
1080		}
1081		pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1082	}
1083	fxp_stop(sc);
1084
1085	sc->suspended = 1;
1086
1087	FXP_UNLOCK(sc);
1088	return (0);
1089}
1090
1091/*
1092 * Device resume routine. re-enable busmastering, and restart the interface if
1093 * appropriate.
1094 */
1095static int
1096fxp_resume(device_t dev)
1097{
1098	struct fxp_softc *sc = device_get_softc(dev);
1099	struct ifnet *ifp = sc->ifp;
1100	int pmc;
1101	uint16_t pmstat;
1102
1103	FXP_LOCK(sc);
1104
1105	if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1106		sc->flags &= ~FXP_FLAG_WOL;
1107		pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1108		/* Disable PME and clear PME status. */
1109		pmstat &= ~PCIM_PSTAT_PMEENABLE;
1110		pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1111		if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1112			CSR_WRITE_1(sc, FXP_CSR_PMDR,
1113			    CSR_READ_1(sc, FXP_CSR_PMDR));
1114	}
1115
1116	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1117	DELAY(10);
1118
1119	/* reinitialize interface if necessary */
1120	if (ifp->if_flags & IFF_UP)
1121		fxp_init_body(sc, 1);
1122
1123	sc->suspended = 0;
1124
1125	FXP_UNLOCK(sc);
1126	return (0);
1127}
1128
1129static void
1130fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1131{
1132	uint16_t reg;
1133	int x;
1134
1135	/*
1136	 * Shift in data.
1137	 */
1138	for (x = 1 << (length - 1); x; x >>= 1) {
1139		if (data & x)
1140			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1141		else
1142			reg = FXP_EEPROM_EECS;
1143		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1144		DELAY(1);
1145		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1146		DELAY(1);
1147		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1148		DELAY(1);
1149	}
1150}
1151
1152/*
1153 * Read from the serial EEPROM. Basically, you manually shift in
1154 * the read opcode (one bit at a time) and then shift in the address,
1155 * and then you shift out the data (all of this one bit at a time).
1156 * The word size is 16 bits, so you have to provide the address for
1157 * every 16 bits of data.
1158 */
1159static uint16_t
1160fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1161{
1162	uint16_t reg, data;
1163	int x;
1164
1165	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1166	/*
1167	 * Shift in read opcode.
1168	 */
1169	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1170	/*
1171	 * Shift in address.
1172	 */
1173	data = 0;
1174	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1175		if (offset & x)
1176			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1177		else
1178			reg = FXP_EEPROM_EECS;
1179		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1180		DELAY(1);
1181		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1182		DELAY(1);
1183		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1184		DELAY(1);
1185		reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1186		data++;
1187		if (autosize && reg == 0) {
1188			sc->eeprom_size = data;
1189			break;
1190		}
1191	}
1192	/*
1193	 * Shift out data.
1194	 */
1195	data = 0;
1196	reg = FXP_EEPROM_EECS;
1197	for (x = 1 << 15; x; x >>= 1) {
1198		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1199		DELAY(1);
1200		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1201			data |= x;
1202		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1203		DELAY(1);
1204	}
1205	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1206	DELAY(1);
1207
1208	return (data);
1209}
1210
1211static void
1212fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1213{
1214	int i;
1215
1216	/*
1217	 * Erase/write enable.
1218	 */
1219	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1220	fxp_eeprom_shiftin(sc, 0x4, 3);
1221	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1222	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1223	DELAY(1);
1224	/*
1225	 * Shift in write opcode, address, data.
1226	 */
1227	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1228	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1229	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1230	fxp_eeprom_shiftin(sc, data, 16);
1231	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1232	DELAY(1);
1233	/*
1234	 * Wait for EEPROM to finish up.
1235	 */
1236	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1237	DELAY(1);
1238	for (i = 0; i < 1000; i++) {
1239		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1240			break;
1241		DELAY(50);
1242	}
1243	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1244	DELAY(1);
1245	/*
1246	 * Erase/write disable.
1247	 */
1248	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1249	fxp_eeprom_shiftin(sc, 0x4, 3);
1250	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1251	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1252	DELAY(1);
1253}
1254
1255/*
1256 * From NetBSD:
1257 *
1258 * Figure out EEPROM size.
1259 *
1260 * 559's can have either 64-word or 256-word EEPROMs, the 558
1261 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1262 * talks about the existance of 16 to 256 word EEPROMs.
1263 *
1264 * The only known sizes are 64 and 256, where the 256 version is used
1265 * by CardBus cards to store CIS information.
1266 *
1267 * The address is shifted in msb-to-lsb, and after the last
1268 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1269 * after which follows the actual data. We try to detect this zero, by
1270 * probing the data-out bit in the EEPROM control register just after
1271 * having shifted in a bit. If the bit is zero, we assume we've
1272 * shifted enough address bits. The data-out should be tri-state,
1273 * before this, which should translate to a logical one.
1274 */
1275static void
1276fxp_autosize_eeprom(struct fxp_softc *sc)
1277{
1278
1279	/* guess maximum size of 256 words */
1280	sc->eeprom_size = 8;
1281
1282	/* autosize */
1283	(void) fxp_eeprom_getword(sc, 0, 1);
1284}
1285
1286static void
1287fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1288{
1289	int i;
1290
1291	for (i = 0; i < words; i++)
1292		data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1293}
1294
1295static void
1296fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1297{
1298	int i;
1299
1300	for (i = 0; i < words; i++)
1301		fxp_eeprom_putword(sc, offset + i, data[i]);
1302}
1303
1304/*
1305 * Grab the softc lock and call the real fxp_start_body() routine
1306 */
1307static void
1308fxp_start(struct ifnet *ifp)
1309{
1310	struct fxp_softc *sc = ifp->if_softc;
1311
1312	FXP_LOCK(sc);
1313	fxp_start_body(ifp);
1314	FXP_UNLOCK(sc);
1315}
1316
1317/*
1318 * Start packet transmission on the interface.
1319 * This routine must be called with the softc lock held, and is an
1320 * internal entry point only.
1321 */
1322static void
1323fxp_start_body(struct ifnet *ifp)
1324{
1325	struct fxp_softc *sc = ifp->if_softc;
1326	struct mbuf *mb_head;
1327	int txqueued;
1328
1329	FXP_LOCK_ASSERT(sc, MA_OWNED);
1330
1331	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1332	    IFF_DRV_RUNNING)
1333		return;
1334
1335	if (sc->tx_queued > FXP_NTXCB_HIWAT)
1336		fxp_txeof(sc);
1337	/*
1338	 * We're finished if there is nothing more to add to the list or if
1339	 * we're all filled up with buffers to transmit.
1340	 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1341	 *       a NOP command when needed.
1342	 */
1343	txqueued = 0;
1344	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1345	    sc->tx_queued < FXP_NTXCB - 1) {
1346
1347		/*
1348		 * Grab a packet to transmit.
1349		 */
1350		IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1351		if (mb_head == NULL)
1352			break;
1353
1354		if (fxp_encap(sc, &mb_head)) {
1355			if (mb_head == NULL)
1356				break;
1357			IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1358			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1359		}
1360		txqueued++;
1361		/*
1362		 * Pass packet to bpf if there is a listener.
1363		 */
1364		BPF_MTAP(ifp, mb_head);
1365	}
1366
1367	/*
1368	 * We're finished. If we added to the list, issue a RESUME to get DMA
1369	 * going again if suspended.
1370	 */
1371	if (txqueued > 0) {
1372		bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1373		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1374		fxp_scb_wait(sc);
1375		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1376		/*
1377		 * Set a 5 second timer just in case we don't hear
1378		 * from the card again.
1379		 */
1380		sc->watchdog_timer = 5;
1381	}
1382}
1383
1384static int
1385fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1386{
1387	struct ifnet *ifp;
1388	struct mbuf *m;
1389	struct fxp_tx *txp;
1390	struct fxp_cb_tx *cbp;
1391	struct tcphdr *tcp;
1392	bus_dma_segment_t segs[FXP_NTXSEG];
1393	int error, i, nseg, tcp_payload;
1394
1395	FXP_LOCK_ASSERT(sc, MA_OWNED);
1396	ifp = sc->ifp;
1397
1398	tcp_payload = 0;
1399	tcp = NULL;
1400	/*
1401	 * Get pointer to next available tx desc.
1402	 */
1403	txp = sc->fxp_desc.tx_last->tx_next;
1404
1405	/*
1406	 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1407	 * Ethernet Controller Family Open Source Software
1408	 * Developer Manual says:
1409	 *   Using software parsing is only allowed with legal
1410	 *   TCP/IP or UDP/IP packets.
1411	 *   ...
1412	 *   For all other datagrams, hardware parsing must
1413	 *   be used.
1414	 * Software parsing appears to truncate ICMP and
1415	 * fragmented UDP packets that contain one to three
1416	 * bytes in the second (and final) mbuf of the packet.
1417	 */
1418	if (sc->flags & FXP_FLAG_EXT_RFA)
1419		txp->tx_cb->ipcb_ip_activation_high =
1420		    FXP_IPCB_HARDWAREPARSING_ENABLE;
1421
1422	m = *m_head;
1423	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1424		/*
1425		 * 82550/82551 requires ethernet/IP/TCP headers must be
1426		 * contained in the first active transmit buffer.
1427		 */
1428		struct ether_header *eh;
1429		struct ip *ip;
1430		uint32_t ip_off, poff;
1431
1432		if (M_WRITABLE(*m_head) == 0) {
1433			/* Get a writable copy. */
1434			m = m_dup(*m_head, M_DONTWAIT);
1435			m_freem(*m_head);
1436			if (m == NULL) {
1437				*m_head = NULL;
1438				return (ENOBUFS);
1439			}
1440			*m_head = m;
1441		}
1442		ip_off = sizeof(struct ether_header);
1443		m = m_pullup(*m_head, ip_off);
1444		if (m == NULL) {
1445			*m_head = NULL;
1446			return (ENOBUFS);
1447		}
1448		eh = mtod(m, struct ether_header *);
1449		/* Check the existence of VLAN tag. */
1450		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1451			ip_off = sizeof(struct ether_vlan_header);
1452			m = m_pullup(m, ip_off);
1453			if (m == NULL) {
1454				*m_head = NULL;
1455				return (ENOBUFS);
1456			}
1457		}
1458		m = m_pullup(m, ip_off + sizeof(struct ip));
1459		if (m == NULL) {
1460			*m_head = NULL;
1461			return (ENOBUFS);
1462		}
1463		ip = (struct ip *)(mtod(m, char *) + ip_off);
1464		poff = ip_off + (ip->ip_hl << 2);
1465		m = m_pullup(m, poff + sizeof(struct tcphdr));
1466		if (m == NULL) {
1467			*m_head = NULL;
1468			return (ENOBUFS);
1469		}
1470		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1471		m = m_pullup(m, poff + (tcp->th_off << 2));
1472		if (m == NULL) {
1473			*m_head = NULL;
1474			return (ENOBUFS);
1475		}
1476
1477		/*
1478		 * Since 82550/82551 doesn't modify IP length and pseudo
1479		 * checksum in the first frame driver should compute it.
1480		 */
1481		ip = (struct ip *)(mtod(m, char *) + ip_off);
1482		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1483		ip->ip_sum = 0;
1484		ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1485		    (tcp->th_off << 2));
1486		tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1487		    htons(IPPROTO_TCP + (tcp->th_off << 2) +
1488		    m->m_pkthdr.tso_segsz));
1489		/* Compute total TCP payload. */
1490		tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1491		tcp_payload -= tcp->th_off << 2;
1492		*m_head = m;
1493	} else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1494		/*
1495		 * Deal with TCP/IP checksum offload. Note that
1496		 * in order for TCP checksum offload to work,
1497		 * the pseudo header checksum must have already
1498		 * been computed and stored in the checksum field
1499		 * in the TCP header. The stack should have
1500		 * already done this for us.
1501		 */
1502		txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1503		if (m->m_pkthdr.csum_flags & CSUM_TCP)
1504			txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1505
1506#ifdef FXP_IP_CSUM_WAR
1507		/*
1508		 * XXX The 82550 chip appears to have trouble
1509		 * dealing with IP header checksums in very small
1510		 * datagrams, namely fragments from 1 to 3 bytes
1511		 * in size. For example, say you want to transmit
1512		 * a UDP packet of 1473 bytes. The packet will be
1513		 * fragmented over two IP datagrams, the latter
1514		 * containing only one byte of data. The 82550 will
1515		 * botch the header checksum on the 1-byte fragment.
1516		 * As long as the datagram contains 4 or more bytes
1517		 * of data, you're ok.
1518		 *
1519                 * The following code attempts to work around this
1520		 * problem: if the datagram is less than 38 bytes
1521		 * in size (14 bytes ether header, 20 bytes IP header,
1522		 * plus 4 bytes of data), we punt and compute the IP
1523		 * header checksum by hand. This workaround doesn't
1524		 * work very well, however, since it can be fooled
1525		 * by things like VLAN tags and IP options that make
1526		 * the header sizes/offsets vary.
1527		 */
1528
1529		if (m->m_pkthdr.csum_flags & CSUM_IP) {
1530			if (m->m_pkthdr.len < 38) {
1531				struct ip *ip;
1532				m->m_data += ETHER_HDR_LEN;
1533				ip = mtod(m, struct ip *);
1534				ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1535				m->m_data -= ETHER_HDR_LEN;
1536				m->m_pkthdr.csum_flags &= ~CSUM_IP;
1537			} else {
1538				txp->tx_cb->ipcb_ip_activation_high =
1539				    FXP_IPCB_HARDWAREPARSING_ENABLE;
1540				txp->tx_cb->ipcb_ip_schedule |=
1541				    FXP_IPCB_IP_CHECKSUM_ENABLE;
1542			}
1543		}
1544#endif
1545	}
1546
1547	error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1548	    segs, &nseg, 0);
1549	if (error == EFBIG) {
1550		m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg);
1551		if (m == NULL) {
1552			m_freem(*m_head);
1553			*m_head = NULL;
1554			return (ENOMEM);
1555		}
1556		*m_head = m;
1557		error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1558		    *m_head, segs, &nseg, 0);
1559		if (error != 0) {
1560			m_freem(*m_head);
1561			*m_head = NULL;
1562			return (ENOMEM);
1563		}
1564	} else if (error != 0)
1565		return (error);
1566	if (nseg == 0) {
1567		m_freem(*m_head);
1568		*m_head = NULL;
1569		return (EIO);
1570	}
1571
1572	KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1573	bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1574
1575	cbp = txp->tx_cb;
1576	for (i = 0; i < nseg; i++) {
1577		/*
1578		 * If this is an 82550/82551, then we're using extended
1579		 * TxCBs _and_ we're using checksum offload. This means
1580		 * that the TxCB is really an IPCB. One major difference
1581		 * between the two is that with plain extended TxCBs,
1582		 * the bottom half of the TxCB contains two entries from
1583		 * the TBD array, whereas IPCBs contain just one entry:
1584		 * one entry (8 bytes) has been sacrificed for the TCP/IP
1585		 * checksum offload control bits. So to make things work
1586		 * right, we have to start filling in the TBD array
1587		 * starting from a different place depending on whether
1588		 * the chip is an 82550/82551 or not.
1589		 */
1590		if (sc->flags & FXP_FLAG_EXT_RFA) {
1591			cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1592			cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1593		} else {
1594			cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1595			cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1596		}
1597	}
1598	if (sc->flags & FXP_FLAG_EXT_RFA) {
1599		/* Configure dynamic TBD for 82550/82551. */
1600		cbp->tbd_number = 0xFF;
1601		cbp->tbd[nseg].tb_size |= htole32(0x8000);
1602	} else
1603		cbp->tbd_number = nseg;
1604	/* Configure TSO. */
1605	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1606		cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1607		cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1608		cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1609		    FXP_IPCB_IP_CHECKSUM_ENABLE |
1610		    FXP_IPCB_TCP_PACKET |
1611		    FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1612	}
1613	/* Configure VLAN hardware tag insertion. */
1614	if ((m->m_flags & M_VLANTAG) != 0) {
1615		cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1616		txp->tx_cb->ipcb_ip_activation_high |=
1617		    FXP_IPCB_INSERTVLAN_ENABLE;
1618	}
1619
1620	txp->tx_mbuf = m;
1621	txp->tx_cb->cb_status = 0;
1622	txp->tx_cb->byte_count = 0;
1623	if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1624		txp->tx_cb->cb_command =
1625		    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1626		    FXP_CB_COMMAND_S);
1627	else
1628		txp->tx_cb->cb_command =
1629		    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1630		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1631	if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1632		txp->tx_cb->tx_threshold = tx_threshold;
1633
1634	/*
1635	 * Advance the end of list forward.
1636	 */
1637	sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1638	sc->fxp_desc.tx_last = txp;
1639
1640	/*
1641	 * Advance the beginning of the list forward if there are
1642	 * no other packets queued (when nothing is queued, tx_first
1643	 * sits on the last TxCB that was sent out).
1644	 */
1645	if (sc->tx_queued == 0)
1646		sc->fxp_desc.tx_first = txp;
1647
1648	sc->tx_queued++;
1649
1650	return (0);
1651}
1652
1653#ifdef DEVICE_POLLING
1654static poll_handler_t fxp_poll;
1655
1656static int
1657fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1658{
1659	struct fxp_softc *sc = ifp->if_softc;
1660	uint8_t statack;
1661	int rx_npkts = 0;
1662
1663	FXP_LOCK(sc);
1664	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1665		FXP_UNLOCK(sc);
1666		return (rx_npkts);
1667	}
1668
1669	statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1670	    FXP_SCB_STATACK_FR;
1671	if (cmd == POLL_AND_CHECK_STATUS) {
1672		uint8_t tmp;
1673
1674		tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1675		if (tmp == 0xff || tmp == 0) {
1676			FXP_UNLOCK(sc);
1677			return (rx_npkts); /* nothing to do */
1678		}
1679		tmp &= ~statack;
1680		/* ack what we can */
1681		if (tmp != 0)
1682			CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1683		statack |= tmp;
1684	}
1685	rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1686	FXP_UNLOCK(sc);
1687	return (rx_npkts);
1688}
1689#endif /* DEVICE_POLLING */
1690
1691/*
1692 * Process interface interrupts.
1693 */
1694static void
1695fxp_intr(void *xsc)
1696{
1697	struct fxp_softc *sc = xsc;
1698	struct ifnet *ifp = sc->ifp;
1699	uint8_t statack;
1700
1701	FXP_LOCK(sc);
1702	if (sc->suspended) {
1703		FXP_UNLOCK(sc);
1704		return;
1705	}
1706
1707#ifdef DEVICE_POLLING
1708	if (ifp->if_capenable & IFCAP_POLLING) {
1709		FXP_UNLOCK(sc);
1710		return;
1711	}
1712#endif
1713	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1714		/*
1715		 * It should not be possible to have all bits set; the
1716		 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1717		 * all bits are set, this may indicate that the card has
1718		 * been physically ejected, so ignore it.
1719		 */
1720		if (statack == 0xff) {
1721			FXP_UNLOCK(sc);
1722			return;
1723		}
1724
1725		/*
1726		 * First ACK all the interrupts in this pass.
1727		 */
1728		CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1729		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1730			fxp_intr_body(sc, ifp, statack, -1);
1731	}
1732	FXP_UNLOCK(sc);
1733}
1734
1735static void
1736fxp_txeof(struct fxp_softc *sc)
1737{
1738	struct ifnet *ifp;
1739	struct fxp_tx *txp;
1740
1741	ifp = sc->ifp;
1742	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1743	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1744	for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1745	    (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1746	    txp = txp->tx_next) {
1747		if (txp->tx_mbuf != NULL) {
1748			bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1749			    BUS_DMASYNC_POSTWRITE);
1750			bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1751			m_freem(txp->tx_mbuf);
1752			txp->tx_mbuf = NULL;
1753			/* clear this to reset csum offload bits */
1754			txp->tx_cb->tbd[0].tb_addr = 0;
1755		}
1756		sc->tx_queued--;
1757		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1758	}
1759	sc->fxp_desc.tx_first = txp;
1760	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1761	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1762	if (sc->tx_queued == 0)
1763		sc->watchdog_timer = 0;
1764}
1765
1766static void
1767fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1768    uint16_t status, int pos)
1769{
1770	struct ether_header *eh;
1771	struct ip *ip;
1772	struct udphdr *uh;
1773	int32_t hlen, len, pktlen, temp32;
1774	uint16_t csum, *opts;
1775
1776	if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1777		if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1778			if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1779				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1780			if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1781				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1782			if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1783			    (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1784				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1785				    CSUM_PSEUDO_HDR;
1786				m->m_pkthdr.csum_data = 0xffff;
1787			}
1788		}
1789		return;
1790	}
1791
1792	pktlen = m->m_pkthdr.len;
1793	if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1794		return;
1795	eh = mtod(m, struct ether_header *);
1796	if (eh->ether_type != htons(ETHERTYPE_IP))
1797		return;
1798	ip = (struct ip *)(eh + 1);
1799	if (ip->ip_v != IPVERSION)
1800		return;
1801
1802	hlen = ip->ip_hl << 2;
1803	pktlen -= sizeof(struct ether_header);
1804	if (hlen < sizeof(struct ip))
1805		return;
1806	if (ntohs(ip->ip_len) < hlen)
1807		return;
1808	if (ntohs(ip->ip_len) != pktlen)
1809		return;
1810	if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1811		return;	/* can't handle fragmented packet */
1812
1813	switch (ip->ip_p) {
1814	case IPPROTO_TCP:
1815		if (pktlen < (hlen + sizeof(struct tcphdr)))
1816			return;
1817		break;
1818	case IPPROTO_UDP:
1819		if (pktlen < (hlen + sizeof(struct udphdr)))
1820			return;
1821		uh = (struct udphdr *)((caddr_t)ip + hlen);
1822		if (uh->uh_sum == 0)
1823			return; /* no checksum */
1824		break;
1825	default:
1826		return;
1827	}
1828	/* Extract computed checksum. */
1829	csum = be16dec(mtod(m, char *) + pos);
1830	/* checksum fixup for IP options */
1831	len = hlen - sizeof(struct ip);
1832	if (len > 0) {
1833		opts = (uint16_t *)(ip + 1);
1834		for (; len > 0; len -= sizeof(uint16_t), opts++) {
1835			temp32 = csum - *opts;
1836			temp32 = (temp32 >> 16) + (temp32 & 65535);
1837			csum = temp32 & 65535;
1838		}
1839	}
1840	m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1841	m->m_pkthdr.csum_data = csum;
1842}
1843
1844static int
1845fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1846    int count)
1847{
1848	struct mbuf *m;
1849	struct fxp_rx *rxp;
1850	struct fxp_rfa *rfa;
1851	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1852	int rx_npkts;
1853	uint16_t status;
1854
1855	rx_npkts = 0;
1856	FXP_LOCK_ASSERT(sc, MA_OWNED);
1857
1858	if (rnr)
1859		sc->rnr++;
1860#ifdef DEVICE_POLLING
1861	/* Pick up a deferred RNR condition if `count' ran out last time. */
1862	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1863		sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1864		rnr = 1;
1865	}
1866#endif
1867
1868	/*
1869	 * Free any finished transmit mbuf chains.
1870	 *
1871	 * Handle the CNA event likt a CXTNO event. It used to
1872	 * be that this event (control unit not ready) was not
1873	 * encountered, but it is now with the SMPng modifications.
1874	 * The exact sequence of events that occur when the interface
1875	 * is brought up are different now, and if this event
1876	 * goes unhandled, the configuration/rxfilter setup sequence
1877	 * can stall for several seconds. The result is that no
1878	 * packets go out onto the wire for about 5 to 10 seconds
1879	 * after the interface is ifconfig'ed for the first time.
1880	 */
1881	if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1882		fxp_txeof(sc);
1883
1884	/*
1885	 * Try to start more packets transmitting.
1886	 */
1887	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1888		fxp_start_body(ifp);
1889
1890	/*
1891	 * Just return if nothing happened on the receive side.
1892	 */
1893	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1894		return (rx_npkts);
1895
1896	/*
1897	 * Process receiver interrupts. If a no-resource (RNR)
1898	 * condition exists, get whatever packets we can and
1899	 * re-start the receiver.
1900	 *
1901	 * When using polling, we do not process the list to completion,
1902	 * so when we get an RNR interrupt we must defer the restart
1903	 * until we hit the last buffer with the C bit set.
1904	 * If we run out of cycles and rfa_headm has the C bit set,
1905	 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1906	 * that the info will be used in the subsequent polling cycle.
1907	 */
1908	for (;;) {
1909		rxp = sc->fxp_desc.rx_head;
1910		m = rxp->rx_mbuf;
1911		rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1912		    RFA_ALIGNMENT_FUDGE);
1913		bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1914		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1915
1916#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1917		if (count >= 0 && count-- == 0) {
1918			if (rnr) {
1919				/* Defer RNR processing until the next time. */
1920				sc->flags |= FXP_FLAG_DEFERRED_RNR;
1921				rnr = 0;
1922			}
1923			break;
1924		}
1925#endif /* DEVICE_POLLING */
1926
1927		status = le16toh(rfa->rfa_status);
1928		if ((status & FXP_RFA_STATUS_C) == 0)
1929			break;
1930
1931		if ((status & FXP_RFA_STATUS_RNR) != 0)
1932			rnr++;
1933		/*
1934		 * Advance head forward.
1935		 */
1936		sc->fxp_desc.rx_head = rxp->rx_next;
1937
1938		/*
1939		 * Add a new buffer to the receive chain.
1940		 * If this fails, the old buffer is recycled
1941		 * instead.
1942		 */
1943		if (fxp_new_rfabuf(sc, rxp) == 0) {
1944			int total_len;
1945
1946			/*
1947			 * Fetch packet length (the top 2 bits of
1948			 * actual_size are flags set by the controller
1949			 * upon completion), and drop the packet in case
1950			 * of bogus length or CRC errors.
1951			 */
1952			total_len = le16toh(rfa->actual_size) & 0x3fff;
1953			if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1954			    (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1955				/* Adjust for appended checksum bytes. */
1956				total_len -= 2;
1957			}
1958			if (total_len < (int)sizeof(struct ether_header) ||
1959			    total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1960			    sc->rfa_size) ||
1961			    status & (FXP_RFA_STATUS_CRC |
1962			    FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1963				m_freem(m);
1964				fxp_add_rfabuf(sc, rxp);
1965				continue;
1966			}
1967
1968			m->m_pkthdr.len = m->m_len = total_len;
1969			m->m_pkthdr.rcvif = ifp;
1970
1971                        /* Do IP checksum checking. */
1972			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1973				fxp_rxcsum(sc, ifp, m, status, total_len);
1974			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1975			    (status & FXP_RFA_STATUS_VLAN) != 0) {
1976				m->m_pkthdr.ether_vtag =
1977				    ntohs(rfa->rfax_vlan_id);
1978				m->m_flags |= M_VLANTAG;
1979			}
1980			/*
1981			 * Drop locks before calling if_input() since it
1982			 * may re-enter fxp_start() in the netisr case.
1983			 * This would result in a lock reversal.  Better
1984			 * performance might be obtained by chaining all
1985			 * packets received, dropping the lock, and then
1986			 * calling if_input() on each one.
1987			 */
1988			FXP_UNLOCK(sc);
1989			(*ifp->if_input)(ifp, m);
1990			FXP_LOCK(sc);
1991			rx_npkts++;
1992			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1993				return (rx_npkts);
1994		} else {
1995			/* Reuse RFA and loaded DMA map. */
1996			ifp->if_iqdrops++;
1997			fxp_discard_rfabuf(sc, rxp);
1998		}
1999		fxp_add_rfabuf(sc, rxp);
2000	}
2001	if (rnr) {
2002		fxp_scb_wait(sc);
2003		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2004		    sc->fxp_desc.rx_head->rx_addr);
2005		fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2006	}
2007	return (rx_npkts);
2008}
2009
2010static void
2011fxp_update_stats(struct fxp_softc *sc)
2012{
2013	struct ifnet *ifp = sc->ifp;
2014	struct fxp_stats *sp = sc->fxp_stats;
2015	struct fxp_hwstats *hsp;
2016	uint32_t *status;
2017
2018	FXP_LOCK_ASSERT(sc, MA_OWNED);
2019
2020	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2021	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2022	/* Update statistical counters. */
2023	if (sc->revision >= FXP_REV_82559_A0)
2024		status = &sp->completion_status;
2025	else if (sc->revision >= FXP_REV_82558_A4)
2026		status = (uint32_t *)&sp->tx_tco;
2027	else
2028		status = &sp->tx_pause;
2029	if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2030		hsp = &sc->fxp_hwstats;
2031		hsp->tx_good += le32toh(sp->tx_good);
2032		hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2033		hsp->tx_latecols += le32toh(sp->tx_latecols);
2034		hsp->tx_underruns += le32toh(sp->tx_underruns);
2035		hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2036		hsp->tx_deffered += le32toh(sp->tx_deffered);
2037		hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2038		hsp->tx_multiple_collisions +=
2039		    le32toh(sp->tx_multiple_collisions);
2040		hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2041		hsp->rx_good += le32toh(sp->rx_good);
2042		hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2043		hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2044		hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2045		hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2046		hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2047		hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2048		hsp->tx_pause += le32toh(sp->tx_pause);
2049		hsp->rx_pause += le32toh(sp->rx_pause);
2050		hsp->rx_controls += le32toh(sp->rx_controls);
2051		hsp->tx_tco += le16toh(sp->tx_tco);
2052		hsp->rx_tco += le16toh(sp->rx_tco);
2053
2054		ifp->if_opackets += le32toh(sp->tx_good);
2055		ifp->if_collisions += le32toh(sp->tx_total_collisions);
2056		if (sp->rx_good) {
2057			ifp->if_ipackets += le32toh(sp->rx_good);
2058			sc->rx_idle_secs = 0;
2059		} else if (sc->flags & FXP_FLAG_RXBUG) {
2060			/*
2061			 * Receiver's been idle for another second.
2062			 */
2063			sc->rx_idle_secs++;
2064		}
2065		ifp->if_ierrors +=
2066		    le32toh(sp->rx_crc_errors) +
2067		    le32toh(sp->rx_alignment_errors) +
2068		    le32toh(sp->rx_rnr_errors) +
2069		    le32toh(sp->rx_overrun_errors);
2070		/*
2071		 * If any transmit underruns occured, bump up the transmit
2072		 * threshold by another 512 bytes (64 * 8).
2073		 */
2074		if (sp->tx_underruns) {
2075			ifp->if_oerrors += le32toh(sp->tx_underruns);
2076			if (tx_threshold < 192)
2077				tx_threshold += 64;
2078		}
2079		*status = 0;
2080		bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2081		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2082	}
2083}
2084
2085/*
2086 * Update packet in/out/collision statistics. The i82557 doesn't
2087 * allow you to access these counters without doing a fairly
2088 * expensive DMA to get _all_ of the statistics it maintains, so
2089 * we do this operation here only once per second. The statistics
2090 * counters in the kernel are updated from the previous dump-stats
2091 * DMA and then a new dump-stats DMA is started. The on-chip
2092 * counters are zeroed when the DMA completes. If we can't start
2093 * the DMA immediately, we don't wait - we just prepare to read
2094 * them again next time.
2095 */
2096static void
2097fxp_tick(void *xsc)
2098{
2099	struct fxp_softc *sc = xsc;
2100	struct ifnet *ifp = sc->ifp;
2101
2102	FXP_LOCK_ASSERT(sc, MA_OWNED);
2103
2104	/* Update statistical counters. */
2105	fxp_update_stats(sc);
2106
2107	/*
2108	 * Release any xmit buffers that have completed DMA. This isn't
2109	 * strictly necessary to do here, but it's advantagous for mbufs
2110	 * with external storage to be released in a timely manner rather
2111	 * than being defered for a potentially long time. This limits
2112	 * the delay to a maximum of one second.
2113	 */
2114	fxp_txeof(sc);
2115
2116	/*
2117	 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2118	 * then assume the receiver has locked up and attempt to clear
2119	 * the condition by reprogramming the multicast filter. This is
2120	 * a work-around for a bug in the 82557 where the receiver locks
2121	 * up if it gets certain types of garbage in the syncronization
2122	 * bits prior to the packet header. This bug is supposed to only
2123	 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2124	 * mode as well (perhaps due to a 10/100 speed transition).
2125	 */
2126	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2127		sc->rx_idle_secs = 0;
2128		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2129			fxp_init_body(sc, 1);
2130		return;
2131	}
2132	/*
2133	 * If there is no pending command, start another stats
2134	 * dump. Otherwise punt for now.
2135	 */
2136	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2137		/*
2138		 * Start another stats dump.
2139		 */
2140		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2141	}
2142	if (sc->miibus != NULL)
2143		mii_tick(device_get_softc(sc->miibus));
2144
2145	/*
2146	 * Check that chip hasn't hung.
2147	 */
2148	fxp_watchdog(sc);
2149
2150	/*
2151	 * Schedule another timeout one second from now.
2152	 */
2153	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2154}
2155
2156/*
2157 * Stop the interface. Cancels the statistics updater and resets
2158 * the interface.
2159 */
2160static void
2161fxp_stop(struct fxp_softc *sc)
2162{
2163	struct ifnet *ifp = sc->ifp;
2164	struct fxp_tx *txp;
2165	int i;
2166
2167	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2168	sc->watchdog_timer = 0;
2169
2170	/*
2171	 * Cancel stats updater.
2172	 */
2173	callout_stop(&sc->stat_ch);
2174
2175	/*
2176	 * Preserve PCI configuration, configure, IA/multicast
2177	 * setup and put RU and CU into idle state.
2178	 */
2179	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2180	DELAY(50);
2181	/* Disable interrupts. */
2182	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2183
2184	fxp_update_stats(sc);
2185
2186	/*
2187	 * Release any xmit buffers.
2188	 */
2189	txp = sc->fxp_desc.tx_list;
2190	if (txp != NULL) {
2191		for (i = 0; i < FXP_NTXCB; i++) {
2192			if (txp[i].tx_mbuf != NULL) {
2193				bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2194				    BUS_DMASYNC_POSTWRITE);
2195				bus_dmamap_unload(sc->fxp_txmtag,
2196				    txp[i].tx_map);
2197				m_freem(txp[i].tx_mbuf);
2198				txp[i].tx_mbuf = NULL;
2199				/* clear this to reset csum offload bits */
2200				txp[i].tx_cb->tbd[0].tb_addr = 0;
2201			}
2202		}
2203	}
2204	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2205	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2206	sc->tx_queued = 0;
2207}
2208
2209/*
2210 * Watchdog/transmission transmit timeout handler. Called when a
2211 * transmission is started on the interface, but no interrupt is
2212 * received before the timeout. This usually indicates that the
2213 * card has wedged for some reason.
2214 */
2215static void
2216fxp_watchdog(struct fxp_softc *sc)
2217{
2218
2219	FXP_LOCK_ASSERT(sc, MA_OWNED);
2220
2221	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2222		return;
2223
2224	device_printf(sc->dev, "device timeout\n");
2225	sc->ifp->if_oerrors++;
2226
2227	fxp_init_body(sc, 1);
2228}
2229
2230/*
2231 * Acquire locks and then call the real initialization function.  This
2232 * is necessary because ether_ioctl() calls if_init() and this would
2233 * result in mutex recursion if the mutex was held.
2234 */
2235static void
2236fxp_init(void *xsc)
2237{
2238	struct fxp_softc *sc = xsc;
2239
2240	FXP_LOCK(sc);
2241	fxp_init_body(sc, 1);
2242	FXP_UNLOCK(sc);
2243}
2244
2245/*
2246 * Perform device initialization. This routine must be called with the
2247 * softc lock held.
2248 */
2249static void
2250fxp_init_body(struct fxp_softc *sc, int setmedia)
2251{
2252	struct ifnet *ifp = sc->ifp;
2253	struct mii_data *mii;
2254	struct fxp_cb_config *cbp;
2255	struct fxp_cb_ias *cb_ias;
2256	struct fxp_cb_tx *tcbp;
2257	struct fxp_tx *txp;
2258	int i, prm;
2259
2260	FXP_LOCK_ASSERT(sc, MA_OWNED);
2261	/*
2262	 * Cancel any pending I/O
2263	 */
2264	fxp_stop(sc);
2265
2266	/*
2267	 * Issue software reset, which also unloads the microcode.
2268	 */
2269	sc->flags &= ~FXP_FLAG_UCODE;
2270	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2271	DELAY(50);
2272
2273	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2274
2275	/*
2276	 * Initialize base of CBL and RFA memory. Loading with zero
2277	 * sets it up for regular linear addressing.
2278	 */
2279	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2280	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2281
2282	fxp_scb_wait(sc);
2283	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2284
2285	/*
2286	 * Initialize base of dump-stats buffer.
2287	 */
2288	fxp_scb_wait(sc);
2289	bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2290	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2291	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2292	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2293	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2294
2295	/*
2296	 * Attempt to load microcode if requested.
2297	 * For ICH based controllers do not load microcode.
2298	 */
2299	if (sc->ident->ich == 0) {
2300		if (ifp->if_flags & IFF_LINK0 &&
2301		    (sc->flags & FXP_FLAG_UCODE) == 0)
2302			fxp_load_ucode(sc);
2303	}
2304
2305	/*
2306	 * Set IFF_ALLMULTI status. It's needed in configure action
2307	 * command.
2308	 */
2309	fxp_mc_addrs(sc);
2310
2311	/*
2312	 * We temporarily use memory that contains the TxCB list to
2313	 * construct the config CB. The TxCB list memory is rebuilt
2314	 * later.
2315	 */
2316	cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2317
2318	/*
2319	 * This bcopy is kind of disgusting, but there are a bunch of must be
2320	 * zero and must be one bits in this structure and this is the easiest
2321	 * way to initialize them all to proper values.
2322	 */
2323	bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2324
2325	cbp->cb_status =	0;
2326	cbp->cb_command =	htole16(FXP_CB_COMMAND_CONFIG |
2327	    FXP_CB_COMMAND_EL);
2328	cbp->link_addr =	0xffffffff;	/* (no) next command */
2329	cbp->byte_count =	sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2330	cbp->rx_fifo_limit =	8;	/* rx fifo threshold (32 bytes) */
2331	cbp->tx_fifo_limit =	0;	/* tx fifo threshold (0 bytes) */
2332	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
2333	cbp->mwi_enable =	sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2334	cbp->type_enable =	0;	/* actually reserved */
2335	cbp->read_align_en =	sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2336	cbp->end_wr_on_cl =	sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2337	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
2338	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
2339	cbp->dma_mbce =		0;	/* (disable) dma max counters */
2340	cbp->late_scb =		0;	/* (don't) defer SCB update */
2341	cbp->direct_dma_dis =	1;	/* disable direct rcv dma mode */
2342	cbp->tno_int_or_tco_en =0;	/* (disable) tx not okay interrupt */
2343	cbp->ci_int =		1;	/* interrupt on CU idle */
2344	cbp->ext_txcb_dis = 	sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2345	cbp->ext_stats_dis = 	1;	/* disable extended counters */
2346	cbp->keep_overrun_rx = 	0;	/* don't pass overrun frames to host */
2347	cbp->save_bf =		sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2348	cbp->disc_short_rx =	!prm;	/* discard short packets */
2349	cbp->underrun_retry =	1;	/* retry mode (once) on DMA underrun */
2350	cbp->two_frames =	0;	/* do not limit FIFO to 2 frames */
2351	cbp->dyn_tbd =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2352	cbp->ext_rfa =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2353	cbp->mediatype =	sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2354	cbp->csma_dis =		0;	/* (don't) disable link */
2355	cbp->tcp_udp_cksum =	((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2356	    (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2357	cbp->vlan_tco =		0;	/* (don't) enable vlan wakeup */
2358	cbp->link_wake_en =	0;	/* (don't) assert PME# on link change */
2359	cbp->arp_wake_en =	0;	/* (don't) assert PME# on arp */
2360	cbp->mc_wake_en =	0;	/* (don't) enable PME# on mcmatch */
2361	cbp->nsai =		1;	/* (don't) disable source addr insert */
2362	cbp->preamble_length =	2;	/* (7 byte) preamble */
2363	cbp->loopback =		0;	/* (don't) loopback */
2364	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
2365	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
2366	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
2367	cbp->promiscuous =	prm;	/* promiscuous mode */
2368	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
2369	cbp->wait_after_win =	0;	/* (don't) enable modified backoff alg*/
2370	cbp->ignore_ul =	0;	/* consider U/L bit in IA matching */
2371	cbp->crc16_en =		0;	/* (don't) enable crc-16 algorithm */
2372	cbp->crscdt =		sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2373
2374	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
2375	cbp->padding =		1;	/* (do) pad short tx packets */
2376	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
2377	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2378	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
2379	cbp->magic_pkt_dis =	sc->flags & FXP_FLAG_WOL ? 0 : 1;
2380	cbp->force_fdx =	0;	/* (don't) force full duplex */
2381	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
2382	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
2383	cbp->mc_all =		ifp->if_flags & IFF_ALLMULTI ? 1 : prm;
2384	cbp->gamla_rx =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2385	cbp->vlan_strip_en =	((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2386	    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2387
2388	if (sc->revision == FXP_REV_82557) {
2389		/*
2390		 * The 82557 has no hardware flow control, the values
2391		 * below are the defaults for the chip.
2392		 */
2393		cbp->fc_delay_lsb =	0;
2394		cbp->fc_delay_msb =	0x40;
2395		cbp->pri_fc_thresh =	3;
2396		cbp->tx_fc_dis =	0;
2397		cbp->rx_fc_restop =	0;
2398		cbp->rx_fc_restart =	0;
2399		cbp->fc_filter =	0;
2400		cbp->pri_fc_loc =	1;
2401	} else {
2402		/* Set pause RX FIFO threshold to 1KB. */
2403		CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2404		/* Set pause time. */
2405		cbp->fc_delay_lsb =	0xff;
2406		cbp->fc_delay_msb =	0xff;
2407		cbp->pri_fc_thresh =	3;
2408		mii = device_get_softc(sc->miibus);
2409		if ((IFM_OPTIONS(mii->mii_media_active) &
2410		    IFM_ETH_TXPAUSE) != 0)
2411			/* enable transmit FC */
2412			cbp->tx_fc_dis = 0;
2413		else
2414			/* disable transmit FC */
2415			cbp->tx_fc_dis = 1;
2416		if ((IFM_OPTIONS(mii->mii_media_active) &
2417		    IFM_ETH_RXPAUSE) != 0) {
2418			/* enable FC restart/restop frames */
2419			cbp->rx_fc_restart = 1;
2420			cbp->rx_fc_restop = 1;
2421		} else {
2422			/* disable FC restart/restop frames */
2423			cbp->rx_fc_restart = 0;
2424			cbp->rx_fc_restop = 0;
2425		}
2426		cbp->fc_filter =	!prm;	/* drop FC frames to host */
2427		cbp->pri_fc_loc =	1;	/* FC pri location (byte31) */
2428	}
2429
2430	/* Enable 82558 and 82559 extended statistics functionality. */
2431	if (sc->revision >= FXP_REV_82558_A4) {
2432		if (sc->revision >= FXP_REV_82559_A0) {
2433			/*
2434			 * Extend configuration table size to 32
2435			 * to include TCO configuration.
2436			 */
2437			cbp->byte_count = 32;
2438			cbp->ext_stats_dis = 1;
2439			/* Enable TCO stats. */
2440			cbp->tno_int_or_tco_en = 1;
2441			cbp->gamla_rx = 1;
2442		} else
2443			cbp->ext_stats_dis = 0;
2444	}
2445
2446	/*
2447	 * Start the config command/DMA.
2448	 */
2449	fxp_scb_wait(sc);
2450	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2451	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2452	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2453	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2454	/* ...and wait for it to complete. */
2455	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2456
2457	/*
2458	 * Now initialize the station address. Temporarily use the TxCB
2459	 * memory area like we did above for the config CB.
2460	 */
2461	cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2462	cb_ias->cb_status = 0;
2463	cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2464	cb_ias->link_addr = 0xffffffff;
2465	bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2466
2467	/*
2468	 * Start the IAS (Individual Address Setup) command/DMA.
2469	 */
2470	fxp_scb_wait(sc);
2471	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2472	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2473	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2474	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2475	/* ...and wait for it to complete. */
2476	fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2477
2478	/*
2479	 * Initialize the multicast address list.
2480	 */
2481	fxp_mc_setup(sc);
2482
2483	/*
2484	 * Initialize transmit control block (TxCB) list.
2485	 */
2486	txp = sc->fxp_desc.tx_list;
2487	tcbp = sc->fxp_desc.cbl_list;
2488	bzero(tcbp, FXP_TXCB_SZ);
2489	for (i = 0; i < FXP_NTXCB; i++) {
2490		txp[i].tx_mbuf = NULL;
2491		tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2492		tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2493		tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2494		    (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2495		if (sc->flags & FXP_FLAG_EXT_TXCB)
2496			tcbp[i].tbd_array_addr =
2497			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2498		else
2499			tcbp[i].tbd_array_addr =
2500			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2501		txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2502	}
2503	/*
2504	 * Set the suspend flag on the first TxCB and start the control
2505	 * unit. It will execute the NOP and then suspend.
2506	 */
2507	tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2508	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2509	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2510	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2511	sc->tx_queued = 1;
2512
2513	fxp_scb_wait(sc);
2514	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2515	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2516
2517	/*
2518	 * Initialize receiver buffer area - RFA.
2519	 */
2520	fxp_scb_wait(sc);
2521	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2522	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2523
2524	if (sc->miibus != NULL && setmedia != 0)
2525		mii_mediachg(device_get_softc(sc->miibus));
2526
2527	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2528	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2529
2530	/*
2531	 * Enable interrupts.
2532	 */
2533#ifdef DEVICE_POLLING
2534	/*
2535	 * ... but only do that if we are not polling. And because (presumably)
2536	 * the default is interrupts on, we need to disable them explicitly!
2537	 */
2538	if (ifp->if_capenable & IFCAP_POLLING )
2539		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2540	else
2541#endif /* DEVICE_POLLING */
2542	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2543
2544	/*
2545	 * Start stats updater.
2546	 */
2547	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2548}
2549
2550static int
2551fxp_serial_ifmedia_upd(struct ifnet *ifp)
2552{
2553
2554	return (0);
2555}
2556
2557static void
2558fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2559{
2560
2561	ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2562}
2563
2564/*
2565 * Change media according to request.
2566 */
2567static int
2568fxp_ifmedia_upd(struct ifnet *ifp)
2569{
2570	struct fxp_softc *sc = ifp->if_softc;
2571	struct mii_data *mii;
2572	struct mii_softc	*miisc;
2573
2574	mii = device_get_softc(sc->miibus);
2575	FXP_LOCK(sc);
2576	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2577		PHY_RESET(miisc);
2578	mii_mediachg(mii);
2579	FXP_UNLOCK(sc);
2580	return (0);
2581}
2582
2583/*
2584 * Notify the world which media we're using.
2585 */
2586static void
2587fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2588{
2589	struct fxp_softc *sc = ifp->if_softc;
2590	struct mii_data *mii;
2591
2592	mii = device_get_softc(sc->miibus);
2593	FXP_LOCK(sc);
2594	mii_pollstat(mii);
2595	ifmr->ifm_active = mii->mii_media_active;
2596	ifmr->ifm_status = mii->mii_media_status;
2597
2598	if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2599	    sc->flags & FXP_FLAG_CU_RESUME_BUG)
2600		sc->cu_resume_bug = 1;
2601	else
2602		sc->cu_resume_bug = 0;
2603	FXP_UNLOCK(sc);
2604}
2605
2606/*
2607 * Add a buffer to the end of the RFA buffer list.
2608 * Return 0 if successful, 1 for failure. A failure results in
2609 * reusing the RFA buffer.
2610 * The RFA struct is stuck at the beginning of mbuf cluster and the
2611 * data pointer is fixed up to point just past it.
2612 */
2613static int
2614fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2615{
2616	struct mbuf *m;
2617	struct fxp_rfa *rfa;
2618	bus_dmamap_t tmp_map;
2619	int error;
2620
2621	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2622	if (m == NULL)
2623		return (ENOBUFS);
2624
2625	/*
2626	 * Move the data pointer up so that the incoming data packet
2627	 * will be 32-bit aligned.
2628	 */
2629	m->m_data += RFA_ALIGNMENT_FUDGE;
2630
2631	/*
2632	 * Get a pointer to the base of the mbuf cluster and move
2633	 * data start past it.
2634	 */
2635	rfa = mtod(m, struct fxp_rfa *);
2636	m->m_data += sc->rfa_size;
2637	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2638
2639	rfa->rfa_status = 0;
2640	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2641	rfa->actual_size = 0;
2642	m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2643	    sc->rfa_size;
2644
2645	/*
2646	 * Initialize the rest of the RFA.  Note that since the RFA
2647	 * is misaligned, we cannot store values directly.  We're thus
2648	 * using the le32enc() function which handles endianness and
2649	 * is also alignment-safe.
2650	 */
2651	le32enc(&rfa->link_addr, 0xffffffff);
2652	le32enc(&rfa->rbd_addr, 0xffffffff);
2653
2654	/* Map the RFA into DMA memory. */
2655	error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2656	    MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2657	    &rxp->rx_addr, BUS_DMA_NOWAIT);
2658	if (error) {
2659		m_freem(m);
2660		return (error);
2661	}
2662
2663	if (rxp->rx_mbuf != NULL)
2664		bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2665	tmp_map = sc->spare_map;
2666	sc->spare_map = rxp->rx_map;
2667	rxp->rx_map = tmp_map;
2668	rxp->rx_mbuf = m;
2669
2670	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2671	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2672	return (0);
2673}
2674
2675static void
2676fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2677{
2678	struct fxp_rfa *p_rfa;
2679	struct fxp_rx *p_rx;
2680
2681	/*
2682	 * If there are other buffers already on the list, attach this
2683	 * one to the end by fixing up the tail to point to this one.
2684	 */
2685	if (sc->fxp_desc.rx_head != NULL) {
2686		p_rx = sc->fxp_desc.rx_tail;
2687		p_rfa = (struct fxp_rfa *)
2688		    (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2689		p_rx->rx_next = rxp;
2690		le32enc(&p_rfa->link_addr, rxp->rx_addr);
2691		p_rfa->rfa_control = 0;
2692		bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2693		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2694	} else {
2695		rxp->rx_next = NULL;
2696		sc->fxp_desc.rx_head = rxp;
2697	}
2698	sc->fxp_desc.rx_tail = rxp;
2699}
2700
2701static void
2702fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2703{
2704	struct mbuf *m;
2705	struct fxp_rfa *rfa;
2706
2707	m = rxp->rx_mbuf;
2708	m->m_data = m->m_ext.ext_buf;
2709	/*
2710	 * Move the data pointer up so that the incoming data packet
2711	 * will be 32-bit aligned.
2712	 */
2713	m->m_data += RFA_ALIGNMENT_FUDGE;
2714
2715	/*
2716	 * Get a pointer to the base of the mbuf cluster and move
2717	 * data start past it.
2718	 */
2719	rfa = mtod(m, struct fxp_rfa *);
2720	m->m_data += sc->rfa_size;
2721	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2722
2723	rfa->rfa_status = 0;
2724	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2725	rfa->actual_size = 0;
2726
2727	/*
2728	 * Initialize the rest of the RFA.  Note that since the RFA
2729	 * is misaligned, we cannot store values directly.  We're thus
2730	 * using the le32enc() function which handles endianness and
2731	 * is also alignment-safe.
2732	 */
2733	le32enc(&rfa->link_addr, 0xffffffff);
2734	le32enc(&rfa->rbd_addr, 0xffffffff);
2735
2736	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2737	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2738}
2739
2740static int
2741fxp_miibus_readreg(device_t dev, int phy, int reg)
2742{
2743	struct fxp_softc *sc = device_get_softc(dev);
2744	int count = 10000;
2745	int value;
2746
2747	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2748	    (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2749
2750	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2751	    && count--)
2752		DELAY(10);
2753
2754	if (count <= 0)
2755		device_printf(dev, "fxp_miibus_readreg: timed out\n");
2756
2757	return (value & 0xffff);
2758}
2759
2760static int
2761fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2762{
2763	struct fxp_softc *sc = device_get_softc(dev);
2764	int count = 10000;
2765
2766	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2767	    (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2768	    (value & 0xffff));
2769
2770	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2771	    count--)
2772		DELAY(10);
2773
2774	if (count <= 0)
2775		device_printf(dev, "fxp_miibus_writereg: timed out\n");
2776	return (0);
2777}
2778
2779static void
2780fxp_miibus_statchg(device_t dev)
2781{
2782	struct fxp_softc *sc;
2783	struct mii_data *mii;
2784	struct ifnet *ifp;
2785
2786	sc = device_get_softc(dev);
2787	mii = device_get_softc(sc->miibus);
2788	ifp = sc->ifp;
2789	if (mii == NULL || ifp == NULL ||
2790	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
2791	    (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2792	    (IFM_AVALID | IFM_ACTIVE))
2793		return;
2794
2795	/*
2796	 * Call fxp_init_body in order to adjust the flow control settings.
2797	 * Note that the 82557 doesn't support hardware flow control.
2798	 */
2799	if (sc->revision == FXP_REV_82557)
2800		return;
2801	fxp_init_body(sc, 0);
2802}
2803
2804static int
2805fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2806{
2807	struct fxp_softc *sc = ifp->if_softc;
2808	struct ifreq *ifr = (struct ifreq *)data;
2809	struct mii_data *mii;
2810	int flag, mask, error = 0, reinit;
2811
2812	switch (command) {
2813	case SIOCSIFFLAGS:
2814		FXP_LOCK(sc);
2815		/*
2816		 * If interface is marked up and not running, then start it.
2817		 * If it is marked down and running, stop it.
2818		 * XXX If it's up then re-initialize it. This is so flags
2819		 * such as IFF_PROMISC are handled.
2820		 */
2821		if (ifp->if_flags & IFF_UP) {
2822			if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2823			    ((ifp->if_flags ^ sc->if_flags) &
2824			    (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0)
2825				fxp_init_body(sc, 0);
2826			else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2827				fxp_init_body(sc, 1);
2828		} else {
2829			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2830				fxp_stop(sc);
2831		}
2832		sc->if_flags = ifp->if_flags;
2833		FXP_UNLOCK(sc);
2834		break;
2835
2836	case SIOCADDMULTI:
2837	case SIOCDELMULTI:
2838		FXP_LOCK(sc);
2839		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2840			fxp_init_body(sc, 0);
2841		FXP_UNLOCK(sc);
2842		break;
2843
2844	case SIOCSIFMEDIA:
2845	case SIOCGIFMEDIA:
2846		if (sc->miibus != NULL) {
2847			mii = device_get_softc(sc->miibus);
2848                        error = ifmedia_ioctl(ifp, ifr,
2849                            &mii->mii_media, command);
2850		} else {
2851                        error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2852		}
2853		break;
2854
2855	case SIOCSIFCAP:
2856		reinit = 0;
2857		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2858#ifdef DEVICE_POLLING
2859		if (mask & IFCAP_POLLING) {
2860			if (ifr->ifr_reqcap & IFCAP_POLLING) {
2861				error = ether_poll_register(fxp_poll, ifp);
2862				if (error)
2863					return(error);
2864				FXP_LOCK(sc);
2865				CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2866				    FXP_SCB_INTR_DISABLE);
2867				ifp->if_capenable |= IFCAP_POLLING;
2868				FXP_UNLOCK(sc);
2869			} else {
2870				error = ether_poll_deregister(ifp);
2871				/* Enable interrupts in any case */
2872				FXP_LOCK(sc);
2873				CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2874				ifp->if_capenable &= ~IFCAP_POLLING;
2875				FXP_UNLOCK(sc);
2876			}
2877		}
2878#endif
2879		FXP_LOCK(sc);
2880		if ((mask & IFCAP_TXCSUM) != 0 &&
2881		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2882			ifp->if_capenable ^= IFCAP_TXCSUM;
2883			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2884				ifp->if_hwassist |= FXP_CSUM_FEATURES;
2885			else
2886				ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2887		}
2888		if ((mask & IFCAP_RXCSUM) != 0 &&
2889		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2890			ifp->if_capenable ^= IFCAP_RXCSUM;
2891			if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2892				reinit++;
2893		}
2894		if ((mask & IFCAP_TSO4) != 0 &&
2895		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2896			ifp->if_capenable ^= IFCAP_TSO4;
2897			if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2898				ifp->if_hwassist |= CSUM_TSO;
2899			else
2900				ifp->if_hwassist &= ~CSUM_TSO;
2901		}
2902		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2903		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2904			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2905		if ((mask & IFCAP_VLAN_MTU) != 0 &&
2906		    (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2907			ifp->if_capenable ^= IFCAP_VLAN_MTU;
2908			if (sc->revision != FXP_REV_82557)
2909				flag = FXP_FLAG_LONG_PKT_EN;
2910			else /* a hack to get long frames on the old chip */
2911				flag = FXP_FLAG_SAVE_BAD;
2912			sc->flags ^= flag;
2913			if (ifp->if_flags & IFF_UP)
2914				reinit++;
2915		}
2916		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2917		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2918			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2919		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2920		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2921			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2922		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2923		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2924			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2925			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2926				ifp->if_capenable &=
2927				    ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2928			reinit++;
2929		}
2930		if (reinit > 0 && ifp->if_flags & IFF_UP)
2931			fxp_init_body(sc, 0);
2932		FXP_UNLOCK(sc);
2933		VLAN_CAPABILITIES(ifp);
2934		break;
2935
2936	default:
2937		error = ether_ioctl(ifp, command, data);
2938	}
2939	return (error);
2940}
2941
2942/*
2943 * Fill in the multicast address list and return number of entries.
2944 */
2945static int
2946fxp_mc_addrs(struct fxp_softc *sc)
2947{
2948	struct fxp_cb_mcs *mcsp = sc->mcsp;
2949	struct ifnet *ifp = sc->ifp;
2950	struct ifmultiaddr *ifma;
2951	int nmcasts;
2952
2953	nmcasts = 0;
2954	if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2955		if_maddr_rlock(ifp);
2956		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2957			if (ifma->ifma_addr->sa_family != AF_LINK)
2958				continue;
2959			if (nmcasts >= MAXMCADDR) {
2960				ifp->if_flags |= IFF_ALLMULTI;
2961				nmcasts = 0;
2962				break;
2963			}
2964			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2965			    &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2966			nmcasts++;
2967		}
2968		if_maddr_runlock(ifp);
2969	}
2970	mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2971	return (nmcasts);
2972}
2973
2974/*
2975 * Program the multicast filter.
2976 *
2977 * We have an artificial restriction that the multicast setup command
2978 * must be the first command in the chain, so we take steps to ensure
2979 * this. By requiring this, it allows us to keep up the performance of
2980 * the pre-initialized command ring (esp. link pointers) by not actually
2981 * inserting the mcsetup command in the ring - i.e. its link pointer
2982 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2983 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2984 * lead into the regular TxCB ring when it completes.
2985 */
2986static void
2987fxp_mc_setup(struct fxp_softc *sc)
2988{
2989	struct fxp_cb_mcs *mcsp;
2990	int count;
2991
2992	FXP_LOCK_ASSERT(sc, MA_OWNED);
2993
2994	mcsp = sc->mcsp;
2995	mcsp->cb_status = 0;
2996	mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2997	mcsp->link_addr = 0xffffffff;
2998	fxp_mc_addrs(sc);
2999
3000	/*
3001	 * Wait until command unit is idle. This should never be the
3002	 * case when nothing is queued, but make sure anyway.
3003	 */
3004	count = 100;
3005	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3006	    FXP_SCB_CUS_IDLE && --count)
3007		DELAY(10);
3008	if (count == 0) {
3009		device_printf(sc->dev, "command queue timeout\n");
3010		return;
3011	}
3012
3013	/*
3014	 * Start the multicast setup command.
3015	 */
3016	fxp_scb_wait(sc);
3017	bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3018	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3019	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3020	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3021	/* ...and wait for it to complete. */
3022	fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3023}
3024
3025static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3026static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3027static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3028static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3029static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3030static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3031static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3032
3033#define UCODE(x)	x, sizeof(x)/sizeof(uint32_t)
3034
3035static const struct ucode {
3036	uint32_t	revision;
3037	uint32_t	*ucode;
3038	int		length;
3039	u_short		int_delay_offset;
3040	u_short		bundle_max_offset;
3041} const ucode_table[] = {
3042	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3043	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3044	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3045	    D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3046	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3047	    D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3048	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
3049	    D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3050	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3051	    D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3052	{ FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3053	    D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3054	{ FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3055	    D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3056	{ 0, NULL, 0, 0, 0 }
3057};
3058
3059static void
3060fxp_load_ucode(struct fxp_softc *sc)
3061{
3062	const struct ucode *uc;
3063	struct fxp_cb_ucode *cbp;
3064	int i;
3065
3066	if (sc->flags & FXP_FLAG_NO_UCODE)
3067		return;
3068
3069	for (uc = ucode_table; uc->ucode != NULL; uc++)
3070		if (sc->revision == uc->revision)
3071			break;
3072	if (uc->ucode == NULL)
3073		return;
3074	cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3075	cbp->cb_status = 0;
3076	cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3077	cbp->link_addr = 0xffffffff;    	/* (no) next command */
3078	for (i = 0; i < uc->length; i++)
3079		cbp->ucode[i] = htole32(uc->ucode[i]);
3080	if (uc->int_delay_offset)
3081		*(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3082		    htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3083	if (uc->bundle_max_offset)
3084		*(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3085		    htole16(sc->tunable_bundle_max);
3086	/*
3087	 * Download the ucode to the chip.
3088	 */
3089	fxp_scb_wait(sc);
3090	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3091	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3092	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3093	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3094	/* ...and wait for it to complete. */
3095	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3096	device_printf(sc->dev,
3097	    "Microcode loaded, int_delay: %d usec  bundle_max: %d\n",
3098	    sc->tunable_int_delay,
3099	    uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3100	sc->flags |= FXP_FLAG_UCODE;
3101	bzero(cbp, FXP_TXCB_SZ);
3102}
3103
3104#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d)	\
3105	SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3106
3107static void
3108fxp_sysctl_node(struct fxp_softc *sc)
3109{
3110	struct sysctl_ctx_list *ctx;
3111	struct sysctl_oid_list *child, *parent;
3112	struct sysctl_oid *tree;
3113	struct fxp_hwstats *hsp;
3114
3115	ctx = device_get_sysctl_ctx(sc->dev);
3116	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3117
3118	SYSCTL_ADD_PROC(ctx, child,
3119	    OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3120	    &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3121	    "FXP driver receive interrupt microcode bundling delay");
3122	SYSCTL_ADD_PROC(ctx, child,
3123	    OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3124	    &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3125	    "FXP driver receive interrupt microcode bundle size limit");
3126	SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3127	    "FXP RNR events");
3128
3129	/*
3130	 * Pull in device tunables.
3131	 */
3132	sc->tunable_int_delay = TUNABLE_INT_DELAY;
3133	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3134	(void) resource_int_value(device_get_name(sc->dev),
3135	    device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3136	(void) resource_int_value(device_get_name(sc->dev),
3137	    device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3138	sc->rnr = 0;
3139
3140	hsp = &sc->fxp_hwstats;
3141	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3142	    NULL, "FXP statistics");
3143	parent = SYSCTL_CHILDREN(tree);
3144
3145	/* Rx MAC statistics. */
3146	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3147	    NULL, "Rx MAC statistics");
3148	child = SYSCTL_CHILDREN(tree);
3149	FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3150	    &hsp->rx_good, "Good frames");
3151	FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3152	    &hsp->rx_crc_errors, "CRC errors");
3153	FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3154	    &hsp->rx_alignment_errors, "Alignment errors");
3155	FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3156	    &hsp->rx_rnr_errors, "RNR errors");
3157	FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3158	    &hsp->rx_overrun_errors, "Overrun errors");
3159	FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3160	    &hsp->rx_cdt_errors, "Collision detect errors");
3161	FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3162	    &hsp->rx_shortframes, "Short frame errors");
3163	if (sc->revision >= FXP_REV_82558_A4) {
3164		FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3165		    &hsp->rx_pause, "Pause frames");
3166		FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3167		    &hsp->rx_controls, "Unsupported control frames");
3168	}
3169	if (sc->revision >= FXP_REV_82559_A0)
3170		FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3171		    &hsp->rx_tco, "TCO frames");
3172
3173	/* Tx MAC statistics. */
3174	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3175	    NULL, "Tx MAC statistics");
3176	child = SYSCTL_CHILDREN(tree);
3177	FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3178	    &hsp->tx_good, "Good frames");
3179	FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3180	    &hsp->tx_maxcols, "Maximum collisions errors");
3181	FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3182	    &hsp->tx_latecols, "Late collisions errors");
3183	FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3184	    &hsp->tx_underruns, "Underrun errors");
3185	FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3186	    &hsp->tx_lostcrs, "Lost carrier sense");
3187	FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3188	    &hsp->tx_deffered, "Deferred");
3189	FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3190	    &hsp->tx_single_collisions, "Single collisions");
3191	FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3192	    &hsp->tx_multiple_collisions, "Multiple collisions");
3193	FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3194	    &hsp->tx_total_collisions, "Total collisions");
3195	if (sc->revision >= FXP_REV_82558_A4)
3196		FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3197		    &hsp->tx_pause, "Pause frames");
3198	if (sc->revision >= FXP_REV_82559_A0)
3199		FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3200		    &hsp->tx_tco, "TCO frames");
3201}
3202
3203#undef FXP_SYSCTL_STAT_ADD
3204
3205static int
3206sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3207{
3208	int error, value;
3209
3210	value = *(int *)arg1;
3211	error = sysctl_handle_int(oidp, &value, 0, req);
3212	if (error || !req->newptr)
3213		return (error);
3214	if (value < low || value > high)
3215		return (EINVAL);
3216	*(int *)arg1 = value;
3217	return (0);
3218}
3219
3220/*
3221 * Interrupt delay is expressed in microseconds, a multiplier is used
3222 * to convert this to the appropriate clock ticks before using.
3223 */
3224static int
3225sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3226{
3227
3228	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3229}
3230
3231static int
3232sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3233{
3234
3235	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3236}
3237