if_fxp.c revision 220103
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 220103 2011-03-28 16:58:48Z yongari $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#ifdef HAVE_KERNEL_OPTION_HEADERS 38#include "opt_device_polling.h" 39#endif 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/mbuf.h> 47#include <sys/lock.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/ip.h> 67#include <netinet/tcp.h> 68#include <netinet/udp.h> 69 70#include <machine/bus.h> 71#include <machine/in_cksum.h> 72#include <machine/resource.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 76 77#include <dev/mii/mii.h> 78#include <dev/mii/miivar.h> 79 80#include <dev/fxp/if_fxpreg.h> 81#include <dev/fxp/if_fxpvar.h> 82#include <dev/fxp/rcvbundl.h> 83 84MODULE_DEPEND(fxp, pci, 1, 1, 1); 85MODULE_DEPEND(fxp, ether, 1, 1, 1); 86MODULE_DEPEND(fxp, miibus, 1, 1, 1); 87#include "miibus_if.h" 88 89/* 90 * NOTE! On !x86 we typically have an alignment constraint. The 91 * card DMAs the packet immediately following the RFA. However, 92 * the first thing in the packet is a 14-byte Ethernet header. 93 * This means that the packet is misaligned. To compensate, 94 * we actually offset the RFA 2 bytes into the cluster. This 95 * alignes the packet after the Ethernet header at a 32-bit 96 * boundary. HOWEVER! This means that the RFA is misaligned! 97 */ 98#define RFA_ALIGNMENT_FUDGE 2 99 100/* 101 * Set initial transmit threshold at 64 (512 bytes). This is 102 * increased by 64 (512 bytes) at a time, to maximum of 192 103 * (1536 bytes), if an underrun occurs. 104 */ 105static int tx_threshold = 64; 106 107/* 108 * The configuration byte map has several undefined fields which 109 * must be one or must be zero. Set up a template for these bits. 110 * The actual configuration is performed in fxp_init_body. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static const u_char const fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5, /* 21 */ 140 0x0, /* 22 */ 141 0x0, /* 23 */ 142 0x0, /* 24 */ 143 0x0, /* 25 */ 144 0x0, /* 26 */ 145 0x0, /* 27 */ 146 0x0, /* 28 */ 147 0x0, /* 29 */ 148 0x0, /* 30 */ 149 0x0 /* 31 */ 150}; 151 152/* 153 * Claim various Intel PCI device identifiers for this driver. The 154 * sub-vendor and sub-device field are extensively used to identify 155 * particular variants, but we don't currently differentiate between 156 * them. 157 */ 158static const struct fxp_ident const fxp_ident_table[] = { 159 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 160 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 161 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 162 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 163 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 167 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 168 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 169 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 171 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 172 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 173 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 174 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 175 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 176 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 177 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 178 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 179 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 180 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 181 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 182 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 183 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 184 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 185 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 186 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 187 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 188 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 189 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 190 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 191 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 192 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 193 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 194 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 195 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 196 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 197 { 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" }, 198 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 199 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 200 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 201 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 202 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 203 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 204 { 0, -1, 0, NULL }, 205}; 206 207#ifdef FXP_IP_CSUM_WAR 208#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 209#else 210#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 211#endif 212 213static int fxp_probe(device_t dev); 214static int fxp_attach(device_t dev); 215static int fxp_detach(device_t dev); 216static int fxp_shutdown(device_t dev); 217static int fxp_suspend(device_t dev); 218static int fxp_resume(device_t dev); 219 220static const struct fxp_ident *fxp_find_ident(device_t dev); 221static void fxp_intr(void *xsc); 222static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 223 struct mbuf *m, uint16_t status, int pos); 224static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 225 uint8_t statack, int count); 226static void fxp_init(void *xsc); 227static void fxp_init_body(struct fxp_softc *sc, int); 228static void fxp_tick(void *xsc); 229static void fxp_start(struct ifnet *ifp); 230static void fxp_start_body(struct ifnet *ifp); 231static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 232static void fxp_txeof(struct fxp_softc *sc); 233static void fxp_stop(struct fxp_softc *sc); 234static void fxp_release(struct fxp_softc *sc); 235static int fxp_ioctl(struct ifnet *ifp, u_long command, 236 caddr_t data); 237static void fxp_watchdog(struct fxp_softc *sc); 238static void fxp_add_rfabuf(struct fxp_softc *sc, 239 struct fxp_rx *rxp); 240static void fxp_discard_rfabuf(struct fxp_softc *sc, 241 struct fxp_rx *rxp); 242static int fxp_new_rfabuf(struct fxp_softc *sc, 243 struct fxp_rx *rxp); 244static int fxp_mc_addrs(struct fxp_softc *sc); 245static void fxp_mc_setup(struct fxp_softc *sc); 246static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 247 int autosize); 248static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 249 uint16_t data); 250static void fxp_autosize_eeprom(struct fxp_softc *sc); 251static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 252 int offset, int words); 253static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 254 int offset, int words); 255static int fxp_ifmedia_upd(struct ifnet *ifp); 256static void fxp_ifmedia_sts(struct ifnet *ifp, 257 struct ifmediareq *ifmr); 258static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 259static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 260 struct ifmediareq *ifmr); 261static int fxp_miibus_readreg(device_t dev, int phy, int reg); 262static int fxp_miibus_writereg(device_t dev, int phy, int reg, 263 int value); 264static void fxp_miibus_statchg(device_t dev); 265static void fxp_load_ucode(struct fxp_softc *sc); 266static void fxp_update_stats(struct fxp_softc *sc); 267static void fxp_sysctl_node(struct fxp_softc *sc); 268static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 269 int low, int high); 270static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 271static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 272static void fxp_scb_wait(struct fxp_softc *sc); 273static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 274static void fxp_dma_wait(struct fxp_softc *sc, 275 volatile uint16_t *status, bus_dma_tag_t dmat, 276 bus_dmamap_t map); 277 278static device_method_t fxp_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_probe, fxp_probe), 281 DEVMETHOD(device_attach, fxp_attach), 282 DEVMETHOD(device_detach, fxp_detach), 283 DEVMETHOD(device_shutdown, fxp_shutdown), 284 DEVMETHOD(device_suspend, fxp_suspend), 285 DEVMETHOD(device_resume, fxp_resume), 286 287 /* MII interface */ 288 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 289 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 290 DEVMETHOD(miibus_statchg, fxp_miibus_statchg), 291 292 { 0, 0 } 293}; 294 295static driver_t fxp_driver = { 296 "fxp", 297 fxp_methods, 298 sizeof(struct fxp_softc), 299}; 300 301static devclass_t fxp_devclass; 302 303DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 304DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 305 306static struct resource_spec fxp_res_spec_mem[] = { 307 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 308 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 309 { -1, 0 } 310}; 311 312static struct resource_spec fxp_res_spec_io[] = { 313 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 314 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 315 { -1, 0 } 316}; 317 318/* 319 * Wait for the previous command to be accepted (but not necessarily 320 * completed). 321 */ 322static void 323fxp_scb_wait(struct fxp_softc *sc) 324{ 325 union { 326 uint16_t w; 327 uint8_t b[2]; 328 } flowctl; 329 int i = 10000; 330 331 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 332 DELAY(2); 333 if (i == 0) { 334 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); 335 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); 336 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 337 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 338 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 339 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 340 } 341} 342 343static void 344fxp_scb_cmd(struct fxp_softc *sc, int cmd) 345{ 346 347 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 348 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 349 fxp_scb_wait(sc); 350 } 351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 352} 353 354static void 355fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 356 bus_dma_tag_t dmat, bus_dmamap_t map) 357{ 358 int i; 359 360 for (i = 10000; i > 0; i--) { 361 DELAY(2); 362 bus_dmamap_sync(dmat, map, 363 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 364 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 365 break; 366 } 367 if (i == 0) 368 device_printf(sc->dev, "DMA timeout\n"); 369} 370 371static const struct fxp_ident * 372fxp_find_ident(device_t dev) 373{ 374 uint16_t devid; 375 uint8_t revid; 376 const struct fxp_ident *ident; 377 378 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 379 devid = pci_get_device(dev); 380 revid = pci_get_revid(dev); 381 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 382 if (ident->devid == devid && 383 (ident->revid == revid || ident->revid == -1)) { 384 return (ident); 385 } 386 } 387 } 388 return (NULL); 389} 390 391/* 392 * Return identification string if this device is ours. 393 */ 394static int 395fxp_probe(device_t dev) 396{ 397 const struct fxp_ident *ident; 398 399 ident = fxp_find_ident(dev); 400 if (ident != NULL) { 401 device_set_desc(dev, ident->name); 402 return (BUS_PROBE_DEFAULT); 403 } 404 return (ENXIO); 405} 406 407static void 408fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 409{ 410 uint32_t *addr; 411 412 if (error) 413 return; 414 415 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 416 addr = arg; 417 *addr = segs->ds_addr; 418} 419 420static int 421fxp_attach(device_t dev) 422{ 423 struct fxp_softc *sc; 424 struct fxp_cb_tx *tcbp; 425 struct fxp_tx *txp; 426 struct fxp_rx *rxp; 427 struct ifnet *ifp; 428 uint32_t val; 429 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 430 u_char eaddr[ETHER_ADDR_LEN]; 431 int error, flags, i, pmc, prefer_iomap; 432 433 error = 0; 434 sc = device_get_softc(dev); 435 sc->dev = dev; 436 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 437 MTX_DEF); 438 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 439 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 440 fxp_serial_ifmedia_sts); 441 442 ifp = sc->ifp = if_alloc(IFT_ETHER); 443 if (ifp == NULL) { 444 device_printf(dev, "can not if_alloc()\n"); 445 error = ENOSPC; 446 goto fail; 447 } 448 449 /* 450 * Enable bus mastering. 451 */ 452 pci_enable_busmaster(dev); 453 val = pci_read_config(dev, PCIR_COMMAND, 2); 454 455 /* 456 * Figure out which we should try first - memory mapping or i/o mapping? 457 * We default to memory mapping. Then we accept an override from the 458 * command line. Then we check to see which one is enabled. 459 */ 460 prefer_iomap = 0; 461 resource_int_value(device_get_name(dev), device_get_unit(dev), 462 "prefer_iomap", &prefer_iomap); 463 if (prefer_iomap) 464 sc->fxp_spec = fxp_res_spec_io; 465 else 466 sc->fxp_spec = fxp_res_spec_mem; 467 468 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 469 if (error) { 470 if (sc->fxp_spec == fxp_res_spec_mem) 471 sc->fxp_spec = fxp_res_spec_io; 472 else 473 sc->fxp_spec = fxp_res_spec_mem; 474 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 475 } 476 if (error) { 477 device_printf(dev, "could not allocate resources\n"); 478 error = ENXIO; 479 goto fail; 480 } 481 482 if (bootverbose) { 483 device_printf(dev, "using %s space register mapping\n", 484 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 485 } 486 487 /* 488 * Put CU/RU idle state and prepare full reset. 489 */ 490 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 491 DELAY(10); 492 /* Full reset and disable interrupts. */ 493 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 494 DELAY(10); 495 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 496 497 /* 498 * Find out how large of an SEEPROM we have. 499 */ 500 fxp_autosize_eeprom(sc); 501 502 /* 503 * Find out the chip revision; lump all 82557 revs together. 504 */ 505 sc->ident = fxp_find_ident(dev); 506 if (sc->ident->ich > 0) { 507 /* Assume ICH controllers are 82559. */ 508 sc->revision = FXP_REV_82559_A0; 509 } else { 510 fxp_read_eeprom(sc, &data, 5, 1); 511 if ((data >> 8) == 1) 512 sc->revision = FXP_REV_82557; 513 else 514 sc->revision = pci_get_revid(dev); 515 } 516 517 /* 518 * Check availability of WOL. 82559ER does not support WOL. 519 */ 520 if (sc->revision >= FXP_REV_82558_A4 && 521 sc->revision != FXP_REV_82559S_A) { 522 fxp_read_eeprom(sc, &data, 10, 1); 523 if ((data & 0x20) != 0 && 524 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) 525 sc->flags |= FXP_FLAG_WOLCAP; 526 } 527 528 /* Receiver lock-up workaround detection. */ 529 if (sc->revision < FXP_REV_82558_A4) { 530 fxp_read_eeprom(sc, &data, 3, 1); 531 if ((data & 0x03) != 0x03) { 532 sc->flags |= FXP_FLAG_RXBUG; 533 device_printf(dev, "Enabling Rx lock-up workaround\n"); 534 } 535 } 536 537 /* 538 * Determine whether we must use the 503 serial interface. 539 */ 540 fxp_read_eeprom(sc, &data, 6, 1); 541 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 542 && (data & FXP_PHY_SERIAL_ONLY)) 543 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 544 545 fxp_sysctl_node(sc); 546 /* 547 * Enable workarounds for certain chip revision deficiencies. 548 * 549 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 550 * some systems based a normal 82559 design, have a defect where 551 * the chip can cause a PCI protocol violation if it receives 552 * a CU_RESUME command when it is entering the IDLE state. The 553 * workaround is to disable Dynamic Standby Mode, so the chip never 554 * deasserts CLKRUN#, and always remains in an active state. 555 * 556 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 557 */ 558 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 559 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 560 fxp_read_eeprom(sc, &data, 10, 1); 561 if (data & 0x02) { /* STB enable */ 562 uint16_t cksum; 563 int i; 564 565 device_printf(dev, 566 "Disabling dynamic standby mode in EEPROM\n"); 567 data &= ~0x02; 568 fxp_write_eeprom(sc, &data, 10, 1); 569 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 570 cksum = 0; 571 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 572 fxp_read_eeprom(sc, &data, i, 1); 573 cksum += data; 574 } 575 i = (1 << sc->eeprom_size) - 1; 576 cksum = 0xBABA - cksum; 577 fxp_read_eeprom(sc, &data, i, 1); 578 fxp_write_eeprom(sc, &cksum, i, 1); 579 device_printf(dev, 580 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 581 i, data, cksum); 582#if 1 583 /* 584 * If the user elects to continue, try the software 585 * workaround, as it is better than nothing. 586 */ 587 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 588#endif 589 } 590 } 591 592 /* 593 * If we are not a 82557 chip, we can enable extended features. 594 */ 595 if (sc->revision != FXP_REV_82557) { 596 /* 597 * If MWI is enabled in the PCI configuration, and there 598 * is a valid cacheline size (8 or 16 dwords), then tell 599 * the board to turn on MWI. 600 */ 601 if (val & PCIM_CMD_MWRICEN && 602 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 603 sc->flags |= FXP_FLAG_MWI_ENABLE; 604 605 /* turn on the extended TxCB feature */ 606 sc->flags |= FXP_FLAG_EXT_TXCB; 607 608 /* enable reception of long frames for VLAN */ 609 sc->flags |= FXP_FLAG_LONG_PKT_EN; 610 } else { 611 /* a hack to get long VLAN frames on a 82557 */ 612 sc->flags |= FXP_FLAG_SAVE_BAD; 613 } 614 615 /* For 82559 or later chips, Rx checksum offload is supported. */ 616 if (sc->revision >= FXP_REV_82559_A0) { 617 /* 82559ER does not support Rx checksum offloading. */ 618 if (sc->ident->devid != 0x1209) 619 sc->flags |= FXP_FLAG_82559_RXCSUM; 620 } 621 /* 622 * Enable use of extended RFDs and TCBs for 82550 623 * and later chips. Note: we need extended TXCB support 624 * too, but that's already enabled by the code above. 625 * Be careful to do this only on the right devices. 626 */ 627 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 628 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 629 || sc->revision == FXP_REV_82551_10) { 630 sc->rfa_size = sizeof (struct fxp_rfa); 631 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 632 sc->flags |= FXP_FLAG_EXT_RFA; 633 /* Use extended RFA instead of 82559 checksum mode. */ 634 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 635 } else { 636 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 637 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 638 } 639 640 /* 641 * Allocate DMA tags and DMA safe memory. 642 */ 643 sc->maxtxseg = FXP_NTXSEG; 644 sc->maxsegsize = MCLBYTES; 645 if (sc->flags & FXP_FLAG_EXT_RFA) { 646 sc->maxtxseg--; 647 sc->maxsegsize = FXP_TSO_SEGSIZE; 648 } 649 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 650 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 651 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 652 sc->maxtxseg, sc->maxsegsize, 0, 653 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 654 if (error) { 655 device_printf(dev, "could not create TX DMA tag\n"); 656 goto fail; 657 } 658 659 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 660 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 661 MCLBYTES, 1, MCLBYTES, 0, 662 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 663 if (error) { 664 device_printf(dev, "could not create RX DMA tag\n"); 665 goto fail; 666 } 667 668 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 669 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 670 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 671 busdma_lock_mutex, &Giant, &sc->fxp_stag); 672 if (error) { 673 device_printf(dev, "could not create stats DMA tag\n"); 674 goto fail; 675 } 676 677 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 678 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap); 679 if (error) { 680 device_printf(dev, "could not allocate stats DMA memory\n"); 681 goto fail; 682 } 683 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 684 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 685 if (error) { 686 device_printf(dev, "could not load the stats DMA buffer\n"); 687 goto fail; 688 } 689 690 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 691 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 692 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 693 busdma_lock_mutex, &Giant, &sc->cbl_tag); 694 if (error) { 695 device_printf(dev, "could not create TxCB DMA tag\n"); 696 goto fail; 697 } 698 699 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 700 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map); 701 if (error) { 702 device_printf(dev, "could not allocate TxCB DMA memory\n"); 703 goto fail; 704 } 705 706 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 707 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 708 &sc->fxp_desc.cbl_addr, 0); 709 if (error) { 710 device_printf(dev, "could not load TxCB DMA buffer\n"); 711 goto fail; 712 } 713 714 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 715 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 716 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 717 busdma_lock_mutex, &Giant, &sc->mcs_tag); 718 if (error) { 719 device_printf(dev, 720 "could not create multicast setup DMA tag\n"); 721 goto fail; 722 } 723 724 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 725 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map); 726 if (error) { 727 device_printf(dev, 728 "could not allocate multicast setup DMA memory\n"); 729 goto fail; 730 } 731 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 732 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 733 if (error) { 734 device_printf(dev, 735 "can't load the multicast setup DMA buffer\n"); 736 goto fail; 737 } 738 739 /* 740 * Pre-allocate the TX DMA maps and setup the pointers to 741 * the TX command blocks. 742 */ 743 txp = sc->fxp_desc.tx_list; 744 tcbp = sc->fxp_desc.cbl_list; 745 for (i = 0; i < FXP_NTXCB; i++) { 746 txp[i].tx_cb = tcbp + i; 747 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 748 if (error) { 749 device_printf(dev, "can't create DMA map for TX\n"); 750 goto fail; 751 } 752 } 753 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 754 if (error) { 755 device_printf(dev, "can't create spare DMA map\n"); 756 goto fail; 757 } 758 759 /* 760 * Pre-allocate our receive buffers. 761 */ 762 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 763 for (i = 0; i < FXP_NRFABUFS; i++) { 764 rxp = &sc->fxp_desc.rx_list[i]; 765 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 766 if (error) { 767 device_printf(dev, "can't create DMA map for RX\n"); 768 goto fail; 769 } 770 if (fxp_new_rfabuf(sc, rxp) != 0) { 771 error = ENOMEM; 772 goto fail; 773 } 774 fxp_add_rfabuf(sc, rxp); 775 } 776 777 /* 778 * Read MAC address. 779 */ 780 fxp_read_eeprom(sc, myea, 0, 3); 781 eaddr[0] = myea[0] & 0xff; 782 eaddr[1] = myea[0] >> 8; 783 eaddr[2] = myea[1] & 0xff; 784 eaddr[3] = myea[1] >> 8; 785 eaddr[4] = myea[2] & 0xff; 786 eaddr[5] = myea[2] >> 8; 787 if (bootverbose) { 788 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 789 pci_get_vendor(dev), pci_get_device(dev), 790 pci_get_subvendor(dev), pci_get_subdevice(dev), 791 pci_get_revid(dev)); 792 fxp_read_eeprom(sc, &data, 10, 1); 793 device_printf(dev, "Dynamic Standby mode is %s\n", 794 data & 0x02 ? "enabled" : "disabled"); 795 } 796 797 /* 798 * If this is only a 10Mbps device, then there is no MII, and 799 * the PHY will use a serial interface instead. 800 * 801 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 802 * doesn't have a programming interface of any sort. The 803 * media is sensed automatically based on how the link partner 804 * is configured. This is, in essence, manual configuration. 805 */ 806 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 807 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 808 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 809 } else { 810 /* 811 * i82557 wedge when isolating all of their PHYs. 812 */ 813 flags = MIIF_NOISOLATE; 814 if (sc->revision >= FXP_REV_82558_A4) 815 flags |= MIIF_DOPAUSE; 816 error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd, 817 fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 818 MII_OFFSET_ANY, flags); 819 if (error != 0) { 820 device_printf(dev, "attaching PHYs failed\n"); 821 goto fail; 822 } 823 } 824 825 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 826 ifp->if_init = fxp_init; 827 ifp->if_softc = sc; 828 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 829 ifp->if_ioctl = fxp_ioctl; 830 ifp->if_start = fxp_start; 831 832 ifp->if_capabilities = ifp->if_capenable = 0; 833 834 /* Enable checksum offload/TSO for 82550 or better chips */ 835 if (sc->flags & FXP_FLAG_EXT_RFA) { 836 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 837 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 838 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 839 } 840 841 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 842 ifp->if_capabilities |= IFCAP_RXCSUM; 843 ifp->if_capenable |= IFCAP_RXCSUM; 844 } 845 846 if (sc->flags & FXP_FLAG_WOLCAP) { 847 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 848 ifp->if_capenable |= IFCAP_WOL_MAGIC; 849 } 850 851#ifdef DEVICE_POLLING 852 /* Inform the world we support polling. */ 853 ifp->if_capabilities |= IFCAP_POLLING; 854#endif 855 856 /* 857 * Attach the interface. 858 */ 859 ether_ifattach(ifp, eaddr); 860 861 /* 862 * Tell the upper layer(s) we support long frames. 863 * Must appear after the call to ether_ifattach() because 864 * ether_ifattach() sets ifi_hdrlen to the default value. 865 */ 866 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 867 ifp->if_capabilities |= IFCAP_VLAN_MTU; 868 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 869 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 870 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 871 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 872 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 873 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 874 } 875 876 /* 877 * Let the system queue as many packets as we have available 878 * TX descriptors. 879 */ 880 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 881 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 882 IFQ_SET_READY(&ifp->if_snd); 883 884 /* 885 * Hook our interrupt after all initialization is complete. 886 */ 887 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 888 NULL, fxp_intr, sc, &sc->ih); 889 if (error) { 890 device_printf(dev, "could not setup irq\n"); 891 ether_ifdetach(sc->ifp); 892 goto fail; 893 } 894 895 /* 896 * Configure hardware to reject magic frames otherwise 897 * system will hang on recipt of magic frames. 898 */ 899 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 900 FXP_LOCK(sc); 901 /* Clear wakeup events. */ 902 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 903 fxp_init_body(sc, 1); 904 fxp_stop(sc); 905 FXP_UNLOCK(sc); 906 } 907 908fail: 909 if (error) 910 fxp_release(sc); 911 return (error); 912} 913 914/* 915 * Release all resources. The softc lock should not be held and the 916 * interrupt should already be torn down. 917 */ 918static void 919fxp_release(struct fxp_softc *sc) 920{ 921 struct fxp_rx *rxp; 922 struct fxp_tx *txp; 923 int i; 924 925 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 926 KASSERT(sc->ih == NULL, 927 ("fxp_release() called with intr handle still active")); 928 if (sc->miibus) 929 device_delete_child(sc->dev, sc->miibus); 930 bus_generic_detach(sc->dev); 931 ifmedia_removeall(&sc->sc_media); 932 if (sc->fxp_desc.cbl_list) { 933 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 934 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 935 sc->cbl_map); 936 } 937 if (sc->fxp_stats) { 938 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 939 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 940 } 941 if (sc->mcsp) { 942 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 943 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 944 } 945 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 946 if (sc->fxp_rxmtag) { 947 for (i = 0; i < FXP_NRFABUFS; i++) { 948 rxp = &sc->fxp_desc.rx_list[i]; 949 if (rxp->rx_mbuf != NULL) { 950 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 951 BUS_DMASYNC_POSTREAD); 952 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 953 m_freem(rxp->rx_mbuf); 954 } 955 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 956 } 957 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 958 bus_dma_tag_destroy(sc->fxp_rxmtag); 959 } 960 if (sc->fxp_txmtag) { 961 for (i = 0; i < FXP_NTXCB; i++) { 962 txp = &sc->fxp_desc.tx_list[i]; 963 if (txp->tx_mbuf != NULL) { 964 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 965 BUS_DMASYNC_POSTWRITE); 966 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 967 m_freem(txp->tx_mbuf); 968 } 969 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 970 } 971 bus_dma_tag_destroy(sc->fxp_txmtag); 972 } 973 if (sc->fxp_stag) 974 bus_dma_tag_destroy(sc->fxp_stag); 975 if (sc->cbl_tag) 976 bus_dma_tag_destroy(sc->cbl_tag); 977 if (sc->mcs_tag) 978 bus_dma_tag_destroy(sc->mcs_tag); 979 if (sc->ifp) 980 if_free(sc->ifp); 981 982 mtx_destroy(&sc->sc_mtx); 983} 984 985/* 986 * Detach interface. 987 */ 988static int 989fxp_detach(device_t dev) 990{ 991 struct fxp_softc *sc = device_get_softc(dev); 992 993#ifdef DEVICE_POLLING 994 if (sc->ifp->if_capenable & IFCAP_POLLING) 995 ether_poll_deregister(sc->ifp); 996#endif 997 998 FXP_LOCK(sc); 999 /* 1000 * Stop DMA and drop transmit queue, but disable interrupts first. 1001 */ 1002 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1003 fxp_stop(sc); 1004 FXP_UNLOCK(sc); 1005 callout_drain(&sc->stat_ch); 1006 1007 /* 1008 * Close down routes etc. 1009 */ 1010 ether_ifdetach(sc->ifp); 1011 1012 /* 1013 * Unhook interrupt before dropping lock. This is to prevent 1014 * races with fxp_intr(). 1015 */ 1016 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1017 sc->ih = NULL; 1018 1019 /* Release our allocated resources. */ 1020 fxp_release(sc); 1021 return (0); 1022} 1023 1024/* 1025 * Device shutdown routine. Called at system shutdown after sync. The 1026 * main purpose of this routine is to shut off receiver DMA so that 1027 * kernel memory doesn't get clobbered during warmboot. 1028 */ 1029static int 1030fxp_shutdown(device_t dev) 1031{ 1032 1033 /* 1034 * Make sure that DMA is disabled prior to reboot. Not doing 1035 * do could allow DMA to corrupt kernel memory during the 1036 * reboot before the driver initializes. 1037 */ 1038 return (fxp_suspend(dev)); 1039} 1040 1041/* 1042 * Device suspend routine. Stop the interface and save some PCI 1043 * settings in case the BIOS doesn't restore them properly on 1044 * resume. 1045 */ 1046static int 1047fxp_suspend(device_t dev) 1048{ 1049 struct fxp_softc *sc = device_get_softc(dev); 1050 struct ifnet *ifp; 1051 int pmc; 1052 uint16_t pmstat; 1053 1054 FXP_LOCK(sc); 1055 1056 ifp = sc->ifp; 1057 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1058 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1059 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1060 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1061 /* Request PME. */ 1062 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1063 sc->flags |= FXP_FLAG_WOL; 1064 /* Reconfigure hardware to accept magic frames. */ 1065 fxp_init_body(sc, 1); 1066 } 1067 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1068 } 1069 fxp_stop(sc); 1070 1071 sc->suspended = 1; 1072 1073 FXP_UNLOCK(sc); 1074 return (0); 1075} 1076 1077/* 1078 * Device resume routine. re-enable busmastering, and restart the interface if 1079 * appropriate. 1080 */ 1081static int 1082fxp_resume(device_t dev) 1083{ 1084 struct fxp_softc *sc = device_get_softc(dev); 1085 struct ifnet *ifp = sc->ifp; 1086 int pmc; 1087 uint16_t pmstat; 1088 1089 FXP_LOCK(sc); 1090 1091 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1092 sc->flags &= ~FXP_FLAG_WOL; 1093 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1094 /* Disable PME and clear PME status. */ 1095 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1096 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1097 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1098 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1099 CSR_READ_1(sc, FXP_CSR_PMDR)); 1100 } 1101 1102 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1103 DELAY(10); 1104 1105 /* reinitialize interface if necessary */ 1106 if (ifp->if_flags & IFF_UP) 1107 fxp_init_body(sc, 1); 1108 1109 sc->suspended = 0; 1110 1111 FXP_UNLOCK(sc); 1112 return (0); 1113} 1114 1115static void 1116fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1117{ 1118 uint16_t reg; 1119 int x; 1120 1121 /* 1122 * Shift in data. 1123 */ 1124 for (x = 1 << (length - 1); x; x >>= 1) { 1125 if (data & x) 1126 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1127 else 1128 reg = FXP_EEPROM_EECS; 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1130 DELAY(1); 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1132 DELAY(1); 1133 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1134 DELAY(1); 1135 } 1136} 1137 1138/* 1139 * Read from the serial EEPROM. Basically, you manually shift in 1140 * the read opcode (one bit at a time) and then shift in the address, 1141 * and then you shift out the data (all of this one bit at a time). 1142 * The word size is 16 bits, so you have to provide the address for 1143 * every 16 bits of data. 1144 */ 1145static uint16_t 1146fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1147{ 1148 uint16_t reg, data; 1149 int x; 1150 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1152 /* 1153 * Shift in read opcode. 1154 */ 1155 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1156 /* 1157 * Shift in address. 1158 */ 1159 data = 0; 1160 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1161 if (offset & x) 1162 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1163 else 1164 reg = FXP_EEPROM_EECS; 1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1166 DELAY(1); 1167 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1168 DELAY(1); 1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1170 DELAY(1); 1171 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1172 data++; 1173 if (autosize && reg == 0) { 1174 sc->eeprom_size = data; 1175 break; 1176 } 1177 } 1178 /* 1179 * Shift out data. 1180 */ 1181 data = 0; 1182 reg = FXP_EEPROM_EECS; 1183 for (x = 1 << 15; x; x >>= 1) { 1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1185 DELAY(1); 1186 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1187 data |= x; 1188 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1189 DELAY(1); 1190 } 1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1192 DELAY(1); 1193 1194 return (data); 1195} 1196 1197static void 1198fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1199{ 1200 int i; 1201 1202 /* 1203 * Erase/write enable. 1204 */ 1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1206 fxp_eeprom_shiftin(sc, 0x4, 3); 1207 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1208 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1209 DELAY(1); 1210 /* 1211 * Shift in write opcode, address, data. 1212 */ 1213 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1214 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1215 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1216 fxp_eeprom_shiftin(sc, data, 16); 1217 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1218 DELAY(1); 1219 /* 1220 * Wait for EEPROM to finish up. 1221 */ 1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1223 DELAY(1); 1224 for (i = 0; i < 1000; i++) { 1225 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1226 break; 1227 DELAY(50); 1228 } 1229 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1230 DELAY(1); 1231 /* 1232 * Erase/write disable. 1233 */ 1234 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1235 fxp_eeprom_shiftin(sc, 0x4, 3); 1236 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1237 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1238 DELAY(1); 1239} 1240 1241/* 1242 * From NetBSD: 1243 * 1244 * Figure out EEPROM size. 1245 * 1246 * 559's can have either 64-word or 256-word EEPROMs, the 558 1247 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1248 * talks about the existance of 16 to 256 word EEPROMs. 1249 * 1250 * The only known sizes are 64 and 256, where the 256 version is used 1251 * by CardBus cards to store CIS information. 1252 * 1253 * The address is shifted in msb-to-lsb, and after the last 1254 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1255 * after which follows the actual data. We try to detect this zero, by 1256 * probing the data-out bit in the EEPROM control register just after 1257 * having shifted in a bit. If the bit is zero, we assume we've 1258 * shifted enough address bits. The data-out should be tri-state, 1259 * before this, which should translate to a logical one. 1260 */ 1261static void 1262fxp_autosize_eeprom(struct fxp_softc *sc) 1263{ 1264 1265 /* guess maximum size of 256 words */ 1266 sc->eeprom_size = 8; 1267 1268 /* autosize */ 1269 (void) fxp_eeprom_getword(sc, 0, 1); 1270} 1271 1272static void 1273fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1274{ 1275 int i; 1276 1277 for (i = 0; i < words; i++) 1278 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1279} 1280 1281static void 1282fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1283{ 1284 int i; 1285 1286 for (i = 0; i < words; i++) 1287 fxp_eeprom_putword(sc, offset + i, data[i]); 1288} 1289 1290/* 1291 * Grab the softc lock and call the real fxp_start_body() routine 1292 */ 1293static void 1294fxp_start(struct ifnet *ifp) 1295{ 1296 struct fxp_softc *sc = ifp->if_softc; 1297 1298 FXP_LOCK(sc); 1299 fxp_start_body(ifp); 1300 FXP_UNLOCK(sc); 1301} 1302 1303/* 1304 * Start packet transmission on the interface. 1305 * This routine must be called with the softc lock held, and is an 1306 * internal entry point only. 1307 */ 1308static void 1309fxp_start_body(struct ifnet *ifp) 1310{ 1311 struct fxp_softc *sc = ifp->if_softc; 1312 struct mbuf *mb_head; 1313 int txqueued; 1314 1315 FXP_LOCK_ASSERT(sc, MA_OWNED); 1316 1317 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1318 IFF_DRV_RUNNING) 1319 return; 1320 1321 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1322 fxp_txeof(sc); 1323 /* 1324 * We're finished if there is nothing more to add to the list or if 1325 * we're all filled up with buffers to transmit. 1326 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1327 * a NOP command when needed. 1328 */ 1329 txqueued = 0; 1330 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1331 sc->tx_queued < FXP_NTXCB - 1) { 1332 1333 /* 1334 * Grab a packet to transmit. 1335 */ 1336 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1337 if (mb_head == NULL) 1338 break; 1339 1340 if (fxp_encap(sc, &mb_head)) { 1341 if (mb_head == NULL) 1342 break; 1343 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1344 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1345 } 1346 txqueued++; 1347 /* 1348 * Pass packet to bpf if there is a listener. 1349 */ 1350 BPF_MTAP(ifp, mb_head); 1351 } 1352 1353 /* 1354 * We're finished. If we added to the list, issue a RESUME to get DMA 1355 * going again if suspended. 1356 */ 1357 if (txqueued > 0) { 1358 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1360 fxp_scb_wait(sc); 1361 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1362 /* 1363 * Set a 5 second timer just in case we don't hear 1364 * from the card again. 1365 */ 1366 sc->watchdog_timer = 5; 1367 } 1368} 1369 1370static int 1371fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1372{ 1373 struct ifnet *ifp; 1374 struct mbuf *m; 1375 struct fxp_tx *txp; 1376 struct fxp_cb_tx *cbp; 1377 struct tcphdr *tcp; 1378 bus_dma_segment_t segs[FXP_NTXSEG]; 1379 int error, i, nseg, tcp_payload; 1380 1381 FXP_LOCK_ASSERT(sc, MA_OWNED); 1382 ifp = sc->ifp; 1383 1384 tcp_payload = 0; 1385 tcp = NULL; 1386 /* 1387 * Get pointer to next available tx desc. 1388 */ 1389 txp = sc->fxp_desc.tx_last->tx_next; 1390 1391 /* 1392 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1393 * Ethernet Controller Family Open Source Software 1394 * Developer Manual says: 1395 * Using software parsing is only allowed with legal 1396 * TCP/IP or UDP/IP packets. 1397 * ... 1398 * For all other datagrams, hardware parsing must 1399 * be used. 1400 * Software parsing appears to truncate ICMP and 1401 * fragmented UDP packets that contain one to three 1402 * bytes in the second (and final) mbuf of the packet. 1403 */ 1404 if (sc->flags & FXP_FLAG_EXT_RFA) 1405 txp->tx_cb->ipcb_ip_activation_high = 1406 FXP_IPCB_HARDWAREPARSING_ENABLE; 1407 1408 m = *m_head; 1409 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1410 /* 1411 * 82550/82551 requires ethernet/IP/TCP headers must be 1412 * contained in the first active transmit buffer. 1413 */ 1414 struct ether_header *eh; 1415 struct ip *ip; 1416 uint32_t ip_off, poff; 1417 1418 if (M_WRITABLE(*m_head) == 0) { 1419 /* Get a writable copy. */ 1420 m = m_dup(*m_head, M_DONTWAIT); 1421 m_freem(*m_head); 1422 if (m == NULL) { 1423 *m_head = NULL; 1424 return (ENOBUFS); 1425 } 1426 *m_head = m; 1427 } 1428 ip_off = sizeof(struct ether_header); 1429 m = m_pullup(*m_head, ip_off); 1430 if (m == NULL) { 1431 *m_head = NULL; 1432 return (ENOBUFS); 1433 } 1434 eh = mtod(m, struct ether_header *); 1435 /* Check the existence of VLAN tag. */ 1436 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1437 ip_off = sizeof(struct ether_vlan_header); 1438 m = m_pullup(m, ip_off); 1439 if (m == NULL) { 1440 *m_head = NULL; 1441 return (ENOBUFS); 1442 } 1443 } 1444 m = m_pullup(m, ip_off + sizeof(struct ip)); 1445 if (m == NULL) { 1446 *m_head = NULL; 1447 return (ENOBUFS); 1448 } 1449 ip = (struct ip *)(mtod(m, char *) + ip_off); 1450 poff = ip_off + (ip->ip_hl << 2); 1451 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1452 if (m == NULL) { 1453 *m_head = NULL; 1454 return (ENOBUFS); 1455 } 1456 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1457 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1458 if (m == NULL) { 1459 *m_head = NULL; 1460 return (ENOBUFS); 1461 } 1462 1463 /* 1464 * Since 82550/82551 doesn't modify IP length and pseudo 1465 * checksum in the first frame driver should compute it. 1466 */ 1467 ip = (struct ip *)(mtod(m, char *) + ip_off); 1468 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1469 ip->ip_sum = 0; 1470 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1471 (tcp->th_off << 2)); 1472 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1473 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1474 m->m_pkthdr.tso_segsz)); 1475 /* Compute total TCP payload. */ 1476 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1477 tcp_payload -= tcp->th_off << 2; 1478 *m_head = m; 1479 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1480 /* 1481 * Deal with TCP/IP checksum offload. Note that 1482 * in order for TCP checksum offload to work, 1483 * the pseudo header checksum must have already 1484 * been computed and stored in the checksum field 1485 * in the TCP header. The stack should have 1486 * already done this for us. 1487 */ 1488 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1489 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1490 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1491 1492#ifdef FXP_IP_CSUM_WAR 1493 /* 1494 * XXX The 82550 chip appears to have trouble 1495 * dealing with IP header checksums in very small 1496 * datagrams, namely fragments from 1 to 3 bytes 1497 * in size. For example, say you want to transmit 1498 * a UDP packet of 1473 bytes. The packet will be 1499 * fragmented over two IP datagrams, the latter 1500 * containing only one byte of data. The 82550 will 1501 * botch the header checksum on the 1-byte fragment. 1502 * As long as the datagram contains 4 or more bytes 1503 * of data, you're ok. 1504 * 1505 * The following code attempts to work around this 1506 * problem: if the datagram is less than 38 bytes 1507 * in size (14 bytes ether header, 20 bytes IP header, 1508 * plus 4 bytes of data), we punt and compute the IP 1509 * header checksum by hand. This workaround doesn't 1510 * work very well, however, since it can be fooled 1511 * by things like VLAN tags and IP options that make 1512 * the header sizes/offsets vary. 1513 */ 1514 1515 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1516 if (m->m_pkthdr.len < 38) { 1517 struct ip *ip; 1518 m->m_data += ETHER_HDR_LEN; 1519 ip = mtod(m, struct ip *); 1520 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1521 m->m_data -= ETHER_HDR_LEN; 1522 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1523 } else { 1524 txp->tx_cb->ipcb_ip_activation_high = 1525 FXP_IPCB_HARDWAREPARSING_ENABLE; 1526 txp->tx_cb->ipcb_ip_schedule |= 1527 FXP_IPCB_IP_CHECKSUM_ENABLE; 1528 } 1529 } 1530#endif 1531 } 1532 1533 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1534 segs, &nseg, 0); 1535 if (error == EFBIG) { 1536 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1537 if (m == NULL) { 1538 m_freem(*m_head); 1539 *m_head = NULL; 1540 return (ENOMEM); 1541 } 1542 *m_head = m; 1543 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1544 *m_head, segs, &nseg, 0); 1545 if (error != 0) { 1546 m_freem(*m_head); 1547 *m_head = NULL; 1548 return (ENOMEM); 1549 } 1550 } else if (error != 0) 1551 return (error); 1552 if (nseg == 0) { 1553 m_freem(*m_head); 1554 *m_head = NULL; 1555 return (EIO); 1556 } 1557 1558 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1559 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1560 1561 cbp = txp->tx_cb; 1562 for (i = 0; i < nseg; i++) { 1563 /* 1564 * If this is an 82550/82551, then we're using extended 1565 * TxCBs _and_ we're using checksum offload. This means 1566 * that the TxCB is really an IPCB. One major difference 1567 * between the two is that with plain extended TxCBs, 1568 * the bottom half of the TxCB contains two entries from 1569 * the TBD array, whereas IPCBs contain just one entry: 1570 * one entry (8 bytes) has been sacrificed for the TCP/IP 1571 * checksum offload control bits. So to make things work 1572 * right, we have to start filling in the TBD array 1573 * starting from a different place depending on whether 1574 * the chip is an 82550/82551 or not. 1575 */ 1576 if (sc->flags & FXP_FLAG_EXT_RFA) { 1577 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1578 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1579 } else { 1580 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1581 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1582 } 1583 } 1584 if (sc->flags & FXP_FLAG_EXT_RFA) { 1585 /* Configure dynamic TBD for 82550/82551. */ 1586 cbp->tbd_number = 0xFF; 1587 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1588 } else 1589 cbp->tbd_number = nseg; 1590 /* Configure TSO. */ 1591 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1592 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1593 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1594 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1595 FXP_IPCB_IP_CHECKSUM_ENABLE | 1596 FXP_IPCB_TCP_PACKET | 1597 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1598 } 1599 /* Configure VLAN hardware tag insertion. */ 1600 if ((m->m_flags & M_VLANTAG) != 0) { 1601 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1602 txp->tx_cb->ipcb_ip_activation_high |= 1603 FXP_IPCB_INSERTVLAN_ENABLE; 1604 } 1605 1606 txp->tx_mbuf = m; 1607 txp->tx_cb->cb_status = 0; 1608 txp->tx_cb->byte_count = 0; 1609 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1610 txp->tx_cb->cb_command = 1611 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1612 FXP_CB_COMMAND_S); 1613 else 1614 txp->tx_cb->cb_command = 1615 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1616 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1617 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1618 txp->tx_cb->tx_threshold = tx_threshold; 1619 1620 /* 1621 * Advance the end of list forward. 1622 */ 1623 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1624 sc->fxp_desc.tx_last = txp; 1625 1626 /* 1627 * Advance the beginning of the list forward if there are 1628 * no other packets queued (when nothing is queued, tx_first 1629 * sits on the last TxCB that was sent out). 1630 */ 1631 if (sc->tx_queued == 0) 1632 sc->fxp_desc.tx_first = txp; 1633 1634 sc->tx_queued++; 1635 1636 return (0); 1637} 1638 1639#ifdef DEVICE_POLLING 1640static poll_handler_t fxp_poll; 1641 1642static int 1643fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1644{ 1645 struct fxp_softc *sc = ifp->if_softc; 1646 uint8_t statack; 1647 int rx_npkts = 0; 1648 1649 FXP_LOCK(sc); 1650 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1651 FXP_UNLOCK(sc); 1652 return (rx_npkts); 1653 } 1654 1655 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1656 FXP_SCB_STATACK_FR; 1657 if (cmd == POLL_AND_CHECK_STATUS) { 1658 uint8_t tmp; 1659 1660 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1661 if (tmp == 0xff || tmp == 0) { 1662 FXP_UNLOCK(sc); 1663 return (rx_npkts); /* nothing to do */ 1664 } 1665 tmp &= ~statack; 1666 /* ack what we can */ 1667 if (tmp != 0) 1668 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1669 statack |= tmp; 1670 } 1671 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1672 FXP_UNLOCK(sc); 1673 return (rx_npkts); 1674} 1675#endif /* DEVICE_POLLING */ 1676 1677/* 1678 * Process interface interrupts. 1679 */ 1680static void 1681fxp_intr(void *xsc) 1682{ 1683 struct fxp_softc *sc = xsc; 1684 struct ifnet *ifp = sc->ifp; 1685 uint8_t statack; 1686 1687 FXP_LOCK(sc); 1688 if (sc->suspended) { 1689 FXP_UNLOCK(sc); 1690 return; 1691 } 1692 1693#ifdef DEVICE_POLLING 1694 if (ifp->if_capenable & IFCAP_POLLING) { 1695 FXP_UNLOCK(sc); 1696 return; 1697 } 1698#endif 1699 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1700 /* 1701 * It should not be possible to have all bits set; the 1702 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1703 * all bits are set, this may indicate that the card has 1704 * been physically ejected, so ignore it. 1705 */ 1706 if (statack == 0xff) { 1707 FXP_UNLOCK(sc); 1708 return; 1709 } 1710 1711 /* 1712 * First ACK all the interrupts in this pass. 1713 */ 1714 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1715 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1716 fxp_intr_body(sc, ifp, statack, -1); 1717 } 1718 FXP_UNLOCK(sc); 1719} 1720 1721static void 1722fxp_txeof(struct fxp_softc *sc) 1723{ 1724 struct ifnet *ifp; 1725 struct fxp_tx *txp; 1726 1727 ifp = sc->ifp; 1728 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1729 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1730 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1731 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1732 txp = txp->tx_next) { 1733 if (txp->tx_mbuf != NULL) { 1734 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1735 BUS_DMASYNC_POSTWRITE); 1736 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1737 m_freem(txp->tx_mbuf); 1738 txp->tx_mbuf = NULL; 1739 /* clear this to reset csum offload bits */ 1740 txp->tx_cb->tbd[0].tb_addr = 0; 1741 } 1742 sc->tx_queued--; 1743 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1744 } 1745 sc->fxp_desc.tx_first = txp; 1746 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1748 if (sc->tx_queued == 0) 1749 sc->watchdog_timer = 0; 1750} 1751 1752static void 1753fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1754 uint16_t status, int pos) 1755{ 1756 struct ether_header *eh; 1757 struct ip *ip; 1758 struct udphdr *uh; 1759 int32_t hlen, len, pktlen, temp32; 1760 uint16_t csum, *opts; 1761 1762 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1763 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1764 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1765 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1766 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1767 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1768 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1769 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1770 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1771 CSUM_PSEUDO_HDR; 1772 m->m_pkthdr.csum_data = 0xffff; 1773 } 1774 } 1775 return; 1776 } 1777 1778 pktlen = m->m_pkthdr.len; 1779 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1780 return; 1781 eh = mtod(m, struct ether_header *); 1782 if (eh->ether_type != htons(ETHERTYPE_IP)) 1783 return; 1784 ip = (struct ip *)(eh + 1); 1785 if (ip->ip_v != IPVERSION) 1786 return; 1787 1788 hlen = ip->ip_hl << 2; 1789 pktlen -= sizeof(struct ether_header); 1790 if (hlen < sizeof(struct ip)) 1791 return; 1792 if (ntohs(ip->ip_len) < hlen) 1793 return; 1794 if (ntohs(ip->ip_len) != pktlen) 1795 return; 1796 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1797 return; /* can't handle fragmented packet */ 1798 1799 switch (ip->ip_p) { 1800 case IPPROTO_TCP: 1801 if (pktlen < (hlen + sizeof(struct tcphdr))) 1802 return; 1803 break; 1804 case IPPROTO_UDP: 1805 if (pktlen < (hlen + sizeof(struct udphdr))) 1806 return; 1807 uh = (struct udphdr *)((caddr_t)ip + hlen); 1808 if (uh->uh_sum == 0) 1809 return; /* no checksum */ 1810 break; 1811 default: 1812 return; 1813 } 1814 /* Extract computed checksum. */ 1815 csum = be16dec(mtod(m, char *) + pos); 1816 /* checksum fixup for IP options */ 1817 len = hlen - sizeof(struct ip); 1818 if (len > 0) { 1819 opts = (uint16_t *)(ip + 1); 1820 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1821 temp32 = csum - *opts; 1822 temp32 = (temp32 >> 16) + (temp32 & 65535); 1823 csum = temp32 & 65535; 1824 } 1825 } 1826 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1827 m->m_pkthdr.csum_data = csum; 1828} 1829 1830static int 1831fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1832 int count) 1833{ 1834 struct mbuf *m; 1835 struct fxp_rx *rxp; 1836 struct fxp_rfa *rfa; 1837 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1838 int rx_npkts; 1839 uint16_t status; 1840 1841 rx_npkts = 0; 1842 FXP_LOCK_ASSERT(sc, MA_OWNED); 1843 1844 if (rnr) 1845 sc->rnr++; 1846#ifdef DEVICE_POLLING 1847 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1848 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1849 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1850 rnr = 1; 1851 } 1852#endif 1853 1854 /* 1855 * Free any finished transmit mbuf chains. 1856 * 1857 * Handle the CNA event likt a CXTNO event. It used to 1858 * be that this event (control unit not ready) was not 1859 * encountered, but it is now with the SMPng modifications. 1860 * The exact sequence of events that occur when the interface 1861 * is brought up are different now, and if this event 1862 * goes unhandled, the configuration/rxfilter setup sequence 1863 * can stall for several seconds. The result is that no 1864 * packets go out onto the wire for about 5 to 10 seconds 1865 * after the interface is ifconfig'ed for the first time. 1866 */ 1867 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1868 fxp_txeof(sc); 1869 1870 /* 1871 * Try to start more packets transmitting. 1872 */ 1873 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1874 fxp_start_body(ifp); 1875 1876 /* 1877 * Just return if nothing happened on the receive side. 1878 */ 1879 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1880 return (rx_npkts); 1881 1882 /* 1883 * Process receiver interrupts. If a no-resource (RNR) 1884 * condition exists, get whatever packets we can and 1885 * re-start the receiver. 1886 * 1887 * When using polling, we do not process the list to completion, 1888 * so when we get an RNR interrupt we must defer the restart 1889 * until we hit the last buffer with the C bit set. 1890 * If we run out of cycles and rfa_headm has the C bit set, 1891 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1892 * that the info will be used in the subsequent polling cycle. 1893 */ 1894 for (;;) { 1895 rxp = sc->fxp_desc.rx_head; 1896 m = rxp->rx_mbuf; 1897 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1898 RFA_ALIGNMENT_FUDGE); 1899 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1900 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1901 1902#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1903 if (count >= 0 && count-- == 0) { 1904 if (rnr) { 1905 /* Defer RNR processing until the next time. */ 1906 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1907 rnr = 0; 1908 } 1909 break; 1910 } 1911#endif /* DEVICE_POLLING */ 1912 1913 status = le16toh(rfa->rfa_status); 1914 if ((status & FXP_RFA_STATUS_C) == 0) 1915 break; 1916 1917 if ((status & FXP_RFA_STATUS_RNR) != 0) 1918 rnr++; 1919 /* 1920 * Advance head forward. 1921 */ 1922 sc->fxp_desc.rx_head = rxp->rx_next; 1923 1924 /* 1925 * Add a new buffer to the receive chain. 1926 * If this fails, the old buffer is recycled 1927 * instead. 1928 */ 1929 if (fxp_new_rfabuf(sc, rxp) == 0) { 1930 int total_len; 1931 1932 /* 1933 * Fetch packet length (the top 2 bits of 1934 * actual_size are flags set by the controller 1935 * upon completion), and drop the packet in case 1936 * of bogus length or CRC errors. 1937 */ 1938 total_len = le16toh(rfa->actual_size) & 0x3fff; 1939 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1940 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1941 /* Adjust for appended checksum bytes. */ 1942 total_len -= 2; 1943 } 1944 if (total_len < (int)sizeof(struct ether_header) || 1945 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE - 1946 sc->rfa_size) || 1947 status & (FXP_RFA_STATUS_CRC | 1948 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) { 1949 m_freem(m); 1950 fxp_add_rfabuf(sc, rxp); 1951 continue; 1952 } 1953 1954 m->m_pkthdr.len = m->m_len = total_len; 1955 m->m_pkthdr.rcvif = ifp; 1956 1957 /* Do IP checksum checking. */ 1958 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1959 fxp_rxcsum(sc, ifp, m, status, total_len); 1960 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1961 (status & FXP_RFA_STATUS_VLAN) != 0) { 1962 m->m_pkthdr.ether_vtag = 1963 ntohs(rfa->rfax_vlan_id); 1964 m->m_flags |= M_VLANTAG; 1965 } 1966 /* 1967 * Drop locks before calling if_input() since it 1968 * may re-enter fxp_start() in the netisr case. 1969 * This would result in a lock reversal. Better 1970 * performance might be obtained by chaining all 1971 * packets received, dropping the lock, and then 1972 * calling if_input() on each one. 1973 */ 1974 FXP_UNLOCK(sc); 1975 (*ifp->if_input)(ifp, m); 1976 FXP_LOCK(sc); 1977 rx_npkts++; 1978 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1979 return (rx_npkts); 1980 } else { 1981 /* Reuse RFA and loaded DMA map. */ 1982 ifp->if_iqdrops++; 1983 fxp_discard_rfabuf(sc, rxp); 1984 } 1985 fxp_add_rfabuf(sc, rxp); 1986 } 1987 if (rnr) { 1988 fxp_scb_wait(sc); 1989 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1990 sc->fxp_desc.rx_head->rx_addr); 1991 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1992 } 1993 return (rx_npkts); 1994} 1995 1996static void 1997fxp_update_stats(struct fxp_softc *sc) 1998{ 1999 struct ifnet *ifp = sc->ifp; 2000 struct fxp_stats *sp = sc->fxp_stats; 2001 struct fxp_hwstats *hsp; 2002 uint32_t *status; 2003 2004 FXP_LOCK_ASSERT(sc, MA_OWNED); 2005 2006 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2007 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2008 /* Update statistical counters. */ 2009 if (sc->revision >= FXP_REV_82559_A0) 2010 status = &sp->completion_status; 2011 else if (sc->revision >= FXP_REV_82558_A4) 2012 status = (uint32_t *)&sp->tx_tco; 2013 else 2014 status = &sp->tx_pause; 2015 if (*status == htole32(FXP_STATS_DR_COMPLETE)) { 2016 hsp = &sc->fxp_hwstats; 2017 hsp->tx_good += le32toh(sp->tx_good); 2018 hsp->tx_maxcols += le32toh(sp->tx_maxcols); 2019 hsp->tx_latecols += le32toh(sp->tx_latecols); 2020 hsp->tx_underruns += le32toh(sp->tx_underruns); 2021 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs); 2022 hsp->tx_deffered += le32toh(sp->tx_deffered); 2023 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions); 2024 hsp->tx_multiple_collisions += 2025 le32toh(sp->tx_multiple_collisions); 2026 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions); 2027 hsp->rx_good += le32toh(sp->rx_good); 2028 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors); 2029 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors); 2030 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors); 2031 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors); 2032 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors); 2033 hsp->rx_shortframes += le32toh(sp->rx_shortframes); 2034 hsp->tx_pause += le32toh(sp->tx_pause); 2035 hsp->rx_pause += le32toh(sp->rx_pause); 2036 hsp->rx_controls += le32toh(sp->rx_controls); 2037 hsp->tx_tco += le16toh(sp->tx_tco); 2038 hsp->rx_tco += le16toh(sp->rx_tco); 2039 2040 ifp->if_opackets += le32toh(sp->tx_good); 2041 ifp->if_collisions += le32toh(sp->tx_total_collisions); 2042 if (sp->rx_good) { 2043 ifp->if_ipackets += le32toh(sp->rx_good); 2044 sc->rx_idle_secs = 0; 2045 } else if (sc->flags & FXP_FLAG_RXBUG) { 2046 /* 2047 * Receiver's been idle for another second. 2048 */ 2049 sc->rx_idle_secs++; 2050 } 2051 ifp->if_ierrors += 2052 le32toh(sp->rx_crc_errors) + 2053 le32toh(sp->rx_alignment_errors) + 2054 le32toh(sp->rx_rnr_errors) + 2055 le32toh(sp->rx_overrun_errors); 2056 /* 2057 * If any transmit underruns occured, bump up the transmit 2058 * threshold by another 512 bytes (64 * 8). 2059 */ 2060 if (sp->tx_underruns) { 2061 ifp->if_oerrors += le32toh(sp->tx_underruns); 2062 if (tx_threshold < 192) 2063 tx_threshold += 64; 2064 } 2065 *status = 0; 2066 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2068 } 2069} 2070 2071/* 2072 * Update packet in/out/collision statistics. The i82557 doesn't 2073 * allow you to access these counters without doing a fairly 2074 * expensive DMA to get _all_ of the statistics it maintains, so 2075 * we do this operation here only once per second. The statistics 2076 * counters in the kernel are updated from the previous dump-stats 2077 * DMA and then a new dump-stats DMA is started. The on-chip 2078 * counters are zeroed when the DMA completes. If we can't start 2079 * the DMA immediately, we don't wait - we just prepare to read 2080 * them again next time. 2081 */ 2082static void 2083fxp_tick(void *xsc) 2084{ 2085 struct fxp_softc *sc = xsc; 2086 struct ifnet *ifp = sc->ifp; 2087 2088 FXP_LOCK_ASSERT(sc, MA_OWNED); 2089 2090 /* Update statistical counters. */ 2091 fxp_update_stats(sc); 2092 2093 /* 2094 * Release any xmit buffers that have completed DMA. This isn't 2095 * strictly necessary to do here, but it's advantagous for mbufs 2096 * with external storage to be released in a timely manner rather 2097 * than being defered for a potentially long time. This limits 2098 * the delay to a maximum of one second. 2099 */ 2100 fxp_txeof(sc); 2101 2102 /* 2103 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2104 * then assume the receiver has locked up and attempt to clear 2105 * the condition by reprogramming the multicast filter. This is 2106 * a work-around for a bug in the 82557 where the receiver locks 2107 * up if it gets certain types of garbage in the syncronization 2108 * bits prior to the packet header. This bug is supposed to only 2109 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2110 * mode as well (perhaps due to a 10/100 speed transition). 2111 */ 2112 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2113 sc->rx_idle_secs = 0; 2114 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2115 fxp_init_body(sc, 1); 2116 return; 2117 } 2118 /* 2119 * If there is no pending command, start another stats 2120 * dump. Otherwise punt for now. 2121 */ 2122 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2123 /* 2124 * Start another stats dump. 2125 */ 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2127 } 2128 if (sc->miibus != NULL) 2129 mii_tick(device_get_softc(sc->miibus)); 2130 2131 /* 2132 * Check that chip hasn't hung. 2133 */ 2134 fxp_watchdog(sc); 2135 2136 /* 2137 * Schedule another timeout one second from now. 2138 */ 2139 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2140} 2141 2142/* 2143 * Stop the interface. Cancels the statistics updater and resets 2144 * the interface. 2145 */ 2146static void 2147fxp_stop(struct fxp_softc *sc) 2148{ 2149 struct ifnet *ifp = sc->ifp; 2150 struct fxp_tx *txp; 2151 int i; 2152 2153 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2154 sc->watchdog_timer = 0; 2155 2156 /* 2157 * Cancel stats updater. 2158 */ 2159 callout_stop(&sc->stat_ch); 2160 2161 /* 2162 * Preserve PCI configuration, configure, IA/multicast 2163 * setup and put RU and CU into idle state. 2164 */ 2165 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2166 DELAY(50); 2167 /* Disable interrupts. */ 2168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2169 2170 fxp_update_stats(sc); 2171 2172 /* 2173 * Release any xmit buffers. 2174 */ 2175 txp = sc->fxp_desc.tx_list; 2176 if (txp != NULL) { 2177 for (i = 0; i < FXP_NTXCB; i++) { 2178 if (txp[i].tx_mbuf != NULL) { 2179 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2180 BUS_DMASYNC_POSTWRITE); 2181 bus_dmamap_unload(sc->fxp_txmtag, 2182 txp[i].tx_map); 2183 m_freem(txp[i].tx_mbuf); 2184 txp[i].tx_mbuf = NULL; 2185 /* clear this to reset csum offload bits */ 2186 txp[i].tx_cb->tbd[0].tb_addr = 0; 2187 } 2188 } 2189 } 2190 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2191 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2192 sc->tx_queued = 0; 2193} 2194 2195/* 2196 * Watchdog/transmission transmit timeout handler. Called when a 2197 * transmission is started on the interface, but no interrupt is 2198 * received before the timeout. This usually indicates that the 2199 * card has wedged for some reason. 2200 */ 2201static void 2202fxp_watchdog(struct fxp_softc *sc) 2203{ 2204 2205 FXP_LOCK_ASSERT(sc, MA_OWNED); 2206 2207 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2208 return; 2209 2210 device_printf(sc->dev, "device timeout\n"); 2211 sc->ifp->if_oerrors++; 2212 2213 fxp_init_body(sc, 1); 2214} 2215 2216/* 2217 * Acquire locks and then call the real initialization function. This 2218 * is necessary because ether_ioctl() calls if_init() and this would 2219 * result in mutex recursion if the mutex was held. 2220 */ 2221static void 2222fxp_init(void *xsc) 2223{ 2224 struct fxp_softc *sc = xsc; 2225 2226 FXP_LOCK(sc); 2227 fxp_init_body(sc, 1); 2228 FXP_UNLOCK(sc); 2229} 2230 2231/* 2232 * Perform device initialization. This routine must be called with the 2233 * softc lock held. 2234 */ 2235static void 2236fxp_init_body(struct fxp_softc *sc, int setmedia) 2237{ 2238 struct ifnet *ifp = sc->ifp; 2239 struct mii_data *mii; 2240 struct fxp_cb_config *cbp; 2241 struct fxp_cb_ias *cb_ias; 2242 struct fxp_cb_tx *tcbp; 2243 struct fxp_tx *txp; 2244 int i, prm; 2245 2246 FXP_LOCK_ASSERT(sc, MA_OWNED); 2247 /* 2248 * Cancel any pending I/O 2249 */ 2250 fxp_stop(sc); 2251 2252 /* 2253 * Issue software reset, which also unloads the microcode. 2254 */ 2255 sc->flags &= ~FXP_FLAG_UCODE; 2256 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2257 DELAY(50); 2258 2259 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2260 2261 /* 2262 * Initialize base of CBL and RFA memory. Loading with zero 2263 * sets it up for regular linear addressing. 2264 */ 2265 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2266 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2267 2268 fxp_scb_wait(sc); 2269 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2270 2271 /* 2272 * Initialize base of dump-stats buffer. 2273 */ 2274 fxp_scb_wait(sc); 2275 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 2276 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2277 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2278 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2279 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2280 2281 /* 2282 * Attempt to load microcode if requested. 2283 * For ICH based controllers do not load microcode. 2284 */ 2285 if (sc->ident->ich == 0) { 2286 if (ifp->if_flags & IFF_LINK0 && 2287 (sc->flags & FXP_FLAG_UCODE) == 0) 2288 fxp_load_ucode(sc); 2289 } 2290 2291 /* 2292 * Set IFF_ALLMULTI status. It's needed in configure action 2293 * command. 2294 */ 2295 fxp_mc_addrs(sc); 2296 2297 /* 2298 * We temporarily use memory that contains the TxCB list to 2299 * construct the config CB. The TxCB list memory is rebuilt 2300 * later. 2301 */ 2302 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2303 2304 /* 2305 * This bcopy is kind of disgusting, but there are a bunch of must be 2306 * zero and must be one bits in this structure and this is the easiest 2307 * way to initialize them all to proper values. 2308 */ 2309 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2310 2311 cbp->cb_status = 0; 2312 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2313 FXP_CB_COMMAND_EL); 2314 cbp->link_addr = 0xffffffff; /* (no) next command */ 2315 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2316 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2317 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2318 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2319 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2320 cbp->type_enable = 0; /* actually reserved */ 2321 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2322 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2323 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2324 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2325 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2326 cbp->late_scb = 0; /* (don't) defer SCB update */ 2327 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2328 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2329 cbp->ci_int = 1; /* interrupt on CU idle */ 2330 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2331 cbp->ext_stats_dis = 1; /* disable extended counters */ 2332 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2333 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2334 cbp->disc_short_rx = !prm; /* discard short packets */ 2335 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2336 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2337 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2338 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2339 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2340 cbp->csma_dis = 0; /* (don't) disable link */ 2341 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2342 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2343 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2344 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2345 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2346 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2347 cbp->nsai = 1; /* (don't) disable source addr insert */ 2348 cbp->preamble_length = 2; /* (7 byte) preamble */ 2349 cbp->loopback = 0; /* (don't) loopback */ 2350 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2351 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2352 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2353 cbp->promiscuous = prm; /* promiscuous mode */ 2354 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2355 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2356 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2357 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2358 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2359 2360 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2361 cbp->padding = 1; /* (do) pad short tx packets */ 2362 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2363 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2364 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2365 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2366 cbp->force_fdx = 0; /* (don't) force full duplex */ 2367 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2368 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2369 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm; 2370 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2371 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2372 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2373 2374 if (sc->revision == FXP_REV_82557) { 2375 /* 2376 * The 82557 has no hardware flow control, the values 2377 * below are the defaults for the chip. 2378 */ 2379 cbp->fc_delay_lsb = 0; 2380 cbp->fc_delay_msb = 0x40; 2381 cbp->pri_fc_thresh = 3; 2382 cbp->tx_fc_dis = 0; 2383 cbp->rx_fc_restop = 0; 2384 cbp->rx_fc_restart = 0; 2385 cbp->fc_filter = 0; 2386 cbp->pri_fc_loc = 1; 2387 } else { 2388 /* Set pause RX FIFO threshold to 1KB. */ 2389 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); 2390 /* Set pause time. */ 2391 cbp->fc_delay_lsb = 0xff; 2392 cbp->fc_delay_msb = 0xff; 2393 cbp->pri_fc_thresh = 3; 2394 mii = device_get_softc(sc->miibus); 2395 if ((IFM_OPTIONS(mii->mii_media_active) & 2396 IFM_ETH_TXPAUSE) != 0) 2397 /* enable transmit FC */ 2398 cbp->tx_fc_dis = 0; 2399 else 2400 /* disable transmit FC */ 2401 cbp->tx_fc_dis = 1; 2402 if ((IFM_OPTIONS(mii->mii_media_active) & 2403 IFM_ETH_RXPAUSE) != 0) { 2404 /* enable FC restart/restop frames */ 2405 cbp->rx_fc_restart = 1; 2406 cbp->rx_fc_restop = 1; 2407 } else { 2408 /* disable FC restart/restop frames */ 2409 cbp->rx_fc_restart = 0; 2410 cbp->rx_fc_restop = 0; 2411 } 2412 cbp->fc_filter = !prm; /* drop FC frames to host */ 2413 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2414 } 2415 2416 /* Enable 82558 and 82559 extended statistics functionality. */ 2417 if (sc->revision >= FXP_REV_82558_A4) { 2418 if (sc->revision >= FXP_REV_82559_A0) { 2419 /* 2420 * Extend configuration table size to 32 2421 * to include TCO configuration. 2422 */ 2423 cbp->byte_count = 32; 2424 cbp->ext_stats_dis = 1; 2425 /* Enable TCO stats. */ 2426 cbp->tno_int_or_tco_en = 1; 2427 cbp->gamla_rx = 1; 2428 } else 2429 cbp->ext_stats_dis = 0; 2430 } 2431 2432 /* 2433 * Start the config command/DMA. 2434 */ 2435 fxp_scb_wait(sc); 2436 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2437 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2438 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2439 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2440 /* ...and wait for it to complete. */ 2441 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2442 2443 /* 2444 * Now initialize the station address. Temporarily use the TxCB 2445 * memory area like we did above for the config CB. 2446 */ 2447 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2448 cb_ias->cb_status = 0; 2449 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2450 cb_ias->link_addr = 0xffffffff; 2451 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2452 2453 /* 2454 * Start the IAS (Individual Address Setup) command/DMA. 2455 */ 2456 fxp_scb_wait(sc); 2457 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2458 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2459 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2460 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2461 /* ...and wait for it to complete. */ 2462 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2463 2464 /* 2465 * Initialize the multicast address list. 2466 */ 2467 fxp_mc_setup(sc); 2468 2469 /* 2470 * Initialize transmit control block (TxCB) list. 2471 */ 2472 txp = sc->fxp_desc.tx_list; 2473 tcbp = sc->fxp_desc.cbl_list; 2474 bzero(tcbp, FXP_TXCB_SZ); 2475 for (i = 0; i < FXP_NTXCB; i++) { 2476 txp[i].tx_mbuf = NULL; 2477 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2478 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2479 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2480 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2481 if (sc->flags & FXP_FLAG_EXT_TXCB) 2482 tcbp[i].tbd_array_addr = 2483 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2484 else 2485 tcbp[i].tbd_array_addr = 2486 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2487 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2488 } 2489 /* 2490 * Set the suspend flag on the first TxCB and start the control 2491 * unit. It will execute the NOP and then suspend. 2492 */ 2493 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2494 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2496 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2497 sc->tx_queued = 1; 2498 2499 fxp_scb_wait(sc); 2500 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2501 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2502 2503 /* 2504 * Initialize receiver buffer area - RFA. 2505 */ 2506 fxp_scb_wait(sc); 2507 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2508 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2509 2510 if (sc->miibus != NULL && setmedia != 0) 2511 mii_mediachg(device_get_softc(sc->miibus)); 2512 2513 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2514 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2515 2516 /* 2517 * Enable interrupts. 2518 */ 2519#ifdef DEVICE_POLLING 2520 /* 2521 * ... but only do that if we are not polling. And because (presumably) 2522 * the default is interrupts on, we need to disable them explicitly! 2523 */ 2524 if (ifp->if_capenable & IFCAP_POLLING ) 2525 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2526 else 2527#endif /* DEVICE_POLLING */ 2528 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2529 2530 /* 2531 * Start stats updater. 2532 */ 2533 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2534} 2535 2536static int 2537fxp_serial_ifmedia_upd(struct ifnet *ifp) 2538{ 2539 2540 return (0); 2541} 2542 2543static void 2544fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2545{ 2546 2547 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2548} 2549 2550/* 2551 * Change media according to request. 2552 */ 2553static int 2554fxp_ifmedia_upd(struct ifnet *ifp) 2555{ 2556 struct fxp_softc *sc = ifp->if_softc; 2557 struct mii_data *mii; 2558 2559 mii = device_get_softc(sc->miibus); 2560 FXP_LOCK(sc); 2561 if (mii->mii_instance) { 2562 struct mii_softc *miisc; 2563 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2564 mii_phy_reset(miisc); 2565 } 2566 mii_mediachg(mii); 2567 FXP_UNLOCK(sc); 2568 return (0); 2569} 2570 2571/* 2572 * Notify the world which media we're using. 2573 */ 2574static void 2575fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2576{ 2577 struct fxp_softc *sc = ifp->if_softc; 2578 struct mii_data *mii; 2579 2580 mii = device_get_softc(sc->miibus); 2581 FXP_LOCK(sc); 2582 mii_pollstat(mii); 2583 ifmr->ifm_active = mii->mii_media_active; 2584 ifmr->ifm_status = mii->mii_media_status; 2585 2586 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2587 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2588 sc->cu_resume_bug = 1; 2589 else 2590 sc->cu_resume_bug = 0; 2591 FXP_UNLOCK(sc); 2592} 2593 2594/* 2595 * Add a buffer to the end of the RFA buffer list. 2596 * Return 0 if successful, 1 for failure. A failure results in 2597 * reusing the RFA buffer. 2598 * The RFA struct is stuck at the beginning of mbuf cluster and the 2599 * data pointer is fixed up to point just past it. 2600 */ 2601static int 2602fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2603{ 2604 struct mbuf *m; 2605 struct fxp_rfa *rfa; 2606 bus_dmamap_t tmp_map; 2607 int error; 2608 2609 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2610 if (m == NULL) 2611 return (ENOBUFS); 2612 2613 /* 2614 * Move the data pointer up so that the incoming data packet 2615 * will be 32-bit aligned. 2616 */ 2617 m->m_data += RFA_ALIGNMENT_FUDGE; 2618 2619 /* 2620 * Get a pointer to the base of the mbuf cluster and move 2621 * data start past it. 2622 */ 2623 rfa = mtod(m, struct fxp_rfa *); 2624 m->m_data += sc->rfa_size; 2625 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2626 2627 rfa->rfa_status = 0; 2628 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2629 rfa->actual_size = 0; 2630 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2631 sc->rfa_size; 2632 2633 /* 2634 * Initialize the rest of the RFA. Note that since the RFA 2635 * is misaligned, we cannot store values directly. We're thus 2636 * using the le32enc() function which handles endianness and 2637 * is also alignment-safe. 2638 */ 2639 le32enc(&rfa->link_addr, 0xffffffff); 2640 le32enc(&rfa->rbd_addr, 0xffffffff); 2641 2642 /* Map the RFA into DMA memory. */ 2643 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2644 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2645 &rxp->rx_addr, BUS_DMA_NOWAIT); 2646 if (error) { 2647 m_freem(m); 2648 return (error); 2649 } 2650 2651 if (rxp->rx_mbuf != NULL) 2652 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2653 tmp_map = sc->spare_map; 2654 sc->spare_map = rxp->rx_map; 2655 rxp->rx_map = tmp_map; 2656 rxp->rx_mbuf = m; 2657 2658 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2659 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2660 return (0); 2661} 2662 2663static void 2664fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2665{ 2666 struct fxp_rfa *p_rfa; 2667 struct fxp_rx *p_rx; 2668 2669 /* 2670 * If there are other buffers already on the list, attach this 2671 * one to the end by fixing up the tail to point to this one. 2672 */ 2673 if (sc->fxp_desc.rx_head != NULL) { 2674 p_rx = sc->fxp_desc.rx_tail; 2675 p_rfa = (struct fxp_rfa *) 2676 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2677 p_rx->rx_next = rxp; 2678 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2679 p_rfa->rfa_control = 0; 2680 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2682 } else { 2683 rxp->rx_next = NULL; 2684 sc->fxp_desc.rx_head = rxp; 2685 } 2686 sc->fxp_desc.rx_tail = rxp; 2687} 2688 2689static void 2690fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2691{ 2692 struct mbuf *m; 2693 struct fxp_rfa *rfa; 2694 2695 m = rxp->rx_mbuf; 2696 m->m_data = m->m_ext.ext_buf; 2697 /* 2698 * Move the data pointer up so that the incoming data packet 2699 * will be 32-bit aligned. 2700 */ 2701 m->m_data += RFA_ALIGNMENT_FUDGE; 2702 2703 /* 2704 * Get a pointer to the base of the mbuf cluster and move 2705 * data start past it. 2706 */ 2707 rfa = mtod(m, struct fxp_rfa *); 2708 m->m_data += sc->rfa_size; 2709 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2710 2711 rfa->rfa_status = 0; 2712 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2713 rfa->actual_size = 0; 2714 2715 /* 2716 * Initialize the rest of the RFA. Note that since the RFA 2717 * is misaligned, we cannot store values directly. We're thus 2718 * using the le32enc() function which handles endianness and 2719 * is also alignment-safe. 2720 */ 2721 le32enc(&rfa->link_addr, 0xffffffff); 2722 le32enc(&rfa->rbd_addr, 0xffffffff); 2723 2724 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2726} 2727 2728static int 2729fxp_miibus_readreg(device_t dev, int phy, int reg) 2730{ 2731 struct fxp_softc *sc = device_get_softc(dev); 2732 int count = 10000; 2733 int value; 2734 2735 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2736 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2737 2738 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2739 && count--) 2740 DELAY(10); 2741 2742 if (count <= 0) 2743 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2744 2745 return (value & 0xffff); 2746} 2747 2748static int 2749fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2750{ 2751 struct fxp_softc *sc = device_get_softc(dev); 2752 int count = 10000; 2753 2754 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2755 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2756 (value & 0xffff)); 2757 2758 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2759 count--) 2760 DELAY(10); 2761 2762 if (count <= 0) 2763 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2764 return (0); 2765} 2766 2767static void 2768fxp_miibus_statchg(device_t dev) 2769{ 2770 struct fxp_softc *sc; 2771 struct mii_data *mii; 2772 struct ifnet *ifp; 2773 2774 sc = device_get_softc(dev); 2775 mii = device_get_softc(sc->miibus); 2776 ifp = sc->ifp; 2777 if (mii == NULL || ifp == NULL || 2778 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 2779 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) != 2780 (IFM_AVALID | IFM_ACTIVE)) 2781 return; 2782 2783 /* 2784 * Call fxp_init_body in order to adjust the flow control settings. 2785 * Note that the 82557 doesn't support hardware flow control. 2786 */ 2787 if (sc->revision == FXP_REV_82557) 2788 return; 2789 fxp_init_body(sc, 0); 2790} 2791 2792static int 2793fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2794{ 2795 struct fxp_softc *sc = ifp->if_softc; 2796 struct ifreq *ifr = (struct ifreq *)data; 2797 struct mii_data *mii; 2798 int flag, mask, error = 0, reinit; 2799 2800 switch (command) { 2801 case SIOCSIFFLAGS: 2802 FXP_LOCK(sc); 2803 /* 2804 * If interface is marked up and not running, then start it. 2805 * If it is marked down and running, stop it. 2806 * XXX If it's up then re-initialize it. This is so flags 2807 * such as IFF_PROMISC are handled. 2808 */ 2809 if (ifp->if_flags & IFF_UP) { 2810 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) && 2811 ((ifp->if_flags ^ sc->if_flags) & 2812 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) 2813 fxp_init_body(sc, 1); 2814 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2815 fxp_init_body(sc, 1); 2816 } else { 2817 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2818 fxp_stop(sc); 2819 } 2820 sc->if_flags = ifp->if_flags; 2821 FXP_UNLOCK(sc); 2822 break; 2823 2824 case SIOCADDMULTI: 2825 case SIOCDELMULTI: 2826 FXP_LOCK(sc); 2827 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2828 fxp_init_body(sc, 0); 2829 FXP_UNLOCK(sc); 2830 break; 2831 2832 case SIOCSIFMEDIA: 2833 case SIOCGIFMEDIA: 2834 if (sc->miibus != NULL) { 2835 mii = device_get_softc(sc->miibus); 2836 error = ifmedia_ioctl(ifp, ifr, 2837 &mii->mii_media, command); 2838 } else { 2839 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2840 } 2841 break; 2842 2843 case SIOCSIFCAP: 2844 reinit = 0; 2845 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2846#ifdef DEVICE_POLLING 2847 if (mask & IFCAP_POLLING) { 2848 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2849 error = ether_poll_register(fxp_poll, ifp); 2850 if (error) 2851 return(error); 2852 FXP_LOCK(sc); 2853 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2854 FXP_SCB_INTR_DISABLE); 2855 ifp->if_capenable |= IFCAP_POLLING; 2856 FXP_UNLOCK(sc); 2857 } else { 2858 error = ether_poll_deregister(ifp); 2859 /* Enable interrupts in any case */ 2860 FXP_LOCK(sc); 2861 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2862 ifp->if_capenable &= ~IFCAP_POLLING; 2863 FXP_UNLOCK(sc); 2864 } 2865 } 2866#endif 2867 FXP_LOCK(sc); 2868 if ((mask & IFCAP_TXCSUM) != 0 && 2869 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2870 ifp->if_capenable ^= IFCAP_TXCSUM; 2871 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2872 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2873 else 2874 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2875 } 2876 if ((mask & IFCAP_RXCSUM) != 0 && 2877 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2878 ifp->if_capenable ^= IFCAP_RXCSUM; 2879 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2880 reinit++; 2881 } 2882 if ((mask & IFCAP_TSO4) != 0 && 2883 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2884 ifp->if_capenable ^= IFCAP_TSO4; 2885 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2886 ifp->if_hwassist |= CSUM_TSO; 2887 else 2888 ifp->if_hwassist &= ~CSUM_TSO; 2889 } 2890 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2891 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2892 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2893 if ((mask & IFCAP_VLAN_MTU) != 0 && 2894 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2895 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2896 if (sc->revision != FXP_REV_82557) 2897 flag = FXP_FLAG_LONG_PKT_EN; 2898 else /* a hack to get long frames on the old chip */ 2899 flag = FXP_FLAG_SAVE_BAD; 2900 sc->flags ^= flag; 2901 if (ifp->if_flags & IFF_UP) 2902 reinit++; 2903 } 2904 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2905 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2906 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2907 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2908 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2909 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2910 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2911 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2912 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2913 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2914 ifp->if_capenable &= 2915 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2916 reinit++; 2917 } 2918 if (reinit > 0 && ifp->if_flags & IFF_UP) 2919 fxp_init_body(sc, 1); 2920 FXP_UNLOCK(sc); 2921 VLAN_CAPABILITIES(ifp); 2922 break; 2923 2924 default: 2925 error = ether_ioctl(ifp, command, data); 2926 } 2927 return (error); 2928} 2929 2930/* 2931 * Fill in the multicast address list and return number of entries. 2932 */ 2933static int 2934fxp_mc_addrs(struct fxp_softc *sc) 2935{ 2936 struct fxp_cb_mcs *mcsp = sc->mcsp; 2937 struct ifnet *ifp = sc->ifp; 2938 struct ifmultiaddr *ifma; 2939 int nmcasts; 2940 2941 nmcasts = 0; 2942 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2943 if_maddr_rlock(ifp); 2944 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2945 if (ifma->ifma_addr->sa_family != AF_LINK) 2946 continue; 2947 if (nmcasts >= MAXMCADDR) { 2948 ifp->if_flags |= IFF_ALLMULTI; 2949 nmcasts = 0; 2950 break; 2951 } 2952 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2953 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2954 nmcasts++; 2955 } 2956 if_maddr_runlock(ifp); 2957 } 2958 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2959 return (nmcasts); 2960} 2961 2962/* 2963 * Program the multicast filter. 2964 * 2965 * We have an artificial restriction that the multicast setup command 2966 * must be the first command in the chain, so we take steps to ensure 2967 * this. By requiring this, it allows us to keep up the performance of 2968 * the pre-initialized command ring (esp. link pointers) by not actually 2969 * inserting the mcsetup command in the ring - i.e. its link pointer 2970 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2971 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2972 * lead into the regular TxCB ring when it completes. 2973 */ 2974static void 2975fxp_mc_setup(struct fxp_softc *sc) 2976{ 2977 struct fxp_cb_mcs *mcsp; 2978 int count; 2979 2980 FXP_LOCK_ASSERT(sc, MA_OWNED); 2981 2982 mcsp = sc->mcsp; 2983 mcsp->cb_status = 0; 2984 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2985 mcsp->link_addr = 0xffffffff; 2986 fxp_mc_addrs(sc); 2987 2988 /* 2989 * Wait until command unit is idle. This should never be the 2990 * case when nothing is queued, but make sure anyway. 2991 */ 2992 count = 100; 2993 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 2994 FXP_SCB_CUS_IDLE && --count) 2995 DELAY(10); 2996 if (count == 0) { 2997 device_printf(sc->dev, "command queue timeout\n"); 2998 return; 2999 } 3000 3001 /* 3002 * Start the multicast setup command. 3003 */ 3004 fxp_scb_wait(sc); 3005 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 3006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3007 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 3008 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3009 /* ...and wait for it to complete. */ 3010 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 3011} 3012 3013static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3014static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3015static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3016static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3017static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3018static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3019static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3020 3021#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3022 3023static const struct ucode { 3024 uint32_t revision; 3025 uint32_t *ucode; 3026 int length; 3027 u_short int_delay_offset; 3028 u_short bundle_max_offset; 3029} const ucode_table[] = { 3030 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3031 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3032 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3033 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3034 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3035 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3036 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3037 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3038 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3039 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3040 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3041 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3042 { 0, NULL, 0, 0, 0 } 3043}; 3044 3045static void 3046fxp_load_ucode(struct fxp_softc *sc) 3047{ 3048 const struct ucode *uc; 3049 struct fxp_cb_ucode *cbp; 3050 int i; 3051 3052 for (uc = ucode_table; uc->ucode != NULL; uc++) 3053 if (sc->revision == uc->revision) 3054 break; 3055 if (uc->ucode == NULL) 3056 return; 3057 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3058 cbp->cb_status = 0; 3059 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3060 cbp->link_addr = 0xffffffff; /* (no) next command */ 3061 for (i = 0; i < uc->length; i++) 3062 cbp->ucode[i] = htole32(uc->ucode[i]); 3063 if (uc->int_delay_offset) 3064 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3065 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3066 if (uc->bundle_max_offset) 3067 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3068 htole16(sc->tunable_bundle_max); 3069 /* 3070 * Download the ucode to the chip. 3071 */ 3072 fxp_scb_wait(sc); 3073 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3074 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3075 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3076 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3077 /* ...and wait for it to complete. */ 3078 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3079 device_printf(sc->dev, 3080 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3081 sc->tunable_int_delay, 3082 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3083 sc->flags |= FXP_FLAG_UCODE; 3084} 3085 3086#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \ 3087 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3088 3089static void 3090fxp_sysctl_node(struct fxp_softc *sc) 3091{ 3092 struct sysctl_ctx_list *ctx; 3093 struct sysctl_oid_list *child, *parent; 3094 struct sysctl_oid *tree; 3095 struct fxp_hwstats *hsp; 3096 3097 ctx = device_get_sysctl_ctx(sc->dev); 3098 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3099 3100 SYSCTL_ADD_PROC(ctx, child, 3101 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 3102 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 3103 "FXP driver receive interrupt microcode bundling delay"); 3104 SYSCTL_ADD_PROC(ctx, child, 3105 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 3106 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 3107 "FXP driver receive interrupt microcode bundle size limit"); 3108 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 3109 "FXP RNR events"); 3110 3111 /* 3112 * Pull in device tunables. 3113 */ 3114 sc->tunable_int_delay = TUNABLE_INT_DELAY; 3115 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 3116 (void) resource_int_value(device_get_name(sc->dev), 3117 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay); 3118 (void) resource_int_value(device_get_name(sc->dev), 3119 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max); 3120 sc->rnr = 0; 3121 3122 hsp = &sc->fxp_hwstats; 3123 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3124 NULL, "FXP statistics"); 3125 parent = SYSCTL_CHILDREN(tree); 3126 3127 /* Rx MAC statistics. */ 3128 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3129 NULL, "Rx MAC statistics"); 3130 child = SYSCTL_CHILDREN(tree); 3131 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3132 &hsp->rx_good, "Good frames"); 3133 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors", 3134 &hsp->rx_crc_errors, "CRC errors"); 3135 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors", 3136 &hsp->rx_alignment_errors, "Alignment errors"); 3137 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors", 3138 &hsp->rx_rnr_errors, "RNR errors"); 3139 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors", 3140 &hsp->rx_overrun_errors, "Overrun errors"); 3141 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors", 3142 &hsp->rx_cdt_errors, "Collision detect errors"); 3143 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes", 3144 &hsp->rx_shortframes, "Short frame errors"); 3145 if (sc->revision >= FXP_REV_82558_A4) { 3146 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3147 &hsp->rx_pause, "Pause frames"); 3148 FXP_SYSCTL_STAT_ADD(ctx, child, "controls", 3149 &hsp->rx_controls, "Unsupported control frames"); 3150 } 3151 if (sc->revision >= FXP_REV_82559_A0) 3152 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3153 &hsp->rx_tco, "TCO frames"); 3154 3155 /* Tx MAC statistics. */ 3156 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3157 NULL, "Tx MAC statistics"); 3158 child = SYSCTL_CHILDREN(tree); 3159 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames", 3160 &hsp->tx_good, "Good frames"); 3161 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols", 3162 &hsp->tx_maxcols, "Maximum collisions errors"); 3163 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols", 3164 &hsp->tx_latecols, "Late collisions errors"); 3165 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns", 3166 &hsp->tx_underruns, "Underrun errors"); 3167 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs", 3168 &hsp->tx_lostcrs, "Lost carrier sense"); 3169 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered", 3170 &hsp->tx_deffered, "Deferred"); 3171 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions", 3172 &hsp->tx_single_collisions, "Single collisions"); 3173 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions", 3174 &hsp->tx_multiple_collisions, "Multiple collisions"); 3175 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions", 3176 &hsp->tx_total_collisions, "Total collisions"); 3177 if (sc->revision >= FXP_REV_82558_A4) 3178 FXP_SYSCTL_STAT_ADD(ctx, child, "pause", 3179 &hsp->tx_pause, "Pause frames"); 3180 if (sc->revision >= FXP_REV_82559_A0) 3181 FXP_SYSCTL_STAT_ADD(ctx, child, "tco", 3182 &hsp->tx_tco, "TCO frames"); 3183} 3184 3185#undef FXP_SYSCTL_STAT_ADD 3186 3187static int 3188sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3189{ 3190 int error, value; 3191 3192 value = *(int *)arg1; 3193 error = sysctl_handle_int(oidp, &value, 0, req); 3194 if (error || !req->newptr) 3195 return (error); 3196 if (value < low || value > high) 3197 return (EINVAL); 3198 *(int *)arg1 = value; 3199 return (0); 3200} 3201 3202/* 3203 * Interrupt delay is expressed in microseconds, a multiplier is used 3204 * to convert this to the appropriate clock ticks before using. 3205 */ 3206static int 3207sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3208{ 3209 3210 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3211} 3212 3213static int 3214sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3215{ 3216 3217 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3218} 3219