if_fxp.c revision 194572
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 194572 2009-06-21 06:46:32Z yongari $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#ifdef HAVE_KERNEL_OPTION_HEADERS 38#include "opt_device_polling.h" 39#endif 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/mbuf.h> 47#include <sys/lock.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/ip.h> 67#include <netinet/tcp.h> 68#include <netinet/udp.h> 69 70#include <machine/bus.h> 71#include <machine/in_cksum.h> 72#include <machine/resource.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 76 77#include <dev/mii/mii.h> 78#include <dev/mii/miivar.h> 79 80#include <dev/fxp/if_fxpreg.h> 81#include <dev/fxp/if_fxpvar.h> 82#include <dev/fxp/rcvbundl.h> 83 84MODULE_DEPEND(fxp, pci, 1, 1, 1); 85MODULE_DEPEND(fxp, ether, 1, 1, 1); 86MODULE_DEPEND(fxp, miibus, 1, 1, 1); 87#include "miibus_if.h" 88 89/* 90 * NOTE! On the Alpha, we have an alignment constraint. The 91 * card DMAs the packet immediately following the RFA. However, 92 * the first thing in the packet is a 14-byte Ethernet header. 93 * This means that the packet is misaligned. To compensate, 94 * we actually offset the RFA 2 bytes into the cluster. This 95 * alignes the packet after the Ethernet header at a 32-bit 96 * boundary. HOWEVER! This means that the RFA is misaligned! 97 */ 98#define RFA_ALIGNMENT_FUDGE 2 99 100/* 101 * Set initial transmit threshold at 64 (512 bytes). This is 102 * increased by 64 (512 bytes) at a time, to maximum of 192 103 * (1536 bytes), if an underrun occurs. 104 */ 105static int tx_threshold = 64; 106 107/* 108 * The configuration byte map has several undefined fields which 109 * must be one or must be zero. Set up a template for these bits 110 * only, (assuming a 82557 chip) leaving the actual configuration 111 * to fxp_init. 112 * 113 * See struct fxp_cb_config for the bit definitions. 114 */ 115static u_char fxp_cb_config_template[] = { 116 0x0, 0x0, /* cb_status */ 117 0x0, 0x0, /* cb_command */ 118 0x0, 0x0, 0x0, 0x0, /* link_addr */ 119 0x0, /* 0 */ 120 0x0, /* 1 */ 121 0x0, /* 2 */ 122 0x0, /* 3 */ 123 0x0, /* 4 */ 124 0x0, /* 5 */ 125 0x32, /* 6 */ 126 0x0, /* 7 */ 127 0x0, /* 8 */ 128 0x0, /* 9 */ 129 0x6, /* 10 */ 130 0x0, /* 11 */ 131 0x0, /* 12 */ 132 0x0, /* 13 */ 133 0xf2, /* 14 */ 134 0x48, /* 15 */ 135 0x0, /* 16 */ 136 0x40, /* 17 */ 137 0xf0, /* 18 */ 138 0x0, /* 19 */ 139 0x3f, /* 20 */ 140 0x5 /* 21 */ 141}; 142 143struct fxp_ident { 144 uint16_t devid; 145 int16_t revid; /* -1 matches anything */ 146 char *name; 147}; 148 149/* 150 * Claim various Intel PCI device identifiers for this driver. The 151 * sub-vendor and sub-device field are extensively used to identify 152 * particular variants, but we don't currently differentiate between 153 * them. 154 */ 155static struct fxp_ident fxp_ident_table[] = { 156 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 157 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 158 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 160 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 170 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 171 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 172 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 173 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 175 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 176 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 177 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 178 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 179 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 180 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 181 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 182 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 183 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 184 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 185 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 186 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 187 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 188 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 189 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 190 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 191 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 192 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 193 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 194 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 195 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 196 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 197 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 198 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 199 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 200 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 201 { 0, -1, NULL }, 202}; 203 204#ifdef FXP_IP_CSUM_WAR 205#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 206#else 207#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 208#endif 209 210static int fxp_probe(device_t dev); 211static int fxp_attach(device_t dev); 212static int fxp_detach(device_t dev); 213static int fxp_shutdown(device_t dev); 214static int fxp_suspend(device_t dev); 215static int fxp_resume(device_t dev); 216 217static void fxp_intr(void *xsc); 218static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 219 struct mbuf *m, uint16_t status, int pos); 220static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 221 uint8_t statack, int count); 222static void fxp_init(void *xsc); 223static void fxp_init_body(struct fxp_softc *sc); 224static void fxp_tick(void *xsc); 225static void fxp_start(struct ifnet *ifp); 226static void fxp_start_body(struct ifnet *ifp); 227static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 228static void fxp_txeof(struct fxp_softc *sc); 229static void fxp_stop(struct fxp_softc *sc); 230static void fxp_release(struct fxp_softc *sc); 231static int fxp_ioctl(struct ifnet *ifp, u_long command, 232 caddr_t data); 233static void fxp_watchdog(struct fxp_softc *sc); 234static void fxp_add_rfabuf(struct fxp_softc *sc, 235 struct fxp_rx *rxp); 236static void fxp_discard_rfabuf(struct fxp_softc *sc, 237 struct fxp_rx *rxp); 238static int fxp_new_rfabuf(struct fxp_softc *sc, 239 struct fxp_rx *rxp); 240static int fxp_mc_addrs(struct fxp_softc *sc); 241static void fxp_mc_setup(struct fxp_softc *sc); 242static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 243 int autosize); 244static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 245 uint16_t data); 246static void fxp_autosize_eeprom(struct fxp_softc *sc); 247static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 248 int offset, int words); 249static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 250 int offset, int words); 251static int fxp_ifmedia_upd(struct ifnet *ifp); 252static void fxp_ifmedia_sts(struct ifnet *ifp, 253 struct ifmediareq *ifmr); 254static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 255static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 256 struct ifmediareq *ifmr); 257static int fxp_miibus_readreg(device_t dev, int phy, int reg); 258static int fxp_miibus_writereg(device_t dev, int phy, int reg, 259 int value); 260static void fxp_load_ucode(struct fxp_softc *sc); 261static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 262 int low, int high); 263static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 264static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 265static void fxp_scb_wait(struct fxp_softc *sc); 266static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 267static void fxp_dma_wait(struct fxp_softc *sc, 268 volatile uint16_t *status, bus_dma_tag_t dmat, 269 bus_dmamap_t map); 270 271static device_method_t fxp_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, fxp_probe), 274 DEVMETHOD(device_attach, fxp_attach), 275 DEVMETHOD(device_detach, fxp_detach), 276 DEVMETHOD(device_shutdown, fxp_shutdown), 277 DEVMETHOD(device_suspend, fxp_suspend), 278 DEVMETHOD(device_resume, fxp_resume), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 282 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 283 284 { 0, 0 } 285}; 286 287static driver_t fxp_driver = { 288 "fxp", 289 fxp_methods, 290 sizeof(struct fxp_softc), 291}; 292 293static devclass_t fxp_devclass; 294 295DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 296DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 297 298static struct resource_spec fxp_res_spec_mem[] = { 299 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 300 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 301 { -1, 0 } 302}; 303 304static struct resource_spec fxp_res_spec_io[] = { 305 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 306 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 307 { -1, 0 } 308}; 309 310/* 311 * Wait for the previous command to be accepted (but not necessarily 312 * completed). 313 */ 314static void 315fxp_scb_wait(struct fxp_softc *sc) 316{ 317 union { 318 uint16_t w; 319 uint8_t b[2]; 320 } flowctl; 321 int i = 10000; 322 323 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 324 DELAY(2); 325 if (i == 0) { 326 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 327 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 328 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 329 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 330 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 331 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 332 } 333} 334 335static void 336fxp_scb_cmd(struct fxp_softc *sc, int cmd) 337{ 338 339 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 340 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 341 fxp_scb_wait(sc); 342 } 343 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 344} 345 346static void 347fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 348 bus_dma_tag_t dmat, bus_dmamap_t map) 349{ 350 int i; 351 352 for (i = 10000; i > 0; i--) { 353 DELAY(2); 354 bus_dmamap_sync(dmat, map, 355 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 356 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 357 break; 358 } 359 if (i == 0) 360 device_printf(sc->dev, "DMA timeout\n"); 361} 362 363/* 364 * Return identification string if this device is ours. 365 */ 366static int 367fxp_probe(device_t dev) 368{ 369 uint16_t devid; 370 uint8_t revid; 371 struct fxp_ident *ident; 372 373 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 374 devid = pci_get_device(dev); 375 revid = pci_get_revid(dev); 376 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 377 if (ident->devid == devid && 378 (ident->revid == revid || ident->revid == -1)) { 379 device_set_desc(dev, ident->name); 380 return (BUS_PROBE_DEFAULT); 381 } 382 } 383 } 384 return (ENXIO); 385} 386 387static void 388fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 389{ 390 uint32_t *addr; 391 392 if (error) 393 return; 394 395 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 396 addr = arg; 397 *addr = segs->ds_addr; 398} 399 400static int 401fxp_attach(device_t dev) 402{ 403 struct fxp_softc *sc; 404 struct fxp_cb_tx *tcbp; 405 struct fxp_tx *txp; 406 struct fxp_rx *rxp; 407 struct ifnet *ifp; 408 uint32_t val; 409 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 410 u_char eaddr[ETHER_ADDR_LEN]; 411 int i, pmc, prefer_iomap; 412 int error; 413 414 error = 0; 415 sc = device_get_softc(dev); 416 sc->dev = dev; 417 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 418 MTX_DEF); 419 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 420 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 421 fxp_serial_ifmedia_sts); 422 423 ifp = sc->ifp = if_alloc(IFT_ETHER); 424 if (ifp == NULL) { 425 device_printf(dev, "can not if_alloc()\n"); 426 error = ENOSPC; 427 goto fail; 428 } 429 430 /* 431 * Enable bus mastering. 432 */ 433 pci_enable_busmaster(dev); 434 val = pci_read_config(dev, PCIR_COMMAND, 2); 435 436 /* 437 * Figure out which we should try first - memory mapping or i/o mapping? 438 * We default to memory mapping. Then we accept an override from the 439 * command line. Then we check to see which one is enabled. 440 */ 441 prefer_iomap = 0; 442 resource_int_value(device_get_name(dev), device_get_unit(dev), 443 "prefer_iomap", &prefer_iomap); 444 if (prefer_iomap) 445 sc->fxp_spec = fxp_res_spec_io; 446 else 447 sc->fxp_spec = fxp_res_spec_mem; 448 449 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 450 if (error) { 451 if (sc->fxp_spec == fxp_res_spec_mem) 452 sc->fxp_spec = fxp_res_spec_io; 453 else 454 sc->fxp_spec = fxp_res_spec_mem; 455 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 456 } 457 if (error) { 458 device_printf(dev, "could not allocate resources\n"); 459 error = ENXIO; 460 goto fail; 461 } 462 463 if (bootverbose) { 464 device_printf(dev, "using %s space register mapping\n", 465 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 466 } 467 468 /* 469 * Put CU/RU idle state and prepare full reset. 470 */ 471 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 472 DELAY(10); 473 /* Full reset and disable interrupts. */ 474 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 475 DELAY(10); 476 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 477 478 /* 479 * Find out how large of an SEEPROM we have. 480 */ 481 fxp_autosize_eeprom(sc); 482 483 /* 484 * Find out the chip revision; lump all 82557 revs together. 485 */ 486 fxp_read_eeprom(sc, &data, 5, 1); 487 if ((data >> 8) == 1) 488 sc->revision = FXP_REV_82557; 489 else 490 sc->revision = pci_get_revid(dev); 491 492 /* 493 * Check availability of WOL. 82559ER does not support WOL. 494 */ 495 if (sc->revision >= FXP_REV_82558_A4 && 496 sc->revision != FXP_REV_82559S_A) { 497 fxp_read_eeprom(sc, &data, 10, 1); 498 if ((data & 0x20) != 0 && 499 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) 500 sc->flags |= FXP_FLAG_WOLCAP; 501 } 502 503 /* Receiver lock-up workaround detection. */ 504 fxp_read_eeprom(sc, &data, 3, 1); 505 if ((data & 0x03) != 0x03) { 506 sc->flags |= FXP_FLAG_RXBUG; 507 device_printf(dev, "Enabling Rx lock-up workaround\n"); 508 } 509 510 /* 511 * Determine whether we must use the 503 serial interface. 512 */ 513 fxp_read_eeprom(sc, &data, 6, 1); 514 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 515 && (data & FXP_PHY_SERIAL_ONLY)) 516 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 517 518 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 519 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 520 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 521 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 522 "FXP driver receive interrupt microcode bundling delay"); 523 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 524 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 525 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 526 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 527 "FXP driver receive interrupt microcode bundle size limit"); 528 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 529 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 530 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 531 "FXP RNR events"); 532 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 534 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 535 "FXP flow control disabled"); 536 537 /* 538 * Pull in device tunables. 539 */ 540 sc->tunable_int_delay = TUNABLE_INT_DELAY; 541 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 542 sc->tunable_noflow = 1; 543 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 544 "int_delay", &sc->tunable_int_delay); 545 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 546 "bundle_max", &sc->tunable_bundle_max); 547 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 548 "noflow", &sc->tunable_noflow); 549 sc->rnr = 0; 550 551 /* 552 * Enable workarounds for certain chip revision deficiencies. 553 * 554 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 555 * some systems based a normal 82559 design, have a defect where 556 * the chip can cause a PCI protocol violation if it receives 557 * a CU_RESUME command when it is entering the IDLE state. The 558 * workaround is to disable Dynamic Standby Mode, so the chip never 559 * deasserts CLKRUN#, and always remains in an active state. 560 * 561 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 562 */ 563 i = pci_get_device(dev); 564 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 565 sc->revision >= FXP_REV_82559_A0) { 566 fxp_read_eeprom(sc, &data, 10, 1); 567 if (data & 0x02) { /* STB enable */ 568 uint16_t cksum; 569 int i; 570 571 device_printf(dev, 572 "Disabling dynamic standby mode in EEPROM\n"); 573 data &= ~0x02; 574 fxp_write_eeprom(sc, &data, 10, 1); 575 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 576 cksum = 0; 577 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 578 fxp_read_eeprom(sc, &data, i, 1); 579 cksum += data; 580 } 581 i = (1 << sc->eeprom_size) - 1; 582 cksum = 0xBABA - cksum; 583 fxp_read_eeprom(sc, &data, i, 1); 584 fxp_write_eeprom(sc, &cksum, i, 1); 585 device_printf(dev, 586 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 587 i, data, cksum); 588#if 1 589 /* 590 * If the user elects to continue, try the software 591 * workaround, as it is better than nothing. 592 */ 593 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 594#endif 595 } 596 } 597 598 /* 599 * If we are not a 82557 chip, we can enable extended features. 600 */ 601 if (sc->revision != FXP_REV_82557) { 602 /* 603 * If MWI is enabled in the PCI configuration, and there 604 * is a valid cacheline size (8 or 16 dwords), then tell 605 * the board to turn on MWI. 606 */ 607 if (val & PCIM_CMD_MWRICEN && 608 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 609 sc->flags |= FXP_FLAG_MWI_ENABLE; 610 611 /* turn on the extended TxCB feature */ 612 sc->flags |= FXP_FLAG_EXT_TXCB; 613 614 /* enable reception of long frames for VLAN */ 615 sc->flags |= FXP_FLAG_LONG_PKT_EN; 616 } else { 617 /* a hack to get long VLAN frames on a 82557 */ 618 sc->flags |= FXP_FLAG_SAVE_BAD; 619 } 620 621 /* For 82559 or later chips, Rx checksum offload is supported. */ 622 if (sc->revision >= FXP_REV_82559_A0) 623 sc->flags |= FXP_FLAG_82559_RXCSUM; 624 /* 625 * Enable use of extended RFDs and TCBs for 82550 626 * and later chips. Note: we need extended TXCB support 627 * too, but that's already enabled by the code above. 628 * Be careful to do this only on the right devices. 629 */ 630 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 631 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 632 || sc->revision == FXP_REV_82551_10) { 633 sc->rfa_size = sizeof (struct fxp_rfa); 634 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 635 sc->flags |= FXP_FLAG_EXT_RFA; 636 /* Use extended RFA instead of 82559 checksum mode. */ 637 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 638 } else { 639 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 640 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 641 } 642 643 /* 644 * Allocate DMA tags and DMA safe memory. 645 */ 646 sc->maxtxseg = FXP_NTXSEG; 647 sc->maxsegsize = MCLBYTES; 648 if (sc->flags & FXP_FLAG_EXT_RFA) { 649 sc->maxtxseg--; 650 sc->maxsegsize = FXP_TSO_SEGSIZE; 651 } 652 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 653 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 654 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 655 sc->maxtxseg, sc->maxsegsize, 0, 656 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 657 if (error) { 658 device_printf(dev, "could not create TX DMA tag\n"); 659 goto fail; 660 } 661 662 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 663 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 664 MCLBYTES, 1, MCLBYTES, 0, 665 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 666 if (error) { 667 device_printf(dev, "could not create RX DMA tag\n"); 668 goto fail; 669 } 670 671 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 672 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 673 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 674 busdma_lock_mutex, &Giant, &sc->fxp_stag); 675 if (error) { 676 device_printf(dev, "could not create stats DMA tag\n"); 677 goto fail; 678 } 679 680 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 681 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 682 if (error) { 683 device_printf(dev, "could not allocate stats DMA memory\n"); 684 goto fail; 685 } 686 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 687 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 688 if (error) { 689 device_printf(dev, "could not load the stats DMA buffer\n"); 690 goto fail; 691 } 692 693 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 694 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 695 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 696 busdma_lock_mutex, &Giant, &sc->cbl_tag); 697 if (error) { 698 device_printf(dev, "could not create TxCB DMA tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 704 if (error) { 705 device_printf(dev, "could not allocate TxCB DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 710 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 711 &sc->fxp_desc.cbl_addr, 0); 712 if (error) { 713 device_printf(dev, "could not load TxCB DMA buffer\n"); 714 goto fail; 715 } 716 717 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 718 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 719 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 720 busdma_lock_mutex, &Giant, &sc->mcs_tag); 721 if (error) { 722 device_printf(dev, 723 "could not create multicast setup DMA tag\n"); 724 goto fail; 725 } 726 727 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 728 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->mcs_map); 729 if (error) { 730 device_printf(dev, 731 "could not allocate multicast setup DMA memory\n"); 732 goto fail; 733 } 734 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 735 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 736 if (error) { 737 device_printf(dev, 738 "can't load the multicast setup DMA buffer\n"); 739 goto fail; 740 } 741 742 /* 743 * Pre-allocate the TX DMA maps and setup the pointers to 744 * the TX command blocks. 745 */ 746 txp = sc->fxp_desc.tx_list; 747 tcbp = sc->fxp_desc.cbl_list; 748 for (i = 0; i < FXP_NTXCB; i++) { 749 txp[i].tx_cb = tcbp + i; 750 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 751 if (error) { 752 device_printf(dev, "can't create DMA map for TX\n"); 753 goto fail; 754 } 755 } 756 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 757 if (error) { 758 device_printf(dev, "can't create spare DMA map\n"); 759 goto fail; 760 } 761 762 /* 763 * Pre-allocate our receive buffers. 764 */ 765 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 766 for (i = 0; i < FXP_NRFABUFS; i++) { 767 rxp = &sc->fxp_desc.rx_list[i]; 768 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 769 if (error) { 770 device_printf(dev, "can't create DMA map for RX\n"); 771 goto fail; 772 } 773 if (fxp_new_rfabuf(sc, rxp) != 0) { 774 error = ENOMEM; 775 goto fail; 776 } 777 fxp_add_rfabuf(sc, rxp); 778 } 779 780 /* 781 * Read MAC address. 782 */ 783 fxp_read_eeprom(sc, myea, 0, 3); 784 eaddr[0] = myea[0] & 0xff; 785 eaddr[1] = myea[0] >> 8; 786 eaddr[2] = myea[1] & 0xff; 787 eaddr[3] = myea[1] >> 8; 788 eaddr[4] = myea[2] & 0xff; 789 eaddr[5] = myea[2] >> 8; 790 if (bootverbose) { 791 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 792 pci_get_vendor(dev), pci_get_device(dev), 793 pci_get_subvendor(dev), pci_get_subdevice(dev), 794 pci_get_revid(dev)); 795 fxp_read_eeprom(sc, &data, 10, 1); 796 device_printf(dev, "Dynamic Standby mode is %s\n", 797 data & 0x02 ? "enabled" : "disabled"); 798 } 799 800 /* 801 * If this is only a 10Mbps device, then there is no MII, and 802 * the PHY will use a serial interface instead. 803 * 804 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 805 * doesn't have a programming interface of any sort. The 806 * media is sensed automatically based on how the link partner 807 * is configured. This is, in essence, manual configuration. 808 */ 809 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 810 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 811 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 812 } else { 813 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 814 fxp_ifmedia_sts)) { 815 device_printf(dev, "MII without any PHY!\n"); 816 error = ENXIO; 817 goto fail; 818 } 819 } 820 821 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 822 ifp->if_init = fxp_init; 823 ifp->if_softc = sc; 824 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 825 ifp->if_ioctl = fxp_ioctl; 826 ifp->if_start = fxp_start; 827 828 ifp->if_capabilities = ifp->if_capenable = 0; 829 830 /* Enable checksum offload/TSO for 82550 or better chips */ 831 if (sc->flags & FXP_FLAG_EXT_RFA) { 832 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 833 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 834 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 835 } 836 837 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 838 ifp->if_capabilities |= IFCAP_RXCSUM; 839 ifp->if_capenable |= IFCAP_RXCSUM; 840 } 841 842 if (sc->flags & FXP_FLAG_WOLCAP) { 843 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 844 ifp->if_capenable |= IFCAP_WOL_MAGIC; 845 } 846 847#ifdef DEVICE_POLLING 848 /* Inform the world we support polling. */ 849 ifp->if_capabilities |= IFCAP_POLLING; 850#endif 851 852 /* 853 * Attach the interface. 854 */ 855 ether_ifattach(ifp, eaddr); 856 857 /* 858 * Tell the upper layer(s) we support long frames. 859 * Must appear after the call to ether_ifattach() because 860 * ether_ifattach() sets ifi_hdrlen to the default value. 861 */ 862 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 863 ifp->if_capabilities |= IFCAP_VLAN_MTU; 864 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 865 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 866 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 867 IFCAP_VLAN_HWCSUM; 868 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 869 IFCAP_VLAN_HWCSUM; 870 } 871 872 /* 873 * Let the system queue as many packets as we have available 874 * TX descriptors. 875 */ 876 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 877 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 878 IFQ_SET_READY(&ifp->if_snd); 879 880 /* 881 * Hook our interrupt after all initialization is complete. 882 */ 883 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 884 NULL, fxp_intr, sc, &sc->ih); 885 if (error) { 886 device_printf(dev, "could not setup irq\n"); 887 ether_ifdetach(sc->ifp); 888 goto fail; 889 } 890 891 /* 892 * Configure hardware to reject magic frames otherwise 893 * system will hang on recipt of magic frames. 894 */ 895 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 896 FXP_LOCK(sc); 897 /* Clear wakeup events. */ 898 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 899 fxp_init_body(sc); 900 fxp_stop(sc); 901 FXP_UNLOCK(sc); 902 } 903 904fail: 905 if (error) 906 fxp_release(sc); 907 return (error); 908} 909 910/* 911 * Release all resources. The softc lock should not be held and the 912 * interrupt should already be torn down. 913 */ 914static void 915fxp_release(struct fxp_softc *sc) 916{ 917 struct fxp_rx *rxp; 918 struct fxp_tx *txp; 919 int i; 920 921 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 922 KASSERT(sc->ih == NULL, 923 ("fxp_release() called with intr handle still active")); 924 if (sc->miibus) 925 device_delete_child(sc->dev, sc->miibus); 926 bus_generic_detach(sc->dev); 927 ifmedia_removeall(&sc->sc_media); 928 if (sc->fxp_desc.cbl_list) { 929 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 930 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 931 sc->cbl_map); 932 } 933 if (sc->fxp_stats) { 934 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 935 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 936 } 937 if (sc->mcsp) { 938 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 939 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 940 } 941 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 942 if (sc->fxp_rxmtag) { 943 for (i = 0; i < FXP_NRFABUFS; i++) { 944 rxp = &sc->fxp_desc.rx_list[i]; 945 if (rxp->rx_mbuf != NULL) { 946 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 947 BUS_DMASYNC_POSTREAD); 948 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 949 m_freem(rxp->rx_mbuf); 950 } 951 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 952 } 953 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 954 bus_dma_tag_destroy(sc->fxp_rxmtag); 955 } 956 if (sc->fxp_txmtag) { 957 for (i = 0; i < FXP_NTXCB; i++) { 958 txp = &sc->fxp_desc.tx_list[i]; 959 if (txp->tx_mbuf != NULL) { 960 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 961 BUS_DMASYNC_POSTWRITE); 962 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 963 m_freem(txp->tx_mbuf); 964 } 965 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 966 } 967 bus_dma_tag_destroy(sc->fxp_txmtag); 968 } 969 if (sc->fxp_stag) 970 bus_dma_tag_destroy(sc->fxp_stag); 971 if (sc->cbl_tag) 972 bus_dma_tag_destroy(sc->cbl_tag); 973 if (sc->mcs_tag) 974 bus_dma_tag_destroy(sc->mcs_tag); 975 if (sc->ifp) 976 if_free(sc->ifp); 977 978 mtx_destroy(&sc->sc_mtx); 979} 980 981/* 982 * Detach interface. 983 */ 984static int 985fxp_detach(device_t dev) 986{ 987 struct fxp_softc *sc = device_get_softc(dev); 988 989#ifdef DEVICE_POLLING 990 if (sc->ifp->if_capenable & IFCAP_POLLING) 991 ether_poll_deregister(sc->ifp); 992#endif 993 994 FXP_LOCK(sc); 995 /* 996 * Stop DMA and drop transmit queue, but disable interrupts first. 997 */ 998 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 999 fxp_stop(sc); 1000 FXP_UNLOCK(sc); 1001 callout_drain(&sc->stat_ch); 1002 1003 /* 1004 * Close down routes etc. 1005 */ 1006 ether_ifdetach(sc->ifp); 1007 1008 /* 1009 * Unhook interrupt before dropping lock. This is to prevent 1010 * races with fxp_intr(). 1011 */ 1012 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1013 sc->ih = NULL; 1014 1015 /* Release our allocated resources. */ 1016 fxp_release(sc); 1017 return (0); 1018} 1019 1020/* 1021 * Device shutdown routine. Called at system shutdown after sync. The 1022 * main purpose of this routine is to shut off receiver DMA so that 1023 * kernel memory doesn't get clobbered during warmboot. 1024 */ 1025static int 1026fxp_shutdown(device_t dev) 1027{ 1028 1029 /* 1030 * Make sure that DMA is disabled prior to reboot. Not doing 1031 * do could allow DMA to corrupt kernel memory during the 1032 * reboot before the driver initializes. 1033 */ 1034 return (fxp_suspend(dev)); 1035} 1036 1037/* 1038 * Device suspend routine. Stop the interface and save some PCI 1039 * settings in case the BIOS doesn't restore them properly on 1040 * resume. 1041 */ 1042static int 1043fxp_suspend(device_t dev) 1044{ 1045 struct fxp_softc *sc = device_get_softc(dev); 1046 struct ifnet *ifp; 1047 int pmc; 1048 uint16_t pmstat; 1049 1050 FXP_LOCK(sc); 1051 1052 ifp = sc->ifp; 1053 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1054 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1055 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1056 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1057 /* Request PME. */ 1058 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1059 sc->flags |= FXP_FLAG_WOL; 1060 /* Reconfigure hardware to accept magic frames. */ 1061 fxp_init_body(sc); 1062 } 1063 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1064 } 1065 fxp_stop(sc); 1066 1067 sc->suspended = 1; 1068 1069 FXP_UNLOCK(sc); 1070 return (0); 1071} 1072 1073/* 1074 * Device resume routine. re-enable busmastering, and restart the interface if 1075 * appropriate. 1076 */ 1077static int 1078fxp_resume(device_t dev) 1079{ 1080 struct fxp_softc *sc = device_get_softc(dev); 1081 struct ifnet *ifp = sc->ifp; 1082 int pmc; 1083 uint16_t pmstat; 1084 1085 FXP_LOCK(sc); 1086 1087 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1088 sc->flags &= ~FXP_FLAG_WOL; 1089 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1090 /* Disable PME and clear PME status. */ 1091 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1092 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1093 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1094 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1095 CSR_READ_1(sc, FXP_CSR_PMDR)); 1096 } 1097 1098 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1099 DELAY(10); 1100 1101 /* reinitialize interface if necessary */ 1102 if (ifp->if_flags & IFF_UP) 1103 fxp_init_body(sc); 1104 1105 sc->suspended = 0; 1106 1107 FXP_UNLOCK(sc); 1108 return (0); 1109} 1110 1111static void 1112fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1113{ 1114 uint16_t reg; 1115 int x; 1116 1117 /* 1118 * Shift in data. 1119 */ 1120 for (x = 1 << (length - 1); x; x >>= 1) { 1121 if (data & x) 1122 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1123 else 1124 reg = FXP_EEPROM_EECS; 1125 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1126 DELAY(1); 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1128 DELAY(1); 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1130 DELAY(1); 1131 } 1132} 1133 1134/* 1135 * Read from the serial EEPROM. Basically, you manually shift in 1136 * the read opcode (one bit at a time) and then shift in the address, 1137 * and then you shift out the data (all of this one bit at a time). 1138 * The word size is 16 bits, so you have to provide the address for 1139 * every 16 bits of data. 1140 */ 1141static uint16_t 1142fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1143{ 1144 uint16_t reg, data; 1145 int x; 1146 1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1148 /* 1149 * Shift in read opcode. 1150 */ 1151 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1152 /* 1153 * Shift in address. 1154 */ 1155 data = 0; 1156 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1157 if (offset & x) 1158 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1159 else 1160 reg = FXP_EEPROM_EECS; 1161 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1162 DELAY(1); 1163 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1164 DELAY(1); 1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1166 DELAY(1); 1167 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1168 data++; 1169 if (autosize && reg == 0) { 1170 sc->eeprom_size = data; 1171 break; 1172 } 1173 } 1174 /* 1175 * Shift out data. 1176 */ 1177 data = 0; 1178 reg = FXP_EEPROM_EECS; 1179 for (x = 1 << 15; x; x >>= 1) { 1180 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1181 DELAY(1); 1182 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1183 data |= x; 1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1185 DELAY(1); 1186 } 1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1188 DELAY(1); 1189 1190 return (data); 1191} 1192 1193static void 1194fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1195{ 1196 int i; 1197 1198 /* 1199 * Erase/write enable. 1200 */ 1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1202 fxp_eeprom_shiftin(sc, 0x4, 3); 1203 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1204 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1205 DELAY(1); 1206 /* 1207 * Shift in write opcode, address, data. 1208 */ 1209 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1210 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1211 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1212 fxp_eeprom_shiftin(sc, data, 16); 1213 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1214 DELAY(1); 1215 /* 1216 * Wait for EEPROM to finish up. 1217 */ 1218 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1219 DELAY(1); 1220 for (i = 0; i < 1000; i++) { 1221 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1222 break; 1223 DELAY(50); 1224 } 1225 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1226 DELAY(1); 1227 /* 1228 * Erase/write disable. 1229 */ 1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1231 fxp_eeprom_shiftin(sc, 0x4, 3); 1232 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1233 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1234 DELAY(1); 1235} 1236 1237/* 1238 * From NetBSD: 1239 * 1240 * Figure out EEPROM size. 1241 * 1242 * 559's can have either 64-word or 256-word EEPROMs, the 558 1243 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1244 * talks about the existance of 16 to 256 word EEPROMs. 1245 * 1246 * The only known sizes are 64 and 256, where the 256 version is used 1247 * by CardBus cards to store CIS information. 1248 * 1249 * The address is shifted in msb-to-lsb, and after the last 1250 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1251 * after which follows the actual data. We try to detect this zero, by 1252 * probing the data-out bit in the EEPROM control register just after 1253 * having shifted in a bit. If the bit is zero, we assume we've 1254 * shifted enough address bits. The data-out should be tri-state, 1255 * before this, which should translate to a logical one. 1256 */ 1257static void 1258fxp_autosize_eeprom(struct fxp_softc *sc) 1259{ 1260 1261 /* guess maximum size of 256 words */ 1262 sc->eeprom_size = 8; 1263 1264 /* autosize */ 1265 (void) fxp_eeprom_getword(sc, 0, 1); 1266} 1267 1268static void 1269fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1270{ 1271 int i; 1272 1273 for (i = 0; i < words; i++) 1274 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1275} 1276 1277static void 1278fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1279{ 1280 int i; 1281 1282 for (i = 0; i < words; i++) 1283 fxp_eeprom_putword(sc, offset + i, data[i]); 1284} 1285 1286/* 1287 * Grab the softc lock and call the real fxp_start_body() routine 1288 */ 1289static void 1290fxp_start(struct ifnet *ifp) 1291{ 1292 struct fxp_softc *sc = ifp->if_softc; 1293 1294 FXP_LOCK(sc); 1295 fxp_start_body(ifp); 1296 FXP_UNLOCK(sc); 1297} 1298 1299/* 1300 * Start packet transmission on the interface. 1301 * This routine must be called with the softc lock held, and is an 1302 * internal entry point only. 1303 */ 1304static void 1305fxp_start_body(struct ifnet *ifp) 1306{ 1307 struct fxp_softc *sc = ifp->if_softc; 1308 struct mbuf *mb_head; 1309 int txqueued; 1310 1311 FXP_LOCK_ASSERT(sc, MA_OWNED); 1312 1313 /* 1314 * See if we need to suspend xmit until the multicast filter 1315 * has been reprogrammed (which can only be done at the head 1316 * of the command chain). 1317 */ 1318 if (sc->need_mcsetup) 1319 return; 1320 1321 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1322 IFF_DRV_RUNNING) 1323 return; 1324 1325 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1326 fxp_txeof(sc); 1327 /* 1328 * We're finished if there is nothing more to add to the list or if 1329 * we're all filled up with buffers to transmit. 1330 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1331 * a NOP command when needed. 1332 */ 1333 txqueued = 0; 1334 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1335 sc->tx_queued < FXP_NTXCB - 1) { 1336 1337 /* 1338 * Grab a packet to transmit. 1339 */ 1340 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1341 if (mb_head == NULL) 1342 break; 1343 1344 if (fxp_encap(sc, &mb_head)) { 1345 if (mb_head == NULL) 1346 break; 1347 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1348 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1349 } 1350 txqueued++; 1351 /* 1352 * Pass packet to bpf if there is a listener. 1353 */ 1354 BPF_MTAP(ifp, mb_head); 1355 } 1356 1357 /* 1358 * We're finished. If we added to the list, issue a RESUME to get DMA 1359 * going again if suspended. 1360 */ 1361 if (txqueued > 0) { 1362 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1364 fxp_scb_wait(sc); 1365 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1366 /* 1367 * Set a 5 second timer just in case we don't hear 1368 * from the card again. 1369 */ 1370 sc->watchdog_timer = 5; 1371 } 1372} 1373 1374static int 1375fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1376{ 1377 struct ifnet *ifp; 1378 struct mbuf *m; 1379 struct fxp_tx *txp; 1380 struct fxp_cb_tx *cbp; 1381 struct tcphdr *tcp; 1382 bus_dma_segment_t segs[FXP_NTXSEG]; 1383 int error, i, nseg, tcp_payload; 1384 1385 FXP_LOCK_ASSERT(sc, MA_OWNED); 1386 ifp = sc->ifp; 1387 1388 tcp_payload = 0; 1389 tcp = NULL; 1390 /* 1391 * Get pointer to next available tx desc. 1392 */ 1393 txp = sc->fxp_desc.tx_last->tx_next; 1394 1395 /* 1396 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1397 * Ethernet Controller Family Open Source Software 1398 * Developer Manual says: 1399 * Using software parsing is only allowed with legal 1400 * TCP/IP or UDP/IP packets. 1401 * ... 1402 * For all other datagrams, hardware parsing must 1403 * be used. 1404 * Software parsing appears to truncate ICMP and 1405 * fragmented UDP packets that contain one to three 1406 * bytes in the second (and final) mbuf of the packet. 1407 */ 1408 if (sc->flags & FXP_FLAG_EXT_RFA) 1409 txp->tx_cb->ipcb_ip_activation_high = 1410 FXP_IPCB_HARDWAREPARSING_ENABLE; 1411 1412 m = *m_head; 1413 /* 1414 * Deal with TCP/IP checksum offload. Note that 1415 * in order for TCP checksum offload to work, 1416 * the pseudo header checksum must have already 1417 * been computed and stored in the checksum field 1418 * in the TCP header. The stack should have 1419 * already done this for us. 1420 */ 1421 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1422 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1423 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1424 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1425 1426#ifdef FXP_IP_CSUM_WAR 1427 /* 1428 * XXX The 82550 chip appears to have trouble 1429 * dealing with IP header checksums in very small 1430 * datagrams, namely fragments from 1 to 3 bytes 1431 * in size. For example, say you want to transmit 1432 * a UDP packet of 1473 bytes. The packet will be 1433 * fragmented over two IP datagrams, the latter 1434 * containing only one byte of data. The 82550 will 1435 * botch the header checksum on the 1-byte fragment. 1436 * As long as the datagram contains 4 or more bytes 1437 * of data, you're ok. 1438 * 1439 * The following code attempts to work around this 1440 * problem: if the datagram is less than 38 bytes 1441 * in size (14 bytes ether header, 20 bytes IP header, 1442 * plus 4 bytes of data), we punt and compute the IP 1443 * header checksum by hand. This workaround doesn't 1444 * work very well, however, since it can be fooled 1445 * by things like VLAN tags and IP options that make 1446 * the header sizes/offsets vary. 1447 */ 1448 1449 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1450 if (m->m_pkthdr.len < 38) { 1451 struct ip *ip; 1452 m->m_data += ETHER_HDR_LEN; 1453 ip = mtod(m, struct ip *); 1454 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1455 m->m_data -= ETHER_HDR_LEN; 1456 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1457 } else { 1458 txp->tx_cb->ipcb_ip_activation_high = 1459 FXP_IPCB_HARDWAREPARSING_ENABLE; 1460 txp->tx_cb->ipcb_ip_schedule |= 1461 FXP_IPCB_IP_CHECKSUM_ENABLE; 1462 } 1463 } 1464#endif 1465 } 1466 1467 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1468 /* 1469 * 82550/82551 requires ethernet/IP/TCP headers must be 1470 * contained in the first active transmit buffer. 1471 */ 1472 struct ether_header *eh; 1473 struct ip *ip; 1474 uint32_t ip_off, poff; 1475 1476 if (M_WRITABLE(*m_head) == 0) { 1477 /* Get a writable copy. */ 1478 m = m_dup(*m_head, M_DONTWAIT); 1479 m_freem(*m_head); 1480 if (m == NULL) { 1481 *m_head = NULL; 1482 return (ENOBUFS); 1483 } 1484 *m_head = m; 1485 } 1486 ip_off = sizeof(struct ether_header); 1487 m = m_pullup(*m_head, ip_off); 1488 if (m == NULL) { 1489 *m_head = NULL; 1490 return (ENOBUFS); 1491 } 1492 eh = mtod(m, struct ether_header *); 1493 /* Check the existence of VLAN tag. */ 1494 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1495 ip_off = sizeof(struct ether_vlan_header); 1496 m = m_pullup(m, ip_off); 1497 if (m == NULL) { 1498 *m_head = NULL; 1499 return (ENOBUFS); 1500 } 1501 } 1502 m = m_pullup(m, ip_off + sizeof(struct ip)); 1503 if (m == NULL) { 1504 *m_head = NULL; 1505 return (ENOBUFS); 1506 } 1507 ip = (struct ip *)(mtod(m, char *) + ip_off); 1508 poff = ip_off + (ip->ip_hl << 2); 1509 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1510 if (m == NULL) { 1511 *m_head = NULL; 1512 return (ENOBUFS); 1513 } 1514 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1515 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1516 if (m == NULL) { 1517 *m_head = NULL; 1518 return (ENOBUFS); 1519 } 1520 1521 /* 1522 * Since 82550/82551 doesn't modify IP length and pseudo 1523 * checksum in the first frame driver should compute it. 1524 */ 1525 ip->ip_sum = 0; 1526 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1527 (tcp->th_off << 2)); 1528 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1529 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1530 m->m_pkthdr.tso_segsz)); 1531 /* Compute total TCP payload. */ 1532 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1533 tcp_payload -= tcp->th_off << 2; 1534 *m_head = m; 1535 } 1536 1537 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1538 segs, &nseg, 0); 1539 if (error == EFBIG) { 1540 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1541 if (m == NULL) { 1542 m_freem(*m_head); 1543 *m_head = NULL; 1544 return (ENOMEM); 1545 } 1546 *m_head = m; 1547 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1548 *m_head, segs, &nseg, 0); 1549 if (error != 0) { 1550 m_freem(*m_head); 1551 *m_head = NULL; 1552 return (ENOMEM); 1553 } 1554 } else if (error != 0) 1555 return (error); 1556 if (nseg == 0) { 1557 m_freem(*m_head); 1558 *m_head = NULL; 1559 return (EIO); 1560 } 1561 1562 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1563 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1564 1565 cbp = txp->tx_cb; 1566 for (i = 0; i < nseg; i++) { 1567 /* 1568 * If this is an 82550/82551, then we're using extended 1569 * TxCBs _and_ we're using checksum offload. This means 1570 * that the TxCB is really an IPCB. One major difference 1571 * between the two is that with plain extended TxCBs, 1572 * the bottom half of the TxCB contains two entries from 1573 * the TBD array, whereas IPCBs contain just one entry: 1574 * one entry (8 bytes) has been sacrificed for the TCP/IP 1575 * checksum offload control bits. So to make things work 1576 * right, we have to start filling in the TBD array 1577 * starting from a different place depending on whether 1578 * the chip is an 82550/82551 or not. 1579 */ 1580 if (sc->flags & FXP_FLAG_EXT_RFA) { 1581 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1582 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1583 } else { 1584 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1585 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1586 } 1587 } 1588 if (sc->flags & FXP_FLAG_EXT_RFA) { 1589 /* Configure dynamic TBD for 82550/82551. */ 1590 cbp->tbd_number = 0xFF; 1591 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1592 } else 1593 cbp->tbd_number = nseg; 1594 /* Configure TSO. */ 1595 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1596 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1597 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1598 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1599 FXP_IPCB_IP_CHECKSUM_ENABLE | 1600 FXP_IPCB_TCP_PACKET | 1601 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1602 } 1603 /* Configure VLAN hardware tag insertion. */ 1604 if ((m->m_flags & M_VLANTAG) != 0) { 1605 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1606 txp->tx_cb->ipcb_ip_activation_high |= 1607 FXP_IPCB_INSERTVLAN_ENABLE; 1608 } 1609 1610 txp->tx_mbuf = m; 1611 txp->tx_cb->cb_status = 0; 1612 txp->tx_cb->byte_count = 0; 1613 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1614 txp->tx_cb->cb_command = 1615 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1616 FXP_CB_COMMAND_S); 1617 else 1618 txp->tx_cb->cb_command = 1619 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1620 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1621 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1622 txp->tx_cb->tx_threshold = tx_threshold; 1623 1624 /* 1625 * Advance the end of list forward. 1626 */ 1627 1628#ifdef __alpha__ 1629 /* 1630 * On platforms which can't access memory in 16-bit 1631 * granularities, we must prevent the card from DMA'ing 1632 * up the status while we update the command field. 1633 * This could cause us to overwrite the completion status. 1634 * XXX This is probably bogus and we're _not_ looking 1635 * for atomicity here. 1636 */ 1637 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1638 htole16(FXP_CB_COMMAND_S)); 1639#else 1640 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1641#endif /*__alpha__*/ 1642 sc->fxp_desc.tx_last = txp; 1643 1644 /* 1645 * Advance the beginning of the list forward if there are 1646 * no other packets queued (when nothing is queued, tx_first 1647 * sits on the last TxCB that was sent out). 1648 */ 1649 if (sc->tx_queued == 0) 1650 sc->fxp_desc.tx_first = txp; 1651 1652 sc->tx_queued++; 1653 1654 return (0); 1655} 1656 1657#ifdef DEVICE_POLLING 1658static poll_handler_t fxp_poll; 1659 1660static int 1661fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1662{ 1663 struct fxp_softc *sc = ifp->if_softc; 1664 uint8_t statack; 1665 int rx_npkts = 0; 1666 1667 FXP_LOCK(sc); 1668 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1669 FXP_UNLOCK(sc); 1670 return (rx_npkts); 1671 } 1672 1673 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1674 FXP_SCB_STATACK_FR; 1675 if (cmd == POLL_AND_CHECK_STATUS) { 1676 uint8_t tmp; 1677 1678 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1679 if (tmp == 0xff || tmp == 0) { 1680 FXP_UNLOCK(sc); 1681 return (rx_npkts); /* nothing to do */ 1682 } 1683 tmp &= ~statack; 1684 /* ack what we can */ 1685 if (tmp != 0) 1686 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1687 statack |= tmp; 1688 } 1689 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1690 FXP_UNLOCK(sc); 1691 return (rx_npkts); 1692} 1693#endif /* DEVICE_POLLING */ 1694 1695/* 1696 * Process interface interrupts. 1697 */ 1698static void 1699fxp_intr(void *xsc) 1700{ 1701 struct fxp_softc *sc = xsc; 1702 struct ifnet *ifp = sc->ifp; 1703 uint8_t statack; 1704 1705 FXP_LOCK(sc); 1706 if (sc->suspended) { 1707 FXP_UNLOCK(sc); 1708 return; 1709 } 1710 1711#ifdef DEVICE_POLLING 1712 if (ifp->if_capenable & IFCAP_POLLING) { 1713 FXP_UNLOCK(sc); 1714 return; 1715 } 1716#endif 1717 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1718 /* 1719 * It should not be possible to have all bits set; the 1720 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1721 * all bits are set, this may indicate that the card has 1722 * been physically ejected, so ignore it. 1723 */ 1724 if (statack == 0xff) { 1725 FXP_UNLOCK(sc); 1726 return; 1727 } 1728 1729 /* 1730 * First ACK all the interrupts in this pass. 1731 */ 1732 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1733 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1734 fxp_intr_body(sc, ifp, statack, -1); 1735 } 1736 FXP_UNLOCK(sc); 1737} 1738 1739static void 1740fxp_txeof(struct fxp_softc *sc) 1741{ 1742 struct ifnet *ifp; 1743 struct fxp_tx *txp; 1744 1745 ifp = sc->ifp; 1746 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1747 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1748 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1749 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1750 txp = txp->tx_next) { 1751 if (txp->tx_mbuf != NULL) { 1752 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1753 BUS_DMASYNC_POSTWRITE); 1754 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1755 m_freem(txp->tx_mbuf); 1756 txp->tx_mbuf = NULL; 1757 /* clear this to reset csum offload bits */ 1758 txp->tx_cb->tbd[0].tb_addr = 0; 1759 } 1760 sc->tx_queued--; 1761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1762 } 1763 sc->fxp_desc.tx_first = txp; 1764 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1765 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1766 if (sc->tx_queued == 0) { 1767 sc->watchdog_timer = 0; 1768 if (sc->need_mcsetup) 1769 fxp_mc_setup(sc); 1770 } 1771} 1772 1773static void 1774fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1775 uint16_t status, int pos) 1776{ 1777 struct ether_header *eh; 1778 struct ip *ip; 1779 struct udphdr *uh; 1780 int32_t hlen, len, pktlen, temp32; 1781 uint16_t csum, *opts; 1782 1783 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1784 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1785 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1786 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1787 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1788 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1789 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1790 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1791 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1792 CSUM_PSEUDO_HDR; 1793 m->m_pkthdr.csum_data = 0xffff; 1794 } 1795 } 1796 return; 1797 } 1798 1799 pktlen = m->m_pkthdr.len; 1800 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1801 return; 1802 eh = mtod(m, struct ether_header *); 1803 if (eh->ether_type != htons(ETHERTYPE_IP)) 1804 return; 1805 ip = (struct ip *)(eh + 1); 1806 if (ip->ip_v != IPVERSION) 1807 return; 1808 1809 hlen = ip->ip_hl << 2; 1810 pktlen -= sizeof(struct ether_header); 1811 if (hlen < sizeof(struct ip)) 1812 return; 1813 if (ntohs(ip->ip_len) < hlen) 1814 return; 1815 if (ntohs(ip->ip_len) != pktlen) 1816 return; 1817 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1818 return; /* can't handle fragmented packet */ 1819 1820 switch (ip->ip_p) { 1821 case IPPROTO_TCP: 1822 if (pktlen < (hlen + sizeof(struct tcphdr))) 1823 return; 1824 break; 1825 case IPPROTO_UDP: 1826 if (pktlen < (hlen + sizeof(struct udphdr))) 1827 return; 1828 uh = (struct udphdr *)((caddr_t)ip + hlen); 1829 if (uh->uh_sum == 0) 1830 return; /* no checksum */ 1831 break; 1832 default: 1833 return; 1834 } 1835 /* Extract computed checksum. */ 1836 csum = be16dec(mtod(m, char *) + pos); 1837 /* checksum fixup for IP options */ 1838 len = hlen - sizeof(struct ip); 1839 if (len > 0) { 1840 opts = (uint16_t *)(ip + 1); 1841 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1842 temp32 = csum - *opts; 1843 temp32 = (temp32 >> 16) + (temp32 & 65535); 1844 csum = temp32 & 65535; 1845 } 1846 } 1847 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1848 m->m_pkthdr.csum_data = csum; 1849} 1850 1851static int 1852fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1853 int count) 1854{ 1855 struct mbuf *m; 1856 struct fxp_rx *rxp; 1857 struct fxp_rfa *rfa; 1858 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1859 int rx_npkts; 1860 uint16_t status; 1861 1862 rx_npkts = 0; 1863 FXP_LOCK_ASSERT(sc, MA_OWNED); 1864 1865 if (rnr) 1866 sc->rnr++; 1867#ifdef DEVICE_POLLING 1868 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1869 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1870 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1871 rnr = 1; 1872 } 1873#endif 1874 1875 /* 1876 * Free any finished transmit mbuf chains. 1877 * 1878 * Handle the CNA event likt a CXTNO event. It used to 1879 * be that this event (control unit not ready) was not 1880 * encountered, but it is now with the SMPng modifications. 1881 * The exact sequence of events that occur when the interface 1882 * is brought up are different now, and if this event 1883 * goes unhandled, the configuration/rxfilter setup sequence 1884 * can stall for several seconds. The result is that no 1885 * packets go out onto the wire for about 5 to 10 seconds 1886 * after the interface is ifconfig'ed for the first time. 1887 */ 1888 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1889 fxp_txeof(sc); 1890 1891 /* 1892 * Try to start more packets transmitting. 1893 */ 1894 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1895 fxp_start_body(ifp); 1896 1897 /* 1898 * Just return if nothing happened on the receive side. 1899 */ 1900 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1901 return (rx_npkts); 1902 1903 /* 1904 * Process receiver interrupts. If a no-resource (RNR) 1905 * condition exists, get whatever packets we can and 1906 * re-start the receiver. 1907 * 1908 * When using polling, we do not process the list to completion, 1909 * so when we get an RNR interrupt we must defer the restart 1910 * until we hit the last buffer with the C bit set. 1911 * If we run out of cycles and rfa_headm has the C bit set, 1912 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1913 * that the info will be used in the subsequent polling cycle. 1914 */ 1915 for (;;) { 1916 rxp = sc->fxp_desc.rx_head; 1917 m = rxp->rx_mbuf; 1918 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1919 RFA_ALIGNMENT_FUDGE); 1920 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1921 BUS_DMASYNC_POSTREAD); 1922 1923#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1924 if (count >= 0 && count-- == 0) { 1925 if (rnr) { 1926 /* Defer RNR processing until the next time. */ 1927 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1928 rnr = 0; 1929 } 1930 break; 1931 } 1932#endif /* DEVICE_POLLING */ 1933 1934 status = le16toh(rfa->rfa_status); 1935 if ((status & FXP_RFA_STATUS_C) == 0) 1936 break; 1937 1938 /* 1939 * Advance head forward. 1940 */ 1941 sc->fxp_desc.rx_head = rxp->rx_next; 1942 1943 /* 1944 * Add a new buffer to the receive chain. 1945 * If this fails, the old buffer is recycled 1946 * instead. 1947 */ 1948 if (fxp_new_rfabuf(sc, rxp) == 0) { 1949 int total_len; 1950 1951 /* 1952 * Fetch packet length (the top 2 bits of 1953 * actual_size are flags set by the controller 1954 * upon completion), and drop the packet in case 1955 * of bogus length or CRC errors. 1956 */ 1957 total_len = le16toh(rfa->actual_size) & 0x3fff; 1958 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1959 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1960 /* Adjust for appended checksum bytes. */ 1961 total_len -= 2; 1962 } 1963 if (total_len < sizeof(struct ether_header) || 1964 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1965 sc->rfa_size || status & FXP_RFA_STATUS_CRC) { 1966 m_freem(m); 1967 continue; 1968 } 1969 1970 m->m_pkthdr.len = m->m_len = total_len; 1971 m->m_pkthdr.rcvif = ifp; 1972 1973 /* Do IP checksum checking. */ 1974 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1975 fxp_rxcsum(sc, ifp, m, status, total_len); 1976 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1977 (status & FXP_RFA_STATUS_VLAN) != 0) { 1978 m->m_pkthdr.ether_vtag = 1979 ntohs(rfa->rfax_vlan_id); 1980 m->m_flags |= M_VLANTAG; 1981 } 1982 /* 1983 * Drop locks before calling if_input() since it 1984 * may re-enter fxp_start() in the netisr case. 1985 * This would result in a lock reversal. Better 1986 * performance might be obtained by chaining all 1987 * packets received, dropping the lock, and then 1988 * calling if_input() on each one. 1989 */ 1990 FXP_UNLOCK(sc); 1991 (*ifp->if_input)(ifp, m); 1992 FXP_LOCK(sc); 1993 rx_npkts++; 1994 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1995 return (rx_npkts); 1996 } else { 1997 /* Reuse RFA and loaded DMA map. */ 1998 ifp->if_iqdrops++; 1999 fxp_discard_rfabuf(sc, rxp); 2000 } 2001 fxp_add_rfabuf(sc, rxp); 2002 } 2003 if (rnr) { 2004 fxp_scb_wait(sc); 2005 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2006 sc->fxp_desc.rx_head->rx_addr); 2007 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2008 } 2009 return (rx_npkts); 2010} 2011 2012/* 2013 * Update packet in/out/collision statistics. The i82557 doesn't 2014 * allow you to access these counters without doing a fairly 2015 * expensive DMA to get _all_ of the statistics it maintains, so 2016 * we do this operation here only once per second. The statistics 2017 * counters in the kernel are updated from the previous dump-stats 2018 * DMA and then a new dump-stats DMA is started. The on-chip 2019 * counters are zeroed when the DMA completes. If we can't start 2020 * the DMA immediately, we don't wait - we just prepare to read 2021 * them again next time. 2022 */ 2023static void 2024fxp_tick(void *xsc) 2025{ 2026 struct fxp_softc *sc = xsc; 2027 struct ifnet *ifp = sc->ifp; 2028 struct fxp_stats *sp = sc->fxp_stats; 2029 2030 FXP_LOCK_ASSERT(sc, MA_OWNED); 2031 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 2032 ifp->if_opackets += le32toh(sp->tx_good); 2033 ifp->if_collisions += le32toh(sp->tx_total_collisions); 2034 if (sp->rx_good) { 2035 ifp->if_ipackets += le32toh(sp->rx_good); 2036 sc->rx_idle_secs = 0; 2037 } else if (sc->flags & FXP_FLAG_RXBUG) { 2038 /* 2039 * Receiver's been idle for another second. 2040 */ 2041 sc->rx_idle_secs++; 2042 } 2043 ifp->if_ierrors += 2044 le32toh(sp->rx_crc_errors) + 2045 le32toh(sp->rx_alignment_errors) + 2046 le32toh(sp->rx_rnr_errors) + 2047 le32toh(sp->rx_overrun_errors); 2048 /* 2049 * If any transmit underruns occured, bump up the transmit 2050 * threshold by another 512 bytes (64 * 8). 2051 */ 2052 if (sp->tx_underruns) { 2053 ifp->if_oerrors += le32toh(sp->tx_underruns); 2054 if (tx_threshold < 192) 2055 tx_threshold += 64; 2056 } 2057 2058 /* 2059 * Release any xmit buffers that have completed DMA. This isn't 2060 * strictly necessary to do here, but it's advantagous for mbufs 2061 * with external storage to be released in a timely manner rather 2062 * than being defered for a potentially long time. This limits 2063 * the delay to a maximum of one second. 2064 */ 2065 fxp_txeof(sc); 2066 2067 /* 2068 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2069 * then assume the receiver has locked up and attempt to clear 2070 * the condition by reprogramming the multicast filter. This is 2071 * a work-around for a bug in the 82557 where the receiver locks 2072 * up if it gets certain types of garbage in the syncronization 2073 * bits prior to the packet header. This bug is supposed to only 2074 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2075 * mode as well (perhaps due to a 10/100 speed transition). 2076 */ 2077 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2078 sc->rx_idle_secs = 0; 2079 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2080 fxp_mc_setup(sc); 2081 } 2082 /* 2083 * If there is no pending command, start another stats 2084 * dump. Otherwise punt for now. 2085 */ 2086 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2087 /* 2088 * Start another stats dump. 2089 */ 2090 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2091 BUS_DMASYNC_PREREAD); 2092 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2093 } else { 2094 /* 2095 * A previous command is still waiting to be accepted. 2096 * Just zero our copy of the stats and wait for the 2097 * next timer event to update them. 2098 */ 2099 sp->tx_good = 0; 2100 sp->tx_underruns = 0; 2101 sp->tx_total_collisions = 0; 2102 2103 sp->rx_good = 0; 2104 sp->rx_crc_errors = 0; 2105 sp->rx_alignment_errors = 0; 2106 sp->rx_rnr_errors = 0; 2107 sp->rx_overrun_errors = 0; 2108 } 2109 if (sc->miibus != NULL) 2110 mii_tick(device_get_softc(sc->miibus)); 2111 2112 /* 2113 * Check that chip hasn't hung. 2114 */ 2115 fxp_watchdog(sc); 2116 2117 /* 2118 * Schedule another timeout one second from now. 2119 */ 2120 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2121} 2122 2123/* 2124 * Stop the interface. Cancels the statistics updater and resets 2125 * the interface. 2126 */ 2127static void 2128fxp_stop(struct fxp_softc *sc) 2129{ 2130 struct ifnet *ifp = sc->ifp; 2131 struct fxp_tx *txp; 2132 int i; 2133 2134 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2135 sc->watchdog_timer = 0; 2136 2137 /* 2138 * Cancel stats updater. 2139 */ 2140 callout_stop(&sc->stat_ch); 2141 2142 /* 2143 * Preserve PCI configuration, configure, IA/multicast 2144 * setup and put RU and CU into idle state. 2145 */ 2146 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2147 DELAY(50); 2148 /* Disable interrupts. */ 2149 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2150 2151 /* 2152 * Release any xmit buffers. 2153 */ 2154 txp = sc->fxp_desc.tx_list; 2155 if (txp != NULL) { 2156 for (i = 0; i < FXP_NTXCB; i++) { 2157 if (txp[i].tx_mbuf != NULL) { 2158 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2159 BUS_DMASYNC_POSTWRITE); 2160 bus_dmamap_unload(sc->fxp_txmtag, 2161 txp[i].tx_map); 2162 m_freem(txp[i].tx_mbuf); 2163 txp[i].tx_mbuf = NULL; 2164 /* clear this to reset csum offload bits */ 2165 txp[i].tx_cb->tbd[0].tb_addr = 0; 2166 } 2167 } 2168 } 2169 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2170 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2171 sc->tx_queued = 0; 2172} 2173 2174/* 2175 * Watchdog/transmission transmit timeout handler. Called when a 2176 * transmission is started on the interface, but no interrupt is 2177 * received before the timeout. This usually indicates that the 2178 * card has wedged for some reason. 2179 */ 2180static void 2181fxp_watchdog(struct fxp_softc *sc) 2182{ 2183 2184 FXP_LOCK_ASSERT(sc, MA_OWNED); 2185 2186 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2187 return; 2188 2189 device_printf(sc->dev, "device timeout\n"); 2190 sc->ifp->if_oerrors++; 2191 2192 fxp_init_body(sc); 2193} 2194 2195/* 2196 * Acquire locks and then call the real initialization function. This 2197 * is necessary because ether_ioctl() calls if_init() and this would 2198 * result in mutex recursion if the mutex was held. 2199 */ 2200static void 2201fxp_init(void *xsc) 2202{ 2203 struct fxp_softc *sc = xsc; 2204 2205 FXP_LOCK(sc); 2206 fxp_init_body(sc); 2207 FXP_UNLOCK(sc); 2208} 2209 2210/* 2211 * Perform device initialization. This routine must be called with the 2212 * softc lock held. 2213 */ 2214static void 2215fxp_init_body(struct fxp_softc *sc) 2216{ 2217 struct ifnet *ifp = sc->ifp; 2218 struct fxp_cb_config *cbp; 2219 struct fxp_cb_ias *cb_ias; 2220 struct fxp_cb_tx *tcbp; 2221 struct fxp_tx *txp; 2222 struct fxp_cb_mcs *mcsp; 2223 int i, prm; 2224 2225 FXP_LOCK_ASSERT(sc, MA_OWNED); 2226 /* 2227 * Cancel any pending I/O 2228 */ 2229 fxp_stop(sc); 2230 2231 /* 2232 * Issue software reset, which also unloads the microcode. 2233 */ 2234 sc->flags &= ~FXP_FLAG_UCODE; 2235 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2236 DELAY(50); 2237 2238 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2239 2240 /* 2241 * Initialize base of CBL and RFA memory. Loading with zero 2242 * sets it up for regular linear addressing. 2243 */ 2244 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2245 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2246 2247 fxp_scb_wait(sc); 2248 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2249 2250 /* 2251 * Initialize base of dump-stats buffer. 2252 */ 2253 fxp_scb_wait(sc); 2254 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2255 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2256 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2257 2258 /* 2259 * Attempt to load microcode if requested. 2260 */ 2261 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2262 fxp_load_ucode(sc); 2263 2264 /* 2265 * Initialize the multicast address list. 2266 */ 2267 if (fxp_mc_addrs(sc)) { 2268 mcsp = sc->mcsp; 2269 mcsp->cb_status = 0; 2270 mcsp->cb_command = 2271 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2272 mcsp->link_addr = 0xffffffff; 2273 /* 2274 * Start the multicast setup command. 2275 */ 2276 fxp_scb_wait(sc); 2277 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2278 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2279 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2280 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2281 /* ...and wait for it to complete. */ 2282 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2283 } 2284 2285 /* 2286 * We temporarily use memory that contains the TxCB list to 2287 * construct the config CB. The TxCB list memory is rebuilt 2288 * later. 2289 */ 2290 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2291 2292 /* 2293 * This bcopy is kind of disgusting, but there are a bunch of must be 2294 * zero and must be one bits in this structure and this is the easiest 2295 * way to initialize them all to proper values. 2296 */ 2297 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2298 2299 cbp->cb_status = 0; 2300 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2301 FXP_CB_COMMAND_EL); 2302 cbp->link_addr = 0xffffffff; /* (no) next command */ 2303 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2304 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2305 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2306 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2307 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2308 cbp->type_enable = 0; /* actually reserved */ 2309 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2310 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2311 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2312 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2313 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2314 cbp->late_scb = 0; /* (don't) defer SCB update */ 2315 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2316 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2317 cbp->ci_int = 1; /* interrupt on CU idle */ 2318 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2319 cbp->ext_stats_dis = 1; /* disable extended counters */ 2320 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2321 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2322 cbp->disc_short_rx = !prm; /* discard short packets */ 2323 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2324 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2325 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2326 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2327 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2328 cbp->csma_dis = 0; /* (don't) disable link */ 2329 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2330 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2331 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2332 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2333 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2334 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2335 cbp->nsai = 1; /* (don't) disable source addr insert */ 2336 cbp->preamble_length = 2; /* (7 byte) preamble */ 2337 cbp->loopback = 0; /* (don't) loopback */ 2338 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2339 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2340 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2341 cbp->promiscuous = prm; /* promiscuous mode */ 2342 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2343 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2344 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2345 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2346 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2347 2348 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2349 cbp->padding = 1; /* (do) pad short tx packets */ 2350 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2351 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2352 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2353 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2354 cbp->force_fdx = 0; /* (don't) force full duplex */ 2355 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2356 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2357 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2358 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2359 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2360 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2361 2362 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2363 /* 2364 * The 82557 has no hardware flow control, the values 2365 * below are the defaults for the chip. 2366 */ 2367 cbp->fc_delay_lsb = 0; 2368 cbp->fc_delay_msb = 0x40; 2369 cbp->pri_fc_thresh = 3; 2370 cbp->tx_fc_dis = 0; 2371 cbp->rx_fc_restop = 0; 2372 cbp->rx_fc_restart = 0; 2373 cbp->fc_filter = 0; 2374 cbp->pri_fc_loc = 1; 2375 } else { 2376 cbp->fc_delay_lsb = 0x1f; 2377 cbp->fc_delay_msb = 0x01; 2378 cbp->pri_fc_thresh = 3; 2379 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2380 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2381 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2382 cbp->fc_filter = !prm; /* drop FC frames to host */ 2383 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2384 } 2385 2386 /* 2387 * Start the config command/DMA. 2388 */ 2389 fxp_scb_wait(sc); 2390 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2391 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2392 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2393 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2394 /* ...and wait for it to complete. */ 2395 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2396 2397 /* 2398 * Now initialize the station address. Temporarily use the TxCB 2399 * memory area like we did above for the config CB. 2400 */ 2401 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2402 cb_ias->cb_status = 0; 2403 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2404 cb_ias->link_addr = 0xffffffff; 2405 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2406 2407 /* 2408 * Start the IAS (Individual Address Setup) command/DMA. 2409 */ 2410 fxp_scb_wait(sc); 2411 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2412 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2413 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2414 /* ...and wait for it to complete. */ 2415 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2416 2417 /* 2418 * Initialize transmit control block (TxCB) list. 2419 */ 2420 txp = sc->fxp_desc.tx_list; 2421 tcbp = sc->fxp_desc.cbl_list; 2422 bzero(tcbp, FXP_TXCB_SZ); 2423 for (i = 0; i < FXP_NTXCB; i++) { 2424 txp[i].tx_mbuf = NULL; 2425 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2426 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2427 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2428 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2429 if (sc->flags & FXP_FLAG_EXT_TXCB) 2430 tcbp[i].tbd_array_addr = 2431 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2432 else 2433 tcbp[i].tbd_array_addr = 2434 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2435 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2436 } 2437 /* 2438 * Set the suspend flag on the first TxCB and start the control 2439 * unit. It will execute the NOP and then suspend. 2440 */ 2441 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2442 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2443 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2444 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2445 sc->tx_queued = 1; 2446 2447 fxp_scb_wait(sc); 2448 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2449 2450 /* 2451 * Initialize receiver buffer area - RFA. 2452 */ 2453 fxp_scb_wait(sc); 2454 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2455 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2456 2457 /* 2458 * Set current media. 2459 */ 2460 if (sc->miibus != NULL) 2461 mii_mediachg(device_get_softc(sc->miibus)); 2462 2463 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2464 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2465 2466 /* 2467 * Enable interrupts. 2468 */ 2469#ifdef DEVICE_POLLING 2470 /* 2471 * ... but only do that if we are not polling. And because (presumably) 2472 * the default is interrupts on, we need to disable them explicitly! 2473 */ 2474 if (ifp->if_capenable & IFCAP_POLLING ) 2475 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2476 else 2477#endif /* DEVICE_POLLING */ 2478 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2479 2480 /* 2481 * Start stats updater. 2482 */ 2483 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2484} 2485 2486static int 2487fxp_serial_ifmedia_upd(struct ifnet *ifp) 2488{ 2489 2490 return (0); 2491} 2492 2493static void 2494fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2495{ 2496 2497 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2498} 2499 2500/* 2501 * Change media according to request. 2502 */ 2503static int 2504fxp_ifmedia_upd(struct ifnet *ifp) 2505{ 2506 struct fxp_softc *sc = ifp->if_softc; 2507 struct mii_data *mii; 2508 2509 mii = device_get_softc(sc->miibus); 2510 FXP_LOCK(sc); 2511 if (mii->mii_instance) { 2512 struct mii_softc *miisc; 2513 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2514 mii_phy_reset(miisc); 2515 } 2516 mii_mediachg(mii); 2517 FXP_UNLOCK(sc); 2518 return (0); 2519} 2520 2521/* 2522 * Notify the world which media we're using. 2523 */ 2524static void 2525fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2526{ 2527 struct fxp_softc *sc = ifp->if_softc; 2528 struct mii_data *mii; 2529 2530 mii = device_get_softc(sc->miibus); 2531 FXP_LOCK(sc); 2532 mii_pollstat(mii); 2533 ifmr->ifm_active = mii->mii_media_active; 2534 ifmr->ifm_status = mii->mii_media_status; 2535 2536 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2537 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2538 sc->cu_resume_bug = 1; 2539 else 2540 sc->cu_resume_bug = 0; 2541 FXP_UNLOCK(sc); 2542} 2543 2544/* 2545 * Add a buffer to the end of the RFA buffer list. 2546 * Return 0 if successful, 1 for failure. A failure results in 2547 * reusing the RFA buffer. 2548 * The RFA struct is stuck at the beginning of mbuf cluster and the 2549 * data pointer is fixed up to point just past it. 2550 */ 2551static int 2552fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2553{ 2554 struct mbuf *m; 2555 struct fxp_rfa *rfa; 2556 bus_dmamap_t tmp_map; 2557 int error; 2558 2559 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2560 if (m == NULL) 2561 return (ENOBUFS); 2562 2563 /* 2564 * Move the data pointer up so that the incoming data packet 2565 * will be 32-bit aligned. 2566 */ 2567 m->m_data += RFA_ALIGNMENT_FUDGE; 2568 2569 /* 2570 * Get a pointer to the base of the mbuf cluster and move 2571 * data start past it. 2572 */ 2573 rfa = mtod(m, struct fxp_rfa *); 2574 m->m_data += sc->rfa_size; 2575 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2576 2577 rfa->rfa_status = 0; 2578 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2579 rfa->actual_size = 0; 2580 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2581 sc->rfa_size; 2582 2583 /* 2584 * Initialize the rest of the RFA. Note that since the RFA 2585 * is misaligned, we cannot store values directly. We're thus 2586 * using the le32enc() function which handles endianness and 2587 * is also alignment-safe. 2588 */ 2589 le32enc(&rfa->link_addr, 0xffffffff); 2590 le32enc(&rfa->rbd_addr, 0xffffffff); 2591 2592 /* Map the RFA into DMA memory. */ 2593 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2594 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2595 &rxp->rx_addr, 0); 2596 if (error) { 2597 m_freem(m); 2598 return (error); 2599 } 2600 2601 if (rxp->rx_mbuf != NULL) 2602 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2603 tmp_map = sc->spare_map; 2604 sc->spare_map = rxp->rx_map; 2605 rxp->rx_map = tmp_map; 2606 rxp->rx_mbuf = m; 2607 2608 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2609 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2610 return (0); 2611} 2612 2613static void 2614fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2615{ 2616 struct fxp_rfa *p_rfa; 2617 struct fxp_rx *p_rx; 2618 2619 /* 2620 * If there are other buffers already on the list, attach this 2621 * one to the end by fixing up the tail to point to this one. 2622 */ 2623 if (sc->fxp_desc.rx_head != NULL) { 2624 p_rx = sc->fxp_desc.rx_tail; 2625 p_rfa = (struct fxp_rfa *) 2626 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2627 p_rx->rx_next = rxp; 2628 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2629 p_rfa->rfa_control = 0; 2630 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2631 BUS_DMASYNC_PREWRITE); 2632 } else { 2633 rxp->rx_next = NULL; 2634 sc->fxp_desc.rx_head = rxp; 2635 } 2636 sc->fxp_desc.rx_tail = rxp; 2637} 2638 2639static void 2640fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2641{ 2642 struct mbuf *m; 2643 struct fxp_rfa *rfa; 2644 2645 m = rxp->rx_mbuf; 2646 m->m_data = m->m_ext.ext_buf; 2647 /* 2648 * Move the data pointer up so that the incoming data packet 2649 * will be 32-bit aligned. 2650 */ 2651 m->m_data += RFA_ALIGNMENT_FUDGE; 2652 2653 /* 2654 * Get a pointer to the base of the mbuf cluster and move 2655 * data start past it. 2656 */ 2657 rfa = mtod(m, struct fxp_rfa *); 2658 m->m_data += sc->rfa_size; 2659 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2660 2661 rfa->rfa_status = 0; 2662 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2663 rfa->actual_size = 0; 2664 2665 /* 2666 * Initialize the rest of the RFA. Note that since the RFA 2667 * is misaligned, we cannot store values directly. We're thus 2668 * using the le32enc() function which handles endianness and 2669 * is also alignment-safe. 2670 */ 2671 le32enc(&rfa->link_addr, 0xffffffff); 2672 le32enc(&rfa->rbd_addr, 0xffffffff); 2673 2674 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2676} 2677 2678static int 2679fxp_miibus_readreg(device_t dev, int phy, int reg) 2680{ 2681 struct fxp_softc *sc = device_get_softc(dev); 2682 int count = 10000; 2683 int value; 2684 2685 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2686 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2687 2688 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2689 && count--) 2690 DELAY(10); 2691 2692 if (count <= 0) 2693 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2694 2695 return (value & 0xffff); 2696} 2697 2698static int 2699fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2700{ 2701 struct fxp_softc *sc = device_get_softc(dev); 2702 int count = 10000; 2703 2704 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2705 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2706 (value & 0xffff)); 2707 2708 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2709 count--) 2710 DELAY(10); 2711 2712 if (count <= 0) 2713 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2714 return (0); 2715} 2716 2717static int 2718fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2719{ 2720 struct fxp_softc *sc = ifp->if_softc; 2721 struct ifreq *ifr = (struct ifreq *)data; 2722 struct mii_data *mii; 2723 int flag, mask, error = 0, reinit; 2724 2725 switch (command) { 2726 case SIOCSIFFLAGS: 2727 FXP_LOCK(sc); 2728 if (ifp->if_flags & IFF_ALLMULTI) 2729 sc->flags |= FXP_FLAG_ALL_MCAST; 2730 else 2731 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2732 2733 /* 2734 * If interface is marked up and not running, then start it. 2735 * If it is marked down and running, stop it. 2736 * XXX If it's up then re-initialize it. This is so flags 2737 * such as IFF_PROMISC are handled. 2738 */ 2739 if (ifp->if_flags & IFF_UP) { 2740 fxp_init_body(sc); 2741 } else { 2742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2743 fxp_stop(sc); 2744 } 2745 FXP_UNLOCK(sc); 2746 break; 2747 2748 case SIOCADDMULTI: 2749 case SIOCDELMULTI: 2750 FXP_LOCK(sc); 2751 if (ifp->if_flags & IFF_ALLMULTI) 2752 sc->flags |= FXP_FLAG_ALL_MCAST; 2753 else 2754 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2755 /* 2756 * Multicast list has changed; set the hardware filter 2757 * accordingly. 2758 */ 2759 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2760 fxp_mc_setup(sc); 2761 /* 2762 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2763 * again rather than else {}. 2764 */ 2765 if (sc->flags & FXP_FLAG_ALL_MCAST) 2766 fxp_init_body(sc); 2767 FXP_UNLOCK(sc); 2768 error = 0; 2769 break; 2770 2771 case SIOCSIFMEDIA: 2772 case SIOCGIFMEDIA: 2773 if (sc->miibus != NULL) { 2774 mii = device_get_softc(sc->miibus); 2775 error = ifmedia_ioctl(ifp, ifr, 2776 &mii->mii_media, command); 2777 } else { 2778 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2779 } 2780 break; 2781 2782 case SIOCSIFCAP: 2783 reinit = 0; 2784 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2785#ifdef DEVICE_POLLING 2786 if (mask & IFCAP_POLLING) { 2787 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2788 error = ether_poll_register(fxp_poll, ifp); 2789 if (error) 2790 return(error); 2791 FXP_LOCK(sc); 2792 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2793 FXP_SCB_INTR_DISABLE); 2794 ifp->if_capenable |= IFCAP_POLLING; 2795 FXP_UNLOCK(sc); 2796 } else { 2797 error = ether_poll_deregister(ifp); 2798 /* Enable interrupts in any case */ 2799 FXP_LOCK(sc); 2800 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2801 ifp->if_capenable &= ~IFCAP_POLLING; 2802 FXP_UNLOCK(sc); 2803 } 2804 } 2805#endif 2806 FXP_LOCK(sc); 2807 if ((mask & IFCAP_TXCSUM) != 0 && 2808 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2809 ifp->if_capenable ^= IFCAP_TXCSUM; 2810 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2811 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2812 else 2813 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2814 } 2815 if ((mask & IFCAP_RXCSUM) != 0 && 2816 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2817 ifp->if_capenable ^= IFCAP_RXCSUM; 2818 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2819 reinit++; 2820 } 2821 if ((mask & IFCAP_TSO4) != 0 && 2822 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2823 ifp->if_capenable ^= IFCAP_TSO4; 2824 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2825 ifp->if_hwassist |= CSUM_TSO; 2826 else 2827 ifp->if_hwassist &= ~CSUM_TSO; 2828 } 2829 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2830 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2831 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2832 if ((mask & IFCAP_VLAN_MTU) != 0 && 2833 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2834 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2835 if (sc->revision != FXP_REV_82557) 2836 flag = FXP_FLAG_LONG_PKT_EN; 2837 else /* a hack to get long frames on the old chip */ 2838 flag = FXP_FLAG_SAVE_BAD; 2839 sc->flags ^= flag; 2840 if (ifp->if_flags & IFF_UP) 2841 reinit++; 2842 } 2843 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2844 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2845 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2846 reinit++; 2847 } 2848 if (reinit > 0 && ifp->if_flags & IFF_UP) 2849 fxp_init_body(sc); 2850 FXP_UNLOCK(sc); 2851 VLAN_CAPABILITIES(ifp); 2852 break; 2853 2854 default: 2855 error = ether_ioctl(ifp, command, data); 2856 } 2857 return (error); 2858} 2859 2860/* 2861 * Fill in the multicast address list and return number of entries. 2862 */ 2863static int 2864fxp_mc_addrs(struct fxp_softc *sc) 2865{ 2866 struct fxp_cb_mcs *mcsp = sc->mcsp; 2867 struct ifnet *ifp = sc->ifp; 2868 struct ifmultiaddr *ifma; 2869 int nmcasts; 2870 2871 nmcasts = 0; 2872 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2873 IF_ADDR_LOCK(ifp); 2874 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2875 if (ifma->ifma_addr->sa_family != AF_LINK) 2876 continue; 2877 if (nmcasts >= MAXMCADDR) { 2878 sc->flags |= FXP_FLAG_ALL_MCAST; 2879 nmcasts = 0; 2880 break; 2881 } 2882 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2883 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2884 nmcasts++; 2885 } 2886 IF_ADDR_UNLOCK(ifp); 2887 } 2888 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2889 return (nmcasts); 2890} 2891 2892/* 2893 * Program the multicast filter. 2894 * 2895 * We have an artificial restriction that the multicast setup command 2896 * must be the first command in the chain, so we take steps to ensure 2897 * this. By requiring this, it allows us to keep up the performance of 2898 * the pre-initialized command ring (esp. link pointers) by not actually 2899 * inserting the mcsetup command in the ring - i.e. its link pointer 2900 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2901 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2902 * lead into the regular TxCB ring when it completes. 2903 * 2904 * This function must be called at splimp. 2905 */ 2906static void 2907fxp_mc_setup(struct fxp_softc *sc) 2908{ 2909 struct fxp_cb_mcs *mcsp = sc->mcsp; 2910 struct fxp_tx *txp; 2911 int count; 2912 2913 FXP_LOCK_ASSERT(sc, MA_OWNED); 2914 /* 2915 * If there are queued commands, we must wait until they are all 2916 * completed. If we are already waiting, then add a NOP command 2917 * with interrupt option so that we're notified when all commands 2918 * have been completed - fxp_start() ensures that no additional 2919 * TX commands will be added when need_mcsetup is true. 2920 */ 2921 if (sc->tx_queued) { 2922 /* 2923 * need_mcsetup will be true if we are already waiting for the 2924 * NOP command to be completed (see below). In this case, bail. 2925 */ 2926 if (sc->need_mcsetup) 2927 return; 2928 sc->need_mcsetup = 1; 2929 2930 /* 2931 * Add a NOP command with interrupt so that we are notified 2932 * when all TX commands have been processed. 2933 */ 2934 txp = sc->fxp_desc.tx_last->tx_next; 2935 txp->tx_mbuf = NULL; 2936 txp->tx_cb->cb_status = 0; 2937 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2938 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2939 /* 2940 * Advance the end of list forward. 2941 */ 2942 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2943 htole16(~FXP_CB_COMMAND_S); 2944 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2945 sc->fxp_desc.tx_last = txp; 2946 sc->tx_queued++; 2947 /* 2948 * Issue a resume in case the CU has just suspended. 2949 */ 2950 fxp_scb_wait(sc); 2951 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2952 /* 2953 * Set a 5 second timer just in case we don't hear from the 2954 * card again. 2955 */ 2956 sc->watchdog_timer = 5; 2957 2958 return; 2959 } 2960 sc->need_mcsetup = 0; 2961 2962 /* 2963 * Initialize multicast setup descriptor. 2964 */ 2965 mcsp->cb_status = 0; 2966 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2967 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2968 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2969 txp = &sc->fxp_desc.mcs_tx; 2970 txp->tx_mbuf = NULL; 2971 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2972 txp->tx_next = sc->fxp_desc.tx_list; 2973 (void) fxp_mc_addrs(sc); 2974 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2975 sc->tx_queued = 1; 2976 2977 /* 2978 * Wait until command unit is not active. This should never 2979 * be the case when nothing is queued, but make sure anyway. 2980 */ 2981 count = 100; 2982 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2983 FXP_SCB_CUS_ACTIVE && --count) 2984 DELAY(10); 2985 if (count == 0) { 2986 device_printf(sc->dev, "command queue timeout\n"); 2987 return; 2988 } 2989 2990 /* 2991 * Start the multicast setup command. 2992 */ 2993 fxp_scb_wait(sc); 2994 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2996 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2997 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2998 2999 sc->watchdog_timer = 2; 3000 return; 3001} 3002 3003static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 3004static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 3005static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 3006static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 3007static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 3008static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 3009static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 3010 3011#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 3012 3013struct ucode { 3014 uint32_t revision; 3015 uint32_t *ucode; 3016 int length; 3017 u_short int_delay_offset; 3018 u_short bundle_max_offset; 3019} ucode_table[] = { 3020 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 3021 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 3022 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 3023 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 3024 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 3025 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 3026 { FXP_REV_82550, UCODE(fxp_ucode_d102), 3027 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 3028 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 3029 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 3030 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 3031 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 3032 { 0, NULL, 0, 0, 0 } 3033}; 3034 3035static void 3036fxp_load_ucode(struct fxp_softc *sc) 3037{ 3038 struct ucode *uc; 3039 struct fxp_cb_ucode *cbp; 3040 int i; 3041 3042 for (uc = ucode_table; uc->ucode != NULL; uc++) 3043 if (sc->revision == uc->revision) 3044 break; 3045 if (uc->ucode == NULL) 3046 return; 3047 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3048 cbp->cb_status = 0; 3049 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3050 cbp->link_addr = 0xffffffff; /* (no) next command */ 3051 for (i = 0; i < uc->length; i++) 3052 cbp->ucode[i] = htole32(uc->ucode[i]); 3053 if (uc->int_delay_offset) 3054 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3055 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3056 if (uc->bundle_max_offset) 3057 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3058 htole16(sc->tunable_bundle_max); 3059 /* 3060 * Download the ucode to the chip. 3061 */ 3062 fxp_scb_wait(sc); 3063 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 3064 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3065 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3066 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3067 /* ...and wait for it to complete. */ 3068 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3069 device_printf(sc->dev, 3070 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3071 sc->tunable_int_delay, 3072 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3073 sc->flags |= FXP_FLAG_UCODE; 3074} 3075 3076static int 3077sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3078{ 3079 int error, value; 3080 3081 value = *(int *)arg1; 3082 error = sysctl_handle_int(oidp, &value, 0, req); 3083 if (error || !req->newptr) 3084 return (error); 3085 if (value < low || value > high) 3086 return (EINVAL); 3087 *(int *)arg1 = value; 3088 return (0); 3089} 3090 3091/* 3092 * Interrupt delay is expressed in microseconds, a multiplier is used 3093 * to convert this to the appropriate clock ticks before using. 3094 */ 3095static int 3096sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3097{ 3098 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3099} 3100 3101static int 3102sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3103{ 3104 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3105} 3106