if_fxp.c revision 186262
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 186262 2008-12-18 01:36:46Z yongari $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#ifdef HAVE_KERNEL_OPTION_HEADERS 38#include "opt_device_polling.h" 39#endif 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/mbuf.h> 47#include <sys/lock.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/ip.h> 67#include <netinet/tcp.h> 68#include <netinet/udp.h> 69 70#include <machine/bus.h> 71#include <machine/in_cksum.h> 72#include <machine/resource.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 76 77#include <dev/mii/mii.h> 78#include <dev/mii/miivar.h> 79 80#include <dev/fxp/if_fxpreg.h> 81#include <dev/fxp/if_fxpvar.h> 82#include <dev/fxp/rcvbundl.h> 83 84MODULE_DEPEND(fxp, pci, 1, 1, 1); 85MODULE_DEPEND(fxp, ether, 1, 1, 1); 86MODULE_DEPEND(fxp, miibus, 1, 1, 1); 87#include "miibus_if.h" 88 89/* 90 * NOTE! On the Alpha, we have an alignment constraint. The 91 * card DMAs the packet immediately following the RFA. However, 92 * the first thing in the packet is a 14-byte Ethernet header. 93 * This means that the packet is misaligned. To compensate, 94 * we actually offset the RFA 2 bytes into the cluster. This 95 * alignes the packet after the Ethernet header at a 32-bit 96 * boundary. HOWEVER! This means that the RFA is misaligned! 97 */ 98#define RFA_ALIGNMENT_FUDGE 2 99 100/* 101 * Set initial transmit threshold at 64 (512 bytes). This is 102 * increased by 64 (512 bytes) at a time, to maximum of 192 103 * (1536 bytes), if an underrun occurs. 104 */ 105static int tx_threshold = 64; 106 107/* 108 * The configuration byte map has several undefined fields which 109 * must be one or must be zero. Set up a template for these bits 110 * only, (assuming a 82557 chip) leaving the actual configuration 111 * to fxp_init. 112 * 113 * See struct fxp_cb_config for the bit definitions. 114 */ 115static u_char fxp_cb_config_template[] = { 116 0x0, 0x0, /* cb_status */ 117 0x0, 0x0, /* cb_command */ 118 0x0, 0x0, 0x0, 0x0, /* link_addr */ 119 0x0, /* 0 */ 120 0x0, /* 1 */ 121 0x0, /* 2 */ 122 0x0, /* 3 */ 123 0x0, /* 4 */ 124 0x0, /* 5 */ 125 0x32, /* 6 */ 126 0x0, /* 7 */ 127 0x0, /* 8 */ 128 0x0, /* 9 */ 129 0x6, /* 10 */ 130 0x0, /* 11 */ 131 0x0, /* 12 */ 132 0x0, /* 13 */ 133 0xf2, /* 14 */ 134 0x48, /* 15 */ 135 0x0, /* 16 */ 136 0x40, /* 17 */ 137 0xf0, /* 18 */ 138 0x0, /* 19 */ 139 0x3f, /* 20 */ 140 0x5 /* 21 */ 141}; 142 143struct fxp_ident { 144 uint16_t devid; 145 int16_t revid; /* -1 matches anything */ 146 char *name; 147}; 148 149/* 150 * Claim various Intel PCI device identifiers for this driver. The 151 * sub-vendor and sub-device field are extensively used to identify 152 * particular variants, but we don't currently differentiate between 153 * them. 154 */ 155static struct fxp_ident fxp_ident_table[] = { 156 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 157 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 158 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 160 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 170 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 171 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 172 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 173 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 175 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 176 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 177 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 178 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 179 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 180 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 181 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 182 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 183 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 184 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 185 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 186 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 187 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 188 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 189 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 190 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 191 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 192 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 193 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 194 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 195 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 196 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 197 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 198 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 199 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 200 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 201 { 0, -1, NULL }, 202}; 203 204#ifdef FXP_IP_CSUM_WAR 205#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 206#else 207#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 208#endif 209 210static int fxp_probe(device_t dev); 211static int fxp_attach(device_t dev); 212static int fxp_detach(device_t dev); 213static int fxp_shutdown(device_t dev); 214static int fxp_suspend(device_t dev); 215static int fxp_resume(device_t dev); 216 217static void fxp_intr(void *xsc); 218static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 219 struct mbuf *m, uint16_t status, int pos); 220static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 221 uint8_t statack, int count); 222static void fxp_init(void *xsc); 223static void fxp_init_body(struct fxp_softc *sc); 224static void fxp_tick(void *xsc); 225static void fxp_start(struct ifnet *ifp); 226static void fxp_start_body(struct ifnet *ifp); 227static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 228static void fxp_txeof(struct fxp_softc *sc); 229static void fxp_stop(struct fxp_softc *sc); 230static void fxp_release(struct fxp_softc *sc); 231static int fxp_ioctl(struct ifnet *ifp, u_long command, 232 caddr_t data); 233static void fxp_watchdog(struct fxp_softc *sc); 234static void fxp_add_rfabuf(struct fxp_softc *sc, 235 struct fxp_rx *rxp); 236static void fxp_discard_rfabuf(struct fxp_softc *sc, 237 struct fxp_rx *rxp); 238static int fxp_new_rfabuf(struct fxp_softc *sc, 239 struct fxp_rx *rxp); 240static int fxp_mc_addrs(struct fxp_softc *sc); 241static void fxp_mc_setup(struct fxp_softc *sc); 242static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 243 int autosize); 244static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 245 uint16_t data); 246static void fxp_autosize_eeprom(struct fxp_softc *sc); 247static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 248 int offset, int words); 249static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 250 int offset, int words); 251static int fxp_ifmedia_upd(struct ifnet *ifp); 252static void fxp_ifmedia_sts(struct ifnet *ifp, 253 struct ifmediareq *ifmr); 254static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 255static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 256 struct ifmediareq *ifmr); 257static int fxp_miibus_readreg(device_t dev, int phy, int reg); 258static void fxp_miibus_writereg(device_t dev, int phy, int reg, 259 int value); 260static void fxp_load_ucode(struct fxp_softc *sc); 261static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 262 int low, int high); 263static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 264static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 265static void fxp_scb_wait(struct fxp_softc *sc); 266static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 267static void fxp_dma_wait(struct fxp_softc *sc, 268 volatile uint16_t *status, bus_dma_tag_t dmat, 269 bus_dmamap_t map); 270 271static device_method_t fxp_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, fxp_probe), 274 DEVMETHOD(device_attach, fxp_attach), 275 DEVMETHOD(device_detach, fxp_detach), 276 DEVMETHOD(device_shutdown, fxp_shutdown), 277 DEVMETHOD(device_suspend, fxp_suspend), 278 DEVMETHOD(device_resume, fxp_resume), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 282 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 283 284 { 0, 0 } 285}; 286 287static driver_t fxp_driver = { 288 "fxp", 289 fxp_methods, 290 sizeof(struct fxp_softc), 291}; 292 293static devclass_t fxp_devclass; 294 295DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 296DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 297DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 298 299static struct resource_spec fxp_res_spec_mem[] = { 300 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 301 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 302 { -1, 0 } 303}; 304 305static struct resource_spec fxp_res_spec_io[] = { 306 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 307 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 308 { -1, 0 } 309}; 310 311/* 312 * Wait for the previous command to be accepted (but not necessarily 313 * completed). 314 */ 315static void 316fxp_scb_wait(struct fxp_softc *sc) 317{ 318 union { 319 uint16_t w; 320 uint8_t b[2]; 321 } flowctl; 322 int i = 10000; 323 324 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 325 DELAY(2); 326 if (i == 0) { 327 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 328 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 329 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 330 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 331 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 332 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 333 } 334} 335 336static void 337fxp_scb_cmd(struct fxp_softc *sc, int cmd) 338{ 339 340 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 341 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 342 fxp_scb_wait(sc); 343 } 344 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 345} 346 347static void 348fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 349 bus_dma_tag_t dmat, bus_dmamap_t map) 350{ 351 int i = 10000; 352 353 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 354 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 355 DELAY(2); 356 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 357 } 358 if (i == 0) 359 device_printf(sc->dev, "DMA timeout\n"); 360} 361 362/* 363 * Return identification string if this device is ours. 364 */ 365static int 366fxp_probe(device_t dev) 367{ 368 uint16_t devid; 369 uint8_t revid; 370 struct fxp_ident *ident; 371 372 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 373 devid = pci_get_device(dev); 374 revid = pci_get_revid(dev); 375 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 376 if (ident->devid == devid && 377 (ident->revid == revid || ident->revid == -1)) { 378 device_set_desc(dev, ident->name); 379 return (BUS_PROBE_DEFAULT); 380 } 381 } 382 } 383 return (ENXIO); 384} 385 386static void 387fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 388{ 389 uint32_t *addr; 390 391 if (error) 392 return; 393 394 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 395 addr = arg; 396 *addr = segs->ds_addr; 397} 398 399static int 400fxp_attach(device_t dev) 401{ 402 struct fxp_softc *sc; 403 struct fxp_cb_tx *tcbp; 404 struct fxp_tx *txp; 405 struct fxp_rx *rxp; 406 struct ifnet *ifp; 407 uint32_t val; 408 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 409 u_char eaddr[ETHER_ADDR_LEN]; 410 int i, pmc, prefer_iomap; 411 int error; 412 413 error = 0; 414 sc = device_get_softc(dev); 415 sc->dev = dev; 416 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 417 MTX_DEF); 418 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 419 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 420 fxp_serial_ifmedia_sts); 421 422 ifp = sc->ifp = if_alloc(IFT_ETHER); 423 if (ifp == NULL) { 424 device_printf(dev, "can not if_alloc()\n"); 425 error = ENOSPC; 426 goto fail; 427 } 428 429 /* 430 * Enable bus mastering. 431 */ 432 pci_enable_busmaster(dev); 433 val = pci_read_config(dev, PCIR_COMMAND, 2); 434 435 /* 436 * Figure out which we should try first - memory mapping or i/o mapping? 437 * We default to memory mapping. Then we accept an override from the 438 * command line. Then we check to see which one is enabled. 439 */ 440 prefer_iomap = 0; 441 resource_int_value(device_get_name(dev), device_get_unit(dev), 442 "prefer_iomap", &prefer_iomap); 443 if (prefer_iomap) 444 sc->fxp_spec = fxp_res_spec_io; 445 else 446 sc->fxp_spec = fxp_res_spec_mem; 447 448 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 449 if (error) { 450 if (sc->fxp_spec == fxp_res_spec_mem) 451 sc->fxp_spec = fxp_res_spec_io; 452 else 453 sc->fxp_spec = fxp_res_spec_mem; 454 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 455 } 456 if (error) { 457 device_printf(dev, "could not allocate resources\n"); 458 error = ENXIO; 459 goto fail; 460 } 461 462 if (bootverbose) { 463 device_printf(dev, "using %s space register mapping\n", 464 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 465 } 466 467 /* 468 * Reset to a stable state. 469 */ 470 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 471 DELAY(10); 472 473 /* 474 * Find out how large of an SEEPROM we have. 475 */ 476 fxp_autosize_eeprom(sc); 477 478 /* 479 * Find out the chip revision; lump all 82557 revs together. 480 */ 481 fxp_read_eeprom(sc, &data, 5, 1); 482 if ((data >> 8) == 1) 483 sc->revision = FXP_REV_82557; 484 else 485 sc->revision = pci_get_revid(dev); 486 487 /* 488 * Check availability of WOL. 82559ER does not support WOL. 489 */ 490 if (sc->revision >= FXP_REV_82558_A4 && 491 sc->revision != FXP_REV_82559S_A) { 492 fxp_read_eeprom(sc, &data, 10, 1); 493 if ((data & 0x20) != 0 && 494 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) 495 sc->flags |= FXP_FLAG_WOLCAP; 496 } 497 498 /* 499 * Determine whether we must use the 503 serial interface. 500 */ 501 fxp_read_eeprom(sc, &data, 6, 1); 502 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 503 && (data & FXP_PHY_SERIAL_ONLY)) 504 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 505 506 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 507 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 508 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 509 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 510 "FXP driver receive interrupt microcode bundling delay"); 511 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 517 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 518 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 519 "FXP RNR events"); 520 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 521 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 522 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 523 "FXP flow control disabled"); 524 525 /* 526 * Pull in device tunables. 527 */ 528 sc->tunable_int_delay = TUNABLE_INT_DELAY; 529 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 530 sc->tunable_noflow = 1; 531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "int_delay", &sc->tunable_int_delay); 533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "bundle_max", &sc->tunable_bundle_max); 535 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 536 "noflow", &sc->tunable_noflow); 537 sc->rnr = 0; 538 539 /* 540 * Enable workarounds for certain chip revision deficiencies. 541 * 542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 543 * some systems based a normal 82559 design, have a defect where 544 * the chip can cause a PCI protocol violation if it receives 545 * a CU_RESUME command when it is entering the IDLE state. The 546 * workaround is to disable Dynamic Standby Mode, so the chip never 547 * deasserts CLKRUN#, and always remains in an active state. 548 * 549 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 550 */ 551 i = pci_get_device(dev); 552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 553 sc->revision >= FXP_REV_82559_A0) { 554 fxp_read_eeprom(sc, &data, 10, 1); 555 if (data & 0x02) { /* STB enable */ 556 uint16_t cksum; 557 int i; 558 559 device_printf(dev, 560 "Disabling dynamic standby mode in EEPROM\n"); 561 data &= ~0x02; 562 fxp_write_eeprom(sc, &data, 10, 1); 563 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 564 cksum = 0; 565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 566 fxp_read_eeprom(sc, &data, i, 1); 567 cksum += data; 568 } 569 i = (1 << sc->eeprom_size) - 1; 570 cksum = 0xBABA - cksum; 571 fxp_read_eeprom(sc, &data, i, 1); 572 fxp_write_eeprom(sc, &cksum, i, 1); 573 device_printf(dev, 574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 575 i, data, cksum); 576#if 1 577 /* 578 * If the user elects to continue, try the software 579 * workaround, as it is better than nothing. 580 */ 581 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 582#endif 583 } 584 } 585 586 /* 587 * If we are not a 82557 chip, we can enable extended features. 588 */ 589 if (sc->revision != FXP_REV_82557) { 590 /* 591 * If MWI is enabled in the PCI configuration, and there 592 * is a valid cacheline size (8 or 16 dwords), then tell 593 * the board to turn on MWI. 594 */ 595 if (val & PCIM_CMD_MWRICEN && 596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 597 sc->flags |= FXP_FLAG_MWI_ENABLE; 598 599 /* turn on the extended TxCB feature */ 600 sc->flags |= FXP_FLAG_EXT_TXCB; 601 602 /* enable reception of long frames for VLAN */ 603 sc->flags |= FXP_FLAG_LONG_PKT_EN; 604 } else { 605 /* a hack to get long VLAN frames on a 82557 */ 606 sc->flags |= FXP_FLAG_SAVE_BAD; 607 } 608 609 /* For 82559 or later chips, Rx checksum offload is supported. */ 610 if (sc->revision >= FXP_REV_82559_A0) 611 sc->flags |= FXP_FLAG_82559_RXCSUM; 612 /* 613 * Enable use of extended RFDs and TCBs for 82550 614 * and later chips. Note: we need extended TXCB support 615 * too, but that's already enabled by the code above. 616 * Be careful to do this only on the right devices. 617 */ 618 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 619 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 620 || sc->revision == FXP_REV_82551_10) { 621 sc->rfa_size = sizeof (struct fxp_rfa); 622 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 623 sc->flags |= FXP_FLAG_EXT_RFA; 624 /* Use extended RFA instead of 82559 checksum mode. */ 625 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 626 } else { 627 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 628 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 629 } 630 631 /* 632 * Allocate DMA tags and DMA safe memory. 633 */ 634 sc->maxtxseg = FXP_NTXSEG; 635 sc->maxsegsize = MCLBYTES; 636 if (sc->flags & FXP_FLAG_EXT_RFA) { 637 sc->maxtxseg--; 638 sc->maxsegsize = FXP_TSO_SEGSIZE; 639 } 640 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 641 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 642 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 643 sc->maxtxseg, sc->maxsegsize, 0, 644 busdma_lock_mutex, &Giant, &sc->fxp_mtag); 645 if (error) { 646 device_printf(dev, "could not allocate dma tag\n"); 647 goto fail; 648 } 649 650 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 651 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 652 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 653 busdma_lock_mutex, &Giant, &sc->fxp_stag); 654 if (error) { 655 device_printf(dev, "could not allocate dma tag\n"); 656 goto fail; 657 } 658 659 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 660 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 661 if (error) 662 goto fail; 663 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 664 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 665 if (error) { 666 device_printf(dev, "could not map the stats buffer\n"); 667 goto fail; 668 } 669 670 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 671 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 672 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 673 busdma_lock_mutex, &Giant, &sc->cbl_tag); 674 if (error) { 675 device_printf(dev, "could not allocate dma tag\n"); 676 goto fail; 677 } 678 679 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 680 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 681 if (error) 682 goto fail; 683 684 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 685 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 686 &sc->fxp_desc.cbl_addr, 0); 687 if (error) { 688 device_printf(dev, "could not map DMA memory\n"); 689 goto fail; 690 } 691 692 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 693 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 694 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 695 busdma_lock_mutex, &Giant, &sc->mcs_tag); 696 if (error) { 697 device_printf(dev, "could not allocate dma tag\n"); 698 goto fail; 699 } 700 701 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 702 BUS_DMA_NOWAIT, &sc->mcs_map); 703 if (error) 704 goto fail; 705 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 706 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 707 if (error) { 708 device_printf(dev, "can't map the multicast setup command\n"); 709 goto fail; 710 } 711 712 /* 713 * Pre-allocate the TX DMA maps and setup the pointers to 714 * the TX command blocks. 715 */ 716 txp = sc->fxp_desc.tx_list; 717 tcbp = sc->fxp_desc.cbl_list; 718 for (i = 0; i < FXP_NTXCB; i++) { 719 txp[i].tx_cb = tcbp + i; 720 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 721 if (error) { 722 device_printf(dev, "can't create DMA map for TX\n"); 723 goto fail; 724 } 725 } 726 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 727 if (error) { 728 device_printf(dev, "can't create spare DMA map\n"); 729 goto fail; 730 } 731 732 /* 733 * Pre-allocate our receive buffers. 734 */ 735 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 736 for (i = 0; i < FXP_NRFABUFS; i++) { 737 rxp = &sc->fxp_desc.rx_list[i]; 738 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 739 if (error) { 740 device_printf(dev, "can't create DMA map for RX\n"); 741 goto fail; 742 } 743 if (fxp_new_rfabuf(sc, rxp) != 0) { 744 error = ENOMEM; 745 goto fail; 746 } 747 fxp_add_rfabuf(sc, rxp); 748 } 749 750 /* 751 * Read MAC address. 752 */ 753 fxp_read_eeprom(sc, myea, 0, 3); 754 eaddr[0] = myea[0] & 0xff; 755 eaddr[1] = myea[0] >> 8; 756 eaddr[2] = myea[1] & 0xff; 757 eaddr[3] = myea[1] >> 8; 758 eaddr[4] = myea[2] & 0xff; 759 eaddr[5] = myea[2] >> 8; 760 if (bootverbose) { 761 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 762 pci_get_vendor(dev), pci_get_device(dev), 763 pci_get_subvendor(dev), pci_get_subdevice(dev), 764 pci_get_revid(dev)); 765 fxp_read_eeprom(sc, &data, 10, 1); 766 device_printf(dev, "Dynamic Standby mode is %s\n", 767 data & 0x02 ? "enabled" : "disabled"); 768 } 769 770 /* 771 * If this is only a 10Mbps device, then there is no MII, and 772 * the PHY will use a serial interface instead. 773 * 774 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 775 * doesn't have a programming interface of any sort. The 776 * media is sensed automatically based on how the link partner 777 * is configured. This is, in essence, manual configuration. 778 */ 779 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 780 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 781 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 782 } else { 783 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 784 fxp_ifmedia_sts)) { 785 device_printf(dev, "MII without any PHY!\n"); 786 error = ENXIO; 787 goto fail; 788 } 789 } 790 791 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 792 ifp->if_init = fxp_init; 793 ifp->if_softc = sc; 794 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 795 ifp->if_ioctl = fxp_ioctl; 796 ifp->if_start = fxp_start; 797 798 ifp->if_capabilities = ifp->if_capenable = 0; 799 800 /* Enable checksum offload/TSO for 82550 or better chips */ 801 if (sc->flags & FXP_FLAG_EXT_RFA) { 802 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 803 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 804 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 805 } 806 807 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 808 ifp->if_capabilities |= IFCAP_RXCSUM; 809 ifp->if_capenable |= IFCAP_RXCSUM; 810 } 811 812 if (sc->flags & FXP_FLAG_WOLCAP) { 813 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 814 ifp->if_capenable |= IFCAP_WOL_MAGIC; 815 } 816 817#ifdef DEVICE_POLLING 818 /* Inform the world we support polling. */ 819 ifp->if_capabilities |= IFCAP_POLLING; 820#endif 821 822 /* 823 * Attach the interface. 824 */ 825 ether_ifattach(ifp, eaddr); 826 827 /* 828 * Tell the upper layer(s) we support long frames. 829 * Must appear after the call to ether_ifattach() because 830 * ether_ifattach() sets ifi_hdrlen to the default value. 831 */ 832 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 833 ifp->if_capabilities |= IFCAP_VLAN_MTU; 834 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 835 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 836 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 837 IFCAP_VLAN_HWCSUM; 838 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 839 IFCAP_VLAN_HWCSUM; 840 } 841 842 /* 843 * Let the system queue as many packets as we have available 844 * TX descriptors. 845 */ 846 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 847 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 848 IFQ_SET_READY(&ifp->if_snd); 849 850 /* 851 * Hook our interrupt after all initialization is complete. 852 */ 853 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 854 NULL, fxp_intr, sc, &sc->ih); 855 if (error) { 856 device_printf(dev, "could not setup irq\n"); 857 ether_ifdetach(sc->ifp); 858 goto fail; 859 } 860 861 /* 862 * Configure hardware to reject magic frames otherwise 863 * system will hang on recipt of magic frames. 864 */ 865 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 866 FXP_LOCK(sc); 867 /* Clear wakeup events. */ 868 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 869 fxp_init_body(sc); 870 fxp_stop(sc); 871 FXP_UNLOCK(sc); 872 } 873 874fail: 875 if (error) 876 fxp_release(sc); 877 return (error); 878} 879 880/* 881 * Release all resources. The softc lock should not be held and the 882 * interrupt should already be torn down. 883 */ 884static void 885fxp_release(struct fxp_softc *sc) 886{ 887 struct fxp_rx *rxp; 888 struct fxp_tx *txp; 889 int i; 890 891 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 892 KASSERT(sc->ih == NULL, 893 ("fxp_release() called with intr handle still active")); 894 if (sc->miibus) 895 device_delete_child(sc->dev, sc->miibus); 896 bus_generic_detach(sc->dev); 897 ifmedia_removeall(&sc->sc_media); 898 if (sc->fxp_desc.cbl_list) { 899 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 900 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 901 sc->cbl_map); 902 } 903 if (sc->fxp_stats) { 904 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 905 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 906 } 907 if (sc->mcsp) { 908 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 909 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 910 } 911 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 912 if (sc->fxp_mtag) { 913 for (i = 0; i < FXP_NRFABUFS; i++) { 914 rxp = &sc->fxp_desc.rx_list[i]; 915 if (rxp->rx_mbuf != NULL) { 916 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 917 BUS_DMASYNC_POSTREAD); 918 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 919 m_freem(rxp->rx_mbuf); 920 } 921 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 922 } 923 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 924 for (i = 0; i < FXP_NTXCB; i++) { 925 txp = &sc->fxp_desc.tx_list[i]; 926 if (txp->tx_mbuf != NULL) { 927 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 928 BUS_DMASYNC_POSTWRITE); 929 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 930 m_freem(txp->tx_mbuf); 931 } 932 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 933 } 934 bus_dma_tag_destroy(sc->fxp_mtag); 935 } 936 if (sc->fxp_stag) 937 bus_dma_tag_destroy(sc->fxp_stag); 938 if (sc->cbl_tag) 939 bus_dma_tag_destroy(sc->cbl_tag); 940 if (sc->mcs_tag) 941 bus_dma_tag_destroy(sc->mcs_tag); 942 if (sc->ifp) 943 if_free(sc->ifp); 944 945 mtx_destroy(&sc->sc_mtx); 946} 947 948/* 949 * Detach interface. 950 */ 951static int 952fxp_detach(device_t dev) 953{ 954 struct fxp_softc *sc = device_get_softc(dev); 955 956#ifdef DEVICE_POLLING 957 if (sc->ifp->if_capenable & IFCAP_POLLING) 958 ether_poll_deregister(sc->ifp); 959#endif 960 961 FXP_LOCK(sc); 962 sc->suspended = 1; /* Do same thing as we do for suspend */ 963 /* 964 * Stop DMA and drop transmit queue, but disable interrupts first. 965 */ 966 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 967 fxp_stop(sc); 968 FXP_UNLOCK(sc); 969 callout_drain(&sc->stat_ch); 970 971 /* 972 * Close down routes etc. 973 */ 974 ether_ifdetach(sc->ifp); 975 976 /* 977 * Unhook interrupt before dropping lock. This is to prevent 978 * races with fxp_intr(). 979 */ 980 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 981 sc->ih = NULL; 982 983 /* Release our allocated resources. */ 984 fxp_release(sc); 985 return (0); 986} 987 988/* 989 * Device shutdown routine. Called at system shutdown after sync. The 990 * main purpose of this routine is to shut off receiver DMA so that 991 * kernel memory doesn't get clobbered during warmboot. 992 */ 993static int 994fxp_shutdown(device_t dev) 995{ 996 997 /* 998 * Make sure that DMA is disabled prior to reboot. Not doing 999 * do could allow DMA to corrupt kernel memory during the 1000 * reboot before the driver initializes. 1001 */ 1002 return (fxp_suspend(dev)); 1003} 1004 1005/* 1006 * Device suspend routine. Stop the interface and save some PCI 1007 * settings in case the BIOS doesn't restore them properly on 1008 * resume. 1009 */ 1010static int 1011fxp_suspend(device_t dev) 1012{ 1013 struct fxp_softc *sc = device_get_softc(dev); 1014 struct ifnet *ifp; 1015 int pmc; 1016 uint16_t pmstat; 1017 1018 FXP_LOCK(sc); 1019 1020 ifp = sc->ifp; 1021 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1022 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1023 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1024 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1025 /* Request PME. */ 1026 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1027 sc->flags |= FXP_FLAG_WOL; 1028 /* Reconfigure hardware to accept magic frames. */ 1029 fxp_init_body(sc); 1030 } 1031 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1032 } 1033 fxp_stop(sc); 1034 1035 sc->suspended = 1; 1036 1037 FXP_UNLOCK(sc); 1038 return (0); 1039} 1040 1041/* 1042 * Device resume routine. re-enable busmastering, and restart the interface if 1043 * appropriate. 1044 */ 1045static int 1046fxp_resume(device_t dev) 1047{ 1048 struct fxp_softc *sc = device_get_softc(dev); 1049 struct ifnet *ifp = sc->ifp; 1050 int pmc; 1051 uint16_t pmstat; 1052 1053 FXP_LOCK(sc); 1054 1055 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1056 sc->flags &= ~FXP_FLAG_WOL; 1057 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1058 /* Disable PME and clear PME status. */ 1059 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1060 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1061 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1062 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1063 CSR_READ_1(sc, FXP_CSR_PMDR)); 1064 } 1065 1066 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1067 DELAY(10); 1068 1069 /* reinitialize interface if necessary */ 1070 if (ifp->if_flags & IFF_UP) 1071 fxp_init_body(sc); 1072 1073 sc->suspended = 0; 1074 1075 FXP_UNLOCK(sc); 1076 return (0); 1077} 1078 1079static void 1080fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1081{ 1082 uint16_t reg; 1083 int x; 1084 1085 /* 1086 * Shift in data. 1087 */ 1088 for (x = 1 << (length - 1); x; x >>= 1) { 1089 if (data & x) 1090 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1091 else 1092 reg = FXP_EEPROM_EECS; 1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1094 DELAY(1); 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1096 DELAY(1); 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1098 DELAY(1); 1099 } 1100} 1101 1102/* 1103 * Read from the serial EEPROM. Basically, you manually shift in 1104 * the read opcode (one bit at a time) and then shift in the address, 1105 * and then you shift out the data (all of this one bit at a time). 1106 * The word size is 16 bits, so you have to provide the address for 1107 * every 16 bits of data. 1108 */ 1109static uint16_t 1110fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1111{ 1112 uint16_t reg, data; 1113 int x; 1114 1115 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1116 /* 1117 * Shift in read opcode. 1118 */ 1119 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1120 /* 1121 * Shift in address. 1122 */ 1123 data = 0; 1124 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1125 if (offset & x) 1126 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1127 else 1128 reg = FXP_EEPROM_EECS; 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1130 DELAY(1); 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1132 DELAY(1); 1133 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1134 DELAY(1); 1135 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1136 data++; 1137 if (autosize && reg == 0) { 1138 sc->eeprom_size = data; 1139 break; 1140 } 1141 } 1142 /* 1143 * Shift out data. 1144 */ 1145 data = 0; 1146 reg = FXP_EEPROM_EECS; 1147 for (x = 1 << 15; x; x >>= 1) { 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1149 DELAY(1); 1150 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1151 data |= x; 1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1153 DELAY(1); 1154 } 1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1156 DELAY(1); 1157 1158 return (data); 1159} 1160 1161static void 1162fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1163{ 1164 int i; 1165 1166 /* 1167 * Erase/write enable. 1168 */ 1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1170 fxp_eeprom_shiftin(sc, 0x4, 3); 1171 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1172 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1173 DELAY(1); 1174 /* 1175 * Shift in write opcode, address, data. 1176 */ 1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1178 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1179 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1180 fxp_eeprom_shiftin(sc, data, 16); 1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1182 DELAY(1); 1183 /* 1184 * Wait for EEPROM to finish up. 1185 */ 1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1187 DELAY(1); 1188 for (i = 0; i < 1000; i++) { 1189 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1190 break; 1191 DELAY(50); 1192 } 1193 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1194 DELAY(1); 1195 /* 1196 * Erase/write disable. 1197 */ 1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1199 fxp_eeprom_shiftin(sc, 0x4, 3); 1200 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1202 DELAY(1); 1203} 1204 1205/* 1206 * From NetBSD: 1207 * 1208 * Figure out EEPROM size. 1209 * 1210 * 559's can have either 64-word or 256-word EEPROMs, the 558 1211 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1212 * talks about the existance of 16 to 256 word EEPROMs. 1213 * 1214 * The only known sizes are 64 and 256, where the 256 version is used 1215 * by CardBus cards to store CIS information. 1216 * 1217 * The address is shifted in msb-to-lsb, and after the last 1218 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1219 * after which follows the actual data. We try to detect this zero, by 1220 * probing the data-out bit in the EEPROM control register just after 1221 * having shifted in a bit. If the bit is zero, we assume we've 1222 * shifted enough address bits. The data-out should be tri-state, 1223 * before this, which should translate to a logical one. 1224 */ 1225static void 1226fxp_autosize_eeprom(struct fxp_softc *sc) 1227{ 1228 1229 /* guess maximum size of 256 words */ 1230 sc->eeprom_size = 8; 1231 1232 /* autosize */ 1233 (void) fxp_eeprom_getword(sc, 0, 1); 1234} 1235 1236static void 1237fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1238{ 1239 int i; 1240 1241 for (i = 0; i < words; i++) 1242 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1243} 1244 1245static void 1246fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1247{ 1248 int i; 1249 1250 for (i = 0; i < words; i++) 1251 fxp_eeprom_putword(sc, offset + i, data[i]); 1252} 1253 1254/* 1255 * Grab the softc lock and call the real fxp_start_body() routine 1256 */ 1257static void 1258fxp_start(struct ifnet *ifp) 1259{ 1260 struct fxp_softc *sc = ifp->if_softc; 1261 1262 FXP_LOCK(sc); 1263 fxp_start_body(ifp); 1264 FXP_UNLOCK(sc); 1265} 1266 1267/* 1268 * Start packet transmission on the interface. 1269 * This routine must be called with the softc lock held, and is an 1270 * internal entry point only. 1271 */ 1272static void 1273fxp_start_body(struct ifnet *ifp) 1274{ 1275 struct fxp_softc *sc = ifp->if_softc; 1276 struct mbuf *mb_head; 1277 int txqueued; 1278 1279 FXP_LOCK_ASSERT(sc, MA_OWNED); 1280 1281 /* 1282 * See if we need to suspend xmit until the multicast filter 1283 * has been reprogrammed (which can only be done at the head 1284 * of the command chain). 1285 */ 1286 if (sc->need_mcsetup) 1287 return; 1288 1289 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1290 fxp_txeof(sc); 1291 /* 1292 * We're finished if there is nothing more to add to the list or if 1293 * we're all filled up with buffers to transmit. 1294 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1295 * a NOP command when needed. 1296 */ 1297 txqueued = 0; 1298 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1299 sc->tx_queued < FXP_NTXCB - 1) { 1300 1301 /* 1302 * Grab a packet to transmit. 1303 */ 1304 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1305 if (mb_head == NULL) 1306 break; 1307 1308 if (fxp_encap(sc, &mb_head)) { 1309 if (mb_head == NULL) 1310 break; 1311 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1312 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1313 } 1314 txqueued++; 1315 /* 1316 * Pass packet to bpf if there is a listener. 1317 */ 1318 BPF_MTAP(ifp, mb_head); 1319 } 1320 1321 /* 1322 * We're finished. If we added to the list, issue a RESUME to get DMA 1323 * going again if suspended. 1324 */ 1325 if (txqueued > 0) { 1326 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1327 fxp_scb_wait(sc); 1328 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1329 /* 1330 * Set a 5 second timer just in case we don't hear 1331 * from the card again. 1332 */ 1333 sc->watchdog_timer = 5; 1334 } 1335} 1336 1337static int 1338fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1339{ 1340 struct ifnet *ifp; 1341 struct mbuf *m; 1342 struct fxp_tx *txp; 1343 struct fxp_cb_tx *cbp; 1344 struct tcphdr *tcp; 1345 bus_dma_segment_t segs[FXP_NTXSEG]; 1346 int error, i, nseg, tcp_payload; 1347 1348 FXP_LOCK_ASSERT(sc, MA_OWNED); 1349 ifp = sc->ifp; 1350 1351 tcp_payload = 0; 1352 tcp = NULL; 1353 /* 1354 * Get pointer to next available tx desc. 1355 */ 1356 txp = sc->fxp_desc.tx_last->tx_next; 1357 1358 /* 1359 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1360 * Ethernet Controller Family Open Source Software 1361 * Developer Manual says: 1362 * Using software parsing is only allowed with legal 1363 * TCP/IP or UDP/IP packets. 1364 * ... 1365 * For all other datagrams, hardware parsing must 1366 * be used. 1367 * Software parsing appears to truncate ICMP and 1368 * fragmented UDP packets that contain one to three 1369 * bytes in the second (and final) mbuf of the packet. 1370 */ 1371 if (sc->flags & FXP_FLAG_EXT_RFA) 1372 txp->tx_cb->ipcb_ip_activation_high = 1373 FXP_IPCB_HARDWAREPARSING_ENABLE; 1374 1375 m = *m_head; 1376 /* 1377 * Deal with TCP/IP checksum offload. Note that 1378 * in order for TCP checksum offload to work, 1379 * the pseudo header checksum must have already 1380 * been computed and stored in the checksum field 1381 * in the TCP header. The stack should have 1382 * already done this for us. 1383 */ 1384 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1385 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1386 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1387 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1388 1389#ifdef FXP_IP_CSUM_WAR 1390 /* 1391 * XXX The 82550 chip appears to have trouble 1392 * dealing with IP header checksums in very small 1393 * datagrams, namely fragments from 1 to 3 bytes 1394 * in size. For example, say you want to transmit 1395 * a UDP packet of 1473 bytes. The packet will be 1396 * fragmented over two IP datagrams, the latter 1397 * containing only one byte of data. The 82550 will 1398 * botch the header checksum on the 1-byte fragment. 1399 * As long as the datagram contains 4 or more bytes 1400 * of data, you're ok. 1401 * 1402 * The following code attempts to work around this 1403 * problem: if the datagram is less than 38 bytes 1404 * in size (14 bytes ether header, 20 bytes IP header, 1405 * plus 4 bytes of data), we punt and compute the IP 1406 * header checksum by hand. This workaround doesn't 1407 * work very well, however, since it can be fooled 1408 * by things like VLAN tags and IP options that make 1409 * the header sizes/offsets vary. 1410 */ 1411 1412 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1413 if (m->m_pkthdr.len < 38) { 1414 struct ip *ip; 1415 m->m_data += ETHER_HDR_LEN; 1416 ip = mtod(m, struct ip *); 1417 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1418 m->m_data -= ETHER_HDR_LEN; 1419 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1420 } else { 1421 txp->tx_cb->ipcb_ip_activation_high = 1422 FXP_IPCB_HARDWAREPARSING_ENABLE; 1423 txp->tx_cb->ipcb_ip_schedule |= 1424 FXP_IPCB_IP_CHECKSUM_ENABLE; 1425 } 1426 } 1427#endif 1428 } 1429 1430 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1431 /* 1432 * 82550/82551 requires ethernet/IP/TCP headers must be 1433 * contained in the first active transmit buffer. 1434 */ 1435 struct ether_header *eh; 1436 struct ip *ip; 1437 uint32_t ip_off, poff; 1438 1439 if (M_WRITABLE(*m_head) == 0) { 1440 /* Get a writable copy. */ 1441 m = m_dup(*m_head, M_DONTWAIT); 1442 m_freem(*m_head); 1443 if (m == NULL) { 1444 *m_head = NULL; 1445 return (ENOBUFS); 1446 } 1447 *m_head = m; 1448 } 1449 ip_off = sizeof(struct ether_header); 1450 m = m_pullup(*m_head, ip_off); 1451 if (m == NULL) { 1452 *m_head = NULL; 1453 return (ENOBUFS); 1454 } 1455 eh = mtod(m, struct ether_header *); 1456 /* Check the existence of VLAN tag. */ 1457 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1458 ip_off = sizeof(struct ether_vlan_header); 1459 m = m_pullup(m, ip_off); 1460 if (m == NULL) { 1461 *m_head = NULL; 1462 return (ENOBUFS); 1463 } 1464 } 1465 m = m_pullup(m, ip_off + sizeof(struct ip)); 1466 if (m == NULL) { 1467 *m_head = NULL; 1468 return (ENOBUFS); 1469 } 1470 ip = (struct ip *)(mtod(m, char *) + ip_off); 1471 poff = ip_off + (ip->ip_hl << 2); 1472 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1473 if (m == NULL) { 1474 *m_head = NULL; 1475 return (ENOBUFS); 1476 } 1477 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1478 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1479 if (m == NULL) { 1480 *m_head = NULL; 1481 return (ENOBUFS); 1482 } 1483 1484 /* 1485 * Since 82550/82551 doesn't modify IP length and pseudo 1486 * checksum in the first frame driver should compute it. 1487 */ 1488 ip->ip_sum = 0; 1489 ip->ip_len = htons(ifp->if_mtu); 1490 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1491 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1492 m->m_pkthdr.tso_segsz)); 1493 /* Compute total TCP payload. */ 1494 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1495 tcp_payload -= tcp->th_off << 2; 1496 *m_head = m; 1497 } 1498 1499 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, *m_head, 1500 segs, &nseg, 0); 1501 if (error == EFBIG) { 1502 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1503 if (m == NULL) { 1504 m_freem(*m_head); 1505 *m_head = NULL; 1506 return (ENOMEM); 1507 } 1508 *m_head = m; 1509 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1510 *m_head, segs, &nseg, 0); 1511 if (error != 0) { 1512 m_freem(*m_head); 1513 *m_head = NULL; 1514 return (ENOMEM); 1515 } 1516 } else if (error != 0) 1517 return (error); 1518 if (nseg == 0) { 1519 m_freem(*m_head); 1520 *m_head = NULL; 1521 return (EIO); 1522 } 1523 1524 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1525 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1526 1527 cbp = txp->tx_cb; 1528 for (i = 0; i < nseg; i++) { 1529 /* 1530 * If this is an 82550/82551, then we're using extended 1531 * TxCBs _and_ we're using checksum offload. This means 1532 * that the TxCB is really an IPCB. One major difference 1533 * between the two is that with plain extended TxCBs, 1534 * the bottom half of the TxCB contains two entries from 1535 * the TBD array, whereas IPCBs contain just one entry: 1536 * one entry (8 bytes) has been sacrificed for the TCP/IP 1537 * checksum offload control bits. So to make things work 1538 * right, we have to start filling in the TBD array 1539 * starting from a different place depending on whether 1540 * the chip is an 82550/82551 or not. 1541 */ 1542 if (sc->flags & FXP_FLAG_EXT_RFA) { 1543 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1544 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1545 } else { 1546 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1547 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1548 } 1549 } 1550 if (sc->flags & FXP_FLAG_EXT_RFA) { 1551 /* Configure dynamic TBD for 82550/82551. */ 1552 cbp->tbd_number = 0xFF; 1553 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1554 } else 1555 cbp->tbd_number = nseg; 1556 /* Configure TSO. */ 1557 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1558 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1559 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1560 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1561 FXP_IPCB_IP_CHECKSUM_ENABLE | 1562 FXP_IPCB_TCP_PACKET | 1563 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1564 } 1565 /* Configure VLAN hardware tag insertion. */ 1566 if ((m->m_flags & M_VLANTAG) != 0) { 1567 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1568 txp->tx_cb->ipcb_ip_activation_high |= 1569 FXP_IPCB_INSERTVLAN_ENABLE; 1570 } 1571 1572 txp->tx_mbuf = m; 1573 txp->tx_cb->cb_status = 0; 1574 txp->tx_cb->byte_count = 0; 1575 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1576 txp->tx_cb->cb_command = 1577 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1578 FXP_CB_COMMAND_S); 1579 else 1580 txp->tx_cb->cb_command = 1581 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1582 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1583 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1584 txp->tx_cb->tx_threshold = tx_threshold; 1585 1586 /* 1587 * Advance the end of list forward. 1588 */ 1589 1590#ifdef __alpha__ 1591 /* 1592 * On platforms which can't access memory in 16-bit 1593 * granularities, we must prevent the card from DMA'ing 1594 * up the status while we update the command field. 1595 * This could cause us to overwrite the completion status. 1596 * XXX This is probably bogus and we're _not_ looking 1597 * for atomicity here. 1598 */ 1599 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1600 htole16(FXP_CB_COMMAND_S)); 1601#else 1602 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1603#endif /*__alpha__*/ 1604 sc->fxp_desc.tx_last = txp; 1605 1606 /* 1607 * Advance the beginning of the list forward if there are 1608 * no other packets queued (when nothing is queued, tx_first 1609 * sits on the last TxCB that was sent out). 1610 */ 1611 if (sc->tx_queued == 0) 1612 sc->fxp_desc.tx_first = txp; 1613 1614 sc->tx_queued++; 1615 1616 return (0); 1617} 1618 1619#ifdef DEVICE_POLLING 1620static poll_handler_t fxp_poll; 1621 1622static void 1623fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1624{ 1625 struct fxp_softc *sc = ifp->if_softc; 1626 uint8_t statack; 1627 1628 FXP_LOCK(sc); 1629 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1630 FXP_UNLOCK(sc); 1631 return; 1632 } 1633 1634 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1635 FXP_SCB_STATACK_FR; 1636 if (cmd == POLL_AND_CHECK_STATUS) { 1637 uint8_t tmp; 1638 1639 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1640 if (tmp == 0xff || tmp == 0) { 1641 FXP_UNLOCK(sc); 1642 return; /* nothing to do */ 1643 } 1644 tmp &= ~statack; 1645 /* ack what we can */ 1646 if (tmp != 0) 1647 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1648 statack |= tmp; 1649 } 1650 fxp_intr_body(sc, ifp, statack, count); 1651 FXP_UNLOCK(sc); 1652} 1653#endif /* DEVICE_POLLING */ 1654 1655/* 1656 * Process interface interrupts. 1657 */ 1658static void 1659fxp_intr(void *xsc) 1660{ 1661 struct fxp_softc *sc = xsc; 1662 struct ifnet *ifp = sc->ifp; 1663 uint8_t statack; 1664 1665 FXP_LOCK(sc); 1666 if (sc->suspended) { 1667 FXP_UNLOCK(sc); 1668 return; 1669 } 1670 1671#ifdef DEVICE_POLLING 1672 if (ifp->if_capenable & IFCAP_POLLING) { 1673 FXP_UNLOCK(sc); 1674 return; 1675 } 1676#endif 1677 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1678 /* 1679 * It should not be possible to have all bits set; the 1680 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1681 * all bits are set, this may indicate that the card has 1682 * been physically ejected, so ignore it. 1683 */ 1684 if (statack == 0xff) { 1685 FXP_UNLOCK(sc); 1686 return; 1687 } 1688 1689 /* 1690 * First ACK all the interrupts in this pass. 1691 */ 1692 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1693 fxp_intr_body(sc, ifp, statack, -1); 1694 } 1695 FXP_UNLOCK(sc); 1696} 1697 1698static void 1699fxp_txeof(struct fxp_softc *sc) 1700{ 1701 struct ifnet *ifp; 1702 struct fxp_tx *txp; 1703 1704 ifp = sc->ifp; 1705 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1706 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1707 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1708 txp = txp->tx_next) { 1709 if (txp->tx_mbuf != NULL) { 1710 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1711 BUS_DMASYNC_POSTWRITE); 1712 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1713 m_freem(txp->tx_mbuf); 1714 txp->tx_mbuf = NULL; 1715 /* clear this to reset csum offload bits */ 1716 txp->tx_cb->tbd[0].tb_addr = 0; 1717 } 1718 sc->tx_queued--; 1719 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1720 } 1721 sc->fxp_desc.tx_first = txp; 1722 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1723 if (sc->tx_queued == 0) { 1724 sc->watchdog_timer = 0; 1725 if (sc->need_mcsetup) 1726 fxp_mc_setup(sc); 1727 } 1728} 1729 1730static void 1731fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1732 uint16_t status, int pos) 1733{ 1734 struct ether_header *eh; 1735 struct ip *ip; 1736 struct udphdr *uh; 1737 int32_t hlen, len, pktlen, temp32; 1738 uint16_t csum, *opts; 1739 1740 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1741 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1742 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1743 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1744 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1745 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1746 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1747 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1748 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1749 CSUM_PSEUDO_HDR; 1750 m->m_pkthdr.csum_data = 0xffff; 1751 } 1752 } 1753 return; 1754 } 1755 1756 pktlen = m->m_pkthdr.len; 1757 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1758 return; 1759 eh = mtod(m, struct ether_header *); 1760 if (eh->ether_type != htons(ETHERTYPE_IP)) 1761 return; 1762 ip = (struct ip *)(eh + 1); 1763 if (ip->ip_v != IPVERSION) 1764 return; 1765 1766 hlen = ip->ip_hl << 2; 1767 pktlen -= sizeof(struct ether_header); 1768 if (hlen < sizeof(struct ip)) 1769 return; 1770 if (ntohs(ip->ip_len) < hlen) 1771 return; 1772 if (ntohs(ip->ip_len) != pktlen) 1773 return; 1774 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1775 return; /* can't handle fragmented packet */ 1776 1777 switch (ip->ip_p) { 1778 case IPPROTO_TCP: 1779 if (pktlen < (hlen + sizeof(struct tcphdr))) 1780 return; 1781 break; 1782 case IPPROTO_UDP: 1783 if (pktlen < (hlen + sizeof(struct udphdr))) 1784 return; 1785 uh = (struct udphdr *)((caddr_t)ip + hlen); 1786 if (uh->uh_sum == 0) 1787 return; /* no checksum */ 1788 break; 1789 default: 1790 return; 1791 } 1792 /* Extract computed checksum. */ 1793 csum = be16dec(mtod(m, char *) + pos); 1794 /* checksum fixup for IP options */ 1795 len = hlen - sizeof(struct ip); 1796 if (len > 0) { 1797 opts = (uint16_t *)(ip + 1); 1798 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1799 temp32 = csum - *opts; 1800 temp32 = (temp32 >> 16) + (temp32 & 65535); 1801 csum = temp32 & 65535; 1802 } 1803 } 1804 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1805 m->m_pkthdr.csum_data = csum; 1806} 1807 1808static void 1809fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1810 int count) 1811{ 1812 struct mbuf *m; 1813 struct fxp_rx *rxp; 1814 struct fxp_rfa *rfa; 1815 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1816 uint16_t status; 1817 1818 FXP_LOCK_ASSERT(sc, MA_OWNED); 1819 if (rnr) 1820 sc->rnr++; 1821#ifdef DEVICE_POLLING 1822 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1823 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1824 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1825 rnr = 1; 1826 } 1827#endif 1828 1829 /* 1830 * Free any finished transmit mbuf chains. 1831 * 1832 * Handle the CNA event likt a CXTNO event. It used to 1833 * be that this event (control unit not ready) was not 1834 * encountered, but it is now with the SMPng modifications. 1835 * The exact sequence of events that occur when the interface 1836 * is brought up are different now, and if this event 1837 * goes unhandled, the configuration/rxfilter setup sequence 1838 * can stall for several seconds. The result is that no 1839 * packets go out onto the wire for about 5 to 10 seconds 1840 * after the interface is ifconfig'ed for the first time. 1841 */ 1842 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1843 fxp_txeof(sc); 1844 1845 /* 1846 * Try to start more packets transmitting. 1847 */ 1848 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1849 fxp_start_body(ifp); 1850 1851 /* 1852 * Just return if nothing happened on the receive side. 1853 */ 1854 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1855 return; 1856 1857 /* 1858 * Process receiver interrupts. If a no-resource (RNR) 1859 * condition exists, get whatever packets we can and 1860 * re-start the receiver. 1861 * 1862 * When using polling, we do not process the list to completion, 1863 * so when we get an RNR interrupt we must defer the restart 1864 * until we hit the last buffer with the C bit set. 1865 * If we run out of cycles and rfa_headm has the C bit set, 1866 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1867 * that the info will be used in the subsequent polling cycle. 1868 */ 1869 for (;;) { 1870 rxp = sc->fxp_desc.rx_head; 1871 m = rxp->rx_mbuf; 1872 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1873 RFA_ALIGNMENT_FUDGE); 1874 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1875 BUS_DMASYNC_POSTREAD); 1876 1877#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1878 if (count >= 0 && count-- == 0) { 1879 if (rnr) { 1880 /* Defer RNR processing until the next time. */ 1881 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1882 rnr = 0; 1883 } 1884 break; 1885 } 1886#endif /* DEVICE_POLLING */ 1887 1888 status = le16toh(rfa->rfa_status); 1889 if ((status & FXP_RFA_STATUS_C) == 0) 1890 break; 1891 1892 /* 1893 * Advance head forward. 1894 */ 1895 sc->fxp_desc.rx_head = rxp->rx_next; 1896 1897 /* 1898 * Add a new buffer to the receive chain. 1899 * If this fails, the old buffer is recycled 1900 * instead. 1901 */ 1902 if (fxp_new_rfabuf(sc, rxp) == 0) { 1903 int total_len; 1904 1905 /* 1906 * Fetch packet length (the top 2 bits of 1907 * actual_size are flags set by the controller 1908 * upon completion), and drop the packet in case 1909 * of bogus length or CRC errors. 1910 */ 1911 total_len = le16toh(rfa->actual_size) & 0x3fff; 1912 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1913 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1914 /* Adjust for appended checksum bytes. */ 1915 total_len -= 2; 1916 } 1917 if (total_len < sizeof(struct ether_header) || 1918 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1919 sc->rfa_size || status & FXP_RFA_STATUS_CRC) { 1920 m_freem(m); 1921 continue; 1922 } 1923 1924 m->m_pkthdr.len = m->m_len = total_len; 1925 m->m_pkthdr.rcvif = ifp; 1926 1927 /* Do IP checksum checking. */ 1928 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1929 fxp_rxcsum(sc, ifp, m, status, total_len); 1930 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1931 (status & FXP_RFA_STATUS_VLAN) != 0) { 1932 m->m_pkthdr.ether_vtag = 1933 ntohs(rfa->rfax_vlan_id); 1934 m->m_flags |= M_VLANTAG; 1935 } 1936 /* 1937 * Drop locks before calling if_input() since it 1938 * may re-enter fxp_start() in the netisr case. 1939 * This would result in a lock reversal. Better 1940 * performance might be obtained by chaining all 1941 * packets received, dropping the lock, and then 1942 * calling if_input() on each one. 1943 */ 1944 FXP_UNLOCK(sc); 1945 (*ifp->if_input)(ifp, m); 1946 FXP_LOCK(sc); 1947 } else { 1948 /* Reuse RFA and loaded DMA map. */ 1949 ifp->if_iqdrops++; 1950 fxp_discard_rfabuf(sc, rxp); 1951 } 1952 fxp_add_rfabuf(sc, rxp); 1953 } 1954 if (rnr) { 1955 fxp_scb_wait(sc); 1956 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1957 sc->fxp_desc.rx_head->rx_addr); 1958 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1959 } 1960} 1961 1962/* 1963 * Update packet in/out/collision statistics. The i82557 doesn't 1964 * allow you to access these counters without doing a fairly 1965 * expensive DMA to get _all_ of the statistics it maintains, so 1966 * we do this operation here only once per second. The statistics 1967 * counters in the kernel are updated from the previous dump-stats 1968 * DMA and then a new dump-stats DMA is started. The on-chip 1969 * counters are zeroed when the DMA completes. If we can't start 1970 * the DMA immediately, we don't wait - we just prepare to read 1971 * them again next time. 1972 */ 1973static void 1974fxp_tick(void *xsc) 1975{ 1976 struct fxp_softc *sc = xsc; 1977 struct ifnet *ifp = sc->ifp; 1978 struct fxp_stats *sp = sc->fxp_stats; 1979 1980 FXP_LOCK_ASSERT(sc, MA_OWNED); 1981 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1982 ifp->if_opackets += le32toh(sp->tx_good); 1983 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1984 if (sp->rx_good) { 1985 ifp->if_ipackets += le32toh(sp->rx_good); 1986 sc->rx_idle_secs = 0; 1987 } else { 1988 /* 1989 * Receiver's been idle for another second. 1990 */ 1991 sc->rx_idle_secs++; 1992 } 1993 ifp->if_ierrors += 1994 le32toh(sp->rx_crc_errors) + 1995 le32toh(sp->rx_alignment_errors) + 1996 le32toh(sp->rx_rnr_errors) + 1997 le32toh(sp->rx_overrun_errors); 1998 /* 1999 * If any transmit underruns occured, bump up the transmit 2000 * threshold by another 512 bytes (64 * 8). 2001 */ 2002 if (sp->tx_underruns) { 2003 ifp->if_oerrors += le32toh(sp->tx_underruns); 2004 if (tx_threshold < 192) 2005 tx_threshold += 64; 2006 } 2007 2008 /* 2009 * Release any xmit buffers that have completed DMA. This isn't 2010 * strictly necessary to do here, but it's advantagous for mbufs 2011 * with external storage to be released in a timely manner rather 2012 * than being defered for a potentially long time. This limits 2013 * the delay to a maximum of one second. 2014 */ 2015 fxp_txeof(sc); 2016 2017 /* 2018 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2019 * then assume the receiver has locked up and attempt to clear 2020 * the condition by reprogramming the multicast filter. This is 2021 * a work-around for a bug in the 82557 where the receiver locks 2022 * up if it gets certain types of garbage in the syncronization 2023 * bits prior to the packet header. This bug is supposed to only 2024 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2025 * mode as well (perhaps due to a 10/100 speed transition). 2026 */ 2027 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2028 sc->rx_idle_secs = 0; 2029 fxp_mc_setup(sc); 2030 } 2031 /* 2032 * If there is no pending command, start another stats 2033 * dump. Otherwise punt for now. 2034 */ 2035 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2036 /* 2037 * Start another stats dump. 2038 */ 2039 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2040 BUS_DMASYNC_PREREAD); 2041 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2042 } else { 2043 /* 2044 * A previous command is still waiting to be accepted. 2045 * Just zero our copy of the stats and wait for the 2046 * next timer event to update them. 2047 */ 2048 sp->tx_good = 0; 2049 sp->tx_underruns = 0; 2050 sp->tx_total_collisions = 0; 2051 2052 sp->rx_good = 0; 2053 sp->rx_crc_errors = 0; 2054 sp->rx_alignment_errors = 0; 2055 sp->rx_rnr_errors = 0; 2056 sp->rx_overrun_errors = 0; 2057 } 2058 if (sc->miibus != NULL) 2059 mii_tick(device_get_softc(sc->miibus)); 2060 2061 /* 2062 * Check that chip hasn't hung. 2063 */ 2064 fxp_watchdog(sc); 2065 2066 /* 2067 * Schedule another timeout one second from now. 2068 */ 2069 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2070} 2071 2072/* 2073 * Stop the interface. Cancels the statistics updater and resets 2074 * the interface. 2075 */ 2076static void 2077fxp_stop(struct fxp_softc *sc) 2078{ 2079 struct ifnet *ifp = sc->ifp; 2080 struct fxp_tx *txp; 2081 int i; 2082 2083 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2084 sc->watchdog_timer = 0; 2085 2086 /* 2087 * Cancel stats updater. 2088 */ 2089 callout_stop(&sc->stat_ch); 2090 2091 /* 2092 * Preserve PCI configuration, configure, IA/multicast 2093 * setup and put RU and CU into idle state. 2094 */ 2095 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2096 DELAY(50); 2097 /* Disable interrupts. */ 2098 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2099 2100 /* 2101 * Release any xmit buffers. 2102 */ 2103 txp = sc->fxp_desc.tx_list; 2104 if (txp != NULL) { 2105 for (i = 0; i < FXP_NTXCB; i++) { 2106 if (txp[i].tx_mbuf != NULL) { 2107 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 2108 BUS_DMASYNC_POSTWRITE); 2109 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 2110 m_freem(txp[i].tx_mbuf); 2111 txp[i].tx_mbuf = NULL; 2112 /* clear this to reset csum offload bits */ 2113 txp[i].tx_cb->tbd[0].tb_addr = 0; 2114 } 2115 } 2116 } 2117 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2118 sc->tx_queued = 0; 2119} 2120 2121/* 2122 * Watchdog/transmission transmit timeout handler. Called when a 2123 * transmission is started on the interface, but no interrupt is 2124 * received before the timeout. This usually indicates that the 2125 * card has wedged for some reason. 2126 */ 2127static void 2128fxp_watchdog(struct fxp_softc *sc) 2129{ 2130 2131 FXP_LOCK_ASSERT(sc, MA_OWNED); 2132 2133 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2134 return; 2135 2136 device_printf(sc->dev, "device timeout\n"); 2137 sc->ifp->if_oerrors++; 2138 2139 fxp_init_body(sc); 2140} 2141 2142/* 2143 * Acquire locks and then call the real initialization function. This 2144 * is necessary because ether_ioctl() calls if_init() and this would 2145 * result in mutex recursion if the mutex was held. 2146 */ 2147static void 2148fxp_init(void *xsc) 2149{ 2150 struct fxp_softc *sc = xsc; 2151 2152 FXP_LOCK(sc); 2153 fxp_init_body(sc); 2154 FXP_UNLOCK(sc); 2155} 2156 2157/* 2158 * Perform device initialization. This routine must be called with the 2159 * softc lock held. 2160 */ 2161static void 2162fxp_init_body(struct fxp_softc *sc) 2163{ 2164 struct ifnet *ifp = sc->ifp; 2165 struct fxp_cb_config *cbp; 2166 struct fxp_cb_ias *cb_ias; 2167 struct fxp_cb_tx *tcbp; 2168 struct fxp_tx *txp; 2169 struct fxp_cb_mcs *mcsp; 2170 int i, prm; 2171 2172 FXP_LOCK_ASSERT(sc, MA_OWNED); 2173 /* 2174 * Cancel any pending I/O 2175 */ 2176 fxp_stop(sc); 2177 2178 /* 2179 * Issue software reset, which also unloads the microcode. 2180 */ 2181 sc->flags &= ~FXP_FLAG_UCODE; 2182 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2183 DELAY(50); 2184 2185 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2186 2187 /* 2188 * Initialize base of CBL and RFA memory. Loading with zero 2189 * sets it up for regular linear addressing. 2190 */ 2191 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2192 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2193 2194 fxp_scb_wait(sc); 2195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2196 2197 /* 2198 * Initialize base of dump-stats buffer. 2199 */ 2200 fxp_scb_wait(sc); 2201 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2202 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2203 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2204 2205 /* 2206 * Attempt to load microcode if requested. 2207 */ 2208 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2209 fxp_load_ucode(sc); 2210 2211 /* 2212 * Initialize the multicast address list. 2213 */ 2214 if (fxp_mc_addrs(sc)) { 2215 mcsp = sc->mcsp; 2216 mcsp->cb_status = 0; 2217 mcsp->cb_command = 2218 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2219 mcsp->link_addr = 0xffffffff; 2220 /* 2221 * Start the multicast setup command. 2222 */ 2223 fxp_scb_wait(sc); 2224 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2225 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2226 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2227 /* ...and wait for it to complete. */ 2228 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2229 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2230 BUS_DMASYNC_POSTWRITE); 2231 } 2232 2233 /* 2234 * We temporarily use memory that contains the TxCB list to 2235 * construct the config CB. The TxCB list memory is rebuilt 2236 * later. 2237 */ 2238 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2239 2240 /* 2241 * This bcopy is kind of disgusting, but there are a bunch of must be 2242 * zero and must be one bits in this structure and this is the easiest 2243 * way to initialize them all to proper values. 2244 */ 2245 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2246 2247 cbp->cb_status = 0; 2248 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2249 FXP_CB_COMMAND_EL); 2250 cbp->link_addr = 0xffffffff; /* (no) next command */ 2251 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2252 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2253 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2254 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2255 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2256 cbp->type_enable = 0; /* actually reserved */ 2257 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2258 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2259 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2260 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2261 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2262 cbp->late_scb = 0; /* (don't) defer SCB update */ 2263 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2264 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2265 cbp->ci_int = 1; /* interrupt on CU idle */ 2266 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2267 cbp->ext_stats_dis = 1; /* disable extended counters */ 2268 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2269 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2270 cbp->disc_short_rx = !prm; /* discard short packets */ 2271 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2272 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2273 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2274 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2275 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2276 cbp->csma_dis = 0; /* (don't) disable link */ 2277 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2278 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2279 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2280 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2281 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2282 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2283 cbp->nsai = 1; /* (don't) disable source addr insert */ 2284 cbp->preamble_length = 2; /* (7 byte) preamble */ 2285 cbp->loopback = 0; /* (don't) loopback */ 2286 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2287 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2288 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2289 cbp->promiscuous = prm; /* promiscuous mode */ 2290 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2291 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2292 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2293 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2294 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2295 2296 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2297 cbp->padding = 1; /* (do) pad short tx packets */ 2298 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2299 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2300 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2301 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2302 cbp->force_fdx = 0; /* (don't) force full duplex */ 2303 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2304 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2305 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2306 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2307 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2308 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2309 2310 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2311 /* 2312 * The 82557 has no hardware flow control, the values 2313 * below are the defaults for the chip. 2314 */ 2315 cbp->fc_delay_lsb = 0; 2316 cbp->fc_delay_msb = 0x40; 2317 cbp->pri_fc_thresh = 3; 2318 cbp->tx_fc_dis = 0; 2319 cbp->rx_fc_restop = 0; 2320 cbp->rx_fc_restart = 0; 2321 cbp->fc_filter = 0; 2322 cbp->pri_fc_loc = 1; 2323 } else { 2324 cbp->fc_delay_lsb = 0x1f; 2325 cbp->fc_delay_msb = 0x01; 2326 cbp->pri_fc_thresh = 3; 2327 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2328 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2329 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2330 cbp->fc_filter = !prm; /* drop FC frames to host */ 2331 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2332 } 2333 2334 /* 2335 * Start the config command/DMA. 2336 */ 2337 fxp_scb_wait(sc); 2338 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2339 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2340 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2341 /* ...and wait for it to complete. */ 2342 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2343 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2344 2345 /* 2346 * Now initialize the station address. Temporarily use the TxCB 2347 * memory area like we did above for the config CB. 2348 */ 2349 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2350 cb_ias->cb_status = 0; 2351 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2352 cb_ias->link_addr = 0xffffffff; 2353 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2354 2355 /* 2356 * Start the IAS (Individual Address Setup) command/DMA. 2357 */ 2358 fxp_scb_wait(sc); 2359 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2360 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2361 /* ...and wait for it to complete. */ 2362 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2363 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2364 2365 /* 2366 * Initialize transmit control block (TxCB) list. 2367 */ 2368 txp = sc->fxp_desc.tx_list; 2369 tcbp = sc->fxp_desc.cbl_list; 2370 bzero(tcbp, FXP_TXCB_SZ); 2371 for (i = 0; i < FXP_NTXCB; i++) { 2372 txp[i].tx_mbuf = NULL; 2373 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2374 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2375 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2376 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2377 if (sc->flags & FXP_FLAG_EXT_TXCB) 2378 tcbp[i].tbd_array_addr = 2379 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2380 else 2381 tcbp[i].tbd_array_addr = 2382 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2383 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2384 } 2385 /* 2386 * Set the suspend flag on the first TxCB and start the control 2387 * unit. It will execute the NOP and then suspend. 2388 */ 2389 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2390 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2391 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2392 sc->tx_queued = 1; 2393 2394 fxp_scb_wait(sc); 2395 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2396 2397 /* 2398 * Initialize receiver buffer area - RFA. 2399 */ 2400 fxp_scb_wait(sc); 2401 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2402 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2403 2404 /* 2405 * Set current media. 2406 */ 2407 if (sc->miibus != NULL) 2408 mii_mediachg(device_get_softc(sc->miibus)); 2409 2410 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2411 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2412 2413 /* 2414 * Enable interrupts. 2415 */ 2416#ifdef DEVICE_POLLING 2417 /* 2418 * ... but only do that if we are not polling. And because (presumably) 2419 * the default is interrupts on, we need to disable them explicitly! 2420 */ 2421 if (ifp->if_capenable & IFCAP_POLLING ) 2422 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2423 else 2424#endif /* DEVICE_POLLING */ 2425 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2426 2427 /* 2428 * Start stats updater. 2429 */ 2430 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2431} 2432 2433static int 2434fxp_serial_ifmedia_upd(struct ifnet *ifp) 2435{ 2436 2437 return (0); 2438} 2439 2440static void 2441fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2442{ 2443 2444 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2445} 2446 2447/* 2448 * Change media according to request. 2449 */ 2450static int 2451fxp_ifmedia_upd(struct ifnet *ifp) 2452{ 2453 struct fxp_softc *sc = ifp->if_softc; 2454 struct mii_data *mii; 2455 2456 mii = device_get_softc(sc->miibus); 2457 FXP_LOCK(sc); 2458 if (mii->mii_instance) { 2459 struct mii_softc *miisc; 2460 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2461 mii_phy_reset(miisc); 2462 } 2463 mii_mediachg(mii); 2464 FXP_UNLOCK(sc); 2465 return (0); 2466} 2467 2468/* 2469 * Notify the world which media we're using. 2470 */ 2471static void 2472fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2473{ 2474 struct fxp_softc *sc = ifp->if_softc; 2475 struct mii_data *mii; 2476 2477 mii = device_get_softc(sc->miibus); 2478 FXP_LOCK(sc); 2479 mii_pollstat(mii); 2480 ifmr->ifm_active = mii->mii_media_active; 2481 ifmr->ifm_status = mii->mii_media_status; 2482 2483 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2484 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2485 sc->cu_resume_bug = 1; 2486 else 2487 sc->cu_resume_bug = 0; 2488 FXP_UNLOCK(sc); 2489} 2490 2491/* 2492 * Add a buffer to the end of the RFA buffer list. 2493 * Return 0 if successful, 1 for failure. A failure results in 2494 * reusing the RFA buffer. 2495 * The RFA struct is stuck at the beginning of mbuf cluster and the 2496 * data pointer is fixed up to point just past it. 2497 */ 2498static int 2499fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2500{ 2501 struct mbuf *m; 2502 struct fxp_rfa *rfa; 2503 bus_dmamap_t tmp_map; 2504 int error; 2505 2506 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2507 if (m == NULL) 2508 return (ENOBUFS); 2509 2510 /* 2511 * Move the data pointer up so that the incoming data packet 2512 * will be 32-bit aligned. 2513 */ 2514 m->m_data += RFA_ALIGNMENT_FUDGE; 2515 2516 /* 2517 * Get a pointer to the base of the mbuf cluster and move 2518 * data start past it. 2519 */ 2520 rfa = mtod(m, struct fxp_rfa *); 2521 m->m_data += sc->rfa_size; 2522 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2523 2524 rfa->rfa_status = 0; 2525 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2526 rfa->actual_size = 0; 2527 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2528 sc->rfa_size; 2529 2530 /* 2531 * Initialize the rest of the RFA. Note that since the RFA 2532 * is misaligned, we cannot store values directly. We're thus 2533 * using the le32enc() function which handles endianness and 2534 * is also alignment-safe. 2535 */ 2536 le32enc(&rfa->link_addr, 0xffffffff); 2537 le32enc(&rfa->rbd_addr, 0xffffffff); 2538 2539 /* Map the RFA into DMA memory. */ 2540 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2541 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2542 &rxp->rx_addr, 0); 2543 if (error) { 2544 m_freem(m); 2545 return (error); 2546 } 2547 2548 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2549 tmp_map = sc->spare_map; 2550 sc->spare_map = rxp->rx_map; 2551 rxp->rx_map = tmp_map; 2552 rxp->rx_mbuf = m; 2553 2554 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2556 return (0); 2557} 2558 2559static void 2560fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2561{ 2562 struct fxp_rfa *p_rfa; 2563 struct fxp_rx *p_rx; 2564 2565 /* 2566 * If there are other buffers already on the list, attach this 2567 * one to the end by fixing up the tail to point to this one. 2568 */ 2569 if (sc->fxp_desc.rx_head != NULL) { 2570 p_rx = sc->fxp_desc.rx_tail; 2571 p_rfa = (struct fxp_rfa *) 2572 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2573 p_rx->rx_next = rxp; 2574 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2575 p_rfa->rfa_control = 0; 2576 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2577 BUS_DMASYNC_PREWRITE); 2578 } else { 2579 rxp->rx_next = NULL; 2580 sc->fxp_desc.rx_head = rxp; 2581 } 2582 sc->fxp_desc.rx_tail = rxp; 2583} 2584 2585static void 2586fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2587{ 2588 struct mbuf *m; 2589 struct fxp_rfa *rfa; 2590 2591 m = rxp->rx_mbuf; 2592 m->m_data = m->m_ext.ext_buf; 2593 /* 2594 * Move the data pointer up so that the incoming data packet 2595 * will be 32-bit aligned. 2596 */ 2597 m->m_data += RFA_ALIGNMENT_FUDGE; 2598 2599 /* 2600 * Get a pointer to the base of the mbuf cluster and move 2601 * data start past it. 2602 */ 2603 rfa = mtod(m, struct fxp_rfa *); 2604 m->m_data += sc->rfa_size; 2605 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2606 2607 rfa->rfa_status = 0; 2608 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2609 rfa->actual_size = 0; 2610 2611 /* 2612 * Initialize the rest of the RFA. Note that since the RFA 2613 * is misaligned, we cannot store values directly. We're thus 2614 * using the le32enc() function which handles endianness and 2615 * is also alignment-safe. 2616 */ 2617 le32enc(&rfa->link_addr, 0xffffffff); 2618 le32enc(&rfa->rbd_addr, 0xffffffff); 2619 2620 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2621 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2622} 2623 2624static int 2625fxp_miibus_readreg(device_t dev, int phy, int reg) 2626{ 2627 struct fxp_softc *sc = device_get_softc(dev); 2628 int count = 10000; 2629 int value; 2630 2631 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2632 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2633 2634 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2635 && count--) 2636 DELAY(10); 2637 2638 if (count <= 0) 2639 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2640 2641 return (value & 0xffff); 2642} 2643 2644static void 2645fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2646{ 2647 struct fxp_softc *sc = device_get_softc(dev); 2648 int count = 10000; 2649 2650 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2651 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2652 (value & 0xffff)); 2653 2654 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2655 count--) 2656 DELAY(10); 2657 2658 if (count <= 0) 2659 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2660} 2661 2662static int 2663fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2664{ 2665 struct fxp_softc *sc = ifp->if_softc; 2666 struct ifreq *ifr = (struct ifreq *)data; 2667 struct mii_data *mii; 2668 int flag, mask, error = 0, reinit; 2669 2670 switch (command) { 2671 case SIOCSIFFLAGS: 2672 FXP_LOCK(sc); 2673 if (ifp->if_flags & IFF_ALLMULTI) 2674 sc->flags |= FXP_FLAG_ALL_MCAST; 2675 else 2676 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2677 2678 /* 2679 * If interface is marked up and not running, then start it. 2680 * If it is marked down and running, stop it. 2681 * XXX If it's up then re-initialize it. This is so flags 2682 * such as IFF_PROMISC are handled. 2683 */ 2684 if (ifp->if_flags & IFF_UP) { 2685 fxp_init_body(sc); 2686 } else { 2687 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2688 fxp_stop(sc); 2689 } 2690 FXP_UNLOCK(sc); 2691 break; 2692 2693 case SIOCADDMULTI: 2694 case SIOCDELMULTI: 2695 FXP_LOCK(sc); 2696 if (ifp->if_flags & IFF_ALLMULTI) 2697 sc->flags |= FXP_FLAG_ALL_MCAST; 2698 else 2699 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2700 /* 2701 * Multicast list has changed; set the hardware filter 2702 * accordingly. 2703 */ 2704 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2705 fxp_mc_setup(sc); 2706 /* 2707 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2708 * again rather than else {}. 2709 */ 2710 if (sc->flags & FXP_FLAG_ALL_MCAST) 2711 fxp_init_body(sc); 2712 FXP_UNLOCK(sc); 2713 error = 0; 2714 break; 2715 2716 case SIOCSIFMEDIA: 2717 case SIOCGIFMEDIA: 2718 if (sc->miibus != NULL) { 2719 mii = device_get_softc(sc->miibus); 2720 error = ifmedia_ioctl(ifp, ifr, 2721 &mii->mii_media, command); 2722 } else { 2723 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2724 } 2725 break; 2726 2727 case SIOCSIFCAP: 2728 reinit = 0; 2729 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2730#ifdef DEVICE_POLLING 2731 if (mask & IFCAP_POLLING) { 2732 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2733 error = ether_poll_register(fxp_poll, ifp); 2734 if (error) 2735 return(error); 2736 FXP_LOCK(sc); 2737 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2738 FXP_SCB_INTR_DISABLE); 2739 ifp->if_capenable |= IFCAP_POLLING; 2740 FXP_UNLOCK(sc); 2741 } else { 2742 error = ether_poll_deregister(ifp); 2743 /* Enable interrupts in any case */ 2744 FXP_LOCK(sc); 2745 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2746 ifp->if_capenable &= ~IFCAP_POLLING; 2747 FXP_UNLOCK(sc); 2748 } 2749 } 2750#endif 2751 FXP_LOCK(sc); 2752 if ((mask & IFCAP_TXCSUM) != 0 && 2753 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2754 ifp->if_capenable ^= IFCAP_TXCSUM; 2755 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2756 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2757 else 2758 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2759 } 2760 if ((mask & IFCAP_RXCSUM) != 0 && 2761 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2762 ifp->if_capenable ^= IFCAP_RXCSUM; 2763 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2764 reinit++; 2765 } 2766 if ((mask & IFCAP_TSO4) != 0 && 2767 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2768 ifp->if_capenable ^= IFCAP_TSO4; 2769 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2770 ifp->if_hwassist |= CSUM_TSO; 2771 else 2772 ifp->if_hwassist &= ~CSUM_TSO; 2773 } 2774 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2775 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2776 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2777 if ((mask & IFCAP_VLAN_MTU) != 0 && 2778 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2779 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2780 if (sc->revision != FXP_REV_82557) 2781 flag = FXP_FLAG_LONG_PKT_EN; 2782 else /* a hack to get long frames on the old chip */ 2783 flag = FXP_FLAG_SAVE_BAD; 2784 sc->flags ^= flag; 2785 if (ifp->if_flags & IFF_UP) 2786 reinit++; 2787 } 2788 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2789 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2790 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2791 reinit++; 2792 } 2793 if (reinit > 0 && ifp->if_flags & IFF_UP) 2794 fxp_init_body(sc); 2795 FXP_UNLOCK(sc); 2796 VLAN_CAPABILITIES(ifp); 2797 break; 2798 2799 default: 2800 error = ether_ioctl(ifp, command, data); 2801 } 2802 return (error); 2803} 2804 2805/* 2806 * Fill in the multicast address list and return number of entries. 2807 */ 2808static int 2809fxp_mc_addrs(struct fxp_softc *sc) 2810{ 2811 struct fxp_cb_mcs *mcsp = sc->mcsp; 2812 struct ifnet *ifp = sc->ifp; 2813 struct ifmultiaddr *ifma; 2814 int nmcasts; 2815 2816 nmcasts = 0; 2817 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2818 IF_ADDR_LOCK(ifp); 2819 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2820 if (ifma->ifma_addr->sa_family != AF_LINK) 2821 continue; 2822 if (nmcasts >= MAXMCADDR) { 2823 sc->flags |= FXP_FLAG_ALL_MCAST; 2824 nmcasts = 0; 2825 break; 2826 } 2827 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2828 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2829 nmcasts++; 2830 } 2831 IF_ADDR_UNLOCK(ifp); 2832 } 2833 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2834 return (nmcasts); 2835} 2836 2837/* 2838 * Program the multicast filter. 2839 * 2840 * We have an artificial restriction that the multicast setup command 2841 * must be the first command in the chain, so we take steps to ensure 2842 * this. By requiring this, it allows us to keep up the performance of 2843 * the pre-initialized command ring (esp. link pointers) by not actually 2844 * inserting the mcsetup command in the ring - i.e. its link pointer 2845 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2846 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2847 * lead into the regular TxCB ring when it completes. 2848 * 2849 * This function must be called at splimp. 2850 */ 2851static void 2852fxp_mc_setup(struct fxp_softc *sc) 2853{ 2854 struct fxp_cb_mcs *mcsp = sc->mcsp; 2855 struct fxp_tx *txp; 2856 int count; 2857 2858 FXP_LOCK_ASSERT(sc, MA_OWNED); 2859 /* 2860 * If there are queued commands, we must wait until they are all 2861 * completed. If we are already waiting, then add a NOP command 2862 * with interrupt option so that we're notified when all commands 2863 * have been completed - fxp_start() ensures that no additional 2864 * TX commands will be added when need_mcsetup is true. 2865 */ 2866 if (sc->tx_queued) { 2867 /* 2868 * need_mcsetup will be true if we are already waiting for the 2869 * NOP command to be completed (see below). In this case, bail. 2870 */ 2871 if (sc->need_mcsetup) 2872 return; 2873 sc->need_mcsetup = 1; 2874 2875 /* 2876 * Add a NOP command with interrupt so that we are notified 2877 * when all TX commands have been processed. 2878 */ 2879 txp = sc->fxp_desc.tx_last->tx_next; 2880 txp->tx_mbuf = NULL; 2881 txp->tx_cb->cb_status = 0; 2882 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2883 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2884 /* 2885 * Advance the end of list forward. 2886 */ 2887 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2888 htole16(~FXP_CB_COMMAND_S); 2889 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2890 sc->fxp_desc.tx_last = txp; 2891 sc->tx_queued++; 2892 /* 2893 * Issue a resume in case the CU has just suspended. 2894 */ 2895 fxp_scb_wait(sc); 2896 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2897 /* 2898 * Set a 5 second timer just in case we don't hear from the 2899 * card again. 2900 */ 2901 sc->watchdog_timer = 5; 2902 2903 return; 2904 } 2905 sc->need_mcsetup = 0; 2906 2907 /* 2908 * Initialize multicast setup descriptor. 2909 */ 2910 mcsp->cb_status = 0; 2911 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2912 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2913 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2914 txp = &sc->fxp_desc.mcs_tx; 2915 txp->tx_mbuf = NULL; 2916 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2917 txp->tx_next = sc->fxp_desc.tx_list; 2918 (void) fxp_mc_addrs(sc); 2919 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2920 sc->tx_queued = 1; 2921 2922 /* 2923 * Wait until command unit is not active. This should never 2924 * be the case when nothing is queued, but make sure anyway. 2925 */ 2926 count = 100; 2927 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2928 FXP_SCB_CUS_ACTIVE && --count) 2929 DELAY(10); 2930 if (count == 0) { 2931 device_printf(sc->dev, "command queue timeout\n"); 2932 return; 2933 } 2934 2935 /* 2936 * Start the multicast setup command. 2937 */ 2938 fxp_scb_wait(sc); 2939 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2940 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2941 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2942 2943 sc->watchdog_timer = 2; 2944 return; 2945} 2946 2947static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2948static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2949static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2950static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2951static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2952static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2953static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2954 2955#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2956 2957struct ucode { 2958 uint32_t revision; 2959 uint32_t *ucode; 2960 int length; 2961 u_short int_delay_offset; 2962 u_short bundle_max_offset; 2963} ucode_table[] = { 2964 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2965 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2966 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2967 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2968 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2969 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2970 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2971 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2972 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2973 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2974 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2975 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2976 { 0, NULL, 0, 0, 0 } 2977}; 2978 2979static void 2980fxp_load_ucode(struct fxp_softc *sc) 2981{ 2982 struct ucode *uc; 2983 struct fxp_cb_ucode *cbp; 2984 int i; 2985 2986 for (uc = ucode_table; uc->ucode != NULL; uc++) 2987 if (sc->revision == uc->revision) 2988 break; 2989 if (uc->ucode == NULL) 2990 return; 2991 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2992 cbp->cb_status = 0; 2993 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2994 cbp->link_addr = 0xffffffff; /* (no) next command */ 2995 for (i = 0; i < uc->length; i++) 2996 cbp->ucode[i] = htole32(uc->ucode[i]); 2997 if (uc->int_delay_offset) 2998 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2999 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3000 if (uc->bundle_max_offset) 3001 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3002 htole16(sc->tunable_bundle_max); 3003 /* 3004 * Download the ucode to the chip. 3005 */ 3006 fxp_scb_wait(sc); 3007 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 3008 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3009 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3010 /* ...and wait for it to complete. */ 3011 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3012 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 3013 device_printf(sc->dev, 3014 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3015 sc->tunable_int_delay, 3016 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3017 sc->flags |= FXP_FLAG_UCODE; 3018} 3019 3020static int 3021sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3022{ 3023 int error, value; 3024 3025 value = *(int *)arg1; 3026 error = sysctl_handle_int(oidp, &value, 0, req); 3027 if (error || !req->newptr) 3028 return (error); 3029 if (value < low || value > high) 3030 return (EINVAL); 3031 *(int *)arg1 = value; 3032 return (0); 3033} 3034 3035/* 3036 * Interrupt delay is expressed in microseconds, a multiplier is used 3037 * to convert this to the appropriate clock ticks before using. 3038 */ 3039static int 3040sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3041{ 3042 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3043} 3044 3045static int 3046sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3047{ 3048 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3049} 3050