if_fxp.c revision 150408
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 150408 2005-09-21 04:36:40Z marcel $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 194 { 0, -1, NULL }, 195}; 196 197#ifdef FXP_IP_CSUM_WAR 198#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 199#else 200#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 201#endif 202 203static int fxp_probe(device_t dev); 204static int fxp_attach(device_t dev); 205static int fxp_detach(device_t dev); 206static int fxp_shutdown(device_t dev); 207static int fxp_suspend(device_t dev); 208static int fxp_resume(device_t dev); 209 210static void fxp_intr(void *xsc); 211static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 212 uint8_t statack, int count); 213static void fxp_init(void *xsc); 214static void fxp_init_body(struct fxp_softc *sc); 215static void fxp_tick(void *xsc); 216static void fxp_start(struct ifnet *ifp); 217static void fxp_start_body(struct ifnet *ifp); 218static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 219static void fxp_stop(struct fxp_softc *sc); 220static void fxp_release(struct fxp_softc *sc); 221static int fxp_ioctl(struct ifnet *ifp, u_long command, 222 caddr_t data); 223static void fxp_watchdog(struct ifnet *ifp); 224static int fxp_add_rfabuf(struct fxp_softc *sc, 225 struct fxp_rx *rxp); 226static int fxp_mc_addrs(struct fxp_softc *sc); 227static void fxp_mc_setup(struct fxp_softc *sc); 228static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 229 int autosize); 230static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 231 uint16_t data); 232static void fxp_autosize_eeprom(struct fxp_softc *sc); 233static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 236 int offset, int words); 237static int fxp_ifmedia_upd(struct ifnet *ifp); 238static void fxp_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 241static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 242 struct ifmediareq *ifmr); 243static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 244static void fxp_miibus_writereg(device_t dev, int phy, int reg, 245 int value); 246static void fxp_load_ucode(struct fxp_softc *sc); 247static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 248 int low, int high); 249static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 250static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 251static void fxp_scb_wait(struct fxp_softc *sc); 252static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253static void fxp_dma_wait(struct fxp_softc *sc, 254 volatile uint16_t *status, bus_dma_tag_t dmat, 255 bus_dmamap_t map); 256 257static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271}; 272 273static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277}; 278 279static devclass_t fxp_devclass; 280 281DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 283DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 284 285/* 286 * Wait for the previous command to be accepted (but not necessarily 287 * completed). 288 */ 289static void 290fxp_scb_wait(struct fxp_softc *sc) 291{ 292 union { 293 uint16_t w; 294 uint8_t b[2]; 295 } flowctl; 296 int i = 10000; 297 298 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 299 DELAY(2); 300 if (i == 0) { 301 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 302 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 303 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 304 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 305 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 306 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 307 } 308} 309 310static void 311fxp_scb_cmd(struct fxp_softc *sc, int cmd) 312{ 313 314 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 315 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 316 fxp_scb_wait(sc); 317 } 318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 319} 320 321static void 322fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 323 bus_dma_tag_t dmat, bus_dmamap_t map) 324{ 325 int i = 10000; 326 327 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 328 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 329 DELAY(2); 330 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 331 } 332 if (i == 0) 333 device_printf(sc->dev, "DMA timeout\n"); 334} 335 336/* 337 * Return identification string if this device is ours. 338 */ 339static int 340fxp_probe(device_t dev) 341{ 342 uint16_t devid; 343 uint8_t revid; 344 struct fxp_ident *ident; 345 346 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 347 devid = pci_get_device(dev); 348 revid = pci_get_revid(dev); 349 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 350 if (ident->devid == devid && 351 (ident->revid == revid || ident->revid == -1)) { 352 device_set_desc(dev, ident->name); 353 return (BUS_PROBE_DEFAULT); 354 } 355 } 356 } 357 return (ENXIO); 358} 359 360static void 361fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 362{ 363 uint32_t *addr; 364 365 if (error) 366 return; 367 368 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 369 addr = arg; 370 *addr = segs->ds_addr; 371} 372 373static int 374fxp_attach(device_t dev) 375{ 376 struct fxp_softc *sc; 377 struct fxp_cb_tx *tcbp; 378 struct fxp_tx *txp; 379 struct fxp_rx *rxp; 380 struct ifnet *ifp; 381 uint32_t val; 382 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 383 u_char eaddr[ETHER_ADDR_LEN]; 384 int i, rid, m1, m2, prefer_iomap; 385 int error; 386 387 error = 0; 388 sc = device_get_softc(dev); 389 sc->dev = dev; 390 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 391 MTX_DEF); 392 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 393 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 394 fxp_serial_ifmedia_sts); 395 396 ifp = sc->ifp = if_alloc(IFT_ETHER); 397 if (ifp == NULL) { 398 device_printf(dev, "can not if_alloc()\n"); 399 error = ENOSPC; 400 goto fail; 401 } 402 403 /* 404 * Enable bus mastering. 405 */ 406 pci_enable_busmaster(dev); 407 val = pci_read_config(dev, PCIR_COMMAND, 2); 408 409 /* 410 * Figure out which we should try first - memory mapping or i/o mapping? 411 * We default to memory mapping. Then we accept an override from the 412 * command line. Then we check to see which one is enabled. 413 */ 414 m1 = PCIM_CMD_MEMEN; 415 m2 = PCIM_CMD_PORTEN; 416 prefer_iomap = 0; 417 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 418 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 419 m1 = PCIM_CMD_PORTEN; 420 m2 = PCIM_CMD_MEMEN; 421 } 422 423 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 424 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 425 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 426 if (sc->mem == NULL) { 427 sc->rtp = 428 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 429 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 430 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 431 RF_ACTIVE); 432 } 433 434 if (!sc->mem) { 435 error = ENXIO; 436 goto fail; 437 } 438 if (bootverbose) { 439 device_printf(dev, "using %s space register mapping\n", 440 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 441 } 442 443 sc->sc_st = rman_get_bustag(sc->mem); 444 sc->sc_sh = rman_get_bushandle(sc->mem); 445 446 /* 447 * Allocate our interrupt. 448 */ 449 rid = 0; 450 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 451 RF_SHAREABLE | RF_ACTIVE); 452 if (sc->irq == NULL) { 453 device_printf(dev, "could not map interrupt\n"); 454 error = ENXIO; 455 goto fail; 456 } 457 458 /* 459 * Reset to a stable state. 460 */ 461 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 462 DELAY(10); 463 464 /* 465 * Find out how large of an SEEPROM we have. 466 */ 467 fxp_autosize_eeprom(sc); 468 469 /* 470 * Find out the chip revision; lump all 82557 revs together. 471 */ 472 fxp_read_eeprom(sc, &data, 5, 1); 473 if ((data >> 8) == 1) 474 sc->revision = FXP_REV_82557; 475 else 476 sc->revision = pci_get_revid(dev); 477 478 /* 479 * Determine whether we must use the 503 serial interface. 480 */ 481 fxp_read_eeprom(sc, &data, 6, 1); 482 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 483 && (data & FXP_PHY_SERIAL_ONLY)) 484 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 485 486 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 487 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 488 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 489 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 490 "FXP driver receive interrupt microcode bundling delay"); 491 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 492 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 493 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 494 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 495 "FXP driver receive interrupt microcode bundle size limit"); 496 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 497 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 498 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 499 "FXP RNR events"); 500 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 501 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 502 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 503 "FXP flow control disabled"); 504 505 /* 506 * Pull in device tunables. 507 */ 508 sc->tunable_int_delay = TUNABLE_INT_DELAY; 509 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 510 sc->tunable_noflow = 1; 511 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 512 "int_delay", &sc->tunable_int_delay); 513 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 514 "bundle_max", &sc->tunable_bundle_max); 515 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 516 "noflow", &sc->tunable_noflow); 517 sc->rnr = 0; 518 519 /* 520 * Enable workarounds for certain chip revision deficiencies. 521 * 522 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 523 * some systems based a normal 82559 design, have a defect where 524 * the chip can cause a PCI protocol violation if it receives 525 * a CU_RESUME command when it is entering the IDLE state. The 526 * workaround is to disable Dynamic Standby Mode, so the chip never 527 * deasserts CLKRUN#, and always remains in an active state. 528 * 529 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 530 */ 531 i = pci_get_device(dev); 532 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 533 sc->revision >= FXP_REV_82559_A0) { 534 fxp_read_eeprom(sc, &data, 10, 1); 535 if (data & 0x02) { /* STB enable */ 536 uint16_t cksum; 537 int i; 538 539 device_printf(dev, 540 "Disabling dynamic standby mode in EEPROM\n"); 541 data &= ~0x02; 542 fxp_write_eeprom(sc, &data, 10, 1); 543 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 544 cksum = 0; 545 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 546 fxp_read_eeprom(sc, &data, i, 1); 547 cksum += data; 548 } 549 i = (1 << sc->eeprom_size) - 1; 550 cksum = 0xBABA - cksum; 551 fxp_read_eeprom(sc, &data, i, 1); 552 fxp_write_eeprom(sc, &cksum, i, 1); 553 device_printf(dev, 554 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 555 i, data, cksum); 556#if 1 557 /* 558 * If the user elects to continue, try the software 559 * workaround, as it is better than nothing. 560 */ 561 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 562#endif 563 } 564 } 565 566 /* 567 * If we are not a 82557 chip, we can enable extended features. 568 */ 569 if (sc->revision != FXP_REV_82557) { 570 /* 571 * If MWI is enabled in the PCI configuration, and there 572 * is a valid cacheline size (8 or 16 dwords), then tell 573 * the board to turn on MWI. 574 */ 575 if (val & PCIM_CMD_MWRICEN && 576 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 577 sc->flags |= FXP_FLAG_MWI_ENABLE; 578 579 /* turn on the extended TxCB feature */ 580 sc->flags |= FXP_FLAG_EXT_TXCB; 581 582 /* enable reception of long frames for VLAN */ 583 sc->flags |= FXP_FLAG_LONG_PKT_EN; 584 } else { 585 /* a hack to get long VLAN frames on a 82557 */ 586 sc->flags |= FXP_FLAG_SAVE_BAD; 587 } 588 589 /* 590 * Enable use of extended RFDs and TCBs for 82550 591 * and later chips. Note: we need extended TXCB support 592 * too, but that's already enabled by the code above. 593 * Be careful to do this only on the right devices. 594 */ 595 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 596 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 597 || sc->revision == FXP_REV_82551_10) { 598 sc->rfa_size = sizeof (struct fxp_rfa); 599 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 600 sc->flags |= FXP_FLAG_EXT_RFA; 601 } else { 602 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 603 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 604 } 605 606 /* 607 * Allocate DMA tags and DMA safe memory. 608 */ 609 sc->maxtxseg = FXP_NTXSEG; 610 if (sc->flags & FXP_FLAG_EXT_RFA) 611 sc->maxtxseg--; 612 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 613 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 614 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 615 &sc->fxp_mtag); 616 if (error) { 617 device_printf(dev, "could not allocate dma tag\n"); 618 goto fail; 619 } 620 621 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 622 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 623 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 624 &sc->fxp_stag); 625 if (error) { 626 device_printf(dev, "could not allocate dma tag\n"); 627 goto fail; 628 } 629 630 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 631 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 632 if (error) 633 goto fail; 634 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 635 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 636 if (error) { 637 device_printf(dev, "could not map the stats buffer\n"); 638 goto fail; 639 } 640 641 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 642 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 643 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 644 if (error) { 645 device_printf(dev, "could not allocate dma tag\n"); 646 goto fail; 647 } 648 649 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 650 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 651 if (error) 652 goto fail; 653 654 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 655 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 656 &sc->fxp_desc.cbl_addr, 0); 657 if (error) { 658 device_printf(dev, "could not map DMA memory\n"); 659 goto fail; 660 } 661 662 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 663 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 664 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 665 &sc->mcs_tag); 666 if (error) { 667 device_printf(dev, "could not allocate dma tag\n"); 668 goto fail; 669 } 670 671 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 672 BUS_DMA_NOWAIT, &sc->mcs_map); 673 if (error) 674 goto fail; 675 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 676 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 677 if (error) { 678 device_printf(dev, "can't map the multicast setup command\n"); 679 goto fail; 680 } 681 682 /* 683 * Pre-allocate the TX DMA maps and setup the pointers to 684 * the TX command blocks. 685 */ 686 txp = sc->fxp_desc.tx_list; 687 tcbp = sc->fxp_desc.cbl_list; 688 for (i = 0; i < FXP_NTXCB; i++) { 689 txp[i].tx_cb = tcbp + i; 690 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 691 if (error) { 692 device_printf(dev, "can't create DMA map for TX\n"); 693 goto fail; 694 } 695 } 696 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 697 if (error) { 698 device_printf(dev, "can't create spare DMA map\n"); 699 goto fail; 700 } 701 702 /* 703 * Pre-allocate our receive buffers. 704 */ 705 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 706 for (i = 0; i < FXP_NRFABUFS; i++) { 707 rxp = &sc->fxp_desc.rx_list[i]; 708 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 709 if (error) { 710 device_printf(dev, "can't create DMA map for RX\n"); 711 goto fail; 712 } 713 if (fxp_add_rfabuf(sc, rxp) != 0) { 714 error = ENOMEM; 715 goto fail; 716 } 717 } 718 719 /* 720 * Read MAC address. 721 */ 722 fxp_read_eeprom(sc, myea, 0, 3); 723 eaddr[0] = myea[0] & 0xff; 724 eaddr[1] = myea[0] >> 8; 725 eaddr[2] = myea[1] & 0xff; 726 eaddr[3] = myea[1] >> 8; 727 eaddr[4] = myea[2] & 0xff; 728 eaddr[5] = myea[2] >> 8; 729 if (bootverbose) { 730 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 731 pci_get_vendor(dev), pci_get_device(dev), 732 pci_get_subvendor(dev), pci_get_subdevice(dev), 733 pci_get_revid(dev)); 734 fxp_read_eeprom(sc, &data, 10, 1); 735 device_printf(dev, "Dynamic Standby mode is %s\n", 736 data & 0x02 ? "enabled" : "disabled"); 737 } 738 739 /* 740 * If this is only a 10Mbps device, then there is no MII, and 741 * the PHY will use a serial interface instead. 742 * 743 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 744 * doesn't have a programming interface of any sort. The 745 * media is sensed automatically based on how the link partner 746 * is configured. This is, in essence, manual configuration. 747 */ 748 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 749 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 750 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 751 } else { 752 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 753 fxp_ifmedia_sts)) { 754 device_printf(dev, "MII without any PHY!\n"); 755 error = ENXIO; 756 goto fail; 757 } 758 } 759 760 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 761 ifp->if_baudrate = 100000000; 762 ifp->if_init = fxp_init; 763 ifp->if_softc = sc; 764 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 765 ifp->if_ioctl = fxp_ioctl; 766 ifp->if_start = fxp_start; 767 ifp->if_watchdog = fxp_watchdog; 768 769 ifp->if_capabilities = ifp->if_capenable = 0; 770 771 /* Enable checksum offload for 82550 or better chips */ 772 if (sc->flags & FXP_FLAG_EXT_RFA) { 773 ifp->if_hwassist = FXP_CSUM_FEATURES; 774 ifp->if_capabilities |= IFCAP_HWCSUM; 775 ifp->if_capenable |= IFCAP_HWCSUM; 776 } 777 778#ifdef DEVICE_POLLING 779 /* Inform the world we support polling. */ 780 ifp->if_capabilities |= IFCAP_POLLING; 781 ifp->if_capenable |= IFCAP_POLLING; 782#endif 783 784 /* 785 * Attach the interface. 786 */ 787 ether_ifattach(ifp, eaddr); 788 789 /* 790 * Tell the upper layer(s) we support long frames. 791 * Must appear after the call to ether_ifattach() because 792 * ether_ifattach() sets ifi_hdrlen to the default value. 793 */ 794 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 795 ifp->if_capabilities |= IFCAP_VLAN_MTU; 796 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 797 798 /* 799 * Let the system queue as many packets as we have available 800 * TX descriptors. 801 */ 802 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 803 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 804 IFQ_SET_READY(&ifp->if_snd); 805 806 /* 807 * Hook our interrupt after all initialization is complete. 808 */ 809 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 810 fxp_intr, sc, &sc->ih); 811 if (error) { 812 device_printf(dev, "could not setup irq\n"); 813 ether_ifdetach(sc->ifp); 814 goto fail; 815 } 816 817fail: 818 if (error) 819 fxp_release(sc); 820 return (error); 821} 822 823/* 824 * Release all resources. The softc lock should not be held and the 825 * interrupt should already be torn down. 826 */ 827static void 828fxp_release(struct fxp_softc *sc) 829{ 830 struct fxp_rx *rxp; 831 struct fxp_tx *txp; 832 int i; 833 834 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 835 KASSERT(sc->ih == NULL, 836 ("fxp_release() called with intr handle still active")); 837 if (sc->miibus) 838 device_delete_child(sc->dev, sc->miibus); 839 bus_generic_detach(sc->dev); 840 ifmedia_removeall(&sc->sc_media); 841 if (sc->fxp_desc.cbl_list) { 842 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 843 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 844 sc->cbl_map); 845 } 846 if (sc->fxp_stats) { 847 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 848 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 849 } 850 if (sc->mcsp) { 851 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 852 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 853 } 854 if (sc->irq) 855 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 856 if (sc->mem) 857 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 858 if (sc->fxp_mtag) { 859 for (i = 0; i < FXP_NRFABUFS; i++) { 860 rxp = &sc->fxp_desc.rx_list[i]; 861 if (rxp->rx_mbuf != NULL) { 862 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 863 BUS_DMASYNC_POSTREAD); 864 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 865 m_freem(rxp->rx_mbuf); 866 } 867 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 868 } 869 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 870 for (i = 0; i < FXP_NTXCB; i++) { 871 txp = &sc->fxp_desc.tx_list[i]; 872 if (txp->tx_mbuf != NULL) { 873 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 874 BUS_DMASYNC_POSTWRITE); 875 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 876 m_freem(txp->tx_mbuf); 877 } 878 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 879 } 880 bus_dma_tag_destroy(sc->fxp_mtag); 881 } 882 if (sc->fxp_stag) 883 bus_dma_tag_destroy(sc->fxp_stag); 884 if (sc->cbl_tag) 885 bus_dma_tag_destroy(sc->cbl_tag); 886 if (sc->mcs_tag) 887 bus_dma_tag_destroy(sc->mcs_tag); 888 if (sc->ifp) 889 if_free(sc->ifp); 890 891 mtx_destroy(&sc->sc_mtx); 892} 893 894/* 895 * Detach interface. 896 */ 897static int 898fxp_detach(device_t dev) 899{ 900 struct fxp_softc *sc = device_get_softc(dev); 901 902 FXP_LOCK(sc); 903 sc->suspended = 1; /* Do same thing as we do for suspend */ 904 /* 905 * Stop DMA and drop transmit queue, but disable interrupts first. 906 */ 907 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 908 fxp_stop(sc); 909 FXP_UNLOCK(sc); 910 callout_drain(&sc->stat_ch); 911 912 /* 913 * Close down routes etc. 914 */ 915 ether_ifdetach(sc->ifp); 916 917 /* 918 * Unhook interrupt before dropping lock. This is to prevent 919 * races with fxp_intr(). 920 */ 921 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 922 sc->ih = NULL; 923 924 /* Release our allocated resources. */ 925 fxp_release(sc); 926 return (0); 927} 928 929/* 930 * Device shutdown routine. Called at system shutdown after sync. The 931 * main purpose of this routine is to shut off receiver DMA so that 932 * kernel memory doesn't get clobbered during warmboot. 933 */ 934static int 935fxp_shutdown(device_t dev) 936{ 937 struct fxp_softc *sc = device_get_softc(dev); 938 939 /* 940 * Make sure that DMA is disabled prior to reboot. Not doing 941 * do could allow DMA to corrupt kernel memory during the 942 * reboot before the driver initializes. 943 */ 944 FXP_LOCK(sc); 945 fxp_stop(sc); 946 FXP_UNLOCK(sc); 947 return (0); 948} 949 950/* 951 * Device suspend routine. Stop the interface and save some PCI 952 * settings in case the BIOS doesn't restore them properly on 953 * resume. 954 */ 955static int 956fxp_suspend(device_t dev) 957{ 958 struct fxp_softc *sc = device_get_softc(dev); 959 960 FXP_LOCK(sc); 961 962 fxp_stop(sc); 963 964 sc->suspended = 1; 965 966 FXP_UNLOCK(sc); 967 return (0); 968} 969 970/* 971 * Device resume routine. re-enable busmastering, and restart the interface if 972 * appropriate. 973 */ 974static int 975fxp_resume(device_t dev) 976{ 977 struct fxp_softc *sc = device_get_softc(dev); 978 struct ifnet *ifp = sc->ifp; 979 980 FXP_LOCK(sc); 981 982 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 983 DELAY(10); 984 985 /* reinitialize interface if necessary */ 986 if (ifp->if_flags & IFF_UP) 987 fxp_init_body(sc); 988 989 sc->suspended = 0; 990 991 FXP_UNLOCK(sc); 992 return (0); 993} 994 995static void 996fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 997{ 998 uint16_t reg; 999 int x; 1000 1001 /* 1002 * Shift in data. 1003 */ 1004 for (x = 1 << (length - 1); x; x >>= 1) { 1005 if (data & x) 1006 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1007 else 1008 reg = FXP_EEPROM_EECS; 1009 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1010 DELAY(1); 1011 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1012 DELAY(1); 1013 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1014 DELAY(1); 1015 } 1016} 1017 1018/* 1019 * Read from the serial EEPROM. Basically, you manually shift in 1020 * the read opcode (one bit at a time) and then shift in the address, 1021 * and then you shift out the data (all of this one bit at a time). 1022 * The word size is 16 bits, so you have to provide the address for 1023 * every 16 bits of data. 1024 */ 1025static uint16_t 1026fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1027{ 1028 uint16_t reg, data; 1029 int x; 1030 1031 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1032 /* 1033 * Shift in read opcode. 1034 */ 1035 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1036 /* 1037 * Shift in address. 1038 */ 1039 data = 0; 1040 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1041 if (offset & x) 1042 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1043 else 1044 reg = FXP_EEPROM_EECS; 1045 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1046 DELAY(1); 1047 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1048 DELAY(1); 1049 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1050 DELAY(1); 1051 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1052 data++; 1053 if (autosize && reg == 0) { 1054 sc->eeprom_size = data; 1055 break; 1056 } 1057 } 1058 /* 1059 * Shift out data. 1060 */ 1061 data = 0; 1062 reg = FXP_EEPROM_EECS; 1063 for (x = 1 << 15; x; x >>= 1) { 1064 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1065 DELAY(1); 1066 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1067 data |= x; 1068 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1069 DELAY(1); 1070 } 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1072 DELAY(1); 1073 1074 return (data); 1075} 1076 1077static void 1078fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1079{ 1080 int i; 1081 1082 /* 1083 * Erase/write enable. 1084 */ 1085 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1086 fxp_eeprom_shiftin(sc, 0x4, 3); 1087 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1089 DELAY(1); 1090 /* 1091 * Shift in write opcode, address, data. 1092 */ 1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1094 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1095 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1096 fxp_eeprom_shiftin(sc, data, 16); 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1098 DELAY(1); 1099 /* 1100 * Wait for EEPROM to finish up. 1101 */ 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1103 DELAY(1); 1104 for (i = 0; i < 1000; i++) { 1105 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1106 break; 1107 DELAY(50); 1108 } 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1110 DELAY(1); 1111 /* 1112 * Erase/write disable. 1113 */ 1114 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1115 fxp_eeprom_shiftin(sc, 0x4, 3); 1116 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1117 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1118 DELAY(1); 1119} 1120 1121/* 1122 * From NetBSD: 1123 * 1124 * Figure out EEPROM size. 1125 * 1126 * 559's can have either 64-word or 256-word EEPROMs, the 558 1127 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1128 * talks about the existance of 16 to 256 word EEPROMs. 1129 * 1130 * The only known sizes are 64 and 256, where the 256 version is used 1131 * by CardBus cards to store CIS information. 1132 * 1133 * The address is shifted in msb-to-lsb, and after the last 1134 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1135 * after which follows the actual data. We try to detect this zero, by 1136 * probing the data-out bit in the EEPROM control register just after 1137 * having shifted in a bit. If the bit is zero, we assume we've 1138 * shifted enough address bits. The data-out should be tri-state, 1139 * before this, which should translate to a logical one. 1140 */ 1141static void 1142fxp_autosize_eeprom(struct fxp_softc *sc) 1143{ 1144 1145 /* guess maximum size of 256 words */ 1146 sc->eeprom_size = 8; 1147 1148 /* autosize */ 1149 (void) fxp_eeprom_getword(sc, 0, 1); 1150} 1151 1152static void 1153fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1154{ 1155 int i; 1156 1157 for (i = 0; i < words; i++) 1158 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1159} 1160 1161static void 1162fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1163{ 1164 int i; 1165 1166 for (i = 0; i < words; i++) 1167 fxp_eeprom_putword(sc, offset + i, data[i]); 1168} 1169 1170/* 1171 * Grab the softc lock and call the real fxp_start_body() routine 1172 */ 1173static void 1174fxp_start(struct ifnet *ifp) 1175{ 1176 struct fxp_softc *sc = ifp->if_softc; 1177 1178 FXP_LOCK(sc); 1179 fxp_start_body(ifp); 1180 FXP_UNLOCK(sc); 1181} 1182 1183/* 1184 * Start packet transmission on the interface. 1185 * This routine must be called with the softc lock held, and is an 1186 * internal entry point only. 1187 */ 1188static void 1189fxp_start_body(struct ifnet *ifp) 1190{ 1191 struct fxp_softc *sc = ifp->if_softc; 1192 struct mbuf *mb_head; 1193 int error, txqueued; 1194 1195 FXP_LOCK_ASSERT(sc, MA_OWNED); 1196 1197 /* 1198 * See if we need to suspend xmit until the multicast filter 1199 * has been reprogrammed (which can only be done at the head 1200 * of the command chain). 1201 */ 1202 if (sc->need_mcsetup) 1203 return; 1204 1205 /* 1206 * We're finished if there is nothing more to add to the list or if 1207 * we're all filled up with buffers to transmit. 1208 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1209 * a NOP command when needed. 1210 */ 1211 txqueued = 0; 1212 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1213 sc->tx_queued < FXP_NTXCB - 1) { 1214 1215 /* 1216 * Grab a packet to transmit. 1217 */ 1218 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1219 if (mb_head == NULL) 1220 break; 1221 1222 error = fxp_encap(sc, mb_head); 1223 if (error) 1224 break; 1225 txqueued = 1; 1226 } 1227 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1228 1229 /* 1230 * We're finished. If we added to the list, issue a RESUME to get DMA 1231 * going again if suspended. 1232 */ 1233 if (txqueued) { 1234 fxp_scb_wait(sc); 1235 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1236 } 1237} 1238 1239static int 1240fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1241{ 1242 struct ifnet *ifp; 1243 struct mbuf *m; 1244 struct fxp_tx *txp; 1245 struct fxp_cb_tx *cbp; 1246 bus_dma_segment_t segs[FXP_NTXSEG]; 1247 int chainlen, error, i, nseg; 1248 1249 FXP_LOCK_ASSERT(sc, MA_OWNED); 1250 ifp = sc->ifp; 1251 1252 /* 1253 * Get pointer to next available tx desc. 1254 */ 1255 txp = sc->fxp_desc.tx_last->tx_next; 1256 1257 /* 1258 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1259 * Ethernet Controller Family Open Source Software 1260 * Developer Manual says: 1261 * Using software parsing is only allowed with legal 1262 * TCP/IP or UDP/IP packets. 1263 * ... 1264 * For all other datagrams, hardware parsing must 1265 * be used. 1266 * Software parsing appears to truncate ICMP and 1267 * fragmented UDP packets that contain one to three 1268 * bytes in the second (and final) mbuf of the packet. 1269 */ 1270 if (sc->flags & FXP_FLAG_EXT_RFA) 1271 txp->tx_cb->ipcb_ip_activation_high = 1272 FXP_IPCB_HARDWAREPARSING_ENABLE; 1273 1274 /* 1275 * Deal with TCP/IP checksum offload. Note that 1276 * in order for TCP checksum offload to work, 1277 * the pseudo header checksum must have already 1278 * been computed and stored in the checksum field 1279 * in the TCP header. The stack should have 1280 * already done this for us. 1281 */ 1282 if (m_head->m_pkthdr.csum_flags) { 1283 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1284 txp->tx_cb->ipcb_ip_schedule = 1285 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1286 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1287 txp->tx_cb->ipcb_ip_schedule |= 1288 FXP_IPCB_TCP_PACKET; 1289 } 1290 1291#ifdef FXP_IP_CSUM_WAR 1292 /* 1293 * XXX The 82550 chip appears to have trouble 1294 * dealing with IP header checksums in very small 1295 * datagrams, namely fragments from 1 to 3 bytes 1296 * in size. For example, say you want to transmit 1297 * a UDP packet of 1473 bytes. The packet will be 1298 * fragmented over two IP datagrams, the latter 1299 * containing only one byte of data. The 82550 will 1300 * botch the header checksum on the 1-byte fragment. 1301 * As long as the datagram contains 4 or more bytes 1302 * of data, you're ok. 1303 * 1304 * The following code attempts to work around this 1305 * problem: if the datagram is less than 38 bytes 1306 * in size (14 bytes ether header, 20 bytes IP header, 1307 * plus 4 bytes of data), we punt and compute the IP 1308 * header checksum by hand. This workaround doesn't 1309 * work very well, however, since it can be fooled 1310 * by things like VLAN tags and IP options that make 1311 * the header sizes/offsets vary. 1312 */ 1313 1314 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1315 if (m_head->m_pkthdr.len < 38) { 1316 struct ip *ip; 1317 m_head->m_data += ETHER_HDR_LEN; 1318 ip = mtod(mb_head, struct ip *); 1319 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1320 m_head->m_data -= ETHER_HDR_LEN; 1321 } else { 1322 txp->tx_cb->ipcb_ip_activation_high = 1323 FXP_IPCB_HARDWAREPARSING_ENABLE; 1324 txp->tx_cb->ipcb_ip_schedule |= 1325 FXP_IPCB_IP_CHECKSUM_ENABLE; 1326 } 1327 } 1328#endif 1329 } 1330 1331 chainlen = 0; 1332 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1333 chainlen++; 1334 if (chainlen > sc->maxtxseg) { 1335 struct mbuf *mn; 1336 1337 /* 1338 * We ran out of segments. We have to recopy this 1339 * mbuf chain first. Bail out if we can't get the 1340 * new buffers. 1341 */ 1342 mn = m_defrag(m_head, M_DONTWAIT); 1343 if (mn == NULL) { 1344 m_freem(m_head); 1345 return (-1); 1346 } else { 1347 m_head = mn; 1348 } 1349 } 1350 1351 /* 1352 * Go through each of the mbufs in the chain and initialize 1353 * the transmit buffer descriptors with the physical address 1354 * and size of the mbuf. 1355 */ 1356 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1357 m_head, segs, &nseg, 0); 1358 if (error) { 1359 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1360 m_freem(m_head); 1361 return (-1); 1362 } 1363 1364 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1365 1366 cbp = txp->tx_cb; 1367 for (i = 0; i < nseg; i++) { 1368 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1369 /* 1370 * If this is an 82550/82551, then we're using extended 1371 * TxCBs _and_ we're using checksum offload. This means 1372 * that the TxCB is really an IPCB. One major difference 1373 * between the two is that with plain extended TxCBs, 1374 * the bottom half of the TxCB contains two entries from 1375 * the TBD array, whereas IPCBs contain just one entry: 1376 * one entry (8 bytes) has been sacrificed for the TCP/IP 1377 * checksum offload control bits. So to make things work 1378 * right, we have to start filling in the TBD array 1379 * starting from a different place depending on whether 1380 * the chip is an 82550/82551 or not. 1381 */ 1382 if (sc->flags & FXP_FLAG_EXT_RFA) { 1383 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1384 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1385 } else { 1386 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1387 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1388 } 1389 } 1390 cbp->tbd_number = nseg; 1391 1392 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1393 txp->tx_mbuf = m_head; 1394 txp->tx_cb->cb_status = 0; 1395 txp->tx_cb->byte_count = 0; 1396 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1397 txp->tx_cb->cb_command = 1398 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1399 FXP_CB_COMMAND_S); 1400 } else { 1401 txp->tx_cb->cb_command = 1402 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1403 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1404 /* 1405 * Set a 5 second timer just in case we don't hear 1406 * from the card again. 1407 */ 1408 ifp->if_timer = 5; 1409 } 1410 txp->tx_cb->tx_threshold = tx_threshold; 1411 1412 /* 1413 * Advance the end of list forward. 1414 */ 1415 1416#ifdef __alpha__ 1417 /* 1418 * On platforms which can't access memory in 16-bit 1419 * granularities, we must prevent the card from DMA'ing 1420 * up the status while we update the command field. 1421 * This could cause us to overwrite the completion status. 1422 * XXX This is probably bogus and we're _not_ looking 1423 * for atomicity here. 1424 */ 1425 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1426 htole16(FXP_CB_COMMAND_S)); 1427#else 1428 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1429#endif /*__alpha__*/ 1430 sc->fxp_desc.tx_last = txp; 1431 1432 /* 1433 * Advance the beginning of the list forward if there are 1434 * no other packets queued (when nothing is queued, tx_first 1435 * sits on the last TxCB that was sent out). 1436 */ 1437 if (sc->tx_queued == 0) 1438 sc->fxp_desc.tx_first = txp; 1439 1440 sc->tx_queued++; 1441 1442 /* 1443 * Pass packet to bpf if there is a listener. 1444 */ 1445 BPF_MTAP(ifp, m_head); 1446 return (0); 1447} 1448 1449#ifdef DEVICE_POLLING 1450static poll_handler_t fxp_poll; 1451 1452static void 1453fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1454{ 1455 struct fxp_softc *sc = ifp->if_softc; 1456 uint8_t statack; 1457 1458 FXP_LOCK(sc); 1459 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1460 ether_poll_deregister(ifp); 1461 cmd = POLL_DEREGISTER; 1462 } 1463 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1464 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1465 FXP_UNLOCK(sc); 1466 return; 1467 } 1468 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1469 FXP_SCB_STATACK_FR; 1470 if (cmd == POLL_AND_CHECK_STATUS) { 1471 uint8_t tmp; 1472 1473 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1474 if (tmp == 0xff || tmp == 0) { 1475 FXP_UNLOCK(sc); 1476 return; /* nothing to do */ 1477 } 1478 tmp &= ~statack; 1479 /* ack what we can */ 1480 if (tmp != 0) 1481 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1482 statack |= tmp; 1483 } 1484 fxp_intr_body(sc, ifp, statack, count); 1485 FXP_UNLOCK(sc); 1486} 1487#endif /* DEVICE_POLLING */ 1488 1489/* 1490 * Process interface interrupts. 1491 */ 1492static void 1493fxp_intr(void *xsc) 1494{ 1495 struct fxp_softc *sc = xsc; 1496 struct ifnet *ifp = sc->ifp; 1497 uint8_t statack; 1498 1499 FXP_LOCK(sc); 1500 if (sc->suspended) { 1501 FXP_UNLOCK(sc); 1502 return; 1503 } 1504 1505#ifdef DEVICE_POLLING 1506 if (ifp->if_flags & IFF_POLLING) { 1507 FXP_UNLOCK(sc); 1508 return; 1509 } 1510 if ((ifp->if_capenable & IFCAP_POLLING) && 1511 ether_poll_register(fxp_poll, ifp)) { 1512 /* disable interrupts */ 1513 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1514 FXP_UNLOCK(sc); 1515 fxp_poll(ifp, 0, 1); 1516 return; 1517 } 1518#endif 1519 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1520 /* 1521 * It should not be possible to have all bits set; the 1522 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1523 * all bits are set, this may indicate that the card has 1524 * been physically ejected, so ignore it. 1525 */ 1526 if (statack == 0xff) { 1527 FXP_UNLOCK(sc); 1528 return; 1529 } 1530 1531 /* 1532 * First ACK all the interrupts in this pass. 1533 */ 1534 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1535 fxp_intr_body(sc, ifp, statack, -1); 1536 } 1537 FXP_UNLOCK(sc); 1538} 1539 1540static void 1541fxp_txeof(struct fxp_softc *sc) 1542{ 1543 struct fxp_tx *txp; 1544 1545 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1546 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1547 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1548 txp = txp->tx_next) { 1549 if (txp->tx_mbuf != NULL) { 1550 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1551 BUS_DMASYNC_POSTWRITE); 1552 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1553 m_freem(txp->tx_mbuf); 1554 txp->tx_mbuf = NULL; 1555 /* clear this to reset csum offload bits */ 1556 txp->tx_cb->tbd[0].tb_addr = 0; 1557 } 1558 sc->tx_queued--; 1559 } 1560 sc->fxp_desc.tx_first = txp; 1561 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1562} 1563 1564static void 1565fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1566 int count) 1567{ 1568 struct mbuf *m; 1569 struct fxp_rx *rxp; 1570 struct fxp_rfa *rfa; 1571 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1572 int fxp_rc = 0; 1573 1574 FXP_LOCK_ASSERT(sc, MA_OWNED); 1575 if (rnr) 1576 sc->rnr++; 1577#ifdef DEVICE_POLLING 1578 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1579 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1580 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1581 rnr = 1; 1582 } 1583#endif 1584 1585 /* 1586 * Free any finished transmit mbuf chains. 1587 * 1588 * Handle the CNA event likt a CXTNO event. It used to 1589 * be that this event (control unit not ready) was not 1590 * encountered, but it is now with the SMPng modifications. 1591 * The exact sequence of events that occur when the interface 1592 * is brought up are different now, and if this event 1593 * goes unhandled, the configuration/rxfilter setup sequence 1594 * can stall for several seconds. The result is that no 1595 * packets go out onto the wire for about 5 to 10 seconds 1596 * after the interface is ifconfig'ed for the first time. 1597 */ 1598 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1599 fxp_txeof(sc); 1600 1601 ifp->if_timer = 0; 1602 if (sc->tx_queued == 0) { 1603 if (sc->need_mcsetup) 1604 fxp_mc_setup(sc); 1605 } 1606 /* 1607 * Try to start more packets transmitting. 1608 */ 1609 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1610 fxp_start_body(ifp); 1611 } 1612 1613 /* 1614 * Just return if nothing happened on the receive side. 1615 */ 1616 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1617 return; 1618 1619 /* 1620 * Process receiver interrupts. If a no-resource (RNR) 1621 * condition exists, get whatever packets we can and 1622 * re-start the receiver. 1623 * 1624 * When using polling, we do not process the list to completion, 1625 * so when we get an RNR interrupt we must defer the restart 1626 * until we hit the last buffer with the C bit set. 1627 * If we run out of cycles and rfa_headm has the C bit set, 1628 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1629 * that the info will be used in the subsequent polling cycle. 1630 */ 1631 for (;;) { 1632 rxp = sc->fxp_desc.rx_head; 1633 m = rxp->rx_mbuf; 1634 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1635 RFA_ALIGNMENT_FUDGE); 1636 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1637 BUS_DMASYNC_POSTREAD); 1638 1639#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1640 if (count >= 0 && count-- == 0) { 1641 if (rnr) { 1642 /* Defer RNR processing until the next time. */ 1643 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1644 rnr = 0; 1645 } 1646 break; 1647 } 1648#endif /* DEVICE_POLLING */ 1649 1650 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1651 break; 1652 1653 /* 1654 * Advance head forward. 1655 */ 1656 sc->fxp_desc.rx_head = rxp->rx_next; 1657 1658 /* 1659 * Add a new buffer to the receive chain. 1660 * If this fails, the old buffer is recycled 1661 * instead. 1662 */ 1663 fxp_rc = fxp_add_rfabuf(sc, rxp); 1664 if (fxp_rc == 0) { 1665 int total_len; 1666 1667 /* 1668 * Fetch packet length (the top 2 bits of 1669 * actual_size are flags set by the controller 1670 * upon completion), and drop the packet in case 1671 * of bogus length or CRC errors. 1672 */ 1673 total_len = le16toh(rfa->actual_size) & 0x3fff; 1674 if (total_len < sizeof(struct ether_header) || 1675 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1676 sc->rfa_size || 1677 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1678 m_freem(m); 1679 continue; 1680 } 1681 1682 /* Do IP checksum checking. */ 1683 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1684 if (rfa->rfax_csum_sts & 1685 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1686 m->m_pkthdr.csum_flags |= 1687 CSUM_IP_CHECKED; 1688 if (rfa->rfax_csum_sts & 1689 FXP_RFDX_CS_IP_CSUM_VALID) 1690 m->m_pkthdr.csum_flags |= 1691 CSUM_IP_VALID; 1692 if ((rfa->rfax_csum_sts & 1693 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1694 (rfa->rfax_csum_sts & 1695 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1696 m->m_pkthdr.csum_flags |= 1697 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1698 m->m_pkthdr.csum_data = 0xffff; 1699 } 1700 } 1701 1702 m->m_pkthdr.len = m->m_len = total_len; 1703 m->m_pkthdr.rcvif = ifp; 1704 1705 /* 1706 * Drop locks before calling if_input() since it 1707 * may re-enter fxp_start() in the netisr case. 1708 * This would result in a lock reversal. Better 1709 * performance might be obtained by chaining all 1710 * packets received, dropping the lock, and then 1711 * calling if_input() on each one. 1712 */ 1713 FXP_UNLOCK(sc); 1714 (*ifp->if_input)(ifp, m); 1715 FXP_LOCK(sc); 1716 } else if (fxp_rc == ENOBUFS) { 1717 rnr = 0; 1718 break; 1719 } 1720 } 1721 if (rnr) { 1722 fxp_scb_wait(sc); 1723 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1724 sc->fxp_desc.rx_head->rx_addr); 1725 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1726 } 1727} 1728 1729/* 1730 * Update packet in/out/collision statistics. The i82557 doesn't 1731 * allow you to access these counters without doing a fairly 1732 * expensive DMA to get _all_ of the statistics it maintains, so 1733 * we do this operation here only once per second. The statistics 1734 * counters in the kernel are updated from the previous dump-stats 1735 * DMA and then a new dump-stats DMA is started. The on-chip 1736 * counters are zeroed when the DMA completes. If we can't start 1737 * the DMA immediately, we don't wait - we just prepare to read 1738 * them again next time. 1739 */ 1740static void 1741fxp_tick(void *xsc) 1742{ 1743 struct fxp_softc *sc = xsc; 1744 struct ifnet *ifp = sc->ifp; 1745 struct fxp_stats *sp = sc->fxp_stats; 1746 1747 FXP_LOCK_ASSERT(sc, MA_OWNED); 1748 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1749 ifp->if_opackets += le32toh(sp->tx_good); 1750 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1751 if (sp->rx_good) { 1752 ifp->if_ipackets += le32toh(sp->rx_good); 1753 sc->rx_idle_secs = 0; 1754 } else { 1755 /* 1756 * Receiver's been idle for another second. 1757 */ 1758 sc->rx_idle_secs++; 1759 } 1760 ifp->if_ierrors += 1761 le32toh(sp->rx_crc_errors) + 1762 le32toh(sp->rx_alignment_errors) + 1763 le32toh(sp->rx_rnr_errors) + 1764 le32toh(sp->rx_overrun_errors); 1765 /* 1766 * If any transmit underruns occured, bump up the transmit 1767 * threshold by another 512 bytes (64 * 8). 1768 */ 1769 if (sp->tx_underruns) { 1770 ifp->if_oerrors += le32toh(sp->tx_underruns); 1771 if (tx_threshold < 192) 1772 tx_threshold += 64; 1773 } 1774 1775 /* 1776 * Release any xmit buffers that have completed DMA. This isn't 1777 * strictly necessary to do here, but it's advantagous for mbufs 1778 * with external storage to be released in a timely manner rather 1779 * than being defered for a potentially long time. This limits 1780 * the delay to a maximum of one second. 1781 */ 1782 fxp_txeof(sc); 1783 1784 /* 1785 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1786 * then assume the receiver has locked up and attempt to clear 1787 * the condition by reprogramming the multicast filter. This is 1788 * a work-around for a bug in the 82557 where the receiver locks 1789 * up if it gets certain types of garbage in the syncronization 1790 * bits prior to the packet header. This bug is supposed to only 1791 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1792 * mode as well (perhaps due to a 10/100 speed transition). 1793 */ 1794 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1795 sc->rx_idle_secs = 0; 1796 fxp_mc_setup(sc); 1797 } 1798 /* 1799 * If there is no pending command, start another stats 1800 * dump. Otherwise punt for now. 1801 */ 1802 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1803 /* 1804 * Start another stats dump. 1805 */ 1806 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1807 BUS_DMASYNC_PREREAD); 1808 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1809 } else { 1810 /* 1811 * A previous command is still waiting to be accepted. 1812 * Just zero our copy of the stats and wait for the 1813 * next timer event to update them. 1814 */ 1815 sp->tx_good = 0; 1816 sp->tx_underruns = 0; 1817 sp->tx_total_collisions = 0; 1818 1819 sp->rx_good = 0; 1820 sp->rx_crc_errors = 0; 1821 sp->rx_alignment_errors = 0; 1822 sp->rx_rnr_errors = 0; 1823 sp->rx_overrun_errors = 0; 1824 } 1825 if (sc->miibus != NULL) 1826 mii_tick(device_get_softc(sc->miibus)); 1827 1828 /* 1829 * Schedule another timeout one second from now. 1830 */ 1831 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1832} 1833 1834/* 1835 * Stop the interface. Cancels the statistics updater and resets 1836 * the interface. 1837 */ 1838static void 1839fxp_stop(struct fxp_softc *sc) 1840{ 1841 struct ifnet *ifp = sc->ifp; 1842 struct fxp_tx *txp; 1843 int i; 1844 1845 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1846 ifp->if_timer = 0; 1847 1848#ifdef DEVICE_POLLING 1849 ether_poll_deregister(ifp); 1850#endif 1851 /* 1852 * Cancel stats updater. 1853 */ 1854 callout_stop(&sc->stat_ch); 1855 1856 /* 1857 * Issue software reset, which also unloads the microcode. 1858 */ 1859 sc->flags &= ~FXP_FLAG_UCODE; 1860 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1861 DELAY(50); 1862 1863 /* 1864 * Release any xmit buffers. 1865 */ 1866 txp = sc->fxp_desc.tx_list; 1867 if (txp != NULL) { 1868 for (i = 0; i < FXP_NTXCB; i++) { 1869 if (txp[i].tx_mbuf != NULL) { 1870 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1871 BUS_DMASYNC_POSTWRITE); 1872 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1873 m_freem(txp[i].tx_mbuf); 1874 txp[i].tx_mbuf = NULL; 1875 /* clear this to reset csum offload bits */ 1876 txp[i].tx_cb->tbd[0].tb_addr = 0; 1877 } 1878 } 1879 } 1880 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1881 sc->tx_queued = 0; 1882} 1883 1884/* 1885 * Watchdog/transmission transmit timeout handler. Called when a 1886 * transmission is started on the interface, but no interrupt is 1887 * received before the timeout. This usually indicates that the 1888 * card has wedged for some reason. 1889 */ 1890static void 1891fxp_watchdog(struct ifnet *ifp) 1892{ 1893 struct fxp_softc *sc = ifp->if_softc; 1894 1895 FXP_LOCK(sc); 1896 device_printf(sc->dev, "device timeout\n"); 1897 ifp->if_oerrors++; 1898 1899 fxp_init_body(sc); 1900 FXP_UNLOCK(sc); 1901} 1902 1903/* 1904 * Acquire locks and then call the real initialization function. This 1905 * is necessary because ether_ioctl() calls if_init() and this would 1906 * result in mutex recursion if the mutex was held. 1907 */ 1908static void 1909fxp_init(void *xsc) 1910{ 1911 struct fxp_softc *sc = xsc; 1912 1913 FXP_LOCK(sc); 1914 fxp_init_body(sc); 1915 FXP_UNLOCK(sc); 1916} 1917 1918/* 1919 * Perform device initialization. This routine must be called with the 1920 * softc lock held. 1921 */ 1922static void 1923fxp_init_body(struct fxp_softc *sc) 1924{ 1925 struct ifnet *ifp = sc->ifp; 1926 struct fxp_cb_config *cbp; 1927 struct fxp_cb_ias *cb_ias; 1928 struct fxp_cb_tx *tcbp; 1929 struct fxp_tx *txp; 1930 struct fxp_cb_mcs *mcsp; 1931 int i, prm; 1932 1933 FXP_LOCK_ASSERT(sc, MA_OWNED); 1934 /* 1935 * Cancel any pending I/O 1936 */ 1937 fxp_stop(sc); 1938 1939 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1940 1941 /* 1942 * Initialize base of CBL and RFA memory. Loading with zero 1943 * sets it up for regular linear addressing. 1944 */ 1945 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1946 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1947 1948 fxp_scb_wait(sc); 1949 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1950 1951 /* 1952 * Initialize base of dump-stats buffer. 1953 */ 1954 fxp_scb_wait(sc); 1955 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1956 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1957 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1958 1959 /* 1960 * Attempt to load microcode if requested. 1961 */ 1962 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1963 fxp_load_ucode(sc); 1964 1965 /* 1966 * Initialize the multicast address list. 1967 */ 1968 if (fxp_mc_addrs(sc)) { 1969 mcsp = sc->mcsp; 1970 mcsp->cb_status = 0; 1971 mcsp->cb_command = 1972 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1973 mcsp->link_addr = 0xffffffff; 1974 /* 1975 * Start the multicast setup command. 1976 */ 1977 fxp_scb_wait(sc); 1978 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1979 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1980 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1981 /* ...and wait for it to complete. */ 1982 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1983 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1984 BUS_DMASYNC_POSTWRITE); 1985 } 1986 1987 /* 1988 * We temporarily use memory that contains the TxCB list to 1989 * construct the config CB. The TxCB list memory is rebuilt 1990 * later. 1991 */ 1992 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1993 1994 /* 1995 * This bcopy is kind of disgusting, but there are a bunch of must be 1996 * zero and must be one bits in this structure and this is the easiest 1997 * way to initialize them all to proper values. 1998 */ 1999 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2000 2001 cbp->cb_status = 0; 2002 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2003 FXP_CB_COMMAND_EL); 2004 cbp->link_addr = 0xffffffff; /* (no) next command */ 2005 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2006 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2007 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2008 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2009 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2010 cbp->type_enable = 0; /* actually reserved */ 2011 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2012 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2013 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2014 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2015 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2016 cbp->late_scb = 0; /* (don't) defer SCB update */ 2017 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2018 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2019 cbp->ci_int = 1; /* interrupt on CU idle */ 2020 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2021 cbp->ext_stats_dis = 1; /* disable extended counters */ 2022 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2023 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2024 cbp->disc_short_rx = !prm; /* discard short packets */ 2025 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2026 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2027 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2028 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2029 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2030 cbp->csma_dis = 0; /* (don't) disable link */ 2031 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2032 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2033 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2034 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2035 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2036 cbp->nsai = 1; /* (don't) disable source addr insert */ 2037 cbp->preamble_length = 2; /* (7 byte) preamble */ 2038 cbp->loopback = 0; /* (don't) loopback */ 2039 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2040 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2041 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2042 cbp->promiscuous = prm; /* promiscuous mode */ 2043 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2044 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2045 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2046 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2047 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2048 2049 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2050 cbp->padding = 1; /* (do) pad short tx packets */ 2051 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2052 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2053 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2054 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2055 /* must set wake_en in PMCSR also */ 2056 cbp->force_fdx = 0; /* (don't) force full duplex */ 2057 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2058 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2059 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2060 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2061 2062 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2063 /* 2064 * The 82557 has no hardware flow control, the values 2065 * below are the defaults for the chip. 2066 */ 2067 cbp->fc_delay_lsb = 0; 2068 cbp->fc_delay_msb = 0x40; 2069 cbp->pri_fc_thresh = 3; 2070 cbp->tx_fc_dis = 0; 2071 cbp->rx_fc_restop = 0; 2072 cbp->rx_fc_restart = 0; 2073 cbp->fc_filter = 0; 2074 cbp->pri_fc_loc = 1; 2075 } else { 2076 cbp->fc_delay_lsb = 0x1f; 2077 cbp->fc_delay_msb = 0x01; 2078 cbp->pri_fc_thresh = 3; 2079 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2080 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2081 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2082 cbp->fc_filter = !prm; /* drop FC frames to host */ 2083 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2084 } 2085 2086 /* 2087 * Start the config command/DMA. 2088 */ 2089 fxp_scb_wait(sc); 2090 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2091 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2092 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2093 /* ...and wait for it to complete. */ 2094 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2095 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2096 2097 /* 2098 * Now initialize the station address. Temporarily use the TxCB 2099 * memory area like we did above for the config CB. 2100 */ 2101 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2102 cb_ias->cb_status = 0; 2103 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2104 cb_ias->link_addr = 0xffffffff; 2105 bcopy(IFP2ENADDR(sc->ifp), cb_ias->macaddr, 2106 sizeof(IFP2ENADDR(sc->ifp))); 2107 2108 /* 2109 * Start the IAS (Individual Address Setup) command/DMA. 2110 */ 2111 fxp_scb_wait(sc); 2112 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2113 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2114 /* ...and wait for it to complete. */ 2115 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2116 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2117 2118 /* 2119 * Initialize transmit control block (TxCB) list. 2120 */ 2121 txp = sc->fxp_desc.tx_list; 2122 tcbp = sc->fxp_desc.cbl_list; 2123 bzero(tcbp, FXP_TXCB_SZ); 2124 for (i = 0; i < FXP_NTXCB; i++) { 2125 txp[i].tx_mbuf = NULL; 2126 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2127 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2128 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2129 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2130 if (sc->flags & FXP_FLAG_EXT_TXCB) 2131 tcbp[i].tbd_array_addr = 2132 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2133 else 2134 tcbp[i].tbd_array_addr = 2135 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2136 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2137 } 2138 /* 2139 * Set the suspend flag on the first TxCB and start the control 2140 * unit. It will execute the NOP and then suspend. 2141 */ 2142 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2143 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2144 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2145 sc->tx_queued = 1; 2146 2147 fxp_scb_wait(sc); 2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2149 2150 /* 2151 * Initialize receiver buffer area - RFA. 2152 */ 2153 fxp_scb_wait(sc); 2154 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2156 2157 /* 2158 * Set current media. 2159 */ 2160 if (sc->miibus != NULL) 2161 mii_mediachg(device_get_softc(sc->miibus)); 2162 2163 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2164 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2165 2166 /* 2167 * Enable interrupts. 2168 */ 2169#ifdef DEVICE_POLLING 2170 /* 2171 * ... but only do that if we are not polling. And because (presumably) 2172 * the default is interrupts on, we need to disable them explicitly! 2173 */ 2174 if ( ifp->if_flags & IFF_POLLING ) 2175 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2176 else 2177#endif /* DEVICE_POLLING */ 2178 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2179 2180 /* 2181 * Start stats updater. 2182 */ 2183 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2184} 2185 2186static int 2187fxp_serial_ifmedia_upd(struct ifnet *ifp) 2188{ 2189 2190 return (0); 2191} 2192 2193static void 2194fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2195{ 2196 2197 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2198} 2199 2200/* 2201 * Change media according to request. 2202 */ 2203static int 2204fxp_ifmedia_upd(struct ifnet *ifp) 2205{ 2206 struct fxp_softc *sc = ifp->if_softc; 2207 struct mii_data *mii; 2208 2209 mii = device_get_softc(sc->miibus); 2210 FXP_LOCK(sc); 2211 mii_mediachg(mii); 2212 FXP_UNLOCK(sc); 2213 return (0); 2214} 2215 2216/* 2217 * Notify the world which media we're using. 2218 */ 2219static void 2220fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2221{ 2222 struct fxp_softc *sc = ifp->if_softc; 2223 struct mii_data *mii; 2224 2225 mii = device_get_softc(sc->miibus); 2226 FXP_LOCK(sc); 2227 mii_pollstat(mii); 2228 ifmr->ifm_active = mii->mii_media_active; 2229 ifmr->ifm_status = mii->mii_media_status; 2230 2231 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2232 sc->cu_resume_bug = 1; 2233 else 2234 sc->cu_resume_bug = 0; 2235 FXP_UNLOCK(sc); 2236} 2237 2238/* 2239 * Add a buffer to the end of the RFA buffer list. 2240 * Return 0 if successful, 1 for failure. A failure results in 2241 * adding the 'oldm' (if non-NULL) on to the end of the list - 2242 * tossing out its old contents and recycling it. 2243 * The RFA struct is stuck at the beginning of mbuf cluster and the 2244 * data pointer is fixed up to point just past it. 2245 */ 2246static int 2247fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2248{ 2249 struct mbuf *m; 2250 struct fxp_rfa *rfa, *p_rfa; 2251 struct fxp_rx *p_rx; 2252 bus_dmamap_t tmp_map; 2253 int error; 2254 2255 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2256 if (m == NULL) 2257 return (ENOBUFS); 2258 2259 /* 2260 * Move the data pointer up so that the incoming data packet 2261 * will be 32-bit aligned. 2262 */ 2263 m->m_data += RFA_ALIGNMENT_FUDGE; 2264 2265 /* 2266 * Get a pointer to the base of the mbuf cluster and move 2267 * data start past it. 2268 */ 2269 rfa = mtod(m, struct fxp_rfa *); 2270 m->m_data += sc->rfa_size; 2271 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2272 2273 rfa->rfa_status = 0; 2274 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2275 rfa->actual_size = 0; 2276 2277 /* 2278 * Initialize the rest of the RFA. Note that since the RFA 2279 * is misaligned, we cannot store values directly. We're thus 2280 * using the le32enc() function which handles endianness and 2281 * is also alignment-safe. 2282 */ 2283 le32enc(&rfa->link_addr, 0xffffffff); 2284 le32enc(&rfa->rbd_addr, 0xffffffff); 2285 2286 /* Map the RFA into DMA memory. */ 2287 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2288 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2289 &rxp->rx_addr, 0); 2290 if (error) { 2291 m_freem(m); 2292 return (error); 2293 } 2294 2295 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2296 tmp_map = sc->spare_map; 2297 sc->spare_map = rxp->rx_map; 2298 rxp->rx_map = tmp_map; 2299 rxp->rx_mbuf = m; 2300 2301 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2302 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2303 2304 /* 2305 * If there are other buffers already on the list, attach this 2306 * one to the end by fixing up the tail to point to this one. 2307 */ 2308 if (sc->fxp_desc.rx_head != NULL) { 2309 p_rx = sc->fxp_desc.rx_tail; 2310 p_rfa = (struct fxp_rfa *) 2311 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2312 p_rx->rx_next = rxp; 2313 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2314 p_rfa->rfa_control = 0; 2315 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2316 BUS_DMASYNC_PREWRITE); 2317 } else { 2318 rxp->rx_next = NULL; 2319 sc->fxp_desc.rx_head = rxp; 2320 } 2321 sc->fxp_desc.rx_tail = rxp; 2322 return (0); 2323} 2324 2325static volatile int 2326fxp_miibus_readreg(device_t dev, int phy, int reg) 2327{ 2328 struct fxp_softc *sc = device_get_softc(dev); 2329 int count = 10000; 2330 int value; 2331 2332 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2333 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2334 2335 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2336 && count--) 2337 DELAY(10); 2338 2339 if (count <= 0) 2340 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2341 2342 return (value & 0xffff); 2343} 2344 2345static void 2346fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2347{ 2348 struct fxp_softc *sc = device_get_softc(dev); 2349 int count = 10000; 2350 2351 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2352 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2353 (value & 0xffff)); 2354 2355 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2356 count--) 2357 DELAY(10); 2358 2359 if (count <= 0) 2360 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2361} 2362 2363static int 2364fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2365{ 2366 struct fxp_softc *sc = ifp->if_softc; 2367 struct ifreq *ifr = (struct ifreq *)data; 2368 struct mii_data *mii; 2369 int flag, mask, error = 0; 2370 2371 switch (command) { 2372 case SIOCSIFFLAGS: 2373 FXP_LOCK(sc); 2374 if (ifp->if_flags & IFF_ALLMULTI) 2375 sc->flags |= FXP_FLAG_ALL_MCAST; 2376 else 2377 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2378 2379 /* 2380 * If interface is marked up and not running, then start it. 2381 * If it is marked down and running, stop it. 2382 * XXX If it's up then re-initialize it. This is so flags 2383 * such as IFF_PROMISC are handled. 2384 */ 2385 if (ifp->if_flags & IFF_UP) { 2386 fxp_init_body(sc); 2387 } else { 2388 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2389 fxp_stop(sc); 2390 } 2391 FXP_UNLOCK(sc); 2392 break; 2393 2394 case SIOCADDMULTI: 2395 case SIOCDELMULTI: 2396 FXP_LOCK(sc); 2397 if (ifp->if_flags & IFF_ALLMULTI) 2398 sc->flags |= FXP_FLAG_ALL_MCAST; 2399 else 2400 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2401 /* 2402 * Multicast list has changed; set the hardware filter 2403 * accordingly. 2404 */ 2405 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2406 fxp_mc_setup(sc); 2407 /* 2408 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2409 * again rather than else {}. 2410 */ 2411 if (sc->flags & FXP_FLAG_ALL_MCAST) 2412 fxp_init_body(sc); 2413 FXP_UNLOCK(sc); 2414 error = 0; 2415 break; 2416 2417 case SIOCSIFMEDIA: 2418 case SIOCGIFMEDIA: 2419 if (sc->miibus != NULL) { 2420 mii = device_get_softc(sc->miibus); 2421 error = ifmedia_ioctl(ifp, ifr, 2422 &mii->mii_media, command); 2423 } else { 2424 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2425 } 2426 break; 2427 2428 case SIOCSIFCAP: 2429 FXP_LOCK(sc); 2430 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2431 if (mask & IFCAP_POLLING) 2432 ifp->if_capenable ^= IFCAP_POLLING; 2433 if (mask & IFCAP_VLAN_MTU) { 2434 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2435 if (sc->revision != FXP_REV_82557) 2436 flag = FXP_FLAG_LONG_PKT_EN; 2437 else /* a hack to get long frames on the old chip */ 2438 flag = FXP_FLAG_SAVE_BAD; 2439 sc->flags ^= flag; 2440 if (ifp->if_flags & IFF_UP) 2441 fxp_init_body(sc); 2442 } 2443 FXP_UNLOCK(sc); 2444 break; 2445 2446 default: 2447 error = ether_ioctl(ifp, command, data); 2448 } 2449 return (error); 2450} 2451 2452/* 2453 * Fill in the multicast address list and return number of entries. 2454 */ 2455static int 2456fxp_mc_addrs(struct fxp_softc *sc) 2457{ 2458 struct fxp_cb_mcs *mcsp = sc->mcsp; 2459 struct ifnet *ifp = sc->ifp; 2460 struct ifmultiaddr *ifma; 2461 int nmcasts; 2462 2463 nmcasts = 0; 2464 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2465 IF_ADDR_LOCK(ifp); 2466 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2467 if (ifma->ifma_addr->sa_family != AF_LINK) 2468 continue; 2469 if (nmcasts >= MAXMCADDR) { 2470 sc->flags |= FXP_FLAG_ALL_MCAST; 2471 nmcasts = 0; 2472 break; 2473 } 2474 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2475 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2476 nmcasts++; 2477 } 2478 IF_ADDR_UNLOCK(ifp); 2479 } 2480 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2481 return (nmcasts); 2482} 2483 2484/* 2485 * Program the multicast filter. 2486 * 2487 * We have an artificial restriction that the multicast setup command 2488 * must be the first command in the chain, so we take steps to ensure 2489 * this. By requiring this, it allows us to keep up the performance of 2490 * the pre-initialized command ring (esp. link pointers) by not actually 2491 * inserting the mcsetup command in the ring - i.e. its link pointer 2492 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2493 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2494 * lead into the regular TxCB ring when it completes. 2495 * 2496 * This function must be called at splimp. 2497 */ 2498static void 2499fxp_mc_setup(struct fxp_softc *sc) 2500{ 2501 struct fxp_cb_mcs *mcsp = sc->mcsp; 2502 struct ifnet *ifp = sc->ifp; 2503 struct fxp_tx *txp; 2504 int count; 2505 2506 FXP_LOCK_ASSERT(sc, MA_OWNED); 2507 /* 2508 * If there are queued commands, we must wait until they are all 2509 * completed. If we are already waiting, then add a NOP command 2510 * with interrupt option so that we're notified when all commands 2511 * have been completed - fxp_start() ensures that no additional 2512 * TX commands will be added when need_mcsetup is true. 2513 */ 2514 if (sc->tx_queued) { 2515 /* 2516 * need_mcsetup will be true if we are already waiting for the 2517 * NOP command to be completed (see below). In this case, bail. 2518 */ 2519 if (sc->need_mcsetup) 2520 return; 2521 sc->need_mcsetup = 1; 2522 2523 /* 2524 * Add a NOP command with interrupt so that we are notified 2525 * when all TX commands have been processed. 2526 */ 2527 txp = sc->fxp_desc.tx_last->tx_next; 2528 txp->tx_mbuf = NULL; 2529 txp->tx_cb->cb_status = 0; 2530 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2531 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2532 /* 2533 * Advance the end of list forward. 2534 */ 2535 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2536 htole16(~FXP_CB_COMMAND_S); 2537 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2538 sc->fxp_desc.tx_last = txp; 2539 sc->tx_queued++; 2540 /* 2541 * Issue a resume in case the CU has just suspended. 2542 */ 2543 fxp_scb_wait(sc); 2544 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2545 /* 2546 * Set a 5 second timer just in case we don't hear from the 2547 * card again. 2548 */ 2549 ifp->if_timer = 5; 2550 2551 return; 2552 } 2553 sc->need_mcsetup = 0; 2554 2555 /* 2556 * Initialize multicast setup descriptor. 2557 */ 2558 mcsp->cb_status = 0; 2559 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2560 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2561 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2562 txp = &sc->fxp_desc.mcs_tx; 2563 txp->tx_mbuf = NULL; 2564 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2565 txp->tx_next = sc->fxp_desc.tx_list; 2566 (void) fxp_mc_addrs(sc); 2567 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2568 sc->tx_queued = 1; 2569 2570 /* 2571 * Wait until command unit is not active. This should never 2572 * be the case when nothing is queued, but make sure anyway. 2573 */ 2574 count = 100; 2575 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2576 FXP_SCB_CUS_ACTIVE && --count) 2577 DELAY(10); 2578 if (count == 0) { 2579 device_printf(sc->dev, "command queue timeout\n"); 2580 return; 2581 } 2582 2583 /* 2584 * Start the multicast setup command. 2585 */ 2586 fxp_scb_wait(sc); 2587 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2588 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2589 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2590 2591 ifp->if_timer = 2; 2592 return; 2593} 2594 2595static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2596static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2597static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2598static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2599static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2600static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2601static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2602 2603#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2604 2605struct ucode { 2606 uint32_t revision; 2607 uint32_t *ucode; 2608 int length; 2609 u_short int_delay_offset; 2610 u_short bundle_max_offset; 2611} ucode_table[] = { 2612 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2613 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2614 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2615 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2616 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2617 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2618 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2619 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2620 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2621 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2622 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2623 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2624 { 0, NULL, 0, 0, 0 } 2625}; 2626 2627static void 2628fxp_load_ucode(struct fxp_softc *sc) 2629{ 2630 struct ucode *uc; 2631 struct fxp_cb_ucode *cbp; 2632 int i; 2633 2634 for (uc = ucode_table; uc->ucode != NULL; uc++) 2635 if (sc->revision == uc->revision) 2636 break; 2637 if (uc->ucode == NULL) 2638 return; 2639 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2640 cbp->cb_status = 0; 2641 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2642 cbp->link_addr = 0xffffffff; /* (no) next command */ 2643 for (i = 0; i < uc->length; i++) 2644 cbp->ucode[i] = htole32(uc->ucode[i]); 2645 if (uc->int_delay_offset) 2646 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2647 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2648 if (uc->bundle_max_offset) 2649 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2650 htole16(sc->tunable_bundle_max); 2651 /* 2652 * Download the ucode to the chip. 2653 */ 2654 fxp_scb_wait(sc); 2655 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2656 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2657 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2658 /* ...and wait for it to complete. */ 2659 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2660 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2661 device_printf(sc->dev, 2662 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2663 sc->tunable_int_delay, 2664 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2665 sc->flags |= FXP_FLAG_UCODE; 2666} 2667 2668static int 2669sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2670{ 2671 int error, value; 2672 2673 value = *(int *)arg1; 2674 error = sysctl_handle_int(oidp, &value, 0, req); 2675 if (error || !req->newptr) 2676 return (error); 2677 if (value < low || value > high) 2678 return (EINVAL); 2679 *(int *)arg1 = value; 2680 return (0); 2681} 2682 2683/* 2684 * Interrupt delay is expressed in microseconds, a multiplier is used 2685 * to convert this to the appropriate clock ticks before using. 2686 */ 2687static int 2688sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2689{ 2690 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2691} 2692 2693static int 2694sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2695{ 2696 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2697} 2698