if_fxp.c revision 147269
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 147269 2005-06-10 20:42:02Z brooks $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194}; 195 196#ifdef FXP_IP_CSUM_WAR 197#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198#else 199#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200#endif 201 202static int fxp_probe(device_t dev); 203static int fxp_attach(device_t dev); 204static int fxp_detach(device_t dev); 205static int fxp_shutdown(device_t dev); 206static int fxp_suspend(device_t dev); 207static int fxp_resume(device_t dev); 208 209static void fxp_intr(void *xsc); 210static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212static void fxp_init(void *xsc); 213static void fxp_init_body(struct fxp_softc *sc); 214static void fxp_tick(void *xsc); 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218static void fxp_stop(struct fxp_softc *sc); 219static void fxp_release(struct fxp_softc *sc); 220static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222static void fxp_watchdog(struct ifnet *ifp); 223static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225static int fxp_mc_addrs(struct fxp_softc *sc); 226static void fxp_mc_setup(struct fxp_softc *sc); 227static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231static void fxp_autosize_eeprom(struct fxp_softc *sc); 232static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236static int fxp_ifmedia_upd(struct ifnet *ifp); 237static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245static void fxp_load_ucode(struct fxp_softc *sc); 246static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250static void fxp_scb_wait(struct fxp_softc *sc); 251static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270}; 271 272static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276}; 277 278static devclass_t fxp_devclass; 279 280DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284/* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288static void 289fxp_scb_wait(struct fxp_softc *sc) 290{ 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301} 302 303static void 304fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305{ 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312} 313 314static void 315fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317{ 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327} 328 329/* 330 * Return identification string if this device is ours. 331 */ 332static int 333fxp_probe(device_t dev) 334{ 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351} 352 353static void 354fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355{ 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 u_char eaddr[ETHER_ADDR_LEN]; 377 int i, rid, m1, m2, prefer_iomap; 378 int error, s; 379 380 error = 0; 381 sc = device_get_softc(dev); 382 sc->dev = dev; 383 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 384 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF); 386 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 387 fxp_serial_ifmedia_sts); 388 389 s = splimp(); 390 391 /* 392 * Enable bus mastering. 393 */ 394 pci_enable_busmaster(dev); 395 val = pci_read_config(dev, PCIR_COMMAND, 2); 396 397 /* 398 * Figure out which we should try first - memory mapping or i/o mapping? 399 * We default to memory mapping. Then we accept an override from the 400 * command line. Then we check to see which one is enabled. 401 */ 402 m1 = PCIM_CMD_MEMEN; 403 m2 = PCIM_CMD_PORTEN; 404 prefer_iomap = 0; 405 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 406 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 407 m1 = PCIM_CMD_PORTEN; 408 m2 = PCIM_CMD_MEMEN; 409 } 410 411 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 413 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 414 if (sc->mem == NULL) { 415 sc->rtp = 416 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 417 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 418 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 419 RF_ACTIVE); 420 } 421 422 if (!sc->mem) { 423 error = ENXIO; 424 goto fail; 425 } 426 if (bootverbose) { 427 device_printf(dev, "using %s space register mapping\n", 428 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 429 } 430 431 sc->sc_st = rman_get_bustag(sc->mem); 432 sc->sc_sh = rman_get_bushandle(sc->mem); 433 434 /* 435 * Allocate our interrupt. 436 */ 437 rid = 0; 438 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 439 RF_SHAREABLE | RF_ACTIVE); 440 if (sc->irq == NULL) { 441 device_printf(dev, "could not map interrupt\n"); 442 error = ENXIO; 443 goto fail; 444 } 445 446 /* 447 * Reset to a stable state. 448 */ 449 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 450 DELAY(10); 451 452 /* 453 * Find out how large of an SEEPROM we have. 454 */ 455 fxp_autosize_eeprom(sc); 456 457 /* 458 * Find out the chip revision; lump all 82557 revs together. 459 */ 460 fxp_read_eeprom(sc, &data, 5, 1); 461 if ((data >> 8) == 1) 462 sc->revision = FXP_REV_82557; 463 else 464 sc->revision = pci_get_revid(dev); 465 466 /* 467 * Determine whether we must use the 503 serial interface. 468 */ 469 fxp_read_eeprom(sc, &data, 6, 1); 470 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 471 && (data & FXP_PHY_SERIAL_ONLY)) 472 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 473 474 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 476 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 477 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 478 "FXP driver receive interrupt microcode bundling delay"); 479 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 480 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 481 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 482 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 483 "FXP driver receive interrupt microcode bundle size limit"); 484 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 485 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 486 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 487 "FXP RNR events"); 488 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 489 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 490 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 491 "FXP flow control disabled"); 492 493 /* 494 * Pull in device tunables. 495 */ 496 sc->tunable_int_delay = TUNABLE_INT_DELAY; 497 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 498 sc->tunable_noflow = 1; 499 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 500 "int_delay", &sc->tunable_int_delay); 501 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 502 "bundle_max", &sc->tunable_bundle_max); 503 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 504 "noflow", &sc->tunable_noflow); 505 sc->rnr = 0; 506 507 /* 508 * Enable workarounds for certain chip revision deficiencies. 509 * 510 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 511 * some systems based a normal 82559 design, have a defect where 512 * the chip can cause a PCI protocol violation if it receives 513 * a CU_RESUME command when it is entering the IDLE state. The 514 * workaround is to disable Dynamic Standby Mode, so the chip never 515 * deasserts CLKRUN#, and always remains in an active state. 516 * 517 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 518 */ 519 i = pci_get_device(dev); 520 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 521 sc->revision >= FXP_REV_82559_A0) { 522 fxp_read_eeprom(sc, &data, 10, 1); 523 if (data & 0x02) { /* STB enable */ 524 uint16_t cksum; 525 int i; 526 527 device_printf(dev, 528 "Disabling dynamic standby mode in EEPROM\n"); 529 data &= ~0x02; 530 fxp_write_eeprom(sc, &data, 10, 1); 531 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 532 cksum = 0; 533 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 534 fxp_read_eeprom(sc, &data, i, 1); 535 cksum += data; 536 } 537 i = (1 << sc->eeprom_size) - 1; 538 cksum = 0xBABA - cksum; 539 fxp_read_eeprom(sc, &data, i, 1); 540 fxp_write_eeprom(sc, &cksum, i, 1); 541 device_printf(dev, 542 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 543 i, data, cksum); 544#if 1 545 /* 546 * If the user elects to continue, try the software 547 * workaround, as it is better than nothing. 548 */ 549 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 550#endif 551 } 552 } 553 554 /* 555 * If we are not a 82557 chip, we can enable extended features. 556 */ 557 if (sc->revision != FXP_REV_82557) { 558 /* 559 * If MWI is enabled in the PCI configuration, and there 560 * is a valid cacheline size (8 or 16 dwords), then tell 561 * the board to turn on MWI. 562 */ 563 if (val & PCIM_CMD_MWRICEN && 564 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 565 sc->flags |= FXP_FLAG_MWI_ENABLE; 566 567 /* turn on the extended TxCB feature */ 568 sc->flags |= FXP_FLAG_EXT_TXCB; 569 570 /* enable reception of long frames for VLAN */ 571 sc->flags |= FXP_FLAG_LONG_PKT_EN; 572 } else { 573 /* a hack to get long VLAN frames on a 82557 */ 574 sc->flags |= FXP_FLAG_SAVE_BAD; 575 } 576 577 /* 578 * Enable use of extended RFDs and TCBs for 82550 579 * and later chips. Note: we need extended TXCB support 580 * too, but that's already enabled by the code above. 581 * Be careful to do this only on the right devices. 582 */ 583 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 584 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 585 || sc->revision == FXP_REV_82551_10) { 586 sc->rfa_size = sizeof (struct fxp_rfa); 587 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 588 sc->flags |= FXP_FLAG_EXT_RFA; 589 } else { 590 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 591 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 592 } 593 594 /* 595 * Allocate DMA tags and DMA safe memory. 596 */ 597 sc->maxtxseg = FXP_NTXSEG; 598 if (sc->flags & FXP_FLAG_EXT_RFA) 599 sc->maxtxseg--; 600 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 601 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 602 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 603 &sc->fxp_mtag); 604 if (error) { 605 device_printf(dev, "could not allocate dma tag\n"); 606 goto fail; 607 } 608 609 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 610 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 611 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 612 &sc->fxp_stag); 613 if (error) { 614 device_printf(dev, "could not allocate dma tag\n"); 615 goto fail; 616 } 617 618 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 619 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 620 if (error) 621 goto fail; 622 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 623 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 624 if (error) { 625 device_printf(dev, "could not map the stats buffer\n"); 626 goto fail; 627 } 628 629 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 630 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 631 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 632 if (error) { 633 device_printf(dev, "could not allocate dma tag\n"); 634 goto fail; 635 } 636 637 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 638 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 639 if (error) 640 goto fail; 641 642 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 643 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 644 &sc->fxp_desc.cbl_addr, 0); 645 if (error) { 646 device_printf(dev, "could not map DMA memory\n"); 647 goto fail; 648 } 649 650 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 651 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 652 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 653 &sc->mcs_tag); 654 if (error) { 655 device_printf(dev, "could not allocate dma tag\n"); 656 goto fail; 657 } 658 659 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 660 BUS_DMA_NOWAIT, &sc->mcs_map); 661 if (error) 662 goto fail; 663 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 664 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 665 if (error) { 666 device_printf(dev, "can't map the multicast setup command\n"); 667 goto fail; 668 } 669 670 /* 671 * Pre-allocate the TX DMA maps and setup the pointers to 672 * the TX command blocks. 673 */ 674 txp = sc->fxp_desc.tx_list; 675 tcbp = sc->fxp_desc.cbl_list; 676 for (i = 0; i < FXP_NTXCB; i++) { 677 txp[i].tx_cb = tcbp + i; 678 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 679 if (error) { 680 device_printf(dev, "can't create DMA map for TX\n"); 681 goto fail; 682 } 683 } 684 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 685 if (error) { 686 device_printf(dev, "can't create spare DMA map\n"); 687 goto fail; 688 } 689 690 /* 691 * Pre-allocate our receive buffers. 692 */ 693 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 694 for (i = 0; i < FXP_NRFABUFS; i++) { 695 rxp = &sc->fxp_desc.rx_list[i]; 696 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 697 if (error) { 698 device_printf(dev, "can't create DMA map for RX\n"); 699 goto fail; 700 } 701 if (fxp_add_rfabuf(sc, rxp) != 0) { 702 error = ENOMEM; 703 goto fail; 704 } 705 } 706 707 /* 708 * Read MAC address. 709 */ 710 fxp_read_eeprom(sc, myea, 0, 3); 711 eaddr[0] = myea[0] & 0xff; 712 eaddr[1] = myea[0] >> 8; 713 eaddr[2] = myea[1] & 0xff; 714 eaddr[3] = myea[1] >> 8; 715 eaddr[4] = myea[2] & 0xff; 716 eaddr[5] = myea[2] >> 8; 717 if (bootverbose) { 718 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 719 pci_get_vendor(dev), pci_get_device(dev), 720 pci_get_subvendor(dev), pci_get_subdevice(dev), 721 pci_get_revid(dev)); 722 fxp_read_eeprom(sc, &data, 10, 1); 723 device_printf(dev, "Dynamic Standby mode is %s\n", 724 data & 0x02 ? "enabled" : "disabled"); 725 } 726 727 /* 728 * If this is only a 10Mbps device, then there is no MII, and 729 * the PHY will use a serial interface instead. 730 * 731 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 732 * doesn't have a programming interface of any sort. The 733 * media is sensed automatically based on how the link partner 734 * is configured. This is, in essence, manual configuration. 735 */ 736 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 737 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 738 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 739 } else { 740 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 741 fxp_ifmedia_sts)) { 742 device_printf(dev, "MII without any PHY!\n"); 743 error = ENXIO; 744 goto fail; 745 } 746 } 747 748 ifp = sc->ifp = if_alloc(IFT_ETHER); 749 if (ifp == NULL) { 750 device_printf(dev, "can not if_alloc()\n"); 751 error = ENOSPC; 752 goto fail; 753 } 754 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 755 ifp->if_baudrate = 100000000; 756 ifp->if_init = fxp_init; 757 ifp->if_softc = sc; 758 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 759 ifp->if_ioctl = fxp_ioctl; 760 ifp->if_start = fxp_start; 761 ifp->if_watchdog = fxp_watchdog; 762 763 ifp->if_capabilities = ifp->if_capenable = 0; 764 765 /* Enable checksum offload for 82550 or better chips */ 766 if (sc->flags & FXP_FLAG_EXT_RFA) { 767 ifp->if_hwassist = FXP_CSUM_FEATURES; 768 ifp->if_capabilities |= IFCAP_HWCSUM; 769 ifp->if_capenable |= IFCAP_HWCSUM; 770 } 771 772#ifdef DEVICE_POLLING 773 /* Inform the world we support polling. */ 774 ifp->if_capabilities |= IFCAP_POLLING; 775 ifp->if_capenable |= IFCAP_POLLING; 776#endif 777 778 /* 779 * Attach the interface. 780 */ 781 ether_ifattach(ifp, eaddr); 782 783 /* 784 * Tell the upper layer(s) we support long frames. 785 * Must appear after the call to ether_ifattach() because 786 * ether_ifattach() sets ifi_hdrlen to the default value. 787 */ 788 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 789 ifp->if_capabilities |= IFCAP_VLAN_MTU; 790 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 791 792 /* 793 * Let the system queue as many packets as we have available 794 * TX descriptors. 795 */ 796 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 797 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 798 IFQ_SET_READY(&ifp->if_snd); 799 800 /* 801 * Hook our interrupt after all initialization is complete. 802 */ 803 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 804 fxp_intr, sc, &sc->ih); 805 if (error) { 806 device_printf(dev, "could not setup irq\n"); 807 ether_ifdetach(sc->ifp); 808 goto fail; 809 } 810 811fail: 812 splx(s); 813 if (error) 814 fxp_release(sc); 815 return (error); 816} 817 818/* 819 * Release all resources. The softc lock should not be held and the 820 * interrupt should already be torn down. 821 */ 822static void 823fxp_release(struct fxp_softc *sc) 824{ 825 struct fxp_rx *rxp; 826 struct fxp_tx *txp; 827 int i; 828 829 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 830 KASSERT(sc->ih == NULL, 831 ("fxp_release() called with intr handle still active")); 832 if (sc->miibus) 833 device_delete_child(sc->dev, sc->miibus); 834 bus_generic_detach(sc->dev); 835 ifmedia_removeall(&sc->sc_media); 836 if (sc->fxp_desc.cbl_list) { 837 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 838 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 839 sc->cbl_map); 840 } 841 if (sc->fxp_stats) { 842 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 843 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 844 } 845 if (sc->mcsp) { 846 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 847 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 848 } 849 if (sc->irq) 850 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 851 if (sc->mem) 852 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 853 if (sc->fxp_mtag) { 854 for (i = 0; i < FXP_NRFABUFS; i++) { 855 rxp = &sc->fxp_desc.rx_list[i]; 856 if (rxp->rx_mbuf != NULL) { 857 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 858 BUS_DMASYNC_POSTREAD); 859 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 860 m_freem(rxp->rx_mbuf); 861 } 862 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 863 } 864 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 865 for (i = 0; i < FXP_NTXCB; i++) { 866 txp = &sc->fxp_desc.tx_list[i]; 867 if (txp->tx_mbuf != NULL) { 868 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 869 BUS_DMASYNC_POSTWRITE); 870 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 871 m_freem(txp->tx_mbuf); 872 } 873 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 874 } 875 bus_dma_tag_destroy(sc->fxp_mtag); 876 } 877 if (sc->fxp_stag) 878 bus_dma_tag_destroy(sc->fxp_stag); 879 if (sc->cbl_tag) 880 bus_dma_tag_destroy(sc->cbl_tag); 881 if (sc->mcs_tag) 882 bus_dma_tag_destroy(sc->mcs_tag); 883 if (sc->ifp) 884 if_free(sc->ifp); 885 886 mtx_destroy(&sc->sc_mtx); 887} 888 889/* 890 * Detach interface. 891 */ 892static int 893fxp_detach(device_t dev) 894{ 895 struct fxp_softc *sc = device_get_softc(dev); 896 int s; 897 898 FXP_LOCK(sc); 899 s = splimp(); 900 901 sc->suspended = 1; /* Do same thing as we do for suspend */ 902 /* 903 * Close down routes etc. 904 */ 905 ether_ifdetach(sc->ifp); 906 907 /* 908 * Stop DMA and drop transmit queue, but disable interrupts first. 909 */ 910 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 911 fxp_stop(sc); 912 FXP_UNLOCK(sc); 913 914 /* 915 * Unhook interrupt before dropping lock. This is to prevent 916 * races with fxp_intr(). 917 */ 918 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 919 sc->ih = NULL; 920 921 splx(s); 922 923 /* Release our allocated resources. */ 924 fxp_release(sc); 925 return (0); 926} 927 928/* 929 * Device shutdown routine. Called at system shutdown after sync. The 930 * main purpose of this routine is to shut off receiver DMA so that 931 * kernel memory doesn't get clobbered during warmboot. 932 */ 933static int 934fxp_shutdown(device_t dev) 935{ 936 /* 937 * Make sure that DMA is disabled prior to reboot. Not doing 938 * do could allow DMA to corrupt kernel memory during the 939 * reboot before the driver initializes. 940 */ 941 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 942 return (0); 943} 944 945/* 946 * Device suspend routine. Stop the interface and save some PCI 947 * settings in case the BIOS doesn't restore them properly on 948 * resume. 949 */ 950static int 951fxp_suspend(device_t dev) 952{ 953 struct fxp_softc *sc = device_get_softc(dev); 954 int s; 955 956 FXP_LOCK(sc); 957 s = splimp(); 958 959 fxp_stop(sc); 960 961 sc->suspended = 1; 962 963 FXP_UNLOCK(sc); 964 splx(s); 965 return (0); 966} 967 968/* 969 * Device resume routine. re-enable busmastering, and restart the interface if 970 * appropriate. 971 */ 972static int 973fxp_resume(device_t dev) 974{ 975 struct fxp_softc *sc = device_get_softc(dev); 976 struct ifnet *ifp = sc->ifp; 977 uint16_t pci_command; 978 int s; 979 980 FXP_LOCK(sc); 981 s = splimp(); 982 983 /* reenable busmastering */ 984 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 985 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 986 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 987 988 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 989 DELAY(10); 990 991 /* reinitialize interface if necessary */ 992 if (ifp->if_flags & IFF_UP) 993 fxp_init_body(sc); 994 995 sc->suspended = 0; 996 997 FXP_UNLOCK(sc); 998 splx(s); 999 return (0); 1000} 1001 1002static void 1003fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1004{ 1005 uint16_t reg; 1006 int x; 1007 1008 /* 1009 * Shift in data. 1010 */ 1011 for (x = 1 << (length - 1); x; x >>= 1) { 1012 if (data & x) 1013 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1014 else 1015 reg = FXP_EEPROM_EECS; 1016 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1017 DELAY(1); 1018 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1019 DELAY(1); 1020 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1021 DELAY(1); 1022 } 1023} 1024 1025/* 1026 * Read from the serial EEPROM. Basically, you manually shift in 1027 * the read opcode (one bit at a time) and then shift in the address, 1028 * and then you shift out the data (all of this one bit at a time). 1029 * The word size is 16 bits, so you have to provide the address for 1030 * every 16 bits of data. 1031 */ 1032static uint16_t 1033fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1034{ 1035 uint16_t reg, data; 1036 int x; 1037 1038 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1039 /* 1040 * Shift in read opcode. 1041 */ 1042 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1043 /* 1044 * Shift in address. 1045 */ 1046 data = 0; 1047 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1048 if (offset & x) 1049 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1050 else 1051 reg = FXP_EEPROM_EECS; 1052 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1053 DELAY(1); 1054 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1055 DELAY(1); 1056 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1057 DELAY(1); 1058 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1059 data++; 1060 if (autosize && reg == 0) { 1061 sc->eeprom_size = data; 1062 break; 1063 } 1064 } 1065 /* 1066 * Shift out data. 1067 */ 1068 data = 0; 1069 reg = FXP_EEPROM_EECS; 1070 for (x = 1 << 15; x; x >>= 1) { 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1072 DELAY(1); 1073 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1074 data |= x; 1075 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1076 DELAY(1); 1077 } 1078 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1079 DELAY(1); 1080 1081 return (data); 1082} 1083 1084static void 1085fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1086{ 1087 int i; 1088 1089 /* 1090 * Erase/write enable. 1091 */ 1092 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1093 fxp_eeprom_shiftin(sc, 0x4, 3); 1094 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1096 DELAY(1); 1097 /* 1098 * Shift in write opcode, address, data. 1099 */ 1100 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1101 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1102 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1103 fxp_eeprom_shiftin(sc, data, 16); 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1105 DELAY(1); 1106 /* 1107 * Wait for EEPROM to finish up. 1108 */ 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1110 DELAY(1); 1111 for (i = 0; i < 1000; i++) { 1112 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1113 break; 1114 DELAY(50); 1115 } 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1117 DELAY(1); 1118 /* 1119 * Erase/write disable. 1120 */ 1121 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1122 fxp_eeprom_shiftin(sc, 0x4, 3); 1123 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1125 DELAY(1); 1126} 1127 1128/* 1129 * From NetBSD: 1130 * 1131 * Figure out EEPROM size. 1132 * 1133 * 559's can have either 64-word or 256-word EEPROMs, the 558 1134 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1135 * talks about the existance of 16 to 256 word EEPROMs. 1136 * 1137 * The only known sizes are 64 and 256, where the 256 version is used 1138 * by CardBus cards to store CIS information. 1139 * 1140 * The address is shifted in msb-to-lsb, and after the last 1141 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1142 * after which follows the actual data. We try to detect this zero, by 1143 * probing the data-out bit in the EEPROM control register just after 1144 * having shifted in a bit. If the bit is zero, we assume we've 1145 * shifted enough address bits. The data-out should be tri-state, 1146 * before this, which should translate to a logical one. 1147 */ 1148static void 1149fxp_autosize_eeprom(struct fxp_softc *sc) 1150{ 1151 1152 /* guess maximum size of 256 words */ 1153 sc->eeprom_size = 8; 1154 1155 /* autosize */ 1156 (void) fxp_eeprom_getword(sc, 0, 1); 1157} 1158 1159static void 1160fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1161{ 1162 int i; 1163 1164 for (i = 0; i < words; i++) 1165 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1166} 1167 1168static void 1169fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1170{ 1171 int i; 1172 1173 for (i = 0; i < words; i++) 1174 fxp_eeprom_putword(sc, offset + i, data[i]); 1175} 1176 1177/* 1178 * Grab the softc lock and call the real fxp_start_body() routine 1179 */ 1180static void 1181fxp_start(struct ifnet *ifp) 1182{ 1183 struct fxp_softc *sc = ifp->if_softc; 1184 1185 FXP_LOCK(sc); 1186 fxp_start_body(ifp); 1187 FXP_UNLOCK(sc); 1188} 1189 1190/* 1191 * Start packet transmission on the interface. 1192 * This routine must be called with the softc lock held, and is an 1193 * internal entry point only. 1194 */ 1195static void 1196fxp_start_body(struct ifnet *ifp) 1197{ 1198 struct fxp_softc *sc = ifp->if_softc; 1199 struct mbuf *mb_head; 1200 int error, txqueued; 1201 1202 FXP_LOCK_ASSERT(sc, MA_OWNED); 1203 1204 /* 1205 * See if we need to suspend xmit until the multicast filter 1206 * has been reprogrammed (which can only be done at the head 1207 * of the command chain). 1208 */ 1209 if (sc->need_mcsetup) 1210 return; 1211 1212 /* 1213 * We're finished if there is nothing more to add to the list or if 1214 * we're all filled up with buffers to transmit. 1215 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1216 * a NOP command when needed. 1217 */ 1218 txqueued = 0; 1219 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1220 sc->tx_queued < FXP_NTXCB - 1) { 1221 1222 /* 1223 * Grab a packet to transmit. 1224 */ 1225 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1226 if (mb_head == NULL) 1227 break; 1228 1229 error = fxp_encap(sc, mb_head); 1230 if (error) 1231 break; 1232 txqueued = 1; 1233 } 1234 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1235 1236 /* 1237 * We're finished. If we added to the list, issue a RESUME to get DMA 1238 * going again if suspended. 1239 */ 1240 if (txqueued) { 1241 fxp_scb_wait(sc); 1242 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1243 } 1244} 1245 1246static int 1247fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1248{ 1249 struct ifnet *ifp; 1250 struct mbuf *m; 1251 struct fxp_tx *txp; 1252 struct fxp_cb_tx *cbp; 1253 bus_dma_segment_t segs[FXP_NTXSEG]; 1254 int chainlen, error, i, nseg; 1255 1256 FXP_LOCK_ASSERT(sc, MA_OWNED); 1257 ifp = sc->ifp; 1258 1259 /* 1260 * Get pointer to next available tx desc. 1261 */ 1262 txp = sc->fxp_desc.tx_last->tx_next; 1263 1264 /* 1265 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1266 * Ethernet Controller Family Open Source Software 1267 * Developer Manual says: 1268 * Using software parsing is only allowed with legal 1269 * TCP/IP or UDP/IP packets. 1270 * ... 1271 * For all other datagrams, hardware parsing must 1272 * be used. 1273 * Software parsing appears to truncate ICMP and 1274 * fragmented UDP packets that contain one to three 1275 * bytes in the second (and final) mbuf of the packet. 1276 */ 1277 if (sc->flags & FXP_FLAG_EXT_RFA) 1278 txp->tx_cb->ipcb_ip_activation_high = 1279 FXP_IPCB_HARDWAREPARSING_ENABLE; 1280 1281 /* 1282 * Deal with TCP/IP checksum offload. Note that 1283 * in order for TCP checksum offload to work, 1284 * the pseudo header checksum must have already 1285 * been computed and stored in the checksum field 1286 * in the TCP header. The stack should have 1287 * already done this for us. 1288 */ 1289 if (m_head->m_pkthdr.csum_flags) { 1290 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1291 txp->tx_cb->ipcb_ip_schedule = 1292 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1293 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1294 txp->tx_cb->ipcb_ip_schedule |= 1295 FXP_IPCB_TCP_PACKET; 1296 } 1297 1298#ifdef FXP_IP_CSUM_WAR 1299 /* 1300 * XXX The 82550 chip appears to have trouble 1301 * dealing with IP header checksums in very small 1302 * datagrams, namely fragments from 1 to 3 bytes 1303 * in size. For example, say you want to transmit 1304 * a UDP packet of 1473 bytes. The packet will be 1305 * fragmented over two IP datagrams, the latter 1306 * containing only one byte of data. The 82550 will 1307 * botch the header checksum on the 1-byte fragment. 1308 * As long as the datagram contains 4 or more bytes 1309 * of data, you're ok. 1310 * 1311 * The following code attempts to work around this 1312 * problem: if the datagram is less than 38 bytes 1313 * in size (14 bytes ether header, 20 bytes IP header, 1314 * plus 4 bytes of data), we punt and compute the IP 1315 * header checksum by hand. This workaround doesn't 1316 * work very well, however, since it can be fooled 1317 * by things like VLAN tags and IP options that make 1318 * the header sizes/offsets vary. 1319 */ 1320 1321 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1322 if (m_head->m_pkthdr.len < 38) { 1323 struct ip *ip; 1324 m_head->m_data += ETHER_HDR_LEN; 1325 ip = mtod(mb_head, struct ip *); 1326 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1327 m_head->m_data -= ETHER_HDR_LEN; 1328 } else { 1329 txp->tx_cb->ipcb_ip_activation_high = 1330 FXP_IPCB_HARDWAREPARSING_ENABLE; 1331 txp->tx_cb->ipcb_ip_schedule |= 1332 FXP_IPCB_IP_CHECKSUM_ENABLE; 1333 } 1334 } 1335#endif 1336 } 1337 1338 chainlen = 0; 1339 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1340 chainlen++; 1341 if (chainlen > sc->maxtxseg) { 1342 struct mbuf *mn; 1343 1344 /* 1345 * We ran out of segments. We have to recopy this 1346 * mbuf chain first. Bail out if we can't get the 1347 * new buffers. 1348 */ 1349 mn = m_defrag(m_head, M_DONTWAIT); 1350 if (mn == NULL) { 1351 m_freem(m_head); 1352 return (-1); 1353 } else { 1354 m_head = mn; 1355 } 1356 } 1357 1358 /* 1359 * Go through each of the mbufs in the chain and initialize 1360 * the transmit buffer descriptors with the physical address 1361 * and size of the mbuf. 1362 */ 1363 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1364 m_head, segs, &nseg, 0); 1365 if (error) { 1366 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1367 m_freem(m_head); 1368 return (-1); 1369 } 1370 1371 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1372 1373 cbp = txp->tx_cb; 1374 for (i = 0; i < nseg; i++) { 1375 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1376 /* 1377 * If this is an 82550/82551, then we're using extended 1378 * TxCBs _and_ we're using checksum offload. This means 1379 * that the TxCB is really an IPCB. One major difference 1380 * between the two is that with plain extended TxCBs, 1381 * the bottom half of the TxCB contains two entries from 1382 * the TBD array, whereas IPCBs contain just one entry: 1383 * one entry (8 bytes) has been sacrificed for the TCP/IP 1384 * checksum offload control bits. So to make things work 1385 * right, we have to start filling in the TBD array 1386 * starting from a different place depending on whether 1387 * the chip is an 82550/82551 or not. 1388 */ 1389 if (sc->flags & FXP_FLAG_EXT_RFA) { 1390 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1391 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1392 } else { 1393 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1394 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1395 } 1396 } 1397 cbp->tbd_number = nseg; 1398 1399 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1400 txp->tx_mbuf = m_head; 1401 txp->tx_cb->cb_status = 0; 1402 txp->tx_cb->byte_count = 0; 1403 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1404 txp->tx_cb->cb_command = 1405 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1406 FXP_CB_COMMAND_S); 1407 } else { 1408 txp->tx_cb->cb_command = 1409 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1410 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1411 /* 1412 * Set a 5 second timer just in case we don't hear 1413 * from the card again. 1414 */ 1415 ifp->if_timer = 5; 1416 } 1417 txp->tx_cb->tx_threshold = tx_threshold; 1418 1419 /* 1420 * Advance the end of list forward. 1421 */ 1422 1423#ifdef __alpha__ 1424 /* 1425 * On platforms which can't access memory in 16-bit 1426 * granularities, we must prevent the card from DMA'ing 1427 * up the status while we update the command field. 1428 * This could cause us to overwrite the completion status. 1429 * XXX This is probably bogus and we're _not_ looking 1430 * for atomicity here. 1431 */ 1432 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1433 htole16(FXP_CB_COMMAND_S)); 1434#else 1435 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1436#endif /*__alpha__*/ 1437 sc->fxp_desc.tx_last = txp; 1438 1439 /* 1440 * Advance the beginning of the list forward if there are 1441 * no other packets queued (when nothing is queued, tx_first 1442 * sits on the last TxCB that was sent out). 1443 */ 1444 if (sc->tx_queued == 0) 1445 sc->fxp_desc.tx_first = txp; 1446 1447 sc->tx_queued++; 1448 1449 /* 1450 * Pass packet to bpf if there is a listener. 1451 */ 1452 BPF_MTAP(ifp, m_head); 1453 return (0); 1454} 1455 1456#ifdef DEVICE_POLLING 1457static poll_handler_t fxp_poll; 1458 1459static void 1460fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1461{ 1462 struct fxp_softc *sc = ifp->if_softc; 1463 uint8_t statack; 1464 1465 FXP_LOCK(sc); 1466 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1467 ether_poll_deregister(ifp); 1468 cmd = POLL_DEREGISTER; 1469 } 1470 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1471 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1472 FXP_UNLOCK(sc); 1473 return; 1474 } 1475 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1476 FXP_SCB_STATACK_FR; 1477 if (cmd == POLL_AND_CHECK_STATUS) { 1478 uint8_t tmp; 1479 1480 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1481 if (tmp == 0xff || tmp == 0) { 1482 FXP_UNLOCK(sc); 1483 return; /* nothing to do */ 1484 } 1485 tmp &= ~statack; 1486 /* ack what we can */ 1487 if (tmp != 0) 1488 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1489 statack |= tmp; 1490 } 1491 fxp_intr_body(sc, ifp, statack, count); 1492 FXP_UNLOCK(sc); 1493} 1494#endif /* DEVICE_POLLING */ 1495 1496/* 1497 * Process interface interrupts. 1498 */ 1499static void 1500fxp_intr(void *xsc) 1501{ 1502 struct fxp_softc *sc = xsc; 1503 struct ifnet *ifp = sc->ifp; 1504 uint8_t statack; 1505 1506 FXP_LOCK(sc); 1507 if (sc->suspended) { 1508 FXP_UNLOCK(sc); 1509 return; 1510 } 1511 1512#ifdef DEVICE_POLLING 1513 if (ifp->if_flags & IFF_POLLING) { 1514 FXP_UNLOCK(sc); 1515 return; 1516 } 1517 if ((ifp->if_capenable & IFCAP_POLLING) && 1518 ether_poll_register(fxp_poll, ifp)) { 1519 /* disable interrupts */ 1520 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1521 FXP_UNLOCK(sc); 1522 fxp_poll(ifp, 0, 1); 1523 return; 1524 } 1525#endif 1526 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1527 /* 1528 * It should not be possible to have all bits set; the 1529 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1530 * all bits are set, this may indicate that the card has 1531 * been physically ejected, so ignore it. 1532 */ 1533 if (statack == 0xff) { 1534 FXP_UNLOCK(sc); 1535 return; 1536 } 1537 1538 /* 1539 * First ACK all the interrupts in this pass. 1540 */ 1541 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1542 fxp_intr_body(sc, ifp, statack, -1); 1543 } 1544 FXP_UNLOCK(sc); 1545} 1546 1547static void 1548fxp_txeof(struct fxp_softc *sc) 1549{ 1550 struct fxp_tx *txp; 1551 1552 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1553 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1554 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1555 txp = txp->tx_next) { 1556 if (txp->tx_mbuf != NULL) { 1557 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1558 BUS_DMASYNC_POSTWRITE); 1559 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1560 m_freem(txp->tx_mbuf); 1561 txp->tx_mbuf = NULL; 1562 /* clear this to reset csum offload bits */ 1563 txp->tx_cb->tbd[0].tb_addr = 0; 1564 } 1565 sc->tx_queued--; 1566 } 1567 sc->fxp_desc.tx_first = txp; 1568 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1569} 1570 1571static void 1572fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1573 int count) 1574{ 1575 struct mbuf *m; 1576 struct fxp_rx *rxp; 1577 struct fxp_rfa *rfa; 1578 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1579 1580 FXP_LOCK_ASSERT(sc, MA_OWNED); 1581 if (rnr) 1582 sc->rnr++; 1583#ifdef DEVICE_POLLING 1584 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1585 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1586 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1587 rnr = 1; 1588 } 1589#endif 1590 1591 /* 1592 * Free any finished transmit mbuf chains. 1593 * 1594 * Handle the CNA event likt a CXTNO event. It used to 1595 * be that this event (control unit not ready) was not 1596 * encountered, but it is now with the SMPng modifications. 1597 * The exact sequence of events that occur when the interface 1598 * is brought up are different now, and if this event 1599 * goes unhandled, the configuration/rxfilter setup sequence 1600 * can stall for several seconds. The result is that no 1601 * packets go out onto the wire for about 5 to 10 seconds 1602 * after the interface is ifconfig'ed for the first time. 1603 */ 1604 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1605 fxp_txeof(sc); 1606 1607 ifp->if_timer = 0; 1608 if (sc->tx_queued == 0) { 1609 if (sc->need_mcsetup) 1610 fxp_mc_setup(sc); 1611 } 1612 /* 1613 * Try to start more packets transmitting. 1614 */ 1615 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1616 fxp_start_body(ifp); 1617 } 1618 1619 /* 1620 * Just return if nothing happened on the receive side. 1621 */ 1622 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1623 return; 1624 1625 /* 1626 * Process receiver interrupts. If a no-resource (RNR) 1627 * condition exists, get whatever packets we can and 1628 * re-start the receiver. 1629 * 1630 * When using polling, we do not process the list to completion, 1631 * so when we get an RNR interrupt we must defer the restart 1632 * until we hit the last buffer with the C bit set. 1633 * If we run out of cycles and rfa_headm has the C bit set, 1634 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1635 * that the info will be used in the subsequent polling cycle. 1636 */ 1637 for (;;) { 1638 rxp = sc->fxp_desc.rx_head; 1639 m = rxp->rx_mbuf; 1640 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1641 RFA_ALIGNMENT_FUDGE); 1642 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1643 BUS_DMASYNC_POSTREAD); 1644 1645#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1646 if (count >= 0 && count-- == 0) { 1647 if (rnr) { 1648 /* Defer RNR processing until the next time. */ 1649 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1650 rnr = 0; 1651 } 1652 break; 1653 } 1654#endif /* DEVICE_POLLING */ 1655 1656 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1657 break; 1658 1659 /* 1660 * Advance head forward. 1661 */ 1662 sc->fxp_desc.rx_head = rxp->rx_next; 1663 1664 /* 1665 * Add a new buffer to the receive chain. 1666 * If this fails, the old buffer is recycled 1667 * instead. 1668 */ 1669 if (fxp_add_rfabuf(sc, rxp) == 0) { 1670 int total_len; 1671 1672 /* 1673 * Fetch packet length (the top 2 bits of 1674 * actual_size are flags set by the controller 1675 * upon completion), and drop the packet in case 1676 * of bogus length or CRC errors. 1677 */ 1678 total_len = le16toh(rfa->actual_size) & 0x3fff; 1679 if (total_len < sizeof(struct ether_header) || 1680 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1681 sc->rfa_size || 1682 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1683 m_freem(m); 1684 continue; 1685 } 1686 1687 /* Do IP checksum checking. */ 1688 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1689 if (rfa->rfax_csum_sts & 1690 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1691 m->m_pkthdr.csum_flags |= 1692 CSUM_IP_CHECKED; 1693 if (rfa->rfax_csum_sts & 1694 FXP_RFDX_CS_IP_CSUM_VALID) 1695 m->m_pkthdr.csum_flags |= 1696 CSUM_IP_VALID; 1697 if ((rfa->rfax_csum_sts & 1698 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1699 (rfa->rfax_csum_sts & 1700 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1701 m->m_pkthdr.csum_flags |= 1702 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1703 m->m_pkthdr.csum_data = 0xffff; 1704 } 1705 } 1706 1707 m->m_pkthdr.len = m->m_len = total_len; 1708 m->m_pkthdr.rcvif = ifp; 1709 1710 /* 1711 * Drop locks before calling if_input() since it 1712 * may re-enter fxp_start() in the netisr case. 1713 * This would result in a lock reversal. Better 1714 * performance might be obtained by chaining all 1715 * packets received, dropping the lock, and then 1716 * calling if_input() on each one. 1717 */ 1718 FXP_UNLOCK(sc); 1719 (*ifp->if_input)(ifp, m); 1720 FXP_LOCK(sc); 1721 } 1722 } 1723 if (rnr) { 1724 fxp_scb_wait(sc); 1725 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1726 sc->fxp_desc.rx_head->rx_addr); 1727 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1728 } 1729} 1730 1731/* 1732 * Update packet in/out/collision statistics. The i82557 doesn't 1733 * allow you to access these counters without doing a fairly 1734 * expensive DMA to get _all_ of the statistics it maintains, so 1735 * we do this operation here only once per second. The statistics 1736 * counters in the kernel are updated from the previous dump-stats 1737 * DMA and then a new dump-stats DMA is started. The on-chip 1738 * counters are zeroed when the DMA completes. If we can't start 1739 * the DMA immediately, we don't wait - we just prepare to read 1740 * them again next time. 1741 */ 1742static void 1743fxp_tick(void *xsc) 1744{ 1745 struct fxp_softc *sc = xsc; 1746 struct ifnet *ifp = sc->ifp; 1747 struct fxp_stats *sp = sc->fxp_stats; 1748 int s; 1749 1750 FXP_LOCK(sc); 1751 s = splimp(); 1752 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1753 ifp->if_opackets += le32toh(sp->tx_good); 1754 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1755 if (sp->rx_good) { 1756 ifp->if_ipackets += le32toh(sp->rx_good); 1757 sc->rx_idle_secs = 0; 1758 } else { 1759 /* 1760 * Receiver's been idle for another second. 1761 */ 1762 sc->rx_idle_secs++; 1763 } 1764 ifp->if_ierrors += 1765 le32toh(sp->rx_crc_errors) + 1766 le32toh(sp->rx_alignment_errors) + 1767 le32toh(sp->rx_rnr_errors) + 1768 le32toh(sp->rx_overrun_errors); 1769 /* 1770 * If any transmit underruns occured, bump up the transmit 1771 * threshold by another 512 bytes (64 * 8). 1772 */ 1773 if (sp->tx_underruns) { 1774 ifp->if_oerrors += le32toh(sp->tx_underruns); 1775 if (tx_threshold < 192) 1776 tx_threshold += 64; 1777 } 1778 1779 /* 1780 * Release any xmit buffers that have completed DMA. This isn't 1781 * strictly necessary to do here, but it's advantagous for mbufs 1782 * with external storage to be released in a timely manner rather 1783 * than being defered for a potentially long time. This limits 1784 * the delay to a maximum of one second. 1785 */ 1786 fxp_txeof(sc); 1787 1788 /* 1789 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1790 * then assume the receiver has locked up and attempt to clear 1791 * the condition by reprogramming the multicast filter. This is 1792 * a work-around for a bug in the 82557 where the receiver locks 1793 * up if it gets certain types of garbage in the syncronization 1794 * bits prior to the packet header. This bug is supposed to only 1795 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1796 * mode as well (perhaps due to a 10/100 speed transition). 1797 */ 1798 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1799 sc->rx_idle_secs = 0; 1800 fxp_mc_setup(sc); 1801 } 1802 /* 1803 * If there is no pending command, start another stats 1804 * dump. Otherwise punt for now. 1805 */ 1806 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1807 /* 1808 * Start another stats dump. 1809 */ 1810 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1811 BUS_DMASYNC_PREREAD); 1812 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1813 } else { 1814 /* 1815 * A previous command is still waiting to be accepted. 1816 * Just zero our copy of the stats and wait for the 1817 * next timer event to update them. 1818 */ 1819 sp->tx_good = 0; 1820 sp->tx_underruns = 0; 1821 sp->tx_total_collisions = 0; 1822 1823 sp->rx_good = 0; 1824 sp->rx_crc_errors = 0; 1825 sp->rx_alignment_errors = 0; 1826 sp->rx_rnr_errors = 0; 1827 sp->rx_overrun_errors = 0; 1828 } 1829 if (sc->miibus != NULL) 1830 mii_tick(device_get_softc(sc->miibus)); 1831 1832 /* 1833 * Schedule another timeout one second from now. 1834 */ 1835 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1836 FXP_UNLOCK(sc); 1837 splx(s); 1838} 1839 1840/* 1841 * Stop the interface. Cancels the statistics updater and resets 1842 * the interface. 1843 */ 1844static void 1845fxp_stop(struct fxp_softc *sc) 1846{ 1847 struct ifnet *ifp = sc->ifp; 1848 struct fxp_tx *txp; 1849 int i; 1850 1851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1852 ifp->if_timer = 0; 1853 1854#ifdef DEVICE_POLLING 1855 ether_poll_deregister(ifp); 1856#endif 1857 /* 1858 * Cancel stats updater. 1859 */ 1860 callout_stop(&sc->stat_ch); 1861 1862 /* 1863 * Issue software reset, which also unloads the microcode. 1864 */ 1865 sc->flags &= ~FXP_FLAG_UCODE; 1866 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1867 DELAY(50); 1868 1869 /* 1870 * Release any xmit buffers. 1871 */ 1872 txp = sc->fxp_desc.tx_list; 1873 if (txp != NULL) { 1874 for (i = 0; i < FXP_NTXCB; i++) { 1875 if (txp[i].tx_mbuf != NULL) { 1876 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1877 BUS_DMASYNC_POSTWRITE); 1878 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1879 m_freem(txp[i].tx_mbuf); 1880 txp[i].tx_mbuf = NULL; 1881 /* clear this to reset csum offload bits */ 1882 txp[i].tx_cb->tbd[0].tb_addr = 0; 1883 } 1884 } 1885 } 1886 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1887 sc->tx_queued = 0; 1888} 1889 1890/* 1891 * Watchdog/transmission transmit timeout handler. Called when a 1892 * transmission is started on the interface, but no interrupt is 1893 * received before the timeout. This usually indicates that the 1894 * card has wedged for some reason. 1895 */ 1896static void 1897fxp_watchdog(struct ifnet *ifp) 1898{ 1899 struct fxp_softc *sc = ifp->if_softc; 1900 1901 FXP_LOCK(sc); 1902 device_printf(sc->dev, "device timeout\n"); 1903 ifp->if_oerrors++; 1904 1905 fxp_init_body(sc); 1906 FXP_UNLOCK(sc); 1907} 1908 1909/* 1910 * Acquire locks and then call the real initialization function. This 1911 * is necessary because ether_ioctl() calls if_init() and this would 1912 * result in mutex recursion if the mutex was held. 1913 */ 1914static void 1915fxp_init(void *xsc) 1916{ 1917 struct fxp_softc *sc = xsc; 1918 1919 FXP_LOCK(sc); 1920 fxp_init_body(sc); 1921 FXP_UNLOCK(sc); 1922} 1923 1924/* 1925 * Perform device initialization. This routine must be called with the 1926 * softc lock held. 1927 */ 1928static void 1929fxp_init_body(struct fxp_softc *sc) 1930{ 1931 struct ifnet *ifp = sc->ifp; 1932 struct fxp_cb_config *cbp; 1933 struct fxp_cb_ias *cb_ias; 1934 struct fxp_cb_tx *tcbp; 1935 struct fxp_tx *txp; 1936 struct fxp_cb_mcs *mcsp; 1937 int i, prm, s; 1938 1939 FXP_LOCK_ASSERT(sc, MA_OWNED); 1940 s = splimp(); 1941 /* 1942 * Cancel any pending I/O 1943 */ 1944 fxp_stop(sc); 1945 1946 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1947 1948 /* 1949 * Initialize base of CBL and RFA memory. Loading with zero 1950 * sets it up for regular linear addressing. 1951 */ 1952 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1953 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1954 1955 fxp_scb_wait(sc); 1956 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1957 1958 /* 1959 * Initialize base of dump-stats buffer. 1960 */ 1961 fxp_scb_wait(sc); 1962 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1963 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1964 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1965 1966 /* 1967 * Attempt to load microcode if requested. 1968 */ 1969 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1970 fxp_load_ucode(sc); 1971 1972 /* 1973 * Initialize the multicast address list. 1974 */ 1975 if (fxp_mc_addrs(sc)) { 1976 mcsp = sc->mcsp; 1977 mcsp->cb_status = 0; 1978 mcsp->cb_command = 1979 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1980 mcsp->link_addr = 0xffffffff; 1981 /* 1982 * Start the multicast setup command. 1983 */ 1984 fxp_scb_wait(sc); 1985 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1986 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1987 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1988 /* ...and wait for it to complete. */ 1989 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1990 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1991 BUS_DMASYNC_POSTWRITE); 1992 } 1993 1994 /* 1995 * We temporarily use memory that contains the TxCB list to 1996 * construct the config CB. The TxCB list memory is rebuilt 1997 * later. 1998 */ 1999 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2000 2001 /* 2002 * This bcopy is kind of disgusting, but there are a bunch of must be 2003 * zero and must be one bits in this structure and this is the easiest 2004 * way to initialize them all to proper values. 2005 */ 2006 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2007 2008 cbp->cb_status = 0; 2009 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2010 FXP_CB_COMMAND_EL); 2011 cbp->link_addr = 0xffffffff; /* (no) next command */ 2012 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2013 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2014 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2015 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2016 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2017 cbp->type_enable = 0; /* actually reserved */ 2018 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2019 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2020 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2021 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2022 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2023 cbp->late_scb = 0; /* (don't) defer SCB update */ 2024 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2025 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2026 cbp->ci_int = 1; /* interrupt on CU idle */ 2027 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2028 cbp->ext_stats_dis = 1; /* disable extended counters */ 2029 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2030 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2031 cbp->disc_short_rx = !prm; /* discard short packets */ 2032 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2033 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2034 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2035 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2036 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2037 cbp->csma_dis = 0; /* (don't) disable link */ 2038 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2039 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2040 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2041 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2042 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2043 cbp->nsai = 1; /* (don't) disable source addr insert */ 2044 cbp->preamble_length = 2; /* (7 byte) preamble */ 2045 cbp->loopback = 0; /* (don't) loopback */ 2046 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2047 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2048 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2049 cbp->promiscuous = prm; /* promiscuous mode */ 2050 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2051 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2052 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2053 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2054 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2055 2056 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2057 cbp->padding = 1; /* (do) pad short tx packets */ 2058 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2059 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2060 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2061 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2062 /* must set wake_en in PMCSR also */ 2063 cbp->force_fdx = 0; /* (don't) force full duplex */ 2064 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2065 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2066 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2067 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2068 2069 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2070 /* 2071 * The 82557 has no hardware flow control, the values 2072 * below are the defaults for the chip. 2073 */ 2074 cbp->fc_delay_lsb = 0; 2075 cbp->fc_delay_msb = 0x40; 2076 cbp->pri_fc_thresh = 3; 2077 cbp->tx_fc_dis = 0; 2078 cbp->rx_fc_restop = 0; 2079 cbp->rx_fc_restart = 0; 2080 cbp->fc_filter = 0; 2081 cbp->pri_fc_loc = 1; 2082 } else { 2083 cbp->fc_delay_lsb = 0x1f; 2084 cbp->fc_delay_msb = 0x01; 2085 cbp->pri_fc_thresh = 3; 2086 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2087 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2088 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2089 cbp->fc_filter = !prm; /* drop FC frames to host */ 2090 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2091 } 2092 2093 /* 2094 * Start the config command/DMA. 2095 */ 2096 fxp_scb_wait(sc); 2097 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2098 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2099 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2100 /* ...and wait for it to complete. */ 2101 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2102 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2103 2104 /* 2105 * Now initialize the station address. Temporarily use the TxCB 2106 * memory area like we did above for the config CB. 2107 */ 2108 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2109 cb_ias->cb_status = 0; 2110 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2111 cb_ias->link_addr = 0xffffffff; 2112 bcopy(IFP2ENADDR(sc->ifp), cb_ias->macaddr, 2113 sizeof(IFP2ENADDR(sc->ifp))); 2114 2115 /* 2116 * Start the IAS (Individual Address Setup) command/DMA. 2117 */ 2118 fxp_scb_wait(sc); 2119 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2120 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2121 /* ...and wait for it to complete. */ 2122 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2123 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2124 2125 /* 2126 * Initialize transmit control block (TxCB) list. 2127 */ 2128 txp = sc->fxp_desc.tx_list; 2129 tcbp = sc->fxp_desc.cbl_list; 2130 bzero(tcbp, FXP_TXCB_SZ); 2131 for (i = 0; i < FXP_NTXCB; i++) { 2132 txp[i].tx_mbuf = NULL; 2133 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2134 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2135 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2136 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2137 if (sc->flags & FXP_FLAG_EXT_TXCB) 2138 tcbp[i].tbd_array_addr = 2139 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2140 else 2141 tcbp[i].tbd_array_addr = 2142 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2143 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2144 } 2145 /* 2146 * Set the suspend flag on the first TxCB and start the control 2147 * unit. It will execute the NOP and then suspend. 2148 */ 2149 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2150 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2151 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2152 sc->tx_queued = 1; 2153 2154 fxp_scb_wait(sc); 2155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2156 2157 /* 2158 * Initialize receiver buffer area - RFA. 2159 */ 2160 fxp_scb_wait(sc); 2161 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2163 2164 /* 2165 * Set current media. 2166 */ 2167 if (sc->miibus != NULL) 2168 mii_mediachg(device_get_softc(sc->miibus)); 2169 2170 ifp->if_flags |= IFF_RUNNING; 2171 ifp->if_flags &= ~IFF_OACTIVE; 2172 2173 /* 2174 * Enable interrupts. 2175 */ 2176#ifdef DEVICE_POLLING 2177 /* 2178 * ... but only do that if we are not polling. And because (presumably) 2179 * the default is interrupts on, we need to disable them explicitly! 2180 */ 2181 if ( ifp->if_flags & IFF_POLLING ) 2182 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2183 else 2184#endif /* DEVICE_POLLING */ 2185 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2186 2187 /* 2188 * Start stats updater. 2189 */ 2190 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2191 splx(s); 2192} 2193 2194static int 2195fxp_serial_ifmedia_upd(struct ifnet *ifp) 2196{ 2197 2198 return (0); 2199} 2200 2201static void 2202fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2203{ 2204 2205 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2206} 2207 2208/* 2209 * Change media according to request. 2210 */ 2211static int 2212fxp_ifmedia_upd(struct ifnet *ifp) 2213{ 2214 struct fxp_softc *sc = ifp->if_softc; 2215 struct mii_data *mii; 2216 2217 mii = device_get_softc(sc->miibus); 2218 mii_mediachg(mii); 2219 return (0); 2220} 2221 2222/* 2223 * Notify the world which media we're using. 2224 */ 2225static void 2226fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2227{ 2228 struct fxp_softc *sc = ifp->if_softc; 2229 struct mii_data *mii; 2230 2231 mii = device_get_softc(sc->miibus); 2232 mii_pollstat(mii); 2233 ifmr->ifm_active = mii->mii_media_active; 2234 ifmr->ifm_status = mii->mii_media_status; 2235 2236 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2237 sc->cu_resume_bug = 1; 2238 else 2239 sc->cu_resume_bug = 0; 2240} 2241 2242/* 2243 * Add a buffer to the end of the RFA buffer list. 2244 * Return 0 if successful, 1 for failure. A failure results in 2245 * adding the 'oldm' (if non-NULL) on to the end of the list - 2246 * tossing out its old contents and recycling it. 2247 * The RFA struct is stuck at the beginning of mbuf cluster and the 2248 * data pointer is fixed up to point just past it. 2249 */ 2250static int 2251fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2252{ 2253 struct mbuf *m; 2254 struct fxp_rfa *rfa, *p_rfa; 2255 struct fxp_rx *p_rx; 2256 bus_dmamap_t tmp_map; 2257 int error; 2258 2259 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2260 if (m == NULL) 2261 return (ENOBUFS); 2262 2263 /* 2264 * Move the data pointer up so that the incoming data packet 2265 * will be 32-bit aligned. 2266 */ 2267 m->m_data += RFA_ALIGNMENT_FUDGE; 2268 2269 /* 2270 * Get a pointer to the base of the mbuf cluster and move 2271 * data start past it. 2272 */ 2273 rfa = mtod(m, struct fxp_rfa *); 2274 m->m_data += sc->rfa_size; 2275 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2276 2277 rfa->rfa_status = 0; 2278 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2279 rfa->actual_size = 0; 2280 2281 /* 2282 * Initialize the rest of the RFA. Note that since the RFA 2283 * is misaligned, we cannot store values directly. We're thus 2284 * using the le32enc() function which handles endianness and 2285 * is also alignment-safe. 2286 */ 2287 le32enc(&rfa->link_addr, 0xffffffff); 2288 le32enc(&rfa->rbd_addr, 0xffffffff); 2289 2290 /* Map the RFA into DMA memory. */ 2291 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2292 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2293 &rxp->rx_addr, 0); 2294 if (error) { 2295 m_freem(m); 2296 return (error); 2297 } 2298 2299 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2300 tmp_map = sc->spare_map; 2301 sc->spare_map = rxp->rx_map; 2302 rxp->rx_map = tmp_map; 2303 rxp->rx_mbuf = m; 2304 2305 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2307 2308 /* 2309 * If there are other buffers already on the list, attach this 2310 * one to the end by fixing up the tail to point to this one. 2311 */ 2312 if (sc->fxp_desc.rx_head != NULL) { 2313 p_rx = sc->fxp_desc.rx_tail; 2314 p_rfa = (struct fxp_rfa *) 2315 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2316 p_rx->rx_next = rxp; 2317 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2318 p_rfa->rfa_control = 0; 2319 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2320 BUS_DMASYNC_PREWRITE); 2321 } else { 2322 rxp->rx_next = NULL; 2323 sc->fxp_desc.rx_head = rxp; 2324 } 2325 sc->fxp_desc.rx_tail = rxp; 2326 return (0); 2327} 2328 2329static volatile int 2330fxp_miibus_readreg(device_t dev, int phy, int reg) 2331{ 2332 struct fxp_softc *sc = device_get_softc(dev); 2333 int count = 10000; 2334 int value; 2335 2336 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2337 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2338 2339 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2340 && count--) 2341 DELAY(10); 2342 2343 if (count <= 0) 2344 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2345 2346 return (value & 0xffff); 2347} 2348 2349static void 2350fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2351{ 2352 struct fxp_softc *sc = device_get_softc(dev); 2353 int count = 10000; 2354 2355 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2356 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2357 (value & 0xffff)); 2358 2359 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2360 count--) 2361 DELAY(10); 2362 2363 if (count <= 0) 2364 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2365} 2366 2367static int 2368fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2369{ 2370 struct fxp_softc *sc = ifp->if_softc; 2371 struct ifreq *ifr = (struct ifreq *)data; 2372 struct mii_data *mii; 2373 int flag, mask, s, error = 0; 2374 2375 /* 2376 * Detaching causes us to call ioctl with the mutex owned. Preclude 2377 * that by saying we're busy if the lock is already held. 2378 */ 2379 if (FXP_LOCKED(sc)) 2380 return (EBUSY); 2381 2382 FXP_LOCK(sc); 2383 s = splimp(); 2384 2385 switch (command) { 2386 case SIOCSIFFLAGS: 2387 if (ifp->if_flags & IFF_ALLMULTI) 2388 sc->flags |= FXP_FLAG_ALL_MCAST; 2389 else 2390 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2391 2392 /* 2393 * If interface is marked up and not running, then start it. 2394 * If it is marked down and running, stop it. 2395 * XXX If it's up then re-initialize it. This is so flags 2396 * such as IFF_PROMISC are handled. 2397 */ 2398 if (ifp->if_flags & IFF_UP) { 2399 fxp_init_body(sc); 2400 } else { 2401 if (ifp->if_flags & IFF_RUNNING) 2402 fxp_stop(sc); 2403 } 2404 break; 2405 2406 case SIOCADDMULTI: 2407 case SIOCDELMULTI: 2408 if (ifp->if_flags & IFF_ALLMULTI) 2409 sc->flags |= FXP_FLAG_ALL_MCAST; 2410 else 2411 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2412 /* 2413 * Multicast list has changed; set the hardware filter 2414 * accordingly. 2415 */ 2416 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2417 fxp_mc_setup(sc); 2418 /* 2419 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2420 * again rather than else {}. 2421 */ 2422 if (sc->flags & FXP_FLAG_ALL_MCAST) 2423 fxp_init_body(sc); 2424 error = 0; 2425 break; 2426 2427 case SIOCSIFMEDIA: 2428 case SIOCGIFMEDIA: 2429 if (sc->miibus != NULL) { 2430 mii = device_get_softc(sc->miibus); 2431 error = ifmedia_ioctl(ifp, ifr, 2432 &mii->mii_media, command); 2433 } else { 2434 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2435 } 2436 break; 2437 2438 case SIOCSIFCAP: 2439 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2440 if (mask & IFCAP_POLLING) 2441 ifp->if_capenable ^= IFCAP_POLLING; 2442 if (mask & IFCAP_VLAN_MTU) { 2443 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2444 if (sc->revision != FXP_REV_82557) 2445 flag = FXP_FLAG_LONG_PKT_EN; 2446 else /* a hack to get long frames on the old chip */ 2447 flag = FXP_FLAG_SAVE_BAD; 2448 sc->flags ^= flag; 2449 if (ifp->if_flags & IFF_UP) 2450 fxp_init_body(sc); 2451 } 2452 break; 2453 2454 default: 2455 /* 2456 * ether_ioctl() will eventually call fxp_start() which 2457 * will result in mutex recursion so drop it first. 2458 */ 2459 FXP_UNLOCK(sc); 2460 error = ether_ioctl(ifp, command, data); 2461 } 2462 if (FXP_LOCKED(sc)) 2463 FXP_UNLOCK(sc); 2464 splx(s); 2465 return (error); 2466} 2467 2468/* 2469 * Fill in the multicast address list and return number of entries. 2470 */ 2471static int 2472fxp_mc_addrs(struct fxp_softc *sc) 2473{ 2474 struct fxp_cb_mcs *mcsp = sc->mcsp; 2475 struct ifnet *ifp = sc->ifp; 2476 struct ifmultiaddr *ifma; 2477 int nmcasts; 2478 2479 nmcasts = 0; 2480 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2481#if __FreeBSD_version < 500000 2482 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2483#else 2484 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2485#endif 2486 if (ifma->ifma_addr->sa_family != AF_LINK) 2487 continue; 2488 if (nmcasts >= MAXMCADDR) { 2489 sc->flags |= FXP_FLAG_ALL_MCAST; 2490 nmcasts = 0; 2491 break; 2492 } 2493 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2494 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2495 nmcasts++; 2496 } 2497 } 2498 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2499 return (nmcasts); 2500} 2501 2502/* 2503 * Program the multicast filter. 2504 * 2505 * We have an artificial restriction that the multicast setup command 2506 * must be the first command in the chain, so we take steps to ensure 2507 * this. By requiring this, it allows us to keep up the performance of 2508 * the pre-initialized command ring (esp. link pointers) by not actually 2509 * inserting the mcsetup command in the ring - i.e. its link pointer 2510 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2511 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2512 * lead into the regular TxCB ring when it completes. 2513 * 2514 * This function must be called at splimp. 2515 */ 2516static void 2517fxp_mc_setup(struct fxp_softc *sc) 2518{ 2519 struct fxp_cb_mcs *mcsp = sc->mcsp; 2520 struct ifnet *ifp = sc->ifp; 2521 struct fxp_tx *txp; 2522 int count; 2523 2524 FXP_LOCK_ASSERT(sc, MA_OWNED); 2525 /* 2526 * If there are queued commands, we must wait until they are all 2527 * completed. If we are already waiting, then add a NOP command 2528 * with interrupt option so that we're notified when all commands 2529 * have been completed - fxp_start() ensures that no additional 2530 * TX commands will be added when need_mcsetup is true. 2531 */ 2532 if (sc->tx_queued) { 2533 /* 2534 * need_mcsetup will be true if we are already waiting for the 2535 * NOP command to be completed (see below). In this case, bail. 2536 */ 2537 if (sc->need_mcsetup) 2538 return; 2539 sc->need_mcsetup = 1; 2540 2541 /* 2542 * Add a NOP command with interrupt so that we are notified 2543 * when all TX commands have been processed. 2544 */ 2545 txp = sc->fxp_desc.tx_last->tx_next; 2546 txp->tx_mbuf = NULL; 2547 txp->tx_cb->cb_status = 0; 2548 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2549 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2550 /* 2551 * Advance the end of list forward. 2552 */ 2553 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2554 htole16(~FXP_CB_COMMAND_S); 2555 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2556 sc->fxp_desc.tx_last = txp; 2557 sc->tx_queued++; 2558 /* 2559 * Issue a resume in case the CU has just suspended. 2560 */ 2561 fxp_scb_wait(sc); 2562 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2563 /* 2564 * Set a 5 second timer just in case we don't hear from the 2565 * card again. 2566 */ 2567 ifp->if_timer = 5; 2568 2569 return; 2570 } 2571 sc->need_mcsetup = 0; 2572 2573 /* 2574 * Initialize multicast setup descriptor. 2575 */ 2576 mcsp->cb_status = 0; 2577 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2578 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2579 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2580 txp = &sc->fxp_desc.mcs_tx; 2581 txp->tx_mbuf = NULL; 2582 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2583 txp->tx_next = sc->fxp_desc.tx_list; 2584 (void) fxp_mc_addrs(sc); 2585 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2586 sc->tx_queued = 1; 2587 2588 /* 2589 * Wait until command unit is not active. This should never 2590 * be the case when nothing is queued, but make sure anyway. 2591 */ 2592 count = 100; 2593 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2594 FXP_SCB_CUS_ACTIVE && --count) 2595 DELAY(10); 2596 if (count == 0) { 2597 device_printf(sc->dev, "command queue timeout\n"); 2598 return; 2599 } 2600 2601 /* 2602 * Start the multicast setup command. 2603 */ 2604 fxp_scb_wait(sc); 2605 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2606 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2607 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2608 2609 ifp->if_timer = 2; 2610 return; 2611} 2612 2613static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2614static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2615static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2616static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2617static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2618static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2619static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2620 2621#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2622 2623struct ucode { 2624 uint32_t revision; 2625 uint32_t *ucode; 2626 int length; 2627 u_short int_delay_offset; 2628 u_short bundle_max_offset; 2629} ucode_table[] = { 2630 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2631 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2632 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2633 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2634 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2635 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2636 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2637 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2638 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2639 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2641 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { 0, NULL, 0, 0, 0 } 2643}; 2644 2645static void 2646fxp_load_ucode(struct fxp_softc *sc) 2647{ 2648 struct ucode *uc; 2649 struct fxp_cb_ucode *cbp; 2650 int i; 2651 2652 for (uc = ucode_table; uc->ucode != NULL; uc++) 2653 if (sc->revision == uc->revision) 2654 break; 2655 if (uc->ucode == NULL) 2656 return; 2657 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2658 cbp->cb_status = 0; 2659 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2660 cbp->link_addr = 0xffffffff; /* (no) next command */ 2661 for (i = 0; i < uc->length; i++) 2662 cbp->ucode[i] = htole32(uc->ucode[i]); 2663 if (uc->int_delay_offset) 2664 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2665 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2666 if (uc->bundle_max_offset) 2667 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2668 htole16(sc->tunable_bundle_max); 2669 /* 2670 * Download the ucode to the chip. 2671 */ 2672 fxp_scb_wait(sc); 2673 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2674 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2675 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2676 /* ...and wait for it to complete. */ 2677 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2678 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2679 device_printf(sc->dev, 2680 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2681 sc->tunable_int_delay, 2682 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2683 sc->flags |= FXP_FLAG_UCODE; 2684} 2685 2686static int 2687sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2688{ 2689 int error, value; 2690 2691 value = *(int *)arg1; 2692 error = sysctl_handle_int(oidp, &value, 0, req); 2693 if (error || !req->newptr) 2694 return (error); 2695 if (value < low || value > high) 2696 return (EINVAL); 2697 *(int *)arg1 = value; 2698 return (0); 2699} 2700 2701/* 2702 * Interrupt delay is expressed in microseconds, a multiplier is used 2703 * to convert this to the appropriate clock ticks before using. 2704 */ 2705static int 2706sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2707{ 2708 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2709} 2710 2711static int 2712sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2713{ 2714 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2715} 2716