if_fxp.c revision 147256
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 147256 2005-06-10 16:49:24Z brooks $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194}; 195 196#ifdef FXP_IP_CSUM_WAR 197#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198#else 199#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200#endif 201 202static int fxp_probe(device_t dev); 203static int fxp_attach(device_t dev); 204static int fxp_detach(device_t dev); 205static int fxp_shutdown(device_t dev); 206static int fxp_suspend(device_t dev); 207static int fxp_resume(device_t dev); 208 209static void fxp_intr(void *xsc); 210static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212static void fxp_init(void *xsc); 213static void fxp_init_body(struct fxp_softc *sc); 214static void fxp_tick(void *xsc); 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218static void fxp_stop(struct fxp_softc *sc); 219static void fxp_release(struct fxp_softc *sc); 220static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222static void fxp_watchdog(struct ifnet *ifp); 223static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225static int fxp_mc_addrs(struct fxp_softc *sc); 226static void fxp_mc_setup(struct fxp_softc *sc); 227static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231static void fxp_autosize_eeprom(struct fxp_softc *sc); 232static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236static int fxp_ifmedia_upd(struct ifnet *ifp); 237static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245static void fxp_load_ucode(struct fxp_softc *sc); 246static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250static void fxp_scb_wait(struct fxp_softc *sc); 251static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270}; 271 272static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276}; 277 278static devclass_t fxp_devclass; 279 280DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284/* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288static void 289fxp_scb_wait(struct fxp_softc *sc) 290{ 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301} 302 303static void 304fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305{ 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312} 313 314static void 315fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317{ 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327} 328 329/* 330 * Return identification string if this device is ours. 331 */ 332static int 333fxp_probe(device_t dev) 334{ 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351} 352 353static void 354fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355{ 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 u_char eaddr[ETHER_ADDR_LEN]; 377 int i, rid, m1, m2, prefer_iomap; 378 int error, s; 379 380 error = 0; 381 sc = device_get_softc(dev); 382 sc->dev = dev; 383 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 384 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF); 386 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 387 fxp_serial_ifmedia_sts); 388 389 s = splimp(); 390 391 /* 392 * Enable bus mastering. 393 */ 394 pci_enable_busmaster(dev); 395 val = pci_read_config(dev, PCIR_COMMAND, 2); 396 397 /* 398 * Figure out which we should try first - memory mapping or i/o mapping? 399 * We default to memory mapping. Then we accept an override from the 400 * command line. Then we check to see which one is enabled. 401 */ 402 m1 = PCIM_CMD_MEMEN; 403 m2 = PCIM_CMD_PORTEN; 404 prefer_iomap = 0; 405 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 406 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 407 m1 = PCIM_CMD_PORTEN; 408 m2 = PCIM_CMD_MEMEN; 409 } 410 411 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 413 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 414 if (sc->mem == NULL) { 415 sc->rtp = 416 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 417 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 418 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 419 RF_ACTIVE); 420 } 421 422 if (!sc->mem) { 423 error = ENXIO; 424 goto fail; 425 } 426 if (bootverbose) { 427 device_printf(dev, "using %s space register mapping\n", 428 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 429 } 430 431 sc->sc_st = rman_get_bustag(sc->mem); 432 sc->sc_sh = rman_get_bushandle(sc->mem); 433 434 /* 435 * Allocate our interrupt. 436 */ 437 rid = 0; 438 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 439 RF_SHAREABLE | RF_ACTIVE); 440 if (sc->irq == NULL) { 441 device_printf(dev, "could not map interrupt\n"); 442 error = ENXIO; 443 goto fail; 444 } 445 446 /* 447 * Reset to a stable state. 448 */ 449 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 450 DELAY(10); 451 452 /* 453 * Find out how large of an SEEPROM we have. 454 */ 455 fxp_autosize_eeprom(sc); 456 457 /* 458 * Find out the chip revision; lump all 82557 revs together. 459 */ 460 fxp_read_eeprom(sc, &data, 5, 1); 461 if ((data >> 8) == 1) 462 sc->revision = FXP_REV_82557; 463 else 464 sc->revision = pci_get_revid(dev); 465 466 /* 467 * Determine whether we must use the 503 serial interface. 468 */ 469 fxp_read_eeprom(sc, &data, 6, 1); 470 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 471 && (data & FXP_PHY_SERIAL_ONLY)) 472 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 473 474 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 476 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 477 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 478 "FXP driver receive interrupt microcode bundling delay"); 479 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 480 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 481 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 482 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 483 "FXP driver receive interrupt microcode bundle size limit"); 484 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 485 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 486 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 487 "FXP RNR events"); 488 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 489 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 490 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 491 "FXP flow control disabled"); 492 493 /* 494 * Pull in device tunables. 495 */ 496 sc->tunable_int_delay = TUNABLE_INT_DELAY; 497 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 498 sc->tunable_noflow = 1; 499 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 500 "int_delay", &sc->tunable_int_delay); 501 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 502 "bundle_max", &sc->tunable_bundle_max); 503 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 504 "noflow", &sc->tunable_noflow); 505 sc->rnr = 0; 506 507 /* 508 * Enable workarounds for certain chip revision deficiencies. 509 * 510 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 511 * some systems based a normal 82559 design, have a defect where 512 * the chip can cause a PCI protocol violation if it receives 513 * a CU_RESUME command when it is entering the IDLE state. The 514 * workaround is to disable Dynamic Standby Mode, so the chip never 515 * deasserts CLKRUN#, and always remains in an active state. 516 * 517 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 518 */ 519 i = pci_get_device(dev); 520 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 521 sc->revision >= FXP_REV_82559_A0) { 522 fxp_read_eeprom(sc, &data, 10, 1); 523 if (data & 0x02) { /* STB enable */ 524 uint16_t cksum; 525 int i; 526 527 device_printf(dev, 528 "Disabling dynamic standby mode in EEPROM\n"); 529 data &= ~0x02; 530 fxp_write_eeprom(sc, &data, 10, 1); 531 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 532 cksum = 0; 533 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 534 fxp_read_eeprom(sc, &data, i, 1); 535 cksum += data; 536 } 537 i = (1 << sc->eeprom_size) - 1; 538 cksum = 0xBABA - cksum; 539 fxp_read_eeprom(sc, &data, i, 1); 540 fxp_write_eeprom(sc, &cksum, i, 1); 541 device_printf(dev, 542 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 543 i, data, cksum); 544#if 1 545 /* 546 * If the user elects to continue, try the software 547 * workaround, as it is better than nothing. 548 */ 549 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 550#endif 551 } 552 } 553 554 /* 555 * If we are not a 82557 chip, we can enable extended features. 556 */ 557 if (sc->revision != FXP_REV_82557) { 558 /* 559 * If MWI is enabled in the PCI configuration, and there 560 * is a valid cacheline size (8 or 16 dwords), then tell 561 * the board to turn on MWI. 562 */ 563 if (val & PCIM_CMD_MWRICEN && 564 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 565 sc->flags |= FXP_FLAG_MWI_ENABLE; 566 567 /* turn on the extended TxCB feature */ 568 sc->flags |= FXP_FLAG_EXT_TXCB; 569 570 /* enable reception of long frames for VLAN */ 571 sc->flags |= FXP_FLAG_LONG_PKT_EN; 572 } else { 573 /* a hack to get long VLAN frames on a 82557 */ 574 sc->flags |= FXP_FLAG_SAVE_BAD; 575 } 576 577 /* 578 * Enable use of extended RFDs and TCBs for 82550 579 * and later chips. Note: we need extended TXCB support 580 * too, but that's already enabled by the code above. 581 * Be careful to do this only on the right devices. 582 */ 583 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 584 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 585 || sc->revision == FXP_REV_82551_10) { 586 sc->rfa_size = sizeof (struct fxp_rfa); 587 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 588 sc->flags |= FXP_FLAG_EXT_RFA; 589 } else { 590 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 591 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 592 } 593 594 /* 595 * Allocate DMA tags and DMA safe memory. 596 */ 597 sc->maxtxseg = FXP_NTXSEG; 598 if (sc->flags & FXP_FLAG_EXT_RFA) 599 sc->maxtxseg--; 600 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 601 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 602 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 603 &sc->fxp_mtag); 604 if (error) { 605 device_printf(dev, "could not allocate dma tag\n"); 606 goto fail; 607 } 608 609 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 610 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 611 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 612 &sc->fxp_stag); 613 if (error) { 614 device_printf(dev, "could not allocate dma tag\n"); 615 goto fail; 616 } 617 618 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 619 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 620 if (error) 621 goto fail; 622 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 623 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 624 if (error) { 625 device_printf(dev, "could not map the stats buffer\n"); 626 goto fail; 627 } 628 629 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 630 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 631 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 632 if (error) { 633 device_printf(dev, "could not allocate dma tag\n"); 634 goto fail; 635 } 636 637 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 638 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 639 if (error) 640 goto fail; 641 642 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 643 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 644 &sc->fxp_desc.cbl_addr, 0); 645 if (error) { 646 device_printf(dev, "could not map DMA memory\n"); 647 goto fail; 648 } 649 650 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 651 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 652 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 653 &sc->mcs_tag); 654 if (error) { 655 device_printf(dev, "could not allocate dma tag\n"); 656 goto fail; 657 } 658 659 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 660 BUS_DMA_NOWAIT, &sc->mcs_map); 661 if (error) 662 goto fail; 663 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 664 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 665 if (error) { 666 device_printf(dev, "can't map the multicast setup command\n"); 667 goto fail; 668 } 669 670 /* 671 * Pre-allocate the TX DMA maps and setup the pointers to 672 * the TX command blocks. 673 */ 674 txp = sc->fxp_desc.tx_list; 675 tcbp = sc->fxp_desc.cbl_list; 676 for (i = 0; i < FXP_NTXCB; i++) { 677 txp[i].tx_cb = tcbp + i; 678 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 679 if (error) { 680 device_printf(dev, "can't create DMA map for TX\n"); 681 goto fail; 682 } 683 } 684 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 685 if (error) { 686 device_printf(dev, "can't create spare DMA map\n"); 687 goto fail; 688 } 689 690 /* 691 * Pre-allocate our receive buffers. 692 */ 693 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 694 for (i = 0; i < FXP_NRFABUFS; i++) { 695 rxp = &sc->fxp_desc.rx_list[i]; 696 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 697 if (error) { 698 device_printf(dev, "can't create DMA map for RX\n"); 699 goto fail; 700 } 701 if (fxp_add_rfabuf(sc, rxp) != 0) { 702 error = ENOMEM; 703 goto fail; 704 } 705 } 706 707 /* 708 * Read MAC address. 709 */ 710 fxp_read_eeprom(sc, myea, 0, 3); 711 eaddr[0] = myea[0] & 0xff; 712 eaddr[1] = myea[0] >> 8; 713 eaddr[2] = myea[1] & 0xff; 714 eaddr[3] = myea[1] >> 8; 715 eaddr[4] = myea[2] & 0xff; 716 eaddr[5] = myea[2] >> 8; 717 if (bootverbose) { 718 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 719 pci_get_vendor(dev), pci_get_device(dev), 720 pci_get_subvendor(dev), pci_get_subdevice(dev), 721 pci_get_revid(dev)); 722 fxp_read_eeprom(sc, &data, 10, 1); 723 device_printf(dev, "Dynamic Standby mode is %s\n", 724 data & 0x02 ? "enabled" : "disabled"); 725 } 726 727 /* 728 * If this is only a 10Mbps device, then there is no MII, and 729 * the PHY will use a serial interface instead. 730 * 731 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 732 * doesn't have a programming interface of any sort. The 733 * media is sensed automatically based on how the link partner 734 * is configured. This is, in essence, manual configuration. 735 */ 736 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 737 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 738 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 739 } else { 740 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 741 fxp_ifmedia_sts)) { 742 device_printf(dev, "MII without any PHY!\n"); 743 error = ENXIO; 744 goto fail; 745 } 746 } 747 748 ifp = sc->ifp = if_alloc(IFT_ETHER); 749 if (ifp == NULL) { 750 device_printf(dev, "can not if_alloc()\n"); 751 error = ENOSPC; 752 goto fail; 753 } 754 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 755 ifp->if_baudrate = 100000000; 756 ifp->if_init = fxp_init; 757 ifp->if_softc = sc; 758 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 759 ifp->if_ioctl = fxp_ioctl; 760 ifp->if_start = fxp_start; 761 ifp->if_watchdog = fxp_watchdog; 762 763 ifp->if_capabilities = ifp->if_capenable = 0; 764 765 /* Enable checksum offload for 82550 or better chips */ 766 if (sc->flags & FXP_FLAG_EXT_RFA) { 767 ifp->if_hwassist = FXP_CSUM_FEATURES; 768 ifp->if_capabilities |= IFCAP_HWCSUM; 769 ifp->if_capenable |= IFCAP_HWCSUM; 770 } 771 772#ifdef DEVICE_POLLING 773 /* Inform the world we support polling. */ 774 ifp->if_capabilities |= IFCAP_POLLING; 775 ifp->if_capenable |= IFCAP_POLLING; 776#endif 777 778 /* 779 * Attach the interface. 780 */ 781 ether_ifattach(ifp, eaddr); 782 783 /* 784 * Tell the upper layer(s) we support long frames. 785 * Must appear after the call to ether_ifattach() because 786 * ether_ifattach() sets ifi_hdrlen to the default value. 787 */ 788 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 789 ifp->if_capabilities |= IFCAP_VLAN_MTU; 790 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 791 792 /* 793 * Let the system queue as many packets as we have available 794 * TX descriptors. 795 */ 796 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 797 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 798 IFQ_SET_READY(&ifp->if_snd); 799 800 /* 801 * Hook our interrupt after all initialization is complete. 802 */ 803 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 804 fxp_intr, sc, &sc->ih); 805 if (error) { 806 device_printf(dev, "could not setup irq\n"); 807 ether_ifdetach(sc->ifp); 808 goto fail; 809 } 810 811fail: 812 splx(s); 813 if (error) { 814 fxp_release(sc); 815 } 816 return (error); 817} 818 819/* 820 * Release all resources. The softc lock should not be held and the 821 * interrupt should already be torn down. 822 */ 823static void 824fxp_release(struct fxp_softc *sc) 825{ 826 struct fxp_rx *rxp; 827 struct fxp_tx *txp; 828 int i; 829 830 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 831 KASSERT(sc->ih == NULL, 832 ("fxp_release() called with intr handle still active")); 833 if (sc->miibus) 834 device_delete_child(sc->dev, sc->miibus); 835 bus_generic_detach(sc->dev); 836 ifmedia_removeall(&sc->sc_media); 837 if (sc->fxp_desc.cbl_list) { 838 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 839 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 840 sc->cbl_map); 841 } 842 if (sc->fxp_stats) { 843 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 844 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 845 } 846 if (sc->mcsp) { 847 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 848 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 849 } 850 if (sc->irq) 851 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 852 if (sc->mem) 853 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 854 if (sc->fxp_mtag) { 855 for (i = 0; i < FXP_NRFABUFS; i++) { 856 rxp = &sc->fxp_desc.rx_list[i]; 857 if (rxp->rx_mbuf != NULL) { 858 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 859 BUS_DMASYNC_POSTREAD); 860 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 861 m_freem(rxp->rx_mbuf); 862 } 863 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 864 } 865 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 866 for (i = 0; i < FXP_NTXCB; i++) { 867 txp = &sc->fxp_desc.tx_list[i]; 868 if (txp->tx_mbuf != NULL) { 869 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 870 BUS_DMASYNC_POSTWRITE); 871 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 872 m_freem(txp->tx_mbuf); 873 } 874 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 875 } 876 bus_dma_tag_destroy(sc->fxp_mtag); 877 } 878 if (sc->fxp_stag) 879 bus_dma_tag_destroy(sc->fxp_stag); 880 if (sc->cbl_tag) 881 bus_dma_tag_destroy(sc->cbl_tag); 882 if (sc->mcs_tag) 883 bus_dma_tag_destroy(sc->mcs_tag); 884 if (sc->ifp) 885 if_free(sc->ifp); 886 887 mtx_destroy(&sc->sc_mtx); 888} 889 890/* 891 * Detach interface. 892 */ 893static int 894fxp_detach(device_t dev) 895{ 896 struct fxp_softc *sc = device_get_softc(dev); 897 int s; 898 899 FXP_LOCK(sc); 900 s = splimp(); 901 902 sc->suspended = 1; /* Do same thing as we do for suspend */ 903 /* 904 * Close down routes etc. 905 */ 906 ether_ifdetach(sc->ifp); 907 if_free(sc->ifp); 908 909 /* 910 * Stop DMA and drop transmit queue, but disable interrupts first. 911 */ 912 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 913 fxp_stop(sc); 914 FXP_UNLOCK(sc); 915 916 /* 917 * Unhook interrupt before dropping lock. This is to prevent 918 * races with fxp_intr(). 919 */ 920 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 921 sc->ih = NULL; 922 923 splx(s); 924 925 /* Release our allocated resources. */ 926 fxp_release(sc); 927 return (0); 928} 929 930/* 931 * Device shutdown routine. Called at system shutdown after sync. The 932 * main purpose of this routine is to shut off receiver DMA so that 933 * kernel memory doesn't get clobbered during warmboot. 934 */ 935static int 936fxp_shutdown(device_t dev) 937{ 938 /* 939 * Make sure that DMA is disabled prior to reboot. Not doing 940 * do could allow DMA to corrupt kernel memory during the 941 * reboot before the driver initializes. 942 */ 943 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 944 return (0); 945} 946 947/* 948 * Device suspend routine. Stop the interface and save some PCI 949 * settings in case the BIOS doesn't restore them properly on 950 * resume. 951 */ 952static int 953fxp_suspend(device_t dev) 954{ 955 struct fxp_softc *sc = device_get_softc(dev); 956 int s; 957 958 FXP_LOCK(sc); 959 s = splimp(); 960 961 fxp_stop(sc); 962 963 sc->suspended = 1; 964 965 FXP_UNLOCK(sc); 966 splx(s); 967 return (0); 968} 969 970/* 971 * Device resume routine. re-enable busmastering, and restart the interface if 972 * appropriate. 973 */ 974static int 975fxp_resume(device_t dev) 976{ 977 struct fxp_softc *sc = device_get_softc(dev); 978 struct ifnet *ifp = sc->ifp; 979 uint16_t pci_command; 980 int s; 981 982 FXP_LOCK(sc); 983 s = splimp(); 984 985 /* reenable busmastering */ 986 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 987 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 988 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 989 990 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 991 DELAY(10); 992 993 /* reinitialize interface if necessary */ 994 if (ifp->if_flags & IFF_UP) 995 fxp_init_body(sc); 996 997 sc->suspended = 0; 998 999 FXP_UNLOCK(sc); 1000 splx(s); 1001 return (0); 1002} 1003 1004static void 1005fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1006{ 1007 uint16_t reg; 1008 int x; 1009 1010 /* 1011 * Shift in data. 1012 */ 1013 for (x = 1 << (length - 1); x; x >>= 1) { 1014 if (data & x) 1015 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1016 else 1017 reg = FXP_EEPROM_EECS; 1018 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1019 DELAY(1); 1020 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1021 DELAY(1); 1022 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1023 DELAY(1); 1024 } 1025} 1026 1027/* 1028 * Read from the serial EEPROM. Basically, you manually shift in 1029 * the read opcode (one bit at a time) and then shift in the address, 1030 * and then you shift out the data (all of this one bit at a time). 1031 * The word size is 16 bits, so you have to provide the address for 1032 * every 16 bits of data. 1033 */ 1034static uint16_t 1035fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1036{ 1037 uint16_t reg, data; 1038 int x; 1039 1040 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1041 /* 1042 * Shift in read opcode. 1043 */ 1044 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1045 /* 1046 * Shift in address. 1047 */ 1048 data = 0; 1049 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1050 if (offset & x) 1051 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1052 else 1053 reg = FXP_EEPROM_EECS; 1054 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1055 DELAY(1); 1056 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1057 DELAY(1); 1058 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1059 DELAY(1); 1060 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1061 data++; 1062 if (autosize && reg == 0) { 1063 sc->eeprom_size = data; 1064 break; 1065 } 1066 } 1067 /* 1068 * Shift out data. 1069 */ 1070 data = 0; 1071 reg = FXP_EEPROM_EECS; 1072 for (x = 1 << 15; x; x >>= 1) { 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1074 DELAY(1); 1075 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1076 data |= x; 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1078 DELAY(1); 1079 } 1080 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1081 DELAY(1); 1082 1083 return (data); 1084} 1085 1086static void 1087fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1088{ 1089 int i; 1090 1091 /* 1092 * Erase/write enable. 1093 */ 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1095 fxp_eeprom_shiftin(sc, 0x4, 3); 1096 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1098 DELAY(1); 1099 /* 1100 * Shift in write opcode, address, data. 1101 */ 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1103 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1104 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1105 fxp_eeprom_shiftin(sc, data, 16); 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1107 DELAY(1); 1108 /* 1109 * Wait for EEPROM to finish up. 1110 */ 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1112 DELAY(1); 1113 for (i = 0; i < 1000; i++) { 1114 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1115 break; 1116 DELAY(50); 1117 } 1118 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1119 DELAY(1); 1120 /* 1121 * Erase/write disable. 1122 */ 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1124 fxp_eeprom_shiftin(sc, 0x4, 3); 1125 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1127 DELAY(1); 1128} 1129 1130/* 1131 * From NetBSD: 1132 * 1133 * Figure out EEPROM size. 1134 * 1135 * 559's can have either 64-word or 256-word EEPROMs, the 558 1136 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1137 * talks about the existance of 16 to 256 word EEPROMs. 1138 * 1139 * The only known sizes are 64 and 256, where the 256 version is used 1140 * by CardBus cards to store CIS information. 1141 * 1142 * The address is shifted in msb-to-lsb, and after the last 1143 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1144 * after which follows the actual data. We try to detect this zero, by 1145 * probing the data-out bit in the EEPROM control register just after 1146 * having shifted in a bit. If the bit is zero, we assume we've 1147 * shifted enough address bits. The data-out should be tri-state, 1148 * before this, which should translate to a logical one. 1149 */ 1150static void 1151fxp_autosize_eeprom(struct fxp_softc *sc) 1152{ 1153 1154 /* guess maximum size of 256 words */ 1155 sc->eeprom_size = 8; 1156 1157 /* autosize */ 1158 (void) fxp_eeprom_getword(sc, 0, 1); 1159} 1160 1161static void 1162fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1163{ 1164 int i; 1165 1166 for (i = 0; i < words; i++) 1167 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1168} 1169 1170static void 1171fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1172{ 1173 int i; 1174 1175 for (i = 0; i < words; i++) 1176 fxp_eeprom_putword(sc, offset + i, data[i]); 1177} 1178 1179/* 1180 * Grab the softc lock and call the real fxp_start_body() routine 1181 */ 1182static void 1183fxp_start(struct ifnet *ifp) 1184{ 1185 struct fxp_softc *sc = ifp->if_softc; 1186 1187 FXP_LOCK(sc); 1188 fxp_start_body(ifp); 1189 FXP_UNLOCK(sc); 1190} 1191 1192/* 1193 * Start packet transmission on the interface. 1194 * This routine must be called with the softc lock held, and is an 1195 * internal entry point only. 1196 */ 1197static void 1198fxp_start_body(struct ifnet *ifp) 1199{ 1200 struct fxp_softc *sc = ifp->if_softc; 1201 struct mbuf *mb_head; 1202 int error, txqueued; 1203 1204 FXP_LOCK_ASSERT(sc, MA_OWNED); 1205 1206 /* 1207 * See if we need to suspend xmit until the multicast filter 1208 * has been reprogrammed (which can only be done at the head 1209 * of the command chain). 1210 */ 1211 if (sc->need_mcsetup) 1212 return; 1213 1214 /* 1215 * We're finished if there is nothing more to add to the list or if 1216 * we're all filled up with buffers to transmit. 1217 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1218 * a NOP command when needed. 1219 */ 1220 txqueued = 0; 1221 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1222 sc->tx_queued < FXP_NTXCB - 1) { 1223 1224 /* 1225 * Grab a packet to transmit. 1226 */ 1227 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1228 if (mb_head == NULL) 1229 break; 1230 1231 error = fxp_encap(sc, mb_head); 1232 if (error) 1233 break; 1234 txqueued = 1; 1235 } 1236 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1237 1238 /* 1239 * We're finished. If we added to the list, issue a RESUME to get DMA 1240 * going again if suspended. 1241 */ 1242 if (txqueued) { 1243 fxp_scb_wait(sc); 1244 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1245 } 1246} 1247 1248static int 1249fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1250{ 1251 struct ifnet *ifp; 1252 struct mbuf *m; 1253 struct fxp_tx *txp; 1254 struct fxp_cb_tx *cbp; 1255 bus_dma_segment_t segs[FXP_NTXSEG]; 1256 int chainlen, error, i, nseg; 1257 1258 FXP_LOCK_ASSERT(sc, MA_OWNED); 1259 ifp = sc->ifp; 1260 1261 /* 1262 * Get pointer to next available tx desc. 1263 */ 1264 txp = sc->fxp_desc.tx_last->tx_next; 1265 1266 /* 1267 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1268 * Ethernet Controller Family Open Source Software 1269 * Developer Manual says: 1270 * Using software parsing is only allowed with legal 1271 * TCP/IP or UDP/IP packets. 1272 * ... 1273 * For all other datagrams, hardware parsing must 1274 * be used. 1275 * Software parsing appears to truncate ICMP and 1276 * fragmented UDP packets that contain one to three 1277 * bytes in the second (and final) mbuf of the packet. 1278 */ 1279 if (sc->flags & FXP_FLAG_EXT_RFA) 1280 txp->tx_cb->ipcb_ip_activation_high = 1281 FXP_IPCB_HARDWAREPARSING_ENABLE; 1282 1283 /* 1284 * Deal with TCP/IP checksum offload. Note that 1285 * in order for TCP checksum offload to work, 1286 * the pseudo header checksum must have already 1287 * been computed and stored in the checksum field 1288 * in the TCP header. The stack should have 1289 * already done this for us. 1290 */ 1291 if (m_head->m_pkthdr.csum_flags) { 1292 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1293 txp->tx_cb->ipcb_ip_schedule = 1294 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1295 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1296 txp->tx_cb->ipcb_ip_schedule |= 1297 FXP_IPCB_TCP_PACKET; 1298 } 1299 1300#ifdef FXP_IP_CSUM_WAR 1301 /* 1302 * XXX The 82550 chip appears to have trouble 1303 * dealing with IP header checksums in very small 1304 * datagrams, namely fragments from 1 to 3 bytes 1305 * in size. For example, say you want to transmit 1306 * a UDP packet of 1473 bytes. The packet will be 1307 * fragmented over two IP datagrams, the latter 1308 * containing only one byte of data. The 82550 will 1309 * botch the header checksum on the 1-byte fragment. 1310 * As long as the datagram contains 4 or more bytes 1311 * of data, you're ok. 1312 * 1313 * The following code attempts to work around this 1314 * problem: if the datagram is less than 38 bytes 1315 * in size (14 bytes ether header, 20 bytes IP header, 1316 * plus 4 bytes of data), we punt and compute the IP 1317 * header checksum by hand. This workaround doesn't 1318 * work very well, however, since it can be fooled 1319 * by things like VLAN tags and IP options that make 1320 * the header sizes/offsets vary. 1321 */ 1322 1323 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1324 if (m_head->m_pkthdr.len < 38) { 1325 struct ip *ip; 1326 m_head->m_data += ETHER_HDR_LEN; 1327 ip = mtod(mb_head, struct ip *); 1328 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1329 m_head->m_data -= ETHER_HDR_LEN; 1330 } else { 1331 txp->tx_cb->ipcb_ip_activation_high = 1332 FXP_IPCB_HARDWAREPARSING_ENABLE; 1333 txp->tx_cb->ipcb_ip_schedule |= 1334 FXP_IPCB_IP_CHECKSUM_ENABLE; 1335 } 1336 } 1337#endif 1338 } 1339 1340 chainlen = 0; 1341 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1342 chainlen++; 1343 if (chainlen > sc->maxtxseg) { 1344 struct mbuf *mn; 1345 1346 /* 1347 * We ran out of segments. We have to recopy this 1348 * mbuf chain first. Bail out if we can't get the 1349 * new buffers. 1350 */ 1351 mn = m_defrag(m_head, M_DONTWAIT); 1352 if (mn == NULL) { 1353 m_freem(m_head); 1354 return (-1); 1355 } else { 1356 m_head = mn; 1357 } 1358 } 1359 1360 /* 1361 * Go through each of the mbufs in the chain and initialize 1362 * the transmit buffer descriptors with the physical address 1363 * and size of the mbuf. 1364 */ 1365 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1366 m_head, segs, &nseg, 0); 1367 if (error) { 1368 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1369 m_freem(m_head); 1370 return (-1); 1371 } 1372 1373 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1374 1375 cbp = txp->tx_cb; 1376 for (i = 0; i < nseg; i++) { 1377 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1378 /* 1379 * If this is an 82550/82551, then we're using extended 1380 * TxCBs _and_ we're using checksum offload. This means 1381 * that the TxCB is really an IPCB. One major difference 1382 * between the two is that with plain extended TxCBs, 1383 * the bottom half of the TxCB contains two entries from 1384 * the TBD array, whereas IPCBs contain just one entry: 1385 * one entry (8 bytes) has been sacrificed for the TCP/IP 1386 * checksum offload control bits. So to make things work 1387 * right, we have to start filling in the TBD array 1388 * starting from a different place depending on whether 1389 * the chip is an 82550/82551 or not. 1390 */ 1391 if (sc->flags & FXP_FLAG_EXT_RFA) { 1392 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1393 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1394 } else { 1395 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1396 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1397 } 1398 } 1399 cbp->tbd_number = nseg; 1400 1401 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1402 txp->tx_mbuf = m_head; 1403 txp->tx_cb->cb_status = 0; 1404 txp->tx_cb->byte_count = 0; 1405 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1406 txp->tx_cb->cb_command = 1407 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1408 FXP_CB_COMMAND_S); 1409 } else { 1410 txp->tx_cb->cb_command = 1411 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1412 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1413 /* 1414 * Set a 5 second timer just in case we don't hear 1415 * from the card again. 1416 */ 1417 ifp->if_timer = 5; 1418 } 1419 txp->tx_cb->tx_threshold = tx_threshold; 1420 1421 /* 1422 * Advance the end of list forward. 1423 */ 1424 1425#ifdef __alpha__ 1426 /* 1427 * On platforms which can't access memory in 16-bit 1428 * granularities, we must prevent the card from DMA'ing 1429 * up the status while we update the command field. 1430 * This could cause us to overwrite the completion status. 1431 * XXX This is probably bogus and we're _not_ looking 1432 * for atomicity here. 1433 */ 1434 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1435 htole16(FXP_CB_COMMAND_S)); 1436#else 1437 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1438#endif /*__alpha__*/ 1439 sc->fxp_desc.tx_last = txp; 1440 1441 /* 1442 * Advance the beginning of the list forward if there are 1443 * no other packets queued (when nothing is queued, tx_first 1444 * sits on the last TxCB that was sent out). 1445 */ 1446 if (sc->tx_queued == 0) 1447 sc->fxp_desc.tx_first = txp; 1448 1449 sc->tx_queued++; 1450 1451 /* 1452 * Pass packet to bpf if there is a listener. 1453 */ 1454 BPF_MTAP(ifp, m_head); 1455 return (0); 1456} 1457 1458#ifdef DEVICE_POLLING 1459static poll_handler_t fxp_poll; 1460 1461static void 1462fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1463{ 1464 struct fxp_softc *sc = ifp->if_softc; 1465 uint8_t statack; 1466 1467 FXP_LOCK(sc); 1468 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1469 ether_poll_deregister(ifp); 1470 cmd = POLL_DEREGISTER; 1471 } 1472 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1473 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1474 FXP_UNLOCK(sc); 1475 return; 1476 } 1477 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1478 FXP_SCB_STATACK_FR; 1479 if (cmd == POLL_AND_CHECK_STATUS) { 1480 uint8_t tmp; 1481 1482 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1483 if (tmp == 0xff || tmp == 0) { 1484 FXP_UNLOCK(sc); 1485 return; /* nothing to do */ 1486 } 1487 tmp &= ~statack; 1488 /* ack what we can */ 1489 if (tmp != 0) 1490 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1491 statack |= tmp; 1492 } 1493 fxp_intr_body(sc, ifp, statack, count); 1494 FXP_UNLOCK(sc); 1495} 1496#endif /* DEVICE_POLLING */ 1497 1498/* 1499 * Process interface interrupts. 1500 */ 1501static void 1502fxp_intr(void *xsc) 1503{ 1504 struct fxp_softc *sc = xsc; 1505 struct ifnet *ifp = sc->ifp; 1506 uint8_t statack; 1507 1508 FXP_LOCK(sc); 1509 if (sc->suspended) { 1510 FXP_UNLOCK(sc); 1511 return; 1512 } 1513 1514#ifdef DEVICE_POLLING 1515 if (ifp->if_flags & IFF_POLLING) { 1516 FXP_UNLOCK(sc); 1517 return; 1518 } 1519 if ((ifp->if_capenable & IFCAP_POLLING) && 1520 ether_poll_register(fxp_poll, ifp)) { 1521 /* disable interrupts */ 1522 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1523 FXP_UNLOCK(sc); 1524 fxp_poll(ifp, 0, 1); 1525 return; 1526 } 1527#endif 1528 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1529 /* 1530 * It should not be possible to have all bits set; the 1531 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1532 * all bits are set, this may indicate that the card has 1533 * been physically ejected, so ignore it. 1534 */ 1535 if (statack == 0xff) { 1536 FXP_UNLOCK(sc); 1537 return; 1538 } 1539 1540 /* 1541 * First ACK all the interrupts in this pass. 1542 */ 1543 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1544 fxp_intr_body(sc, ifp, statack, -1); 1545 } 1546 FXP_UNLOCK(sc); 1547} 1548 1549static void 1550fxp_txeof(struct fxp_softc *sc) 1551{ 1552 struct fxp_tx *txp; 1553 1554 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1555 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1556 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1557 txp = txp->tx_next) { 1558 if (txp->tx_mbuf != NULL) { 1559 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1560 BUS_DMASYNC_POSTWRITE); 1561 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1562 m_freem(txp->tx_mbuf); 1563 txp->tx_mbuf = NULL; 1564 /* clear this to reset csum offload bits */ 1565 txp->tx_cb->tbd[0].tb_addr = 0; 1566 } 1567 sc->tx_queued--; 1568 } 1569 sc->fxp_desc.tx_first = txp; 1570 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1571} 1572 1573static void 1574fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1575 int count) 1576{ 1577 struct mbuf *m; 1578 struct fxp_rx *rxp; 1579 struct fxp_rfa *rfa; 1580 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1581 1582 FXP_LOCK_ASSERT(sc, MA_OWNED); 1583 if (rnr) 1584 sc->rnr++; 1585#ifdef DEVICE_POLLING 1586 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1587 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1588 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1589 rnr = 1; 1590 } 1591#endif 1592 1593 /* 1594 * Free any finished transmit mbuf chains. 1595 * 1596 * Handle the CNA event likt a CXTNO event. It used to 1597 * be that this event (control unit not ready) was not 1598 * encountered, but it is now with the SMPng modifications. 1599 * The exact sequence of events that occur when the interface 1600 * is brought up are different now, and if this event 1601 * goes unhandled, the configuration/rxfilter setup sequence 1602 * can stall for several seconds. The result is that no 1603 * packets go out onto the wire for about 5 to 10 seconds 1604 * after the interface is ifconfig'ed for the first time. 1605 */ 1606 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1607 fxp_txeof(sc); 1608 1609 ifp->if_timer = 0; 1610 if (sc->tx_queued == 0) { 1611 if (sc->need_mcsetup) 1612 fxp_mc_setup(sc); 1613 } 1614 /* 1615 * Try to start more packets transmitting. 1616 */ 1617 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1618 fxp_start_body(ifp); 1619 } 1620 1621 /* 1622 * Just return if nothing happened on the receive side. 1623 */ 1624 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1625 return; 1626 1627 /* 1628 * Process receiver interrupts. If a no-resource (RNR) 1629 * condition exists, get whatever packets we can and 1630 * re-start the receiver. 1631 * 1632 * When using polling, we do not process the list to completion, 1633 * so when we get an RNR interrupt we must defer the restart 1634 * until we hit the last buffer with the C bit set. 1635 * If we run out of cycles and rfa_headm has the C bit set, 1636 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1637 * that the info will be used in the subsequent polling cycle. 1638 */ 1639 for (;;) { 1640 rxp = sc->fxp_desc.rx_head; 1641 m = rxp->rx_mbuf; 1642 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1643 RFA_ALIGNMENT_FUDGE); 1644 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1645 BUS_DMASYNC_POSTREAD); 1646 1647#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1648 if (count >= 0 && count-- == 0) { 1649 if (rnr) { 1650 /* Defer RNR processing until the next time. */ 1651 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1652 rnr = 0; 1653 } 1654 break; 1655 } 1656#endif /* DEVICE_POLLING */ 1657 1658 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1659 break; 1660 1661 /* 1662 * Advance head forward. 1663 */ 1664 sc->fxp_desc.rx_head = rxp->rx_next; 1665 1666 /* 1667 * Add a new buffer to the receive chain. 1668 * If this fails, the old buffer is recycled 1669 * instead. 1670 */ 1671 if (fxp_add_rfabuf(sc, rxp) == 0) { 1672 int total_len; 1673 1674 /* 1675 * Fetch packet length (the top 2 bits of 1676 * actual_size are flags set by the controller 1677 * upon completion), and drop the packet in case 1678 * of bogus length or CRC errors. 1679 */ 1680 total_len = le16toh(rfa->actual_size) & 0x3fff; 1681 if (total_len < sizeof(struct ether_header) || 1682 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1683 sc->rfa_size || 1684 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1685 m_freem(m); 1686 continue; 1687 } 1688 1689 /* Do IP checksum checking. */ 1690 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1691 if (rfa->rfax_csum_sts & 1692 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1693 m->m_pkthdr.csum_flags |= 1694 CSUM_IP_CHECKED; 1695 if (rfa->rfax_csum_sts & 1696 FXP_RFDX_CS_IP_CSUM_VALID) 1697 m->m_pkthdr.csum_flags |= 1698 CSUM_IP_VALID; 1699 if ((rfa->rfax_csum_sts & 1700 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1701 (rfa->rfax_csum_sts & 1702 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1703 m->m_pkthdr.csum_flags |= 1704 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1705 m->m_pkthdr.csum_data = 0xffff; 1706 } 1707 } 1708 1709 m->m_pkthdr.len = m->m_len = total_len; 1710 m->m_pkthdr.rcvif = ifp; 1711 1712 /* 1713 * Drop locks before calling if_input() since it 1714 * may re-enter fxp_start() in the netisr case. 1715 * This would result in a lock reversal. Better 1716 * performance might be obtained by chaining all 1717 * packets received, dropping the lock, and then 1718 * calling if_input() on each one. 1719 */ 1720 FXP_UNLOCK(sc); 1721 (*ifp->if_input)(ifp, m); 1722 FXP_LOCK(sc); 1723 } 1724 } 1725 if (rnr) { 1726 fxp_scb_wait(sc); 1727 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1728 sc->fxp_desc.rx_head->rx_addr); 1729 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1730 } 1731} 1732 1733/* 1734 * Update packet in/out/collision statistics. The i82557 doesn't 1735 * allow you to access these counters without doing a fairly 1736 * expensive DMA to get _all_ of the statistics it maintains, so 1737 * we do this operation here only once per second. The statistics 1738 * counters in the kernel are updated from the previous dump-stats 1739 * DMA and then a new dump-stats DMA is started. The on-chip 1740 * counters are zeroed when the DMA completes. If we can't start 1741 * the DMA immediately, we don't wait - we just prepare to read 1742 * them again next time. 1743 */ 1744static void 1745fxp_tick(void *xsc) 1746{ 1747 struct fxp_softc *sc = xsc; 1748 struct ifnet *ifp = sc->ifp; 1749 struct fxp_stats *sp = sc->fxp_stats; 1750 int s; 1751 1752 FXP_LOCK(sc); 1753 s = splimp(); 1754 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1755 ifp->if_opackets += le32toh(sp->tx_good); 1756 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1757 if (sp->rx_good) { 1758 ifp->if_ipackets += le32toh(sp->rx_good); 1759 sc->rx_idle_secs = 0; 1760 } else { 1761 /* 1762 * Receiver's been idle for another second. 1763 */ 1764 sc->rx_idle_secs++; 1765 } 1766 ifp->if_ierrors += 1767 le32toh(sp->rx_crc_errors) + 1768 le32toh(sp->rx_alignment_errors) + 1769 le32toh(sp->rx_rnr_errors) + 1770 le32toh(sp->rx_overrun_errors); 1771 /* 1772 * If any transmit underruns occured, bump up the transmit 1773 * threshold by another 512 bytes (64 * 8). 1774 */ 1775 if (sp->tx_underruns) { 1776 ifp->if_oerrors += le32toh(sp->tx_underruns); 1777 if (tx_threshold < 192) 1778 tx_threshold += 64; 1779 } 1780 1781 /* 1782 * Release any xmit buffers that have completed DMA. This isn't 1783 * strictly necessary to do here, but it's advantagous for mbufs 1784 * with external storage to be released in a timely manner rather 1785 * than being defered for a potentially long time. This limits 1786 * the delay to a maximum of one second. 1787 */ 1788 fxp_txeof(sc); 1789 1790 /* 1791 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1792 * then assume the receiver has locked up and attempt to clear 1793 * the condition by reprogramming the multicast filter. This is 1794 * a work-around for a bug in the 82557 where the receiver locks 1795 * up if it gets certain types of garbage in the syncronization 1796 * bits prior to the packet header. This bug is supposed to only 1797 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1798 * mode as well (perhaps due to a 10/100 speed transition). 1799 */ 1800 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1801 sc->rx_idle_secs = 0; 1802 fxp_mc_setup(sc); 1803 } 1804 /* 1805 * If there is no pending command, start another stats 1806 * dump. Otherwise punt for now. 1807 */ 1808 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1809 /* 1810 * Start another stats dump. 1811 */ 1812 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1813 BUS_DMASYNC_PREREAD); 1814 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1815 } else { 1816 /* 1817 * A previous command is still waiting to be accepted. 1818 * Just zero our copy of the stats and wait for the 1819 * next timer event to update them. 1820 */ 1821 sp->tx_good = 0; 1822 sp->tx_underruns = 0; 1823 sp->tx_total_collisions = 0; 1824 1825 sp->rx_good = 0; 1826 sp->rx_crc_errors = 0; 1827 sp->rx_alignment_errors = 0; 1828 sp->rx_rnr_errors = 0; 1829 sp->rx_overrun_errors = 0; 1830 } 1831 if (sc->miibus != NULL) 1832 mii_tick(device_get_softc(sc->miibus)); 1833 1834 /* 1835 * Schedule another timeout one second from now. 1836 */ 1837 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1838 FXP_UNLOCK(sc); 1839 splx(s); 1840} 1841 1842/* 1843 * Stop the interface. Cancels the statistics updater and resets 1844 * the interface. 1845 */ 1846static void 1847fxp_stop(struct fxp_softc *sc) 1848{ 1849 struct ifnet *ifp = sc->ifp; 1850 struct fxp_tx *txp; 1851 int i; 1852 1853 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1854 ifp->if_timer = 0; 1855 1856#ifdef DEVICE_POLLING 1857 ether_poll_deregister(ifp); 1858#endif 1859 /* 1860 * Cancel stats updater. 1861 */ 1862 callout_stop(&sc->stat_ch); 1863 1864 /* 1865 * Issue software reset, which also unloads the microcode. 1866 */ 1867 sc->flags &= ~FXP_FLAG_UCODE; 1868 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1869 DELAY(50); 1870 1871 /* 1872 * Release any xmit buffers. 1873 */ 1874 txp = sc->fxp_desc.tx_list; 1875 if (txp != NULL) { 1876 for (i = 0; i < FXP_NTXCB; i++) { 1877 if (txp[i].tx_mbuf != NULL) { 1878 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1879 BUS_DMASYNC_POSTWRITE); 1880 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1881 m_freem(txp[i].tx_mbuf); 1882 txp[i].tx_mbuf = NULL; 1883 /* clear this to reset csum offload bits */ 1884 txp[i].tx_cb->tbd[0].tb_addr = 0; 1885 } 1886 } 1887 } 1888 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1889 sc->tx_queued = 0; 1890} 1891 1892/* 1893 * Watchdog/transmission transmit timeout handler. Called when a 1894 * transmission is started on the interface, but no interrupt is 1895 * received before the timeout. This usually indicates that the 1896 * card has wedged for some reason. 1897 */ 1898static void 1899fxp_watchdog(struct ifnet *ifp) 1900{ 1901 struct fxp_softc *sc = ifp->if_softc; 1902 1903 FXP_LOCK(sc); 1904 device_printf(sc->dev, "device timeout\n"); 1905 ifp->if_oerrors++; 1906 1907 fxp_init_body(sc); 1908 FXP_UNLOCK(sc); 1909} 1910 1911/* 1912 * Acquire locks and then call the real initialization function. This 1913 * is necessary because ether_ioctl() calls if_init() and this would 1914 * result in mutex recursion if the mutex was held. 1915 */ 1916static void 1917fxp_init(void *xsc) 1918{ 1919 struct fxp_softc *sc = xsc; 1920 1921 FXP_LOCK(sc); 1922 fxp_init_body(sc); 1923 FXP_UNLOCK(sc); 1924} 1925 1926/* 1927 * Perform device initialization. This routine must be called with the 1928 * softc lock held. 1929 */ 1930static void 1931fxp_init_body(struct fxp_softc *sc) 1932{ 1933 struct ifnet *ifp = sc->ifp; 1934 struct fxp_cb_config *cbp; 1935 struct fxp_cb_ias *cb_ias; 1936 struct fxp_cb_tx *tcbp; 1937 struct fxp_tx *txp; 1938 struct fxp_cb_mcs *mcsp; 1939 int i, prm, s; 1940 1941 FXP_LOCK_ASSERT(sc, MA_OWNED); 1942 s = splimp(); 1943 /* 1944 * Cancel any pending I/O 1945 */ 1946 fxp_stop(sc); 1947 1948 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1949 1950 /* 1951 * Initialize base of CBL and RFA memory. Loading with zero 1952 * sets it up for regular linear addressing. 1953 */ 1954 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1955 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1956 1957 fxp_scb_wait(sc); 1958 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1959 1960 /* 1961 * Initialize base of dump-stats buffer. 1962 */ 1963 fxp_scb_wait(sc); 1964 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1965 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1966 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1967 1968 /* 1969 * Attempt to load microcode if requested. 1970 */ 1971 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1972 fxp_load_ucode(sc); 1973 1974 /* 1975 * Initialize the multicast address list. 1976 */ 1977 if (fxp_mc_addrs(sc)) { 1978 mcsp = sc->mcsp; 1979 mcsp->cb_status = 0; 1980 mcsp->cb_command = 1981 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1982 mcsp->link_addr = 0xffffffff; 1983 /* 1984 * Start the multicast setup command. 1985 */ 1986 fxp_scb_wait(sc); 1987 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1988 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1989 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1990 /* ...and wait for it to complete. */ 1991 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1992 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1993 BUS_DMASYNC_POSTWRITE); 1994 } 1995 1996 /* 1997 * We temporarily use memory that contains the TxCB list to 1998 * construct the config CB. The TxCB list memory is rebuilt 1999 * later. 2000 */ 2001 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2002 2003 /* 2004 * This bcopy is kind of disgusting, but there are a bunch of must be 2005 * zero and must be one bits in this structure and this is the easiest 2006 * way to initialize them all to proper values. 2007 */ 2008 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2009 2010 cbp->cb_status = 0; 2011 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2012 FXP_CB_COMMAND_EL); 2013 cbp->link_addr = 0xffffffff; /* (no) next command */ 2014 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2015 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2016 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2017 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2018 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2019 cbp->type_enable = 0; /* actually reserved */ 2020 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2021 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2022 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2023 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2024 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2025 cbp->late_scb = 0; /* (don't) defer SCB update */ 2026 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2027 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2028 cbp->ci_int = 1; /* interrupt on CU idle */ 2029 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2030 cbp->ext_stats_dis = 1; /* disable extended counters */ 2031 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2032 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2033 cbp->disc_short_rx = !prm; /* discard short packets */ 2034 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2035 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2036 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2037 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2038 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2039 cbp->csma_dis = 0; /* (don't) disable link */ 2040 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2041 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2042 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2043 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2044 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2045 cbp->nsai = 1; /* (don't) disable source addr insert */ 2046 cbp->preamble_length = 2; /* (7 byte) preamble */ 2047 cbp->loopback = 0; /* (don't) loopback */ 2048 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2049 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2050 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2051 cbp->promiscuous = prm; /* promiscuous mode */ 2052 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2053 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2054 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2055 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2056 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2057 2058 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2059 cbp->padding = 1; /* (do) pad short tx packets */ 2060 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2061 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2062 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2063 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2064 /* must set wake_en in PMCSR also */ 2065 cbp->force_fdx = 0; /* (don't) force full duplex */ 2066 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2067 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2068 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2069 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2070 2071 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2072 /* 2073 * The 82557 has no hardware flow control, the values 2074 * below are the defaults for the chip. 2075 */ 2076 cbp->fc_delay_lsb = 0; 2077 cbp->fc_delay_msb = 0x40; 2078 cbp->pri_fc_thresh = 3; 2079 cbp->tx_fc_dis = 0; 2080 cbp->rx_fc_restop = 0; 2081 cbp->rx_fc_restart = 0; 2082 cbp->fc_filter = 0; 2083 cbp->pri_fc_loc = 1; 2084 } else { 2085 cbp->fc_delay_lsb = 0x1f; 2086 cbp->fc_delay_msb = 0x01; 2087 cbp->pri_fc_thresh = 3; 2088 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2089 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2090 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2091 cbp->fc_filter = !prm; /* drop FC frames to host */ 2092 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2093 } 2094 2095 /* 2096 * Start the config command/DMA. 2097 */ 2098 fxp_scb_wait(sc); 2099 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2100 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2101 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2102 /* ...and wait for it to complete. */ 2103 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2104 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2105 2106 /* 2107 * Now initialize the station address. Temporarily use the TxCB 2108 * memory area like we did above for the config CB. 2109 */ 2110 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2111 cb_ias->cb_status = 0; 2112 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2113 cb_ias->link_addr = 0xffffffff; 2114 bcopy(IFP2ENADDR(sc->ifp), cb_ias->macaddr, 2115 sizeof(IFP2ENADDR(sc->ifp))); 2116 2117 /* 2118 * Start the IAS (Individual Address Setup) command/DMA. 2119 */ 2120 fxp_scb_wait(sc); 2121 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2122 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2123 /* ...and wait for it to complete. */ 2124 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2125 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2126 2127 /* 2128 * Initialize transmit control block (TxCB) list. 2129 */ 2130 txp = sc->fxp_desc.tx_list; 2131 tcbp = sc->fxp_desc.cbl_list; 2132 bzero(tcbp, FXP_TXCB_SZ); 2133 for (i = 0; i < FXP_NTXCB; i++) { 2134 txp[i].tx_mbuf = NULL; 2135 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2136 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2137 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2138 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2139 if (sc->flags & FXP_FLAG_EXT_TXCB) 2140 tcbp[i].tbd_array_addr = 2141 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2142 else 2143 tcbp[i].tbd_array_addr = 2144 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2145 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2146 } 2147 /* 2148 * Set the suspend flag on the first TxCB and start the control 2149 * unit. It will execute the NOP and then suspend. 2150 */ 2151 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2152 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2153 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2154 sc->tx_queued = 1; 2155 2156 fxp_scb_wait(sc); 2157 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2158 2159 /* 2160 * Initialize receiver buffer area - RFA. 2161 */ 2162 fxp_scb_wait(sc); 2163 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2164 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2165 2166 /* 2167 * Set current media. 2168 */ 2169 if (sc->miibus != NULL) 2170 mii_mediachg(device_get_softc(sc->miibus)); 2171 2172 ifp->if_flags |= IFF_RUNNING; 2173 ifp->if_flags &= ~IFF_OACTIVE; 2174 2175 /* 2176 * Enable interrupts. 2177 */ 2178#ifdef DEVICE_POLLING 2179 /* 2180 * ... but only do that if we are not polling. And because (presumably) 2181 * the default is interrupts on, we need to disable them explicitly! 2182 */ 2183 if ( ifp->if_flags & IFF_POLLING ) 2184 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2185 else 2186#endif /* DEVICE_POLLING */ 2187 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2188 2189 /* 2190 * Start stats updater. 2191 */ 2192 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2193 splx(s); 2194} 2195 2196static int 2197fxp_serial_ifmedia_upd(struct ifnet *ifp) 2198{ 2199 2200 return (0); 2201} 2202 2203static void 2204fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2205{ 2206 2207 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2208} 2209 2210/* 2211 * Change media according to request. 2212 */ 2213static int 2214fxp_ifmedia_upd(struct ifnet *ifp) 2215{ 2216 struct fxp_softc *sc = ifp->if_softc; 2217 struct mii_data *mii; 2218 2219 mii = device_get_softc(sc->miibus); 2220 mii_mediachg(mii); 2221 return (0); 2222} 2223 2224/* 2225 * Notify the world which media we're using. 2226 */ 2227static void 2228fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2229{ 2230 struct fxp_softc *sc = ifp->if_softc; 2231 struct mii_data *mii; 2232 2233 mii = device_get_softc(sc->miibus); 2234 mii_pollstat(mii); 2235 ifmr->ifm_active = mii->mii_media_active; 2236 ifmr->ifm_status = mii->mii_media_status; 2237 2238 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2239 sc->cu_resume_bug = 1; 2240 else 2241 sc->cu_resume_bug = 0; 2242} 2243 2244/* 2245 * Add a buffer to the end of the RFA buffer list. 2246 * Return 0 if successful, 1 for failure. A failure results in 2247 * adding the 'oldm' (if non-NULL) on to the end of the list - 2248 * tossing out its old contents and recycling it. 2249 * The RFA struct is stuck at the beginning of mbuf cluster and the 2250 * data pointer is fixed up to point just past it. 2251 */ 2252static int 2253fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2254{ 2255 struct mbuf *m; 2256 struct fxp_rfa *rfa, *p_rfa; 2257 struct fxp_rx *p_rx; 2258 bus_dmamap_t tmp_map; 2259 int error; 2260 2261 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2262 if (m == NULL) 2263 return (ENOBUFS); 2264 2265 /* 2266 * Move the data pointer up so that the incoming data packet 2267 * will be 32-bit aligned. 2268 */ 2269 m->m_data += RFA_ALIGNMENT_FUDGE; 2270 2271 /* 2272 * Get a pointer to the base of the mbuf cluster and move 2273 * data start past it. 2274 */ 2275 rfa = mtod(m, struct fxp_rfa *); 2276 m->m_data += sc->rfa_size; 2277 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2278 2279 rfa->rfa_status = 0; 2280 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2281 rfa->actual_size = 0; 2282 2283 /* 2284 * Initialize the rest of the RFA. Note that since the RFA 2285 * is misaligned, we cannot store values directly. We're thus 2286 * using the le32enc() function which handles endianness and 2287 * is also alignment-safe. 2288 */ 2289 le32enc(&rfa->link_addr, 0xffffffff); 2290 le32enc(&rfa->rbd_addr, 0xffffffff); 2291 2292 /* Map the RFA into DMA memory. */ 2293 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2294 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2295 &rxp->rx_addr, 0); 2296 if (error) { 2297 m_freem(m); 2298 return (error); 2299 } 2300 2301 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2302 tmp_map = sc->spare_map; 2303 sc->spare_map = rxp->rx_map; 2304 rxp->rx_map = tmp_map; 2305 rxp->rx_mbuf = m; 2306 2307 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2309 2310 /* 2311 * If there are other buffers already on the list, attach this 2312 * one to the end by fixing up the tail to point to this one. 2313 */ 2314 if (sc->fxp_desc.rx_head != NULL) { 2315 p_rx = sc->fxp_desc.rx_tail; 2316 p_rfa = (struct fxp_rfa *) 2317 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2318 p_rx->rx_next = rxp; 2319 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2320 p_rfa->rfa_control = 0; 2321 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2322 BUS_DMASYNC_PREWRITE); 2323 } else { 2324 rxp->rx_next = NULL; 2325 sc->fxp_desc.rx_head = rxp; 2326 } 2327 sc->fxp_desc.rx_tail = rxp; 2328 return (0); 2329} 2330 2331static volatile int 2332fxp_miibus_readreg(device_t dev, int phy, int reg) 2333{ 2334 struct fxp_softc *sc = device_get_softc(dev); 2335 int count = 10000; 2336 int value; 2337 2338 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2339 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2340 2341 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2342 && count--) 2343 DELAY(10); 2344 2345 if (count <= 0) 2346 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2347 2348 return (value & 0xffff); 2349} 2350 2351static void 2352fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2353{ 2354 struct fxp_softc *sc = device_get_softc(dev); 2355 int count = 10000; 2356 2357 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2358 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2359 (value & 0xffff)); 2360 2361 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2362 count--) 2363 DELAY(10); 2364 2365 if (count <= 0) 2366 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2367} 2368 2369static int 2370fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2371{ 2372 struct fxp_softc *sc = ifp->if_softc; 2373 struct ifreq *ifr = (struct ifreq *)data; 2374 struct mii_data *mii; 2375 int flag, mask, s, error = 0; 2376 2377 /* 2378 * Detaching causes us to call ioctl with the mutex owned. Preclude 2379 * that by saying we're busy if the lock is already held. 2380 */ 2381 if (FXP_LOCKED(sc)) 2382 return (EBUSY); 2383 2384 FXP_LOCK(sc); 2385 s = splimp(); 2386 2387 switch (command) { 2388 case SIOCSIFFLAGS: 2389 if (ifp->if_flags & IFF_ALLMULTI) 2390 sc->flags |= FXP_FLAG_ALL_MCAST; 2391 else 2392 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2393 2394 /* 2395 * If interface is marked up and not running, then start it. 2396 * If it is marked down and running, stop it. 2397 * XXX If it's up then re-initialize it. This is so flags 2398 * such as IFF_PROMISC are handled. 2399 */ 2400 if (ifp->if_flags & IFF_UP) { 2401 fxp_init_body(sc); 2402 } else { 2403 if (ifp->if_flags & IFF_RUNNING) 2404 fxp_stop(sc); 2405 } 2406 break; 2407 2408 case SIOCADDMULTI: 2409 case SIOCDELMULTI: 2410 if (ifp->if_flags & IFF_ALLMULTI) 2411 sc->flags |= FXP_FLAG_ALL_MCAST; 2412 else 2413 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2414 /* 2415 * Multicast list has changed; set the hardware filter 2416 * accordingly. 2417 */ 2418 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2419 fxp_mc_setup(sc); 2420 /* 2421 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2422 * again rather than else {}. 2423 */ 2424 if (sc->flags & FXP_FLAG_ALL_MCAST) 2425 fxp_init_body(sc); 2426 error = 0; 2427 break; 2428 2429 case SIOCSIFMEDIA: 2430 case SIOCGIFMEDIA: 2431 if (sc->miibus != NULL) { 2432 mii = device_get_softc(sc->miibus); 2433 error = ifmedia_ioctl(ifp, ifr, 2434 &mii->mii_media, command); 2435 } else { 2436 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2437 } 2438 break; 2439 2440 case SIOCSIFCAP: 2441 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2442 if (mask & IFCAP_POLLING) 2443 ifp->if_capenable ^= IFCAP_POLLING; 2444 if (mask & IFCAP_VLAN_MTU) { 2445 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2446 if (sc->revision != FXP_REV_82557) 2447 flag = FXP_FLAG_LONG_PKT_EN; 2448 else /* a hack to get long frames on the old chip */ 2449 flag = FXP_FLAG_SAVE_BAD; 2450 sc->flags ^= flag; 2451 if (ifp->if_flags & IFF_UP) 2452 fxp_init_body(sc); 2453 } 2454 break; 2455 2456 default: 2457 /* 2458 * ether_ioctl() will eventually call fxp_start() which 2459 * will result in mutex recursion so drop it first. 2460 */ 2461 FXP_UNLOCK(sc); 2462 error = ether_ioctl(ifp, command, data); 2463 } 2464 if (FXP_LOCKED(sc)) 2465 FXP_UNLOCK(sc); 2466 splx(s); 2467 return (error); 2468} 2469 2470/* 2471 * Fill in the multicast address list and return number of entries. 2472 */ 2473static int 2474fxp_mc_addrs(struct fxp_softc *sc) 2475{ 2476 struct fxp_cb_mcs *mcsp = sc->mcsp; 2477 struct ifnet *ifp = sc->ifp; 2478 struct ifmultiaddr *ifma; 2479 int nmcasts; 2480 2481 nmcasts = 0; 2482 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2483#if __FreeBSD_version < 500000 2484 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2485#else 2486 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2487#endif 2488 if (ifma->ifma_addr->sa_family != AF_LINK) 2489 continue; 2490 if (nmcasts >= MAXMCADDR) { 2491 sc->flags |= FXP_FLAG_ALL_MCAST; 2492 nmcasts = 0; 2493 break; 2494 } 2495 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2496 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2497 nmcasts++; 2498 } 2499 } 2500 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2501 return (nmcasts); 2502} 2503 2504/* 2505 * Program the multicast filter. 2506 * 2507 * We have an artificial restriction that the multicast setup command 2508 * must be the first command in the chain, so we take steps to ensure 2509 * this. By requiring this, it allows us to keep up the performance of 2510 * the pre-initialized command ring (esp. link pointers) by not actually 2511 * inserting the mcsetup command in the ring - i.e. its link pointer 2512 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2513 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2514 * lead into the regular TxCB ring when it completes. 2515 * 2516 * This function must be called at splimp. 2517 */ 2518static void 2519fxp_mc_setup(struct fxp_softc *sc) 2520{ 2521 struct fxp_cb_mcs *mcsp = sc->mcsp; 2522 struct ifnet *ifp = sc->ifp; 2523 struct fxp_tx *txp; 2524 int count; 2525 2526 FXP_LOCK_ASSERT(sc, MA_OWNED); 2527 /* 2528 * If there are queued commands, we must wait until they are all 2529 * completed. If we are already waiting, then add a NOP command 2530 * with interrupt option so that we're notified when all commands 2531 * have been completed - fxp_start() ensures that no additional 2532 * TX commands will be added when need_mcsetup is true. 2533 */ 2534 if (sc->tx_queued) { 2535 /* 2536 * need_mcsetup will be true if we are already waiting for the 2537 * NOP command to be completed (see below). In this case, bail. 2538 */ 2539 if (sc->need_mcsetup) 2540 return; 2541 sc->need_mcsetup = 1; 2542 2543 /* 2544 * Add a NOP command with interrupt so that we are notified 2545 * when all TX commands have been processed. 2546 */ 2547 txp = sc->fxp_desc.tx_last->tx_next; 2548 txp->tx_mbuf = NULL; 2549 txp->tx_cb->cb_status = 0; 2550 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2551 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2552 /* 2553 * Advance the end of list forward. 2554 */ 2555 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2556 htole16(~FXP_CB_COMMAND_S); 2557 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2558 sc->fxp_desc.tx_last = txp; 2559 sc->tx_queued++; 2560 /* 2561 * Issue a resume in case the CU has just suspended. 2562 */ 2563 fxp_scb_wait(sc); 2564 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2565 /* 2566 * Set a 5 second timer just in case we don't hear from the 2567 * card again. 2568 */ 2569 ifp->if_timer = 5; 2570 2571 return; 2572 } 2573 sc->need_mcsetup = 0; 2574 2575 /* 2576 * Initialize multicast setup descriptor. 2577 */ 2578 mcsp->cb_status = 0; 2579 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2580 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2581 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2582 txp = &sc->fxp_desc.mcs_tx; 2583 txp->tx_mbuf = NULL; 2584 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2585 txp->tx_next = sc->fxp_desc.tx_list; 2586 (void) fxp_mc_addrs(sc); 2587 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2588 sc->tx_queued = 1; 2589 2590 /* 2591 * Wait until command unit is not active. This should never 2592 * be the case when nothing is queued, but make sure anyway. 2593 */ 2594 count = 100; 2595 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2596 FXP_SCB_CUS_ACTIVE && --count) 2597 DELAY(10); 2598 if (count == 0) { 2599 device_printf(sc->dev, "command queue timeout\n"); 2600 return; 2601 } 2602 2603 /* 2604 * Start the multicast setup command. 2605 */ 2606 fxp_scb_wait(sc); 2607 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2608 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2609 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2610 2611 ifp->if_timer = 2; 2612 return; 2613} 2614 2615static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2616static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2617static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2618static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2619static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2620static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2621static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2622 2623#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2624 2625struct ucode { 2626 uint32_t revision; 2627 uint32_t *ucode; 2628 int length; 2629 u_short int_delay_offset; 2630 u_short bundle_max_offset; 2631} ucode_table[] = { 2632 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2633 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2634 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2635 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2636 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2637 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2638 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2639 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2641 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2643 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2644 { 0, NULL, 0, 0, 0 } 2645}; 2646 2647static void 2648fxp_load_ucode(struct fxp_softc *sc) 2649{ 2650 struct ucode *uc; 2651 struct fxp_cb_ucode *cbp; 2652 int i; 2653 2654 for (uc = ucode_table; uc->ucode != NULL; uc++) 2655 if (sc->revision == uc->revision) 2656 break; 2657 if (uc->ucode == NULL) 2658 return; 2659 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2660 cbp->cb_status = 0; 2661 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2662 cbp->link_addr = 0xffffffff; /* (no) next command */ 2663 for (i = 0; i < uc->length; i++) 2664 cbp->ucode[i] = htole32(uc->ucode[i]); 2665 if (uc->int_delay_offset) 2666 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2667 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2668 if (uc->bundle_max_offset) 2669 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2670 htole16(sc->tunable_bundle_max); 2671 /* 2672 * Download the ucode to the chip. 2673 */ 2674 fxp_scb_wait(sc); 2675 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2676 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2677 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2678 /* ...and wait for it to complete. */ 2679 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2680 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2681 device_printf(sc->dev, 2682 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2683 sc->tunable_int_delay, 2684 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2685 sc->flags |= FXP_FLAG_UCODE; 2686} 2687 2688static int 2689sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2690{ 2691 int error, value; 2692 2693 value = *(int *)arg1; 2694 error = sysctl_handle_int(oidp, &value, 0, req); 2695 if (error || !req->newptr) 2696 return (error); 2697 if (value < low || value > high) 2698 return (EINVAL); 2699 *(int *)arg1 = value; 2700 return (0); 2701} 2702 2703/* 2704 * Interrupt delay is expressed in microseconds, a multiplier is used 2705 * to convert this to the appropriate clock ticks before using. 2706 */ 2707static int 2708sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2709{ 2710 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2711} 2712 2713static int 2714sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2715{ 2716 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2717} 2718