if_fxp.c revision 147029
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 147029 2005-06-05 22:50:55Z imp $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194}; 195 196#ifdef FXP_IP_CSUM_WAR 197#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198#else 199#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200#endif 201 202static int fxp_probe(device_t dev); 203static int fxp_attach(device_t dev); 204static int fxp_detach(device_t dev); 205static int fxp_shutdown(device_t dev); 206static int fxp_suspend(device_t dev); 207static int fxp_resume(device_t dev); 208 209static void fxp_intr(void *xsc); 210static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212static void fxp_init(void *xsc); 213static void fxp_init_body(struct fxp_softc *sc); 214static void fxp_tick(void *xsc); 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218static void fxp_stop(struct fxp_softc *sc); 219static void fxp_release(struct fxp_softc *sc); 220static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222static void fxp_watchdog(struct ifnet *ifp); 223static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225static int fxp_mc_addrs(struct fxp_softc *sc); 226static void fxp_mc_setup(struct fxp_softc *sc); 227static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231static void fxp_autosize_eeprom(struct fxp_softc *sc); 232static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236static int fxp_ifmedia_upd(struct ifnet *ifp); 237static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245static void fxp_load_ucode(struct fxp_softc *sc); 246static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250static void fxp_scb_wait(struct fxp_softc *sc); 251static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270}; 271 272static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276}; 277 278static devclass_t fxp_devclass; 279 280DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284/* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288static void 289fxp_scb_wait(struct fxp_softc *sc) 290{ 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301} 302 303static void 304fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305{ 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312} 313 314static void 315fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317{ 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327} 328 329/* 330 * Return identification string if this device is ours. 331 */ 332static int 333fxp_probe(device_t dev) 334{ 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351} 352 353static void 354fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355{ 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 int i, rid, m1, m2, prefer_iomap; 377 int error, s; 378 379 error = 0; 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 383 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 384 MTX_DEF); 385 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 386 fxp_serial_ifmedia_sts); 387 388 s = splimp(); 389 390 /* 391 * Enable bus mastering. 392 */ 393 pci_enable_busmaster(dev); 394 val = pci_read_config(dev, PCIR_COMMAND, 2); 395 396 /* 397 * Figure out which we should try first - memory mapping or i/o mapping? 398 * We default to memory mapping. Then we accept an override from the 399 * command line. Then we check to see which one is enabled. 400 */ 401 m1 = PCIM_CMD_MEMEN; 402 m2 = PCIM_CMD_PORTEN; 403 prefer_iomap = 0; 404 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 405 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 406 m1 = PCIM_CMD_PORTEN; 407 m2 = PCIM_CMD_MEMEN; 408 } 409 410 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 411 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 412 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 413 if (sc->mem == NULL) { 414 sc->rtp = 415 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 416 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 417 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 418 RF_ACTIVE); 419 } 420 421 if (!sc->mem) { 422 error = ENXIO; 423 goto fail; 424 } 425 if (bootverbose) { 426 device_printf(dev, "using %s space register mapping\n", 427 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 428 } 429 430 sc->sc_st = rman_get_bustag(sc->mem); 431 sc->sc_sh = rman_get_bushandle(sc->mem); 432 433 /* 434 * Allocate our interrupt. 435 */ 436 rid = 0; 437 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 438 RF_SHAREABLE | RF_ACTIVE); 439 if (sc->irq == NULL) { 440 device_printf(dev, "could not map interrupt\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 445 /* 446 * Reset to a stable state. 447 */ 448 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 449 DELAY(10); 450 451 /* 452 * Find out how large of an SEEPROM we have. 453 */ 454 fxp_autosize_eeprom(sc); 455 456 /* 457 * Find out the chip revision; lump all 82557 revs together. 458 */ 459 fxp_read_eeprom(sc, &data, 5, 1); 460 if ((data >> 8) == 1) 461 sc->revision = FXP_REV_82557; 462 else 463 sc->revision = pci_get_revid(dev); 464 465 /* 466 * Determine whether we must use the 503 serial interface. 467 */ 468 fxp_read_eeprom(sc, &data, 6, 1); 469 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 470 && (data & FXP_PHY_SERIAL_ONLY)) 471 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 472 473 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 475 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 476 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 477 "FXP driver receive interrupt microcode bundling delay"); 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 480 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 481 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 482 "FXP driver receive interrupt microcode bundle size limit"); 483 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 486 "FXP RNR events"); 487 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 490 "FXP flow control disabled"); 491 492 /* 493 * Pull in device tunables. 494 */ 495 sc->tunable_int_delay = TUNABLE_INT_DELAY; 496 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 497 sc->tunable_noflow = 1; 498 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 499 "int_delay", &sc->tunable_int_delay); 500 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 501 "bundle_max", &sc->tunable_bundle_max); 502 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 503 "noflow", &sc->tunable_noflow); 504 sc->rnr = 0; 505 506 /* 507 * Enable workarounds for certain chip revision deficiencies. 508 * 509 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 510 * some systems based a normal 82559 design, have a defect where 511 * the chip can cause a PCI protocol violation if it receives 512 * a CU_RESUME command when it is entering the IDLE state. The 513 * workaround is to disable Dynamic Standby Mode, so the chip never 514 * deasserts CLKRUN#, and always remains in an active state. 515 * 516 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 517 */ 518 i = pci_get_device(dev); 519 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 520 sc->revision >= FXP_REV_82559_A0) { 521 fxp_read_eeprom(sc, &data, 10, 1); 522 if (data & 0x02) { /* STB enable */ 523 uint16_t cksum; 524 int i; 525 526 device_printf(dev, 527 "Disabling dynamic standby mode in EEPROM\n"); 528 data &= ~0x02; 529 fxp_write_eeprom(sc, &data, 10, 1); 530 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 531 cksum = 0; 532 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 533 fxp_read_eeprom(sc, &data, i, 1); 534 cksum += data; 535 } 536 i = (1 << sc->eeprom_size) - 1; 537 cksum = 0xBABA - cksum; 538 fxp_read_eeprom(sc, &data, i, 1); 539 fxp_write_eeprom(sc, &cksum, i, 1); 540 device_printf(dev, 541 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 542 i, data, cksum); 543#if 1 544 /* 545 * If the user elects to continue, try the software 546 * workaround, as it is better than nothing. 547 */ 548 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 549#endif 550 } 551 } 552 553 /* 554 * If we are not a 82557 chip, we can enable extended features. 555 */ 556 if (sc->revision != FXP_REV_82557) { 557 /* 558 * If MWI is enabled in the PCI configuration, and there 559 * is a valid cacheline size (8 or 16 dwords), then tell 560 * the board to turn on MWI. 561 */ 562 if (val & PCIM_CMD_MWRICEN && 563 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 564 sc->flags |= FXP_FLAG_MWI_ENABLE; 565 566 /* turn on the extended TxCB feature */ 567 sc->flags |= FXP_FLAG_EXT_TXCB; 568 569 /* enable reception of long frames for VLAN */ 570 sc->flags |= FXP_FLAG_LONG_PKT_EN; 571 } else { 572 /* a hack to get long VLAN frames on a 82557 */ 573 sc->flags |= FXP_FLAG_SAVE_BAD; 574 } 575 576 /* 577 * Enable use of extended RFDs and TCBs for 82550 578 * and later chips. Note: we need extended TXCB support 579 * too, but that's already enabled by the code above. 580 * Be careful to do this only on the right devices. 581 */ 582 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 583 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 584 || sc->revision == FXP_REV_82551_10) { 585 sc->rfa_size = sizeof (struct fxp_rfa); 586 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 587 sc->flags |= FXP_FLAG_EXT_RFA; 588 } else { 589 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 590 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 591 } 592 593 /* 594 * Allocate DMA tags and DMA safe memory. 595 */ 596 sc->maxtxseg = FXP_NTXSEG; 597 if (sc->flags & FXP_FLAG_EXT_RFA) 598 sc->maxtxseg--; 599 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 600 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 601 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 602 &sc->fxp_mtag); 603 if (error) { 604 device_printf(dev, "could not allocate dma tag\n"); 605 goto fail; 606 } 607 608 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 609 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 610 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 611 &sc->fxp_stag); 612 if (error) { 613 device_printf(dev, "could not allocate dma tag\n"); 614 goto fail; 615 } 616 617 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 618 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 619 if (error) 620 goto fail; 621 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 622 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 623 if (error) { 624 device_printf(dev, "could not map the stats buffer\n"); 625 goto fail; 626 } 627 628 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 629 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 630 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 631 if (error) { 632 device_printf(dev, "could not allocate dma tag\n"); 633 goto fail; 634 } 635 636 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 637 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 638 if (error) 639 goto fail; 640 641 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 642 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 643 &sc->fxp_desc.cbl_addr, 0); 644 if (error) { 645 device_printf(dev, "could not map DMA memory\n"); 646 goto fail; 647 } 648 649 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 650 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 651 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 652 &sc->mcs_tag); 653 if (error) { 654 device_printf(dev, "could not allocate dma tag\n"); 655 goto fail; 656 } 657 658 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 659 BUS_DMA_NOWAIT, &sc->mcs_map); 660 if (error) 661 goto fail; 662 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 663 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 664 if (error) { 665 device_printf(dev, "can't map the multicast setup command\n"); 666 goto fail; 667 } 668 669 /* 670 * Pre-allocate the TX DMA maps and setup the pointers to 671 * the TX command blocks. 672 */ 673 txp = sc->fxp_desc.tx_list; 674 tcbp = sc->fxp_desc.cbl_list; 675 for (i = 0; i < FXP_NTXCB; i++) { 676 txp[i].tx_cb = tcbp + i; 677 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 678 if (error) { 679 device_printf(dev, "can't create DMA map for TX\n"); 680 goto fail; 681 } 682 } 683 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 684 if (error) { 685 device_printf(dev, "can't create spare DMA map\n"); 686 goto fail; 687 } 688 689 /* 690 * Pre-allocate our receive buffers. 691 */ 692 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 693 for (i = 0; i < FXP_NRFABUFS; i++) { 694 rxp = &sc->fxp_desc.rx_list[i]; 695 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 696 if (error) { 697 device_printf(dev, "can't create DMA map for RX\n"); 698 goto fail; 699 } 700 if (fxp_add_rfabuf(sc, rxp) != 0) { 701 error = ENOMEM; 702 goto fail; 703 } 704 } 705 706 /* 707 * Read MAC address. 708 */ 709 fxp_read_eeprom(sc, myea, 0, 3); 710 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 711 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 712 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 713 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 714 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 715 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 716 if (bootverbose) { 717 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 718 pci_get_vendor(dev), pci_get_device(dev), 719 pci_get_subvendor(dev), pci_get_subdevice(dev), 720 pci_get_revid(dev)); 721 fxp_read_eeprom(sc, &data, 10, 1); 722 device_printf(dev, "Dynamic Standby mode is %s\n", 723 data & 0x02 ? "enabled" : "disabled"); 724 } 725 726 /* 727 * If this is only a 10Mbps device, then there is no MII, and 728 * the PHY will use a serial interface instead. 729 * 730 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 731 * doesn't have a programming interface of any sort. The 732 * media is sensed automatically based on how the link partner 733 * is configured. This is, in essence, manual configuration. 734 */ 735 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 736 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 737 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 738 } else { 739 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 740 fxp_ifmedia_sts)) { 741 device_printf(dev, "MII without any PHY!\n"); 742 error = ENXIO; 743 goto fail; 744 } 745 } 746 747 ifp = &sc->arpcom.ac_if; 748 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 749 ifp->if_baudrate = 100000000; 750 ifp->if_init = fxp_init; 751 ifp->if_softc = sc; 752 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 753 ifp->if_ioctl = fxp_ioctl; 754 ifp->if_start = fxp_start; 755 ifp->if_watchdog = fxp_watchdog; 756 757 ifp->if_capabilities = ifp->if_capenable = 0; 758 759 /* Enable checksum offload for 82550 or better chips */ 760 if (sc->flags & FXP_FLAG_EXT_RFA) { 761 ifp->if_hwassist = FXP_CSUM_FEATURES; 762 ifp->if_capabilities |= IFCAP_HWCSUM; 763 ifp->if_capenable |= IFCAP_HWCSUM; 764 } 765 766#ifdef DEVICE_POLLING 767 /* Inform the world we support polling. */ 768 ifp->if_capabilities |= IFCAP_POLLING; 769 ifp->if_capenable |= IFCAP_POLLING; 770#endif 771 772 /* 773 * Attach the interface. 774 */ 775 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 776 777 /* 778 * Tell the upper layer(s) we support long frames. 779 * Must appear after the call to ether_ifattach() because 780 * ether_ifattach() sets ifi_hdrlen to the default value. 781 */ 782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 783 ifp->if_capabilities |= IFCAP_VLAN_MTU; 784 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 785 786 /* 787 * Let the system queue as many packets as we have available 788 * TX descriptors. 789 */ 790 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 791 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 792 IFQ_SET_READY(&ifp->if_snd); 793 794 /* 795 * Hook our interrupt after all initialization is complete. 796 */ 797 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 798 fxp_intr, sc, &sc->ih); 799 if (error) { 800 device_printf(dev, "could not setup irq\n"); 801 ether_ifdetach(&sc->arpcom.ac_if); 802 goto fail; 803 } 804 805fail: 806 splx(s); 807 if (error) 808 fxp_release(sc); 809 return (error); 810} 811 812/* 813 * Release all resources. The softc lock should not be held and the 814 * interrupt should already be torn down. 815 */ 816static void 817fxp_release(struct fxp_softc *sc) 818{ 819 struct fxp_rx *rxp; 820 struct fxp_tx *txp; 821 int i; 822 823 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 824 KASSERT(sc->ih == NULL, 825 ("fxp_release() called with intr handle still active")); 826 if (sc->miibus) 827 device_delete_child(sc->dev, sc->miibus); 828 bus_generic_detach(sc->dev); 829 ifmedia_removeall(&sc->sc_media); 830 if (sc->fxp_desc.cbl_list) { 831 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 832 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 833 sc->cbl_map); 834 } 835 if (sc->fxp_stats) { 836 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 837 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 838 } 839 if (sc->mcsp) { 840 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 841 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 842 } 843 if (sc->irq) 844 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 845 if (sc->mem) 846 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 847 if (sc->fxp_mtag) { 848 for (i = 0; i < FXP_NRFABUFS; i++) { 849 rxp = &sc->fxp_desc.rx_list[i]; 850 if (rxp->rx_mbuf != NULL) { 851 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 854 m_freem(rxp->rx_mbuf); 855 } 856 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 857 } 858 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 859 for (i = 0; i < FXP_NTXCB; i++) { 860 txp = &sc->fxp_desc.tx_list[i]; 861 if (txp->tx_mbuf != NULL) { 862 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 863 BUS_DMASYNC_POSTWRITE); 864 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 865 m_freem(txp->tx_mbuf); 866 } 867 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 868 } 869 bus_dma_tag_destroy(sc->fxp_mtag); 870 } 871 if (sc->fxp_stag) 872 bus_dma_tag_destroy(sc->fxp_stag); 873 if (sc->cbl_tag) 874 bus_dma_tag_destroy(sc->cbl_tag); 875 if (sc->mcs_tag) 876 bus_dma_tag_destroy(sc->mcs_tag); 877 878 mtx_destroy(&sc->sc_mtx); 879} 880 881/* 882 * Detach interface. 883 */ 884static int 885fxp_detach(device_t dev) 886{ 887 struct fxp_softc *sc = device_get_softc(dev); 888 int s; 889 890 FXP_LOCK(sc); 891 s = splimp(); 892 893 sc->suspended = 1; /* Do same thing as we do for suspend */ 894 /* 895 * Close down routes etc. 896 */ 897 ether_ifdetach(&sc->arpcom.ac_if); 898 899 /* 900 * Stop DMA and drop transmit queue, but disable interrupts first. 901 */ 902 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 903 fxp_stop(sc); 904 FXP_UNLOCK(sc); 905 906 /* 907 * Unhook interrupt before dropping lock. This is to prevent 908 * races with fxp_intr(). 909 */ 910 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 911 sc->ih = NULL; 912 913 splx(s); 914 915 /* Release our allocated resources. */ 916 fxp_release(sc); 917 return (0); 918} 919 920/* 921 * Device shutdown routine. Called at system shutdown after sync. The 922 * main purpose of this routine is to shut off receiver DMA so that 923 * kernel memory doesn't get clobbered during warmboot. 924 */ 925static int 926fxp_shutdown(device_t dev) 927{ 928 /* 929 * Make sure that DMA is disabled prior to reboot. Not doing 930 * do could allow DMA to corrupt kernel memory during the 931 * reboot before the driver initializes. 932 */ 933 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 934 return (0); 935} 936 937/* 938 * Device suspend routine. Stop the interface and save some PCI 939 * settings in case the BIOS doesn't restore them properly on 940 * resume. 941 */ 942static int 943fxp_suspend(device_t dev) 944{ 945 struct fxp_softc *sc = device_get_softc(dev); 946 int i, s; 947 948 FXP_LOCK(sc); 949 s = splimp(); 950 951 fxp_stop(sc); 952 953 sc->suspended = 1; 954 955 FXP_UNLOCK(sc); 956 splx(s); 957 return (0); 958} 959 960/* 961 * Device resume routine. Restore some PCI settings in case the BIOS 962 * doesn't, re-enable busmastering, and restart the interface if 963 * appropriate. 964 */ 965static int 966fxp_resume(device_t dev) 967{ 968 struct fxp_softc *sc = device_get_softc(dev); 969 struct ifnet *ifp = &sc->sc_if; 970 uint16_t pci_command; 971 int i, s; 972 973 FXP_LOCK(sc); 974 s = splimp(); 975 976 /* reenable busmastering */ 977 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 978 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 979 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 980 981 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 982 DELAY(10); 983 984 /* reinitialize interface if necessary */ 985 if (ifp->if_flags & IFF_UP) 986 fxp_init_body(sc); 987 988 sc->suspended = 0; 989 990 FXP_UNLOCK(sc); 991 splx(s); 992 return (0); 993} 994 995static void 996fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 997{ 998 uint16_t reg; 999 int x; 1000 1001 /* 1002 * Shift in data. 1003 */ 1004 for (x = 1 << (length - 1); x; x >>= 1) { 1005 if (data & x) 1006 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1007 else 1008 reg = FXP_EEPROM_EECS; 1009 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1010 DELAY(1); 1011 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1012 DELAY(1); 1013 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1014 DELAY(1); 1015 } 1016} 1017 1018/* 1019 * Read from the serial EEPROM. Basically, you manually shift in 1020 * the read opcode (one bit at a time) and then shift in the address, 1021 * and then you shift out the data (all of this one bit at a time). 1022 * The word size is 16 bits, so you have to provide the address for 1023 * every 16 bits of data. 1024 */ 1025static uint16_t 1026fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1027{ 1028 uint16_t reg, data; 1029 int x; 1030 1031 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1032 /* 1033 * Shift in read opcode. 1034 */ 1035 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1036 /* 1037 * Shift in address. 1038 */ 1039 data = 0; 1040 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1041 if (offset & x) 1042 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1043 else 1044 reg = FXP_EEPROM_EECS; 1045 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1046 DELAY(1); 1047 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1048 DELAY(1); 1049 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1050 DELAY(1); 1051 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1052 data++; 1053 if (autosize && reg == 0) { 1054 sc->eeprom_size = data; 1055 break; 1056 } 1057 } 1058 /* 1059 * Shift out data. 1060 */ 1061 data = 0; 1062 reg = FXP_EEPROM_EECS; 1063 for (x = 1 << 15; x; x >>= 1) { 1064 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1065 DELAY(1); 1066 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1067 data |= x; 1068 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1069 DELAY(1); 1070 } 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1072 DELAY(1); 1073 1074 return (data); 1075} 1076 1077static void 1078fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1079{ 1080 int i; 1081 1082 /* 1083 * Erase/write enable. 1084 */ 1085 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1086 fxp_eeprom_shiftin(sc, 0x4, 3); 1087 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1089 DELAY(1); 1090 /* 1091 * Shift in write opcode, address, data. 1092 */ 1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1094 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1095 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1096 fxp_eeprom_shiftin(sc, data, 16); 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1098 DELAY(1); 1099 /* 1100 * Wait for EEPROM to finish up. 1101 */ 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1103 DELAY(1); 1104 for (i = 0; i < 1000; i++) { 1105 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1106 break; 1107 DELAY(50); 1108 } 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1110 DELAY(1); 1111 /* 1112 * Erase/write disable. 1113 */ 1114 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1115 fxp_eeprom_shiftin(sc, 0x4, 3); 1116 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1117 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1118 DELAY(1); 1119} 1120 1121/* 1122 * From NetBSD: 1123 * 1124 * Figure out EEPROM size. 1125 * 1126 * 559's can have either 64-word or 256-word EEPROMs, the 558 1127 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1128 * talks about the existance of 16 to 256 word EEPROMs. 1129 * 1130 * The only known sizes are 64 and 256, where the 256 version is used 1131 * by CardBus cards to store CIS information. 1132 * 1133 * The address is shifted in msb-to-lsb, and after the last 1134 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1135 * after which follows the actual data. We try to detect this zero, by 1136 * probing the data-out bit in the EEPROM control register just after 1137 * having shifted in a bit. If the bit is zero, we assume we've 1138 * shifted enough address bits. The data-out should be tri-state, 1139 * before this, which should translate to a logical one. 1140 */ 1141static void 1142fxp_autosize_eeprom(struct fxp_softc *sc) 1143{ 1144 1145 /* guess maximum size of 256 words */ 1146 sc->eeprom_size = 8; 1147 1148 /* autosize */ 1149 (void) fxp_eeprom_getword(sc, 0, 1); 1150} 1151 1152static void 1153fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1154{ 1155 int i; 1156 1157 for (i = 0; i < words; i++) 1158 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1159} 1160 1161static void 1162fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1163{ 1164 int i; 1165 1166 for (i = 0; i < words; i++) 1167 fxp_eeprom_putword(sc, offset + i, data[i]); 1168} 1169 1170/* 1171 * Grab the softc lock and call the real fxp_start_body() routine 1172 */ 1173static void 1174fxp_start(struct ifnet *ifp) 1175{ 1176 struct fxp_softc *sc = ifp->if_softc; 1177 1178 FXP_LOCK(sc); 1179 fxp_start_body(ifp); 1180 FXP_UNLOCK(sc); 1181} 1182 1183/* 1184 * Start packet transmission on the interface. 1185 * This routine must be called with the softc lock held, and is an 1186 * internal entry point only. 1187 */ 1188static void 1189fxp_start_body(struct ifnet *ifp) 1190{ 1191 struct fxp_softc *sc = ifp->if_softc; 1192 struct mbuf *mb_head; 1193 int error, txqueued; 1194 1195 FXP_LOCK_ASSERT(sc, MA_OWNED); 1196 1197 /* 1198 * See if we need to suspend xmit until the multicast filter 1199 * has been reprogrammed (which can only be done at the head 1200 * of the command chain). 1201 */ 1202 if (sc->need_mcsetup) 1203 return; 1204 1205 /* 1206 * We're finished if there is nothing more to add to the list or if 1207 * we're all filled up with buffers to transmit. 1208 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1209 * a NOP command when needed. 1210 */ 1211 txqueued = 0; 1212 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1213 sc->tx_queued < FXP_NTXCB - 1) { 1214 1215 /* 1216 * Grab a packet to transmit. 1217 */ 1218 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1219 if (mb_head == NULL) 1220 break; 1221 1222 error = fxp_encap(sc, mb_head); 1223 if (error) 1224 break; 1225 txqueued = 1; 1226 } 1227 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1228 1229 /* 1230 * We're finished. If we added to the list, issue a RESUME to get DMA 1231 * going again if suspended. 1232 */ 1233 if (txqueued) { 1234 fxp_scb_wait(sc); 1235 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1236 } 1237} 1238 1239static int 1240fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1241{ 1242 struct ifnet *ifp; 1243 struct mbuf *m; 1244 struct fxp_tx *txp; 1245 struct fxp_cb_tx *cbp; 1246 bus_dma_segment_t segs[FXP_NTXSEG]; 1247 int chainlen, error, i, nseg; 1248 1249 FXP_LOCK_ASSERT(sc, MA_OWNED); 1250 ifp = &sc->sc_if; 1251 1252 /* 1253 * Get pointer to next available tx desc. 1254 */ 1255 txp = sc->fxp_desc.tx_last->tx_next; 1256 1257 /* 1258 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1259 * Ethernet Controller Family Open Source Software 1260 * Developer Manual says: 1261 * Using software parsing is only allowed with legal 1262 * TCP/IP or UDP/IP packets. 1263 * ... 1264 * For all other datagrams, hardware parsing must 1265 * be used. 1266 * Software parsing appears to truncate ICMP and 1267 * fragmented UDP packets that contain one to three 1268 * bytes in the second (and final) mbuf of the packet. 1269 */ 1270 if (sc->flags & FXP_FLAG_EXT_RFA) 1271 txp->tx_cb->ipcb_ip_activation_high = 1272 FXP_IPCB_HARDWAREPARSING_ENABLE; 1273 1274 /* 1275 * Deal with TCP/IP checksum offload. Note that 1276 * in order for TCP checksum offload to work, 1277 * the pseudo header checksum must have already 1278 * been computed and stored in the checksum field 1279 * in the TCP header. The stack should have 1280 * already done this for us. 1281 */ 1282 if (m_head->m_pkthdr.csum_flags) { 1283 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1284 txp->tx_cb->ipcb_ip_schedule = 1285 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1286 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1287 txp->tx_cb->ipcb_ip_schedule |= 1288 FXP_IPCB_TCP_PACKET; 1289 } 1290 1291#ifdef FXP_IP_CSUM_WAR 1292 /* 1293 * XXX The 82550 chip appears to have trouble 1294 * dealing with IP header checksums in very small 1295 * datagrams, namely fragments from 1 to 3 bytes 1296 * in size. For example, say you want to transmit 1297 * a UDP packet of 1473 bytes. The packet will be 1298 * fragmented over two IP datagrams, the latter 1299 * containing only one byte of data. The 82550 will 1300 * botch the header checksum on the 1-byte fragment. 1301 * As long as the datagram contains 4 or more bytes 1302 * of data, you're ok. 1303 * 1304 * The following code attempts to work around this 1305 * problem: if the datagram is less than 38 bytes 1306 * in size (14 bytes ether header, 20 bytes IP header, 1307 * plus 4 bytes of data), we punt and compute the IP 1308 * header checksum by hand. This workaround doesn't 1309 * work very well, however, since it can be fooled 1310 * by things like VLAN tags and IP options that make 1311 * the header sizes/offsets vary. 1312 */ 1313 1314 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1315 if (m_head->m_pkthdr.len < 38) { 1316 struct ip *ip; 1317 m_head->m_data += ETHER_HDR_LEN; 1318 ip = mtod(mb_head, struct ip *); 1319 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1320 m_head->m_data -= ETHER_HDR_LEN; 1321 } else { 1322 txp->tx_cb->ipcb_ip_activation_high = 1323 FXP_IPCB_HARDWAREPARSING_ENABLE; 1324 txp->tx_cb->ipcb_ip_schedule |= 1325 FXP_IPCB_IP_CHECKSUM_ENABLE; 1326 } 1327 } 1328#endif 1329 } 1330 1331 chainlen = 0; 1332 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1333 chainlen++; 1334 if (chainlen > sc->maxtxseg) { 1335 struct mbuf *mn; 1336 1337 /* 1338 * We ran out of segments. We have to recopy this 1339 * mbuf chain first. Bail out if we can't get the 1340 * new buffers. 1341 */ 1342 mn = m_defrag(m_head, M_DONTWAIT); 1343 if (mn == NULL) { 1344 m_freem(m_head); 1345 return (-1); 1346 } else { 1347 m_head = mn; 1348 } 1349 } 1350 1351 /* 1352 * Go through each of the mbufs in the chain and initialize 1353 * the transmit buffer descriptors with the physical address 1354 * and size of the mbuf. 1355 */ 1356 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1357 m_head, segs, &nseg, 0); 1358 if (error) { 1359 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1360 m_freem(m_head); 1361 return (-1); 1362 } 1363 1364 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1365 1366 cbp = txp->tx_cb; 1367 for (i = 0; i < nseg; i++) { 1368 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1369 /* 1370 * If this is an 82550/82551, then we're using extended 1371 * TxCBs _and_ we're using checksum offload. This means 1372 * that the TxCB is really an IPCB. One major difference 1373 * between the two is that with plain extended TxCBs, 1374 * the bottom half of the TxCB contains two entries from 1375 * the TBD array, whereas IPCBs contain just one entry: 1376 * one entry (8 bytes) has been sacrificed for the TCP/IP 1377 * checksum offload control bits. So to make things work 1378 * right, we have to start filling in the TBD array 1379 * starting from a different place depending on whether 1380 * the chip is an 82550/82551 or not. 1381 */ 1382 if (sc->flags & FXP_FLAG_EXT_RFA) { 1383 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1384 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1385 } else { 1386 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1387 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1388 } 1389 } 1390 cbp->tbd_number = nseg; 1391 1392 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1393 txp->tx_mbuf = m_head; 1394 txp->tx_cb->cb_status = 0; 1395 txp->tx_cb->byte_count = 0; 1396 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1397 txp->tx_cb->cb_command = 1398 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1399 FXP_CB_COMMAND_S); 1400 } else { 1401 txp->tx_cb->cb_command = 1402 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1403 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1404 /* 1405 * Set a 5 second timer just in case we don't hear 1406 * from the card again. 1407 */ 1408 ifp->if_timer = 5; 1409 } 1410 txp->tx_cb->tx_threshold = tx_threshold; 1411 1412 /* 1413 * Advance the end of list forward. 1414 */ 1415 1416#ifdef __alpha__ 1417 /* 1418 * On platforms which can't access memory in 16-bit 1419 * granularities, we must prevent the card from DMA'ing 1420 * up the status while we update the command field. 1421 * This could cause us to overwrite the completion status. 1422 * XXX This is probably bogus and we're _not_ looking 1423 * for atomicity here. 1424 */ 1425 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1426 htole16(FXP_CB_COMMAND_S)); 1427#else 1428 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1429#endif /*__alpha__*/ 1430 sc->fxp_desc.tx_last = txp; 1431 1432 /* 1433 * Advance the beginning of the list forward if there are 1434 * no other packets queued (when nothing is queued, tx_first 1435 * sits on the last TxCB that was sent out). 1436 */ 1437 if (sc->tx_queued == 0) 1438 sc->fxp_desc.tx_first = txp; 1439 1440 sc->tx_queued++; 1441 1442 /* 1443 * Pass packet to bpf if there is a listener. 1444 */ 1445 BPF_MTAP(ifp, m_head); 1446 return (0); 1447} 1448 1449#ifdef DEVICE_POLLING 1450static poll_handler_t fxp_poll; 1451 1452static void 1453fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1454{ 1455 struct fxp_softc *sc = ifp->if_softc; 1456 uint8_t statack; 1457 1458 FXP_LOCK(sc); 1459 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1460 ether_poll_deregister(ifp); 1461 cmd = POLL_DEREGISTER; 1462 } 1463 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1464 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1465 FXP_UNLOCK(sc); 1466 return; 1467 } 1468 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1469 FXP_SCB_STATACK_FR; 1470 if (cmd == POLL_AND_CHECK_STATUS) { 1471 uint8_t tmp; 1472 1473 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1474 if (tmp == 0xff || tmp == 0) { 1475 FXP_UNLOCK(sc); 1476 return; /* nothing to do */ 1477 } 1478 tmp &= ~statack; 1479 /* ack what we can */ 1480 if (tmp != 0) 1481 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1482 statack |= tmp; 1483 } 1484 fxp_intr_body(sc, ifp, statack, count); 1485 FXP_UNLOCK(sc); 1486} 1487#endif /* DEVICE_POLLING */ 1488 1489/* 1490 * Process interface interrupts. 1491 */ 1492static void 1493fxp_intr(void *xsc) 1494{ 1495 struct fxp_softc *sc = xsc; 1496 struct ifnet *ifp = &sc->sc_if; 1497 uint8_t statack; 1498 1499 FXP_LOCK(sc); 1500 if (sc->suspended) { 1501 FXP_UNLOCK(sc); 1502 return; 1503 } 1504 1505#ifdef DEVICE_POLLING 1506 if (ifp->if_flags & IFF_POLLING) { 1507 FXP_UNLOCK(sc); 1508 return; 1509 } 1510 if ((ifp->if_capenable & IFCAP_POLLING) && 1511 ether_poll_register(fxp_poll, ifp)) { 1512 /* disable interrupts */ 1513 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1514 FXP_UNLOCK(sc); 1515 fxp_poll(ifp, 0, 1); 1516 return; 1517 } 1518#endif 1519 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1520 /* 1521 * It should not be possible to have all bits set; the 1522 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1523 * all bits are set, this may indicate that the card has 1524 * been physically ejected, so ignore it. 1525 */ 1526 if (statack == 0xff) { 1527 FXP_UNLOCK(sc); 1528 return; 1529 } 1530 1531 /* 1532 * First ACK all the interrupts in this pass. 1533 */ 1534 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1535 fxp_intr_body(sc, ifp, statack, -1); 1536 } 1537 FXP_UNLOCK(sc); 1538} 1539 1540static void 1541fxp_txeof(struct fxp_softc *sc) 1542{ 1543 struct fxp_tx *txp; 1544 1545 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1546 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1547 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1548 txp = txp->tx_next) { 1549 if (txp->tx_mbuf != NULL) { 1550 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1551 BUS_DMASYNC_POSTWRITE); 1552 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1553 m_freem(txp->tx_mbuf); 1554 txp->tx_mbuf = NULL; 1555 /* clear this to reset csum offload bits */ 1556 txp->tx_cb->tbd[0].tb_addr = 0; 1557 } 1558 sc->tx_queued--; 1559 } 1560 sc->fxp_desc.tx_first = txp; 1561 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1562} 1563 1564static void 1565fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1566 int count) 1567{ 1568 struct mbuf *m; 1569 struct fxp_rx *rxp; 1570 struct fxp_rfa *rfa; 1571 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1572 1573 FXP_LOCK_ASSERT(sc, MA_OWNED); 1574 if (rnr) 1575 sc->rnr++; 1576#ifdef DEVICE_POLLING 1577 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1578 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1579 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1580 rnr = 1; 1581 } 1582#endif 1583 1584 /* 1585 * Free any finished transmit mbuf chains. 1586 * 1587 * Handle the CNA event likt a CXTNO event. It used to 1588 * be that this event (control unit not ready) was not 1589 * encountered, but it is now with the SMPng modifications. 1590 * The exact sequence of events that occur when the interface 1591 * is brought up are different now, and if this event 1592 * goes unhandled, the configuration/rxfilter setup sequence 1593 * can stall for several seconds. The result is that no 1594 * packets go out onto the wire for about 5 to 10 seconds 1595 * after the interface is ifconfig'ed for the first time. 1596 */ 1597 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1598 fxp_txeof(sc); 1599 1600 ifp->if_timer = 0; 1601 if (sc->tx_queued == 0) { 1602 if (sc->need_mcsetup) 1603 fxp_mc_setup(sc); 1604 } 1605 /* 1606 * Try to start more packets transmitting. 1607 */ 1608 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1609 fxp_start_body(ifp); 1610 } 1611 1612 /* 1613 * Just return if nothing happened on the receive side. 1614 */ 1615 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1616 return; 1617 1618 /* 1619 * Process receiver interrupts. If a no-resource (RNR) 1620 * condition exists, get whatever packets we can and 1621 * re-start the receiver. 1622 * 1623 * When using polling, we do not process the list to completion, 1624 * so when we get an RNR interrupt we must defer the restart 1625 * until we hit the last buffer with the C bit set. 1626 * If we run out of cycles and rfa_headm has the C bit set, 1627 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1628 * that the info will be used in the subsequent polling cycle. 1629 */ 1630 for (;;) { 1631 rxp = sc->fxp_desc.rx_head; 1632 m = rxp->rx_mbuf; 1633 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1634 RFA_ALIGNMENT_FUDGE); 1635 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1636 BUS_DMASYNC_POSTREAD); 1637 1638#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1639 if (count >= 0 && count-- == 0) { 1640 if (rnr) { 1641 /* Defer RNR processing until the next time. */ 1642 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1643 rnr = 0; 1644 } 1645 break; 1646 } 1647#endif /* DEVICE_POLLING */ 1648 1649 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1650 break; 1651 1652 /* 1653 * Advance head forward. 1654 */ 1655 sc->fxp_desc.rx_head = rxp->rx_next; 1656 1657 /* 1658 * Add a new buffer to the receive chain. 1659 * If this fails, the old buffer is recycled 1660 * instead. 1661 */ 1662 if (fxp_add_rfabuf(sc, rxp) == 0) { 1663 int total_len; 1664 1665 /* 1666 * Fetch packet length (the top 2 bits of 1667 * actual_size are flags set by the controller 1668 * upon completion), and drop the packet in case 1669 * of bogus length or CRC errors. 1670 */ 1671 total_len = le16toh(rfa->actual_size) & 0x3fff; 1672 if (total_len < sizeof(struct ether_header) || 1673 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1674 sc->rfa_size || 1675 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1676 m_freem(m); 1677 continue; 1678 } 1679 1680 /* Do IP checksum checking. */ 1681 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1682 if (rfa->rfax_csum_sts & 1683 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1684 m->m_pkthdr.csum_flags |= 1685 CSUM_IP_CHECKED; 1686 if (rfa->rfax_csum_sts & 1687 FXP_RFDX_CS_IP_CSUM_VALID) 1688 m->m_pkthdr.csum_flags |= 1689 CSUM_IP_VALID; 1690 if ((rfa->rfax_csum_sts & 1691 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1692 (rfa->rfax_csum_sts & 1693 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1694 m->m_pkthdr.csum_flags |= 1695 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1696 m->m_pkthdr.csum_data = 0xffff; 1697 } 1698 } 1699 1700 m->m_pkthdr.len = m->m_len = total_len; 1701 m->m_pkthdr.rcvif = ifp; 1702 1703 /* 1704 * Drop locks before calling if_input() since it 1705 * may re-enter fxp_start() in the netisr case. 1706 * This would result in a lock reversal. Better 1707 * performance might be obtained by chaining all 1708 * packets received, dropping the lock, and then 1709 * calling if_input() on each one. 1710 */ 1711 FXP_UNLOCK(sc); 1712 (*ifp->if_input)(ifp, m); 1713 FXP_LOCK(sc); 1714 } 1715 } 1716 if (rnr) { 1717 fxp_scb_wait(sc); 1718 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1719 sc->fxp_desc.rx_head->rx_addr); 1720 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1721 } 1722} 1723 1724/* 1725 * Update packet in/out/collision statistics. The i82557 doesn't 1726 * allow you to access these counters without doing a fairly 1727 * expensive DMA to get _all_ of the statistics it maintains, so 1728 * we do this operation here only once per second. The statistics 1729 * counters in the kernel are updated from the previous dump-stats 1730 * DMA and then a new dump-stats DMA is started. The on-chip 1731 * counters are zeroed when the DMA completes. If we can't start 1732 * the DMA immediately, we don't wait - we just prepare to read 1733 * them again next time. 1734 */ 1735static void 1736fxp_tick(void *xsc) 1737{ 1738 struct fxp_softc *sc = xsc; 1739 struct ifnet *ifp = &sc->sc_if; 1740 struct fxp_stats *sp = sc->fxp_stats; 1741 int s; 1742 1743 FXP_LOCK(sc); 1744 s = splimp(); 1745 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1746 ifp->if_opackets += le32toh(sp->tx_good); 1747 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1748 if (sp->rx_good) { 1749 ifp->if_ipackets += le32toh(sp->rx_good); 1750 sc->rx_idle_secs = 0; 1751 } else { 1752 /* 1753 * Receiver's been idle for another second. 1754 */ 1755 sc->rx_idle_secs++; 1756 } 1757 ifp->if_ierrors += 1758 le32toh(sp->rx_crc_errors) + 1759 le32toh(sp->rx_alignment_errors) + 1760 le32toh(sp->rx_rnr_errors) + 1761 le32toh(sp->rx_overrun_errors); 1762 /* 1763 * If any transmit underruns occured, bump up the transmit 1764 * threshold by another 512 bytes (64 * 8). 1765 */ 1766 if (sp->tx_underruns) { 1767 ifp->if_oerrors += le32toh(sp->tx_underruns); 1768 if (tx_threshold < 192) 1769 tx_threshold += 64; 1770 } 1771 1772 /* 1773 * Release any xmit buffers that have completed DMA. This isn't 1774 * strictly necessary to do here, but it's advantagous for mbufs 1775 * with external storage to be released in a timely manner rather 1776 * than being defered for a potentially long time. This limits 1777 * the delay to a maximum of one second. 1778 */ 1779 fxp_txeof(sc); 1780 1781 /* 1782 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1783 * then assume the receiver has locked up and attempt to clear 1784 * the condition by reprogramming the multicast filter. This is 1785 * a work-around for a bug in the 82557 where the receiver locks 1786 * up if it gets certain types of garbage in the syncronization 1787 * bits prior to the packet header. This bug is supposed to only 1788 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1789 * mode as well (perhaps due to a 10/100 speed transition). 1790 */ 1791 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1792 sc->rx_idle_secs = 0; 1793 fxp_mc_setup(sc); 1794 } 1795 /* 1796 * If there is no pending command, start another stats 1797 * dump. Otherwise punt for now. 1798 */ 1799 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1800 /* 1801 * Start another stats dump. 1802 */ 1803 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1804 BUS_DMASYNC_PREREAD); 1805 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1806 } else { 1807 /* 1808 * A previous command is still waiting to be accepted. 1809 * Just zero our copy of the stats and wait for the 1810 * next timer event to update them. 1811 */ 1812 sp->tx_good = 0; 1813 sp->tx_underruns = 0; 1814 sp->tx_total_collisions = 0; 1815 1816 sp->rx_good = 0; 1817 sp->rx_crc_errors = 0; 1818 sp->rx_alignment_errors = 0; 1819 sp->rx_rnr_errors = 0; 1820 sp->rx_overrun_errors = 0; 1821 } 1822 if (sc->miibus != NULL) 1823 mii_tick(device_get_softc(sc->miibus)); 1824 1825 /* 1826 * Schedule another timeout one second from now. 1827 */ 1828 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1829 FXP_UNLOCK(sc); 1830 splx(s); 1831} 1832 1833/* 1834 * Stop the interface. Cancels the statistics updater and resets 1835 * the interface. 1836 */ 1837static void 1838fxp_stop(struct fxp_softc *sc) 1839{ 1840 struct ifnet *ifp = &sc->sc_if; 1841 struct fxp_tx *txp; 1842 int i; 1843 1844 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1845 ifp->if_timer = 0; 1846 1847#ifdef DEVICE_POLLING 1848 ether_poll_deregister(ifp); 1849#endif 1850 /* 1851 * Cancel stats updater. 1852 */ 1853 callout_stop(&sc->stat_ch); 1854 1855 /* 1856 * Issue software reset, which also unloads the microcode. 1857 */ 1858 sc->flags &= ~FXP_FLAG_UCODE; 1859 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1860 DELAY(50); 1861 1862 /* 1863 * Release any xmit buffers. 1864 */ 1865 txp = sc->fxp_desc.tx_list; 1866 if (txp != NULL) { 1867 for (i = 0; i < FXP_NTXCB; i++) { 1868 if (txp[i].tx_mbuf != NULL) { 1869 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1870 BUS_DMASYNC_POSTWRITE); 1871 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1872 m_freem(txp[i].tx_mbuf); 1873 txp[i].tx_mbuf = NULL; 1874 /* clear this to reset csum offload bits */ 1875 txp[i].tx_cb->tbd[0].tb_addr = 0; 1876 } 1877 } 1878 } 1879 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1880 sc->tx_queued = 0; 1881} 1882 1883/* 1884 * Watchdog/transmission transmit timeout handler. Called when a 1885 * transmission is started on the interface, but no interrupt is 1886 * received before the timeout. This usually indicates that the 1887 * card has wedged for some reason. 1888 */ 1889static void 1890fxp_watchdog(struct ifnet *ifp) 1891{ 1892 struct fxp_softc *sc = ifp->if_softc; 1893 1894 FXP_LOCK(sc); 1895 device_printf(sc->dev, "device timeout\n"); 1896 ifp->if_oerrors++; 1897 1898 fxp_init_body(sc); 1899 FXP_UNLOCK(sc); 1900} 1901 1902/* 1903 * Acquire locks and then call the real initialization function. This 1904 * is necessary because ether_ioctl() calls if_init() and this would 1905 * result in mutex recursion if the mutex was held. 1906 */ 1907static void 1908fxp_init(void *xsc) 1909{ 1910 struct fxp_softc *sc = xsc; 1911 1912 FXP_LOCK(sc); 1913 fxp_init_body(sc); 1914 FXP_UNLOCK(sc); 1915} 1916 1917/* 1918 * Perform device initialization. This routine must be called with the 1919 * softc lock held. 1920 */ 1921static void 1922fxp_init_body(struct fxp_softc *sc) 1923{ 1924 struct ifnet *ifp = &sc->sc_if; 1925 struct fxp_cb_config *cbp; 1926 struct fxp_cb_ias *cb_ias; 1927 struct fxp_cb_tx *tcbp; 1928 struct fxp_tx *txp; 1929 struct fxp_cb_mcs *mcsp; 1930 int i, prm, s; 1931 1932 FXP_LOCK_ASSERT(sc, MA_OWNED); 1933 s = splimp(); 1934 /* 1935 * Cancel any pending I/O 1936 */ 1937 fxp_stop(sc); 1938 1939 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1940 1941 /* 1942 * Initialize base of CBL and RFA memory. Loading with zero 1943 * sets it up for regular linear addressing. 1944 */ 1945 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1946 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1947 1948 fxp_scb_wait(sc); 1949 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1950 1951 /* 1952 * Initialize base of dump-stats buffer. 1953 */ 1954 fxp_scb_wait(sc); 1955 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1956 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1957 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1958 1959 /* 1960 * Attempt to load microcode if requested. 1961 */ 1962 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1963 fxp_load_ucode(sc); 1964 1965 /* 1966 * Initialize the multicast address list. 1967 */ 1968 if (fxp_mc_addrs(sc)) { 1969 mcsp = sc->mcsp; 1970 mcsp->cb_status = 0; 1971 mcsp->cb_command = 1972 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1973 mcsp->link_addr = 0xffffffff; 1974 /* 1975 * Start the multicast setup command. 1976 */ 1977 fxp_scb_wait(sc); 1978 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1979 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1980 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1981 /* ...and wait for it to complete. */ 1982 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1983 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1984 BUS_DMASYNC_POSTWRITE); 1985 } 1986 1987 /* 1988 * We temporarily use memory that contains the TxCB list to 1989 * construct the config CB. The TxCB list memory is rebuilt 1990 * later. 1991 */ 1992 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1993 1994 /* 1995 * This bcopy is kind of disgusting, but there are a bunch of must be 1996 * zero and must be one bits in this structure and this is the easiest 1997 * way to initialize them all to proper values. 1998 */ 1999 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2000 2001 cbp->cb_status = 0; 2002 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2003 FXP_CB_COMMAND_EL); 2004 cbp->link_addr = 0xffffffff; /* (no) next command */ 2005 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2006 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2007 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2008 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2009 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2010 cbp->type_enable = 0; /* actually reserved */ 2011 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2012 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2013 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2014 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2015 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2016 cbp->late_scb = 0; /* (don't) defer SCB update */ 2017 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2018 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2019 cbp->ci_int = 1; /* interrupt on CU idle */ 2020 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2021 cbp->ext_stats_dis = 1; /* disable extended counters */ 2022 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2023 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2024 cbp->disc_short_rx = !prm; /* discard short packets */ 2025 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2026 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2027 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2028 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2029 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2030 cbp->csma_dis = 0; /* (don't) disable link */ 2031 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2032 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2033 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2034 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2035 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2036 cbp->nsai = 1; /* (don't) disable source addr insert */ 2037 cbp->preamble_length = 2; /* (7 byte) preamble */ 2038 cbp->loopback = 0; /* (don't) loopback */ 2039 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2040 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2041 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2042 cbp->promiscuous = prm; /* promiscuous mode */ 2043 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2044 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2045 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2046 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2047 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2048 2049 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2050 cbp->padding = 1; /* (do) pad short tx packets */ 2051 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2052 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2053 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2054 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2055 /* must set wake_en in PMCSR also */ 2056 cbp->force_fdx = 0; /* (don't) force full duplex */ 2057 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2058 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2059 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2060 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2061 2062 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2063 /* 2064 * The 82557 has no hardware flow control, the values 2065 * below are the defaults for the chip. 2066 */ 2067 cbp->fc_delay_lsb = 0; 2068 cbp->fc_delay_msb = 0x40; 2069 cbp->pri_fc_thresh = 3; 2070 cbp->tx_fc_dis = 0; 2071 cbp->rx_fc_restop = 0; 2072 cbp->rx_fc_restart = 0; 2073 cbp->fc_filter = 0; 2074 cbp->pri_fc_loc = 1; 2075 } else { 2076 cbp->fc_delay_lsb = 0x1f; 2077 cbp->fc_delay_msb = 0x01; 2078 cbp->pri_fc_thresh = 3; 2079 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2080 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2081 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2082 cbp->fc_filter = !prm; /* drop FC frames to host */ 2083 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2084 } 2085 2086 /* 2087 * Start the config command/DMA. 2088 */ 2089 fxp_scb_wait(sc); 2090 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2091 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2092 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2093 /* ...and wait for it to complete. */ 2094 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2095 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2096 2097 /* 2098 * Now initialize the station address. Temporarily use the TxCB 2099 * memory area like we did above for the config CB. 2100 */ 2101 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2102 cb_ias->cb_status = 0; 2103 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2104 cb_ias->link_addr = 0xffffffff; 2105 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2106 sizeof(sc->arpcom.ac_enaddr)); 2107 2108 /* 2109 * Start the IAS (Individual Address Setup) command/DMA. 2110 */ 2111 fxp_scb_wait(sc); 2112 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2113 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2114 /* ...and wait for it to complete. */ 2115 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2116 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2117 2118 /* 2119 * Initialize transmit control block (TxCB) list. 2120 */ 2121 txp = sc->fxp_desc.tx_list; 2122 tcbp = sc->fxp_desc.cbl_list; 2123 bzero(tcbp, FXP_TXCB_SZ); 2124 for (i = 0; i < FXP_NTXCB; i++) { 2125 txp[i].tx_mbuf = NULL; 2126 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2127 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2128 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2129 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2130 if (sc->flags & FXP_FLAG_EXT_TXCB) 2131 tcbp[i].tbd_array_addr = 2132 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2133 else 2134 tcbp[i].tbd_array_addr = 2135 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2136 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2137 } 2138 /* 2139 * Set the suspend flag on the first TxCB and start the control 2140 * unit. It will execute the NOP and then suspend. 2141 */ 2142 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2143 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2144 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2145 sc->tx_queued = 1; 2146 2147 fxp_scb_wait(sc); 2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2149 2150 /* 2151 * Initialize receiver buffer area - RFA. 2152 */ 2153 fxp_scb_wait(sc); 2154 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2156 2157 /* 2158 * Set current media. 2159 */ 2160 if (sc->miibus != NULL) 2161 mii_mediachg(device_get_softc(sc->miibus)); 2162 2163 ifp->if_flags |= IFF_RUNNING; 2164 ifp->if_flags &= ~IFF_OACTIVE; 2165 2166 /* 2167 * Enable interrupts. 2168 */ 2169#ifdef DEVICE_POLLING 2170 /* 2171 * ... but only do that if we are not polling. And because (presumably) 2172 * the default is interrupts on, we need to disable them explicitly! 2173 */ 2174 if ( ifp->if_flags & IFF_POLLING ) 2175 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2176 else 2177#endif /* DEVICE_POLLING */ 2178 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2179 2180 /* 2181 * Start stats updater. 2182 */ 2183 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2184 splx(s); 2185} 2186 2187static int 2188fxp_serial_ifmedia_upd(struct ifnet *ifp) 2189{ 2190 2191 return (0); 2192} 2193 2194static void 2195fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2196{ 2197 2198 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2199} 2200 2201/* 2202 * Change media according to request. 2203 */ 2204static int 2205fxp_ifmedia_upd(struct ifnet *ifp) 2206{ 2207 struct fxp_softc *sc = ifp->if_softc; 2208 struct mii_data *mii; 2209 2210 mii = device_get_softc(sc->miibus); 2211 mii_mediachg(mii); 2212 return (0); 2213} 2214 2215/* 2216 * Notify the world which media we're using. 2217 */ 2218static void 2219fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2220{ 2221 struct fxp_softc *sc = ifp->if_softc; 2222 struct mii_data *mii; 2223 2224 mii = device_get_softc(sc->miibus); 2225 mii_pollstat(mii); 2226 ifmr->ifm_active = mii->mii_media_active; 2227 ifmr->ifm_status = mii->mii_media_status; 2228 2229 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2230 sc->cu_resume_bug = 1; 2231 else 2232 sc->cu_resume_bug = 0; 2233} 2234 2235/* 2236 * Add a buffer to the end of the RFA buffer list. 2237 * Return 0 if successful, 1 for failure. A failure results in 2238 * adding the 'oldm' (if non-NULL) on to the end of the list - 2239 * tossing out its old contents and recycling it. 2240 * The RFA struct is stuck at the beginning of mbuf cluster and the 2241 * data pointer is fixed up to point just past it. 2242 */ 2243static int 2244fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2245{ 2246 struct mbuf *m; 2247 struct fxp_rfa *rfa, *p_rfa; 2248 struct fxp_rx *p_rx; 2249 bus_dmamap_t tmp_map; 2250 int error; 2251 2252 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2253 if (m == NULL) 2254 return (ENOBUFS); 2255 2256 /* 2257 * Move the data pointer up so that the incoming data packet 2258 * will be 32-bit aligned. 2259 */ 2260 m->m_data += RFA_ALIGNMENT_FUDGE; 2261 2262 /* 2263 * Get a pointer to the base of the mbuf cluster and move 2264 * data start past it. 2265 */ 2266 rfa = mtod(m, struct fxp_rfa *); 2267 m->m_data += sc->rfa_size; 2268 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2269 2270 rfa->rfa_status = 0; 2271 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2272 rfa->actual_size = 0; 2273 2274 /* 2275 * Initialize the rest of the RFA. Note that since the RFA 2276 * is misaligned, we cannot store values directly. We're thus 2277 * using the le32enc() function which handles endianness and 2278 * is also alignment-safe. 2279 */ 2280 le32enc(&rfa->link_addr, 0xffffffff); 2281 le32enc(&rfa->rbd_addr, 0xffffffff); 2282 2283 /* Map the RFA into DMA memory. */ 2284 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2285 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2286 &rxp->rx_addr, 0); 2287 if (error) { 2288 m_freem(m); 2289 return (error); 2290 } 2291 2292 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2293 tmp_map = sc->spare_map; 2294 sc->spare_map = rxp->rx_map; 2295 rxp->rx_map = tmp_map; 2296 rxp->rx_mbuf = m; 2297 2298 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2299 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2300 2301 /* 2302 * If there are other buffers already on the list, attach this 2303 * one to the end by fixing up the tail to point to this one. 2304 */ 2305 if (sc->fxp_desc.rx_head != NULL) { 2306 p_rx = sc->fxp_desc.rx_tail; 2307 p_rfa = (struct fxp_rfa *) 2308 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2309 p_rx->rx_next = rxp; 2310 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2311 p_rfa->rfa_control = 0; 2312 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2313 BUS_DMASYNC_PREWRITE); 2314 } else { 2315 rxp->rx_next = NULL; 2316 sc->fxp_desc.rx_head = rxp; 2317 } 2318 sc->fxp_desc.rx_tail = rxp; 2319 return (0); 2320} 2321 2322static volatile int 2323fxp_miibus_readreg(device_t dev, int phy, int reg) 2324{ 2325 struct fxp_softc *sc = device_get_softc(dev); 2326 int count = 10000; 2327 int value; 2328 2329 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2330 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2331 2332 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2333 && count--) 2334 DELAY(10); 2335 2336 if (count <= 0) 2337 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2338 2339 return (value & 0xffff); 2340} 2341 2342static void 2343fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2344{ 2345 struct fxp_softc *sc = device_get_softc(dev); 2346 int count = 10000; 2347 2348 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2349 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2350 (value & 0xffff)); 2351 2352 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2353 count--) 2354 DELAY(10); 2355 2356 if (count <= 0) 2357 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2358} 2359 2360static int 2361fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2362{ 2363 struct fxp_softc *sc = ifp->if_softc; 2364 struct ifreq *ifr = (struct ifreq *)data; 2365 struct mii_data *mii; 2366 int flag, mask, s, error = 0; 2367 2368 /* 2369 * Detaching causes us to call ioctl with the mutex owned. Preclude 2370 * that by saying we're busy if the lock is already held. 2371 */ 2372 if (FXP_LOCKED(sc)) 2373 return (EBUSY); 2374 2375 FXP_LOCK(sc); 2376 s = splimp(); 2377 2378 switch (command) { 2379 case SIOCSIFFLAGS: 2380 if (ifp->if_flags & IFF_ALLMULTI) 2381 sc->flags |= FXP_FLAG_ALL_MCAST; 2382 else 2383 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2384 2385 /* 2386 * If interface is marked up and not running, then start it. 2387 * If it is marked down and running, stop it. 2388 * XXX If it's up then re-initialize it. This is so flags 2389 * such as IFF_PROMISC are handled. 2390 */ 2391 if (ifp->if_flags & IFF_UP) { 2392 fxp_init_body(sc); 2393 } else { 2394 if (ifp->if_flags & IFF_RUNNING) 2395 fxp_stop(sc); 2396 } 2397 break; 2398 2399 case SIOCADDMULTI: 2400 case SIOCDELMULTI: 2401 if (ifp->if_flags & IFF_ALLMULTI) 2402 sc->flags |= FXP_FLAG_ALL_MCAST; 2403 else 2404 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2405 /* 2406 * Multicast list has changed; set the hardware filter 2407 * accordingly. 2408 */ 2409 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2410 fxp_mc_setup(sc); 2411 /* 2412 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2413 * again rather than else {}. 2414 */ 2415 if (sc->flags & FXP_FLAG_ALL_MCAST) 2416 fxp_init_body(sc); 2417 error = 0; 2418 break; 2419 2420 case SIOCSIFMEDIA: 2421 case SIOCGIFMEDIA: 2422 if (sc->miibus != NULL) { 2423 mii = device_get_softc(sc->miibus); 2424 error = ifmedia_ioctl(ifp, ifr, 2425 &mii->mii_media, command); 2426 } else { 2427 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2428 } 2429 break; 2430 2431 case SIOCSIFCAP: 2432 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2433 if (mask & IFCAP_POLLING) 2434 ifp->if_capenable ^= IFCAP_POLLING; 2435 if (mask & IFCAP_VLAN_MTU) { 2436 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2437 if (sc->revision != FXP_REV_82557) 2438 flag = FXP_FLAG_LONG_PKT_EN; 2439 else /* a hack to get long frames on the old chip */ 2440 flag = FXP_FLAG_SAVE_BAD; 2441 sc->flags ^= flag; 2442 if (ifp->if_flags & IFF_UP) 2443 fxp_init_body(sc); 2444 } 2445 break; 2446 2447 default: 2448 /* 2449 * ether_ioctl() will eventually call fxp_start() which 2450 * will result in mutex recursion so drop it first. 2451 */ 2452 FXP_UNLOCK(sc); 2453 error = ether_ioctl(ifp, command, data); 2454 } 2455 if (FXP_LOCKED(sc)) 2456 FXP_UNLOCK(sc); 2457 splx(s); 2458 return (error); 2459} 2460 2461/* 2462 * Fill in the multicast address list and return number of entries. 2463 */ 2464static int 2465fxp_mc_addrs(struct fxp_softc *sc) 2466{ 2467 struct fxp_cb_mcs *mcsp = sc->mcsp; 2468 struct ifnet *ifp = &sc->sc_if; 2469 struct ifmultiaddr *ifma; 2470 int nmcasts; 2471 2472 nmcasts = 0; 2473 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2474#if __FreeBSD_version < 500000 2475 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2476#else 2477 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2478#endif 2479 if (ifma->ifma_addr->sa_family != AF_LINK) 2480 continue; 2481 if (nmcasts >= MAXMCADDR) { 2482 sc->flags |= FXP_FLAG_ALL_MCAST; 2483 nmcasts = 0; 2484 break; 2485 } 2486 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2487 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2488 nmcasts++; 2489 } 2490 } 2491 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2492 return (nmcasts); 2493} 2494 2495/* 2496 * Program the multicast filter. 2497 * 2498 * We have an artificial restriction that the multicast setup command 2499 * must be the first command in the chain, so we take steps to ensure 2500 * this. By requiring this, it allows us to keep up the performance of 2501 * the pre-initialized command ring (esp. link pointers) by not actually 2502 * inserting the mcsetup command in the ring - i.e. its link pointer 2503 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2504 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2505 * lead into the regular TxCB ring when it completes. 2506 * 2507 * This function must be called at splimp. 2508 */ 2509static void 2510fxp_mc_setup(struct fxp_softc *sc) 2511{ 2512 struct fxp_cb_mcs *mcsp = sc->mcsp; 2513 struct ifnet *ifp = &sc->sc_if; 2514 struct fxp_tx *txp; 2515 int count; 2516 2517 FXP_LOCK_ASSERT(sc, MA_OWNED); 2518 /* 2519 * If there are queued commands, we must wait until they are all 2520 * completed. If we are already waiting, then add a NOP command 2521 * with interrupt option so that we're notified when all commands 2522 * have been completed - fxp_start() ensures that no additional 2523 * TX commands will be added when need_mcsetup is true. 2524 */ 2525 if (sc->tx_queued) { 2526 /* 2527 * need_mcsetup will be true if we are already waiting for the 2528 * NOP command to be completed (see below). In this case, bail. 2529 */ 2530 if (sc->need_mcsetup) 2531 return; 2532 sc->need_mcsetup = 1; 2533 2534 /* 2535 * Add a NOP command with interrupt so that we are notified 2536 * when all TX commands have been processed. 2537 */ 2538 txp = sc->fxp_desc.tx_last->tx_next; 2539 txp->tx_mbuf = NULL; 2540 txp->tx_cb->cb_status = 0; 2541 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2542 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2543 /* 2544 * Advance the end of list forward. 2545 */ 2546 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2547 htole16(~FXP_CB_COMMAND_S); 2548 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2549 sc->fxp_desc.tx_last = txp; 2550 sc->tx_queued++; 2551 /* 2552 * Issue a resume in case the CU has just suspended. 2553 */ 2554 fxp_scb_wait(sc); 2555 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2556 /* 2557 * Set a 5 second timer just in case we don't hear from the 2558 * card again. 2559 */ 2560 ifp->if_timer = 5; 2561 2562 return; 2563 } 2564 sc->need_mcsetup = 0; 2565 2566 /* 2567 * Initialize multicast setup descriptor. 2568 */ 2569 mcsp->cb_status = 0; 2570 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2571 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2572 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2573 txp = &sc->fxp_desc.mcs_tx; 2574 txp->tx_mbuf = NULL; 2575 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2576 txp->tx_next = sc->fxp_desc.tx_list; 2577 (void) fxp_mc_addrs(sc); 2578 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2579 sc->tx_queued = 1; 2580 2581 /* 2582 * Wait until command unit is not active. This should never 2583 * be the case when nothing is queued, but make sure anyway. 2584 */ 2585 count = 100; 2586 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2587 FXP_SCB_CUS_ACTIVE && --count) 2588 DELAY(10); 2589 if (count == 0) { 2590 device_printf(sc->dev, "command queue timeout\n"); 2591 return; 2592 } 2593 2594 /* 2595 * Start the multicast setup command. 2596 */ 2597 fxp_scb_wait(sc); 2598 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2599 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2600 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2601 2602 ifp->if_timer = 2; 2603 return; 2604} 2605 2606static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2607static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2608static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2609static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2610static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2611static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2612static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2613 2614#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2615 2616struct ucode { 2617 uint32_t revision; 2618 uint32_t *ucode; 2619 int length; 2620 u_short int_delay_offset; 2621 u_short bundle_max_offset; 2622} ucode_table[] = { 2623 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2624 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2625 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2626 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2627 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2628 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2629 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2630 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2631 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2632 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2633 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2634 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2635 { 0, NULL, 0, 0, 0 } 2636}; 2637 2638static void 2639fxp_load_ucode(struct fxp_softc *sc) 2640{ 2641 struct ucode *uc; 2642 struct fxp_cb_ucode *cbp; 2643 int i; 2644 2645 for (uc = ucode_table; uc->ucode != NULL; uc++) 2646 if (sc->revision == uc->revision) 2647 break; 2648 if (uc->ucode == NULL) 2649 return; 2650 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2651 cbp->cb_status = 0; 2652 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2653 cbp->link_addr = 0xffffffff; /* (no) next command */ 2654 for (i = 0; i < uc->length; i++) 2655 cbp->ucode[i] = htole32(uc->ucode[i]); 2656 if (uc->int_delay_offset) 2657 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2658 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2659 if (uc->bundle_max_offset) 2660 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2661 htole16(sc->tunable_bundle_max); 2662 /* 2663 * Download the ucode to the chip. 2664 */ 2665 fxp_scb_wait(sc); 2666 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2667 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2668 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2669 /* ...and wait for it to complete. */ 2670 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2671 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2672 device_printf(sc->dev, 2673 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2674 sc->tunable_int_delay, 2675 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2676 sc->flags |= FXP_FLAG_UCODE; 2677} 2678 2679static int 2680sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2681{ 2682 int error, value; 2683 2684 value = *(int *)arg1; 2685 error = sysctl_handle_int(oidp, &value, 0, req); 2686 if (error || !req->newptr) 2687 return (error); 2688 if (value < low || value > high) 2689 return (EINVAL); 2690 *(int *)arg1 = value; 2691 return (0); 2692} 2693 2694/* 2695 * Interrupt delay is expressed in microseconds, a multiplier is used 2696 * to convert this to the appropriate clock ticks before using. 2697 */ 2698static int 2699sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2700{ 2701 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2702} 2703 2704static int 2705sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2706{ 2707 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2708} 2709