if_fxp.c revision 145368
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 145368 2005-04-21 19:34:57Z mux $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194}; 195 196#ifdef FXP_IP_CSUM_WAR 197#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198#else 199#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200#endif 201 202static int fxp_probe(device_t dev); 203static int fxp_attach(device_t dev); 204static int fxp_detach(device_t dev); 205static int fxp_shutdown(device_t dev); 206static int fxp_suspend(device_t dev); 207static int fxp_resume(device_t dev); 208 209static void fxp_intr(void *xsc); 210static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212static void fxp_init(void *xsc); 213static void fxp_init_body(struct fxp_softc *sc); 214static void fxp_tick(void *xsc); 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218static void fxp_stop(struct fxp_softc *sc); 219static void fxp_release(struct fxp_softc *sc); 220static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222static void fxp_watchdog(struct ifnet *ifp); 223static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225static int fxp_mc_addrs(struct fxp_softc *sc); 226static void fxp_mc_setup(struct fxp_softc *sc); 227static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231static void fxp_autosize_eeprom(struct fxp_softc *sc); 232static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236static int fxp_ifmedia_upd(struct ifnet *ifp); 237static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245static void fxp_load_ucode(struct fxp_softc *sc); 246static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250static void fxp_scb_wait(struct fxp_softc *sc); 251static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270}; 271 272static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276}; 277 278static devclass_t fxp_devclass; 279 280DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284/* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288static void 289fxp_scb_wait(struct fxp_softc *sc) 290{ 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301} 302 303static void 304fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305{ 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312} 313 314static void 315fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317{ 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327} 328 329/* 330 * Return identification string if this device is ours. 331 */ 332static int 333fxp_probe(device_t dev) 334{ 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351} 352 353static void 354fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355{ 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 int i, rid, m1, m2, prefer_iomap; 377 int error, s; 378 379 error = 0; 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 383 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 384 MTX_DEF); 385 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 386 fxp_serial_ifmedia_sts); 387 388 s = splimp(); 389 390 /* 391 * Enable bus mastering. 392 */ 393 pci_enable_busmaster(dev); 394 val = pci_read_config(dev, PCIR_COMMAND, 2); 395 396 /* 397 * Figure out which we should try first - memory mapping or i/o mapping? 398 * We default to memory mapping. Then we accept an override from the 399 * command line. Then we check to see which one is enabled. 400 */ 401 m1 = PCIM_CMD_MEMEN; 402 m2 = PCIM_CMD_PORTEN; 403 prefer_iomap = 0; 404 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 405 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 406 m1 = PCIM_CMD_PORTEN; 407 m2 = PCIM_CMD_MEMEN; 408 } 409 410 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 411 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 412 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 413 if (sc->mem == NULL) { 414 sc->rtp = 415 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 416 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 417 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 418 RF_ACTIVE); 419 } 420 421 if (!sc->mem) { 422 error = ENXIO; 423 goto fail; 424 } 425 if (bootverbose) { 426 device_printf(dev, "using %s space register mapping\n", 427 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 428 } 429 430 sc->sc_st = rman_get_bustag(sc->mem); 431 sc->sc_sh = rman_get_bushandle(sc->mem); 432 433 /* 434 * Allocate our interrupt. 435 */ 436 rid = 0; 437 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 438 RF_SHAREABLE | RF_ACTIVE); 439 if (sc->irq == NULL) { 440 device_printf(dev, "could not map interrupt\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 445 /* 446 * Reset to a stable state. 447 */ 448 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 449 DELAY(10); 450 451 /* 452 * Find out how large of an SEEPROM we have. 453 */ 454 fxp_autosize_eeprom(sc); 455 456 /* 457 * Find out the chip revision; lump all 82557 revs together. 458 */ 459 fxp_read_eeprom(sc, &data, 5, 1); 460 if ((data >> 8) == 1) 461 sc->revision = FXP_REV_82557; 462 else 463 sc->revision = pci_get_revid(dev); 464 465 /* 466 * Determine whether we must use the 503 serial interface. 467 */ 468 fxp_read_eeprom(sc, &data, 6, 1); 469 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 470 && (data & FXP_PHY_SERIAL_ONLY)) 471 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 472 473 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 475 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 476 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 477 "FXP driver receive interrupt microcode bundling delay"); 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 480 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 481 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 482 "FXP driver receive interrupt microcode bundle size limit"); 483 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 486 "FXP RNR events"); 487 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 490 "FXP flow control disabled"); 491 492 /* 493 * Pull in device tunables. 494 */ 495 sc->tunable_int_delay = TUNABLE_INT_DELAY; 496 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 497 sc->tunable_noflow = 1; 498 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 499 "int_delay", &sc->tunable_int_delay); 500 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 501 "bundle_max", &sc->tunable_bundle_max); 502 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 503 "noflow", &sc->tunable_noflow); 504 sc->rnr = 0; 505 506 /* 507 * Enable workarounds for certain chip revision deficiencies. 508 * 509 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 510 * some systems based a normal 82559 design, have a defect where 511 * the chip can cause a PCI protocol violation if it receives 512 * a CU_RESUME command when it is entering the IDLE state. The 513 * workaround is to disable Dynamic Standby Mode, so the chip never 514 * deasserts CLKRUN#, and always remains in an active state. 515 * 516 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 517 */ 518 i = pci_get_device(dev); 519 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 520 sc->revision >= FXP_REV_82559_A0) { 521 fxp_read_eeprom(sc, &data, 10, 1); 522 if (data & 0x02) { /* STB enable */ 523 uint16_t cksum; 524 int i; 525 526 device_printf(dev, 527 "Disabling dynamic standby mode in EEPROM\n"); 528 data &= ~0x02; 529 fxp_write_eeprom(sc, &data, 10, 1); 530 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 531 cksum = 0; 532 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 533 fxp_read_eeprom(sc, &data, i, 1); 534 cksum += data; 535 } 536 i = (1 << sc->eeprom_size) - 1; 537 cksum = 0xBABA - cksum; 538 fxp_read_eeprom(sc, &data, i, 1); 539 fxp_write_eeprom(sc, &cksum, i, 1); 540 device_printf(dev, 541 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 542 i, data, cksum); 543#if 1 544 /* 545 * If the user elects to continue, try the software 546 * workaround, as it is better than nothing. 547 */ 548 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 549#endif 550 } 551 } 552 553 /* 554 * If we are not a 82557 chip, we can enable extended features. 555 */ 556 if (sc->revision != FXP_REV_82557) { 557 /* 558 * If MWI is enabled in the PCI configuration, and there 559 * is a valid cacheline size (8 or 16 dwords), then tell 560 * the board to turn on MWI. 561 */ 562 if (val & PCIM_CMD_MWRICEN && 563 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 564 sc->flags |= FXP_FLAG_MWI_ENABLE; 565 566 /* turn on the extended TxCB feature */ 567 sc->flags |= FXP_FLAG_EXT_TXCB; 568 569 /* enable reception of long frames for VLAN */ 570 sc->flags |= FXP_FLAG_LONG_PKT_EN; 571 } else { 572 /* a hack to get long VLAN frames on a 82557 */ 573 sc->flags |= FXP_FLAG_SAVE_BAD; 574 } 575 576 /* 577 * Enable use of extended RFDs and TCBs for 82550 578 * and later chips. Note: we need extended TXCB support 579 * too, but that's already enabled by the code above. 580 * Be careful to do this only on the right devices. 581 */ 582 if (sc->revision >= FXP_REV_82550) { 583 sc->rfa_size = sizeof (struct fxp_rfa); 584 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 585 sc->flags |= FXP_FLAG_EXT_RFA; 586 } else { 587 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 588 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 589 } 590 591 /* 592 * Allocate DMA tags and DMA safe memory. 593 */ 594 sc->maxtxseg = FXP_NTXSEG; 595 if (sc->flags & FXP_FLAG_EXT_RFA) 596 sc->maxtxseg--; 597 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 598 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 599 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 600 &sc->fxp_mtag); 601 if (error) { 602 device_printf(dev, "could not allocate dma tag\n"); 603 goto fail; 604 } 605 606 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 607 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 608 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 609 &sc->fxp_stag); 610 if (error) { 611 device_printf(dev, "could not allocate dma tag\n"); 612 goto fail; 613 } 614 615 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 616 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 617 if (error) 618 goto fail; 619 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 620 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 621 if (error) { 622 device_printf(dev, "could not map the stats buffer\n"); 623 goto fail; 624 } 625 626 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 627 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 628 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 629 if (error) { 630 device_printf(dev, "could not allocate dma tag\n"); 631 goto fail; 632 } 633 634 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 635 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 636 if (error) 637 goto fail; 638 639 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 640 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 641 &sc->fxp_desc.cbl_addr, 0); 642 if (error) { 643 device_printf(dev, "could not map DMA memory\n"); 644 goto fail; 645 } 646 647 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 648 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 649 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 650 &sc->mcs_tag); 651 if (error) { 652 device_printf(dev, "could not allocate dma tag\n"); 653 goto fail; 654 } 655 656 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 657 BUS_DMA_NOWAIT, &sc->mcs_map); 658 if (error) 659 goto fail; 660 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 661 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 662 if (error) { 663 device_printf(dev, "can't map the multicast setup command\n"); 664 goto fail; 665 } 666 667 /* 668 * Pre-allocate the TX DMA maps and setup the pointers to 669 * the TX command blocks. 670 */ 671 txp = sc->fxp_desc.tx_list; 672 tcbp = sc->fxp_desc.cbl_list; 673 for (i = 0; i < FXP_NTXCB; i++) { 674 txp[i].tx_cb = tcbp + i; 675 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 676 if (error) { 677 device_printf(dev, "can't create DMA map for TX\n"); 678 goto fail; 679 } 680 } 681 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 682 if (error) { 683 device_printf(dev, "can't create spare DMA map\n"); 684 goto fail; 685 } 686 687 /* 688 * Pre-allocate our receive buffers. 689 */ 690 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 691 for (i = 0; i < FXP_NRFABUFS; i++) { 692 rxp = &sc->fxp_desc.rx_list[i]; 693 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 694 if (error) { 695 device_printf(dev, "can't create DMA map for RX\n"); 696 goto fail; 697 } 698 if (fxp_add_rfabuf(sc, rxp) != 0) { 699 error = ENOMEM; 700 goto fail; 701 } 702 } 703 704 /* 705 * Read MAC address. 706 */ 707 fxp_read_eeprom(sc, myea, 0, 3); 708 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 709 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 710 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 711 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 712 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 713 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 714 if (bootverbose) { 715 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 716 pci_get_vendor(dev), pci_get_device(dev), 717 pci_get_subvendor(dev), pci_get_subdevice(dev), 718 pci_get_revid(dev)); 719 fxp_read_eeprom(sc, &data, 10, 1); 720 device_printf(dev, "Dynamic Standby mode is %s\n", 721 data & 0x02 ? "enabled" : "disabled"); 722 } 723 724 /* 725 * If this is only a 10Mbps device, then there is no MII, and 726 * the PHY will use a serial interface instead. 727 * 728 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 729 * doesn't have a programming interface of any sort. The 730 * media is sensed automatically based on how the link partner 731 * is configured. This is, in essence, manual configuration. 732 */ 733 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 734 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 735 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 736 } else { 737 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 738 fxp_ifmedia_sts)) { 739 device_printf(dev, "MII without any PHY!\n"); 740 error = ENXIO; 741 goto fail; 742 } 743 } 744 745 ifp = &sc->arpcom.ac_if; 746 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 747 ifp->if_baudrate = 100000000; 748 ifp->if_init = fxp_init; 749 ifp->if_softc = sc; 750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 751 ifp->if_ioctl = fxp_ioctl; 752 ifp->if_start = fxp_start; 753 ifp->if_watchdog = fxp_watchdog; 754 755 ifp->if_capabilities = ifp->if_capenable = 0; 756 757 /* Enable checksum offload for 82550 or better chips */ 758 if (sc->flags & FXP_FLAG_EXT_RFA) { 759 ifp->if_hwassist = FXP_CSUM_FEATURES; 760 ifp->if_capabilities |= IFCAP_HWCSUM; 761 ifp->if_capenable |= IFCAP_HWCSUM; 762 } 763 764#ifdef DEVICE_POLLING 765 /* Inform the world we support polling. */ 766 ifp->if_capabilities |= IFCAP_POLLING; 767 ifp->if_capenable |= IFCAP_POLLING; 768#endif 769 770 /* 771 * Attach the interface. 772 */ 773 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 774 775 /* 776 * Tell the upper layer(s) we support long frames. 777 * Must appear after the call to ether_ifattach() because 778 * ether_ifattach() sets ifi_hdrlen to the default value. 779 */ 780 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 781 ifp->if_capabilities |= IFCAP_VLAN_MTU; 782 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 783 784 /* 785 * Let the system queue as many packets as we have available 786 * TX descriptors. 787 */ 788 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 789 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 790 IFQ_SET_READY(&ifp->if_snd); 791 792 /* 793 * Hook our interrupt after all initialization is complete. 794 */ 795 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 796 fxp_intr, sc, &sc->ih); 797 if (error) { 798 device_printf(dev, "could not setup irq\n"); 799 ether_ifdetach(&sc->arpcom.ac_if); 800 goto fail; 801 } 802 803fail: 804 splx(s); 805 if (error) 806 fxp_release(sc); 807 return (error); 808} 809 810/* 811 * Release all resources. The softc lock should not be held and the 812 * interrupt should already be torn down. 813 */ 814static void 815fxp_release(struct fxp_softc *sc) 816{ 817 struct fxp_rx *rxp; 818 struct fxp_tx *txp; 819 int i; 820 821 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 822 KASSERT(sc->ih == NULL, 823 ("fxp_release() called with intr handle still active")); 824 if (sc->miibus) 825 device_delete_child(sc->dev, sc->miibus); 826 bus_generic_detach(sc->dev); 827 ifmedia_removeall(&sc->sc_media); 828 if (sc->fxp_desc.cbl_list) { 829 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 830 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 831 sc->cbl_map); 832 } 833 if (sc->fxp_stats) { 834 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 835 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 836 } 837 if (sc->mcsp) { 838 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 839 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 840 } 841 if (sc->irq) 842 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 843 if (sc->mem) 844 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 845 if (sc->fxp_mtag) { 846 for (i = 0; i < FXP_NRFABUFS; i++) { 847 rxp = &sc->fxp_desc.rx_list[i]; 848 if (rxp->rx_mbuf != NULL) { 849 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 850 BUS_DMASYNC_POSTREAD); 851 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 852 m_freem(rxp->rx_mbuf); 853 } 854 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 855 } 856 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 857 for (i = 0; i < FXP_NTXCB; i++) { 858 txp = &sc->fxp_desc.tx_list[i]; 859 if (txp->tx_mbuf != NULL) { 860 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 861 BUS_DMASYNC_POSTWRITE); 862 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 863 m_freem(txp->tx_mbuf); 864 } 865 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 866 } 867 bus_dma_tag_destroy(sc->fxp_mtag); 868 } 869 if (sc->fxp_stag) 870 bus_dma_tag_destroy(sc->fxp_stag); 871 if (sc->cbl_tag) 872 bus_dma_tag_destroy(sc->cbl_tag); 873 if (sc->mcs_tag) 874 bus_dma_tag_destroy(sc->mcs_tag); 875 876 mtx_destroy(&sc->sc_mtx); 877} 878 879/* 880 * Detach interface. 881 */ 882static int 883fxp_detach(device_t dev) 884{ 885 struct fxp_softc *sc = device_get_softc(dev); 886 int s; 887 888 FXP_LOCK(sc); 889 s = splimp(); 890 891 sc->suspended = 1; /* Do same thing as we do for suspend */ 892 /* 893 * Close down routes etc. 894 */ 895 ether_ifdetach(&sc->arpcom.ac_if); 896 897 /* 898 * Stop DMA and drop transmit queue, but disable interrupts first. 899 */ 900 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 901 fxp_stop(sc); 902 FXP_UNLOCK(sc); 903 904 /* 905 * Unhook interrupt before dropping lock. This is to prevent 906 * races with fxp_intr(). 907 */ 908 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 909 sc->ih = NULL; 910 911 splx(s); 912 913 /* Release our allocated resources. */ 914 fxp_release(sc); 915 return (0); 916} 917 918/* 919 * Device shutdown routine. Called at system shutdown after sync. The 920 * main purpose of this routine is to shut off receiver DMA so that 921 * kernel memory doesn't get clobbered during warmboot. 922 */ 923static int 924fxp_shutdown(device_t dev) 925{ 926 /* 927 * Make sure that DMA is disabled prior to reboot. Not doing 928 * do could allow DMA to corrupt kernel memory during the 929 * reboot before the driver initializes. 930 */ 931 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 932 return (0); 933} 934 935/* 936 * Device suspend routine. Stop the interface and save some PCI 937 * settings in case the BIOS doesn't restore them properly on 938 * resume. 939 */ 940static int 941fxp_suspend(device_t dev) 942{ 943 struct fxp_softc *sc = device_get_softc(dev); 944 int i, s; 945 946 FXP_LOCK(sc); 947 s = splimp(); 948 949 fxp_stop(sc); 950 951 for (i = 0; i < 5; i++) 952 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 953 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 954 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 955 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 956 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 957 958 sc->suspended = 1; 959 960 FXP_UNLOCK(sc); 961 splx(s); 962 return (0); 963} 964 965/* 966 * Device resume routine. Restore some PCI settings in case the BIOS 967 * doesn't, re-enable busmastering, and restart the interface if 968 * appropriate. 969 */ 970static int 971fxp_resume(device_t dev) 972{ 973 struct fxp_softc *sc = device_get_softc(dev); 974 struct ifnet *ifp = &sc->sc_if; 975 uint16_t pci_command; 976 int i, s; 977 978 FXP_LOCK(sc); 979 s = splimp(); 980 981 /* better way to do this? */ 982 for (i = 0; i < 5; i++) 983 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 984 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 985 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 986 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 987 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 988 989 /* reenable busmastering */ 990 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 991 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 992 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 993 994 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 995 DELAY(10); 996 997 /* reinitialize interface if necessary */ 998 if (ifp->if_flags & IFF_UP) 999 fxp_init_body(sc); 1000 1001 sc->suspended = 0; 1002 1003 FXP_UNLOCK(sc); 1004 splx(s); 1005 return (0); 1006} 1007 1008static void 1009fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1010{ 1011 uint16_t reg; 1012 int x; 1013 1014 /* 1015 * Shift in data. 1016 */ 1017 for (x = 1 << (length - 1); x; x >>= 1) { 1018 if (data & x) 1019 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1020 else 1021 reg = FXP_EEPROM_EECS; 1022 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1023 DELAY(1); 1024 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1025 DELAY(1); 1026 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1027 DELAY(1); 1028 } 1029} 1030 1031/* 1032 * Read from the serial EEPROM. Basically, you manually shift in 1033 * the read opcode (one bit at a time) and then shift in the address, 1034 * and then you shift out the data (all of this one bit at a time). 1035 * The word size is 16 bits, so you have to provide the address for 1036 * every 16 bits of data. 1037 */ 1038static uint16_t 1039fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1040{ 1041 uint16_t reg, data; 1042 int x; 1043 1044 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1045 /* 1046 * Shift in read opcode. 1047 */ 1048 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1049 /* 1050 * Shift in address. 1051 */ 1052 data = 0; 1053 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1054 if (offset & x) 1055 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1056 else 1057 reg = FXP_EEPROM_EECS; 1058 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1059 DELAY(1); 1060 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1061 DELAY(1); 1062 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1063 DELAY(1); 1064 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1065 data++; 1066 if (autosize && reg == 0) { 1067 sc->eeprom_size = data; 1068 break; 1069 } 1070 } 1071 /* 1072 * Shift out data. 1073 */ 1074 data = 0; 1075 reg = FXP_EEPROM_EECS; 1076 for (x = 1 << 15; x; x >>= 1) { 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1078 DELAY(1); 1079 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1080 data |= x; 1081 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1082 DELAY(1); 1083 } 1084 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1085 DELAY(1); 1086 1087 return (data); 1088} 1089 1090static void 1091fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1092{ 1093 int i; 1094 1095 /* 1096 * Erase/write enable. 1097 */ 1098 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1099 fxp_eeprom_shiftin(sc, 0x4, 3); 1100 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1101 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1102 DELAY(1); 1103 /* 1104 * Shift in write opcode, address, data. 1105 */ 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1107 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1108 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1109 fxp_eeprom_shiftin(sc, data, 16); 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1111 DELAY(1); 1112 /* 1113 * Wait for EEPROM to finish up. 1114 */ 1115 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1116 DELAY(1); 1117 for (i = 0; i < 1000; i++) { 1118 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1119 break; 1120 DELAY(50); 1121 } 1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1123 DELAY(1); 1124 /* 1125 * Erase/write disable. 1126 */ 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1128 fxp_eeprom_shiftin(sc, 0x4, 3); 1129 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1131 DELAY(1); 1132} 1133 1134/* 1135 * From NetBSD: 1136 * 1137 * Figure out EEPROM size. 1138 * 1139 * 559's can have either 64-word or 256-word EEPROMs, the 558 1140 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1141 * talks about the existance of 16 to 256 word EEPROMs. 1142 * 1143 * The only known sizes are 64 and 256, where the 256 version is used 1144 * by CardBus cards to store CIS information. 1145 * 1146 * The address is shifted in msb-to-lsb, and after the last 1147 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1148 * after which follows the actual data. We try to detect this zero, by 1149 * probing the data-out bit in the EEPROM control register just after 1150 * having shifted in a bit. If the bit is zero, we assume we've 1151 * shifted enough address bits. The data-out should be tri-state, 1152 * before this, which should translate to a logical one. 1153 */ 1154static void 1155fxp_autosize_eeprom(struct fxp_softc *sc) 1156{ 1157 1158 /* guess maximum size of 256 words */ 1159 sc->eeprom_size = 8; 1160 1161 /* autosize */ 1162 (void) fxp_eeprom_getword(sc, 0, 1); 1163} 1164 1165static void 1166fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1167{ 1168 int i; 1169 1170 for (i = 0; i < words; i++) 1171 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1172} 1173 1174static void 1175fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1176{ 1177 int i; 1178 1179 for (i = 0; i < words; i++) 1180 fxp_eeprom_putword(sc, offset + i, data[i]); 1181} 1182 1183/* 1184 * Grab the softc lock and call the real fxp_start_body() routine 1185 */ 1186static void 1187fxp_start(struct ifnet *ifp) 1188{ 1189 struct fxp_softc *sc = ifp->if_softc; 1190 1191 FXP_LOCK(sc); 1192 fxp_start_body(ifp); 1193 FXP_UNLOCK(sc); 1194} 1195 1196/* 1197 * Start packet transmission on the interface. 1198 * This routine must be called with the softc lock held, and is an 1199 * internal entry point only. 1200 */ 1201static void 1202fxp_start_body(struct ifnet *ifp) 1203{ 1204 struct fxp_softc *sc = ifp->if_softc; 1205 struct mbuf *mb_head; 1206 int error, txqueued; 1207 1208 FXP_LOCK_ASSERT(sc, MA_OWNED); 1209 1210 /* 1211 * See if we need to suspend xmit until the multicast filter 1212 * has been reprogrammed (which can only be done at the head 1213 * of the command chain). 1214 */ 1215 if (sc->need_mcsetup) 1216 return; 1217 1218 /* 1219 * We're finished if there is nothing more to add to the list or if 1220 * we're all filled up with buffers to transmit. 1221 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1222 * a NOP command when needed. 1223 */ 1224 txqueued = 0; 1225 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1226 sc->tx_queued < FXP_NTXCB - 1) { 1227 1228 /* 1229 * Grab a packet to transmit. 1230 */ 1231 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1232 if (mb_head == NULL) 1233 break; 1234 1235 error = fxp_encap(sc, mb_head); 1236 if (error) 1237 break; 1238 txqueued = 1; 1239 } 1240 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1241 1242 /* 1243 * We're finished. If we added to the list, issue a RESUME to get DMA 1244 * going again if suspended. 1245 */ 1246 if (txqueued) { 1247 fxp_scb_wait(sc); 1248 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1249 } 1250} 1251 1252static int 1253fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1254{ 1255 struct ifnet *ifp; 1256 struct mbuf *m; 1257 struct fxp_tx *txp; 1258 struct fxp_cb_tx *cbp; 1259 bus_dma_segment_t segs[FXP_NTXSEG]; 1260 int chainlen, error, i, nseg; 1261 1262 FXP_LOCK_ASSERT(sc, MA_OWNED); 1263 ifp = &sc->sc_if; 1264 1265 /* 1266 * Get pointer to next available tx desc. 1267 */ 1268 txp = sc->fxp_desc.tx_last->tx_next; 1269 1270 /* 1271 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1272 * Ethernet Controller Family Open Source Software 1273 * Developer Manual says: 1274 * Using software parsing is only allowed with legal 1275 * TCP/IP or UDP/IP packets. 1276 * ... 1277 * For all other datagrams, hardware parsing must 1278 * be used. 1279 * Software parsing appears to truncate ICMP and 1280 * fragmented UDP packets that contain one to three 1281 * bytes in the second (and final) mbuf of the packet. 1282 */ 1283 if (sc->flags & FXP_FLAG_EXT_RFA) 1284 txp->tx_cb->ipcb_ip_activation_high = 1285 FXP_IPCB_HARDWAREPARSING_ENABLE; 1286 1287 /* 1288 * Deal with TCP/IP checksum offload. Note that 1289 * in order for TCP checksum offload to work, 1290 * the pseudo header checksum must have already 1291 * been computed and stored in the checksum field 1292 * in the TCP header. The stack should have 1293 * already done this for us. 1294 */ 1295 if (m_head->m_pkthdr.csum_flags) { 1296 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1297 txp->tx_cb->ipcb_ip_schedule = 1298 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1299 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1300 txp->tx_cb->ipcb_ip_schedule |= 1301 FXP_IPCB_TCP_PACKET; 1302 } 1303 1304#ifdef FXP_IP_CSUM_WAR 1305 /* 1306 * XXX The 82550 chip appears to have trouble 1307 * dealing with IP header checksums in very small 1308 * datagrams, namely fragments from 1 to 3 bytes 1309 * in size. For example, say you want to transmit 1310 * a UDP packet of 1473 bytes. The packet will be 1311 * fragmented over two IP datagrams, the latter 1312 * containing only one byte of data. The 82550 will 1313 * botch the header checksum on the 1-byte fragment. 1314 * As long as the datagram contains 4 or more bytes 1315 * of data, you're ok. 1316 * 1317 * The following code attempts to work around this 1318 * problem: if the datagram is less than 38 bytes 1319 * in size (14 bytes ether header, 20 bytes IP header, 1320 * plus 4 bytes of data), we punt and compute the IP 1321 * header checksum by hand. This workaround doesn't 1322 * work very well, however, since it can be fooled 1323 * by things like VLAN tags and IP options that make 1324 * the header sizes/offsets vary. 1325 */ 1326 1327 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1328 if (m_head->m_pkthdr.len < 38) { 1329 struct ip *ip; 1330 m_head->m_data += ETHER_HDR_LEN; 1331 ip = mtod(mb_head, struct ip *); 1332 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1333 m_head->m_data -= ETHER_HDR_LEN; 1334 } else { 1335 txp->tx_cb->ipcb_ip_activation_high = 1336 FXP_IPCB_HARDWAREPARSING_ENABLE; 1337 txp->tx_cb->ipcb_ip_schedule |= 1338 FXP_IPCB_IP_CHECKSUM_ENABLE; 1339 } 1340 } 1341#endif 1342 } 1343 1344 chainlen = 0; 1345 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1346 chainlen++; 1347 if (chainlen > sc->maxtxseg) { 1348 struct mbuf *mn; 1349 1350 /* 1351 * We ran out of segments. We have to recopy this 1352 * mbuf chain first. Bail out if we can't get the 1353 * new buffers. 1354 */ 1355 mn = m_defrag(m_head, M_DONTWAIT); 1356 if (mn == NULL) { 1357 m_freem(m_head); 1358 return (-1); 1359 } else { 1360 m_head = mn; 1361 } 1362 } 1363 1364 /* 1365 * Go through each of the mbufs in the chain and initialize 1366 * the transmit buffer descriptors with the physical address 1367 * and size of the mbuf. 1368 */ 1369 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1370 m_head, segs, &nseg, 0); 1371 if (error) { 1372 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1373 m_freem(m_head); 1374 return (-1); 1375 } 1376 1377 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1378 1379 cbp = txp->tx_cb; 1380 for (i = 0; i < nseg; i++) { 1381 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1382 /* 1383 * If this is an 82550/82551, then we're using extended 1384 * TxCBs _and_ we're using checksum offload. This means 1385 * that the TxCB is really an IPCB. One major difference 1386 * between the two is that with plain extended TxCBs, 1387 * the bottom half of the TxCB contains two entries from 1388 * the TBD array, whereas IPCBs contain just one entry: 1389 * one entry (8 bytes) has been sacrificed for the TCP/IP 1390 * checksum offload control bits. So to make things work 1391 * right, we have to start filling in the TBD array 1392 * starting from a different place depending on whether 1393 * the chip is an 82550/82551 or not. 1394 */ 1395 if (sc->flags & FXP_FLAG_EXT_RFA) { 1396 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1397 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1398 } else { 1399 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1400 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1401 } 1402 } 1403 cbp->tbd_number = nseg; 1404 1405 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1406 txp->tx_mbuf = m_head; 1407 txp->tx_cb->cb_status = 0; 1408 txp->tx_cb->byte_count = 0; 1409 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1410 txp->tx_cb->cb_command = 1411 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1412 FXP_CB_COMMAND_S); 1413 } else { 1414 txp->tx_cb->cb_command = 1415 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1416 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1417 /* 1418 * Set a 5 second timer just in case we don't hear 1419 * from the card again. 1420 */ 1421 ifp->if_timer = 5; 1422 } 1423 txp->tx_cb->tx_threshold = tx_threshold; 1424 1425 /* 1426 * Advance the end of list forward. 1427 */ 1428 1429#ifdef __alpha__ 1430 /* 1431 * On platforms which can't access memory in 16-bit 1432 * granularities, we must prevent the card from DMA'ing 1433 * up the status while we update the command field. 1434 * This could cause us to overwrite the completion status. 1435 * XXX This is probably bogus and we're _not_ looking 1436 * for atomicity here. 1437 */ 1438 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1439 htole16(FXP_CB_COMMAND_S)); 1440#else 1441 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1442#endif /*__alpha__*/ 1443 sc->fxp_desc.tx_last = txp; 1444 1445 /* 1446 * Advance the beginning of the list forward if there are 1447 * no other packets queued (when nothing is queued, tx_first 1448 * sits on the last TxCB that was sent out). 1449 */ 1450 if (sc->tx_queued == 0) 1451 sc->fxp_desc.tx_first = txp; 1452 1453 sc->tx_queued++; 1454 1455 /* 1456 * Pass packet to bpf if there is a listener. 1457 */ 1458 BPF_MTAP(ifp, m_head); 1459 return (0); 1460} 1461 1462#ifdef DEVICE_POLLING 1463static poll_handler_t fxp_poll; 1464 1465static void 1466fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1467{ 1468 struct fxp_softc *sc = ifp->if_softc; 1469 uint8_t statack; 1470 1471 FXP_LOCK(sc); 1472 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1473 ether_poll_deregister(ifp); 1474 cmd = POLL_DEREGISTER; 1475 } 1476 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1477 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1478 FXP_UNLOCK(sc); 1479 return; 1480 } 1481 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1482 FXP_SCB_STATACK_FR; 1483 if (cmd == POLL_AND_CHECK_STATUS) { 1484 uint8_t tmp; 1485 1486 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1487 if (tmp == 0xff || tmp == 0) { 1488 FXP_UNLOCK(sc); 1489 return; /* nothing to do */ 1490 } 1491 tmp &= ~statack; 1492 /* ack what we can */ 1493 if (tmp != 0) 1494 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1495 statack |= tmp; 1496 } 1497 fxp_intr_body(sc, ifp, statack, count); 1498 FXP_UNLOCK(sc); 1499} 1500#endif /* DEVICE_POLLING */ 1501 1502/* 1503 * Process interface interrupts. 1504 */ 1505static void 1506fxp_intr(void *xsc) 1507{ 1508 struct fxp_softc *sc = xsc; 1509 struct ifnet *ifp = &sc->sc_if; 1510 uint8_t statack; 1511 1512 FXP_LOCK(sc); 1513 if (sc->suspended) { 1514 FXP_UNLOCK(sc); 1515 return; 1516 } 1517 1518#ifdef DEVICE_POLLING 1519 if (ifp->if_flags & IFF_POLLING) { 1520 FXP_UNLOCK(sc); 1521 return; 1522 } 1523 if ((ifp->if_capenable & IFCAP_POLLING) && 1524 ether_poll_register(fxp_poll, ifp)) { 1525 /* disable interrupts */ 1526 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1527 FXP_UNLOCK(sc); 1528 fxp_poll(ifp, 0, 1); 1529 return; 1530 } 1531#endif 1532 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1533 /* 1534 * It should not be possible to have all bits set; the 1535 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1536 * all bits are set, this may indicate that the card has 1537 * been physically ejected, so ignore it. 1538 */ 1539 if (statack == 0xff) { 1540 FXP_UNLOCK(sc); 1541 return; 1542 } 1543 1544 /* 1545 * First ACK all the interrupts in this pass. 1546 */ 1547 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1548 fxp_intr_body(sc, ifp, statack, -1); 1549 } 1550 FXP_UNLOCK(sc); 1551} 1552 1553static void 1554fxp_txeof(struct fxp_softc *sc) 1555{ 1556 struct fxp_tx *txp; 1557 1558 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1559 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1560 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1561 txp = txp->tx_next) { 1562 if (txp->tx_mbuf != NULL) { 1563 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1564 BUS_DMASYNC_POSTWRITE); 1565 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1566 m_freem(txp->tx_mbuf); 1567 txp->tx_mbuf = NULL; 1568 /* clear this to reset csum offload bits */ 1569 txp->tx_cb->tbd[0].tb_addr = 0; 1570 } 1571 sc->tx_queued--; 1572 } 1573 sc->fxp_desc.tx_first = txp; 1574 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1575} 1576 1577static void 1578fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1579 int count) 1580{ 1581 struct mbuf *m; 1582 struct fxp_rx *rxp; 1583 struct fxp_rfa *rfa; 1584 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1585 1586 FXP_LOCK_ASSERT(sc, MA_OWNED); 1587 if (rnr) 1588 sc->rnr++; 1589#ifdef DEVICE_POLLING 1590 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1591 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1592 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1593 rnr = 1; 1594 } 1595#endif 1596 1597 /* 1598 * Free any finished transmit mbuf chains. 1599 * 1600 * Handle the CNA event likt a CXTNO event. It used to 1601 * be that this event (control unit not ready) was not 1602 * encountered, but it is now with the SMPng modifications. 1603 * The exact sequence of events that occur when the interface 1604 * is brought up are different now, and if this event 1605 * goes unhandled, the configuration/rxfilter setup sequence 1606 * can stall for several seconds. The result is that no 1607 * packets go out onto the wire for about 5 to 10 seconds 1608 * after the interface is ifconfig'ed for the first time. 1609 */ 1610 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1611 fxp_txeof(sc); 1612 1613 ifp->if_timer = 0; 1614 if (sc->tx_queued == 0) { 1615 if (sc->need_mcsetup) 1616 fxp_mc_setup(sc); 1617 } 1618 /* 1619 * Try to start more packets transmitting. 1620 */ 1621 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1622 fxp_start_body(ifp); 1623 } 1624 1625 /* 1626 * Just return if nothing happened on the receive side. 1627 */ 1628 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1629 return; 1630 1631 /* 1632 * Process receiver interrupts. If a no-resource (RNR) 1633 * condition exists, get whatever packets we can and 1634 * re-start the receiver. 1635 * 1636 * When using polling, we do not process the list to completion, 1637 * so when we get an RNR interrupt we must defer the restart 1638 * until we hit the last buffer with the C bit set. 1639 * If we run out of cycles and rfa_headm has the C bit set, 1640 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1641 * that the info will be used in the subsequent polling cycle. 1642 */ 1643 for (;;) { 1644 rxp = sc->fxp_desc.rx_head; 1645 m = rxp->rx_mbuf; 1646 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1647 RFA_ALIGNMENT_FUDGE); 1648 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1649 BUS_DMASYNC_POSTREAD); 1650 1651#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1652 if (count >= 0 && count-- == 0) { 1653 if (rnr) { 1654 /* Defer RNR processing until the next time. */ 1655 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1656 rnr = 0; 1657 } 1658 break; 1659 } 1660#endif /* DEVICE_POLLING */ 1661 1662 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1663 break; 1664 1665 /* 1666 * Advance head forward. 1667 */ 1668 sc->fxp_desc.rx_head = rxp->rx_next; 1669 1670 /* 1671 * Add a new buffer to the receive chain. 1672 * If this fails, the old buffer is recycled 1673 * instead. 1674 */ 1675 if (fxp_add_rfabuf(sc, rxp) == 0) { 1676 int total_len; 1677 1678 /* 1679 * Fetch packet length (the top 2 bits of 1680 * actual_size are flags set by the controller 1681 * upon completion), and drop the packet in case 1682 * of bogus length or CRC errors. 1683 */ 1684 total_len = le16toh(rfa->actual_size) & 0x3fff; 1685 if (total_len < sizeof(struct ether_header) || 1686 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1687 sc->rfa_size || 1688 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1689 m_freem(m); 1690 continue; 1691 } 1692 1693 /* Do IP checksum checking. */ 1694 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1695 if (rfa->rfax_csum_sts & 1696 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1697 m->m_pkthdr.csum_flags |= 1698 CSUM_IP_CHECKED; 1699 if (rfa->rfax_csum_sts & 1700 FXP_RFDX_CS_IP_CSUM_VALID) 1701 m->m_pkthdr.csum_flags |= 1702 CSUM_IP_VALID; 1703 if ((rfa->rfax_csum_sts & 1704 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1705 (rfa->rfax_csum_sts & 1706 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1707 m->m_pkthdr.csum_flags |= 1708 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1709 m->m_pkthdr.csum_data = 0xffff; 1710 } 1711 } 1712 1713 m->m_pkthdr.len = m->m_len = total_len; 1714 m->m_pkthdr.rcvif = ifp; 1715 1716 /* 1717 * Drop locks before calling if_input() since it 1718 * may re-enter fxp_start() in the netisr case. 1719 * This would result in a lock reversal. Better 1720 * performance might be obtained by chaining all 1721 * packets received, dropping the lock, and then 1722 * calling if_input() on each one. 1723 */ 1724 FXP_UNLOCK(sc); 1725 (*ifp->if_input)(ifp, m); 1726 FXP_LOCK(sc); 1727 } 1728 } 1729 if (rnr) { 1730 fxp_scb_wait(sc); 1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1732 sc->fxp_desc.rx_head->rx_addr); 1733 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1734 } 1735} 1736 1737/* 1738 * Update packet in/out/collision statistics. The i82557 doesn't 1739 * allow you to access these counters without doing a fairly 1740 * expensive DMA to get _all_ of the statistics it maintains, so 1741 * we do this operation here only once per second. The statistics 1742 * counters in the kernel are updated from the previous dump-stats 1743 * DMA and then a new dump-stats DMA is started. The on-chip 1744 * counters are zeroed when the DMA completes. If we can't start 1745 * the DMA immediately, we don't wait - we just prepare to read 1746 * them again next time. 1747 */ 1748static void 1749fxp_tick(void *xsc) 1750{ 1751 struct fxp_softc *sc = xsc; 1752 struct ifnet *ifp = &sc->sc_if; 1753 struct fxp_stats *sp = sc->fxp_stats; 1754 int s; 1755 1756 FXP_LOCK(sc); 1757 s = splimp(); 1758 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1759 ifp->if_opackets += le32toh(sp->tx_good); 1760 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1761 if (sp->rx_good) { 1762 ifp->if_ipackets += le32toh(sp->rx_good); 1763 sc->rx_idle_secs = 0; 1764 } else { 1765 /* 1766 * Receiver's been idle for another second. 1767 */ 1768 sc->rx_idle_secs++; 1769 } 1770 ifp->if_ierrors += 1771 le32toh(sp->rx_crc_errors) + 1772 le32toh(sp->rx_alignment_errors) + 1773 le32toh(sp->rx_rnr_errors) + 1774 le32toh(sp->rx_overrun_errors); 1775 /* 1776 * If any transmit underruns occured, bump up the transmit 1777 * threshold by another 512 bytes (64 * 8). 1778 */ 1779 if (sp->tx_underruns) { 1780 ifp->if_oerrors += le32toh(sp->tx_underruns); 1781 if (tx_threshold < 192) 1782 tx_threshold += 64; 1783 } 1784 1785 /* 1786 * Release any xmit buffers that have completed DMA. This isn't 1787 * strictly necessary to do here, but it's advantagous for mbufs 1788 * with external storage to be released in a timely manner rather 1789 * than being defered for a potentially long time. This limits 1790 * the delay to a maximum of one second. 1791 */ 1792 fxp_txeof(sc); 1793 1794 /* 1795 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1796 * then assume the receiver has locked up and attempt to clear 1797 * the condition by reprogramming the multicast filter. This is 1798 * a work-around for a bug in the 82557 where the receiver locks 1799 * up if it gets certain types of garbage in the syncronization 1800 * bits prior to the packet header. This bug is supposed to only 1801 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1802 * mode as well (perhaps due to a 10/100 speed transition). 1803 */ 1804 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1805 sc->rx_idle_secs = 0; 1806 fxp_mc_setup(sc); 1807 } 1808 /* 1809 * If there is no pending command, start another stats 1810 * dump. Otherwise punt for now. 1811 */ 1812 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1813 /* 1814 * Start another stats dump. 1815 */ 1816 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1817 BUS_DMASYNC_PREREAD); 1818 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1819 } else { 1820 /* 1821 * A previous command is still waiting to be accepted. 1822 * Just zero our copy of the stats and wait for the 1823 * next timer event to update them. 1824 */ 1825 sp->tx_good = 0; 1826 sp->tx_underruns = 0; 1827 sp->tx_total_collisions = 0; 1828 1829 sp->rx_good = 0; 1830 sp->rx_crc_errors = 0; 1831 sp->rx_alignment_errors = 0; 1832 sp->rx_rnr_errors = 0; 1833 sp->rx_overrun_errors = 0; 1834 } 1835 if (sc->miibus != NULL) 1836 mii_tick(device_get_softc(sc->miibus)); 1837 1838 /* 1839 * Schedule another timeout one second from now. 1840 */ 1841 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1842 FXP_UNLOCK(sc); 1843 splx(s); 1844} 1845 1846/* 1847 * Stop the interface. Cancels the statistics updater and resets 1848 * the interface. 1849 */ 1850static void 1851fxp_stop(struct fxp_softc *sc) 1852{ 1853 struct ifnet *ifp = &sc->sc_if; 1854 struct fxp_tx *txp; 1855 int i; 1856 1857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1858 ifp->if_timer = 0; 1859 1860#ifdef DEVICE_POLLING 1861 ether_poll_deregister(ifp); 1862#endif 1863 /* 1864 * Cancel stats updater. 1865 */ 1866 callout_stop(&sc->stat_ch); 1867 1868 /* 1869 * Issue software reset, which also unloads the microcode. 1870 */ 1871 sc->flags &= ~FXP_FLAG_UCODE; 1872 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1873 DELAY(50); 1874 1875 /* 1876 * Release any xmit buffers. 1877 */ 1878 txp = sc->fxp_desc.tx_list; 1879 if (txp != NULL) { 1880 for (i = 0; i < FXP_NTXCB; i++) { 1881 if (txp[i].tx_mbuf != NULL) { 1882 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1883 BUS_DMASYNC_POSTWRITE); 1884 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1885 m_freem(txp[i].tx_mbuf); 1886 txp[i].tx_mbuf = NULL; 1887 /* clear this to reset csum offload bits */ 1888 txp[i].tx_cb->tbd[0].tb_addr = 0; 1889 } 1890 } 1891 } 1892 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1893 sc->tx_queued = 0; 1894} 1895 1896/* 1897 * Watchdog/transmission transmit timeout handler. Called when a 1898 * transmission is started on the interface, but no interrupt is 1899 * received before the timeout. This usually indicates that the 1900 * card has wedged for some reason. 1901 */ 1902static void 1903fxp_watchdog(struct ifnet *ifp) 1904{ 1905 struct fxp_softc *sc = ifp->if_softc; 1906 1907 FXP_LOCK(sc); 1908 device_printf(sc->dev, "device timeout\n"); 1909 ifp->if_oerrors++; 1910 1911 fxp_init_body(sc); 1912 FXP_UNLOCK(sc); 1913} 1914 1915/* 1916 * Acquire locks and then call the real initialization function. This 1917 * is necessary because ether_ioctl() calls if_init() and this would 1918 * result in mutex recursion if the mutex was held. 1919 */ 1920static void 1921fxp_init(void *xsc) 1922{ 1923 struct fxp_softc *sc = xsc; 1924 1925 FXP_LOCK(sc); 1926 fxp_init_body(sc); 1927 FXP_UNLOCK(sc); 1928} 1929 1930/* 1931 * Perform device initialization. This routine must be called with the 1932 * softc lock held. 1933 */ 1934static void 1935fxp_init_body(struct fxp_softc *sc) 1936{ 1937 struct ifnet *ifp = &sc->sc_if; 1938 struct fxp_cb_config *cbp; 1939 struct fxp_cb_ias *cb_ias; 1940 struct fxp_cb_tx *tcbp; 1941 struct fxp_tx *txp; 1942 struct fxp_cb_mcs *mcsp; 1943 int i, prm, s; 1944 1945 FXP_LOCK_ASSERT(sc, MA_OWNED); 1946 s = splimp(); 1947 /* 1948 * Cancel any pending I/O 1949 */ 1950 fxp_stop(sc); 1951 1952 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1953 1954 /* 1955 * Initialize base of CBL and RFA memory. Loading with zero 1956 * sets it up for regular linear addressing. 1957 */ 1958 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1959 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1960 1961 fxp_scb_wait(sc); 1962 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1963 1964 /* 1965 * Initialize base of dump-stats buffer. 1966 */ 1967 fxp_scb_wait(sc); 1968 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1969 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1970 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1971 1972 /* 1973 * Attempt to load microcode if requested. 1974 */ 1975 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1976 fxp_load_ucode(sc); 1977 1978 /* 1979 * Initialize the multicast address list. 1980 */ 1981 if (fxp_mc_addrs(sc)) { 1982 mcsp = sc->mcsp; 1983 mcsp->cb_status = 0; 1984 mcsp->cb_command = 1985 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1986 mcsp->link_addr = 0xffffffff; 1987 /* 1988 * Start the multicast setup command. 1989 */ 1990 fxp_scb_wait(sc); 1991 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1992 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1993 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1994 /* ...and wait for it to complete. */ 1995 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1996 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1997 BUS_DMASYNC_POSTWRITE); 1998 } 1999 2000 /* 2001 * We temporarily use memory that contains the TxCB list to 2002 * construct the config CB. The TxCB list memory is rebuilt 2003 * later. 2004 */ 2005 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2006 2007 /* 2008 * This bcopy is kind of disgusting, but there are a bunch of must be 2009 * zero and must be one bits in this structure and this is the easiest 2010 * way to initialize them all to proper values. 2011 */ 2012 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2013 2014 cbp->cb_status = 0; 2015 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2016 FXP_CB_COMMAND_EL); 2017 cbp->link_addr = 0xffffffff; /* (no) next command */ 2018 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2019 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2020 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2021 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2022 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2023 cbp->type_enable = 0; /* actually reserved */ 2024 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2025 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2026 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2027 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2028 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2029 cbp->late_scb = 0; /* (don't) defer SCB update */ 2030 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2031 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2032 cbp->ci_int = 1; /* interrupt on CU idle */ 2033 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2034 cbp->ext_stats_dis = 1; /* disable extended counters */ 2035 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2036 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2037 cbp->disc_short_rx = !prm; /* discard short packets */ 2038 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2039 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2040 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2041 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2042 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2043 cbp->csma_dis = 0; /* (don't) disable link */ 2044 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2045 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2046 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2047 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2048 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2049 cbp->nsai = 1; /* (don't) disable source addr insert */ 2050 cbp->preamble_length = 2; /* (7 byte) preamble */ 2051 cbp->loopback = 0; /* (don't) loopback */ 2052 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2053 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2054 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2055 cbp->promiscuous = prm; /* promiscuous mode */ 2056 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2057 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2058 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2059 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2060 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2061 2062 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2063 cbp->padding = 1; /* (do) pad short tx packets */ 2064 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2065 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2066 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2067 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2068 /* must set wake_en in PMCSR also */ 2069 cbp->force_fdx = 0; /* (don't) force full duplex */ 2070 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2071 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2072 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2073 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2074 2075 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2076 /* 2077 * The 82557 has no hardware flow control, the values 2078 * below are the defaults for the chip. 2079 */ 2080 cbp->fc_delay_lsb = 0; 2081 cbp->fc_delay_msb = 0x40; 2082 cbp->pri_fc_thresh = 3; 2083 cbp->tx_fc_dis = 0; 2084 cbp->rx_fc_restop = 0; 2085 cbp->rx_fc_restart = 0; 2086 cbp->fc_filter = 0; 2087 cbp->pri_fc_loc = 1; 2088 } else { 2089 cbp->fc_delay_lsb = 0x1f; 2090 cbp->fc_delay_msb = 0x01; 2091 cbp->pri_fc_thresh = 3; 2092 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2093 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2094 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2095 cbp->fc_filter = !prm; /* drop FC frames to host */ 2096 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2097 } 2098 2099 /* 2100 * Start the config command/DMA. 2101 */ 2102 fxp_scb_wait(sc); 2103 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2104 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2105 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2106 /* ...and wait for it to complete. */ 2107 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2108 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2109 2110 /* 2111 * Now initialize the station address. Temporarily use the TxCB 2112 * memory area like we did above for the config CB. 2113 */ 2114 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2115 cb_ias->cb_status = 0; 2116 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2117 cb_ias->link_addr = 0xffffffff; 2118 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2119 sizeof(sc->arpcom.ac_enaddr)); 2120 2121 /* 2122 * Start the IAS (Individual Address Setup) command/DMA. 2123 */ 2124 fxp_scb_wait(sc); 2125 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2127 /* ...and wait for it to complete. */ 2128 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2129 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2130 2131 /* 2132 * Initialize transmit control block (TxCB) list. 2133 */ 2134 txp = sc->fxp_desc.tx_list; 2135 tcbp = sc->fxp_desc.cbl_list; 2136 bzero(tcbp, FXP_TXCB_SZ); 2137 for (i = 0; i < FXP_NTXCB; i++) { 2138 txp[i].tx_mbuf = NULL; 2139 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2140 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2141 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2142 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2143 if (sc->flags & FXP_FLAG_EXT_TXCB) 2144 tcbp[i].tbd_array_addr = 2145 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2146 else 2147 tcbp[i].tbd_array_addr = 2148 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2149 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2150 } 2151 /* 2152 * Set the suspend flag on the first TxCB and start the control 2153 * unit. It will execute the NOP and then suspend. 2154 */ 2155 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2156 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2157 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2158 sc->tx_queued = 1; 2159 2160 fxp_scb_wait(sc); 2161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2162 2163 /* 2164 * Initialize receiver buffer area - RFA. 2165 */ 2166 fxp_scb_wait(sc); 2167 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2168 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2169 2170 /* 2171 * Set current media. 2172 */ 2173 if (sc->miibus != NULL) 2174 mii_mediachg(device_get_softc(sc->miibus)); 2175 2176 ifp->if_flags |= IFF_RUNNING; 2177 ifp->if_flags &= ~IFF_OACTIVE; 2178 2179 /* 2180 * Enable interrupts. 2181 */ 2182#ifdef DEVICE_POLLING 2183 /* 2184 * ... but only do that if we are not polling. And because (presumably) 2185 * the default is interrupts on, we need to disable them explicitly! 2186 */ 2187 if ( ifp->if_flags & IFF_POLLING ) 2188 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2189 else 2190#endif /* DEVICE_POLLING */ 2191 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2192 2193 /* 2194 * Start stats updater. 2195 */ 2196 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2197 splx(s); 2198} 2199 2200static int 2201fxp_serial_ifmedia_upd(struct ifnet *ifp) 2202{ 2203 2204 return (0); 2205} 2206 2207static void 2208fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2209{ 2210 2211 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2212} 2213 2214/* 2215 * Change media according to request. 2216 */ 2217static int 2218fxp_ifmedia_upd(struct ifnet *ifp) 2219{ 2220 struct fxp_softc *sc = ifp->if_softc; 2221 struct mii_data *mii; 2222 2223 mii = device_get_softc(sc->miibus); 2224 mii_mediachg(mii); 2225 return (0); 2226} 2227 2228/* 2229 * Notify the world which media we're using. 2230 */ 2231static void 2232fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2233{ 2234 struct fxp_softc *sc = ifp->if_softc; 2235 struct mii_data *mii; 2236 2237 mii = device_get_softc(sc->miibus); 2238 mii_pollstat(mii); 2239 ifmr->ifm_active = mii->mii_media_active; 2240 ifmr->ifm_status = mii->mii_media_status; 2241 2242 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2243 sc->cu_resume_bug = 1; 2244 else 2245 sc->cu_resume_bug = 0; 2246} 2247 2248/* 2249 * Add a buffer to the end of the RFA buffer list. 2250 * Return 0 if successful, 1 for failure. A failure results in 2251 * adding the 'oldm' (if non-NULL) on to the end of the list - 2252 * tossing out its old contents and recycling it. 2253 * The RFA struct is stuck at the beginning of mbuf cluster and the 2254 * data pointer is fixed up to point just past it. 2255 */ 2256static int 2257fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2258{ 2259 struct mbuf *m; 2260 struct fxp_rfa *rfa, *p_rfa; 2261 struct fxp_rx *p_rx; 2262 bus_dmamap_t tmp_map; 2263 int error; 2264 2265 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2266 if (m == NULL) 2267 return (ENOBUFS); 2268 2269 /* 2270 * Move the data pointer up so that the incoming data packet 2271 * will be 32-bit aligned. 2272 */ 2273 m->m_data += RFA_ALIGNMENT_FUDGE; 2274 2275 /* 2276 * Get a pointer to the base of the mbuf cluster and move 2277 * data start past it. 2278 */ 2279 rfa = mtod(m, struct fxp_rfa *); 2280 m->m_data += sc->rfa_size; 2281 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2282 2283 rfa->rfa_status = 0; 2284 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2285 rfa->actual_size = 0; 2286 2287 /* 2288 * Initialize the rest of the RFA. Note that since the RFA 2289 * is misaligned, we cannot store values directly. We're thus 2290 * using the le32enc() function which handles endianness and 2291 * is also alignment-safe. 2292 */ 2293 le32enc(&rfa->link_addr, 0xffffffff); 2294 le32enc(&rfa->rbd_addr, 0xffffffff); 2295 2296 /* Map the RFA into DMA memory. */ 2297 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2298 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2299 &rxp->rx_addr, 0); 2300 if (error) { 2301 m_freem(m); 2302 return (error); 2303 } 2304 2305 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2306 tmp_map = sc->spare_map; 2307 sc->spare_map = rxp->rx_map; 2308 rxp->rx_map = tmp_map; 2309 rxp->rx_mbuf = m; 2310 2311 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2312 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2313 2314 /* 2315 * If there are other buffers already on the list, attach this 2316 * one to the end by fixing up the tail to point to this one. 2317 */ 2318 if (sc->fxp_desc.rx_head != NULL) { 2319 p_rx = sc->fxp_desc.rx_tail; 2320 p_rfa = (struct fxp_rfa *) 2321 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2322 p_rx->rx_next = rxp; 2323 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2324 p_rfa->rfa_control = 0; 2325 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2326 BUS_DMASYNC_PREWRITE); 2327 } else { 2328 rxp->rx_next = NULL; 2329 sc->fxp_desc.rx_head = rxp; 2330 } 2331 sc->fxp_desc.rx_tail = rxp; 2332 return (0); 2333} 2334 2335static volatile int 2336fxp_miibus_readreg(device_t dev, int phy, int reg) 2337{ 2338 struct fxp_softc *sc = device_get_softc(dev); 2339 int count = 10000; 2340 int value; 2341 2342 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2343 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2344 2345 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2346 && count--) 2347 DELAY(10); 2348 2349 if (count <= 0) 2350 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2351 2352 return (value & 0xffff); 2353} 2354 2355static void 2356fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2357{ 2358 struct fxp_softc *sc = device_get_softc(dev); 2359 int count = 10000; 2360 2361 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2362 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2363 (value & 0xffff)); 2364 2365 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2366 count--) 2367 DELAY(10); 2368 2369 if (count <= 0) 2370 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2371} 2372 2373static int 2374fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2375{ 2376 struct fxp_softc *sc = ifp->if_softc; 2377 struct ifreq *ifr = (struct ifreq *)data; 2378 struct mii_data *mii; 2379 int flag, mask, s, error = 0; 2380 2381 /* 2382 * Detaching causes us to call ioctl with the mutex owned. Preclude 2383 * that by saying we're busy if the lock is already held. 2384 */ 2385 if (FXP_LOCKED(sc)) 2386 return (EBUSY); 2387 2388 FXP_LOCK(sc); 2389 s = splimp(); 2390 2391 switch (command) { 2392 case SIOCSIFFLAGS: 2393 if (ifp->if_flags & IFF_ALLMULTI) 2394 sc->flags |= FXP_FLAG_ALL_MCAST; 2395 else 2396 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2397 2398 /* 2399 * If interface is marked up and not running, then start it. 2400 * If it is marked down and running, stop it. 2401 * XXX If it's up then re-initialize it. This is so flags 2402 * such as IFF_PROMISC are handled. 2403 */ 2404 if (ifp->if_flags & IFF_UP) { 2405 fxp_init_body(sc); 2406 } else { 2407 if (ifp->if_flags & IFF_RUNNING) 2408 fxp_stop(sc); 2409 } 2410 break; 2411 2412 case SIOCADDMULTI: 2413 case SIOCDELMULTI: 2414 if (ifp->if_flags & IFF_ALLMULTI) 2415 sc->flags |= FXP_FLAG_ALL_MCAST; 2416 else 2417 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2418 /* 2419 * Multicast list has changed; set the hardware filter 2420 * accordingly. 2421 */ 2422 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2423 fxp_mc_setup(sc); 2424 /* 2425 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2426 * again rather than else {}. 2427 */ 2428 if (sc->flags & FXP_FLAG_ALL_MCAST) 2429 fxp_init_body(sc); 2430 error = 0; 2431 break; 2432 2433 case SIOCSIFMEDIA: 2434 case SIOCGIFMEDIA: 2435 if (sc->miibus != NULL) { 2436 mii = device_get_softc(sc->miibus); 2437 error = ifmedia_ioctl(ifp, ifr, 2438 &mii->mii_media, command); 2439 } else { 2440 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2441 } 2442 break; 2443 2444 case SIOCSIFCAP: 2445 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2446 if (mask & IFCAP_POLLING) 2447 ifp->if_capenable ^= IFCAP_POLLING; 2448 if (mask & IFCAP_VLAN_MTU) { 2449 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2450 if (sc->revision != FXP_REV_82557) 2451 flag = FXP_FLAG_LONG_PKT_EN; 2452 else /* a hack to get long frames on the old chip */ 2453 flag = FXP_FLAG_SAVE_BAD; 2454 sc->flags ^= flag; 2455 if (ifp->if_flags & IFF_UP) 2456 fxp_init_body(sc); 2457 } 2458 break; 2459 2460 default: 2461 /* 2462 * ether_ioctl() will eventually call fxp_start() which 2463 * will result in mutex recursion so drop it first. 2464 */ 2465 FXP_UNLOCK(sc); 2466 error = ether_ioctl(ifp, command, data); 2467 } 2468 if (FXP_LOCKED(sc)) 2469 FXP_UNLOCK(sc); 2470 splx(s); 2471 return (error); 2472} 2473 2474/* 2475 * Fill in the multicast address list and return number of entries. 2476 */ 2477static int 2478fxp_mc_addrs(struct fxp_softc *sc) 2479{ 2480 struct fxp_cb_mcs *mcsp = sc->mcsp; 2481 struct ifnet *ifp = &sc->sc_if; 2482 struct ifmultiaddr *ifma; 2483 int nmcasts; 2484 2485 nmcasts = 0; 2486 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2487#if __FreeBSD_version < 500000 2488 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2489#else 2490 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2491#endif 2492 if (ifma->ifma_addr->sa_family != AF_LINK) 2493 continue; 2494 if (nmcasts >= MAXMCADDR) { 2495 sc->flags |= FXP_FLAG_ALL_MCAST; 2496 nmcasts = 0; 2497 break; 2498 } 2499 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2500 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2501 nmcasts++; 2502 } 2503 } 2504 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2505 return (nmcasts); 2506} 2507 2508/* 2509 * Program the multicast filter. 2510 * 2511 * We have an artificial restriction that the multicast setup command 2512 * must be the first command in the chain, so we take steps to ensure 2513 * this. By requiring this, it allows us to keep up the performance of 2514 * the pre-initialized command ring (esp. link pointers) by not actually 2515 * inserting the mcsetup command in the ring - i.e. its link pointer 2516 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2517 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2518 * lead into the regular TxCB ring when it completes. 2519 * 2520 * This function must be called at splimp. 2521 */ 2522static void 2523fxp_mc_setup(struct fxp_softc *sc) 2524{ 2525 struct fxp_cb_mcs *mcsp = sc->mcsp; 2526 struct ifnet *ifp = &sc->sc_if; 2527 struct fxp_tx *txp; 2528 int count; 2529 2530 FXP_LOCK_ASSERT(sc, MA_OWNED); 2531 /* 2532 * If there are queued commands, we must wait until they are all 2533 * completed. If we are already waiting, then add a NOP command 2534 * with interrupt option so that we're notified when all commands 2535 * have been completed - fxp_start() ensures that no additional 2536 * TX commands will be added when need_mcsetup is true. 2537 */ 2538 if (sc->tx_queued) { 2539 /* 2540 * need_mcsetup will be true if we are already waiting for the 2541 * NOP command to be completed (see below). In this case, bail. 2542 */ 2543 if (sc->need_mcsetup) 2544 return; 2545 sc->need_mcsetup = 1; 2546 2547 /* 2548 * Add a NOP command with interrupt so that we are notified 2549 * when all TX commands have been processed. 2550 */ 2551 txp = sc->fxp_desc.tx_last->tx_next; 2552 txp->tx_mbuf = NULL; 2553 txp->tx_cb->cb_status = 0; 2554 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2555 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2556 /* 2557 * Advance the end of list forward. 2558 */ 2559 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2560 htole16(~FXP_CB_COMMAND_S); 2561 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2562 sc->fxp_desc.tx_last = txp; 2563 sc->tx_queued++; 2564 /* 2565 * Issue a resume in case the CU has just suspended. 2566 */ 2567 fxp_scb_wait(sc); 2568 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2569 /* 2570 * Set a 5 second timer just in case we don't hear from the 2571 * card again. 2572 */ 2573 ifp->if_timer = 5; 2574 2575 return; 2576 } 2577 sc->need_mcsetup = 0; 2578 2579 /* 2580 * Initialize multicast setup descriptor. 2581 */ 2582 mcsp->cb_status = 0; 2583 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2584 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2585 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2586 txp = &sc->fxp_desc.mcs_tx; 2587 txp->tx_mbuf = NULL; 2588 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2589 txp->tx_next = sc->fxp_desc.tx_list; 2590 (void) fxp_mc_addrs(sc); 2591 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2592 sc->tx_queued = 1; 2593 2594 /* 2595 * Wait until command unit is not active. This should never 2596 * be the case when nothing is queued, but make sure anyway. 2597 */ 2598 count = 100; 2599 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2600 FXP_SCB_CUS_ACTIVE && --count) 2601 DELAY(10); 2602 if (count == 0) { 2603 device_printf(sc->dev, "command queue timeout\n"); 2604 return; 2605 } 2606 2607 /* 2608 * Start the multicast setup command. 2609 */ 2610 fxp_scb_wait(sc); 2611 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2612 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2613 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2614 2615 ifp->if_timer = 2; 2616 return; 2617} 2618 2619static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2620static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2621static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2622static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2623static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2624static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2625static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2626 2627#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2628 2629struct ucode { 2630 uint32_t revision; 2631 uint32_t *ucode; 2632 int length; 2633 u_short int_delay_offset; 2634 u_short bundle_max_offset; 2635} ucode_table[] = { 2636 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2637 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2638 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2639 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2641 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2643 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2644 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2645 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2646 { FXP_REV_82551, UCODE(fxp_ucode_d102e), 2647 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2648 { 0, NULL, 0, 0, 0 } 2649}; 2650 2651static void 2652fxp_load_ucode(struct fxp_softc *sc) 2653{ 2654 struct ucode *uc; 2655 struct fxp_cb_ucode *cbp; 2656 int i; 2657 2658 for (uc = ucode_table; uc->ucode != NULL; uc++) 2659 if (sc->revision == uc->revision) 2660 break; 2661 if (uc->ucode == NULL) 2662 return; 2663 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2664 cbp->cb_status = 0; 2665 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2666 cbp->link_addr = 0xffffffff; /* (no) next command */ 2667 for (i = 0; i < uc->length; i++) 2668 cbp->ucode[i] = htole32(uc->ucode[i]); 2669 if (uc->int_delay_offset) 2670 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2671 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2672 if (uc->bundle_max_offset) 2673 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2674 htole16(sc->tunable_bundle_max); 2675 /* 2676 * Download the ucode to the chip. 2677 */ 2678 fxp_scb_wait(sc); 2679 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2680 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2681 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2682 /* ...and wait for it to complete. */ 2683 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2684 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2685 device_printf(sc->dev, 2686 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2687 sc->tunable_int_delay, 2688 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2689 sc->flags |= FXP_FLAG_UCODE; 2690} 2691 2692static int 2693sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2694{ 2695 int error, value; 2696 2697 value = *(int *)arg1; 2698 error = sysctl_handle_int(oidp, &value, 0, req); 2699 if (error || !req->newptr) 2700 return (error); 2701 if (value < low || value > high) 2702 return (EINVAL); 2703 *(int *)arg1 = value; 2704 return (0); 2705} 2706 2707/* 2708 * Interrupt delay is expressed in microseconds, a multiplier is used 2709 * to convert this to the appropriate clock ticks before using. 2710 */ 2711static int 2712sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2713{ 2714 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2715} 2716 2717static int 2718sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2719{ 2720 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2721} 2722