if_fxp.c revision 143705
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 143705 2005-03-16 16:39:04Z mux $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194}; 195 196#ifdef FXP_IP_CSUM_WAR 197#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198#else 199#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200#endif 201 202static int fxp_probe(device_t dev); 203static int fxp_attach(device_t dev); 204static int fxp_detach(device_t dev); 205static int fxp_shutdown(device_t dev); 206static int fxp_suspend(device_t dev); 207static int fxp_resume(device_t dev); 208 209static void fxp_intr(void *xsc); 210static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212static void fxp_init(void *xsc); 213static void fxp_init_body(struct fxp_softc *sc); 214static void fxp_tick(void *xsc); 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218static void fxp_stop(struct fxp_softc *sc); 219static void fxp_release(struct fxp_softc *sc); 220static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222static void fxp_watchdog(struct ifnet *ifp); 223static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225static int fxp_mc_addrs(struct fxp_softc *sc); 226static void fxp_mc_setup(struct fxp_softc *sc); 227static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231static void fxp_autosize_eeprom(struct fxp_softc *sc); 232static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236static int fxp_ifmedia_upd(struct ifnet *ifp); 237static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245static void fxp_load_ucode(struct fxp_softc *sc); 246static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250static void fxp_scb_wait(struct fxp_softc *sc); 251static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270}; 271 272static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276}; 277 278static devclass_t fxp_devclass; 279 280DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284/* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288static void 289fxp_scb_wait(struct fxp_softc *sc) 290{ 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301} 302 303static void 304fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305{ 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312} 313 314static void 315fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317{ 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327} 328 329/* 330 * Return identification string if this device is ours. 331 */ 332static int 333fxp_probe(device_t dev) 334{ 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351} 352 353static void 354fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355{ 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 int i, rid, m1, m2, prefer_iomap; 377 int error, s; 378 379 error = 0; 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 383 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 384 MTX_DEF); 385 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 386 fxp_serial_ifmedia_sts); 387 388 s = splimp(); 389 390 /* 391 * Enable bus mastering. 392 */ 393 pci_enable_busmaster(dev); 394 val = pci_read_config(dev, PCIR_COMMAND, 2); 395 396 /* 397 * Figure out which we should try first - memory mapping or i/o mapping? 398 * We default to memory mapping. Then we accept an override from the 399 * command line. Then we check to see which one is enabled. 400 */ 401 m1 = PCIM_CMD_MEMEN; 402 m2 = PCIM_CMD_PORTEN; 403 prefer_iomap = 0; 404 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 405 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 406 m1 = PCIM_CMD_PORTEN; 407 m2 = PCIM_CMD_MEMEN; 408 } 409 410 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 411 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 412 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 413 if (sc->mem == NULL) { 414 sc->rtp = 415 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 416 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 417 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 418 RF_ACTIVE); 419 } 420 421 if (!sc->mem) { 422 error = ENXIO; 423 goto fail; 424 } 425 if (bootverbose) { 426 device_printf(dev, "using %s space register mapping\n", 427 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 428 } 429 430 sc->sc_st = rman_get_bustag(sc->mem); 431 sc->sc_sh = rman_get_bushandle(sc->mem); 432 433 /* 434 * Allocate our interrupt. 435 */ 436 rid = 0; 437 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 438 RF_SHAREABLE | RF_ACTIVE); 439 if (sc->irq == NULL) { 440 device_printf(dev, "could not map interrupt\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 445 /* 446 * Reset to a stable state. 447 */ 448 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 449 DELAY(10); 450 451 /* 452 * Find out how large of an SEEPROM we have. 453 */ 454 fxp_autosize_eeprom(sc); 455 456 /* 457 * Find out the chip revision; lump all 82557 revs together. 458 */ 459 fxp_read_eeprom(sc, &data, 5, 1); 460 if ((data >> 8) == 1) 461 sc->revision = FXP_REV_82557; 462 else 463 sc->revision = pci_get_revid(dev); 464 465 /* 466 * Determine whether we must use the 503 serial interface. 467 */ 468 fxp_read_eeprom(sc, &data, 6, 1); 469 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 470 && (data & FXP_PHY_SERIAL_ONLY)) 471 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 472 473 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 475 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 476 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 477 "FXP driver receive interrupt microcode bundling delay"); 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 480 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 481 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 482 "FXP driver receive interrupt microcode bundle size limit"); 483 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 486 "FXP RNR events"); 487 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 490 "FXP flow control disabled"); 491 492 /* 493 * Pull in device tunables. 494 */ 495 sc->tunable_int_delay = TUNABLE_INT_DELAY; 496 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 497 sc->tunable_noflow = 1; 498 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 499 "int_delay", &sc->tunable_int_delay); 500 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 501 "bundle_max", &sc->tunable_bundle_max); 502 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 503 "noflow", &sc->tunable_noflow); 504 sc->rnr = 0; 505 506 /* 507 * Enable workarounds for certain chip revision deficiencies. 508 * 509 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 510 * some systems based a normal 82559 design, have a defect where 511 * the chip can cause a PCI protocol violation if it receives 512 * a CU_RESUME command when it is entering the IDLE state. The 513 * workaround is to disable Dynamic Standby Mode, so the chip never 514 * deasserts CLKRUN#, and always remains in an active state. 515 * 516 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 517 */ 518 i = pci_get_device(dev); 519 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 520 sc->revision >= FXP_REV_82559_A0) { 521 fxp_read_eeprom(sc, &data, 10, 1); 522 if (data & 0x02) { /* STB enable */ 523 uint16_t cksum; 524 int i; 525 526 device_printf(dev, 527 "Disabling dynamic standby mode in EEPROM\n"); 528 data &= ~0x02; 529 fxp_write_eeprom(sc, &data, 10, 1); 530 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 531 cksum = 0; 532 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 533 fxp_read_eeprom(sc, &data, i, 1); 534 cksum += data; 535 } 536 i = (1 << sc->eeprom_size) - 1; 537 cksum = 0xBABA - cksum; 538 fxp_read_eeprom(sc, &data, i, 1); 539 fxp_write_eeprom(sc, &cksum, i, 1); 540 device_printf(dev, 541 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 542 i, data, cksum); 543#if 1 544 /* 545 * If the user elects to continue, try the software 546 * workaround, as it is better than nothing. 547 */ 548 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 549#endif 550 } 551 } 552 553 /* 554 * If we are not a 82557 chip, we can enable extended features. 555 */ 556 if (sc->revision != FXP_REV_82557) { 557 /* 558 * If MWI is enabled in the PCI configuration, and there 559 * is a valid cacheline size (8 or 16 dwords), then tell 560 * the board to turn on MWI. 561 */ 562 if (val & PCIM_CMD_MWRICEN && 563 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 564 sc->flags |= FXP_FLAG_MWI_ENABLE; 565 566 /* turn on the extended TxCB feature */ 567 sc->flags |= FXP_FLAG_EXT_TXCB; 568 569 /* enable reception of long frames for VLAN */ 570 sc->flags |= FXP_FLAG_LONG_PKT_EN; 571 } else { 572 /* a hack to get long VLAN frames on a 82557 */ 573 sc->flags |= FXP_FLAG_SAVE_BAD; 574 } 575 576 /* 577 * Enable use of extended RFDs and TCBs for 82550 578 * and later chips. Note: we need extended TXCB support 579 * too, but that's already enabled by the code above. 580 * Be careful to do this only on the right devices. 581 */ 582 583 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 584 sc->rfa_size = sizeof (struct fxp_rfa); 585 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 586 sc->flags |= FXP_FLAG_EXT_RFA; 587 } else { 588 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 589 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 590 } 591 592 /* 593 * Allocate DMA tags and DMA safe memory. 594 */ 595 sc->maxtxseg = FXP_NTXSEG; 596 if (sc->flags & FXP_FLAG_EXT_RFA) 597 sc->maxtxseg--; 598 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 599 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 600 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 601 &sc->fxp_mtag); 602 if (error) { 603 device_printf(dev, "could not allocate dma tag\n"); 604 goto fail; 605 } 606 607 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 608 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 609 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 610 &sc->fxp_stag); 611 if (error) { 612 device_printf(dev, "could not allocate dma tag\n"); 613 goto fail; 614 } 615 616 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 617 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 618 if (error) 619 goto fail; 620 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 621 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 622 if (error) { 623 device_printf(dev, "could not map the stats buffer\n"); 624 goto fail; 625 } 626 627 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 628 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 629 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 630 if (error) { 631 device_printf(dev, "could not allocate dma tag\n"); 632 goto fail; 633 } 634 635 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 636 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 637 if (error) 638 goto fail; 639 640 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 641 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 642 &sc->fxp_desc.cbl_addr, 0); 643 if (error) { 644 device_printf(dev, "could not map DMA memory\n"); 645 goto fail; 646 } 647 648 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 649 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 650 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 651 &sc->mcs_tag); 652 if (error) { 653 device_printf(dev, "could not allocate dma tag\n"); 654 goto fail; 655 } 656 657 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 658 BUS_DMA_NOWAIT, &sc->mcs_map); 659 if (error) 660 goto fail; 661 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 662 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 663 if (error) { 664 device_printf(dev, "can't map the multicast setup command\n"); 665 goto fail; 666 } 667 668 /* 669 * Pre-allocate the TX DMA maps and setup the pointers to 670 * the TX command blocks. 671 */ 672 txp = sc->fxp_desc.tx_list; 673 tcbp = sc->fxp_desc.cbl_list; 674 for (i = 0; i < FXP_NTXCB; i++) { 675 txp[i].tx_cb = tcbp + i; 676 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 677 if (error) { 678 device_printf(dev, "can't create DMA map for TX\n"); 679 goto fail; 680 } 681 } 682 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 683 if (error) { 684 device_printf(dev, "can't create spare DMA map\n"); 685 goto fail; 686 } 687 688 /* 689 * Pre-allocate our receive buffers. 690 */ 691 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 692 for (i = 0; i < FXP_NRFABUFS; i++) { 693 rxp = &sc->fxp_desc.rx_list[i]; 694 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 695 if (error) { 696 device_printf(dev, "can't create DMA map for RX\n"); 697 goto fail; 698 } 699 if (fxp_add_rfabuf(sc, rxp) != 0) { 700 error = ENOMEM; 701 goto fail; 702 } 703 } 704 705 /* 706 * Read MAC address. 707 */ 708 fxp_read_eeprom(sc, myea, 0, 3); 709 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 710 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 711 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 712 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 713 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 714 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 715 if (bootverbose) { 716 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 717 pci_get_vendor(dev), pci_get_device(dev), 718 pci_get_subvendor(dev), pci_get_subdevice(dev), 719 pci_get_revid(dev)); 720 fxp_read_eeprom(sc, &data, 10, 1); 721 device_printf(dev, "Dynamic Standby mode is %s\n", 722 data & 0x02 ? "enabled" : "disabled"); 723 } 724 725 /* 726 * If this is only a 10Mbps device, then there is no MII, and 727 * the PHY will use a serial interface instead. 728 * 729 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 730 * doesn't have a programming interface of any sort. The 731 * media is sensed automatically based on how the link partner 732 * is configured. This is, in essence, manual configuration. 733 */ 734 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 735 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 736 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 737 } else { 738 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 739 fxp_ifmedia_sts)) { 740 device_printf(dev, "MII without any PHY!\n"); 741 error = ENXIO; 742 goto fail; 743 } 744 } 745 746 ifp = &sc->arpcom.ac_if; 747 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 748 ifp->if_baudrate = 100000000; 749 ifp->if_init = fxp_init; 750 ifp->if_softc = sc; 751 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 752 ifp->if_ioctl = fxp_ioctl; 753 ifp->if_start = fxp_start; 754 ifp->if_watchdog = fxp_watchdog; 755 756 ifp->if_capabilities = ifp->if_capenable = 0; 757 758 /* Enable checksum offload for 82550 or better chips */ 759 if (sc->flags & FXP_FLAG_EXT_RFA) { 760 ifp->if_hwassist = FXP_CSUM_FEATURES; 761 ifp->if_capabilities |= IFCAP_HWCSUM; 762 ifp->if_capenable |= IFCAP_HWCSUM; 763 } 764 765#ifdef DEVICE_POLLING 766 /* Inform the world we support polling. */ 767 ifp->if_capabilities |= IFCAP_POLLING; 768 ifp->if_capenable |= IFCAP_POLLING; 769#endif 770 771 /* 772 * Attach the interface. 773 */ 774 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 775 776 /* 777 * Tell the upper layer(s) we support long frames. 778 * Must appear after the call to ether_ifattach() because 779 * ether_ifattach() sets ifi_hdrlen to the default value. 780 */ 781 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 782 ifp->if_capabilities |= IFCAP_VLAN_MTU; 783 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 784 785 /* 786 * Let the system queue as many packets as we have available 787 * TX descriptors. 788 */ 789 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 790 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 791 IFQ_SET_READY(&ifp->if_snd); 792 793 /* 794 * Hook our interrupt after all initialization is complete. 795 */ 796 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 797 fxp_intr, sc, &sc->ih); 798 if (error) { 799 device_printf(dev, "could not setup irq\n"); 800 ether_ifdetach(&sc->arpcom.ac_if); 801 goto fail; 802 } 803 804fail: 805 splx(s); 806 if (error) 807 fxp_release(sc); 808 return (error); 809} 810 811/* 812 * Release all resources. The softc lock should not be held and the 813 * interrupt should already be torn down. 814 */ 815static void 816fxp_release(struct fxp_softc *sc) 817{ 818 struct fxp_rx *rxp; 819 struct fxp_tx *txp; 820 int i; 821 822 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 823 KASSERT(sc->ih == NULL, 824 ("fxp_release() called with intr handle still active")); 825 if (sc->miibus) 826 device_delete_child(sc->dev, sc->miibus); 827 bus_generic_detach(sc->dev); 828 ifmedia_removeall(&sc->sc_media); 829 if (sc->fxp_desc.cbl_list) { 830 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 831 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 832 sc->cbl_map); 833 } 834 if (sc->fxp_stats) { 835 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 836 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 837 } 838 if (sc->mcsp) { 839 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 840 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 841 } 842 if (sc->irq) 843 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 844 if (sc->mem) 845 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 846 if (sc->fxp_mtag) { 847 for (i = 0; i < FXP_NRFABUFS; i++) { 848 rxp = &sc->fxp_desc.rx_list[i]; 849 if (rxp->rx_mbuf != NULL) { 850 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 851 BUS_DMASYNC_POSTREAD); 852 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 853 m_freem(rxp->rx_mbuf); 854 } 855 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 856 } 857 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 858 for (i = 0; i < FXP_NTXCB; i++) { 859 txp = &sc->fxp_desc.tx_list[i]; 860 if (txp->tx_mbuf != NULL) { 861 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 862 BUS_DMASYNC_POSTWRITE); 863 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 864 m_freem(txp->tx_mbuf); 865 } 866 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 867 } 868 bus_dma_tag_destroy(sc->fxp_mtag); 869 } 870 if (sc->fxp_stag) 871 bus_dma_tag_destroy(sc->fxp_stag); 872 if (sc->cbl_tag) 873 bus_dma_tag_destroy(sc->cbl_tag); 874 if (sc->mcs_tag) 875 bus_dma_tag_destroy(sc->mcs_tag); 876 877 mtx_destroy(&sc->sc_mtx); 878} 879 880/* 881 * Detach interface. 882 */ 883static int 884fxp_detach(device_t dev) 885{ 886 struct fxp_softc *sc = device_get_softc(dev); 887 int s; 888 889 FXP_LOCK(sc); 890 s = splimp(); 891 892 sc->suspended = 1; /* Do same thing as we do for suspend */ 893 /* 894 * Close down routes etc. 895 */ 896 ether_ifdetach(&sc->arpcom.ac_if); 897 898 /* 899 * Stop DMA and drop transmit queue, but disable interrupts first. 900 */ 901 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 902 fxp_stop(sc); 903 FXP_UNLOCK(sc); 904 905 /* 906 * Unhook interrupt before dropping lock. This is to prevent 907 * races with fxp_intr(). 908 */ 909 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 910 sc->ih = NULL; 911 912 splx(s); 913 914 /* Release our allocated resources. */ 915 fxp_release(sc); 916 return (0); 917} 918 919/* 920 * Device shutdown routine. Called at system shutdown after sync. The 921 * main purpose of this routine is to shut off receiver DMA so that 922 * kernel memory doesn't get clobbered during warmboot. 923 */ 924static int 925fxp_shutdown(device_t dev) 926{ 927 /* 928 * Make sure that DMA is disabled prior to reboot. Not doing 929 * do could allow DMA to corrupt kernel memory during the 930 * reboot before the driver initializes. 931 */ 932 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 933 return (0); 934} 935 936/* 937 * Device suspend routine. Stop the interface and save some PCI 938 * settings in case the BIOS doesn't restore them properly on 939 * resume. 940 */ 941static int 942fxp_suspend(device_t dev) 943{ 944 struct fxp_softc *sc = device_get_softc(dev); 945 int i, s; 946 947 FXP_LOCK(sc); 948 s = splimp(); 949 950 fxp_stop(sc); 951 952 for (i = 0; i < 5; i++) 953 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 954 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 955 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 956 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 957 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 958 959 sc->suspended = 1; 960 961 FXP_UNLOCK(sc); 962 splx(s); 963 return (0); 964} 965 966/* 967 * Device resume routine. Restore some PCI settings in case the BIOS 968 * doesn't, re-enable busmastering, and restart the interface if 969 * appropriate. 970 */ 971static int 972fxp_resume(device_t dev) 973{ 974 struct fxp_softc *sc = device_get_softc(dev); 975 struct ifnet *ifp = &sc->sc_if; 976 uint16_t pci_command; 977 int i, s; 978 979 FXP_LOCK(sc); 980 s = splimp(); 981 982 /* better way to do this? */ 983 for (i = 0; i < 5; i++) 984 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 985 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 986 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 987 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 988 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 989 990 /* reenable busmastering */ 991 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 992 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 993 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 994 995 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 996 DELAY(10); 997 998 /* reinitialize interface if necessary */ 999 if (ifp->if_flags & IFF_UP) 1000 fxp_init_body(sc); 1001 1002 sc->suspended = 0; 1003 1004 FXP_UNLOCK(sc); 1005 splx(s); 1006 return (0); 1007} 1008 1009static void 1010fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1011{ 1012 uint16_t reg; 1013 int x; 1014 1015 /* 1016 * Shift in data. 1017 */ 1018 for (x = 1 << (length - 1); x; x >>= 1) { 1019 if (data & x) 1020 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1021 else 1022 reg = FXP_EEPROM_EECS; 1023 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1024 DELAY(1); 1025 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1026 DELAY(1); 1027 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1028 DELAY(1); 1029 } 1030} 1031 1032/* 1033 * Read from the serial EEPROM. Basically, you manually shift in 1034 * the read opcode (one bit at a time) and then shift in the address, 1035 * and then you shift out the data (all of this one bit at a time). 1036 * The word size is 16 bits, so you have to provide the address for 1037 * every 16 bits of data. 1038 */ 1039static uint16_t 1040fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1041{ 1042 uint16_t reg, data; 1043 int x; 1044 1045 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1046 /* 1047 * Shift in read opcode. 1048 */ 1049 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1050 /* 1051 * Shift in address. 1052 */ 1053 data = 0; 1054 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1055 if (offset & x) 1056 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1057 else 1058 reg = FXP_EEPROM_EECS; 1059 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1060 DELAY(1); 1061 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1062 DELAY(1); 1063 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1064 DELAY(1); 1065 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1066 data++; 1067 if (autosize && reg == 0) { 1068 sc->eeprom_size = data; 1069 break; 1070 } 1071 } 1072 /* 1073 * Shift out data. 1074 */ 1075 data = 0; 1076 reg = FXP_EEPROM_EECS; 1077 for (x = 1 << 15; x; x >>= 1) { 1078 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1079 DELAY(1); 1080 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1081 data |= x; 1082 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1083 DELAY(1); 1084 } 1085 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1086 DELAY(1); 1087 1088 return (data); 1089} 1090 1091static void 1092fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1093{ 1094 int i; 1095 1096 /* 1097 * Erase/write enable. 1098 */ 1099 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1100 fxp_eeprom_shiftin(sc, 0x4, 3); 1101 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1103 DELAY(1); 1104 /* 1105 * Shift in write opcode, address, data. 1106 */ 1107 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1108 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1109 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1110 fxp_eeprom_shiftin(sc, data, 16); 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1112 DELAY(1); 1113 /* 1114 * Wait for EEPROM to finish up. 1115 */ 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1117 DELAY(1); 1118 for (i = 0; i < 1000; i++) { 1119 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1120 break; 1121 DELAY(50); 1122 } 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1124 DELAY(1); 1125 /* 1126 * Erase/write disable. 1127 */ 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1129 fxp_eeprom_shiftin(sc, 0x4, 3); 1130 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1132 DELAY(1); 1133} 1134 1135/* 1136 * From NetBSD: 1137 * 1138 * Figure out EEPROM size. 1139 * 1140 * 559's can have either 64-word or 256-word EEPROMs, the 558 1141 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1142 * talks about the existance of 16 to 256 word EEPROMs. 1143 * 1144 * The only known sizes are 64 and 256, where the 256 version is used 1145 * by CardBus cards to store CIS information. 1146 * 1147 * The address is shifted in msb-to-lsb, and after the last 1148 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1149 * after which follows the actual data. We try to detect this zero, by 1150 * probing the data-out bit in the EEPROM control register just after 1151 * having shifted in a bit. If the bit is zero, we assume we've 1152 * shifted enough address bits. The data-out should be tri-state, 1153 * before this, which should translate to a logical one. 1154 */ 1155static void 1156fxp_autosize_eeprom(struct fxp_softc *sc) 1157{ 1158 1159 /* guess maximum size of 256 words */ 1160 sc->eeprom_size = 8; 1161 1162 /* autosize */ 1163 (void) fxp_eeprom_getword(sc, 0, 1); 1164} 1165 1166static void 1167fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1168{ 1169 int i; 1170 1171 for (i = 0; i < words; i++) 1172 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1173} 1174 1175static void 1176fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1177{ 1178 int i; 1179 1180 for (i = 0; i < words; i++) 1181 fxp_eeprom_putword(sc, offset + i, data[i]); 1182} 1183 1184/* 1185 * Grab the softc lock and call the real fxp_start_body() routine 1186 */ 1187static void 1188fxp_start(struct ifnet *ifp) 1189{ 1190 struct fxp_softc *sc = ifp->if_softc; 1191 1192 FXP_LOCK(sc); 1193 fxp_start_body(ifp); 1194 FXP_UNLOCK(sc); 1195} 1196 1197/* 1198 * Start packet transmission on the interface. 1199 * This routine must be called with the softc lock held, and is an 1200 * internal entry point only. 1201 */ 1202static void 1203fxp_start_body(struct ifnet *ifp) 1204{ 1205 struct fxp_softc *sc = ifp->if_softc; 1206 struct mbuf *mb_head; 1207 int error, txqueued; 1208 1209 FXP_LOCK_ASSERT(sc, MA_OWNED); 1210 1211 /* 1212 * See if we need to suspend xmit until the multicast filter 1213 * has been reprogrammed (which can only be done at the head 1214 * of the command chain). 1215 */ 1216 if (sc->need_mcsetup) 1217 return; 1218 1219 /* 1220 * We're finished if there is nothing more to add to the list or if 1221 * we're all filled up with buffers to transmit. 1222 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1223 * a NOP command when needed. 1224 */ 1225 txqueued = 0; 1226 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1227 sc->tx_queued < FXP_NTXCB - 1) { 1228 1229 /* 1230 * Grab a packet to transmit. 1231 */ 1232 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1233 if (mb_head == NULL) 1234 break; 1235 1236 error = fxp_encap(sc, mb_head); 1237 if (error) 1238 break; 1239 txqueued = 1; 1240 } 1241 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1242 1243 /* 1244 * We're finished. If we added to the list, issue a RESUME to get DMA 1245 * going again if suspended. 1246 */ 1247 if (txqueued) { 1248 fxp_scb_wait(sc); 1249 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1250 } 1251} 1252 1253static int 1254fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1255{ 1256 struct ifnet *ifp; 1257 struct mbuf *m; 1258 struct fxp_tx *txp; 1259 struct fxp_cb_tx *cbp; 1260 bus_dma_segment_t segs[FXP_NTXSEG]; 1261 int chainlen, error, i, nseg; 1262 1263 FXP_LOCK_ASSERT(sc, MA_OWNED); 1264 ifp = &sc->sc_if; 1265 1266 /* 1267 * Get pointer to next available tx desc. 1268 */ 1269 txp = sc->fxp_desc.tx_last->tx_next; 1270 1271 /* 1272 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1273 * Ethernet Controller Family Open Source Software 1274 * Developer Manual says: 1275 * Using software parsing is only allowed with legal 1276 * TCP/IP or UDP/IP packets. 1277 * ... 1278 * For all other datagrams, hardware parsing must 1279 * be used. 1280 * Software parsing appears to truncate ICMP and 1281 * fragmented UDP packets that contain one to three 1282 * bytes in the second (and final) mbuf of the packet. 1283 */ 1284 if (sc->flags & FXP_FLAG_EXT_RFA) 1285 txp->tx_cb->ipcb_ip_activation_high = 1286 FXP_IPCB_HARDWAREPARSING_ENABLE; 1287 1288 /* 1289 * Deal with TCP/IP checksum offload. Note that 1290 * in order for TCP checksum offload to work, 1291 * the pseudo header checksum must have already 1292 * been computed and stored in the checksum field 1293 * in the TCP header. The stack should have 1294 * already done this for us. 1295 */ 1296 if (m_head->m_pkthdr.csum_flags) { 1297 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1298 txp->tx_cb->ipcb_ip_schedule = 1299 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1300 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1301 txp->tx_cb->ipcb_ip_schedule |= 1302 FXP_IPCB_TCP_PACKET; 1303 } 1304 1305#ifdef FXP_IP_CSUM_WAR 1306 /* 1307 * XXX The 82550 chip appears to have trouble 1308 * dealing with IP header checksums in very small 1309 * datagrams, namely fragments from 1 to 3 bytes 1310 * in size. For example, say you want to transmit 1311 * a UDP packet of 1473 bytes. The packet will be 1312 * fragmented over two IP datagrams, the latter 1313 * containing only one byte of data. The 82550 will 1314 * botch the header checksum on the 1-byte fragment. 1315 * As long as the datagram contains 4 or more bytes 1316 * of data, you're ok. 1317 * 1318 * The following code attempts to work around this 1319 * problem: if the datagram is less than 38 bytes 1320 * in size (14 bytes ether header, 20 bytes IP header, 1321 * plus 4 bytes of data), we punt and compute the IP 1322 * header checksum by hand. This workaround doesn't 1323 * work very well, however, since it can be fooled 1324 * by things like VLAN tags and IP options that make 1325 * the header sizes/offsets vary. 1326 */ 1327 1328 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1329 if (m_head->m_pkthdr.len < 38) { 1330 struct ip *ip; 1331 m_head->m_data += ETHER_HDR_LEN; 1332 ip = mtod(mb_head, struct ip *); 1333 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1334 m_head->m_data -= ETHER_HDR_LEN; 1335 } else { 1336 txp->tx_cb->ipcb_ip_activation_high = 1337 FXP_IPCB_HARDWAREPARSING_ENABLE; 1338 txp->tx_cb->ipcb_ip_schedule |= 1339 FXP_IPCB_IP_CHECKSUM_ENABLE; 1340 } 1341 } 1342#endif 1343 } 1344 1345 chainlen = 0; 1346 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1347 chainlen++; 1348 if (chainlen > sc->maxtxseg) { 1349 struct mbuf *mn; 1350 1351 /* 1352 * We ran out of segments. We have to recopy this 1353 * mbuf chain first. Bail out if we can't get the 1354 * new buffers. 1355 */ 1356 mn = m_defrag(m_head, M_DONTWAIT); 1357 if (mn == NULL) { 1358 m_freem(m_head); 1359 return (-1); 1360 } else { 1361 m_head = mn; 1362 } 1363 } 1364 1365 /* 1366 * Go through each of the mbufs in the chain and initialize 1367 * the transmit buffer descriptors with the physical address 1368 * and size of the mbuf. 1369 */ 1370 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1371 m_head, segs, &nseg, 0); 1372 if (error) { 1373 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1374 m_freem(m_head); 1375 return (-1); 1376 } 1377 1378 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1379 1380 cbp = txp->tx_cb; 1381 for (i = 0; i < nseg; i++) { 1382 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1383 /* 1384 * If this is an 82550/82551, then we're using extended 1385 * TxCBs _and_ we're using checksum offload. This means 1386 * that the TxCB is really an IPCB. One major difference 1387 * between the two is that with plain extended TxCBs, 1388 * the bottom half of the TxCB contains two entries from 1389 * the TBD array, whereas IPCBs contain just one entry: 1390 * one entry (8 bytes) has been sacrificed for the TCP/IP 1391 * checksum offload control bits. So to make things work 1392 * right, we have to start filling in the TBD array 1393 * starting from a different place depending on whether 1394 * the chip is an 82550/82551 or not. 1395 */ 1396 if (sc->flags & FXP_FLAG_EXT_RFA) { 1397 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1398 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1399 } else { 1400 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1401 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1402 } 1403 } 1404 cbp->tbd_number = nseg; 1405 1406 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1407 txp->tx_mbuf = m_head; 1408 txp->tx_cb->cb_status = 0; 1409 txp->tx_cb->byte_count = 0; 1410 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1411 txp->tx_cb->cb_command = 1412 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1413 FXP_CB_COMMAND_S); 1414 } else { 1415 txp->tx_cb->cb_command = 1416 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1417 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1418 /* 1419 * Set a 5 second timer just in case we don't hear 1420 * from the card again. 1421 */ 1422 ifp->if_timer = 5; 1423 } 1424 txp->tx_cb->tx_threshold = tx_threshold; 1425 1426 /* 1427 * Advance the end of list forward. 1428 */ 1429 1430#ifdef __alpha__ 1431 /* 1432 * On platforms which can't access memory in 16-bit 1433 * granularities, we must prevent the card from DMA'ing 1434 * up the status while we update the command field. 1435 * This could cause us to overwrite the completion status. 1436 * XXX This is probably bogus and we're _not_ looking 1437 * for atomicity here. 1438 */ 1439 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1440 htole16(FXP_CB_COMMAND_S)); 1441#else 1442 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1443#endif /*__alpha__*/ 1444 sc->fxp_desc.tx_last = txp; 1445 1446 /* 1447 * Advance the beginning of the list forward if there are 1448 * no other packets queued (when nothing is queued, tx_first 1449 * sits on the last TxCB that was sent out). 1450 */ 1451 if (sc->tx_queued == 0) 1452 sc->fxp_desc.tx_first = txp; 1453 1454 sc->tx_queued++; 1455 1456 /* 1457 * Pass packet to bpf if there is a listener. 1458 */ 1459 BPF_MTAP(ifp, m_head); 1460 return (0); 1461} 1462 1463#ifdef DEVICE_POLLING 1464static poll_handler_t fxp_poll; 1465 1466static void 1467fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1468{ 1469 struct fxp_softc *sc = ifp->if_softc; 1470 uint8_t statack; 1471 1472 FXP_LOCK(sc); 1473 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1474 ether_poll_deregister(ifp); 1475 cmd = POLL_DEREGISTER; 1476 } 1477 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1478 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1479 FXP_UNLOCK(sc); 1480 return; 1481 } 1482 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1483 FXP_SCB_STATACK_FR; 1484 if (cmd == POLL_AND_CHECK_STATUS) { 1485 uint8_t tmp; 1486 1487 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1488 if (tmp == 0xff || tmp == 0) { 1489 FXP_UNLOCK(sc); 1490 return; /* nothing to do */ 1491 } 1492 tmp &= ~statack; 1493 /* ack what we can */ 1494 if (tmp != 0) 1495 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1496 statack |= tmp; 1497 } 1498 fxp_intr_body(sc, ifp, statack, count); 1499 FXP_UNLOCK(sc); 1500} 1501#endif /* DEVICE_POLLING */ 1502 1503/* 1504 * Process interface interrupts. 1505 */ 1506static void 1507fxp_intr(void *xsc) 1508{ 1509 struct fxp_softc *sc = xsc; 1510 struct ifnet *ifp = &sc->sc_if; 1511 uint8_t statack; 1512 1513 FXP_LOCK(sc); 1514 if (sc->suspended) { 1515 FXP_UNLOCK(sc); 1516 return; 1517 } 1518 1519#ifdef DEVICE_POLLING 1520 if (ifp->if_flags & IFF_POLLING) { 1521 FXP_UNLOCK(sc); 1522 return; 1523 } 1524 if ((ifp->if_capenable & IFCAP_POLLING) && 1525 ether_poll_register(fxp_poll, ifp)) { 1526 /* disable interrupts */ 1527 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1528 FXP_UNLOCK(sc); 1529 fxp_poll(ifp, 0, 1); 1530 return; 1531 } 1532#endif 1533 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1534 /* 1535 * It should not be possible to have all bits set; the 1536 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1537 * all bits are set, this may indicate that the card has 1538 * been physically ejected, so ignore it. 1539 */ 1540 if (statack == 0xff) { 1541 FXP_UNLOCK(sc); 1542 return; 1543 } 1544 1545 /* 1546 * First ACK all the interrupts in this pass. 1547 */ 1548 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1549 fxp_intr_body(sc, ifp, statack, -1); 1550 } 1551 FXP_UNLOCK(sc); 1552} 1553 1554static void 1555fxp_txeof(struct fxp_softc *sc) 1556{ 1557 struct fxp_tx *txp; 1558 1559 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1560 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1561 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1562 txp = txp->tx_next) { 1563 if (txp->tx_mbuf != NULL) { 1564 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1565 BUS_DMASYNC_POSTWRITE); 1566 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1567 m_freem(txp->tx_mbuf); 1568 txp->tx_mbuf = NULL; 1569 /* clear this to reset csum offload bits */ 1570 txp->tx_cb->tbd[0].tb_addr = 0; 1571 } 1572 sc->tx_queued--; 1573 } 1574 sc->fxp_desc.tx_first = txp; 1575 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1576} 1577 1578static void 1579fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1580 int count) 1581{ 1582 struct mbuf *m; 1583 struct fxp_rx *rxp; 1584 struct fxp_rfa *rfa; 1585 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1586 1587 FXP_LOCK_ASSERT(sc, MA_OWNED); 1588 if (rnr) 1589 sc->rnr++; 1590#ifdef DEVICE_POLLING 1591 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1592 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1593 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1594 rnr = 1; 1595 } 1596#endif 1597 1598 /* 1599 * Free any finished transmit mbuf chains. 1600 * 1601 * Handle the CNA event likt a CXTNO event. It used to 1602 * be that this event (control unit not ready) was not 1603 * encountered, but it is now with the SMPng modifications. 1604 * The exact sequence of events that occur when the interface 1605 * is brought up are different now, and if this event 1606 * goes unhandled, the configuration/rxfilter setup sequence 1607 * can stall for several seconds. The result is that no 1608 * packets go out onto the wire for about 5 to 10 seconds 1609 * after the interface is ifconfig'ed for the first time. 1610 */ 1611 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1612 fxp_txeof(sc); 1613 1614 ifp->if_timer = 0; 1615 if (sc->tx_queued == 0) { 1616 if (sc->need_mcsetup) 1617 fxp_mc_setup(sc); 1618 } 1619 /* 1620 * Try to start more packets transmitting. 1621 */ 1622 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1623 fxp_start_body(ifp); 1624 } 1625 1626 /* 1627 * Just return if nothing happened on the receive side. 1628 */ 1629 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1630 return; 1631 1632 /* 1633 * Process receiver interrupts. If a no-resource (RNR) 1634 * condition exists, get whatever packets we can and 1635 * re-start the receiver. 1636 * 1637 * When using polling, we do not process the list to completion, 1638 * so when we get an RNR interrupt we must defer the restart 1639 * until we hit the last buffer with the C bit set. 1640 * If we run out of cycles and rfa_headm has the C bit set, 1641 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1642 * that the info will be used in the subsequent polling cycle. 1643 */ 1644 for (;;) { 1645 rxp = sc->fxp_desc.rx_head; 1646 m = rxp->rx_mbuf; 1647 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1648 RFA_ALIGNMENT_FUDGE); 1649 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1650 BUS_DMASYNC_POSTREAD); 1651 1652#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1653 if (count >= 0 && count-- == 0) { 1654 if (rnr) { 1655 /* Defer RNR processing until the next time. */ 1656 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1657 rnr = 0; 1658 } 1659 break; 1660 } 1661#endif /* DEVICE_POLLING */ 1662 1663 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1664 break; 1665 1666 /* 1667 * Advance head forward. 1668 */ 1669 sc->fxp_desc.rx_head = rxp->rx_next; 1670 1671 /* 1672 * Add a new buffer to the receive chain. 1673 * If this fails, the old buffer is recycled 1674 * instead. 1675 */ 1676 if (fxp_add_rfabuf(sc, rxp) == 0) { 1677 int total_len; 1678 1679 /* 1680 * Fetch packet length (the top 2 bits of 1681 * actual_size are flags set by the controller 1682 * upon completion), and drop the packet in case 1683 * of bogus length or CRC errors. 1684 */ 1685 total_len = le16toh(rfa->actual_size) & 0x3fff; 1686 if (total_len < sizeof(struct ether_header) || 1687 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1688 sc->rfa_size || 1689 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1690 m_freem(m); 1691 continue; 1692 } 1693 1694 /* Do IP checksum checking. */ 1695 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1696 if (rfa->rfax_csum_sts & 1697 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1698 m->m_pkthdr.csum_flags |= 1699 CSUM_IP_CHECKED; 1700 if (rfa->rfax_csum_sts & 1701 FXP_RFDX_CS_IP_CSUM_VALID) 1702 m->m_pkthdr.csum_flags |= 1703 CSUM_IP_VALID; 1704 if ((rfa->rfax_csum_sts & 1705 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1706 (rfa->rfax_csum_sts & 1707 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1708 m->m_pkthdr.csum_flags |= 1709 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1710 m->m_pkthdr.csum_data = 0xffff; 1711 } 1712 } 1713 1714 m->m_pkthdr.len = m->m_len = total_len; 1715 m->m_pkthdr.rcvif = ifp; 1716 1717 /* 1718 * Drop locks before calling if_input() since it 1719 * may re-enter fxp_start() in the netisr case. 1720 * This would result in a lock reversal. Better 1721 * performance might be obtained by chaining all 1722 * packets received, dropping the lock, and then 1723 * calling if_input() on each one. 1724 */ 1725 FXP_UNLOCK(sc); 1726 (*ifp->if_input)(ifp, m); 1727 FXP_LOCK(sc); 1728 } 1729 } 1730 if (rnr) { 1731 fxp_scb_wait(sc); 1732 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1733 sc->fxp_desc.rx_head->rx_addr); 1734 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1735 } 1736} 1737 1738/* 1739 * Update packet in/out/collision statistics. The i82557 doesn't 1740 * allow you to access these counters without doing a fairly 1741 * expensive DMA to get _all_ of the statistics it maintains, so 1742 * we do this operation here only once per second. The statistics 1743 * counters in the kernel are updated from the previous dump-stats 1744 * DMA and then a new dump-stats DMA is started. The on-chip 1745 * counters are zeroed when the DMA completes. If we can't start 1746 * the DMA immediately, we don't wait - we just prepare to read 1747 * them again next time. 1748 */ 1749static void 1750fxp_tick(void *xsc) 1751{ 1752 struct fxp_softc *sc = xsc; 1753 struct ifnet *ifp = &sc->sc_if; 1754 struct fxp_stats *sp = sc->fxp_stats; 1755 int s; 1756 1757 FXP_LOCK(sc); 1758 s = splimp(); 1759 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1760 ifp->if_opackets += le32toh(sp->tx_good); 1761 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1762 if (sp->rx_good) { 1763 ifp->if_ipackets += le32toh(sp->rx_good); 1764 sc->rx_idle_secs = 0; 1765 } else { 1766 /* 1767 * Receiver's been idle for another second. 1768 */ 1769 sc->rx_idle_secs++; 1770 } 1771 ifp->if_ierrors += 1772 le32toh(sp->rx_crc_errors) + 1773 le32toh(sp->rx_alignment_errors) + 1774 le32toh(sp->rx_rnr_errors) + 1775 le32toh(sp->rx_overrun_errors); 1776 /* 1777 * If any transmit underruns occured, bump up the transmit 1778 * threshold by another 512 bytes (64 * 8). 1779 */ 1780 if (sp->tx_underruns) { 1781 ifp->if_oerrors += le32toh(sp->tx_underruns); 1782 if (tx_threshold < 192) 1783 tx_threshold += 64; 1784 } 1785 1786 /* 1787 * Release any xmit buffers that have completed DMA. This isn't 1788 * strictly necessary to do here, but it's advantagous for mbufs 1789 * with external storage to be released in a timely manner rather 1790 * than being defered for a potentially long time. This limits 1791 * the delay to a maximum of one second. 1792 */ 1793 fxp_txeof(sc); 1794 1795 /* 1796 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1797 * then assume the receiver has locked up and attempt to clear 1798 * the condition by reprogramming the multicast filter. This is 1799 * a work-around for a bug in the 82557 where the receiver locks 1800 * up if it gets certain types of garbage in the syncronization 1801 * bits prior to the packet header. This bug is supposed to only 1802 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1803 * mode as well (perhaps due to a 10/100 speed transition). 1804 */ 1805 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1806 sc->rx_idle_secs = 0; 1807 fxp_mc_setup(sc); 1808 } 1809 /* 1810 * If there is no pending command, start another stats 1811 * dump. Otherwise punt for now. 1812 */ 1813 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1814 /* 1815 * Start another stats dump. 1816 */ 1817 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1818 BUS_DMASYNC_PREREAD); 1819 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1820 } else { 1821 /* 1822 * A previous command is still waiting to be accepted. 1823 * Just zero our copy of the stats and wait for the 1824 * next timer event to update them. 1825 */ 1826 sp->tx_good = 0; 1827 sp->tx_underruns = 0; 1828 sp->tx_total_collisions = 0; 1829 1830 sp->rx_good = 0; 1831 sp->rx_crc_errors = 0; 1832 sp->rx_alignment_errors = 0; 1833 sp->rx_rnr_errors = 0; 1834 sp->rx_overrun_errors = 0; 1835 } 1836 if (sc->miibus != NULL) 1837 mii_tick(device_get_softc(sc->miibus)); 1838 1839 /* 1840 * Schedule another timeout one second from now. 1841 */ 1842 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1843 FXP_UNLOCK(sc); 1844 splx(s); 1845} 1846 1847/* 1848 * Stop the interface. Cancels the statistics updater and resets 1849 * the interface. 1850 */ 1851static void 1852fxp_stop(struct fxp_softc *sc) 1853{ 1854 struct ifnet *ifp = &sc->sc_if; 1855 struct fxp_tx *txp; 1856 int i; 1857 1858 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1859 ifp->if_timer = 0; 1860 1861#ifdef DEVICE_POLLING 1862 ether_poll_deregister(ifp); 1863#endif 1864 /* 1865 * Cancel stats updater. 1866 */ 1867 callout_stop(&sc->stat_ch); 1868 1869 /* 1870 * Issue software reset, which also unloads the microcode. 1871 */ 1872 sc->flags &= ~FXP_FLAG_UCODE; 1873 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1874 DELAY(50); 1875 1876 /* 1877 * Release any xmit buffers. 1878 */ 1879 txp = sc->fxp_desc.tx_list; 1880 if (txp != NULL) { 1881 for (i = 0; i < FXP_NTXCB; i++) { 1882 if (txp[i].tx_mbuf != NULL) { 1883 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1884 BUS_DMASYNC_POSTWRITE); 1885 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1886 m_freem(txp[i].tx_mbuf); 1887 txp[i].tx_mbuf = NULL; 1888 /* clear this to reset csum offload bits */ 1889 txp[i].tx_cb->tbd[0].tb_addr = 0; 1890 } 1891 } 1892 } 1893 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1894 sc->tx_queued = 0; 1895} 1896 1897/* 1898 * Watchdog/transmission transmit timeout handler. Called when a 1899 * transmission is started on the interface, but no interrupt is 1900 * received before the timeout. This usually indicates that the 1901 * card has wedged for some reason. 1902 */ 1903static void 1904fxp_watchdog(struct ifnet *ifp) 1905{ 1906 struct fxp_softc *sc = ifp->if_softc; 1907 1908 FXP_LOCK(sc); 1909 device_printf(sc->dev, "device timeout\n"); 1910 ifp->if_oerrors++; 1911 1912 fxp_init_body(sc); 1913 FXP_UNLOCK(sc); 1914} 1915 1916/* 1917 * Acquire locks and then call the real initialization function. This 1918 * is necessary because ether_ioctl() calls if_init() and this would 1919 * result in mutex recursion if the mutex was held. 1920 */ 1921static void 1922fxp_init(void *xsc) 1923{ 1924 struct fxp_softc *sc = xsc; 1925 1926 FXP_LOCK(sc); 1927 fxp_init_body(sc); 1928 FXP_UNLOCK(sc); 1929} 1930 1931/* 1932 * Perform device initialization. This routine must be called with the 1933 * softc lock held. 1934 */ 1935static void 1936fxp_init_body(struct fxp_softc *sc) 1937{ 1938 struct ifnet *ifp = &sc->sc_if; 1939 struct fxp_cb_config *cbp; 1940 struct fxp_cb_ias *cb_ias; 1941 struct fxp_cb_tx *tcbp; 1942 struct fxp_tx *txp; 1943 struct fxp_cb_mcs *mcsp; 1944 int i, prm, s; 1945 1946 FXP_LOCK_ASSERT(sc, MA_OWNED); 1947 s = splimp(); 1948 /* 1949 * Cancel any pending I/O 1950 */ 1951 fxp_stop(sc); 1952 1953 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1954 1955 /* 1956 * Initialize base of CBL and RFA memory. Loading with zero 1957 * sets it up for regular linear addressing. 1958 */ 1959 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1960 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1961 1962 fxp_scb_wait(sc); 1963 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1964 1965 /* 1966 * Initialize base of dump-stats buffer. 1967 */ 1968 fxp_scb_wait(sc); 1969 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1970 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1971 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1972 1973 /* 1974 * Attempt to load microcode if requested. 1975 */ 1976 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1977 fxp_load_ucode(sc); 1978 1979 /* 1980 * Initialize the multicast address list. 1981 */ 1982 if (fxp_mc_addrs(sc)) { 1983 mcsp = sc->mcsp; 1984 mcsp->cb_status = 0; 1985 mcsp->cb_command = 1986 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1987 mcsp->link_addr = 0xffffffff; 1988 /* 1989 * Start the multicast setup command. 1990 */ 1991 fxp_scb_wait(sc); 1992 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1993 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1994 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1995 /* ...and wait for it to complete. */ 1996 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1997 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1998 BUS_DMASYNC_POSTWRITE); 1999 } 2000 2001 /* 2002 * We temporarily use memory that contains the TxCB list to 2003 * construct the config CB. The TxCB list memory is rebuilt 2004 * later. 2005 */ 2006 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2007 2008 /* 2009 * This bcopy is kind of disgusting, but there are a bunch of must be 2010 * zero and must be one bits in this structure and this is the easiest 2011 * way to initialize them all to proper values. 2012 */ 2013 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2014 2015 cbp->cb_status = 0; 2016 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2017 FXP_CB_COMMAND_EL); 2018 cbp->link_addr = 0xffffffff; /* (no) next command */ 2019 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2020 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2021 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2022 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2023 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2024 cbp->type_enable = 0; /* actually reserved */ 2025 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2026 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2027 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2028 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2029 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2030 cbp->late_scb = 0; /* (don't) defer SCB update */ 2031 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2032 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2033 cbp->ci_int = 1; /* interrupt on CU idle */ 2034 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2035 cbp->ext_stats_dis = 1; /* disable extended counters */ 2036 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2037 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2038 cbp->disc_short_rx = !prm; /* discard short packets */ 2039 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2040 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2041 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2042 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2043 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2044 cbp->csma_dis = 0; /* (don't) disable link */ 2045 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2046 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2047 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2048 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2049 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2050 cbp->nsai = 1; /* (don't) disable source addr insert */ 2051 cbp->preamble_length = 2; /* (7 byte) preamble */ 2052 cbp->loopback = 0; /* (don't) loopback */ 2053 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2054 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2055 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2056 cbp->promiscuous = prm; /* promiscuous mode */ 2057 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2058 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2059 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2060 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2061 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2062 2063 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2064 cbp->padding = 1; /* (do) pad short tx packets */ 2065 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2066 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2067 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2068 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2069 /* must set wake_en in PMCSR also */ 2070 cbp->force_fdx = 0; /* (don't) force full duplex */ 2071 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2072 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2073 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2074 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2075 2076 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2077 /* 2078 * The 82557 has no hardware flow control, the values 2079 * below are the defaults for the chip. 2080 */ 2081 cbp->fc_delay_lsb = 0; 2082 cbp->fc_delay_msb = 0x40; 2083 cbp->pri_fc_thresh = 3; 2084 cbp->tx_fc_dis = 0; 2085 cbp->rx_fc_restop = 0; 2086 cbp->rx_fc_restart = 0; 2087 cbp->fc_filter = 0; 2088 cbp->pri_fc_loc = 1; 2089 } else { 2090 cbp->fc_delay_lsb = 0x1f; 2091 cbp->fc_delay_msb = 0x01; 2092 cbp->pri_fc_thresh = 3; 2093 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2094 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2095 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2096 cbp->fc_filter = !prm; /* drop FC frames to host */ 2097 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2098 } 2099 2100 /* 2101 * Start the config command/DMA. 2102 */ 2103 fxp_scb_wait(sc); 2104 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2105 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2106 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2107 /* ...and wait for it to complete. */ 2108 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2109 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2110 2111 /* 2112 * Now initialize the station address. Temporarily use the TxCB 2113 * memory area like we did above for the config CB. 2114 */ 2115 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2116 cb_ias->cb_status = 0; 2117 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2118 cb_ias->link_addr = 0xffffffff; 2119 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2120 sizeof(sc->arpcom.ac_enaddr)); 2121 2122 /* 2123 * Start the IAS (Individual Address Setup) command/DMA. 2124 */ 2125 fxp_scb_wait(sc); 2126 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2127 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2128 /* ...and wait for it to complete. */ 2129 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2130 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2131 2132 /* 2133 * Initialize transmit control block (TxCB) list. 2134 */ 2135 txp = sc->fxp_desc.tx_list; 2136 tcbp = sc->fxp_desc.cbl_list; 2137 bzero(tcbp, FXP_TXCB_SZ); 2138 for (i = 0; i < FXP_NTXCB; i++) { 2139 txp[i].tx_mbuf = NULL; 2140 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2141 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2142 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2143 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2144 if (sc->flags & FXP_FLAG_EXT_TXCB) 2145 tcbp[i].tbd_array_addr = 2146 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2147 else 2148 tcbp[i].tbd_array_addr = 2149 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2150 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2151 } 2152 /* 2153 * Set the suspend flag on the first TxCB and start the control 2154 * unit. It will execute the NOP and then suspend. 2155 */ 2156 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2157 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2158 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2159 sc->tx_queued = 1; 2160 2161 fxp_scb_wait(sc); 2162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2163 2164 /* 2165 * Initialize receiver buffer area - RFA. 2166 */ 2167 fxp_scb_wait(sc); 2168 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2170 2171 /* 2172 * Set current media. 2173 */ 2174 if (sc->miibus != NULL) 2175 mii_mediachg(device_get_softc(sc->miibus)); 2176 2177 ifp->if_flags |= IFF_RUNNING; 2178 ifp->if_flags &= ~IFF_OACTIVE; 2179 2180 /* 2181 * Enable interrupts. 2182 */ 2183#ifdef DEVICE_POLLING 2184 /* 2185 * ... but only do that if we are not polling. And because (presumably) 2186 * the default is interrupts on, we need to disable them explicitly! 2187 */ 2188 if ( ifp->if_flags & IFF_POLLING ) 2189 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2190 else 2191#endif /* DEVICE_POLLING */ 2192 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2193 2194 /* 2195 * Start stats updater. 2196 */ 2197 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2198 splx(s); 2199} 2200 2201static int 2202fxp_serial_ifmedia_upd(struct ifnet *ifp) 2203{ 2204 2205 return (0); 2206} 2207 2208static void 2209fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2210{ 2211 2212 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2213} 2214 2215/* 2216 * Change media according to request. 2217 */ 2218static int 2219fxp_ifmedia_upd(struct ifnet *ifp) 2220{ 2221 struct fxp_softc *sc = ifp->if_softc; 2222 struct mii_data *mii; 2223 2224 mii = device_get_softc(sc->miibus); 2225 mii_mediachg(mii); 2226 return (0); 2227} 2228 2229/* 2230 * Notify the world which media we're using. 2231 */ 2232static void 2233fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2234{ 2235 struct fxp_softc *sc = ifp->if_softc; 2236 struct mii_data *mii; 2237 2238 mii = device_get_softc(sc->miibus); 2239 mii_pollstat(mii); 2240 ifmr->ifm_active = mii->mii_media_active; 2241 ifmr->ifm_status = mii->mii_media_status; 2242 2243 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2244 sc->cu_resume_bug = 1; 2245 else 2246 sc->cu_resume_bug = 0; 2247} 2248 2249/* 2250 * Add a buffer to the end of the RFA buffer list. 2251 * Return 0 if successful, 1 for failure. A failure results in 2252 * adding the 'oldm' (if non-NULL) on to the end of the list - 2253 * tossing out its old contents and recycling it. 2254 * The RFA struct is stuck at the beginning of mbuf cluster and the 2255 * data pointer is fixed up to point just past it. 2256 */ 2257static int 2258fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2259{ 2260 struct mbuf *m; 2261 struct fxp_rfa *rfa, *p_rfa; 2262 struct fxp_rx *p_rx; 2263 bus_dmamap_t tmp_map; 2264 int error; 2265 2266 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2267 if (m == NULL) 2268 return (ENOBUFS); 2269 2270 /* 2271 * Move the data pointer up so that the incoming data packet 2272 * will be 32-bit aligned. 2273 */ 2274 m->m_data += RFA_ALIGNMENT_FUDGE; 2275 2276 /* 2277 * Get a pointer to the base of the mbuf cluster and move 2278 * data start past it. 2279 */ 2280 rfa = mtod(m, struct fxp_rfa *); 2281 m->m_data += sc->rfa_size; 2282 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2283 2284 rfa->rfa_status = 0; 2285 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2286 rfa->actual_size = 0; 2287 2288 /* 2289 * Initialize the rest of the RFA. Note that since the RFA 2290 * is misaligned, we cannot store values directly. We're thus 2291 * using the le32enc() function which handles endianness and 2292 * is also alignment-safe. 2293 */ 2294 le32enc(&rfa->link_addr, 0xffffffff); 2295 le32enc(&rfa->rbd_addr, 0xffffffff); 2296 2297 /* Map the RFA into DMA memory. */ 2298 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2299 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2300 &rxp->rx_addr, 0); 2301 if (error) { 2302 m_freem(m); 2303 return (error); 2304 } 2305 2306 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2307 tmp_map = sc->spare_map; 2308 sc->spare_map = rxp->rx_map; 2309 rxp->rx_map = tmp_map; 2310 rxp->rx_mbuf = m; 2311 2312 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2313 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2314 2315 /* 2316 * If there are other buffers already on the list, attach this 2317 * one to the end by fixing up the tail to point to this one. 2318 */ 2319 if (sc->fxp_desc.rx_head != NULL) { 2320 p_rx = sc->fxp_desc.rx_tail; 2321 p_rfa = (struct fxp_rfa *) 2322 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2323 p_rx->rx_next = rxp; 2324 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2325 p_rfa->rfa_control = 0; 2326 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2327 BUS_DMASYNC_PREWRITE); 2328 } else { 2329 rxp->rx_next = NULL; 2330 sc->fxp_desc.rx_head = rxp; 2331 } 2332 sc->fxp_desc.rx_tail = rxp; 2333 return (0); 2334} 2335 2336static volatile int 2337fxp_miibus_readreg(device_t dev, int phy, int reg) 2338{ 2339 struct fxp_softc *sc = device_get_softc(dev); 2340 int count = 10000; 2341 int value; 2342 2343 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2344 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2345 2346 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2347 && count--) 2348 DELAY(10); 2349 2350 if (count <= 0) 2351 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2352 2353 return (value & 0xffff); 2354} 2355 2356static void 2357fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2358{ 2359 struct fxp_softc *sc = device_get_softc(dev); 2360 int count = 10000; 2361 2362 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2363 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2364 (value & 0xffff)); 2365 2366 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2367 count--) 2368 DELAY(10); 2369 2370 if (count <= 0) 2371 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2372} 2373 2374static int 2375fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2376{ 2377 struct fxp_softc *sc = ifp->if_softc; 2378 struct ifreq *ifr = (struct ifreq *)data; 2379 struct mii_data *mii; 2380 int flag, mask, s, error = 0; 2381 2382 /* 2383 * Detaching causes us to call ioctl with the mutex owned. Preclude 2384 * that by saying we're busy if the lock is already held. 2385 */ 2386 if (FXP_LOCKED(sc)) 2387 return (EBUSY); 2388 2389 FXP_LOCK(sc); 2390 s = splimp(); 2391 2392 switch (command) { 2393 case SIOCSIFFLAGS: 2394 if (ifp->if_flags & IFF_ALLMULTI) 2395 sc->flags |= FXP_FLAG_ALL_MCAST; 2396 else 2397 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2398 2399 /* 2400 * If interface is marked up and not running, then start it. 2401 * If it is marked down and running, stop it. 2402 * XXX If it's up then re-initialize it. This is so flags 2403 * such as IFF_PROMISC are handled. 2404 */ 2405 if (ifp->if_flags & IFF_UP) { 2406 fxp_init_body(sc); 2407 } else { 2408 if (ifp->if_flags & IFF_RUNNING) 2409 fxp_stop(sc); 2410 } 2411 break; 2412 2413 case SIOCADDMULTI: 2414 case SIOCDELMULTI: 2415 if (ifp->if_flags & IFF_ALLMULTI) 2416 sc->flags |= FXP_FLAG_ALL_MCAST; 2417 else 2418 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2419 /* 2420 * Multicast list has changed; set the hardware filter 2421 * accordingly. 2422 */ 2423 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2424 fxp_mc_setup(sc); 2425 /* 2426 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2427 * again rather than else {}. 2428 */ 2429 if (sc->flags & FXP_FLAG_ALL_MCAST) 2430 fxp_init_body(sc); 2431 error = 0; 2432 break; 2433 2434 case SIOCSIFMEDIA: 2435 case SIOCGIFMEDIA: 2436 if (sc->miibus != NULL) { 2437 mii = device_get_softc(sc->miibus); 2438 error = ifmedia_ioctl(ifp, ifr, 2439 &mii->mii_media, command); 2440 } else { 2441 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2442 } 2443 break; 2444 2445 case SIOCSIFCAP: 2446 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2447 if (mask & IFCAP_POLLING) 2448 ifp->if_capenable ^= IFCAP_POLLING; 2449 if (mask & IFCAP_VLAN_MTU) { 2450 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2451 if (sc->revision != FXP_REV_82557) 2452 flag = FXP_FLAG_LONG_PKT_EN; 2453 else /* a hack to get long frames on the old chip */ 2454 flag = FXP_FLAG_SAVE_BAD; 2455 sc->flags ^= flag; 2456 if (ifp->if_flags & IFF_UP) 2457 fxp_init_body(sc); 2458 } 2459 break; 2460 2461 default: 2462 /* 2463 * ether_ioctl() will eventually call fxp_start() which 2464 * will result in mutex recursion so drop it first. 2465 */ 2466 FXP_UNLOCK(sc); 2467 error = ether_ioctl(ifp, command, data); 2468 } 2469 if (FXP_LOCKED(sc)) 2470 FXP_UNLOCK(sc); 2471 splx(s); 2472 return (error); 2473} 2474 2475/* 2476 * Fill in the multicast address list and return number of entries. 2477 */ 2478static int 2479fxp_mc_addrs(struct fxp_softc *sc) 2480{ 2481 struct fxp_cb_mcs *mcsp = sc->mcsp; 2482 struct ifnet *ifp = &sc->sc_if; 2483 struct ifmultiaddr *ifma; 2484 int nmcasts; 2485 2486 nmcasts = 0; 2487 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2488#if __FreeBSD_version < 500000 2489 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2490#else 2491 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2492#endif 2493 if (ifma->ifma_addr->sa_family != AF_LINK) 2494 continue; 2495 if (nmcasts >= MAXMCADDR) { 2496 sc->flags |= FXP_FLAG_ALL_MCAST; 2497 nmcasts = 0; 2498 break; 2499 } 2500 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2501 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2502 nmcasts++; 2503 } 2504 } 2505 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2506 return (nmcasts); 2507} 2508 2509/* 2510 * Program the multicast filter. 2511 * 2512 * We have an artificial restriction that the multicast setup command 2513 * must be the first command in the chain, so we take steps to ensure 2514 * this. By requiring this, it allows us to keep up the performance of 2515 * the pre-initialized command ring (esp. link pointers) by not actually 2516 * inserting the mcsetup command in the ring - i.e. its link pointer 2517 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2518 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2519 * lead into the regular TxCB ring when it completes. 2520 * 2521 * This function must be called at splimp. 2522 */ 2523static void 2524fxp_mc_setup(struct fxp_softc *sc) 2525{ 2526 struct fxp_cb_mcs *mcsp = sc->mcsp; 2527 struct ifnet *ifp = &sc->sc_if; 2528 struct fxp_tx *txp; 2529 int count; 2530 2531 FXP_LOCK_ASSERT(sc, MA_OWNED); 2532 /* 2533 * If there are queued commands, we must wait until they are all 2534 * completed. If we are already waiting, then add a NOP command 2535 * with interrupt option so that we're notified when all commands 2536 * have been completed - fxp_start() ensures that no additional 2537 * TX commands will be added when need_mcsetup is true. 2538 */ 2539 if (sc->tx_queued) { 2540 /* 2541 * need_mcsetup will be true if we are already waiting for the 2542 * NOP command to be completed (see below). In this case, bail. 2543 */ 2544 if (sc->need_mcsetup) 2545 return; 2546 sc->need_mcsetup = 1; 2547 2548 /* 2549 * Add a NOP command with interrupt so that we are notified 2550 * when all TX commands have been processed. 2551 */ 2552 txp = sc->fxp_desc.tx_last->tx_next; 2553 txp->tx_mbuf = NULL; 2554 txp->tx_cb->cb_status = 0; 2555 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2556 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2557 /* 2558 * Advance the end of list forward. 2559 */ 2560 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2561 htole16(~FXP_CB_COMMAND_S); 2562 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2563 sc->fxp_desc.tx_last = txp; 2564 sc->tx_queued++; 2565 /* 2566 * Issue a resume in case the CU has just suspended. 2567 */ 2568 fxp_scb_wait(sc); 2569 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2570 /* 2571 * Set a 5 second timer just in case we don't hear from the 2572 * card again. 2573 */ 2574 ifp->if_timer = 5; 2575 2576 return; 2577 } 2578 sc->need_mcsetup = 0; 2579 2580 /* 2581 * Initialize multicast setup descriptor. 2582 */ 2583 mcsp->cb_status = 0; 2584 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2585 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2586 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2587 txp = &sc->fxp_desc.mcs_tx; 2588 txp->tx_mbuf = NULL; 2589 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2590 txp->tx_next = sc->fxp_desc.tx_list; 2591 (void) fxp_mc_addrs(sc); 2592 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2593 sc->tx_queued = 1; 2594 2595 /* 2596 * Wait until command unit is not active. This should never 2597 * be the case when nothing is queued, but make sure anyway. 2598 */ 2599 count = 100; 2600 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2601 FXP_SCB_CUS_ACTIVE && --count) 2602 DELAY(10); 2603 if (count == 0) { 2604 device_printf(sc->dev, "command queue timeout\n"); 2605 return; 2606 } 2607 2608 /* 2609 * Start the multicast setup command. 2610 */ 2611 fxp_scb_wait(sc); 2612 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2613 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2615 2616 ifp->if_timer = 2; 2617 return; 2618} 2619 2620static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2621static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2622static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2623static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2624static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2625static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2626 2627#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2628 2629struct ucode { 2630 uint32_t revision; 2631 uint32_t *ucode; 2632 int length; 2633 u_short int_delay_offset; 2634 u_short bundle_max_offset; 2635} ucode_table[] = { 2636 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2637 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2638 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2639 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2641 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2643 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2644 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2645 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2646 { 0, NULL, 0, 0, 0 } 2647}; 2648 2649static void 2650fxp_load_ucode(struct fxp_softc *sc) 2651{ 2652 struct ucode *uc; 2653 struct fxp_cb_ucode *cbp; 2654 int i; 2655 2656 for (uc = ucode_table; uc->ucode != NULL; uc++) 2657 if (sc->revision == uc->revision) 2658 break; 2659 if (uc->ucode == NULL) 2660 return; 2661 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2662 cbp->cb_status = 0; 2663 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2664 cbp->link_addr = 0xffffffff; /* (no) next command */ 2665 for (i = 0; i < uc->length; i++) 2666 cbp->ucode[i] = htole32(uc->ucode[i]); 2667 if (uc->int_delay_offset) 2668 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2669 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2670 if (uc->bundle_max_offset) 2671 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2672 htole16(sc->tunable_bundle_max); 2673 /* 2674 * Download the ucode to the chip. 2675 */ 2676 fxp_scb_wait(sc); 2677 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2678 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2679 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2680 /* ...and wait for it to complete. */ 2681 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2682 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2683 device_printf(sc->dev, 2684 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2685 sc->tunable_int_delay, 2686 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2687 sc->flags |= FXP_FLAG_UCODE; 2688} 2689 2690static int 2691sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2692{ 2693 int error, value; 2694 2695 value = *(int *)arg1; 2696 error = sysctl_handle_int(oidp, &value, 0, req); 2697 if (error || !req->newptr) 2698 return (error); 2699 if (value < low || value > high) 2700 return (EINVAL); 2701 *(int *)arg1 = value; 2702 return (0); 2703} 2704 2705/* 2706 * Interrupt delay is expressed in microseconds, a multiplier is used 2707 * to convert this to the appropriate clock ticks before using. 2708 */ 2709static int 2710sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2711{ 2712 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2713} 2714 2715static int 2716sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2717{ 2718 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2719} 2720