if_fxp.c revision 133524
1/*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice unmodified, this list of conditions, and the following
11 *    disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 133524 2004-08-11 21:41:25Z truckman $");
32
33/*
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/endian.h>
40#include <sys/mbuf.h>
41		/* #include <sys/mutex.h> */
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/sysctl.h>
46
47#include <net/if.h>
48#include <net/if_dl.h>
49#include <net/if_media.h>
50
51#include <net/bpf.h>
52#include <sys/sockio.h>
53#include <sys/bus.h>
54#include <machine/bus.h>
55#include <sys/rman.h>
56#include <machine/resource.h>
57
58#include <net/ethernet.h>
59#include <net/if_arp.h>
60
61#include <machine/clock.h>	/* for DELAY */
62
63#include <net/if_types.h>
64#include <net/if_vlan_var.h>
65
66#ifdef FXP_IP_CSUM_WAR
67#include <netinet/in.h>
68#include <netinet/in_systm.h>
69#include <netinet/ip.h>
70#include <machine/in_cksum.h>
71#endif
72
73#include <dev/pci/pcivar.h>
74#include <dev/pci/pcireg.h>		/* for PCIM_CMD_xxx */
75
76#include <dev/mii/mii.h>
77#include <dev/mii/miivar.h>
78
79#include <dev/fxp/if_fxpreg.h>
80#include <dev/fxp/if_fxpvar.h>
81#include <dev/fxp/rcvbundl.h>
82
83MODULE_DEPEND(fxp, pci, 1, 1, 1);
84MODULE_DEPEND(fxp, ether, 1, 1, 1);
85MODULE_DEPEND(fxp, miibus, 1, 1, 1);
86#include "miibus_if.h"
87
88/*
89 * NOTE!  On the Alpha, we have an alignment constraint.  The
90 * card DMAs the packet immediately following the RFA.  However,
91 * the first thing in the packet is a 14-byte Ethernet header.
92 * This means that the packet is misaligned.  To compensate,
93 * we actually offset the RFA 2 bytes into the cluster.  This
94 * alignes the packet after the Ethernet header at a 32-bit
95 * boundary.  HOWEVER!  This means that the RFA is misaligned!
96 */
97#define	RFA_ALIGNMENT_FUDGE	2
98
99/*
100 * Set initial transmit threshold at 64 (512 bytes). This is
101 * increased by 64 (512 bytes) at a time, to maximum of 192
102 * (1536 bytes), if an underrun occurs.
103 */
104static int tx_threshold = 64;
105
106/*
107 * The configuration byte map has several undefined fields which
108 * must be one or must be zero.  Set up a template for these bits
109 * only, (assuming a 82557 chip) leaving the actual configuration
110 * to fxp_init.
111 *
112 * See struct fxp_cb_config for the bit definitions.
113 */
114static u_char fxp_cb_config_template[] = {
115	0x0, 0x0,		/* cb_status */
116	0x0, 0x0,		/* cb_command */
117	0x0, 0x0, 0x0, 0x0,	/* link_addr */
118	0x0,	/*  0 */
119	0x0,	/*  1 */
120	0x0,	/*  2 */
121	0x0,	/*  3 */
122	0x0,	/*  4 */
123	0x0,	/*  5 */
124	0x32,	/*  6 */
125	0x0,	/*  7 */
126	0x0,	/*  8 */
127	0x0,	/*  9 */
128	0x6,	/* 10 */
129	0x0,	/* 11 */
130	0x0,	/* 12 */
131	0x0,	/* 13 */
132	0xf2,	/* 14 */
133	0x48,	/* 15 */
134	0x0,	/* 16 */
135	0x40,	/* 17 */
136	0xf0,	/* 18 */
137	0x0,	/* 19 */
138	0x3f,	/* 20 */
139	0x5	/* 21 */
140};
141
142struct fxp_ident {
143	u_int16_t	devid;
144	int16_t		revid;		/* -1 matches anything */
145	char 		*name;
146};
147
148/*
149 * Claim various Intel PCI device identifiers for this driver.  The
150 * sub-vendor and sub-device field are extensively used to identify
151 * particular variants, but we don't currently differentiate between
152 * them.
153 */
154static struct fxp_ident fxp_ident_table[] = {
155    { 0x1029,	-1,	"Intel 82559 PCI/CardBus Pro/100" },
156    { 0x1030,	-1,	"Intel 82559 Pro/100 Ethernet" },
157    { 0x1031,	-1,	"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
158    { 0x1032,	-1,	"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
159    { 0x1033,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
160    { 0x1034,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
161    { 0x1035,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
162    { 0x1036,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
163    { 0x1037,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
164    { 0x1038,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165    { 0x1039,	-1,	"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
166    { 0x103A,	-1,	"Intel 82801DB (ICH4) Pro/100 Ethernet" },
167    { 0x103B,	-1,	"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
168    { 0x103C,	-1,	"Intel 82801DB (ICH4) Pro/100 Ethernet" },
169    { 0x103D,	-1,	"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
170    { 0x103E,	-1,	"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
171    { 0x1050,	-1,	"Intel 82801BA (D865) Pro/100 VE Ethernet" },
172    { 0x1051,	-1,	"Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
173    { 0x1059,	-1,	"Intel 82551QM Pro/100 M Mobile Connection" },
174    { 0x1209,	-1,	"Intel 82559ER Embedded 10/100 Ethernet" },
175    { 0x1229,	0x01,	"Intel 82557 Pro/100 Ethernet" },
176    { 0x1229,	0x02,	"Intel 82557 Pro/100 Ethernet" },
177    { 0x1229,	0x03,	"Intel 82557 Pro/100 Ethernet" },
178    { 0x1229,	0x04,	"Intel 82558 Pro/100 Ethernet" },
179    { 0x1229,	0x05,	"Intel 82558 Pro/100 Ethernet" },
180    { 0x1229,	0x06,	"Intel 82559 Pro/100 Ethernet" },
181    { 0x1229,	0x07,	"Intel 82559 Pro/100 Ethernet" },
182    { 0x1229,	0x08,	"Intel 82559 Pro/100 Ethernet" },
183    { 0x1229,	0x09,	"Intel 82559ER Pro/100 Ethernet" },
184    { 0x1229,	0x0c,	"Intel 82550 Pro/100 Ethernet" },
185    { 0x1229,	0x0d,	"Intel 82550 Pro/100 Ethernet" },
186    { 0x1229,	0x0e,	"Intel 82550 Pro/100 Ethernet" },
187    { 0x1229,	0x0f,	"Intel 82551 Pro/100 Ethernet" },
188    { 0x1229,	0x10,	"Intel 82551 Pro/100 Ethernet" },
189    { 0x1229,	-1,	"Intel 82557/8/9 Pro/100 Ethernet" },
190    { 0x2449,	-1,	"Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
191    { 0,	-1,	NULL },
192};
193
194#ifdef FXP_IP_CSUM_WAR
195#define FXP_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
196#else
197#define FXP_CSUM_FEATURES    (CSUM_TCP | CSUM_UDP)
198#endif
199
200static int		fxp_probe(device_t dev);
201static int		fxp_attach(device_t dev);
202static int		fxp_detach(device_t dev);
203static int		fxp_shutdown(device_t dev);
204static int		fxp_suspend(device_t dev);
205static int		fxp_resume(device_t dev);
206
207static void		fxp_intr(void *xsc);
208static void		fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
209			    u_int8_t statack, int count);
210static void 		fxp_init(void *xsc);
211static void 		fxp_init_body(struct fxp_softc *sc);
212static void 		fxp_tick(void *xsc);
213static void 		fxp_start(struct ifnet *ifp);
214static void 		fxp_start_body(struct ifnet *ifp);
215static void		fxp_stop(struct fxp_softc *sc);
216static void 		fxp_release(struct fxp_softc *sc);
217static int		fxp_ioctl(struct ifnet *ifp, u_long command,
218			    caddr_t data);
219static void 		fxp_watchdog(struct ifnet *ifp);
220static int		fxp_add_rfabuf(struct fxp_softc *sc,
221    			    struct fxp_rx *rxp);
222static int		fxp_mc_addrs(struct fxp_softc *sc);
223static void		fxp_mc_setup(struct fxp_softc *sc);
224static u_int16_t	fxp_eeprom_getword(struct fxp_softc *sc, int offset,
225			    int autosize);
226static void 		fxp_eeprom_putword(struct fxp_softc *sc, int offset,
227			    u_int16_t data);
228static void		fxp_autosize_eeprom(struct fxp_softc *sc);
229static void		fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
230			    int offset, int words);
231static void		fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
232			    int offset, int words);
233static int		fxp_ifmedia_upd(struct ifnet *ifp);
234static void		fxp_ifmedia_sts(struct ifnet *ifp,
235			    struct ifmediareq *ifmr);
236static int		fxp_serial_ifmedia_upd(struct ifnet *ifp);
237static void		fxp_serial_ifmedia_sts(struct ifnet *ifp,
238			    struct ifmediareq *ifmr);
239static volatile int	fxp_miibus_readreg(device_t dev, int phy, int reg);
240static void		fxp_miibus_writereg(device_t dev, int phy, int reg,
241			    int value);
242static void		fxp_load_ucode(struct fxp_softc *sc);
243static int		sysctl_int_range(SYSCTL_HANDLER_ARGS,
244			    int low, int high);
245static int		sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
246static int		sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
247static void 		fxp_scb_wait(struct fxp_softc *sc);
248static void		fxp_scb_cmd(struct fxp_softc *sc, int cmd);
249static void		fxp_dma_wait(struct fxp_softc *sc,
250    			    volatile u_int16_t *status, bus_dma_tag_t dmat,
251			    bus_dmamap_t map);
252
253static device_method_t fxp_methods[] = {
254	/* Device interface */
255	DEVMETHOD(device_probe,		fxp_probe),
256	DEVMETHOD(device_attach,	fxp_attach),
257	DEVMETHOD(device_detach,	fxp_detach),
258	DEVMETHOD(device_shutdown,	fxp_shutdown),
259	DEVMETHOD(device_suspend,	fxp_suspend),
260	DEVMETHOD(device_resume,	fxp_resume),
261
262	/* MII interface */
263	DEVMETHOD(miibus_readreg,	fxp_miibus_readreg),
264	DEVMETHOD(miibus_writereg,	fxp_miibus_writereg),
265
266	{ 0, 0 }
267};
268
269static driver_t fxp_driver = {
270	"fxp",
271	fxp_methods,
272	sizeof(struct fxp_softc),
273};
274
275static devclass_t fxp_devclass;
276
277DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
278DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
279DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
280
281/*
282 * Wait for the previous command to be accepted (but not necessarily
283 * completed).
284 */
285static void
286fxp_scb_wait(struct fxp_softc *sc)
287{
288	int i = 10000;
289
290	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
291		DELAY(2);
292	if (i == 0)
293		device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
294		    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
295		    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
296		    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
297		    CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
298}
299
300static void
301fxp_scb_cmd(struct fxp_softc *sc, int cmd)
302{
303
304	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
305		CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
306		fxp_scb_wait(sc);
307	}
308	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
309}
310
311static void
312fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status,
313    bus_dma_tag_t dmat, bus_dmamap_t map)
314{
315	int i = 10000;
316
317	bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
318	while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) {
319		DELAY(2);
320		bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
321	}
322	if (i == 0)
323		device_printf(sc->dev, "DMA timeout\n");
324}
325
326/*
327 * Return identification string if this device is ours.
328 */
329static int
330fxp_probe(device_t dev)
331{
332	u_int16_t devid;
333	u_int8_t revid;
334	struct fxp_ident *ident;
335
336	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
337		devid = pci_get_device(dev);
338		revid = pci_get_revid(dev);
339		for (ident = fxp_ident_table; ident->name != NULL; ident++) {
340			if (ident->devid == devid &&
341			    (ident->revid == revid || ident->revid == -1)) {
342				device_set_desc(dev, ident->name);
343				return (0);
344			}
345		}
346	}
347	return (ENXIO);
348}
349
350static void
351fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
352{
353	u_int32_t *addr;
354
355	if (error)
356		return;
357
358	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
359	addr = arg;
360	*addr = segs->ds_addr;
361}
362
363static int
364fxp_attach(device_t dev)
365{
366	int error = 0;
367	struct fxp_softc *sc = device_get_softc(dev);
368	struct ifnet *ifp;
369	struct fxp_rx *rxp;
370	u_int32_t val;
371	u_int16_t data, myea[ETHER_ADDR_LEN / 2];
372	int i, rid, m1, m2, prefer_iomap, maxtxseg;
373	int s;
374
375	sc->dev = dev;
376	callout_init(&sc->stat_ch, CALLOUT_MPSAFE);
377	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
378	    MTX_DEF);
379	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
380	    fxp_serial_ifmedia_sts);
381
382	s = splimp();
383
384	/*
385	 * Enable bus mastering.
386	 */
387	pci_enable_busmaster(dev);
388	val = pci_read_config(dev, PCIR_COMMAND, 2);
389
390	/*
391	 * Figure out which we should try first - memory mapping or i/o mapping?
392	 * We default to memory mapping. Then we accept an override from the
393	 * command line. Then we check to see which one is enabled.
394	 */
395	m1 = PCIM_CMD_MEMEN;
396	m2 = PCIM_CMD_PORTEN;
397	prefer_iomap = 0;
398	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
399	    "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
400		m1 = PCIM_CMD_PORTEN;
401		m2 = PCIM_CMD_MEMEN;
402	}
403
404	sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
405	sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
406	sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE);
407	if (sc->mem == NULL) {
408		sc->rtp =
409		    (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
410		sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
411		sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
412                                            RF_ACTIVE);
413	}
414
415	if (!sc->mem) {
416		error = ENXIO;
417		goto fail;
418        }
419	if (bootverbose) {
420		device_printf(dev, "using %s space register mapping\n",
421		   sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
422	}
423
424	sc->sc_st = rman_get_bustag(sc->mem);
425	sc->sc_sh = rman_get_bushandle(sc->mem);
426
427	/*
428	 * Allocate our interrupt.
429	 */
430	rid = 0;
431	sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
432				 RF_SHAREABLE | RF_ACTIVE);
433	if (sc->irq == NULL) {
434		device_printf(dev, "could not map interrupt\n");
435		error = ENXIO;
436		goto fail;
437	}
438
439	/*
440	 * Reset to a stable state.
441	 */
442	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
443	DELAY(10);
444
445	/*
446	 * Find out how large of an SEEPROM we have.
447	 */
448	fxp_autosize_eeprom(sc);
449
450	/*
451	 * Determine whether we must use the 503 serial interface.
452	 */
453	fxp_read_eeprom(sc, &data, 6, 1);
454	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
455	    (data & FXP_PHY_SERIAL_ONLY))
456		sc->flags |= FXP_FLAG_SERIAL_MEDIA;
457
458	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
459	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
460	    OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
461	    &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
462	    "FXP driver receive interrupt microcode bundling delay");
463	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
464	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
465	    OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
466	    &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
467	    "FXP driver receive interrupt microcode bundle size limit");
468	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
469	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
470	    OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
471	    "FXP RNR events");
472	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
473	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
474	    OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0,
475	    "FXP flow control disabled");
476
477	/*
478	 * Pull in device tunables.
479	 */
480	sc->tunable_int_delay = TUNABLE_INT_DELAY;
481	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
482	sc->tunable_noflow = 0;
483	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
484	    "int_delay", &sc->tunable_int_delay);
485	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
486	    "bundle_max", &sc->tunable_bundle_max);
487	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
488	    "noflow", &sc->tunable_noflow);
489	sc->rnr = 0;
490
491	/*
492	 * Find out the chip revision; lump all 82557 revs together.
493	 */
494	fxp_read_eeprom(sc, &data, 5, 1);
495	if ((data >> 8) == 1)
496		sc->revision = FXP_REV_82557;
497	else
498		sc->revision = pci_get_revid(dev);
499
500	/*
501	 * Enable workarounds for certain chip revision deficiencies.
502	 *
503	 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
504	 * some systems based a normal 82559 design, have a defect where
505	 * the chip can cause a PCI protocol violation if it receives
506	 * a CU_RESUME command when it is entering the IDLE state.  The
507	 * workaround is to disable Dynamic Standby Mode, so the chip never
508	 * deasserts CLKRUN#, and always remains in an active state.
509	 *
510	 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
511	 */
512	i = pci_get_device(dev);
513	if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
514	    sc->revision >= FXP_REV_82559_A0) {
515		fxp_read_eeprom(sc, &data, 10, 1);
516		if (data & 0x02) {			/* STB enable */
517			u_int16_t cksum;
518			int i;
519
520			device_printf(dev,
521			    "Disabling dynamic standby mode in EEPROM\n");
522			data &= ~0x02;
523			fxp_write_eeprom(sc, &data, 10, 1);
524			device_printf(dev, "New EEPROM ID: 0x%x\n", data);
525			cksum = 0;
526			for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
527				fxp_read_eeprom(sc, &data, i, 1);
528				cksum += data;
529			}
530			i = (1 << sc->eeprom_size) - 1;
531			cksum = 0xBABA - cksum;
532			fxp_read_eeprom(sc, &data, i, 1);
533			fxp_write_eeprom(sc, &cksum, i, 1);
534			device_printf(dev,
535			    "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
536			    i, data, cksum);
537#if 1
538			/*
539			 * If the user elects to continue, try the software
540			 * workaround, as it is better than nothing.
541			 */
542			sc->flags |= FXP_FLAG_CU_RESUME_BUG;
543#endif
544		}
545	}
546
547	/*
548	 * If we are not a 82557 chip, we can enable extended features.
549	 */
550	if (sc->revision != FXP_REV_82557) {
551		/*
552		 * If MWI is enabled in the PCI configuration, and there
553		 * is a valid cacheline size (8 or 16 dwords), then tell
554		 * the board to turn on MWI.
555		 */
556		if (val & PCIM_CMD_MWRICEN &&
557		    pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
558			sc->flags |= FXP_FLAG_MWI_ENABLE;
559
560		/* turn on the extended TxCB feature */
561		sc->flags |= FXP_FLAG_EXT_TXCB;
562
563		/* enable reception of long frames for VLAN */
564		sc->flags |= FXP_FLAG_LONG_PKT_EN;
565	} else {
566		/* a hack to get long VLAN frames on a 82557 */
567		sc->flags |= FXP_FLAG_SAVE_BAD;
568	}
569
570	/*
571	 * Enable use of extended RFDs and TCBs for 82550
572	 * and later chips. Note: we need extended TXCB support
573	 * too, but that's already enabled by the code above.
574	 * Be careful to do this only on the right devices.
575	 */
576
577	if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) {
578		sc->rfa_size = sizeof (struct fxp_rfa);
579		sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
580		sc->flags |= FXP_FLAG_EXT_RFA;
581	} else {
582		sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
583		sc->tx_cmd = FXP_CB_COMMAND_XMIT;
584	}
585
586	/*
587	 * Allocate DMA tags and DMA safe memory.
588	 */
589	maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG;
590	error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT,
591	    BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg,
592	    maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag);
593	if (error) {
594		device_printf(dev, "could not allocate dma tag\n");
595		goto fail;
596	}
597
598	error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
599	    BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1,
600	    sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant,
601	    &sc->fxp_stag);
602	if (error) {
603		device_printf(dev, "could not allocate dma tag\n");
604		goto fail;
605	}
606
607	error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
608	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
609	if (error)
610		goto fail;
611	error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
612	    sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
613	if (error) {
614		device_printf(dev, "could not map the stats buffer\n");
615		goto fail;
616	}
617
618	error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
619	    BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1,
620	    FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag);
621	if (error) {
622		device_printf(dev, "could not allocate dma tag\n");
623		goto fail;
624	}
625
626	error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
627	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
628	if (error)
629		goto fail;
630
631	error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
632	    sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
633	    &sc->fxp_desc.cbl_addr, 0);
634	if (error) {
635		device_printf(dev, "could not map DMA memory\n");
636		goto fail;
637	}
638
639	error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
640	    BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1,
641	    sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant,
642	    &sc->mcs_tag);
643	if (error) {
644		device_printf(dev, "could not allocate dma tag\n");
645		goto fail;
646	}
647
648	error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
649	    BUS_DMA_NOWAIT, &sc->mcs_map);
650	if (error)
651		goto fail;
652	error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
653	    sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
654	if (error) {
655		device_printf(dev, "can't map the multicast setup command\n");
656		goto fail;
657	}
658
659	/*
660	 * Pre-allocate the TX DMA maps.
661	 */
662	for (i = 0; i < FXP_NTXCB; i++) {
663		error = bus_dmamap_create(sc->fxp_mtag, 0,
664		    &sc->fxp_desc.tx_list[i].tx_map);
665		if (error) {
666			device_printf(dev, "can't create DMA map for TX\n");
667			goto fail;
668		}
669	}
670	error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
671	if (error) {
672		device_printf(dev, "can't create spare DMA map\n");
673		goto fail;
674	}
675
676	/*
677	 * Pre-allocate our receive buffers.
678	 */
679	sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
680	for (i = 0; i < FXP_NRFABUFS; i++) {
681		rxp = &sc->fxp_desc.rx_list[i];
682		error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
683		if (error) {
684			device_printf(dev, "can't create DMA map for RX\n");
685			goto fail;
686		}
687		if (fxp_add_rfabuf(sc, rxp) != 0) {
688			error = ENOMEM;
689			goto fail;
690		}
691	}
692
693	/*
694	 * Read MAC address.
695	 */
696	fxp_read_eeprom(sc, myea, 0, 3);
697	sc->arpcom.ac_enaddr[0] = myea[0] & 0xff;
698	sc->arpcom.ac_enaddr[1] = myea[0] >> 8;
699	sc->arpcom.ac_enaddr[2] = myea[1] & 0xff;
700	sc->arpcom.ac_enaddr[3] = myea[1] >> 8;
701	sc->arpcom.ac_enaddr[4] = myea[2] & 0xff;
702	sc->arpcom.ac_enaddr[5] = myea[2] >> 8;
703	if (bootverbose) {
704		device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
705		    pci_get_vendor(dev), pci_get_device(dev),
706		    pci_get_subvendor(dev), pci_get_subdevice(dev),
707		    pci_get_revid(dev));
708		fxp_read_eeprom(sc, &data, 10, 1);
709		device_printf(dev, "Dynamic Standby mode is %s\n",
710		    data & 0x02 ? "enabled" : "disabled");
711	}
712
713	/*
714	 * If this is only a 10Mbps device, then there is no MII, and
715	 * the PHY will use a serial interface instead.
716	 *
717	 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
718	 * doesn't have a programming interface of any sort.  The
719	 * media is sensed automatically based on how the link partner
720	 * is configured.  This is, in essence, manual configuration.
721	 */
722	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
723		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
724		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
725	} else {
726		if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
727		    fxp_ifmedia_sts)) {
728	                device_printf(dev, "MII without any PHY!\n");
729			error = ENXIO;
730			goto fail;
731		}
732	}
733
734	ifp = &sc->arpcom.ac_if;
735	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
736	ifp->if_baudrate = 100000000;
737	ifp->if_init = fxp_init;
738	ifp->if_softc = sc;
739	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
740	ifp->if_ioctl = fxp_ioctl;
741	ifp->if_start = fxp_start;
742	ifp->if_watchdog = fxp_watchdog;
743
744	ifp->if_capabilities = ifp->if_capenable = 0;
745
746	/* Enable checksum offload for 82550 or better chips */
747	if (sc->flags & FXP_FLAG_EXT_RFA) {
748		ifp->if_hwassist = FXP_CSUM_FEATURES;
749		ifp->if_capabilities |= IFCAP_HWCSUM;
750		ifp->if_capenable |= IFCAP_HWCSUM;
751	}
752
753#ifdef DEVICE_POLLING
754	/* Inform the world we support polling. */
755	ifp->if_capabilities |= IFCAP_POLLING;
756	ifp->if_capenable |= IFCAP_POLLING;
757#endif
758
759	/*
760	 * Attach the interface.
761	 */
762	ether_ifattach(ifp, sc->arpcom.ac_enaddr);
763
764	/*
765	 * Tell the upper layer(s) we support long frames.
766	 * Must appear after the call to ether_ifattach() because
767	 * ether_ifattach() sets ifi_hdrlen to the default value.
768	 */
769	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
770	ifp->if_capabilities |= IFCAP_VLAN_MTU;
771	ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
772
773	/*
774	 * Let the system queue as many packets as we have available
775	 * TX descriptors.
776	 */
777	IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
778	ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
779	IFQ_SET_READY(&ifp->if_snd);
780
781	/*
782	 * Hook our interrupt after all initialization is complete.
783	 * XXX This driver has been tested with the INTR_MPSAFFE flag set
784	 * however, ifp and its functions are not fully locked so MPSAFE
785	 * should not be used unless you can handle potential data loss.
786	 */
787	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
788			       fxp_intr, sc, &sc->ih);
789	if (error) {
790		device_printf(dev, "could not setup irq\n");
791		ether_ifdetach(&sc->arpcom.ac_if);
792		goto fail;
793	}
794
795fail:
796	splx(s);
797	if (error)
798		fxp_release(sc);
799	return (error);
800}
801
802/*
803 * Release all resources.  The softc lock should not be held and the
804 * interrupt should already be torn down.
805 */
806static void
807fxp_release(struct fxp_softc *sc)
808{
809	struct fxp_rx *rxp;
810	struct fxp_tx *txp;
811	int i;
812
813	FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
814	KASSERT(sc->ih == NULL,
815	    ("fxp_release() called with intr handle still active"));
816	if (sc->miibus)
817		device_delete_child(sc->dev, sc->miibus);
818	bus_generic_detach(sc->dev);
819	ifmedia_removeall(&sc->sc_media);
820	if (sc->fxp_desc.cbl_list) {
821		bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
822		bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
823		    sc->cbl_map);
824	}
825	if (sc->fxp_stats) {
826		bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
827		bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
828	}
829	if (sc->mcsp) {
830		bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
831		bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
832	}
833	if (sc->irq)
834		bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
835	if (sc->mem)
836		bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
837	if (sc->fxp_mtag) {
838		for (i = 0; i < FXP_NRFABUFS; i++) {
839			rxp = &sc->fxp_desc.rx_list[i];
840			if (rxp->rx_mbuf != NULL) {
841				bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
842				    BUS_DMASYNC_POSTREAD);
843				bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
844				m_freem(rxp->rx_mbuf);
845			}
846			bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
847		}
848		bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
849		bus_dma_tag_destroy(sc->fxp_mtag);
850	}
851	if (sc->fxp_stag) {
852		for (i = 0; i < FXP_NTXCB; i++) {
853			txp = &sc->fxp_desc.tx_list[i];
854			if (txp->tx_mbuf != NULL) {
855				bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
856				    BUS_DMASYNC_POSTWRITE);
857				bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
858				m_freem(txp->tx_mbuf);
859			}
860			bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
861		}
862		bus_dma_tag_destroy(sc->fxp_stag);
863	}
864	if (sc->cbl_tag)
865		bus_dma_tag_destroy(sc->cbl_tag);
866	if (sc->mcs_tag)
867		bus_dma_tag_destroy(sc->mcs_tag);
868
869	mtx_destroy(&sc->sc_mtx);
870}
871
872/*
873 * Detach interface.
874 */
875static int
876fxp_detach(device_t dev)
877{
878	struct fxp_softc *sc = device_get_softc(dev);
879	int s;
880
881	FXP_LOCK(sc);
882	s = splimp();
883
884	sc->suspended = 1;	/* Do same thing as we do for suspend */
885	/*
886	 * Close down routes etc.
887	 */
888	ether_ifdetach(&sc->arpcom.ac_if);
889
890	/*
891	 * Stop DMA and drop transmit queue, but disable interrupts first.
892	 */
893	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
894	fxp_stop(sc);
895	FXP_UNLOCK(sc);
896
897	/*
898	 * Unhook interrupt before dropping lock. This is to prevent
899	 * races with fxp_intr().
900	 */
901	bus_teardown_intr(sc->dev, sc->irq, sc->ih);
902	sc->ih = NULL;
903
904	splx(s);
905
906	/* Release our allocated resources. */
907	fxp_release(sc);
908	return (0);
909}
910
911/*
912 * Device shutdown routine. Called at system shutdown after sync. The
913 * main purpose of this routine is to shut off receiver DMA so that
914 * kernel memory doesn't get clobbered during warmboot.
915 */
916static int
917fxp_shutdown(device_t dev)
918{
919	/*
920	 * Make sure that DMA is disabled prior to reboot. Not doing
921	 * do could allow DMA to corrupt kernel memory during the
922	 * reboot before the driver initializes.
923	 */
924	fxp_stop((struct fxp_softc *) device_get_softc(dev));
925	return (0);
926}
927
928/*
929 * Device suspend routine.  Stop the interface and save some PCI
930 * settings in case the BIOS doesn't restore them properly on
931 * resume.
932 */
933static int
934fxp_suspend(device_t dev)
935{
936	struct fxp_softc *sc = device_get_softc(dev);
937	int i, s;
938
939	FXP_LOCK(sc);
940	s = splimp();
941
942	fxp_stop(sc);
943
944	for (i = 0; i < 5; i++)
945		sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
946	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
947	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
948	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
949	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
950
951	sc->suspended = 1;
952
953	FXP_UNLOCK(sc);
954	splx(s);
955	return (0);
956}
957
958/*
959 * Device resume routine.  Restore some PCI settings in case the BIOS
960 * doesn't, re-enable busmastering, and restart the interface if
961 * appropriate.
962 */
963static int
964fxp_resume(device_t dev)
965{
966	struct fxp_softc *sc = device_get_softc(dev);
967	struct ifnet *ifp = &sc->sc_if;
968	u_int16_t pci_command;
969	int i, s;
970
971	FXP_LOCK(sc);
972	s = splimp();
973
974	/* better way to do this? */
975	for (i = 0; i < 5; i++)
976		pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
977	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
978	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
979	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
980	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
981
982	/* reenable busmastering */
983	pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
984	pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
985	pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
986
987	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
988	DELAY(10);
989
990	/* reinitialize interface if necessary */
991	if (ifp->if_flags & IFF_UP)
992		fxp_init_body(sc);
993
994	sc->suspended = 0;
995
996	FXP_UNLOCK(sc);
997	splx(s);
998	return (0);
999}
1000
1001static void
1002fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1003{
1004	u_int16_t reg;
1005	int x;
1006
1007	/*
1008	 * Shift in data.
1009	 */
1010	for (x = 1 << (length - 1); x; x >>= 1) {
1011		if (data & x)
1012			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1013		else
1014			reg = FXP_EEPROM_EECS;
1015		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1016		DELAY(1);
1017		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1018		DELAY(1);
1019		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1020		DELAY(1);
1021	}
1022}
1023
1024/*
1025 * Read from the serial EEPROM. Basically, you manually shift in
1026 * the read opcode (one bit at a time) and then shift in the address,
1027 * and then you shift out the data (all of this one bit at a time).
1028 * The word size is 16 bits, so you have to provide the address for
1029 * every 16 bits of data.
1030 */
1031static u_int16_t
1032fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1033{
1034	u_int16_t reg, data;
1035	int x;
1036
1037	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1038	/*
1039	 * Shift in read opcode.
1040	 */
1041	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1042	/*
1043	 * Shift in address.
1044	 */
1045	data = 0;
1046	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1047		if (offset & x)
1048			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1049		else
1050			reg = FXP_EEPROM_EECS;
1051		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1052		DELAY(1);
1053		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1054		DELAY(1);
1055		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1056		DELAY(1);
1057		reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1058		data++;
1059		if (autosize && reg == 0) {
1060			sc->eeprom_size = data;
1061			break;
1062		}
1063	}
1064	/*
1065	 * Shift out data.
1066	 */
1067	data = 0;
1068	reg = FXP_EEPROM_EECS;
1069	for (x = 1 << 15; x; x >>= 1) {
1070		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1071		DELAY(1);
1072		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1073			data |= x;
1074		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1075		DELAY(1);
1076	}
1077	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1078	DELAY(1);
1079
1080	return (data);
1081}
1082
1083static void
1084fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1085{
1086	int i;
1087
1088	/*
1089	 * Erase/write enable.
1090	 */
1091	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1092	fxp_eeprom_shiftin(sc, 0x4, 3);
1093	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1094	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1095	DELAY(1);
1096	/*
1097	 * Shift in write opcode, address, data.
1098	 */
1099	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1100	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1101	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1102	fxp_eeprom_shiftin(sc, data, 16);
1103	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1104	DELAY(1);
1105	/*
1106	 * Wait for EEPROM to finish up.
1107	 */
1108	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1109	DELAY(1);
1110	for (i = 0; i < 1000; i++) {
1111		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1112			break;
1113		DELAY(50);
1114	}
1115	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1116	DELAY(1);
1117	/*
1118	 * Erase/write disable.
1119	 */
1120	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1121	fxp_eeprom_shiftin(sc, 0x4, 3);
1122	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1123	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1124	DELAY(1);
1125}
1126
1127/*
1128 * From NetBSD:
1129 *
1130 * Figure out EEPROM size.
1131 *
1132 * 559's can have either 64-word or 256-word EEPROMs, the 558
1133 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1134 * talks about the existance of 16 to 256 word EEPROMs.
1135 *
1136 * The only known sizes are 64 and 256, where the 256 version is used
1137 * by CardBus cards to store CIS information.
1138 *
1139 * The address is shifted in msb-to-lsb, and after the last
1140 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1141 * after which follows the actual data. We try to detect this zero, by
1142 * probing the data-out bit in the EEPROM control register just after
1143 * having shifted in a bit. If the bit is zero, we assume we've
1144 * shifted enough address bits. The data-out should be tri-state,
1145 * before this, which should translate to a logical one.
1146 */
1147static void
1148fxp_autosize_eeprom(struct fxp_softc *sc)
1149{
1150
1151	/* guess maximum size of 256 words */
1152	sc->eeprom_size = 8;
1153
1154	/* autosize */
1155	(void) fxp_eeprom_getword(sc, 0, 1);
1156}
1157
1158static void
1159fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1160{
1161	int i;
1162
1163	for (i = 0; i < words; i++)
1164		data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1165}
1166
1167static void
1168fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1169{
1170	int i;
1171
1172	for (i = 0; i < words; i++)
1173		fxp_eeprom_putword(sc, offset + i, data[i]);
1174}
1175
1176static void
1177fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
1178    bus_size_t mapsize, int error)
1179{
1180	struct fxp_softc *sc;
1181	struct fxp_cb_tx *txp;
1182	int i;
1183
1184	if (error)
1185		return;
1186
1187	KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments"));
1188
1189	sc = arg;
1190	txp = sc->fxp_desc.tx_last->tx_next->tx_cb;
1191	for (i = 0; i < nseg; i++) {
1192		KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
1193		/*
1194		 * If this is an 82550/82551, then we're using extended
1195		 * TxCBs _and_ we're using checksum offload. This means
1196		 * that the TxCB is really an IPCB. One major difference
1197		 * between the two is that with plain extended TxCBs,
1198		 * the bottom half of the TxCB contains two entries from
1199		 * the TBD array, whereas IPCBs contain just one entry:
1200		 * one entry (8 bytes) has been sacrificed for the TCP/IP
1201		 * checksum offload control bits. So to make things work
1202		 * right, we have to start filling in the TBD array
1203		 * starting from a different place depending on whether
1204		 * the chip is an 82550/82551 or not.
1205		 */
1206		if (sc->flags & FXP_FLAG_EXT_RFA) {
1207			txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1208			txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1209		} else {
1210			txp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1211			txp->tbd[i].tb_size = htole32(segs[i].ds_len);
1212		}
1213	}
1214	txp->tbd_number = nseg;
1215}
1216
1217/*
1218 * Grab the softc lock and call the real fxp_start_body() routine
1219 */
1220static void
1221fxp_start(struct ifnet *ifp)
1222{
1223	struct fxp_softc *sc = ifp->if_softc;
1224
1225	FXP_LOCK(sc);
1226	fxp_start_body(ifp);
1227	FXP_UNLOCK(sc);
1228}
1229
1230/*
1231 * Start packet transmission on the interface.
1232 * This routine must be called with the softc lock held, and is an
1233 * internal entry point only.
1234 */
1235static void
1236fxp_start_body(struct ifnet *ifp)
1237{
1238	struct fxp_softc *sc = ifp->if_softc;
1239	struct fxp_tx *txp;
1240	struct mbuf *mb_head;
1241	int error;
1242
1243	FXP_LOCK_ASSERT(sc, MA_OWNED);
1244	/*
1245	 * See if we need to suspend xmit until the multicast filter
1246	 * has been reprogrammed (which can only be done at the head
1247	 * of the command chain).
1248	 */
1249	if (sc->need_mcsetup) {
1250		return;
1251	}
1252
1253	txp = NULL;
1254
1255	/*
1256	 * We're finished if there is nothing more to add to the list or if
1257	 * we're all filled up with buffers to transmit.
1258	 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1259	 *       a NOP command when needed.
1260	 */
1261	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1262	    sc->tx_queued < FXP_NTXCB - 1) {
1263
1264		/*
1265		 * Grab a packet to transmit.
1266		 */
1267		IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1268		if (mb_head == NULL)
1269			break;
1270
1271		/*
1272		 * Get pointer to next available tx desc.
1273		 */
1274		txp = sc->fxp_desc.tx_last->tx_next;
1275
1276		/*
1277		 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1278		 * Ethernet Controller Family Open Source Software
1279		 * Developer Manual says:
1280		 *   Using software parsing is only allowed with legal
1281		 *   TCP/IP or UDP/IP packets.
1282		 *   ...
1283		 *   For all other datagrams, hardware parsing must
1284		 *   be used.
1285		 * Software parsing appears to truncate ICMP and
1286		 * fragmented UDP packets that contain one to three
1287		 * bytes in the second (and final) mbuf of the packet.
1288		 */
1289		if (sc->flags & FXP_FLAG_EXT_RFA)
1290			txp->tx_cb->ipcb_ip_activation_high =
1291			    FXP_IPCB_HARDWAREPARSING_ENABLE;
1292
1293		/*
1294		 * Deal with TCP/IP checksum offload. Note that
1295		 * in order for TCP checksum offload to work,
1296		 * the pseudo header checksum must have already
1297		 * been computed and stored in the checksum field
1298		 * in the TCP header. The stack should have
1299		 * already done this for us.
1300		 */
1301
1302		if (mb_head->m_pkthdr.csum_flags) {
1303			if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1304				txp->tx_cb->ipcb_ip_schedule =
1305				    FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1306				if (mb_head->m_pkthdr.csum_flags & CSUM_TCP)
1307					txp->tx_cb->ipcb_ip_schedule |=
1308					    FXP_IPCB_TCP_PACKET;
1309			}
1310#ifdef FXP_IP_CSUM_WAR
1311		/*
1312		 * XXX The 82550 chip appears to have trouble
1313		 * dealing with IP header checksums in very small
1314		 * datagrams, namely fragments from 1 to 3 bytes
1315		 * in size. For example, say you want to transmit
1316		 * a UDP packet of 1473 bytes. The packet will be
1317		 * fragmented over two IP datagrams, the latter
1318		 * containing only one byte of data. The 82550 will
1319		 * botch the header checksum on the 1-byte fragment.
1320		 * As long as the datagram contains 4 or more bytes
1321		 * of data, you're ok.
1322		 *
1323                 * The following code attempts to work around this
1324		 * problem: if the datagram is less than 38 bytes
1325		 * in size (14 bytes ether header, 20 bytes IP header,
1326		 * plus 4 bytes of data), we punt and compute the IP
1327		 * header checksum by hand. This workaround doesn't
1328		 * work very well, however, since it can be fooled
1329		 * by things like VLAN tags and IP options that make
1330		 * the header sizes/offsets vary.
1331		 */
1332
1333			if (mb_head->m_pkthdr.csum_flags & CSUM_IP) {
1334				if (mb_head->m_pkthdr.len < 38) {
1335					struct ip *ip;
1336					mb_head->m_data += ETHER_HDR_LEN;
1337					ip = mtod(mb_head, struct ip *);
1338					ip->ip_sum = in_cksum(mb_head,
1339					    ip->ip_hl << 2);
1340					mb_head->m_data -= ETHER_HDR_LEN;
1341				} else {
1342					txp->tx_cb->ipcb_ip_activation_high =
1343					    FXP_IPCB_HARDWAREPARSING_ENABLE;
1344					txp->tx_cb->ipcb_ip_schedule |=
1345					    FXP_IPCB_IP_CHECKSUM_ENABLE;
1346				}
1347			}
1348#endif
1349		}
1350
1351		/*
1352		 * Go through each of the mbufs in the chain and initialize
1353		 * the transmit buffer descriptors with the physical address
1354		 * and size of the mbuf.
1355		 */
1356		error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1357		    mb_head, fxp_dma_map_txbuf, sc, 0);
1358
1359		if (error && error != EFBIG) {
1360			device_printf(sc->dev, "can't map mbuf (error %d)\n",
1361			    error);
1362			m_freem(mb_head);
1363			break;
1364		}
1365
1366		if (error) {
1367			struct mbuf *mn;
1368
1369			/*
1370			 * We ran out of segments. We have to recopy this
1371			 * mbuf chain first. Bail out if we can't get the
1372			 * new buffers.
1373			 */
1374			mn = m_defrag(mb_head, M_DONTWAIT);
1375			if (mn == NULL) {
1376				m_freem(mb_head);
1377				break;
1378			} else {
1379				mb_head = mn;
1380			}
1381			error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1382			    mb_head, fxp_dma_map_txbuf, sc, 0);
1383			if (error) {
1384				device_printf(sc->dev,
1385				    "can't map mbuf (error %d)\n", error);
1386				m_freem(mb_head);
1387				break;
1388			}
1389		}
1390
1391		bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1392		    BUS_DMASYNC_PREWRITE);
1393
1394		txp->tx_mbuf = mb_head;
1395		txp->tx_cb->cb_status = 0;
1396		txp->tx_cb->byte_count = 0;
1397		if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1398			txp->tx_cb->cb_command =
1399			    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1400			    FXP_CB_COMMAND_S);
1401		} else {
1402			txp->tx_cb->cb_command =
1403			    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1404			    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1405			/*
1406			 * Set a 5 second timer just in case we don't hear
1407			 * from the card again.
1408			 */
1409			ifp->if_timer = 5;
1410		}
1411		txp->tx_cb->tx_threshold = tx_threshold;
1412
1413		/*
1414		 * Advance the end of list forward.
1415		 */
1416
1417#ifdef __alpha__
1418		/*
1419		 * On platforms which can't access memory in 16-bit
1420		 * granularities, we must prevent the card from DMA'ing
1421		 * up the status while we update the command field.
1422		 * This could cause us to overwrite the completion status.
1423		 * XXX This is probably bogus and we're _not_ looking
1424		 * for atomicity here.
1425		 */
1426		atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1427		    htole16(FXP_CB_COMMAND_S));
1428#else
1429		sc->fxp_desc.tx_last->tx_cb->cb_command &=
1430		    htole16(~FXP_CB_COMMAND_S);
1431#endif /*__alpha__*/
1432		sc->fxp_desc.tx_last = txp;
1433
1434		/*
1435		 * Advance the beginning of the list forward if there are
1436		 * no other packets queued (when nothing is queued, tx_first
1437		 * sits on the last TxCB that was sent out).
1438		 */
1439		if (sc->tx_queued == 0)
1440			sc->fxp_desc.tx_first = txp;
1441
1442		sc->tx_queued++;
1443
1444		/*
1445		 * Pass packet to bpf if there is a listener.
1446		 */
1447		BPF_MTAP(ifp, mb_head);
1448	}
1449	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1450
1451	/*
1452	 * We're finished. If we added to the list, issue a RESUME to get DMA
1453	 * going again if suspended.
1454	 */
1455	if (txp != NULL) {
1456		fxp_scb_wait(sc);
1457		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1458	}
1459}
1460
1461#ifdef DEVICE_POLLING
1462static poll_handler_t fxp_poll;
1463
1464static void
1465fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1466{
1467	struct fxp_softc *sc = ifp->if_softc;
1468	u_int8_t statack;
1469
1470	FXP_LOCK(sc);
1471	if (!(ifp->if_capenable & IFCAP_POLLING)) {
1472		ether_poll_deregister(ifp);
1473		cmd = POLL_DEREGISTER;
1474	}
1475	if (cmd == POLL_DEREGISTER) {	/* final call, enable interrupts */
1476		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1477		FXP_UNLOCK(sc);
1478		return;
1479	}
1480	statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1481	    FXP_SCB_STATACK_FR;
1482	if (cmd == POLL_AND_CHECK_STATUS) {
1483		u_int8_t tmp;
1484
1485		tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1486		if (tmp == 0xff || tmp == 0) {
1487			FXP_UNLOCK(sc);
1488			return; /* nothing to do */
1489		}
1490		tmp &= ~statack;
1491		/* ack what we can */
1492		if (tmp != 0)
1493			CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1494		statack |= tmp;
1495	}
1496	fxp_intr_body(sc, ifp, statack, count);
1497	FXP_UNLOCK(sc);
1498}
1499#endif /* DEVICE_POLLING */
1500
1501/*
1502 * Process interface interrupts.
1503 */
1504static void
1505fxp_intr(void *xsc)
1506{
1507	struct fxp_softc *sc = xsc;
1508	struct ifnet *ifp = &sc->sc_if;
1509	u_int8_t statack;
1510
1511	FXP_LOCK(sc);
1512	if (sc->suspended) {
1513		FXP_UNLOCK(sc);
1514		return;
1515	}
1516
1517#ifdef DEVICE_POLLING
1518	if (ifp->if_flags & IFF_POLLING) {
1519		FXP_UNLOCK(sc);
1520		return;
1521	}
1522	if ((ifp->if_capenable & IFCAP_POLLING) &&
1523	    ether_poll_register(fxp_poll, ifp)) {
1524		/* disable interrupts */
1525		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1526		FXP_UNLOCK(sc);
1527		fxp_poll(ifp, 0, 1);
1528		return;
1529	}
1530#endif
1531	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1532		/*
1533		 * It should not be possible to have all bits set; the
1534		 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1535		 * all bits are set, this may indicate that the card has
1536		 * been physically ejected, so ignore it.
1537		 */
1538		if (statack == 0xff) {
1539			FXP_UNLOCK(sc);
1540			return;
1541		}
1542
1543		/*
1544		 * First ACK all the interrupts in this pass.
1545		 */
1546		CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1547		fxp_intr_body(sc, ifp, statack, -1);
1548	}
1549	FXP_UNLOCK(sc);
1550}
1551
1552static void
1553fxp_txeof(struct fxp_softc *sc)
1554{
1555	struct fxp_tx *txp;
1556
1557	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1558	for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1559	    (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1560	    txp = txp->tx_next) {
1561		if (txp->tx_mbuf != NULL) {
1562			bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1563			    BUS_DMASYNC_POSTWRITE);
1564			bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1565			m_freem(txp->tx_mbuf);
1566			txp->tx_mbuf = NULL;
1567			/* clear this to reset csum offload bits */
1568			txp->tx_cb->tbd[0].tb_addr = 0;
1569		}
1570		sc->tx_queued--;
1571	}
1572	sc->fxp_desc.tx_first = txp;
1573	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1574}
1575
1576static void
1577fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack,
1578    int count)
1579{
1580	struct mbuf *m;
1581	struct fxp_rx *rxp;
1582	struct fxp_rfa *rfa;
1583	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1584
1585	FXP_LOCK_ASSERT(sc, MA_OWNED);
1586	if (rnr)
1587		sc->rnr++;
1588#ifdef DEVICE_POLLING
1589	/* Pick up a deferred RNR condition if `count' ran out last time. */
1590	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1591		sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1592		rnr = 1;
1593	}
1594#endif
1595
1596	/*
1597	 * Free any finished transmit mbuf chains.
1598	 *
1599	 * Handle the CNA event likt a CXTNO event. It used to
1600	 * be that this event (control unit not ready) was not
1601	 * encountered, but it is now with the SMPng modifications.
1602	 * The exact sequence of events that occur when the interface
1603	 * is brought up are different now, and if this event
1604	 * goes unhandled, the configuration/rxfilter setup sequence
1605	 * can stall for several seconds. The result is that no
1606	 * packets go out onto the wire for about 5 to 10 seconds
1607	 * after the interface is ifconfig'ed for the first time.
1608	 */
1609	if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1610		fxp_txeof(sc);
1611
1612		ifp->if_timer = 0;
1613		if (sc->tx_queued == 0) {
1614			if (sc->need_mcsetup)
1615				fxp_mc_setup(sc);
1616		}
1617		/*
1618		 * Try to start more packets transmitting.
1619		 */
1620		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1621			fxp_start_body(ifp);
1622	}
1623
1624	/*
1625	 * Just return if nothing happened on the receive side.
1626	 */
1627	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1628		return;
1629
1630	/*
1631	 * Process receiver interrupts. If a no-resource (RNR)
1632	 * condition exists, get whatever packets we can and
1633	 * re-start the receiver.
1634	 *
1635	 * When using polling, we do not process the list to completion,
1636	 * so when we get an RNR interrupt we must defer the restart
1637	 * until we hit the last buffer with the C bit set.
1638	 * If we run out of cycles and rfa_headm has the C bit set,
1639	 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1640	 * that the info will be used in the subsequent polling cycle.
1641	 */
1642	for (;;) {
1643		rxp = sc->fxp_desc.rx_head;
1644		m = rxp->rx_mbuf;
1645		rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1646		    RFA_ALIGNMENT_FUDGE);
1647		bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1648		    BUS_DMASYNC_POSTREAD);
1649
1650#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1651		if (count >= 0 && count-- == 0) {
1652			if (rnr) {
1653				/* Defer RNR processing until the next time. */
1654				sc->flags |= FXP_FLAG_DEFERRED_RNR;
1655				rnr = 0;
1656			}
1657			break;
1658		}
1659#endif /* DEVICE_POLLING */
1660
1661		if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0)
1662			break;
1663
1664		/*
1665		 * Advance head forward.
1666		 */
1667		sc->fxp_desc.rx_head = rxp->rx_next;
1668
1669		/*
1670		 * Add a new buffer to the receive chain.
1671		 * If this fails, the old buffer is recycled
1672		 * instead.
1673		 */
1674		if (fxp_add_rfabuf(sc, rxp) == 0) {
1675			int total_len;
1676
1677			/*
1678			 * Fetch packet length (the top 2 bits of
1679			 * actual_size are flags set by the controller
1680			 * upon completion), and drop the packet in case
1681			 * of bogus length or CRC errors.
1682			 */
1683			total_len = le16toh(rfa->actual_size) & 0x3fff;
1684			if (total_len < sizeof(struct ether_header) ||
1685			    total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1686				sc->rfa_size ||
1687			    le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) {
1688				m_freem(m);
1689				continue;
1690			}
1691
1692                        /* Do IP checksum checking. */
1693			if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) {
1694				if (rfa->rfax_csum_sts &
1695				    FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1696					m->m_pkthdr.csum_flags |=
1697					    CSUM_IP_CHECKED;
1698				if (rfa->rfax_csum_sts &
1699				    FXP_RFDX_CS_IP_CSUM_VALID)
1700					m->m_pkthdr.csum_flags |=
1701					    CSUM_IP_VALID;
1702				if ((rfa->rfax_csum_sts &
1703				    FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1704				    (rfa->rfax_csum_sts &
1705				    FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1706					m->m_pkthdr.csum_flags |=
1707					    CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1708					m->m_pkthdr.csum_data = 0xffff;
1709				}
1710			}
1711
1712			m->m_pkthdr.len = m->m_len = total_len;
1713			m->m_pkthdr.rcvif = ifp;
1714
1715			/*
1716			 * Drop locks before calling if_input() since it
1717			 * may re-enter fxp_start() in the netisr case.
1718			 * This would result in a lock reversal.  Better
1719			 * performance might be obtained by chaining all
1720			 * packets received, dropping the lock, and then
1721			 * calling if_input() on each one.
1722			 */
1723			FXP_UNLOCK(sc);
1724			(*ifp->if_input)(ifp, m);
1725			FXP_LOCK(sc);
1726		}
1727	}
1728	if (rnr) {
1729		fxp_scb_wait(sc);
1730		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1731		    sc->fxp_desc.rx_head->rx_addr);
1732		fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1733	}
1734}
1735
1736/*
1737 * Update packet in/out/collision statistics. The i82557 doesn't
1738 * allow you to access these counters without doing a fairly
1739 * expensive DMA to get _all_ of the statistics it maintains, so
1740 * we do this operation here only once per second. The statistics
1741 * counters in the kernel are updated from the previous dump-stats
1742 * DMA and then a new dump-stats DMA is started. The on-chip
1743 * counters are zeroed when the DMA completes. If we can't start
1744 * the DMA immediately, we don't wait - we just prepare to read
1745 * them again next time.
1746 */
1747static void
1748fxp_tick(void *xsc)
1749{
1750	struct fxp_softc *sc = xsc;
1751	struct ifnet *ifp = &sc->sc_if;
1752	struct fxp_stats *sp = sc->fxp_stats;
1753	int s;
1754
1755	FXP_LOCK(sc);
1756	s = splimp();
1757	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1758	ifp->if_opackets += le32toh(sp->tx_good);
1759	ifp->if_collisions += le32toh(sp->tx_total_collisions);
1760	if (sp->rx_good) {
1761		ifp->if_ipackets += le32toh(sp->rx_good);
1762		sc->rx_idle_secs = 0;
1763	} else {
1764		/*
1765		 * Receiver's been idle for another second.
1766		 */
1767		sc->rx_idle_secs++;
1768	}
1769	ifp->if_ierrors +=
1770	    le32toh(sp->rx_crc_errors) +
1771	    le32toh(sp->rx_alignment_errors) +
1772	    le32toh(sp->rx_rnr_errors) +
1773	    le32toh(sp->rx_overrun_errors);
1774	/*
1775	 * If any transmit underruns occured, bump up the transmit
1776	 * threshold by another 512 bytes (64 * 8).
1777	 */
1778	if (sp->tx_underruns) {
1779		ifp->if_oerrors += le32toh(sp->tx_underruns);
1780		if (tx_threshold < 192)
1781			tx_threshold += 64;
1782	}
1783
1784	/*
1785	 * Release any xmit buffers that have completed DMA. This isn't
1786	 * strictly necessary to do here, but it's advantagous for mbufs
1787	 * with external storage to be released in a timely manner rather
1788	 * than being defered for a potentially long time. This limits
1789	 * the delay to a maximum of one second.
1790	 */
1791	fxp_txeof(sc);
1792
1793	/*
1794	 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1795	 * then assume the receiver has locked up and attempt to clear
1796	 * the condition by reprogramming the multicast filter. This is
1797	 * a work-around for a bug in the 82557 where the receiver locks
1798	 * up if it gets certain types of garbage in the syncronization
1799	 * bits prior to the packet header. This bug is supposed to only
1800	 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1801	 * mode as well (perhaps due to a 10/100 speed transition).
1802	 */
1803	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1804		sc->rx_idle_secs = 0;
1805		fxp_mc_setup(sc);
1806	}
1807	/*
1808	 * If there is no pending command, start another stats
1809	 * dump. Otherwise punt for now.
1810	 */
1811	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1812		/*
1813		 * Start another stats dump.
1814		 */
1815		bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
1816		    BUS_DMASYNC_PREREAD);
1817		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1818	} else {
1819		/*
1820		 * A previous command is still waiting to be accepted.
1821		 * Just zero our copy of the stats and wait for the
1822		 * next timer event to update them.
1823		 */
1824		sp->tx_good = 0;
1825		sp->tx_underruns = 0;
1826		sp->tx_total_collisions = 0;
1827
1828		sp->rx_good = 0;
1829		sp->rx_crc_errors = 0;
1830		sp->rx_alignment_errors = 0;
1831		sp->rx_rnr_errors = 0;
1832		sp->rx_overrun_errors = 0;
1833	}
1834	if (sc->miibus != NULL)
1835		mii_tick(device_get_softc(sc->miibus));
1836
1837	/*
1838	 * Schedule another timeout one second from now.
1839	 */
1840	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
1841	FXP_UNLOCK(sc);
1842	splx(s);
1843}
1844
1845/*
1846 * Stop the interface. Cancels the statistics updater and resets
1847 * the interface.
1848 */
1849static void
1850fxp_stop(struct fxp_softc *sc)
1851{
1852	struct ifnet *ifp = &sc->sc_if;
1853	struct fxp_tx *txp;
1854	int i;
1855
1856	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1857	ifp->if_timer = 0;
1858
1859#ifdef DEVICE_POLLING
1860	ether_poll_deregister(ifp);
1861#endif
1862	/*
1863	 * Cancel stats updater.
1864	 */
1865	callout_stop(&sc->stat_ch);
1866
1867	/*
1868	 * Issue software reset, which also unloads the microcode.
1869	 */
1870	sc->flags &= ~FXP_FLAG_UCODE;
1871	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1872	DELAY(50);
1873
1874	/*
1875	 * Release any xmit buffers.
1876	 */
1877	txp = sc->fxp_desc.tx_list;
1878	if (txp != NULL) {
1879		for (i = 0; i < FXP_NTXCB; i++) {
1880 			if (txp[i].tx_mbuf != NULL) {
1881				bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
1882				    BUS_DMASYNC_POSTWRITE);
1883				bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
1884				m_freem(txp[i].tx_mbuf);
1885				txp[i].tx_mbuf = NULL;
1886				/* clear this to reset csum offload bits */
1887				txp[i].tx_cb->tbd[0].tb_addr = 0;
1888			}
1889		}
1890	}
1891	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1892	sc->tx_queued = 0;
1893}
1894
1895/*
1896 * Watchdog/transmission transmit timeout handler. Called when a
1897 * transmission is started on the interface, but no interrupt is
1898 * received before the timeout. This usually indicates that the
1899 * card has wedged for some reason.
1900 */
1901static void
1902fxp_watchdog(struct ifnet *ifp)
1903{
1904	struct fxp_softc *sc = ifp->if_softc;
1905
1906	FXP_LOCK(sc);
1907	device_printf(sc->dev, "device timeout\n");
1908	ifp->if_oerrors++;
1909
1910	fxp_init_body(sc);
1911	FXP_UNLOCK(sc);
1912}
1913
1914/*
1915 * Acquire locks and then call the real initialization function.  This
1916 * is necessary because ether_ioctl() calls if_init() and this would
1917 * result in mutex recursion if the mutex was held.
1918 */
1919static void
1920fxp_init(void *xsc)
1921{
1922	struct fxp_softc *sc = xsc;
1923
1924	FXP_LOCK(sc);
1925	fxp_init_body(sc);
1926	FXP_UNLOCK(sc);
1927}
1928
1929/*
1930 * Perform device initialization. This routine must be called with the
1931 * softc lock held.
1932 */
1933static void
1934fxp_init_body(struct fxp_softc *sc)
1935{
1936	struct ifnet *ifp = &sc->sc_if;
1937	struct fxp_cb_config *cbp;
1938	struct fxp_cb_ias *cb_ias;
1939	struct fxp_cb_tx *tcbp;
1940	struct fxp_tx *txp;
1941	struct fxp_cb_mcs *mcsp;
1942	int i, prm, s;
1943
1944	FXP_LOCK_ASSERT(sc, MA_OWNED);
1945	s = splimp();
1946	/*
1947	 * Cancel any pending I/O
1948	 */
1949	fxp_stop(sc);
1950
1951	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1952
1953	/*
1954	 * Initialize base of CBL and RFA memory. Loading with zero
1955	 * sets it up for regular linear addressing.
1956	 */
1957	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1958	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1959
1960	fxp_scb_wait(sc);
1961	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1962
1963	/*
1964	 * Initialize base of dump-stats buffer.
1965	 */
1966	fxp_scb_wait(sc);
1967	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
1968	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
1969	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1970
1971	/*
1972	 * Attempt to load microcode if requested.
1973	 */
1974	if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1975		fxp_load_ucode(sc);
1976
1977	/*
1978	 * Initialize the multicast address list.
1979	 */
1980	if (fxp_mc_addrs(sc)) {
1981		mcsp = sc->mcsp;
1982		mcsp->cb_status = 0;
1983		mcsp->cb_command =
1984		    htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
1985		mcsp->link_addr = 0xffffffff;
1986		/*
1987	 	 * Start the multicast setup command.
1988		 */
1989		fxp_scb_wait(sc);
1990		bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
1991		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
1992		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1993		/* ...and wait for it to complete. */
1994		fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
1995		bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
1996		    BUS_DMASYNC_POSTWRITE);
1997	}
1998
1999	/*
2000	 * We temporarily use memory that contains the TxCB list to
2001	 * construct the config CB. The TxCB list memory is rebuilt
2002	 * later.
2003	 */
2004	cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2005
2006	/*
2007	 * This bcopy is kind of disgusting, but there are a bunch of must be
2008	 * zero and must be one bits in this structure and this is the easiest
2009	 * way to initialize them all to proper values.
2010	 */
2011	bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2012
2013	cbp->cb_status =	0;
2014	cbp->cb_command =	htole16(FXP_CB_COMMAND_CONFIG |
2015	    FXP_CB_COMMAND_EL);
2016	cbp->link_addr =	0xffffffff;	/* (no) next command */
2017	cbp->byte_count =	sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2018	cbp->rx_fifo_limit =	8;	/* rx fifo threshold (32 bytes) */
2019	cbp->tx_fifo_limit =	0;	/* tx fifo threshold (0 bytes) */
2020	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
2021	cbp->mwi_enable =	sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2022	cbp->type_enable =	0;	/* actually reserved */
2023	cbp->read_align_en =	sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2024	cbp->end_wr_on_cl =	sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2025	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
2026	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
2027	cbp->dma_mbce =		0;	/* (disable) dma max counters */
2028	cbp->late_scb =		0;	/* (don't) defer SCB update */
2029	cbp->direct_dma_dis =	1;	/* disable direct rcv dma mode */
2030	cbp->tno_int_or_tco_en =0;	/* (disable) tx not okay interrupt */
2031	cbp->ci_int =		1;	/* interrupt on CU idle */
2032	cbp->ext_txcb_dis = 	sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2033	cbp->ext_stats_dis = 	1;	/* disable extended counters */
2034	cbp->keep_overrun_rx = 	0;	/* don't pass overrun frames to host */
2035	cbp->save_bf =		sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2036	cbp->disc_short_rx =	!prm;	/* discard short packets */
2037	cbp->underrun_retry =	1;	/* retry mode (once) on DMA underrun */
2038	cbp->two_frames =	0;	/* do not limit FIFO to 2 frames */
2039	cbp->dyn_tbd =		0;	/* (no) dynamic TBD mode */
2040	cbp->ext_rfa =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2041	cbp->mediatype =	sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2042	cbp->csma_dis =		0;	/* (don't) disable link */
2043	cbp->tcp_udp_cksum =	0;	/* (don't) enable checksum */
2044	cbp->vlan_tco =		0;	/* (don't) enable vlan wakeup */
2045	cbp->link_wake_en =	0;	/* (don't) assert PME# on link change */
2046	cbp->arp_wake_en =	0;	/* (don't) assert PME# on arp */
2047	cbp->mc_wake_en =	0;	/* (don't) enable PME# on mcmatch */
2048	cbp->nsai =		1;	/* (don't) disable source addr insert */
2049	cbp->preamble_length =	2;	/* (7 byte) preamble */
2050	cbp->loopback =		0;	/* (don't) loopback */
2051	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
2052	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
2053	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
2054	cbp->promiscuous =	prm;	/* promiscuous mode */
2055	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
2056	cbp->wait_after_win =	0;	/* (don't) enable modified backoff alg*/
2057	cbp->ignore_ul =	0;	/* consider U/L bit in IA matching */
2058	cbp->crc16_en =		0;	/* (don't) enable crc-16 algorithm */
2059	cbp->crscdt =		sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2060
2061	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
2062	cbp->padding =		1;	/* (do) pad short tx packets */
2063	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
2064	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2065	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
2066	cbp->magic_pkt_dis =	0;	/* (don't) disable magic packet */
2067					/* must set wake_en in PMCSR also */
2068	cbp->force_fdx =	0;	/* (don't) force full duplex */
2069	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
2070	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
2071	cbp->mc_all =		sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
2072	cbp->gamla_rx =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2073
2074	if (sc->tunable_noflow || sc->revision == FXP_REV_82557) {
2075		/*
2076		 * The 82557 has no hardware flow control, the values
2077		 * below are the defaults for the chip.
2078		 */
2079		cbp->fc_delay_lsb =	0;
2080		cbp->fc_delay_msb =	0x40;
2081		cbp->pri_fc_thresh =	3;
2082		cbp->tx_fc_dis =	0;
2083		cbp->rx_fc_restop =	0;
2084		cbp->rx_fc_restart =	0;
2085		cbp->fc_filter =	0;
2086		cbp->pri_fc_loc =	1;
2087	} else {
2088		cbp->fc_delay_lsb =	0x1f;
2089		cbp->fc_delay_msb =	0x01;
2090		cbp->pri_fc_thresh =	3;
2091		cbp->tx_fc_dis =	0;	/* enable transmit FC */
2092		cbp->rx_fc_restop =	1;	/* enable FC restop frames */
2093		cbp->rx_fc_restart =	1;	/* enable FC restart frames */
2094		cbp->fc_filter =	!prm;	/* drop FC frames to host */
2095		cbp->pri_fc_loc =	1;	/* FC pri location (byte31) */
2096	}
2097
2098	/*
2099	 * Start the config command/DMA.
2100	 */
2101	fxp_scb_wait(sc);
2102	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2103	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2104	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2105	/* ...and wait for it to complete. */
2106	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2107	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2108
2109	/*
2110	 * Now initialize the station address. Temporarily use the TxCB
2111	 * memory area like we did above for the config CB.
2112	 */
2113	cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2114	cb_ias->cb_status = 0;
2115	cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2116	cb_ias->link_addr = 0xffffffff;
2117	bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr,
2118	    sizeof(sc->arpcom.ac_enaddr));
2119
2120	/*
2121	 * Start the IAS (Individual Address Setup) command/DMA.
2122	 */
2123	fxp_scb_wait(sc);
2124	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2125	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2126	/* ...and wait for it to complete. */
2127	fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2128	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2129
2130	/*
2131	 * Initialize transmit control block (TxCB) list.
2132	 */
2133	txp = sc->fxp_desc.tx_list;
2134	tcbp = sc->fxp_desc.cbl_list;
2135	bzero(tcbp, FXP_TXCB_SZ);
2136	for (i = 0; i < FXP_NTXCB; i++) {
2137		txp[i].tx_cb = tcbp + i;
2138		txp[i].tx_mbuf = NULL;
2139		tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2140		tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2141		tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2142		    (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2143		if (sc->flags & FXP_FLAG_EXT_TXCB)
2144			tcbp[i].tbd_array_addr =
2145			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2146		else
2147			tcbp[i].tbd_array_addr =
2148			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2149		txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2150	}
2151	/*
2152	 * Set the suspend flag on the first TxCB and start the control
2153	 * unit. It will execute the NOP and then suspend.
2154	 */
2155	tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2156	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2157	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2158	sc->tx_queued = 1;
2159
2160	fxp_scb_wait(sc);
2161	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2162
2163	/*
2164	 * Initialize receiver buffer area - RFA.
2165	 */
2166	fxp_scb_wait(sc);
2167	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2168	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2169
2170	/*
2171	 * Set current media.
2172	 */
2173	if (sc->miibus != NULL)
2174		mii_mediachg(device_get_softc(sc->miibus));
2175
2176	ifp->if_flags |= IFF_RUNNING;
2177	ifp->if_flags &= ~IFF_OACTIVE;
2178
2179	/*
2180	 * Enable interrupts.
2181	 */
2182#ifdef DEVICE_POLLING
2183	/*
2184	 * ... but only do that if we are not polling. And because (presumably)
2185	 * the default is interrupts on, we need to disable them explicitly!
2186	 */
2187	if ( ifp->if_flags & IFF_POLLING )
2188		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2189	else
2190#endif /* DEVICE_POLLING */
2191	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2192
2193	/*
2194	 * Start stats updater.
2195	 */
2196	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2197	splx(s);
2198}
2199
2200static int
2201fxp_serial_ifmedia_upd(struct ifnet *ifp)
2202{
2203
2204	return (0);
2205}
2206
2207static void
2208fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2209{
2210
2211	ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2212}
2213
2214/*
2215 * Change media according to request.
2216 */
2217static int
2218fxp_ifmedia_upd(struct ifnet *ifp)
2219{
2220	struct fxp_softc *sc = ifp->if_softc;
2221	struct mii_data *mii;
2222
2223	mii = device_get_softc(sc->miibus);
2224	mii_mediachg(mii);
2225	return (0);
2226}
2227
2228/*
2229 * Notify the world which media we're using.
2230 */
2231static void
2232fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2233{
2234	struct fxp_softc *sc = ifp->if_softc;
2235	struct mii_data *mii;
2236
2237	mii = device_get_softc(sc->miibus);
2238	mii_pollstat(mii);
2239	ifmr->ifm_active = mii->mii_media_active;
2240	ifmr->ifm_status = mii->mii_media_status;
2241
2242	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
2243		sc->cu_resume_bug = 1;
2244	else
2245		sc->cu_resume_bug = 0;
2246}
2247
2248/*
2249 * Add a buffer to the end of the RFA buffer list.
2250 * Return 0 if successful, 1 for failure. A failure results in
2251 * adding the 'oldm' (if non-NULL) on to the end of the list -
2252 * tossing out its old contents and recycling it.
2253 * The RFA struct is stuck at the beginning of mbuf cluster and the
2254 * data pointer is fixed up to point just past it.
2255 */
2256static int
2257fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2258{
2259	struct mbuf *m;
2260	struct fxp_rfa *rfa, *p_rfa;
2261	struct fxp_rx *p_rx;
2262	bus_dmamap_t tmp_map;
2263	int error;
2264
2265	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2266	if (m == NULL)
2267		return (ENOBUFS);
2268
2269	/*
2270	 * Move the data pointer up so that the incoming data packet
2271	 * will be 32-bit aligned.
2272	 */
2273	m->m_data += RFA_ALIGNMENT_FUDGE;
2274
2275	/*
2276	 * Get a pointer to the base of the mbuf cluster and move
2277	 * data start past it.
2278	 */
2279	rfa = mtod(m, struct fxp_rfa *);
2280	m->m_data += sc->rfa_size;
2281	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2282
2283	rfa->rfa_status = 0;
2284	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2285	rfa->actual_size = 0;
2286
2287	/*
2288	 * Initialize the rest of the RFA.  Note that since the RFA
2289	 * is misaligned, we cannot store values directly.  We're thus
2290	 * using the le32enc() function which handles endianness and
2291	 * is also alignment-safe.
2292	 */
2293	le32enc(&rfa->link_addr, 0xffffffff);
2294	le32enc(&rfa->rbd_addr, 0xffffffff);
2295
2296	/* Map the RFA into DMA memory. */
2297	error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2298	    MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2299	    &rxp->rx_addr, 0);
2300	if (error) {
2301		m_freem(m);
2302		return (error);
2303	}
2304
2305	bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2306	tmp_map = sc->spare_map;
2307	sc->spare_map = rxp->rx_map;
2308	rxp->rx_map = tmp_map;
2309	rxp->rx_mbuf = m;
2310
2311	bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2312	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2313
2314	/*
2315	 * If there are other buffers already on the list, attach this
2316	 * one to the end by fixing up the tail to point to this one.
2317	 */
2318	if (sc->fxp_desc.rx_head != NULL) {
2319		p_rx = sc->fxp_desc.rx_tail;
2320		p_rfa = (struct fxp_rfa *)
2321		    (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2322		p_rx->rx_next = rxp;
2323		le32enc(&p_rfa->link_addr, rxp->rx_addr);
2324		p_rfa->rfa_control = 0;
2325		bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2326		    BUS_DMASYNC_PREWRITE);
2327	} else {
2328		rxp->rx_next = NULL;
2329		sc->fxp_desc.rx_head = rxp;
2330	}
2331	sc->fxp_desc.rx_tail = rxp;
2332	return (0);
2333}
2334
2335static volatile int
2336fxp_miibus_readreg(device_t dev, int phy, int reg)
2337{
2338	struct fxp_softc *sc = device_get_softc(dev);
2339	int count = 10000;
2340	int value;
2341
2342	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2343	    (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2344
2345	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2346	    && count--)
2347		DELAY(10);
2348
2349	if (count <= 0)
2350		device_printf(dev, "fxp_miibus_readreg: timed out\n");
2351
2352	return (value & 0xffff);
2353}
2354
2355static void
2356fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2357{
2358	struct fxp_softc *sc = device_get_softc(dev);
2359	int count = 10000;
2360
2361	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2362	    (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2363	    (value & 0xffff));
2364
2365	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2366	    count--)
2367		DELAY(10);
2368
2369	if (count <= 0)
2370		device_printf(dev, "fxp_miibus_writereg: timed out\n");
2371}
2372
2373static int
2374fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2375{
2376	struct fxp_softc *sc = ifp->if_softc;
2377	struct ifreq *ifr = (struct ifreq *)data;
2378	struct mii_data *mii;
2379	int flag, mask, s, error = 0;
2380
2381	/*
2382	 * Detaching causes us to call ioctl with the mutex owned.  Preclude
2383	 * that by saying we're busy if the lock is already held.
2384	 */
2385	if (FXP_LOCKED(sc))
2386		return (EBUSY);
2387
2388	FXP_LOCK(sc);
2389	s = splimp();
2390
2391	switch (command) {
2392	case SIOCSIFFLAGS:
2393		if (ifp->if_flags & IFF_ALLMULTI)
2394			sc->flags |= FXP_FLAG_ALL_MCAST;
2395		else
2396			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2397
2398		/*
2399		 * If interface is marked up and not running, then start it.
2400		 * If it is marked down and running, stop it.
2401		 * XXX If it's up then re-initialize it. This is so flags
2402		 * such as IFF_PROMISC are handled.
2403		 */
2404		if (ifp->if_flags & IFF_UP) {
2405			fxp_init_body(sc);
2406		} else {
2407			if (ifp->if_flags & IFF_RUNNING)
2408				fxp_stop(sc);
2409		}
2410		break;
2411
2412	case SIOCADDMULTI:
2413	case SIOCDELMULTI:
2414		if (ifp->if_flags & IFF_ALLMULTI)
2415			sc->flags |= FXP_FLAG_ALL_MCAST;
2416		else
2417			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2418		/*
2419		 * Multicast list has changed; set the hardware filter
2420		 * accordingly.
2421		 */
2422		if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2423			fxp_mc_setup(sc);
2424		/*
2425		 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2426		 * again rather than else {}.
2427		 */
2428		if (sc->flags & FXP_FLAG_ALL_MCAST)
2429			fxp_init_body(sc);
2430		error = 0;
2431		break;
2432
2433	case SIOCSIFMEDIA:
2434	case SIOCGIFMEDIA:
2435		if (sc->miibus != NULL) {
2436			mii = device_get_softc(sc->miibus);
2437                        error = ifmedia_ioctl(ifp, ifr,
2438                            &mii->mii_media, command);
2439		} else {
2440                        error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2441		}
2442		break;
2443
2444	case SIOCSIFCAP:
2445		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2446		if (mask & IFCAP_POLLING)
2447			ifp->if_capenable ^= IFCAP_POLLING;
2448		if (mask & IFCAP_VLAN_MTU) {
2449			ifp->if_capenable ^= IFCAP_VLAN_MTU;
2450			if (sc->revision != FXP_REV_82557)
2451				flag = FXP_FLAG_LONG_PKT_EN;
2452			else /* a hack to get long frames on the old chip */
2453				flag = FXP_FLAG_SAVE_BAD;
2454			sc->flags ^= flag;
2455			if (ifp->if_flags & IFF_UP)
2456				fxp_init_body(sc);
2457		}
2458		break;
2459
2460	default:
2461		/*
2462		 * ether_ioctl() will eventually call fxp_start() which
2463		 * will result in mutex recursion so drop it first.
2464		 */
2465		FXP_UNLOCK(sc);
2466		error = ether_ioctl(ifp, command, data);
2467	}
2468	if (FXP_LOCKED(sc))
2469		FXP_UNLOCK(sc);
2470	splx(s);
2471	return (error);
2472}
2473
2474/*
2475 * Fill in the multicast address list and return number of entries.
2476 */
2477static int
2478fxp_mc_addrs(struct fxp_softc *sc)
2479{
2480	struct fxp_cb_mcs *mcsp = sc->mcsp;
2481	struct ifnet *ifp = &sc->sc_if;
2482	struct ifmultiaddr *ifma;
2483	int nmcasts;
2484
2485	nmcasts = 0;
2486	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2487#if __FreeBSD_version < 500000
2488		LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2489#else
2490		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2491#endif
2492			if (ifma->ifma_addr->sa_family != AF_LINK)
2493				continue;
2494			if (nmcasts >= MAXMCADDR) {
2495				sc->flags |= FXP_FLAG_ALL_MCAST;
2496				nmcasts = 0;
2497				break;
2498			}
2499			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2500			    &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2501			nmcasts++;
2502		}
2503	}
2504	mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2505	return (nmcasts);
2506}
2507
2508/*
2509 * Program the multicast filter.
2510 *
2511 * We have an artificial restriction that the multicast setup command
2512 * must be the first command in the chain, so we take steps to ensure
2513 * this. By requiring this, it allows us to keep up the performance of
2514 * the pre-initialized command ring (esp. link pointers) by not actually
2515 * inserting the mcsetup command in the ring - i.e. its link pointer
2516 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2517 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2518 * lead into the regular TxCB ring when it completes.
2519 *
2520 * This function must be called at splimp.
2521 */
2522static void
2523fxp_mc_setup(struct fxp_softc *sc)
2524{
2525	struct fxp_cb_mcs *mcsp = sc->mcsp;
2526	struct ifnet *ifp = &sc->sc_if;
2527	struct fxp_tx *txp;
2528	int count;
2529
2530	FXP_LOCK_ASSERT(sc, MA_OWNED);
2531	/*
2532	 * If there are queued commands, we must wait until they are all
2533	 * completed. If we are already waiting, then add a NOP command
2534	 * with interrupt option so that we're notified when all commands
2535	 * have been completed - fxp_start() ensures that no additional
2536	 * TX commands will be added when need_mcsetup is true.
2537	 */
2538	if (sc->tx_queued) {
2539		/*
2540		 * need_mcsetup will be true if we are already waiting for the
2541		 * NOP command to be completed (see below). In this case, bail.
2542		 */
2543		if (sc->need_mcsetup)
2544			return;
2545		sc->need_mcsetup = 1;
2546
2547		/*
2548		 * Add a NOP command with interrupt so that we are notified
2549		 * when all TX commands have been processed.
2550		 */
2551		txp = sc->fxp_desc.tx_last->tx_next;
2552		txp->tx_mbuf = NULL;
2553		txp->tx_cb->cb_status = 0;
2554		txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2555		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2556		/*
2557		 * Advance the end of list forward.
2558		 */
2559		sc->fxp_desc.tx_last->tx_cb->cb_command &=
2560		    htole16(~FXP_CB_COMMAND_S);
2561		bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2562		sc->fxp_desc.tx_last = txp;
2563		sc->tx_queued++;
2564		/*
2565		 * Issue a resume in case the CU has just suspended.
2566		 */
2567		fxp_scb_wait(sc);
2568		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2569		/*
2570		 * Set a 5 second timer just in case we don't hear from the
2571		 * card again.
2572		 */
2573		ifp->if_timer = 5;
2574
2575		return;
2576	}
2577	sc->need_mcsetup = 0;
2578
2579	/*
2580	 * Initialize multicast setup descriptor.
2581	 */
2582	mcsp->cb_status = 0;
2583	mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2584	    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2585	mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2586	txp = &sc->fxp_desc.mcs_tx;
2587	txp->tx_mbuf = NULL;
2588	txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2589	txp->tx_next = sc->fxp_desc.tx_list;
2590	(void) fxp_mc_addrs(sc);
2591	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2592	sc->tx_queued = 1;
2593
2594	/*
2595	 * Wait until command unit is not active. This should never
2596	 * be the case when nothing is queued, but make sure anyway.
2597	 */
2598	count = 100;
2599	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2600	    FXP_SCB_CUS_ACTIVE && --count)
2601		DELAY(10);
2602	if (count == 0) {
2603		device_printf(sc->dev, "command queue timeout\n");
2604		return;
2605	}
2606
2607	/*
2608	 * Start the multicast setup command.
2609	 */
2610	fxp_scb_wait(sc);
2611	bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2612	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2613	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2614
2615	ifp->if_timer = 2;
2616	return;
2617}
2618
2619static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2620static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2621static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2622static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2623static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2624static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2625
2626#define UCODE(x)	x, sizeof(x)
2627
2628struct ucode {
2629	u_int32_t	revision;
2630	u_int32_t	*ucode;
2631	int		length;
2632	u_short		int_delay_offset;
2633	u_short		bundle_max_offset;
2634} ucode_table[] = {
2635	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2636	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2637	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2638	    D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2639	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2640	    D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2641	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
2642	    D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2643	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2644	    D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2645	{ 0, NULL, 0, 0, 0 }
2646};
2647
2648static void
2649fxp_load_ucode(struct fxp_softc *sc)
2650{
2651	struct ucode *uc;
2652	struct fxp_cb_ucode *cbp;
2653
2654	for (uc = ucode_table; uc->ucode != NULL; uc++)
2655		if (sc->revision == uc->revision)
2656			break;
2657	if (uc->ucode == NULL)
2658		return;
2659	cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2660	cbp->cb_status = 0;
2661	cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2662	cbp->link_addr = 0xffffffff;    	/* (no) next command */
2663	memcpy(cbp->ucode, uc->ucode, uc->length);
2664	if (uc->int_delay_offset)
2665		*(u_int16_t *)&cbp->ucode[uc->int_delay_offset] =
2666		    htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2667	if (uc->bundle_max_offset)
2668		*(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] =
2669		    htole16(sc->tunable_bundle_max);
2670	/*
2671	 * Download the ucode to the chip.
2672	 */
2673	fxp_scb_wait(sc);
2674	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2675	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2676	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2677	/* ...and wait for it to complete. */
2678	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2679	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2680	device_printf(sc->dev,
2681	    "Microcode loaded, int_delay: %d usec  bundle_max: %d\n",
2682	    sc->tunable_int_delay,
2683	    uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2684	sc->flags |= FXP_FLAG_UCODE;
2685}
2686
2687static int
2688sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2689{
2690	int error, value;
2691
2692	value = *(int *)arg1;
2693	error = sysctl_handle_int(oidp, &value, 0, req);
2694	if (error || !req->newptr)
2695		return (error);
2696	if (value < low || value > high)
2697		return (EINVAL);
2698	*(int *)arg1 = value;
2699	return (0);
2700}
2701
2702/*
2703 * Interrupt delay is expressed in microseconds, a multiplier is used
2704 * to convert this to the appropriate clock ticks before using.
2705 */
2706static int
2707sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2708{
2709	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2710}
2711
2712static int
2713sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2714{
2715	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2716}
2717