if_fxp.c revision 131255
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 131255 2004-06-28 20:26:21Z imp $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sysctl.h> 46 47#include <net/if.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50 51#include <net/bpf.h> 52#include <sys/sockio.h> 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if_arp.h> 60 61#include <machine/clock.h> /* for DELAY */ 62 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#ifdef FXP_IP_CSUM_WAR 67#include <netinet/in.h> 68#include <netinet/in_systm.h> 69#include <netinet/ip.h> 70#include <machine/in_cksum.h> 71#endif 72 73#include <dev/pci/pcivar.h> 74#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/fxp/if_fxpreg.h> 80#include <dev/fxp/if_fxpvar.h> 81#include <dev/fxp/rcvbundl.h> 82 83MODULE_DEPEND(fxp, pci, 1, 1, 1); 84MODULE_DEPEND(fxp, ether, 1, 1, 1); 85MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86#include "miibus_if.h" 87 88/* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97#define RFA_ALIGNMENT_FUDGE 2 98 99/* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104static int tx_threshold = 64; 105 106/* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140}; 141 142struct fxp_ident { 143 u_int16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146}; 147 148/* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 175 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 184 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 190 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 191 { 0, -1, NULL }, 192}; 193 194#ifdef FXP_IP_CSUM_WAR 195#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 196#else 197#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 198#endif 199 200static int fxp_probe(device_t dev); 201static int fxp_attach(device_t dev); 202static int fxp_detach(device_t dev); 203static int fxp_shutdown(device_t dev); 204static int fxp_suspend(device_t dev); 205static int fxp_resume(device_t dev); 206 207static void fxp_intr(void *xsc); 208static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 209 u_int8_t statack, int count); 210static void fxp_init(void *xsc); 211static void fxp_init_body(struct fxp_softc *sc); 212static void fxp_tick(void *xsc); 213static void fxp_start(struct ifnet *ifp); 214static void fxp_start_body(struct ifnet *ifp); 215static void fxp_stop(struct fxp_softc *sc); 216static void fxp_release(struct fxp_softc *sc); 217static int fxp_ioctl(struct ifnet *ifp, u_long command, 218 caddr_t data); 219static void fxp_watchdog(struct ifnet *ifp); 220static int fxp_add_rfabuf(struct fxp_softc *sc, 221 struct fxp_rx *rxp); 222static int fxp_mc_addrs(struct fxp_softc *sc); 223static void fxp_mc_setup(struct fxp_softc *sc); 224static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 225 int autosize); 226static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 227 u_int16_t data); 228static void fxp_autosize_eeprom(struct fxp_softc *sc); 229static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 230 int offset, int words); 231static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233static int fxp_ifmedia_upd(struct ifnet *ifp); 234static void fxp_ifmedia_sts(struct ifnet *ifp, 235 struct ifmediareq *ifmr); 236static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 237static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 240static void fxp_miibus_writereg(device_t dev, int phy, int reg, 241 int value); 242static void fxp_load_ucode(struct fxp_softc *sc); 243static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 244 int low, int high); 245static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 246static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 247static void fxp_scb_wait(struct fxp_softc *sc); 248static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 249static void fxp_dma_wait(struct fxp_softc *sc, 250 volatile u_int16_t *status, bus_dma_tag_t dmat, 251 bus_dmamap_t map); 252 253static device_method_t fxp_methods[] = { 254 /* Device interface */ 255 DEVMETHOD(device_probe, fxp_probe), 256 DEVMETHOD(device_attach, fxp_attach), 257 DEVMETHOD(device_detach, fxp_detach), 258 DEVMETHOD(device_shutdown, fxp_shutdown), 259 DEVMETHOD(device_suspend, fxp_suspend), 260 DEVMETHOD(device_resume, fxp_resume), 261 262 /* MII interface */ 263 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 264 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 265 266 { 0, 0 } 267}; 268 269static driver_t fxp_driver = { 270 "fxp", 271 fxp_methods, 272 sizeof(struct fxp_softc), 273}; 274 275static devclass_t fxp_devclass; 276 277DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 278DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 279DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 280 281/* 282 * Wait for the previous command to be accepted (but not necessarily 283 * completed). 284 */ 285static void 286fxp_scb_wait(struct fxp_softc *sc) 287{ 288 int i = 10000; 289 290 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 291 DELAY(2); 292 if (i == 0) 293 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 294 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 295 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 296 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 297 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 298} 299 300static void 301fxp_scb_cmd(struct fxp_softc *sc, int cmd) 302{ 303 304 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 305 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 306 fxp_scb_wait(sc); 307 } 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 309} 310 311static void 312fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 313 bus_dma_tag_t dmat, bus_dmamap_t map) 314{ 315 int i = 10000; 316 317 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 318 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 319 DELAY(2); 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 } 322 if (i == 0) 323 device_printf(sc->dev, "DMA timeout\n"); 324} 325 326/* 327 * Return identification string if this device is ours. 328 */ 329static int 330fxp_probe(device_t dev) 331{ 332 u_int16_t devid; 333 u_int8_t revid; 334 struct fxp_ident *ident; 335 336 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 337 devid = pci_get_device(dev); 338 revid = pci_get_revid(dev); 339 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 340 if (ident->devid == devid && 341 (ident->revid == revid || ident->revid == -1)) { 342 device_set_desc(dev, ident->name); 343 return (0); 344 } 345 } 346 } 347 return (ENXIO); 348} 349 350static void 351fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 352{ 353 u_int32_t *addr; 354 355 if (error) 356 return; 357 358 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 359 addr = arg; 360 *addr = segs->ds_addr; 361} 362 363static int 364fxp_attach(device_t dev) 365{ 366 int error = 0; 367 struct fxp_softc *sc = device_get_softc(dev); 368 struct ifnet *ifp; 369 struct fxp_rx *rxp; 370 u_int32_t val; 371 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 372 int i, rid, m1, m2, prefer_iomap, maxtxseg; 373 int s, ipcbxmit_disable; 374 375 sc->dev = dev; 376 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 377 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 378 MTX_DEF); 379 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 380 fxp_serial_ifmedia_sts); 381 382 s = splimp(); 383 384 /* 385 * Enable bus mastering. 386 */ 387 pci_enable_busmaster(dev); 388 val = pci_read_config(dev, PCIR_COMMAND, 2); 389 390 /* 391 * Figure out which we should try first - memory mapping or i/o mapping? 392 * We default to memory mapping. Then we accept an override from the 393 * command line. Then we check to see which one is enabled. 394 */ 395 m1 = PCIM_CMD_MEMEN; 396 m2 = PCIM_CMD_PORTEN; 397 prefer_iomap = 0; 398 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 399 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 400 m1 = PCIM_CMD_PORTEN; 401 m2 = PCIM_CMD_MEMEN; 402 } 403 404 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 405 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 406 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 407 if (sc->mem == NULL) { 408 sc->rtp = 409 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 410 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 411 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 412 RF_ACTIVE); 413 } 414 415 if (!sc->mem) { 416 error = ENXIO; 417 goto fail; 418 } 419 if (bootverbose) { 420 device_printf(dev, "using %s space register mapping\n", 421 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 422 } 423 424 sc->sc_st = rman_get_bustag(sc->mem); 425 sc->sc_sh = rman_get_bushandle(sc->mem); 426 427 /* 428 * Allocate our interrupt. 429 */ 430 rid = 0; 431 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 432 RF_SHAREABLE | RF_ACTIVE); 433 if (sc->irq == NULL) { 434 device_printf(dev, "could not map interrupt\n"); 435 error = ENXIO; 436 goto fail; 437 } 438 439 /* 440 * Reset to a stable state. 441 */ 442 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 443 DELAY(10); 444 445 /* 446 * Find out how large of an SEEPROM we have. 447 */ 448 fxp_autosize_eeprom(sc); 449 450 /* 451 * Determine whether we must use the 503 serial interface. 452 */ 453 fxp_read_eeprom(sc, &data, 6, 1); 454 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 455 (data & FXP_PHY_SERIAL_ONLY)) 456 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 457 458 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 459 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 460 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 461 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 462 "FXP driver receive interrupt microcode bundling delay"); 463 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 464 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 465 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 466 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 467 "FXP driver receive interrupt microcode bundle size limit"); 468 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 469 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 470 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 471 "FXP RNR events"); 472 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 473 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 474 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 475 "FXP flow control disabled"); 476 477 /* 478 * Pull in device tunables. 479 */ 480 sc->tunable_int_delay = TUNABLE_INT_DELAY; 481 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 482 sc->tunable_noflow = 0; 483 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 484 "int_delay", &sc->tunable_int_delay); 485 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 486 "bundle_max", &sc->tunable_bundle_max); 487 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 488 "noflow", &sc->tunable_noflow); 489 sc->rnr = 0; 490 491 /* 492 * Find out the chip revision; lump all 82557 revs together. 493 */ 494 fxp_read_eeprom(sc, &data, 5, 1); 495 if ((data >> 8) == 1) 496 sc->revision = FXP_REV_82557; 497 else 498 sc->revision = pci_get_revid(dev); 499 500 /* 501 * Enable workarounds for certain chip revision deficiencies. 502 * 503 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 504 * some systems based a normal 82559 design, have a defect where 505 * the chip can cause a PCI protocol violation if it receives 506 * a CU_RESUME command when it is entering the IDLE state. The 507 * workaround is to disable Dynamic Standby Mode, so the chip never 508 * deasserts CLKRUN#, and always remains in an active state. 509 * 510 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 511 */ 512 i = pci_get_device(dev); 513 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 514 sc->revision >= FXP_REV_82559_A0) { 515 fxp_read_eeprom(sc, &data, 10, 1); 516 if (data & 0x02) { /* STB enable */ 517 u_int16_t cksum; 518 int i; 519 520 device_printf(dev, 521 "Disabling dynamic standby mode in EEPROM\n"); 522 data &= ~0x02; 523 fxp_write_eeprom(sc, &data, 10, 1); 524 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 525 cksum = 0; 526 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 527 fxp_read_eeprom(sc, &data, i, 1); 528 cksum += data; 529 } 530 i = (1 << sc->eeprom_size) - 1; 531 cksum = 0xBABA - cksum; 532 fxp_read_eeprom(sc, &data, i, 1); 533 fxp_write_eeprom(sc, &cksum, i, 1); 534 device_printf(dev, 535 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 536 i, data, cksum); 537#if 1 538 /* 539 * If the user elects to continue, try the software 540 * workaround, as it is better than nothing. 541 */ 542 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 543#endif 544 } 545 } 546 547 /* 548 * If we are not a 82557 chip, we can enable extended features. 549 */ 550 if (sc->revision != FXP_REV_82557) { 551 /* 552 * If MWI is enabled in the PCI configuration, and there 553 * is a valid cacheline size (8 or 16 dwords), then tell 554 * the board to turn on MWI. 555 */ 556 if (val & PCIM_CMD_MWRICEN && 557 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 558 sc->flags |= FXP_FLAG_MWI_ENABLE; 559 560 /* turn on the extended TxCB feature */ 561 sc->flags |= FXP_FLAG_EXT_TXCB; 562 563 /* enable reception of long frames for VLAN */ 564 sc->flags |= FXP_FLAG_LONG_PKT_EN; 565 } else { 566 /* a hack to get long VLAN frames on a 82557 */ 567 sc->flags |= FXP_FLAG_SAVE_BAD; 568 } 569 570 /* 571 * Enable use of extended RFDs and TCBs for 82550 572 * and later chips. Note: we need extended TXCB support 573 * too, but that's already enabled by the code above. 574 * Be careful to do this only on the right devices. 575 * 576 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 577 * truncate packets that end with an mbuf containing 1 to 3 bytes 578 * when used with this feature enabled in the previous version of the 579 * driver. This problem appears to be fixed now that the driver 580 * always sets the hardware parse bit in the IPCB structure, which 581 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 582 * Source Software Developer Manual" says is necessary in the 583 * cases where packet truncation was observed. 584 * 585 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 586 * allows this feature to be disabled at boot time. 587 * 588 * If fxp is not compiled into the kernel, this feature may also 589 * be disabled at run time: 590 * # kldunload fxp 591 * # kenv hint.fxp.0.ipcbxmit_disable=1 592 * # kldload fxp 593 */ 594 595 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 596 &ipcbxmit_disable) != 0) 597 ipcbxmit_disable = 0; 598 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 599 sc->revision == FXP_REV_82550_C)) { 600 sc->rfa_size = sizeof (struct fxp_rfa); 601 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 602 sc->flags |= FXP_FLAG_EXT_RFA; 603 } else { 604 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 605 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 606 } 607 608 /* 609 * Allocate DMA tags and DMA safe memory. 610 */ 611 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 612 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 613 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 614 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 615 if (error) { 616 device_printf(dev, "could not allocate dma tag\n"); 617 goto fail; 618 } 619 620 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 621 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 622 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 623 &sc->fxp_stag); 624 if (error) { 625 device_printf(dev, "could not allocate dma tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 631 if (error) 632 goto fail; 633 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 634 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 635 if (error) { 636 device_printf(dev, "could not map the stats buffer\n"); 637 goto fail; 638 } 639 640 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 641 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 642 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 643 if (error) { 644 device_printf(dev, "could not allocate dma tag\n"); 645 goto fail; 646 } 647 648 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 649 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 650 if (error) 651 goto fail; 652 653 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 654 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 655 &sc->fxp_desc.cbl_addr, 0); 656 if (error) { 657 device_printf(dev, "could not map DMA memory\n"); 658 goto fail; 659 } 660 661 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 662 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 663 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 664 &sc->mcs_tag); 665 if (error) { 666 device_printf(dev, "could not allocate dma tag\n"); 667 goto fail; 668 } 669 670 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 671 BUS_DMA_NOWAIT, &sc->mcs_map); 672 if (error) 673 goto fail; 674 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 675 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 676 if (error) { 677 device_printf(dev, "can't map the multicast setup command\n"); 678 goto fail; 679 } 680 681 /* 682 * Pre-allocate the TX DMA maps. 683 */ 684 for (i = 0; i < FXP_NTXCB; i++) { 685 error = bus_dmamap_create(sc->fxp_mtag, 0, 686 &sc->fxp_desc.tx_list[i].tx_map); 687 if (error) { 688 device_printf(dev, "can't create DMA map for TX\n"); 689 goto fail; 690 } 691 } 692 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 693 if (error) { 694 device_printf(dev, "can't create spare DMA map\n"); 695 goto fail; 696 } 697 698 /* 699 * Pre-allocate our receive buffers. 700 */ 701 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 702 for (i = 0; i < FXP_NRFABUFS; i++) { 703 rxp = &sc->fxp_desc.rx_list[i]; 704 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 705 if (error) { 706 device_printf(dev, "can't create DMA map for RX\n"); 707 goto fail; 708 } 709 if (fxp_add_rfabuf(sc, rxp) != 0) { 710 error = ENOMEM; 711 goto fail; 712 } 713 } 714 715 /* 716 * Read MAC address. 717 */ 718 fxp_read_eeprom(sc, myea, 0, 3); 719 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 720 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 721 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 722 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 723 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 724 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 725 if (bootverbose) { 726 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 727 pci_get_vendor(dev), pci_get_device(dev), 728 pci_get_subvendor(dev), pci_get_subdevice(dev), 729 pci_get_revid(dev)); 730 fxp_read_eeprom(sc, &data, 10, 1); 731 device_printf(dev, "Dynamic Standby mode is %s\n", 732 data & 0x02 ? "enabled" : "disabled"); 733 } 734 735 /* 736 * If this is only a 10Mbps device, then there is no MII, and 737 * the PHY will use a serial interface instead. 738 * 739 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 740 * doesn't have a programming interface of any sort. The 741 * media is sensed automatically based on how the link partner 742 * is configured. This is, in essence, manual configuration. 743 */ 744 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 745 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 746 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 747 } else { 748 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 749 fxp_ifmedia_sts)) { 750 device_printf(dev, "MII without any PHY!\n"); 751 error = ENXIO; 752 goto fail; 753 } 754 } 755 756 ifp = &sc->arpcom.ac_if; 757 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 758 ifp->if_baudrate = 100000000; 759 ifp->if_init = fxp_init; 760 ifp->if_softc = sc; 761 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 762 ifp->if_ioctl = fxp_ioctl; 763 ifp->if_start = fxp_start; 764 ifp->if_watchdog = fxp_watchdog; 765 766 ifp->if_capabilities = ifp->if_capenable = 0; 767 768 /* Enable checksum offload for 82550 or better chips */ 769 if (sc->flags & FXP_FLAG_EXT_RFA) { 770 ifp->if_hwassist = FXP_CSUM_FEATURES; 771 ifp->if_capabilities |= IFCAP_HWCSUM; 772 ifp->if_capenable |= IFCAP_HWCSUM; 773 } 774 775#ifdef DEVICE_POLLING 776 /* Inform the world we support polling. */ 777 ifp->if_capabilities |= IFCAP_POLLING; 778 ifp->if_capenable |= IFCAP_POLLING; 779#endif 780 781 /* 782 * Attach the interface. 783 */ 784 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 785 786 /* 787 * Tell the upper layer(s) we support long frames. 788 * Must appear after the call to ether_ifattach() because 789 * ether_ifattach() sets ifi_hdrlen to the default value. 790 */ 791 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 792 ifp->if_capabilities |= IFCAP_VLAN_MTU; 793 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 794 795 /* 796 * Let the system queue as many packets as we have available 797 * TX descriptors. 798 */ 799 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 800 801 /* 802 * Hook our interrupt after all initialization is complete. 803 * XXX This driver has been tested with the INTR_MPSAFFE flag set 804 * however, ifp and its functions are not fully locked so MPSAFE 805 * should not be used unless you can handle potential data loss. 806 */ 807 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 808 fxp_intr, sc, &sc->ih); 809 if (error) { 810 device_printf(dev, "could not setup irq\n"); 811 ether_ifdetach(&sc->arpcom.ac_if); 812 goto fail; 813 } 814 815fail: 816 splx(s); 817 if (error) 818 fxp_release(sc); 819 return (error); 820} 821 822/* 823 * Release all resources. The softc lock should not be held and the 824 * interrupt should already be torn down. 825 */ 826static void 827fxp_release(struct fxp_softc *sc) 828{ 829 struct fxp_rx *rxp; 830 struct fxp_tx *txp; 831 int i; 832 833 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 834 KASSERT(sc->ih == NULL, 835 ("fxp_release() called with intr handle still active")); 836 if (sc->miibus) 837 device_delete_child(sc->dev, sc->miibus); 838 bus_generic_detach(sc->dev); 839 ifmedia_removeall(&sc->sc_media); 840 if (sc->fxp_desc.cbl_list) { 841 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 842 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 843 sc->cbl_map); 844 } 845 if (sc->fxp_stats) { 846 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 847 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 848 } 849 if (sc->mcsp) { 850 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 851 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 852 } 853 if (sc->irq) 854 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 855 if (sc->mem) 856 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 857 if (sc->fxp_mtag) { 858 for (i = 0; i < FXP_NRFABUFS; i++) { 859 rxp = &sc->fxp_desc.rx_list[i]; 860 if (rxp->rx_mbuf != NULL) { 861 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 862 BUS_DMASYNC_POSTREAD); 863 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 864 m_freem(rxp->rx_mbuf); 865 } 866 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 867 } 868 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 869 bus_dma_tag_destroy(sc->fxp_mtag); 870 } 871 if (sc->fxp_stag) { 872 for (i = 0; i < FXP_NTXCB; i++) { 873 txp = &sc->fxp_desc.tx_list[i]; 874 if (txp->tx_mbuf != NULL) { 875 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 876 BUS_DMASYNC_POSTWRITE); 877 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 878 m_freem(txp->tx_mbuf); 879 } 880 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 881 } 882 bus_dma_tag_destroy(sc->fxp_stag); 883 } 884 if (sc->cbl_tag) 885 bus_dma_tag_destroy(sc->cbl_tag); 886 if (sc->mcs_tag) 887 bus_dma_tag_destroy(sc->mcs_tag); 888 889 mtx_destroy(&sc->sc_mtx); 890} 891 892/* 893 * Detach interface. 894 */ 895static int 896fxp_detach(device_t dev) 897{ 898 struct fxp_softc *sc = device_get_softc(dev); 899 int s; 900 901 FXP_LOCK(sc); 902 s = splimp(); 903 904 sc->suspended = 1; /* Do same thing as we do for suspend */ 905 /* 906 * Close down routes etc. 907 */ 908 ether_ifdetach(&sc->arpcom.ac_if); 909 910 /* 911 * Stop DMA and drop transmit queue, but disable interrupts first. 912 */ 913 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 914 fxp_stop(sc); 915 FXP_UNLOCK(sc); 916 917 /* 918 * Unhook interrupt before dropping lock. This is to prevent 919 * races with fxp_intr(). 920 */ 921 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 922 sc->ih = NULL; 923 924 splx(s); 925 926 /* Release our allocated resources. */ 927 fxp_release(sc); 928 return (0); 929} 930 931/* 932 * Device shutdown routine. Called at system shutdown after sync. The 933 * main purpose of this routine is to shut off receiver DMA so that 934 * kernel memory doesn't get clobbered during warmboot. 935 */ 936static int 937fxp_shutdown(device_t dev) 938{ 939 /* 940 * Make sure that DMA is disabled prior to reboot. Not doing 941 * do could allow DMA to corrupt kernel memory during the 942 * reboot before the driver initializes. 943 */ 944 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 945 return (0); 946} 947 948/* 949 * Device suspend routine. Stop the interface and save some PCI 950 * settings in case the BIOS doesn't restore them properly on 951 * resume. 952 */ 953static int 954fxp_suspend(device_t dev) 955{ 956 struct fxp_softc *sc = device_get_softc(dev); 957 int i, s; 958 959 FXP_LOCK(sc); 960 s = splimp(); 961 962 fxp_stop(sc); 963 964 for (i = 0; i < 5; i++) 965 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 966 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 967 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 968 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 969 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 970 971 sc->suspended = 1; 972 973 FXP_UNLOCK(sc); 974 splx(s); 975 return (0); 976} 977 978/* 979 * Device resume routine. Restore some PCI settings in case the BIOS 980 * doesn't, re-enable busmastering, and restart the interface if 981 * appropriate. 982 */ 983static int 984fxp_resume(device_t dev) 985{ 986 struct fxp_softc *sc = device_get_softc(dev); 987 struct ifnet *ifp = &sc->sc_if; 988 u_int16_t pci_command; 989 int i, s; 990 991 FXP_LOCK(sc); 992 s = splimp(); 993 994 /* better way to do this? */ 995 for (i = 0; i < 5; i++) 996 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 997 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 998 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 999 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1000 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1001 1002 /* reenable busmastering */ 1003 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1004 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1005 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1006 1007 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1008 DELAY(10); 1009 1010 /* reinitialize interface if necessary */ 1011 if (ifp->if_flags & IFF_UP) 1012 fxp_init_body(sc); 1013 1014 sc->suspended = 0; 1015 1016 FXP_UNLOCK(sc); 1017 splx(s); 1018 return (0); 1019} 1020 1021static void 1022fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1023{ 1024 u_int16_t reg; 1025 int x; 1026 1027 /* 1028 * Shift in data. 1029 */ 1030 for (x = 1 << (length - 1); x; x >>= 1) { 1031 if (data & x) 1032 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1033 else 1034 reg = FXP_EEPROM_EECS; 1035 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1036 DELAY(1); 1037 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1038 DELAY(1); 1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1040 DELAY(1); 1041 } 1042} 1043 1044/* 1045 * Read from the serial EEPROM. Basically, you manually shift in 1046 * the read opcode (one bit at a time) and then shift in the address, 1047 * and then you shift out the data (all of this one bit at a time). 1048 * The word size is 16 bits, so you have to provide the address for 1049 * every 16 bits of data. 1050 */ 1051static u_int16_t 1052fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1053{ 1054 u_int16_t reg, data; 1055 int x; 1056 1057 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1058 /* 1059 * Shift in read opcode. 1060 */ 1061 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1062 /* 1063 * Shift in address. 1064 */ 1065 data = 0; 1066 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1067 if (offset & x) 1068 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1069 else 1070 reg = FXP_EEPROM_EECS; 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1072 DELAY(1); 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1074 DELAY(1); 1075 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1076 DELAY(1); 1077 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1078 data++; 1079 if (autosize && reg == 0) { 1080 sc->eeprom_size = data; 1081 break; 1082 } 1083 } 1084 /* 1085 * Shift out data. 1086 */ 1087 data = 0; 1088 reg = FXP_EEPROM_EECS; 1089 for (x = 1 << 15; x; x >>= 1) { 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1091 DELAY(1); 1092 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1093 data |= x; 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1095 DELAY(1); 1096 } 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1098 DELAY(1); 1099 1100 return (data); 1101} 1102 1103static void 1104fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1105{ 1106 int i; 1107 1108 /* 1109 * Erase/write enable. 1110 */ 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1112 fxp_eeprom_shiftin(sc, 0x4, 3); 1113 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1114 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1115 DELAY(1); 1116 /* 1117 * Shift in write opcode, address, data. 1118 */ 1119 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1120 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1121 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1122 fxp_eeprom_shiftin(sc, data, 16); 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1124 DELAY(1); 1125 /* 1126 * Wait for EEPROM to finish up. 1127 */ 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1129 DELAY(1); 1130 for (i = 0; i < 1000; i++) { 1131 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1132 break; 1133 DELAY(50); 1134 } 1135 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1136 DELAY(1); 1137 /* 1138 * Erase/write disable. 1139 */ 1140 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1141 fxp_eeprom_shiftin(sc, 0x4, 3); 1142 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1144 DELAY(1); 1145} 1146 1147/* 1148 * From NetBSD: 1149 * 1150 * Figure out EEPROM size. 1151 * 1152 * 559's can have either 64-word or 256-word EEPROMs, the 558 1153 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1154 * talks about the existance of 16 to 256 word EEPROMs. 1155 * 1156 * The only known sizes are 64 and 256, where the 256 version is used 1157 * by CardBus cards to store CIS information. 1158 * 1159 * The address is shifted in msb-to-lsb, and after the last 1160 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1161 * after which follows the actual data. We try to detect this zero, by 1162 * probing the data-out bit in the EEPROM control register just after 1163 * having shifted in a bit. If the bit is zero, we assume we've 1164 * shifted enough address bits. The data-out should be tri-state, 1165 * before this, which should translate to a logical one. 1166 */ 1167static void 1168fxp_autosize_eeprom(struct fxp_softc *sc) 1169{ 1170 1171 /* guess maximum size of 256 words */ 1172 sc->eeprom_size = 8; 1173 1174 /* autosize */ 1175 (void) fxp_eeprom_getword(sc, 0, 1); 1176} 1177 1178static void 1179fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1180{ 1181 int i; 1182 1183 for (i = 0; i < words; i++) 1184 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1185} 1186 1187static void 1188fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1189{ 1190 int i; 1191 1192 for (i = 0; i < words; i++) 1193 fxp_eeprom_putword(sc, offset + i, data[i]); 1194} 1195 1196static void 1197fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1198 bus_size_t mapsize, int error) 1199{ 1200 struct fxp_softc *sc; 1201 struct fxp_cb_tx *txp; 1202 int i; 1203 1204 if (error) 1205 return; 1206 1207 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1208 1209 sc = arg; 1210 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1211 for (i = 0; i < nseg; i++) { 1212 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1213 /* 1214 * If this is an 82550/82551, then we're using extended 1215 * TxCBs _and_ we're using checksum offload. This means 1216 * that the TxCB is really an IPCB. One major difference 1217 * between the two is that with plain extended TxCBs, 1218 * the bottom half of the TxCB contains two entries from 1219 * the TBD array, whereas IPCBs contain just one entry: 1220 * one entry (8 bytes) has been sacrificed for the TCP/IP 1221 * checksum offload control bits. So to make things work 1222 * right, we have to start filling in the TBD array 1223 * starting from a different place depending on whether 1224 * the chip is an 82550/82551 or not. 1225 */ 1226 if (sc->flags & FXP_FLAG_EXT_RFA) { 1227 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1228 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1229 } else { 1230 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1231 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1232 } 1233 } 1234 txp->tbd_number = nseg; 1235} 1236 1237/* 1238 * Grab the softc lock and call the real fxp_start_body() routine 1239 */ 1240static void 1241fxp_start(struct ifnet *ifp) 1242{ 1243 struct fxp_softc *sc = ifp->if_softc; 1244 1245 FXP_LOCK(sc); 1246 fxp_start_body(ifp); 1247 FXP_UNLOCK(sc); 1248} 1249 1250/* 1251 * Start packet transmission on the interface. 1252 * This routine must be called with the softc lock held, and is an 1253 * internal entry point only. 1254 */ 1255static void 1256fxp_start_body(struct ifnet *ifp) 1257{ 1258 struct fxp_softc *sc = ifp->if_softc; 1259 struct fxp_tx *txp; 1260 struct mbuf *mb_head; 1261 int error; 1262 1263 FXP_LOCK_ASSERT(sc, MA_OWNED); 1264 /* 1265 * See if we need to suspend xmit until the multicast filter 1266 * has been reprogrammed (which can only be done at the head 1267 * of the command chain). 1268 */ 1269 if (sc->need_mcsetup) { 1270 return; 1271 } 1272 1273 txp = NULL; 1274 1275 /* 1276 * We're finished if there is nothing more to add to the list or if 1277 * we're all filled up with buffers to transmit. 1278 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1279 * a NOP command when needed. 1280 */ 1281 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1282 1283 /* 1284 * Grab a packet to transmit. 1285 */ 1286 IF_DEQUEUE(&ifp->if_snd, mb_head); 1287 1288 /* 1289 * Get pointer to next available tx desc. 1290 */ 1291 txp = sc->fxp_desc.tx_last->tx_next; 1292 1293 /* 1294 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1295 * Ethernet Controller Family Open Source Software 1296 * Developer Manual says: 1297 * Using software parsing is only allowed with legal 1298 * TCP/IP or UDP/IP packets. 1299 * ... 1300 * For all other datagrams, hardware parsing must 1301 * be used. 1302 * Software parsing appears to truncate ICMP and 1303 * fragmented UDP packets that contain one to three 1304 * bytes in the second (and final) mbuf of the packet. 1305 */ 1306 if (sc->flags & FXP_FLAG_EXT_RFA) 1307 txp->tx_cb->ipcb_ip_activation_high = 1308 FXP_IPCB_HARDWAREPARSING_ENABLE; 1309 1310 /* 1311 * Deal with TCP/IP checksum offload. Note that 1312 * in order for TCP checksum offload to work, 1313 * the pseudo header checksum must have already 1314 * been computed and stored in the checksum field 1315 * in the TCP header. The stack should have 1316 * already done this for us. 1317 */ 1318 1319 if (mb_head->m_pkthdr.csum_flags) { 1320 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1321 txp->tx_cb->ipcb_ip_schedule = 1322 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1323 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1324 txp->tx_cb->ipcb_ip_schedule |= 1325 FXP_IPCB_TCP_PACKET; 1326 } 1327#ifdef FXP_IP_CSUM_WAR 1328 /* 1329 * XXX The 82550 chip appears to have trouble 1330 * dealing with IP header checksums in very small 1331 * datagrams, namely fragments from 1 to 3 bytes 1332 * in size. For example, say you want to transmit 1333 * a UDP packet of 1473 bytes. The packet will be 1334 * fragmented over two IP datagrams, the latter 1335 * containing only one byte of data. The 82550 will 1336 * botch the header checksum on the 1-byte fragment. 1337 * As long as the datagram contains 4 or more bytes 1338 * of data, you're ok. 1339 * 1340 * The following code attempts to work around this 1341 * problem: if the datagram is less than 38 bytes 1342 * in size (14 bytes ether header, 20 bytes IP header, 1343 * plus 4 bytes of data), we punt and compute the IP 1344 * header checksum by hand. This workaround doesn't 1345 * work very well, however, since it can be fooled 1346 * by things like VLAN tags and IP options that make 1347 * the header sizes/offsets vary. 1348 */ 1349 1350 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1351 if (mb_head->m_pkthdr.len < 38) { 1352 struct ip *ip; 1353 mb_head->m_data += ETHER_HDR_LEN; 1354 ip = mtod(mb_head, struct ip *); 1355 ip->ip_sum = in_cksum(mb_head, 1356 ip->ip_hl << 2); 1357 mb_head->m_data -= ETHER_HDR_LEN; 1358 } else { 1359 txp->tx_cb->ipcb_ip_activation_high = 1360 FXP_IPCB_HARDWAREPARSING_ENABLE; 1361 txp->tx_cb->ipcb_ip_schedule |= 1362 FXP_IPCB_IP_CHECKSUM_ENABLE; 1363 } 1364 } 1365#endif 1366 } 1367 1368 /* 1369 * Go through each of the mbufs in the chain and initialize 1370 * the transmit buffer descriptors with the physical address 1371 * and size of the mbuf. 1372 */ 1373 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1374 mb_head, fxp_dma_map_txbuf, sc, 0); 1375 1376 if (error && error != EFBIG) { 1377 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1378 error); 1379 m_freem(mb_head); 1380 break; 1381 } 1382 1383 if (error) { 1384 struct mbuf *mn; 1385 1386 /* 1387 * We ran out of segments. We have to recopy this 1388 * mbuf chain first. Bail out if we can't get the 1389 * new buffers. 1390 */ 1391 mn = m_defrag(mb_head, M_DONTWAIT); 1392 if (mn == NULL) { 1393 m_freem(mb_head); 1394 break; 1395 } else { 1396 mb_head = mn; 1397 } 1398 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1399 mb_head, fxp_dma_map_txbuf, sc, 0); 1400 if (error) { 1401 device_printf(sc->dev, 1402 "can't map mbuf (error %d)\n", error); 1403 m_freem(mb_head); 1404 break; 1405 } 1406 } 1407 1408 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1409 BUS_DMASYNC_PREWRITE); 1410 1411 txp->tx_mbuf = mb_head; 1412 txp->tx_cb->cb_status = 0; 1413 txp->tx_cb->byte_count = 0; 1414 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1415 txp->tx_cb->cb_command = 1416 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1417 FXP_CB_COMMAND_S); 1418 } else { 1419 txp->tx_cb->cb_command = 1420 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1421 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1422 /* 1423 * Set a 5 second timer just in case we don't hear 1424 * from the card again. 1425 */ 1426 ifp->if_timer = 5; 1427 } 1428 txp->tx_cb->tx_threshold = tx_threshold; 1429 1430 /* 1431 * Advance the end of list forward. 1432 */ 1433 1434#ifdef __alpha__ 1435 /* 1436 * On platforms which can't access memory in 16-bit 1437 * granularities, we must prevent the card from DMA'ing 1438 * up the status while we update the command field. 1439 * This could cause us to overwrite the completion status. 1440 * XXX This is probably bogus and we're _not_ looking 1441 * for atomicity here. 1442 */ 1443 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1444 htole16(FXP_CB_COMMAND_S)); 1445#else 1446 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1447 htole16(~FXP_CB_COMMAND_S); 1448#endif /*__alpha__*/ 1449 sc->fxp_desc.tx_last = txp; 1450 1451 /* 1452 * Advance the beginning of the list forward if there are 1453 * no other packets queued (when nothing is queued, tx_first 1454 * sits on the last TxCB that was sent out). 1455 */ 1456 if (sc->tx_queued == 0) 1457 sc->fxp_desc.tx_first = txp; 1458 1459 sc->tx_queued++; 1460 1461 /* 1462 * Pass packet to bpf if there is a listener. 1463 */ 1464 BPF_MTAP(ifp, mb_head); 1465 } 1466 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1467 1468 /* 1469 * We're finished. If we added to the list, issue a RESUME to get DMA 1470 * going again if suspended. 1471 */ 1472 if (txp != NULL) { 1473 fxp_scb_wait(sc); 1474 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1475 } 1476} 1477 1478#ifdef DEVICE_POLLING 1479static poll_handler_t fxp_poll; 1480 1481static void 1482fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1483{ 1484 struct fxp_softc *sc = ifp->if_softc; 1485 u_int8_t statack; 1486 1487 FXP_LOCK(sc); 1488 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1489 ether_poll_deregister(ifp); 1490 cmd = POLL_DEREGISTER; 1491 } 1492 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1493 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1494 FXP_UNLOCK(sc); 1495 return; 1496 } 1497 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1498 FXP_SCB_STATACK_FR; 1499 if (cmd == POLL_AND_CHECK_STATUS) { 1500 u_int8_t tmp; 1501 1502 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1503 if (tmp == 0xff || tmp == 0) { 1504 FXP_UNLOCK(sc); 1505 return; /* nothing to do */ 1506 } 1507 tmp &= ~statack; 1508 /* ack what we can */ 1509 if (tmp != 0) 1510 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1511 statack |= tmp; 1512 } 1513 fxp_intr_body(sc, ifp, statack, count); 1514 FXP_UNLOCK(sc); 1515} 1516#endif /* DEVICE_POLLING */ 1517 1518/* 1519 * Process interface interrupts. 1520 */ 1521static void 1522fxp_intr(void *xsc) 1523{ 1524 struct fxp_softc *sc = xsc; 1525 struct ifnet *ifp = &sc->sc_if; 1526 u_int8_t statack; 1527 1528 FXP_LOCK(sc); 1529 if (sc->suspended) { 1530 FXP_UNLOCK(sc); 1531 return; 1532 } 1533 1534#ifdef DEVICE_POLLING 1535 if (ifp->if_flags & IFF_POLLING) { 1536 FXP_UNLOCK(sc); 1537 return; 1538 } 1539 if ((ifp->if_capenable & IFCAP_POLLING) && 1540 ether_poll_register(fxp_poll, ifp)) { 1541 /* disable interrupts */ 1542 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1543 FXP_UNLOCK(sc); 1544 fxp_poll(ifp, 0, 1); 1545 return; 1546 } 1547#endif 1548 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1549 /* 1550 * It should not be possible to have all bits set; the 1551 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1552 * all bits are set, this may indicate that the card has 1553 * been physically ejected, so ignore it. 1554 */ 1555 if (statack == 0xff) { 1556 FXP_UNLOCK(sc); 1557 return; 1558 } 1559 1560 /* 1561 * First ACK all the interrupts in this pass. 1562 */ 1563 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1564 fxp_intr_body(sc, ifp, statack, -1); 1565 } 1566 FXP_UNLOCK(sc); 1567} 1568 1569static void 1570fxp_txeof(struct fxp_softc *sc) 1571{ 1572 struct fxp_tx *txp; 1573 1574 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1575 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1576 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1577 txp = txp->tx_next) { 1578 if (txp->tx_mbuf != NULL) { 1579 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1580 BUS_DMASYNC_POSTWRITE); 1581 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1582 m_freem(txp->tx_mbuf); 1583 txp->tx_mbuf = NULL; 1584 /* clear this to reset csum offload bits */ 1585 txp->tx_cb->tbd[0].tb_addr = 0; 1586 } 1587 sc->tx_queued--; 1588 } 1589 sc->fxp_desc.tx_first = txp; 1590 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1591} 1592 1593static void 1594fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1595 int count) 1596{ 1597 struct mbuf *m; 1598 struct fxp_rx *rxp; 1599 struct fxp_rfa *rfa; 1600 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1601 1602 FXP_LOCK_ASSERT(sc, MA_OWNED); 1603 if (rnr) 1604 sc->rnr++; 1605#ifdef DEVICE_POLLING 1606 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1607 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1608 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1609 rnr = 1; 1610 } 1611#endif 1612 1613 /* 1614 * Free any finished transmit mbuf chains. 1615 * 1616 * Handle the CNA event likt a CXTNO event. It used to 1617 * be that this event (control unit not ready) was not 1618 * encountered, but it is now with the SMPng modifications. 1619 * The exact sequence of events that occur when the interface 1620 * is brought up are different now, and if this event 1621 * goes unhandled, the configuration/rxfilter setup sequence 1622 * can stall for several seconds. The result is that no 1623 * packets go out onto the wire for about 5 to 10 seconds 1624 * after the interface is ifconfig'ed for the first time. 1625 */ 1626 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1627 fxp_txeof(sc); 1628 1629 ifp->if_timer = 0; 1630 if (sc->tx_queued == 0) { 1631 if (sc->need_mcsetup) 1632 fxp_mc_setup(sc); 1633 } 1634 /* 1635 * Try to start more packets transmitting. 1636 */ 1637 if (ifp->if_snd.ifq_head != NULL) 1638 fxp_start_body(ifp); 1639 } 1640 1641 /* 1642 * Just return if nothing happened on the receive side. 1643 */ 1644 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1645 return; 1646 1647 /* 1648 * Process receiver interrupts. If a no-resource (RNR) 1649 * condition exists, get whatever packets we can and 1650 * re-start the receiver. 1651 * 1652 * When using polling, we do not process the list to completion, 1653 * so when we get an RNR interrupt we must defer the restart 1654 * until we hit the last buffer with the C bit set. 1655 * If we run out of cycles and rfa_headm has the C bit set, 1656 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1657 * that the info will be used in the subsequent polling cycle. 1658 */ 1659 for (;;) { 1660 rxp = sc->fxp_desc.rx_head; 1661 m = rxp->rx_mbuf; 1662 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1663 RFA_ALIGNMENT_FUDGE); 1664 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1665 BUS_DMASYNC_POSTREAD); 1666 1667#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1668 if (count >= 0 && count-- == 0) { 1669 if (rnr) { 1670 /* Defer RNR processing until the next time. */ 1671 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1672 rnr = 0; 1673 } 1674 break; 1675 } 1676#endif /* DEVICE_POLLING */ 1677 1678 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1679 break; 1680 1681 /* 1682 * Advance head forward. 1683 */ 1684 sc->fxp_desc.rx_head = rxp->rx_next; 1685 1686 /* 1687 * Add a new buffer to the receive chain. 1688 * If this fails, the old buffer is recycled 1689 * instead. 1690 */ 1691 if (fxp_add_rfabuf(sc, rxp) == 0) { 1692 int total_len; 1693 1694 /* 1695 * Fetch packet length (the top 2 bits of 1696 * actual_size are flags set by the controller 1697 * upon completion), and drop the packet in case 1698 * of bogus length or CRC errors. 1699 */ 1700 total_len = le16toh(rfa->actual_size) & 0x3fff; 1701 if (total_len < sizeof(struct ether_header) || 1702 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1703 sc->rfa_size || 1704 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1705 m_freem(m); 1706 continue; 1707 } 1708 1709 /* Do IP checksum checking. */ 1710 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1711 if (rfa->rfax_csum_sts & 1712 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1713 m->m_pkthdr.csum_flags |= 1714 CSUM_IP_CHECKED; 1715 if (rfa->rfax_csum_sts & 1716 FXP_RFDX_CS_IP_CSUM_VALID) 1717 m->m_pkthdr.csum_flags |= 1718 CSUM_IP_VALID; 1719 if ((rfa->rfax_csum_sts & 1720 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1721 (rfa->rfax_csum_sts & 1722 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1723 m->m_pkthdr.csum_flags |= 1724 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1725 m->m_pkthdr.csum_data = 0xffff; 1726 } 1727 } 1728 1729 m->m_pkthdr.len = m->m_len = total_len; 1730 m->m_pkthdr.rcvif = ifp; 1731 1732 /* 1733 * Drop locks before calling if_input() since it 1734 * may re-enter fxp_start() in the netisr case. 1735 * This would result in a lock reversal. Better 1736 * performance might be obtained by chaining all 1737 * packets received, dropping the lock, and then 1738 * calling if_input() on each one. 1739 */ 1740 FXP_UNLOCK(sc); 1741 (*ifp->if_input)(ifp, m); 1742 FXP_LOCK(sc); 1743 } 1744 } 1745 if (rnr) { 1746 fxp_scb_wait(sc); 1747 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1748 sc->fxp_desc.rx_head->rx_addr); 1749 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1750 } 1751} 1752 1753/* 1754 * Update packet in/out/collision statistics. The i82557 doesn't 1755 * allow you to access these counters without doing a fairly 1756 * expensive DMA to get _all_ of the statistics it maintains, so 1757 * we do this operation here only once per second. The statistics 1758 * counters in the kernel are updated from the previous dump-stats 1759 * DMA and then a new dump-stats DMA is started. The on-chip 1760 * counters are zeroed when the DMA completes. If we can't start 1761 * the DMA immediately, we don't wait - we just prepare to read 1762 * them again next time. 1763 */ 1764static void 1765fxp_tick(void *xsc) 1766{ 1767 struct fxp_softc *sc = xsc; 1768 struct ifnet *ifp = &sc->sc_if; 1769 struct fxp_stats *sp = sc->fxp_stats; 1770 int s; 1771 1772 FXP_LOCK(sc); 1773 s = splimp(); 1774 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1775 ifp->if_opackets += le32toh(sp->tx_good); 1776 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1777 if (sp->rx_good) { 1778 ifp->if_ipackets += le32toh(sp->rx_good); 1779 sc->rx_idle_secs = 0; 1780 } else { 1781 /* 1782 * Receiver's been idle for another second. 1783 */ 1784 sc->rx_idle_secs++; 1785 } 1786 ifp->if_ierrors += 1787 le32toh(sp->rx_crc_errors) + 1788 le32toh(sp->rx_alignment_errors) + 1789 le32toh(sp->rx_rnr_errors) + 1790 le32toh(sp->rx_overrun_errors); 1791 /* 1792 * If any transmit underruns occured, bump up the transmit 1793 * threshold by another 512 bytes (64 * 8). 1794 */ 1795 if (sp->tx_underruns) { 1796 ifp->if_oerrors += le32toh(sp->tx_underruns); 1797 if (tx_threshold < 192) 1798 tx_threshold += 64; 1799 } 1800 1801 /* 1802 * Release any xmit buffers that have completed DMA. This isn't 1803 * strictly necessary to do here, but it's advantagous for mbufs 1804 * with external storage to be released in a timely manner rather 1805 * than being defered for a potentially long time. This limits 1806 * the delay to a maximum of one second. 1807 */ 1808 fxp_txeof(sc); 1809 1810 /* 1811 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1812 * then assume the receiver has locked up and attempt to clear 1813 * the condition by reprogramming the multicast filter. This is 1814 * a work-around for a bug in the 82557 where the receiver locks 1815 * up if it gets certain types of garbage in the syncronization 1816 * bits prior to the packet header. This bug is supposed to only 1817 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1818 * mode as well (perhaps due to a 10/100 speed transition). 1819 */ 1820 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1821 sc->rx_idle_secs = 0; 1822 fxp_mc_setup(sc); 1823 } 1824 /* 1825 * If there is no pending command, start another stats 1826 * dump. Otherwise punt for now. 1827 */ 1828 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1829 /* 1830 * Start another stats dump. 1831 */ 1832 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1833 BUS_DMASYNC_PREREAD); 1834 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1835 } else { 1836 /* 1837 * A previous command is still waiting to be accepted. 1838 * Just zero our copy of the stats and wait for the 1839 * next timer event to update them. 1840 */ 1841 sp->tx_good = 0; 1842 sp->tx_underruns = 0; 1843 sp->tx_total_collisions = 0; 1844 1845 sp->rx_good = 0; 1846 sp->rx_crc_errors = 0; 1847 sp->rx_alignment_errors = 0; 1848 sp->rx_rnr_errors = 0; 1849 sp->rx_overrun_errors = 0; 1850 } 1851 if (sc->miibus != NULL) 1852 mii_tick(device_get_softc(sc->miibus)); 1853 1854 /* 1855 * Schedule another timeout one second from now. 1856 */ 1857 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1858 FXP_UNLOCK(sc); 1859 splx(s); 1860} 1861 1862/* 1863 * Stop the interface. Cancels the statistics updater and resets 1864 * the interface. 1865 */ 1866static void 1867fxp_stop(struct fxp_softc *sc) 1868{ 1869 struct ifnet *ifp = &sc->sc_if; 1870 struct fxp_tx *txp; 1871 int i; 1872 1873 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1874 ifp->if_timer = 0; 1875 1876#ifdef DEVICE_POLLING 1877 ether_poll_deregister(ifp); 1878#endif 1879 /* 1880 * Cancel stats updater. 1881 */ 1882 callout_stop(&sc->stat_ch); 1883 1884 /* 1885 * Issue software reset, which also unloads the microcode. 1886 */ 1887 sc->flags &= ~FXP_FLAG_UCODE; 1888 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1889 DELAY(50); 1890 1891 /* 1892 * Release any xmit buffers. 1893 */ 1894 txp = sc->fxp_desc.tx_list; 1895 if (txp != NULL) { 1896 for (i = 0; i < FXP_NTXCB; i++) { 1897 if (txp[i].tx_mbuf != NULL) { 1898 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1899 BUS_DMASYNC_POSTWRITE); 1900 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1901 m_freem(txp[i].tx_mbuf); 1902 txp[i].tx_mbuf = NULL; 1903 /* clear this to reset csum offload bits */ 1904 txp[i].tx_cb->tbd[0].tb_addr = 0; 1905 } 1906 } 1907 } 1908 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1909 sc->tx_queued = 0; 1910} 1911 1912/* 1913 * Watchdog/transmission transmit timeout handler. Called when a 1914 * transmission is started on the interface, but no interrupt is 1915 * received before the timeout. This usually indicates that the 1916 * card has wedged for some reason. 1917 */ 1918static void 1919fxp_watchdog(struct ifnet *ifp) 1920{ 1921 struct fxp_softc *sc = ifp->if_softc; 1922 1923 FXP_LOCK(sc); 1924 device_printf(sc->dev, "device timeout\n"); 1925 ifp->if_oerrors++; 1926 1927 fxp_init_body(sc); 1928 FXP_UNLOCK(sc); 1929} 1930 1931/* 1932 * Acquire locks and then call the real initialization function. This 1933 * is necessary because ether_ioctl() calls if_init() and this would 1934 * result in mutex recursion if the mutex was held. 1935 */ 1936static void 1937fxp_init(void *xsc) 1938{ 1939 struct fxp_softc *sc = xsc; 1940 1941 FXP_LOCK(sc); 1942 fxp_init_body(sc); 1943 FXP_UNLOCK(sc); 1944} 1945 1946/* 1947 * Perform device initialization. This routine must be called with the 1948 * softc lock held. 1949 */ 1950static void 1951fxp_init_body(struct fxp_softc *sc) 1952{ 1953 struct ifnet *ifp = &sc->sc_if; 1954 struct fxp_cb_config *cbp; 1955 struct fxp_cb_ias *cb_ias; 1956 struct fxp_cb_tx *tcbp; 1957 struct fxp_tx *txp; 1958 struct fxp_cb_mcs *mcsp; 1959 int i, prm, s; 1960 1961 FXP_LOCK_ASSERT(sc, MA_OWNED); 1962 s = splimp(); 1963 /* 1964 * Cancel any pending I/O 1965 */ 1966 fxp_stop(sc); 1967 1968 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1969 1970 /* 1971 * Initialize base of CBL and RFA memory. Loading with zero 1972 * sets it up for regular linear addressing. 1973 */ 1974 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1975 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1976 1977 fxp_scb_wait(sc); 1978 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1979 1980 /* 1981 * Initialize base of dump-stats buffer. 1982 */ 1983 fxp_scb_wait(sc); 1984 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1985 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1986 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1987 1988 /* 1989 * Attempt to load microcode if requested. 1990 */ 1991 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1992 fxp_load_ucode(sc); 1993 1994 /* 1995 * Initialize the multicast address list. 1996 */ 1997 if (fxp_mc_addrs(sc)) { 1998 mcsp = sc->mcsp; 1999 mcsp->cb_status = 0; 2000 mcsp->cb_command = 2001 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2002 mcsp->link_addr = 0xffffffff; 2003 /* 2004 * Start the multicast setup command. 2005 */ 2006 fxp_scb_wait(sc); 2007 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2008 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2009 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2010 /* ...and wait for it to complete. */ 2011 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2012 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2013 BUS_DMASYNC_POSTWRITE); 2014 } 2015 2016 /* 2017 * We temporarily use memory that contains the TxCB list to 2018 * construct the config CB. The TxCB list memory is rebuilt 2019 * later. 2020 */ 2021 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2022 2023 /* 2024 * This bcopy is kind of disgusting, but there are a bunch of must be 2025 * zero and must be one bits in this structure and this is the easiest 2026 * way to initialize them all to proper values. 2027 */ 2028 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2029 2030 cbp->cb_status = 0; 2031 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2032 FXP_CB_COMMAND_EL); 2033 cbp->link_addr = 0xffffffff; /* (no) next command */ 2034 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2035 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2036 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2037 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2038 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2039 cbp->type_enable = 0; /* actually reserved */ 2040 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2041 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2042 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2043 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2044 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2045 cbp->late_scb = 0; /* (don't) defer SCB update */ 2046 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2047 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2048 cbp->ci_int = 1; /* interrupt on CU idle */ 2049 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2050 cbp->ext_stats_dis = 1; /* disable extended counters */ 2051 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2052 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2053 cbp->disc_short_rx = !prm; /* discard short packets */ 2054 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2055 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2056 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2057 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2058 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2059 cbp->csma_dis = 0; /* (don't) disable link */ 2060 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2061 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2062 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2063 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2064 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2065 cbp->nsai = 1; /* (don't) disable source addr insert */ 2066 cbp->preamble_length = 2; /* (7 byte) preamble */ 2067 cbp->loopback = 0; /* (don't) loopback */ 2068 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2069 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2070 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2071 cbp->promiscuous = prm; /* promiscuous mode */ 2072 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2073 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2074 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2075 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2076 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2077 2078 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2079 cbp->padding = 1; /* (do) pad short tx packets */ 2080 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2081 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2082 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2083 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2084 /* must set wake_en in PMCSR also */ 2085 cbp->force_fdx = 0; /* (don't) force full duplex */ 2086 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2087 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2088 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2089 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2090 2091 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2092 /* 2093 * The 82557 has no hardware flow control, the values 2094 * below are the defaults for the chip. 2095 */ 2096 cbp->fc_delay_lsb = 0; 2097 cbp->fc_delay_msb = 0x40; 2098 cbp->pri_fc_thresh = 3; 2099 cbp->tx_fc_dis = 0; 2100 cbp->rx_fc_restop = 0; 2101 cbp->rx_fc_restart = 0; 2102 cbp->fc_filter = 0; 2103 cbp->pri_fc_loc = 1; 2104 } else { 2105 cbp->fc_delay_lsb = 0x1f; 2106 cbp->fc_delay_msb = 0x01; 2107 cbp->pri_fc_thresh = 3; 2108 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2109 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2110 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2111 cbp->fc_filter = !prm; /* drop FC frames to host */ 2112 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2113 } 2114 2115 /* 2116 * Start the config command/DMA. 2117 */ 2118 fxp_scb_wait(sc); 2119 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2120 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2121 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2122 /* ...and wait for it to complete. */ 2123 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2124 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2125 2126 /* 2127 * Now initialize the station address. Temporarily use the TxCB 2128 * memory area like we did above for the config CB. 2129 */ 2130 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2131 cb_ias->cb_status = 0; 2132 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2133 cb_ias->link_addr = 0xffffffff; 2134 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2135 sizeof(sc->arpcom.ac_enaddr)); 2136 2137 /* 2138 * Start the IAS (Individual Address Setup) command/DMA. 2139 */ 2140 fxp_scb_wait(sc); 2141 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2143 /* ...and wait for it to complete. */ 2144 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2145 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2146 2147 /* 2148 * Initialize transmit control block (TxCB) list. 2149 */ 2150 txp = sc->fxp_desc.tx_list; 2151 tcbp = sc->fxp_desc.cbl_list; 2152 bzero(tcbp, FXP_TXCB_SZ); 2153 for (i = 0; i < FXP_NTXCB; i++) { 2154 txp[i].tx_cb = tcbp + i; 2155 txp[i].tx_mbuf = NULL; 2156 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2157 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2158 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2159 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2160 if (sc->flags & FXP_FLAG_EXT_TXCB) 2161 tcbp[i].tbd_array_addr = 2162 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2163 else 2164 tcbp[i].tbd_array_addr = 2165 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2166 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2167 } 2168 /* 2169 * Set the suspend flag on the first TxCB and start the control 2170 * unit. It will execute the NOP and then suspend. 2171 */ 2172 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2173 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2174 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2175 sc->tx_queued = 1; 2176 2177 fxp_scb_wait(sc); 2178 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2179 2180 /* 2181 * Initialize receiver buffer area - RFA. 2182 */ 2183 fxp_scb_wait(sc); 2184 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2185 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2186 2187 /* 2188 * Set current media. 2189 */ 2190 if (sc->miibus != NULL) 2191 mii_mediachg(device_get_softc(sc->miibus)); 2192 2193 ifp->if_flags |= IFF_RUNNING; 2194 ifp->if_flags &= ~IFF_OACTIVE; 2195 2196 /* 2197 * Enable interrupts. 2198 */ 2199#ifdef DEVICE_POLLING 2200 /* 2201 * ... but only do that if we are not polling. And because (presumably) 2202 * the default is interrupts on, we need to disable them explicitly! 2203 */ 2204 if ( ifp->if_flags & IFF_POLLING ) 2205 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2206 else 2207#endif /* DEVICE_POLLING */ 2208 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2209 2210 /* 2211 * Start stats updater. 2212 */ 2213 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2214 splx(s); 2215} 2216 2217static int 2218fxp_serial_ifmedia_upd(struct ifnet *ifp) 2219{ 2220 2221 return (0); 2222} 2223 2224static void 2225fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2226{ 2227 2228 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2229} 2230 2231/* 2232 * Change media according to request. 2233 */ 2234static int 2235fxp_ifmedia_upd(struct ifnet *ifp) 2236{ 2237 struct fxp_softc *sc = ifp->if_softc; 2238 struct mii_data *mii; 2239 2240 mii = device_get_softc(sc->miibus); 2241 mii_mediachg(mii); 2242 return (0); 2243} 2244 2245/* 2246 * Notify the world which media we're using. 2247 */ 2248static void 2249fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2250{ 2251 struct fxp_softc *sc = ifp->if_softc; 2252 struct mii_data *mii; 2253 2254 mii = device_get_softc(sc->miibus); 2255 mii_pollstat(mii); 2256 ifmr->ifm_active = mii->mii_media_active; 2257 ifmr->ifm_status = mii->mii_media_status; 2258 2259 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2260 sc->cu_resume_bug = 1; 2261 else 2262 sc->cu_resume_bug = 0; 2263} 2264 2265/* 2266 * Add a buffer to the end of the RFA buffer list. 2267 * Return 0 if successful, 1 for failure. A failure results in 2268 * adding the 'oldm' (if non-NULL) on to the end of the list - 2269 * tossing out its old contents and recycling it. 2270 * The RFA struct is stuck at the beginning of mbuf cluster and the 2271 * data pointer is fixed up to point just past it. 2272 */ 2273static int 2274fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2275{ 2276 struct mbuf *m; 2277 struct fxp_rfa *rfa, *p_rfa; 2278 struct fxp_rx *p_rx; 2279 bus_dmamap_t tmp_map; 2280 int error; 2281 2282 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2283 if (m == NULL) 2284 return (ENOBUFS); 2285 2286 /* 2287 * Move the data pointer up so that the incoming data packet 2288 * will be 32-bit aligned. 2289 */ 2290 m->m_data += RFA_ALIGNMENT_FUDGE; 2291 2292 /* 2293 * Get a pointer to the base of the mbuf cluster and move 2294 * data start past it. 2295 */ 2296 rfa = mtod(m, struct fxp_rfa *); 2297 m->m_data += sc->rfa_size; 2298 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2299 2300 rfa->rfa_status = 0; 2301 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2302 rfa->actual_size = 0; 2303 2304 /* 2305 * Initialize the rest of the RFA. Note that since the RFA 2306 * is misaligned, we cannot store values directly. We're thus 2307 * using the le32enc() function which handles endianness and 2308 * is also alignment-safe. 2309 */ 2310 le32enc(&rfa->link_addr, 0xffffffff); 2311 le32enc(&rfa->rbd_addr, 0xffffffff); 2312 2313 /* Map the RFA into DMA memory. */ 2314 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2315 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2316 &rxp->rx_addr, 0); 2317 if (error) { 2318 m_freem(m); 2319 return (error); 2320 } 2321 2322 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2323 tmp_map = sc->spare_map; 2324 sc->spare_map = rxp->rx_map; 2325 rxp->rx_map = tmp_map; 2326 rxp->rx_mbuf = m; 2327 2328 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2330 2331 /* 2332 * If there are other buffers already on the list, attach this 2333 * one to the end by fixing up the tail to point to this one. 2334 */ 2335 if (sc->fxp_desc.rx_head != NULL) { 2336 p_rx = sc->fxp_desc.rx_tail; 2337 p_rfa = (struct fxp_rfa *) 2338 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2339 p_rx->rx_next = rxp; 2340 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2341 p_rfa->rfa_control = 0; 2342 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2343 BUS_DMASYNC_PREWRITE); 2344 } else { 2345 rxp->rx_next = NULL; 2346 sc->fxp_desc.rx_head = rxp; 2347 } 2348 sc->fxp_desc.rx_tail = rxp; 2349 return (0); 2350} 2351 2352static volatile int 2353fxp_miibus_readreg(device_t dev, int phy, int reg) 2354{ 2355 struct fxp_softc *sc = device_get_softc(dev); 2356 int count = 10000; 2357 int value; 2358 2359 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2360 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2361 2362 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2363 && count--) 2364 DELAY(10); 2365 2366 if (count <= 0) 2367 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2368 2369 return (value & 0xffff); 2370} 2371 2372static void 2373fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2374{ 2375 struct fxp_softc *sc = device_get_softc(dev); 2376 int count = 10000; 2377 2378 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2379 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2380 (value & 0xffff)); 2381 2382 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2383 count--) 2384 DELAY(10); 2385 2386 if (count <= 0) 2387 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2388} 2389 2390static int 2391fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2392{ 2393 struct fxp_softc *sc = ifp->if_softc; 2394 struct ifreq *ifr = (struct ifreq *)data; 2395 struct mii_data *mii; 2396 int flag, mask, s, error = 0; 2397 2398 /* 2399 * Detaching causes us to call ioctl with the mutex owned. Preclude 2400 * that by saying we're busy if the lock is already held. 2401 */ 2402 if (FXP_LOCKED(sc)) 2403 return (EBUSY); 2404 2405 FXP_LOCK(sc); 2406 s = splimp(); 2407 2408 switch (command) { 2409 case SIOCSIFFLAGS: 2410 if (ifp->if_flags & IFF_ALLMULTI) 2411 sc->flags |= FXP_FLAG_ALL_MCAST; 2412 else 2413 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2414 2415 /* 2416 * If interface is marked up and not running, then start it. 2417 * If it is marked down and running, stop it. 2418 * XXX If it's up then re-initialize it. This is so flags 2419 * such as IFF_PROMISC are handled. 2420 */ 2421 if (ifp->if_flags & IFF_UP) { 2422 fxp_init_body(sc); 2423 } else { 2424 if (ifp->if_flags & IFF_RUNNING) 2425 fxp_stop(sc); 2426 } 2427 break; 2428 2429 case SIOCADDMULTI: 2430 case SIOCDELMULTI: 2431 if (ifp->if_flags & IFF_ALLMULTI) 2432 sc->flags |= FXP_FLAG_ALL_MCAST; 2433 else 2434 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2435 /* 2436 * Multicast list has changed; set the hardware filter 2437 * accordingly. 2438 */ 2439 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2440 fxp_mc_setup(sc); 2441 /* 2442 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2443 * again rather than else {}. 2444 */ 2445 if (sc->flags & FXP_FLAG_ALL_MCAST) 2446 fxp_init_body(sc); 2447 error = 0; 2448 break; 2449 2450 case SIOCSIFMEDIA: 2451 case SIOCGIFMEDIA: 2452 if (sc->miibus != NULL) { 2453 mii = device_get_softc(sc->miibus); 2454 error = ifmedia_ioctl(ifp, ifr, 2455 &mii->mii_media, command); 2456 } else { 2457 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2458 } 2459 break; 2460 2461 case SIOCSIFCAP: 2462 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2463 if (mask & IFCAP_POLLING) 2464 ifp->if_capenable ^= IFCAP_POLLING; 2465 if (mask & IFCAP_VLAN_MTU) { 2466 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2467 if (sc->revision != FXP_REV_82557) 2468 flag = FXP_FLAG_LONG_PKT_EN; 2469 else /* a hack to get long frames on the old chip */ 2470 flag = FXP_FLAG_SAVE_BAD; 2471 sc->flags ^= flag; 2472 if (ifp->if_flags & IFF_UP) 2473 fxp_init_body(sc); 2474 } 2475 break; 2476 2477 default: 2478 /* 2479 * ether_ioctl() will eventually call fxp_start() which 2480 * will result in mutex recursion so drop it first. 2481 */ 2482 FXP_UNLOCK(sc); 2483 error = ether_ioctl(ifp, command, data); 2484 } 2485 if (FXP_LOCKED(sc)) 2486 FXP_UNLOCK(sc); 2487 splx(s); 2488 return (error); 2489} 2490 2491/* 2492 * Fill in the multicast address list and return number of entries. 2493 */ 2494static int 2495fxp_mc_addrs(struct fxp_softc *sc) 2496{ 2497 struct fxp_cb_mcs *mcsp = sc->mcsp; 2498 struct ifnet *ifp = &sc->sc_if; 2499 struct ifmultiaddr *ifma; 2500 int nmcasts; 2501 2502 nmcasts = 0; 2503 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2504#if __FreeBSD_version < 500000 2505 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2506#else 2507 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2508#endif 2509 if (ifma->ifma_addr->sa_family != AF_LINK) 2510 continue; 2511 if (nmcasts >= MAXMCADDR) { 2512 sc->flags |= FXP_FLAG_ALL_MCAST; 2513 nmcasts = 0; 2514 break; 2515 } 2516 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2517 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2518 nmcasts++; 2519 } 2520 } 2521 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2522 return (nmcasts); 2523} 2524 2525/* 2526 * Program the multicast filter. 2527 * 2528 * We have an artificial restriction that the multicast setup command 2529 * must be the first command in the chain, so we take steps to ensure 2530 * this. By requiring this, it allows us to keep up the performance of 2531 * the pre-initialized command ring (esp. link pointers) by not actually 2532 * inserting the mcsetup command in the ring - i.e. its link pointer 2533 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2534 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2535 * lead into the regular TxCB ring when it completes. 2536 * 2537 * This function must be called at splimp. 2538 */ 2539static void 2540fxp_mc_setup(struct fxp_softc *sc) 2541{ 2542 struct fxp_cb_mcs *mcsp = sc->mcsp; 2543 struct ifnet *ifp = &sc->sc_if; 2544 struct fxp_tx *txp; 2545 int count; 2546 2547 FXP_LOCK_ASSERT(sc, MA_OWNED); 2548 /* 2549 * If there are queued commands, we must wait until they are all 2550 * completed. If we are already waiting, then add a NOP command 2551 * with interrupt option so that we're notified when all commands 2552 * have been completed - fxp_start() ensures that no additional 2553 * TX commands will be added when need_mcsetup is true. 2554 */ 2555 if (sc->tx_queued) { 2556 /* 2557 * need_mcsetup will be true if we are already waiting for the 2558 * NOP command to be completed (see below). In this case, bail. 2559 */ 2560 if (sc->need_mcsetup) 2561 return; 2562 sc->need_mcsetup = 1; 2563 2564 /* 2565 * Add a NOP command with interrupt so that we are notified 2566 * when all TX commands have been processed. 2567 */ 2568 txp = sc->fxp_desc.tx_last->tx_next; 2569 txp->tx_mbuf = NULL; 2570 txp->tx_cb->cb_status = 0; 2571 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2572 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2573 /* 2574 * Advance the end of list forward. 2575 */ 2576 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2577 htole16(~FXP_CB_COMMAND_S); 2578 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2579 sc->fxp_desc.tx_last = txp; 2580 sc->tx_queued++; 2581 /* 2582 * Issue a resume in case the CU has just suspended. 2583 */ 2584 fxp_scb_wait(sc); 2585 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2586 /* 2587 * Set a 5 second timer just in case we don't hear from the 2588 * card again. 2589 */ 2590 ifp->if_timer = 5; 2591 2592 return; 2593 } 2594 sc->need_mcsetup = 0; 2595 2596 /* 2597 * Initialize multicast setup descriptor. 2598 */ 2599 mcsp->cb_status = 0; 2600 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2601 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2602 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2603 txp = &sc->fxp_desc.mcs_tx; 2604 txp->tx_mbuf = NULL; 2605 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2606 txp->tx_next = sc->fxp_desc.tx_list; 2607 (void) fxp_mc_addrs(sc); 2608 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2609 sc->tx_queued = 1; 2610 2611 /* 2612 * Wait until command unit is not active. This should never 2613 * be the case when nothing is queued, but make sure anyway. 2614 */ 2615 count = 100; 2616 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2617 FXP_SCB_CUS_ACTIVE && --count) 2618 DELAY(10); 2619 if (count == 0) { 2620 device_printf(sc->dev, "command queue timeout\n"); 2621 return; 2622 } 2623 2624 /* 2625 * Start the multicast setup command. 2626 */ 2627 fxp_scb_wait(sc); 2628 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2629 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2630 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2631 2632 ifp->if_timer = 2; 2633 return; 2634} 2635 2636static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2637static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2638static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2639static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2640static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2641static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2642 2643#define UCODE(x) x, sizeof(x) 2644 2645struct ucode { 2646 u_int32_t revision; 2647 u_int32_t *ucode; 2648 int length; 2649 u_short int_delay_offset; 2650 u_short bundle_max_offset; 2651} ucode_table[] = { 2652 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2653 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2654 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2655 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2656 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2657 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2658 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2659 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2660 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2661 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2662 { 0, NULL, 0, 0, 0 } 2663}; 2664 2665static void 2666fxp_load_ucode(struct fxp_softc *sc) 2667{ 2668 struct ucode *uc; 2669 struct fxp_cb_ucode *cbp; 2670 2671 for (uc = ucode_table; uc->ucode != NULL; uc++) 2672 if (sc->revision == uc->revision) 2673 break; 2674 if (uc->ucode == NULL) 2675 return; 2676 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2677 cbp->cb_status = 0; 2678 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2679 cbp->link_addr = 0xffffffff; /* (no) next command */ 2680 memcpy(cbp->ucode, uc->ucode, uc->length); 2681 if (uc->int_delay_offset) 2682 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2683 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2684 if (uc->bundle_max_offset) 2685 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2686 htole16(sc->tunable_bundle_max); 2687 /* 2688 * Download the ucode to the chip. 2689 */ 2690 fxp_scb_wait(sc); 2691 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2692 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2693 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2694 /* ...and wait for it to complete. */ 2695 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2696 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2697 device_printf(sc->dev, 2698 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2699 sc->tunable_int_delay, 2700 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2701 sc->flags |= FXP_FLAG_UCODE; 2702} 2703 2704static int 2705sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2706{ 2707 int error, value; 2708 2709 value = *(int *)arg1; 2710 error = sysctl_handle_int(oidp, &value, 0, req); 2711 if (error || !req->newptr) 2712 return (error); 2713 if (value < low || value > high) 2714 return (EINVAL); 2715 *(int *)arg1 = value; 2716 return (0); 2717} 2718 2719/* 2720 * Interrupt delay is expressed in microseconds, a multiplier is used 2721 * to convert this to the appropriate clock ticks before using. 2722 */ 2723static int 2724sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2725{ 2726 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2727} 2728 2729static int 2730sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2731{ 2732 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2733} 2734