if_fxp.c revision 130020
1321936Shselasky/*- 2321936Shselasky * Copyright (c) 1995, David Greenman 3321936Shselasky * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4321936Shselasky * All rights reserved. 5321936Shselasky * 6321936Shselasky * Redistribution and use in source and binary forms, with or without 7321936Shselasky * modification, are permitted provided that the following conditions 8321936Shselasky * are met: 9321936Shselasky * 1. Redistributions of source code must retain the above copyright 10321936Shselasky * notice unmodified, this list of conditions, and the following 11321936Shselasky * disclaimer. 12321936Shselasky * 2. Redistributions in binary form must reproduce the above copyright 13321936Shselasky * notice, this list of conditions and the following disclaimer in the 14321936Shselasky * documentation and/or other materials provided with the distribution. 15321936Shselasky * 16321936Shselasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17321936Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18321936Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19321936Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20321936Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21321936Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22321936Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23321936Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24321936Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25321936Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26321936Shselasky * SUCH DAMAGE. 27321936Shselasky * 28321936Shselasky */ 29321936Shselasky 30321936Shselasky#include <sys/cdefs.h> 31321936Shselasky__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 130020 2004-06-02 22:59:57Z mux $"); 32321936Shselasky 33321936Shselasky/* 34321936Shselasky * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35321936Shselasky */ 36321936Shselasky 37321936Shselasky#include <sys/param.h> 38321936Shselasky#include <sys/systm.h> 39321936Shselasky#include <sys/endian.h> 40321936Shselasky#include <sys/mbuf.h> 41321936Shselasky /* #include <sys/mutex.h> */ 42321936Shselasky#include <sys/kernel.h> 43321936Shselasky#include <sys/module.h> 44321936Shselasky#include <sys/socket.h> 45321936Shselasky#include <sys/sysctl.h> 46321936Shselasky 47321936Shselasky#include <net/if.h> 48321936Shselasky#include <net/if_dl.h> 49321936Shselasky#include <net/if_media.h> 50321936Shselasky 51321936Shselasky#include <net/bpf.h> 52321936Shselasky#include <sys/sockio.h> 53321936Shselasky#include <sys/bus.h> 54321936Shselasky#include <machine/bus.h> 55321936Shselasky#include <sys/rman.h> 56321936Shselasky#include <machine/resource.h> 57321936Shselasky 58321936Shselasky#include <net/ethernet.h> 59321936Shselasky#include <net/if_arp.h> 60321936Shselasky 61321936Shselasky#include <machine/clock.h> /* for DELAY */ 62321936Shselasky 63321936Shselasky#include <net/if_types.h> 64321936Shselasky#include <net/if_vlan_var.h> 65321936Shselasky 66321936Shselasky#ifdef FXP_IP_CSUM_WAR 67321936Shselasky#include <netinet/in.h> 68321936Shselasky#include <netinet/in_systm.h> 69321936Shselasky#include <netinet/ip.h> 70321936Shselasky#include <machine/in_cksum.h> 71321936Shselasky#endif 72321936Shselasky 73321936Shselasky#include <dev/pci/pcivar.h> 74321936Shselasky#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75321936Shselasky 76321936Shselasky#include <dev/mii/mii.h> 77321936Shselasky#include <dev/mii/miivar.h> 78321936Shselasky 79321936Shselasky#include <dev/fxp/if_fxpreg.h> 80321936Shselasky#include <dev/fxp/if_fxpvar.h> 81321936Shselasky#include <dev/fxp/rcvbundl.h> 82321936Shselasky 83321936ShselaskyMODULE_DEPEND(fxp, pci, 1, 1, 1); 84321936ShselaskyMODULE_DEPEND(fxp, ether, 1, 1, 1); 85321936ShselaskyMODULE_DEPEND(fxp, miibus, 1, 1, 1); 86321936Shselasky#include "miibus_if.h" 87321936Shselasky 88321936Shselasky/* 89321936Shselasky * NOTE! On the Alpha, we have an alignment constraint. The 90321936Shselasky * card DMAs the packet immediately following the RFA. However, 91321936Shselasky * the first thing in the packet is a 14-byte Ethernet header. 92321936Shselasky * This means that the packet is misaligned. To compensate, 93321936Shselasky * we actually offset the RFA 2 bytes into the cluster. This 94321936Shselasky * alignes the packet after the Ethernet header at a 32-bit 95321936Shselasky * boundary. HOWEVER! This means that the RFA is misaligned! 96321936Shselasky */ 97321936Shselasky#define RFA_ALIGNMENT_FUDGE 2 98321936Shselasky 99321936Shselasky/* 100321936Shselasky * Set initial transmit threshold at 64 (512 bytes). This is 101321936Shselasky * increased by 64 (512 bytes) at a time, to maximum of 192 102321936Shselasky * (1536 bytes), if an underrun occurs. 103321936Shselasky */ 104321936Shselaskystatic int tx_threshold = 64; 105321936Shselasky 106321936Shselasky/* 107321936Shselasky * The configuration byte map has several undefined fields which 108321936Shselasky * must be one or must be zero. Set up a template for these bits 109321936Shselasky * only, (assuming a 82557 chip) leaving the actual configuration 110321936Shselasky * to fxp_init. 111321936Shselasky * 112321936Shselasky * See struct fxp_cb_config for the bit definitions. 113321936Shselasky */ 114321936Shselaskystatic u_char fxp_cb_config_template[] = { 115321936Shselasky 0x0, 0x0, /* cb_status */ 116321936Shselasky 0x0, 0x0, /* cb_command */ 117321936Shselasky 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118321936Shselasky 0x0, /* 0 */ 119321936Shselasky 0x0, /* 1 */ 120321936Shselasky 0x0, /* 2 */ 121321936Shselasky 0x0, /* 3 */ 122321936Shselasky 0x0, /* 4 */ 123321936Shselasky 0x0, /* 5 */ 124321936Shselasky 0x32, /* 6 */ 125321936Shselasky 0x0, /* 7 */ 126321936Shselasky 0x0, /* 8 */ 127321936Shselasky 0x0, /* 9 */ 128321936Shselasky 0x6, /* 10 */ 129321936Shselasky 0x0, /* 11 */ 130321936Shselasky 0x0, /* 12 */ 131321936Shselasky 0x0, /* 13 */ 132321936Shselasky 0xf2, /* 14 */ 133321936Shselasky 0x48, /* 15 */ 134321936Shselasky 0x0, /* 16 */ 135321936Shselasky 0x40, /* 17 */ 136321936Shselasky 0xf0, /* 18 */ 137321936Shselasky 0x0, /* 19 */ 138321936Shselasky 0x3f, /* 20 */ 139321936Shselasky 0x5 /* 21 */ 140321936Shselasky}; 141321936Shselasky 142321936Shselaskystruct fxp_ident { 143321936Shselasky u_int16_t devid; 144321936Shselasky int16_t revid; /* -1 matches anything */ 145321936Shselasky char *name; 146321936Shselasky}; 147321936Shselasky 148321936Shselasky/* 149321936Shselasky * Claim various Intel PCI device identifiers for this driver. The 150321936Shselasky * sub-vendor and sub-device field are extensively used to identify 151321936Shselasky * particular variants, but we don't currently differentiate between 152321936Shselasky * them. 153321936Shselasky */ 154321936Shselaskystatic struct fxp_ident fxp_ident_table[] = { 155321936Shselasky { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156321936Shselasky { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157321936Shselasky { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158321936Shselasky { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159321936Shselasky { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160321936Shselasky { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161321936Shselasky { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162321936Shselasky { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163321936Shselasky { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164321936Shselasky { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165321936Shselasky { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166321936Shselasky { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167321936Shselasky { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168321936Shselasky { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169321936Shselasky { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170321936Shselasky { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171321936Shselasky { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172321936Shselasky { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173321936Shselasky { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174321936Shselasky { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 175321936Shselasky { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 176321936Shselasky { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 177321936Shselasky { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 178321936Shselasky { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 179321936Shselasky { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 180321936Shselasky { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 181321936Shselasky { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 182321936Shselasky { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 183321936Shselasky { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 184321936Shselasky { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 185321936Shselasky { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 186321936Shselasky { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 187321936Shselasky { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 188321936Shselasky { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 189321936Shselasky { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 190321936Shselasky { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 191321936Shselasky { 0, -1, NULL }, 192321936Shselasky}; 193321936Shselasky 194321936Shselasky#ifdef FXP_IP_CSUM_WAR 195321936Shselasky#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 196321936Shselasky#else 197321936Shselasky#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 198321936Shselasky#endif 199321936Shselasky 200321936Shselaskystatic int fxp_probe(device_t dev); 201321936Shselaskystatic int fxp_attach(device_t dev); 202321936Shselaskystatic int fxp_detach(device_t dev); 203321936Shselaskystatic int fxp_shutdown(device_t dev); 204321936Shselaskystatic int fxp_suspend(device_t dev); 205321936Shselaskystatic int fxp_resume(device_t dev); 206321936Shselasky 207321936Shselaskystatic void fxp_intr(void *xsc); 208321936Shselaskystatic void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 209321936Shselasky u_int8_t statack, int count); 210321936Shselaskystatic void fxp_init(void *xsc); 211321936Shselaskystatic void fxp_init_body(struct fxp_softc *sc); 212321936Shselaskystatic void fxp_tick(void *xsc); 213321936Shselasky#ifndef BURN_BRIDGES 214321936Shselaskystatic void fxp_powerstate_d0(device_t dev); 215321936Shselasky#endif 216321936Shselaskystatic void fxp_start(struct ifnet *ifp); 217321936Shselaskystatic void fxp_start_body(struct ifnet *ifp); 218321936Shselaskystatic void fxp_stop(struct fxp_softc *sc); 219321936Shselaskystatic void fxp_release(struct fxp_softc *sc); 220321936Shselaskystatic int fxp_ioctl(struct ifnet *ifp, u_long command, 221321936Shselasky caddr_t data); 222321936Shselaskystatic void fxp_watchdog(struct ifnet *ifp); 223321936Shselaskystatic int fxp_add_rfabuf(struct fxp_softc *sc, 224321936Shselasky struct fxp_rx *rxp); 225321936Shselaskystatic int fxp_mc_addrs(struct fxp_softc *sc); 226321936Shselaskystatic void fxp_mc_setup(struct fxp_softc *sc); 227321936Shselaskystatic u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228321936Shselasky int autosize); 229321936Shselaskystatic void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230321936Shselasky u_int16_t data); 231321936Shselaskystatic void fxp_autosize_eeprom(struct fxp_softc *sc); 232321936Shselaskystatic void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233321936Shselasky int offset, int words); 234321936Shselaskystatic void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235321936Shselasky int offset, int words); 236321936Shselaskystatic int fxp_ifmedia_upd(struct ifnet *ifp); 237321936Shselaskystatic void fxp_ifmedia_sts(struct ifnet *ifp, 238321936Shselasky struct ifmediareq *ifmr); 239321936Shselaskystatic int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240321936Shselaskystatic void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241321936Shselasky struct ifmediareq *ifmr); 242321936Shselaskystatic volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243321936Shselaskystatic void fxp_miibus_writereg(device_t dev, int phy, int reg, 244321936Shselasky int value); 245321936Shselaskystatic void fxp_load_ucode(struct fxp_softc *sc); 246321936Shselaskystatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247321936Shselasky int low, int high); 248321936Shselaskystatic int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249321936Shselaskystatic int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250321936Shselaskystatic void fxp_scb_wait(struct fxp_softc *sc); 251321936Shselaskystatic void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252321936Shselaskystatic void fxp_dma_wait(struct fxp_softc *sc, 253321936Shselasky volatile u_int16_t *status, bus_dma_tag_t dmat, 254321936Shselasky bus_dmamap_t map); 255321936Shselasky 256321936Shselaskystatic device_method_t fxp_methods[] = { 257321936Shselasky /* Device interface */ 258321936Shselasky DEVMETHOD(device_probe, fxp_probe), 259321936Shselasky DEVMETHOD(device_attach, fxp_attach), 260321936Shselasky DEVMETHOD(device_detach, fxp_detach), 261321936Shselasky DEVMETHOD(device_shutdown, fxp_shutdown), 262321936Shselasky DEVMETHOD(device_suspend, fxp_suspend), 263321936Shselasky DEVMETHOD(device_resume, fxp_resume), 264321936Shselasky 265321936Shselasky /* MII interface */ 266321936Shselasky DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267321936Shselasky DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268321936Shselasky 269321936Shselasky { 0, 0 } 270321936Shselasky}; 271321936Shselasky 272321936Shselaskystatic driver_t fxp_driver = { 273321936Shselasky "fxp", 274321936Shselasky fxp_methods, 275321936Shselasky sizeof(struct fxp_softc), 276321936Shselasky}; 277321936Shselasky 278321936Shselaskystatic devclass_t fxp_devclass; 279321936Shselasky 280321936ShselaskyDRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281321936ShselaskyDRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282321936ShselaskyDRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283321936Shselasky 284321936Shselasky/* 285321936Shselasky * Wait for the previous command to be accepted (but not necessarily 286321936Shselasky * completed). 287321936Shselasky */ 288321936Shselaskystatic void 289321936Shselaskyfxp_scb_wait(struct fxp_softc *sc) 290321936Shselasky{ 291321936Shselasky int i = 10000; 292321936Shselasky 293321936Shselasky while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294321936Shselasky DELAY(2); 295321936Shselasky if (i == 0) 296321936Shselasky device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297321936Shselasky CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298321936Shselasky CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299321936Shselasky CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300321936Shselasky CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301321936Shselasky} 302321936Shselasky 303321936Shselaskystatic void 304321936Shselaskyfxp_scb_cmd(struct fxp_softc *sc, int cmd) 305321936Shselasky{ 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312} 313 314static void 315fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317{ 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327} 328 329/* 330 * Return identification string if this device is ours. 331 */ 332static int 333fxp_probe(device_t dev) 334{ 335 u_int16_t devid; 336 u_int8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (0); 347 } 348 } 349 } 350 return (ENXIO); 351} 352 353#ifndef BURN_BRIDGES 354static void 355fxp_powerstate_d0(device_t dev) 356{ 357#if __FreeBSD_version >= 430002 358 u_int32_t iobase, membase, irq; 359 360 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 361 /* Save important PCI config data. */ 362 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 363 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 364 irq = pci_read_config(dev, PCIR_INTLINE, 4); 365 366 /* Reset the power state. */ 367 device_printf(dev, "chip is in D%d power mode " 368 "-- setting to D0\n", pci_get_powerstate(dev)); 369 370 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 371 372 /* Restore PCI config data. */ 373 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 374 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 375 pci_write_config(dev, PCIR_INTLINE, irq, 4); 376 } 377#endif 378} 379#endif 380 381static void 382fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 383{ 384 u_int32_t *addr; 385 386 if (error) 387 return; 388 389 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 390 addr = arg; 391 *addr = segs->ds_addr; 392} 393 394static int 395fxp_attach(device_t dev) 396{ 397 int error = 0; 398 struct fxp_softc *sc = device_get_softc(dev); 399 struct ifnet *ifp; 400 struct fxp_rx *rxp; 401 u_int32_t val; 402 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 403 int i, rid, m1, m2, prefer_iomap, maxtxseg; 404 int s, ipcbxmit_disable; 405 406 sc->dev = dev; 407 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 408 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 409 MTX_DEF); 410 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 411 fxp_serial_ifmedia_sts); 412 413 s = splimp(); 414 415 /* 416 * Enable bus mastering. 417 */ 418 pci_enable_busmaster(dev); 419 val = pci_read_config(dev, PCIR_COMMAND, 2); 420#ifndef BURN_BRIDGES 421 fxp_powerstate_d0(dev); 422#endif 423 /* 424 * Figure out which we should try first - memory mapping or i/o mapping? 425 * We default to memory mapping. Then we accept an override from the 426 * command line. Then we check to see which one is enabled. 427 */ 428 m1 = PCIM_CMD_MEMEN; 429 m2 = PCIM_CMD_PORTEN; 430 prefer_iomap = 0; 431 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 432 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 433 m1 = PCIM_CMD_PORTEN; 434 m2 = PCIM_CMD_MEMEN; 435 } 436 437 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 438 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 439 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 440 if (sc->mem == NULL) { 441 sc->rtp = 442 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 443 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 444 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 445 RF_ACTIVE); 446 } 447 448 if (!sc->mem) { 449 error = ENXIO; 450 goto fail; 451 } 452 if (bootverbose) { 453 device_printf(dev, "using %s space register mapping\n", 454 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 455 } 456 457 sc->sc_st = rman_get_bustag(sc->mem); 458 sc->sc_sh = rman_get_bushandle(sc->mem); 459 460 /* 461 * Allocate our interrupt. 462 */ 463 rid = 0; 464 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 465 RF_SHAREABLE | RF_ACTIVE); 466 if (sc->irq == NULL) { 467 device_printf(dev, "could not map interrupt\n"); 468 error = ENXIO; 469 goto fail; 470 } 471 472 /* 473 * Reset to a stable state. 474 */ 475 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 476 DELAY(10); 477 478 /* 479 * Find out how large of an SEEPROM we have. 480 */ 481 fxp_autosize_eeprom(sc); 482 483 /* 484 * Determine whether we must use the 503 serial interface. 485 */ 486 fxp_read_eeprom(sc, &data, 6, 1); 487 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 488 (data & FXP_PHY_SERIAL_ONLY)) 489 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 490 491 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 492 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 493 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 494 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 495 "FXP driver receive interrupt microcode bundling delay"); 496 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 497 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 498 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 499 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 500 "FXP driver receive interrupt microcode bundle size limit"); 501 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 502 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 503 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 504 "FXP RNR events"); 505 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 506 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 507 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 508 "FXP flow control disabled"); 509 510 /* 511 * Pull in device tunables. 512 */ 513 sc->tunable_int_delay = TUNABLE_INT_DELAY; 514 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 515 sc->tunable_noflow = 0; 516 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 517 "int_delay", &sc->tunable_int_delay); 518 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 519 "bundle_max", &sc->tunable_bundle_max); 520 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 521 "noflow", &sc->tunable_noflow); 522 sc->rnr = 0; 523 524 /* 525 * Find out the chip revision; lump all 82557 revs together. 526 */ 527 fxp_read_eeprom(sc, &data, 5, 1); 528 if ((data >> 8) == 1) 529 sc->revision = FXP_REV_82557; 530 else 531 sc->revision = pci_get_revid(dev); 532 533 /* 534 * Enable workarounds for certain chip revision deficiencies. 535 * 536 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 537 * some systems based a normal 82559 design, have a defect where 538 * the chip can cause a PCI protocol violation if it receives 539 * a CU_RESUME command when it is entering the IDLE state. The 540 * workaround is to disable Dynamic Standby Mode, so the chip never 541 * deasserts CLKRUN#, and always remains in an active state. 542 * 543 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 544 */ 545 i = pci_get_device(dev); 546 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 547 sc->revision >= FXP_REV_82559_A0) { 548 fxp_read_eeprom(sc, &data, 10, 1); 549 if (data & 0x02) { /* STB enable */ 550 u_int16_t cksum; 551 int i; 552 553 device_printf(dev, 554 "Disabling dynamic standby mode in EEPROM\n"); 555 data &= ~0x02; 556 fxp_write_eeprom(sc, &data, 10, 1); 557 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 558 cksum = 0; 559 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 560 fxp_read_eeprom(sc, &data, i, 1); 561 cksum += data; 562 } 563 i = (1 << sc->eeprom_size) - 1; 564 cksum = 0xBABA - cksum; 565 fxp_read_eeprom(sc, &data, i, 1); 566 fxp_write_eeprom(sc, &cksum, i, 1); 567 device_printf(dev, 568 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 569 i, data, cksum); 570#if 1 571 /* 572 * If the user elects to continue, try the software 573 * workaround, as it is better than nothing. 574 */ 575 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 576#endif 577 } 578 } 579 580 /* 581 * If we are not a 82557 chip, we can enable extended features. 582 */ 583 if (sc->revision != FXP_REV_82557) { 584 /* 585 * If MWI is enabled in the PCI configuration, and there 586 * is a valid cacheline size (8 or 16 dwords), then tell 587 * the board to turn on MWI. 588 */ 589 if (val & PCIM_CMD_MWRICEN && 590 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 591 sc->flags |= FXP_FLAG_MWI_ENABLE; 592 593 /* turn on the extended TxCB feature */ 594 sc->flags |= FXP_FLAG_EXT_TXCB; 595 596 /* enable reception of long frames for VLAN */ 597 sc->flags |= FXP_FLAG_LONG_PKT_EN; 598 } else { 599 /* a hack to get long VLAN frames on a 82557 */ 600 sc->flags |= FXP_FLAG_SAVE_BAD; 601 } 602 603 /* 604 * Enable use of extended RFDs and TCBs for 82550 605 * and later chips. Note: we need extended TXCB support 606 * too, but that's already enabled by the code above. 607 * Be careful to do this only on the right devices. 608 * 609 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 610 * truncate packets that end with an mbuf containing 1 to 3 bytes 611 * when used with this feature enabled in the previous version of the 612 * driver. This problem appears to be fixed now that the driver 613 * always sets the hardware parse bit in the IPCB structure, which 614 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 615 * Source Software Developer Manual" says is necessary in the 616 * cases where packet truncation was observed. 617 * 618 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 619 * allows this feature to be disabled at boot time. 620 * 621 * If fxp is not compiled into the kernel, this feature may also 622 * be disabled at run time: 623 * # kldunload fxp 624 * # kenv hint.fxp.0.ipcbxmit_disable=1 625 * # kldload fxp 626 */ 627 628 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 629 &ipcbxmit_disable) != 0) 630 ipcbxmit_disable = 0; 631 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 632 sc->revision == FXP_REV_82550_C)) { 633 sc->rfa_size = sizeof (struct fxp_rfa); 634 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 635 sc->flags |= FXP_FLAG_EXT_RFA; 636 } else { 637 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 638 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 639 } 640 641 /* 642 * Allocate DMA tags and DMA safe memory. 643 */ 644 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 645 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 646 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 647 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 648 if (error) { 649 device_printf(dev, "could not allocate dma tag\n"); 650 goto fail; 651 } 652 653 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 654 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 655 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 656 &sc->fxp_stag); 657 if (error) { 658 device_printf(dev, "could not allocate dma tag\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 663 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 664 if (error) 665 goto fail; 666 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 667 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 668 if (error) { 669 device_printf(dev, "could not map the stats buffer\n"); 670 goto fail; 671 } 672 673 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 674 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 675 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 676 if (error) { 677 device_printf(dev, "could not allocate dma tag\n"); 678 goto fail; 679 } 680 681 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 682 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 683 if (error) 684 goto fail; 685 686 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 687 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 688 &sc->fxp_desc.cbl_addr, 0); 689 if (error) { 690 device_printf(dev, "could not map DMA memory\n"); 691 goto fail; 692 } 693 694 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 695 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 696 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 697 &sc->mcs_tag); 698 if (error) { 699 device_printf(dev, "could not allocate dma tag\n"); 700 goto fail; 701 } 702 703 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 704 BUS_DMA_NOWAIT, &sc->mcs_map); 705 if (error) 706 goto fail; 707 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 708 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 709 if (error) { 710 device_printf(dev, "can't map the multicast setup command\n"); 711 goto fail; 712 } 713 714 /* 715 * Pre-allocate the TX DMA maps. 716 */ 717 for (i = 0; i < FXP_NTXCB; i++) { 718 error = bus_dmamap_create(sc->fxp_mtag, 0, 719 &sc->fxp_desc.tx_list[i].tx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for TX\n"); 722 goto fail; 723 } 724 } 725 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 726 if (error) { 727 device_printf(dev, "can't create spare DMA map\n"); 728 goto fail; 729 } 730 731 /* 732 * Pre-allocate our receive buffers. 733 */ 734 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 735 for (i = 0; i < FXP_NRFABUFS; i++) { 736 rxp = &sc->fxp_desc.rx_list[i]; 737 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 738 if (error) { 739 device_printf(dev, "can't create DMA map for RX\n"); 740 goto fail; 741 } 742 if (fxp_add_rfabuf(sc, rxp) != 0) { 743 error = ENOMEM; 744 goto fail; 745 } 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 753 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 754 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 755 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 756 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 757 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 758 if (bootverbose) { 759 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 760 pci_get_vendor(dev), pci_get_device(dev), 761 pci_get_subvendor(dev), pci_get_subdevice(dev), 762 pci_get_revid(dev)); 763 fxp_read_eeprom(sc, &data, 10, 1); 764 device_printf(dev, "Dynamic Standby mode is %s\n", 765 data & 0x02 ? "enabled" : "disabled"); 766 } 767 768 /* 769 * If this is only a 10Mbps device, then there is no MII, and 770 * the PHY will use a serial interface instead. 771 * 772 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 773 * doesn't have a programming interface of any sort. The 774 * media is sensed automatically based on how the link partner 775 * is configured. This is, in essence, manual configuration. 776 */ 777 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 778 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 780 } else { 781 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 782 fxp_ifmedia_sts)) { 783 device_printf(dev, "MII without any PHY!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 } 788 789 ifp = &sc->arpcom.ac_if; 790 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 791 ifp->if_baudrate = 100000000; 792 ifp->if_init = fxp_init; 793 ifp->if_softc = sc; 794 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 795 ifp->if_ioctl = fxp_ioctl; 796 ifp->if_start = fxp_start; 797 ifp->if_watchdog = fxp_watchdog; 798 799 ifp->if_capabilities = ifp->if_capenable = 0; 800 801 /* Enable checksum offload for 82550 or better chips */ 802 if (sc->flags & FXP_FLAG_EXT_RFA) { 803 ifp->if_hwassist = FXP_CSUM_FEATURES; 804 ifp->if_capabilities |= IFCAP_HWCSUM; 805 ifp->if_capenable |= IFCAP_HWCSUM; 806 } 807 808#ifdef DEVICE_POLLING 809 /* Inform the world we support polling. */ 810 ifp->if_capabilities |= IFCAP_POLLING; 811 ifp->if_capenable |= IFCAP_POLLING; 812#endif 813 814 /* 815 * Attach the interface. 816 */ 817 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 818 819 /* 820 * Tell the upper layer(s) we support long frames. 821 * Must appear after the call to ether_ifattach() because 822 * ether_ifattach() sets ifi_hdrlen to the default value. 823 */ 824 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 825 ifp->if_capabilities |= IFCAP_VLAN_MTU; 826 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 827 828 /* 829 * Let the system queue as many packets as we have available 830 * TX descriptors. 831 */ 832 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 833 834 /* 835 * Hook our interrupt after all initialization is complete. 836 * XXX This driver has been tested with the INTR_MPSAFFE flag set 837 * however, ifp and its functions are not fully locked so MPSAFE 838 * should not be used unless you can handle potential data loss. 839 */ 840 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 841 fxp_intr, sc, &sc->ih); 842 if (error) { 843 device_printf(dev, "could not setup irq\n"); 844 ether_ifdetach(&sc->arpcom.ac_if); 845 goto fail; 846 } 847 848fail: 849 splx(s); 850 if (error) 851 fxp_release(sc); 852 return (error); 853} 854 855/* 856 * Release all resources. The softc lock should not be held and the 857 * interrupt should already be torn down. 858 */ 859static void 860fxp_release(struct fxp_softc *sc) 861{ 862 struct fxp_rx *rxp; 863 struct fxp_tx *txp; 864 int i; 865 866 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 867 KASSERT(sc->ih == NULL, 868 ("fxp_release() called with intr handle still active")); 869 if (sc->miibus) 870 device_delete_child(sc->dev, sc->miibus); 871 bus_generic_detach(sc->dev); 872 ifmedia_removeall(&sc->sc_media); 873 if (sc->fxp_desc.cbl_list) { 874 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 875 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 876 sc->cbl_map); 877 } 878 if (sc->fxp_stats) { 879 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 880 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 881 } 882 if (sc->mcsp) { 883 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 884 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 885 } 886 if (sc->irq) 887 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 888 if (sc->mem) 889 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 890 if (sc->fxp_mtag) { 891 for (i = 0; i < FXP_NRFABUFS; i++) { 892 rxp = &sc->fxp_desc.rx_list[i]; 893 if (rxp->rx_mbuf != NULL) { 894 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 895 BUS_DMASYNC_POSTREAD); 896 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 897 m_freem(rxp->rx_mbuf); 898 } 899 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 900 } 901 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 902 bus_dma_tag_destroy(sc->fxp_mtag); 903 } 904 if (sc->fxp_stag) { 905 for (i = 0; i < FXP_NTXCB; i++) { 906 txp = &sc->fxp_desc.tx_list[i]; 907 if (txp->tx_mbuf != NULL) { 908 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 909 BUS_DMASYNC_POSTWRITE); 910 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 911 m_freem(txp->tx_mbuf); 912 } 913 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 914 } 915 bus_dma_tag_destroy(sc->fxp_stag); 916 } 917 if (sc->cbl_tag) 918 bus_dma_tag_destroy(sc->cbl_tag); 919 if (sc->mcs_tag) 920 bus_dma_tag_destroy(sc->mcs_tag); 921 922 mtx_destroy(&sc->sc_mtx); 923} 924 925/* 926 * Detach interface. 927 */ 928static int 929fxp_detach(device_t dev) 930{ 931 struct fxp_softc *sc = device_get_softc(dev); 932 int s; 933 934 FXP_LOCK(sc); 935 s = splimp(); 936 937 sc->suspended = 1; /* Do same thing as we do for suspend */ 938 /* 939 * Close down routes etc. 940 */ 941 ether_ifdetach(&sc->arpcom.ac_if); 942 943 /* 944 * Stop DMA and drop transmit queue, but disable interrupts first. 945 */ 946 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 947 fxp_stop(sc); 948 FXP_UNLOCK(sc); 949 950 /* 951 * Unhook interrupt before dropping lock. This is to prevent 952 * races with fxp_intr(). 953 */ 954 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 955 sc->ih = NULL; 956 957 splx(s); 958 959 /* Release our allocated resources. */ 960 fxp_release(sc); 961 return (0); 962} 963 964/* 965 * Device shutdown routine. Called at system shutdown after sync. The 966 * main purpose of this routine is to shut off receiver DMA so that 967 * kernel memory doesn't get clobbered during warmboot. 968 */ 969static int 970fxp_shutdown(device_t dev) 971{ 972 /* 973 * Make sure that DMA is disabled prior to reboot. Not doing 974 * do could allow DMA to corrupt kernel memory during the 975 * reboot before the driver initializes. 976 */ 977 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 978 return (0); 979} 980 981/* 982 * Device suspend routine. Stop the interface and save some PCI 983 * settings in case the BIOS doesn't restore them properly on 984 * resume. 985 */ 986static int 987fxp_suspend(device_t dev) 988{ 989 struct fxp_softc *sc = device_get_softc(dev); 990 int i, s; 991 992 FXP_LOCK(sc); 993 s = splimp(); 994 995 fxp_stop(sc); 996 997 for (i = 0; i < 5; i++) 998 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 999 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1000 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1001 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1002 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1003 1004 sc->suspended = 1; 1005 1006 FXP_UNLOCK(sc); 1007 splx(s); 1008 return (0); 1009} 1010 1011/* 1012 * Device resume routine. Restore some PCI settings in case the BIOS 1013 * doesn't, re-enable busmastering, and restart the interface if 1014 * appropriate. 1015 */ 1016static int 1017fxp_resume(device_t dev) 1018{ 1019 struct fxp_softc *sc = device_get_softc(dev); 1020 struct ifnet *ifp = &sc->sc_if; 1021 u_int16_t pci_command; 1022 int i, s; 1023 1024 FXP_LOCK(sc); 1025 s = splimp(); 1026#ifndef BURN_BRIDGES 1027 fxp_powerstate_d0(dev); 1028#endif 1029 /* better way to do this? */ 1030 for (i = 0; i < 5; i++) 1031 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1032 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1033 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1034 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1035 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1036 1037 /* reenable busmastering */ 1038 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1039 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1040 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1041 1042 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1043 DELAY(10); 1044 1045 /* reinitialize interface if necessary */ 1046 if (ifp->if_flags & IFF_UP) 1047 fxp_init_body(sc); 1048 1049 sc->suspended = 0; 1050 1051 FXP_UNLOCK(sc); 1052 splx(s); 1053 return (0); 1054} 1055 1056static void 1057fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1058{ 1059 u_int16_t reg; 1060 int x; 1061 1062 /* 1063 * Shift in data. 1064 */ 1065 for (x = 1 << (length - 1); x; x >>= 1) { 1066 if (data & x) 1067 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1068 else 1069 reg = FXP_EEPROM_EECS; 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1071 DELAY(1); 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1073 DELAY(1); 1074 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1075 DELAY(1); 1076 } 1077} 1078 1079/* 1080 * Read from the serial EEPROM. Basically, you manually shift in 1081 * the read opcode (one bit at a time) and then shift in the address, 1082 * and then you shift out the data (all of this one bit at a time). 1083 * The word size is 16 bits, so you have to provide the address for 1084 * every 16 bits of data. 1085 */ 1086static u_int16_t 1087fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1088{ 1089 u_int16_t reg, data; 1090 int x; 1091 1092 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1093 /* 1094 * Shift in read opcode. 1095 */ 1096 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1097 /* 1098 * Shift in address. 1099 */ 1100 data = 0; 1101 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1102 if (offset & x) 1103 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1104 else 1105 reg = FXP_EEPROM_EECS; 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1107 DELAY(1); 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1109 DELAY(1); 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1111 DELAY(1); 1112 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1113 data++; 1114 if (autosize && reg == 0) { 1115 sc->eeprom_size = data; 1116 break; 1117 } 1118 } 1119 /* 1120 * Shift out data. 1121 */ 1122 data = 0; 1123 reg = FXP_EEPROM_EECS; 1124 for (x = 1 << 15; x; x >>= 1) { 1125 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1126 DELAY(1); 1127 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1128 data |= x; 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1130 DELAY(1); 1131 } 1132 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1133 DELAY(1); 1134 1135 return (data); 1136} 1137 1138static void 1139fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1140{ 1141 int i; 1142 1143 /* 1144 * Erase/write enable. 1145 */ 1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1147 fxp_eeprom_shiftin(sc, 0x4, 3); 1148 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1149 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1150 DELAY(1); 1151 /* 1152 * Shift in write opcode, address, data. 1153 */ 1154 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1155 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1156 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1157 fxp_eeprom_shiftin(sc, data, 16); 1158 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1159 DELAY(1); 1160 /* 1161 * Wait for EEPROM to finish up. 1162 */ 1163 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1164 DELAY(1); 1165 for (i = 0; i < 1000; i++) { 1166 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1167 break; 1168 DELAY(50); 1169 } 1170 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1171 DELAY(1); 1172 /* 1173 * Erase/write disable. 1174 */ 1175 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1176 fxp_eeprom_shiftin(sc, 0x4, 3); 1177 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1179 DELAY(1); 1180} 1181 1182/* 1183 * From NetBSD: 1184 * 1185 * Figure out EEPROM size. 1186 * 1187 * 559's can have either 64-word or 256-word EEPROMs, the 558 1188 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1189 * talks about the existance of 16 to 256 word EEPROMs. 1190 * 1191 * The only known sizes are 64 and 256, where the 256 version is used 1192 * by CardBus cards to store CIS information. 1193 * 1194 * The address is shifted in msb-to-lsb, and after the last 1195 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1196 * after which follows the actual data. We try to detect this zero, by 1197 * probing the data-out bit in the EEPROM control register just after 1198 * having shifted in a bit. If the bit is zero, we assume we've 1199 * shifted enough address bits. The data-out should be tri-state, 1200 * before this, which should translate to a logical one. 1201 */ 1202static void 1203fxp_autosize_eeprom(struct fxp_softc *sc) 1204{ 1205 1206 /* guess maximum size of 256 words */ 1207 sc->eeprom_size = 8; 1208 1209 /* autosize */ 1210 (void) fxp_eeprom_getword(sc, 0, 1); 1211} 1212 1213static void 1214fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1215{ 1216 int i; 1217 1218 for (i = 0; i < words; i++) 1219 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1220} 1221 1222static void 1223fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1224{ 1225 int i; 1226 1227 for (i = 0; i < words; i++) 1228 fxp_eeprom_putword(sc, offset + i, data[i]); 1229} 1230 1231static void 1232fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1233 bus_size_t mapsize, int error) 1234{ 1235 struct fxp_softc *sc; 1236 struct fxp_cb_tx *txp; 1237 int i; 1238 1239 if (error) 1240 return; 1241 1242 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1243 1244 sc = arg; 1245 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1246 for (i = 0; i < nseg; i++) { 1247 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1248 /* 1249 * If this is an 82550/82551, then we're using extended 1250 * TxCBs _and_ we're using checksum offload. This means 1251 * that the TxCB is really an IPCB. One major difference 1252 * between the two is that with plain extended TxCBs, 1253 * the bottom half of the TxCB contains two entries from 1254 * the TBD array, whereas IPCBs contain just one entry: 1255 * one entry (8 bytes) has been sacrificed for the TCP/IP 1256 * checksum offload control bits. So to make things work 1257 * right, we have to start filling in the TBD array 1258 * starting from a different place depending on whether 1259 * the chip is an 82550/82551 or not. 1260 */ 1261 if (sc->flags & FXP_FLAG_EXT_RFA) { 1262 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1263 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1264 } else { 1265 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1266 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1267 } 1268 } 1269 txp->tbd_number = nseg; 1270} 1271 1272/* 1273 * Grab the softc lock and call the real fxp_start_body() routine 1274 */ 1275static void 1276fxp_start(struct ifnet *ifp) 1277{ 1278 struct fxp_softc *sc = ifp->if_softc; 1279 1280 FXP_LOCK(sc); 1281 fxp_start_body(ifp); 1282 FXP_UNLOCK(sc); 1283} 1284 1285/* 1286 * Start packet transmission on the interface. 1287 * This routine must be called with the softc lock held, and is an 1288 * internal entry point only. 1289 */ 1290static void 1291fxp_start_body(struct ifnet *ifp) 1292{ 1293 struct fxp_softc *sc = ifp->if_softc; 1294 struct fxp_tx *txp; 1295 struct mbuf *mb_head; 1296 int error; 1297 1298 FXP_LOCK_ASSERT(sc, MA_OWNED); 1299 /* 1300 * See if we need to suspend xmit until the multicast filter 1301 * has been reprogrammed (which can only be done at the head 1302 * of the command chain). 1303 */ 1304 if (sc->need_mcsetup) { 1305 return; 1306 } 1307 1308 txp = NULL; 1309 1310 /* 1311 * We're finished if there is nothing more to add to the list or if 1312 * we're all filled up with buffers to transmit. 1313 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1314 * a NOP command when needed. 1315 */ 1316 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1317 1318 /* 1319 * Grab a packet to transmit. 1320 */ 1321 IF_DEQUEUE(&ifp->if_snd, mb_head); 1322 1323 /* 1324 * Get pointer to next available tx desc. 1325 */ 1326 txp = sc->fxp_desc.tx_last->tx_next; 1327 1328 /* 1329 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1330 * Ethernet Controller Family Open Source Software 1331 * Developer Manual says: 1332 * Using software parsing is only allowed with legal 1333 * TCP/IP or UDP/IP packets. 1334 * ... 1335 * For all other datagrams, hardware parsing must 1336 * be used. 1337 * Software parsing appears to truncate ICMP and 1338 * fragmented UDP packets that contain one to three 1339 * bytes in the second (and final) mbuf of the packet. 1340 */ 1341 if (sc->flags & FXP_FLAG_EXT_RFA) 1342 txp->tx_cb->ipcb_ip_activation_high = 1343 FXP_IPCB_HARDWAREPARSING_ENABLE; 1344 1345 /* 1346 * Deal with TCP/IP checksum offload. Note that 1347 * in order for TCP checksum offload to work, 1348 * the pseudo header checksum must have already 1349 * been computed and stored in the checksum field 1350 * in the TCP header. The stack should have 1351 * already done this for us. 1352 */ 1353 1354 if (mb_head->m_pkthdr.csum_flags) { 1355 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1356 txp->tx_cb->ipcb_ip_schedule = 1357 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1358 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1359 txp->tx_cb->ipcb_ip_schedule |= 1360 FXP_IPCB_TCP_PACKET; 1361 } 1362#ifdef FXP_IP_CSUM_WAR 1363 /* 1364 * XXX The 82550 chip appears to have trouble 1365 * dealing with IP header checksums in very small 1366 * datagrams, namely fragments from 1 to 3 bytes 1367 * in size. For example, say you want to transmit 1368 * a UDP packet of 1473 bytes. The packet will be 1369 * fragmented over two IP datagrams, the latter 1370 * containing only one byte of data. The 82550 will 1371 * botch the header checksum on the 1-byte fragment. 1372 * As long as the datagram contains 4 or more bytes 1373 * of data, you're ok. 1374 * 1375 * The following code attempts to work around this 1376 * problem: if the datagram is less than 38 bytes 1377 * in size (14 bytes ether header, 20 bytes IP header, 1378 * plus 4 bytes of data), we punt and compute the IP 1379 * header checksum by hand. This workaround doesn't 1380 * work very well, however, since it can be fooled 1381 * by things like VLAN tags and IP options that make 1382 * the header sizes/offsets vary. 1383 */ 1384 1385 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1386 if (mb_head->m_pkthdr.len < 38) { 1387 struct ip *ip; 1388 mb_head->m_data += ETHER_HDR_LEN; 1389 ip = mtod(mb_head, struct ip *); 1390 ip->ip_sum = in_cksum(mb_head, 1391 ip->ip_hl << 2); 1392 mb_head->m_data -= ETHER_HDR_LEN; 1393 } else { 1394 txp->tx_cb->ipcb_ip_activation_high = 1395 FXP_IPCB_HARDWAREPARSING_ENABLE; 1396 txp->tx_cb->ipcb_ip_schedule |= 1397 FXP_IPCB_IP_CHECKSUM_ENABLE; 1398 } 1399 } 1400#endif 1401 } 1402 1403 /* 1404 * Go through each of the mbufs in the chain and initialize 1405 * the transmit buffer descriptors with the physical address 1406 * and size of the mbuf. 1407 */ 1408 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1409 mb_head, fxp_dma_map_txbuf, sc, 0); 1410 1411 if (error && error != EFBIG) { 1412 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1413 error); 1414 m_freem(mb_head); 1415 break; 1416 } 1417 1418 if (error) { 1419 struct mbuf *mn; 1420 1421 /* 1422 * We ran out of segments. We have to recopy this 1423 * mbuf chain first. Bail out if we can't get the 1424 * new buffers. 1425 */ 1426 mn = m_defrag(mb_head, M_DONTWAIT); 1427 if (mn == NULL) { 1428 m_freem(mb_head); 1429 break; 1430 } else { 1431 mb_head = mn; 1432 } 1433 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1434 mb_head, fxp_dma_map_txbuf, sc, 0); 1435 if (error) { 1436 device_printf(sc->dev, 1437 "can't map mbuf (error %d)\n", error); 1438 m_freem(mb_head); 1439 break; 1440 } 1441 } 1442 1443 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1444 BUS_DMASYNC_PREWRITE); 1445 1446 txp->tx_mbuf = mb_head; 1447 txp->tx_cb->cb_status = 0; 1448 txp->tx_cb->byte_count = 0; 1449 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1450 txp->tx_cb->cb_command = 1451 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1452 FXP_CB_COMMAND_S); 1453 } else { 1454 txp->tx_cb->cb_command = 1455 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1456 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1457 /* 1458 * Set a 5 second timer just in case we don't hear 1459 * from the card again. 1460 */ 1461 ifp->if_timer = 5; 1462 } 1463 txp->tx_cb->tx_threshold = tx_threshold; 1464 1465 /* 1466 * Advance the end of list forward. 1467 */ 1468 1469#ifdef __alpha__ 1470 /* 1471 * On platforms which can't access memory in 16-bit 1472 * granularities, we must prevent the card from DMA'ing 1473 * up the status while we update the command field. 1474 * This could cause us to overwrite the completion status. 1475 * XXX This is probably bogus and we're _not_ looking 1476 * for atomicity here. 1477 */ 1478 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1479 htole16(FXP_CB_COMMAND_S)); 1480#else 1481 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1482 htole16(~FXP_CB_COMMAND_S); 1483#endif /*__alpha__*/ 1484 sc->fxp_desc.tx_last = txp; 1485 1486 /* 1487 * Advance the beginning of the list forward if there are 1488 * no other packets queued (when nothing is queued, tx_first 1489 * sits on the last TxCB that was sent out). 1490 */ 1491 if (sc->tx_queued == 0) 1492 sc->fxp_desc.tx_first = txp; 1493 1494 sc->tx_queued++; 1495 1496 /* 1497 * Pass packet to bpf if there is a listener. 1498 */ 1499 BPF_MTAP(ifp, mb_head); 1500 } 1501 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1502 1503 /* 1504 * We're finished. If we added to the list, issue a RESUME to get DMA 1505 * going again if suspended. 1506 */ 1507 if (txp != NULL) { 1508 fxp_scb_wait(sc); 1509 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1510 } 1511} 1512 1513#ifdef DEVICE_POLLING 1514static poll_handler_t fxp_poll; 1515 1516static void 1517fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1518{ 1519 struct fxp_softc *sc = ifp->if_softc; 1520 u_int8_t statack; 1521 1522 FXP_LOCK(sc); 1523 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1524 ether_poll_deregister(ifp); 1525 cmd = POLL_DEREGISTER; 1526 } 1527 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1528 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1529 FXP_UNLOCK(sc); 1530 return; 1531 } 1532 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1533 FXP_SCB_STATACK_FR; 1534 if (cmd == POLL_AND_CHECK_STATUS) { 1535 u_int8_t tmp; 1536 1537 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1538 if (tmp == 0xff || tmp == 0) { 1539 FXP_UNLOCK(sc); 1540 return; /* nothing to do */ 1541 } 1542 tmp &= ~statack; 1543 /* ack what we can */ 1544 if (tmp != 0) 1545 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1546 statack |= tmp; 1547 } 1548 fxp_intr_body(sc, ifp, statack, count); 1549 FXP_UNLOCK(sc); 1550} 1551#endif /* DEVICE_POLLING */ 1552 1553/* 1554 * Process interface interrupts. 1555 */ 1556static void 1557fxp_intr(void *xsc) 1558{ 1559 struct fxp_softc *sc = xsc; 1560 struct ifnet *ifp = &sc->sc_if; 1561 u_int8_t statack; 1562 1563 FXP_LOCK(sc); 1564 if (sc->suspended) { 1565 FXP_UNLOCK(sc); 1566 return; 1567 } 1568 1569#ifdef DEVICE_POLLING 1570 if (ifp->if_flags & IFF_POLLING) { 1571 FXP_UNLOCK(sc); 1572 return; 1573 } 1574 if ((ifp->if_capenable & IFCAP_POLLING) && 1575 ether_poll_register(fxp_poll, ifp)) { 1576 /* disable interrupts */ 1577 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1578 FXP_UNLOCK(sc); 1579 fxp_poll(ifp, 0, 1); 1580 return; 1581 } 1582#endif 1583 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1584 /* 1585 * It should not be possible to have all bits set; the 1586 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1587 * all bits are set, this may indicate that the card has 1588 * been physically ejected, so ignore it. 1589 */ 1590 if (statack == 0xff) { 1591 FXP_UNLOCK(sc); 1592 return; 1593 } 1594 1595 /* 1596 * First ACK all the interrupts in this pass. 1597 */ 1598 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1599 fxp_intr_body(sc, ifp, statack, -1); 1600 } 1601 FXP_UNLOCK(sc); 1602} 1603 1604static void 1605fxp_txeof(struct fxp_softc *sc) 1606{ 1607 struct fxp_tx *txp; 1608 1609 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1610 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1611 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1612 txp = txp->tx_next) { 1613 if (txp->tx_mbuf != NULL) { 1614 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1615 BUS_DMASYNC_POSTWRITE); 1616 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1617 m_freem(txp->tx_mbuf); 1618 txp->tx_mbuf = NULL; 1619 /* clear this to reset csum offload bits */ 1620 txp->tx_cb->tbd[0].tb_addr = 0; 1621 } 1622 sc->tx_queued--; 1623 } 1624 sc->fxp_desc.tx_first = txp; 1625 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1626} 1627 1628static void 1629fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1630 int count) 1631{ 1632 struct mbuf *m; 1633 struct fxp_rx *rxp; 1634 struct fxp_rfa *rfa; 1635 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1636 1637 FXP_LOCK_ASSERT(sc, MA_OWNED); 1638 if (rnr) 1639 sc->rnr++; 1640#ifdef DEVICE_POLLING 1641 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1642 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1643 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1644 rnr = 1; 1645 } 1646#endif 1647 1648 /* 1649 * Free any finished transmit mbuf chains. 1650 * 1651 * Handle the CNA event likt a CXTNO event. It used to 1652 * be that this event (control unit not ready) was not 1653 * encountered, but it is now with the SMPng modifications. 1654 * The exact sequence of events that occur when the interface 1655 * is brought up are different now, and if this event 1656 * goes unhandled, the configuration/rxfilter setup sequence 1657 * can stall for several seconds. The result is that no 1658 * packets go out onto the wire for about 5 to 10 seconds 1659 * after the interface is ifconfig'ed for the first time. 1660 */ 1661 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1662 fxp_txeof(sc); 1663 1664 ifp->if_timer = 0; 1665 if (sc->tx_queued == 0) { 1666 if (sc->need_mcsetup) 1667 fxp_mc_setup(sc); 1668 } 1669 /* 1670 * Try to start more packets transmitting. 1671 */ 1672 if (ifp->if_snd.ifq_head != NULL) 1673 fxp_start_body(ifp); 1674 } 1675 1676 /* 1677 * Just return if nothing happened on the receive side. 1678 */ 1679 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1680 return; 1681 1682 /* 1683 * Process receiver interrupts. If a no-resource (RNR) 1684 * condition exists, get whatever packets we can and 1685 * re-start the receiver. 1686 * 1687 * When using polling, we do not process the list to completion, 1688 * so when we get an RNR interrupt we must defer the restart 1689 * until we hit the last buffer with the C bit set. 1690 * If we run out of cycles and rfa_headm has the C bit set, 1691 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1692 * that the info will be used in the subsequent polling cycle. 1693 */ 1694 for (;;) { 1695 rxp = sc->fxp_desc.rx_head; 1696 m = rxp->rx_mbuf; 1697 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1698 RFA_ALIGNMENT_FUDGE); 1699 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1700 BUS_DMASYNC_POSTREAD); 1701 1702#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1703 if (count >= 0 && count-- == 0) { 1704 if (rnr) { 1705 /* Defer RNR processing until the next time. */ 1706 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1707 rnr = 0; 1708 } 1709 break; 1710 } 1711#endif /* DEVICE_POLLING */ 1712 1713 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1714 break; 1715 1716 /* 1717 * Advance head forward. 1718 */ 1719 sc->fxp_desc.rx_head = rxp->rx_next; 1720 1721 /* 1722 * Add a new buffer to the receive chain. 1723 * If this fails, the old buffer is recycled 1724 * instead. 1725 */ 1726 if (fxp_add_rfabuf(sc, rxp) == 0) { 1727 int total_len; 1728 1729 /* 1730 * Fetch packet length (the top 2 bits of 1731 * actual_size are flags set by the controller 1732 * upon completion), and drop the packet in case 1733 * of bogus length or CRC errors. 1734 */ 1735 total_len = le16toh(rfa->actual_size) & 0x3fff; 1736 if (total_len < sizeof(struct ether_header) || 1737 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1738 sc->rfa_size || 1739 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1740 m_freem(m); 1741 continue; 1742 } 1743 1744 /* Do IP checksum checking. */ 1745 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1746 if (rfa->rfax_csum_sts & 1747 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1748 m->m_pkthdr.csum_flags |= 1749 CSUM_IP_CHECKED; 1750 if (rfa->rfax_csum_sts & 1751 FXP_RFDX_CS_IP_CSUM_VALID) 1752 m->m_pkthdr.csum_flags |= 1753 CSUM_IP_VALID; 1754 if ((rfa->rfax_csum_sts & 1755 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1756 (rfa->rfax_csum_sts & 1757 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1758 m->m_pkthdr.csum_flags |= 1759 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1760 m->m_pkthdr.csum_data = 0xffff; 1761 } 1762 } 1763 1764 m->m_pkthdr.len = m->m_len = total_len; 1765 m->m_pkthdr.rcvif = ifp; 1766 1767 /* 1768 * Drop locks before calling if_input() since it 1769 * may re-enter fxp_start() in the netisr case. 1770 * This would result in a lock reversal. Better 1771 * performance might be obtained by chaining all 1772 * packets received, dropping the lock, and then 1773 * calling if_input() on each one. 1774 */ 1775 FXP_UNLOCK(sc); 1776 (*ifp->if_input)(ifp, m); 1777 FXP_LOCK(sc); 1778 } 1779 } 1780 if (rnr) { 1781 fxp_scb_wait(sc); 1782 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1783 sc->fxp_desc.rx_head->rx_addr); 1784 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1785 } 1786} 1787 1788/* 1789 * Update packet in/out/collision statistics. The i82557 doesn't 1790 * allow you to access these counters without doing a fairly 1791 * expensive DMA to get _all_ of the statistics it maintains, so 1792 * we do this operation here only once per second. The statistics 1793 * counters in the kernel are updated from the previous dump-stats 1794 * DMA and then a new dump-stats DMA is started. The on-chip 1795 * counters are zeroed when the DMA completes. If we can't start 1796 * the DMA immediately, we don't wait - we just prepare to read 1797 * them again next time. 1798 */ 1799static void 1800fxp_tick(void *xsc) 1801{ 1802 struct fxp_softc *sc = xsc; 1803 struct ifnet *ifp = &sc->sc_if; 1804 struct fxp_stats *sp = sc->fxp_stats; 1805 int s; 1806 1807 FXP_LOCK(sc); 1808 s = splimp(); 1809 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1810 ifp->if_opackets += le32toh(sp->tx_good); 1811 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1812 if (sp->rx_good) { 1813 ifp->if_ipackets += le32toh(sp->rx_good); 1814 sc->rx_idle_secs = 0; 1815 } else { 1816 /* 1817 * Receiver's been idle for another second. 1818 */ 1819 sc->rx_idle_secs++; 1820 } 1821 ifp->if_ierrors += 1822 le32toh(sp->rx_crc_errors) + 1823 le32toh(sp->rx_alignment_errors) + 1824 le32toh(sp->rx_rnr_errors) + 1825 le32toh(sp->rx_overrun_errors); 1826 /* 1827 * If any transmit underruns occured, bump up the transmit 1828 * threshold by another 512 bytes (64 * 8). 1829 */ 1830 if (sp->tx_underruns) { 1831 ifp->if_oerrors += le32toh(sp->tx_underruns); 1832 if (tx_threshold < 192) 1833 tx_threshold += 64; 1834 } 1835 1836 /* 1837 * Release any xmit buffers that have completed DMA. This isn't 1838 * strictly necessary to do here, but it's advantagous for mbufs 1839 * with external storage to be released in a timely manner rather 1840 * than being defered for a potentially long time. This limits 1841 * the delay to a maximum of one second. 1842 */ 1843 fxp_txeof(sc); 1844 1845 /* 1846 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1847 * then assume the receiver has locked up and attempt to clear 1848 * the condition by reprogramming the multicast filter. This is 1849 * a work-around for a bug in the 82557 where the receiver locks 1850 * up if it gets certain types of garbage in the syncronization 1851 * bits prior to the packet header. This bug is supposed to only 1852 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1853 * mode as well (perhaps due to a 10/100 speed transition). 1854 */ 1855 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1856 sc->rx_idle_secs = 0; 1857 fxp_mc_setup(sc); 1858 } 1859 /* 1860 * If there is no pending command, start another stats 1861 * dump. Otherwise punt for now. 1862 */ 1863 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1864 /* 1865 * Start another stats dump. 1866 */ 1867 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1868 BUS_DMASYNC_PREREAD); 1869 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1870 } else { 1871 /* 1872 * A previous command is still waiting to be accepted. 1873 * Just zero our copy of the stats and wait for the 1874 * next timer event to update them. 1875 */ 1876 sp->tx_good = 0; 1877 sp->tx_underruns = 0; 1878 sp->tx_total_collisions = 0; 1879 1880 sp->rx_good = 0; 1881 sp->rx_crc_errors = 0; 1882 sp->rx_alignment_errors = 0; 1883 sp->rx_rnr_errors = 0; 1884 sp->rx_overrun_errors = 0; 1885 } 1886 if (sc->miibus != NULL) 1887 mii_tick(device_get_softc(sc->miibus)); 1888 1889 /* 1890 * Schedule another timeout one second from now. 1891 */ 1892 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1893 FXP_UNLOCK(sc); 1894 splx(s); 1895} 1896 1897/* 1898 * Stop the interface. Cancels the statistics updater and resets 1899 * the interface. 1900 */ 1901static void 1902fxp_stop(struct fxp_softc *sc) 1903{ 1904 struct ifnet *ifp = &sc->sc_if; 1905 struct fxp_tx *txp; 1906 int i; 1907 1908 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1909 ifp->if_timer = 0; 1910 1911#ifdef DEVICE_POLLING 1912 ether_poll_deregister(ifp); 1913#endif 1914 /* 1915 * Cancel stats updater. 1916 */ 1917 callout_stop(&sc->stat_ch); 1918 1919 /* 1920 * Issue software reset, which also unloads the microcode. 1921 */ 1922 sc->flags &= ~FXP_FLAG_UCODE; 1923 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1924 DELAY(50); 1925 1926 /* 1927 * Release any xmit buffers. 1928 */ 1929 txp = sc->fxp_desc.tx_list; 1930 if (txp != NULL) { 1931 for (i = 0; i < FXP_NTXCB; i++) { 1932 if (txp[i].tx_mbuf != NULL) { 1933 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1934 BUS_DMASYNC_POSTWRITE); 1935 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1936 m_freem(txp[i].tx_mbuf); 1937 txp[i].tx_mbuf = NULL; 1938 /* clear this to reset csum offload bits */ 1939 txp[i].tx_cb->tbd[0].tb_addr = 0; 1940 } 1941 } 1942 } 1943 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1944 sc->tx_queued = 0; 1945} 1946 1947/* 1948 * Watchdog/transmission transmit timeout handler. Called when a 1949 * transmission is started on the interface, but no interrupt is 1950 * received before the timeout. This usually indicates that the 1951 * card has wedged for some reason. 1952 */ 1953static void 1954fxp_watchdog(struct ifnet *ifp) 1955{ 1956 struct fxp_softc *sc = ifp->if_softc; 1957 1958 FXP_LOCK(sc); 1959 device_printf(sc->dev, "device timeout\n"); 1960 ifp->if_oerrors++; 1961 1962 fxp_init_body(sc); 1963 FXP_UNLOCK(sc); 1964} 1965 1966/* 1967 * Acquire locks and then call the real initialization function. This 1968 * is necessary because ether_ioctl() calls if_init() and this would 1969 * result in mutex recursion if the mutex was held. 1970 */ 1971static void 1972fxp_init(void *xsc) 1973{ 1974 struct fxp_softc *sc = xsc; 1975 1976 FXP_LOCK(sc); 1977 fxp_init_body(sc); 1978 FXP_UNLOCK(sc); 1979} 1980 1981/* 1982 * Perform device initialization. This routine must be called with the 1983 * softc lock held. 1984 */ 1985static void 1986fxp_init_body(struct fxp_softc *sc) 1987{ 1988 struct ifnet *ifp = &sc->sc_if; 1989 struct fxp_cb_config *cbp; 1990 struct fxp_cb_ias *cb_ias; 1991 struct fxp_cb_tx *tcbp; 1992 struct fxp_tx *txp; 1993 struct fxp_cb_mcs *mcsp; 1994 int i, prm, s; 1995 1996 FXP_LOCK_ASSERT(sc, MA_OWNED); 1997 s = splimp(); 1998 /* 1999 * Cancel any pending I/O 2000 */ 2001 fxp_stop(sc); 2002 2003 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2004 2005 /* 2006 * Initialize base of CBL and RFA memory. Loading with zero 2007 * sets it up for regular linear addressing. 2008 */ 2009 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2010 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2011 2012 fxp_scb_wait(sc); 2013 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2014 2015 /* 2016 * Initialize base of dump-stats buffer. 2017 */ 2018 fxp_scb_wait(sc); 2019 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2020 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2021 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2022 2023 /* 2024 * Attempt to load microcode if requested. 2025 */ 2026 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2027 fxp_load_ucode(sc); 2028 2029 /* 2030 * Initialize the multicast address list. 2031 */ 2032 if (fxp_mc_addrs(sc)) { 2033 mcsp = sc->mcsp; 2034 mcsp->cb_status = 0; 2035 mcsp->cb_command = 2036 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2037 mcsp->link_addr = 0xffffffff; 2038 /* 2039 * Start the multicast setup command. 2040 */ 2041 fxp_scb_wait(sc); 2042 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2043 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2044 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2045 /* ...and wait for it to complete. */ 2046 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2047 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2048 BUS_DMASYNC_POSTWRITE); 2049 } 2050 2051 /* 2052 * We temporarily use memory that contains the TxCB list to 2053 * construct the config CB. The TxCB list memory is rebuilt 2054 * later. 2055 */ 2056 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2057 2058 /* 2059 * This bcopy is kind of disgusting, but there are a bunch of must be 2060 * zero and must be one bits in this structure and this is the easiest 2061 * way to initialize them all to proper values. 2062 */ 2063 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2064 2065 cbp->cb_status = 0; 2066 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2067 FXP_CB_COMMAND_EL); 2068 cbp->link_addr = 0xffffffff; /* (no) next command */ 2069 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2070 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2071 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2072 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2073 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2074 cbp->type_enable = 0; /* actually reserved */ 2075 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2076 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2077 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2078 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2079 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2080 cbp->late_scb = 0; /* (don't) defer SCB update */ 2081 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2082 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2083 cbp->ci_int = 1; /* interrupt on CU idle */ 2084 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2085 cbp->ext_stats_dis = 1; /* disable extended counters */ 2086 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2087 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2088 cbp->disc_short_rx = !prm; /* discard short packets */ 2089 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2090 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2091 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2092 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2093 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2094 cbp->csma_dis = 0; /* (don't) disable link */ 2095 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2096 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2097 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2098 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2099 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2100 cbp->nsai = 1; /* (don't) disable source addr insert */ 2101 cbp->preamble_length = 2; /* (7 byte) preamble */ 2102 cbp->loopback = 0; /* (don't) loopback */ 2103 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2104 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2105 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2106 cbp->promiscuous = prm; /* promiscuous mode */ 2107 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2108 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2109 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2110 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2111 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2112 2113 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2114 cbp->padding = 1; /* (do) pad short tx packets */ 2115 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2116 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2117 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2118 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2119 /* must set wake_en in PMCSR also */ 2120 cbp->force_fdx = 0; /* (don't) force full duplex */ 2121 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2122 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2123 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2124 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2125 2126 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2127 /* 2128 * The 82557 has no hardware flow control, the values 2129 * below are the defaults for the chip. 2130 */ 2131 cbp->fc_delay_lsb = 0; 2132 cbp->fc_delay_msb = 0x40; 2133 cbp->pri_fc_thresh = 3; 2134 cbp->tx_fc_dis = 0; 2135 cbp->rx_fc_restop = 0; 2136 cbp->rx_fc_restart = 0; 2137 cbp->fc_filter = 0; 2138 cbp->pri_fc_loc = 1; 2139 } else { 2140 cbp->fc_delay_lsb = 0x1f; 2141 cbp->fc_delay_msb = 0x01; 2142 cbp->pri_fc_thresh = 3; 2143 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2144 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2145 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2146 cbp->fc_filter = !prm; /* drop FC frames to host */ 2147 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2148 } 2149 2150 /* 2151 * Start the config command/DMA. 2152 */ 2153 fxp_scb_wait(sc); 2154 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2155 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2156 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2157 /* ...and wait for it to complete. */ 2158 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2159 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2160 2161 /* 2162 * Now initialize the station address. Temporarily use the TxCB 2163 * memory area like we did above for the config CB. 2164 */ 2165 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2166 cb_ias->cb_status = 0; 2167 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2168 cb_ias->link_addr = 0xffffffff; 2169 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2170 sizeof(sc->arpcom.ac_enaddr)); 2171 2172 /* 2173 * Start the IAS (Individual Address Setup) command/DMA. 2174 */ 2175 fxp_scb_wait(sc); 2176 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2177 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2178 /* ...and wait for it to complete. */ 2179 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2180 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2181 2182 /* 2183 * Initialize transmit control block (TxCB) list. 2184 */ 2185 txp = sc->fxp_desc.tx_list; 2186 tcbp = sc->fxp_desc.cbl_list; 2187 bzero(tcbp, FXP_TXCB_SZ); 2188 for (i = 0; i < FXP_NTXCB; i++) { 2189 txp[i].tx_cb = tcbp + i; 2190 txp[i].tx_mbuf = NULL; 2191 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2192 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2193 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2194 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2195 if (sc->flags & FXP_FLAG_EXT_TXCB) 2196 tcbp[i].tbd_array_addr = 2197 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2198 else 2199 tcbp[i].tbd_array_addr = 2200 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2201 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2202 } 2203 /* 2204 * Set the suspend flag on the first TxCB and start the control 2205 * unit. It will execute the NOP and then suspend. 2206 */ 2207 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2208 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2209 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2210 sc->tx_queued = 1; 2211 2212 fxp_scb_wait(sc); 2213 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2214 2215 /* 2216 * Initialize receiver buffer area - RFA. 2217 */ 2218 fxp_scb_wait(sc); 2219 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2220 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2221 2222 /* 2223 * Set current media. 2224 */ 2225 if (sc->miibus != NULL) 2226 mii_mediachg(device_get_softc(sc->miibus)); 2227 2228 ifp->if_flags |= IFF_RUNNING; 2229 ifp->if_flags &= ~IFF_OACTIVE; 2230 2231 /* 2232 * Enable interrupts. 2233 */ 2234#ifdef DEVICE_POLLING 2235 /* 2236 * ... but only do that if we are not polling. And because (presumably) 2237 * the default is interrupts on, we need to disable them explicitly! 2238 */ 2239 if ( ifp->if_flags & IFF_POLLING ) 2240 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2241 else 2242#endif /* DEVICE_POLLING */ 2243 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2244 2245 /* 2246 * Start stats updater. 2247 */ 2248 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2249 splx(s); 2250} 2251 2252static int 2253fxp_serial_ifmedia_upd(struct ifnet *ifp) 2254{ 2255 2256 return (0); 2257} 2258 2259static void 2260fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2261{ 2262 2263 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2264} 2265 2266/* 2267 * Change media according to request. 2268 */ 2269static int 2270fxp_ifmedia_upd(struct ifnet *ifp) 2271{ 2272 struct fxp_softc *sc = ifp->if_softc; 2273 struct mii_data *mii; 2274 2275 mii = device_get_softc(sc->miibus); 2276 mii_mediachg(mii); 2277 return (0); 2278} 2279 2280/* 2281 * Notify the world which media we're using. 2282 */ 2283static void 2284fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2285{ 2286 struct fxp_softc *sc = ifp->if_softc; 2287 struct mii_data *mii; 2288 2289 mii = device_get_softc(sc->miibus); 2290 mii_pollstat(mii); 2291 ifmr->ifm_active = mii->mii_media_active; 2292 ifmr->ifm_status = mii->mii_media_status; 2293 2294 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2295 sc->cu_resume_bug = 1; 2296 else 2297 sc->cu_resume_bug = 0; 2298} 2299 2300/* 2301 * Add a buffer to the end of the RFA buffer list. 2302 * Return 0 if successful, 1 for failure. A failure results in 2303 * adding the 'oldm' (if non-NULL) on to the end of the list - 2304 * tossing out its old contents and recycling it. 2305 * The RFA struct is stuck at the beginning of mbuf cluster and the 2306 * data pointer is fixed up to point just past it. 2307 */ 2308static int 2309fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2310{ 2311 struct mbuf *m; 2312 struct fxp_rfa *rfa, *p_rfa; 2313 struct fxp_rx *p_rx; 2314 bus_dmamap_t tmp_map; 2315 int error; 2316 2317 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2318 if (m == NULL) 2319 return (ENOBUFS); 2320 2321 /* 2322 * Move the data pointer up so that the incoming data packet 2323 * will be 32-bit aligned. 2324 */ 2325 m->m_data += RFA_ALIGNMENT_FUDGE; 2326 2327 /* 2328 * Get a pointer to the base of the mbuf cluster and move 2329 * data start past it. 2330 */ 2331 rfa = mtod(m, struct fxp_rfa *); 2332 m->m_data += sc->rfa_size; 2333 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2334 2335 rfa->rfa_status = 0; 2336 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2337 rfa->actual_size = 0; 2338 2339 /* 2340 * Initialize the rest of the RFA. Note that since the RFA 2341 * is misaligned, we cannot store values directly. We're thus 2342 * using the le32enc() function which handles endianness and 2343 * is also alignment-safe. 2344 */ 2345 le32enc(&rfa->link_addr, 0xffffffff); 2346 le32enc(&rfa->rbd_addr, 0xffffffff); 2347 2348 /* Map the RFA into DMA memory. */ 2349 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2350 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2351 &rxp->rx_addr, 0); 2352 if (error) { 2353 m_freem(m); 2354 return (error); 2355 } 2356 2357 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2358 tmp_map = sc->spare_map; 2359 sc->spare_map = rxp->rx_map; 2360 rxp->rx_map = tmp_map; 2361 rxp->rx_mbuf = m; 2362 2363 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2364 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2365 2366 /* 2367 * If there are other buffers already on the list, attach this 2368 * one to the end by fixing up the tail to point to this one. 2369 */ 2370 if (sc->fxp_desc.rx_head != NULL) { 2371 p_rx = sc->fxp_desc.rx_tail; 2372 p_rfa = (struct fxp_rfa *) 2373 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2374 p_rx->rx_next = rxp; 2375 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2376 p_rfa->rfa_control = 0; 2377 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2378 BUS_DMASYNC_PREWRITE); 2379 } else { 2380 rxp->rx_next = NULL; 2381 sc->fxp_desc.rx_head = rxp; 2382 } 2383 sc->fxp_desc.rx_tail = rxp; 2384 return (0); 2385} 2386 2387static volatile int 2388fxp_miibus_readreg(device_t dev, int phy, int reg) 2389{ 2390 struct fxp_softc *sc = device_get_softc(dev); 2391 int count = 10000; 2392 int value; 2393 2394 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2395 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2396 2397 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2398 && count--) 2399 DELAY(10); 2400 2401 if (count <= 0) 2402 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2403 2404 return (value & 0xffff); 2405} 2406 2407static void 2408fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2409{ 2410 struct fxp_softc *sc = device_get_softc(dev); 2411 int count = 10000; 2412 2413 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2414 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2415 (value & 0xffff)); 2416 2417 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2418 count--) 2419 DELAY(10); 2420 2421 if (count <= 0) 2422 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2423} 2424 2425static int 2426fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2427{ 2428 struct fxp_softc *sc = ifp->if_softc; 2429 struct ifreq *ifr = (struct ifreq *)data; 2430 struct mii_data *mii; 2431 int flag, mask, s, error = 0; 2432 2433 /* 2434 * Detaching causes us to call ioctl with the mutex owned. Preclude 2435 * that by saying we're busy if the lock is already held. 2436 */ 2437 if (FXP_LOCKED(sc)) 2438 return (EBUSY); 2439 2440 FXP_LOCK(sc); 2441 s = splimp(); 2442 2443 switch (command) { 2444 case SIOCSIFFLAGS: 2445 if (ifp->if_flags & IFF_ALLMULTI) 2446 sc->flags |= FXP_FLAG_ALL_MCAST; 2447 else 2448 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2449 2450 /* 2451 * If interface is marked up and not running, then start it. 2452 * If it is marked down and running, stop it. 2453 * XXX If it's up then re-initialize it. This is so flags 2454 * such as IFF_PROMISC are handled. 2455 */ 2456 if (ifp->if_flags & IFF_UP) { 2457 fxp_init_body(sc); 2458 } else { 2459 if (ifp->if_flags & IFF_RUNNING) 2460 fxp_stop(sc); 2461 } 2462 break; 2463 2464 case SIOCADDMULTI: 2465 case SIOCDELMULTI: 2466 if (ifp->if_flags & IFF_ALLMULTI) 2467 sc->flags |= FXP_FLAG_ALL_MCAST; 2468 else 2469 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2470 /* 2471 * Multicast list has changed; set the hardware filter 2472 * accordingly. 2473 */ 2474 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2475 fxp_mc_setup(sc); 2476 /* 2477 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2478 * again rather than else {}. 2479 */ 2480 if (sc->flags & FXP_FLAG_ALL_MCAST) 2481 fxp_init_body(sc); 2482 error = 0; 2483 break; 2484 2485 case SIOCSIFMEDIA: 2486 case SIOCGIFMEDIA: 2487 if (sc->miibus != NULL) { 2488 mii = device_get_softc(sc->miibus); 2489 error = ifmedia_ioctl(ifp, ifr, 2490 &mii->mii_media, command); 2491 } else { 2492 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2493 } 2494 break; 2495 2496 case SIOCSIFCAP: 2497 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2498 if (mask & IFCAP_POLLING) 2499 ifp->if_capenable ^= IFCAP_POLLING; 2500 if (mask & IFCAP_VLAN_MTU) { 2501 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2502 if (sc->revision != FXP_REV_82557) 2503 flag = FXP_FLAG_LONG_PKT_EN; 2504 else /* a hack to get long frames on the old chip */ 2505 flag = FXP_FLAG_SAVE_BAD; 2506 sc->flags ^= flag; 2507 if (ifp->if_flags & IFF_UP) 2508 fxp_init_body(sc); 2509 } 2510 break; 2511 2512 default: 2513 /* 2514 * ether_ioctl() will eventually call fxp_start() which 2515 * will result in mutex recursion so drop it first. 2516 */ 2517 FXP_UNLOCK(sc); 2518 error = ether_ioctl(ifp, command, data); 2519 } 2520 if (FXP_LOCKED(sc)) 2521 FXP_UNLOCK(sc); 2522 splx(s); 2523 return (error); 2524} 2525 2526/* 2527 * Fill in the multicast address list and return number of entries. 2528 */ 2529static int 2530fxp_mc_addrs(struct fxp_softc *sc) 2531{ 2532 struct fxp_cb_mcs *mcsp = sc->mcsp; 2533 struct ifnet *ifp = &sc->sc_if; 2534 struct ifmultiaddr *ifma; 2535 int nmcasts; 2536 2537 nmcasts = 0; 2538 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2539#if __FreeBSD_version < 500000 2540 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2541#else 2542 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2543#endif 2544 if (ifma->ifma_addr->sa_family != AF_LINK) 2545 continue; 2546 if (nmcasts >= MAXMCADDR) { 2547 sc->flags |= FXP_FLAG_ALL_MCAST; 2548 nmcasts = 0; 2549 break; 2550 } 2551 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2552 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2553 nmcasts++; 2554 } 2555 } 2556 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2557 return (nmcasts); 2558} 2559 2560/* 2561 * Program the multicast filter. 2562 * 2563 * We have an artificial restriction that the multicast setup command 2564 * must be the first command in the chain, so we take steps to ensure 2565 * this. By requiring this, it allows us to keep up the performance of 2566 * the pre-initialized command ring (esp. link pointers) by not actually 2567 * inserting the mcsetup command in the ring - i.e. its link pointer 2568 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2569 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2570 * lead into the regular TxCB ring when it completes. 2571 * 2572 * This function must be called at splimp. 2573 */ 2574static void 2575fxp_mc_setup(struct fxp_softc *sc) 2576{ 2577 struct fxp_cb_mcs *mcsp = sc->mcsp; 2578 struct ifnet *ifp = &sc->sc_if; 2579 struct fxp_tx *txp; 2580 int count; 2581 2582 FXP_LOCK_ASSERT(sc, MA_OWNED); 2583 /* 2584 * If there are queued commands, we must wait until they are all 2585 * completed. If we are already waiting, then add a NOP command 2586 * with interrupt option so that we're notified when all commands 2587 * have been completed - fxp_start() ensures that no additional 2588 * TX commands will be added when need_mcsetup is true. 2589 */ 2590 if (sc->tx_queued) { 2591 /* 2592 * need_mcsetup will be true if we are already waiting for the 2593 * NOP command to be completed (see below). In this case, bail. 2594 */ 2595 if (sc->need_mcsetup) 2596 return; 2597 sc->need_mcsetup = 1; 2598 2599 /* 2600 * Add a NOP command with interrupt so that we are notified 2601 * when all TX commands have been processed. 2602 */ 2603 txp = sc->fxp_desc.tx_last->tx_next; 2604 txp->tx_mbuf = NULL; 2605 txp->tx_cb->cb_status = 0; 2606 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2607 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2608 /* 2609 * Advance the end of list forward. 2610 */ 2611 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2612 htole16(~FXP_CB_COMMAND_S); 2613 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2614 sc->fxp_desc.tx_last = txp; 2615 sc->tx_queued++; 2616 /* 2617 * Issue a resume in case the CU has just suspended. 2618 */ 2619 fxp_scb_wait(sc); 2620 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2621 /* 2622 * Set a 5 second timer just in case we don't hear from the 2623 * card again. 2624 */ 2625 ifp->if_timer = 5; 2626 2627 return; 2628 } 2629 sc->need_mcsetup = 0; 2630 2631 /* 2632 * Initialize multicast setup descriptor. 2633 */ 2634 mcsp->cb_status = 0; 2635 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2636 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2637 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2638 txp = &sc->fxp_desc.mcs_tx; 2639 txp->tx_mbuf = NULL; 2640 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2641 txp->tx_next = sc->fxp_desc.tx_list; 2642 (void) fxp_mc_addrs(sc); 2643 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2644 sc->tx_queued = 1; 2645 2646 /* 2647 * Wait until command unit is not active. This should never 2648 * be the case when nothing is queued, but make sure anyway. 2649 */ 2650 count = 100; 2651 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2652 FXP_SCB_CUS_ACTIVE && --count) 2653 DELAY(10); 2654 if (count == 0) { 2655 device_printf(sc->dev, "command queue timeout\n"); 2656 return; 2657 } 2658 2659 /* 2660 * Start the multicast setup command. 2661 */ 2662 fxp_scb_wait(sc); 2663 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2664 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2665 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2666 2667 ifp->if_timer = 2; 2668 return; 2669} 2670 2671static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2672static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2673static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2674static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2675static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2676static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2677 2678#define UCODE(x) x, sizeof(x) 2679 2680struct ucode { 2681 u_int32_t revision; 2682 u_int32_t *ucode; 2683 int length; 2684 u_short int_delay_offset; 2685 u_short bundle_max_offset; 2686} ucode_table[] = { 2687 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2688 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2689 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2690 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2691 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2692 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2693 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2694 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2695 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2696 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2697 { 0, NULL, 0, 0, 0 } 2698}; 2699 2700static void 2701fxp_load_ucode(struct fxp_softc *sc) 2702{ 2703 struct ucode *uc; 2704 struct fxp_cb_ucode *cbp; 2705 2706 for (uc = ucode_table; uc->ucode != NULL; uc++) 2707 if (sc->revision == uc->revision) 2708 break; 2709 if (uc->ucode == NULL) 2710 return; 2711 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2712 cbp->cb_status = 0; 2713 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2714 cbp->link_addr = 0xffffffff; /* (no) next command */ 2715 memcpy(cbp->ucode, uc->ucode, uc->length); 2716 if (uc->int_delay_offset) 2717 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2718 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2719 if (uc->bundle_max_offset) 2720 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2721 htole16(sc->tunable_bundle_max); 2722 /* 2723 * Download the ucode to the chip. 2724 */ 2725 fxp_scb_wait(sc); 2726 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2727 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2728 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2729 /* ...and wait for it to complete. */ 2730 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2731 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2732 device_printf(sc->dev, 2733 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2734 sc->tunable_int_delay, 2735 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2736 sc->flags |= FXP_FLAG_UCODE; 2737} 2738 2739static int 2740sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2741{ 2742 int error, value; 2743 2744 value = *(int *)arg1; 2745 error = sysctl_handle_int(oidp, &value, 0, req); 2746 if (error || !req->newptr) 2747 return (error); 2748 if (value < low || value > high) 2749 return (EINVAL); 2750 *(int *)arg1 = value; 2751 return (0); 2752} 2753 2754/* 2755 * Interrupt delay is expressed in microseconds, a multiplier is used 2756 * to convert this to the appropriate clock ticks before using. 2757 */ 2758static int 2759sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2760{ 2761 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2762} 2763 2764static int 2765sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2766{ 2767 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2768} 2769