if_fxp.c revision 129780
172445Sassar/*- 272445Sassar * Copyright (c) 1995, David Greenman 3233294Sstas * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4233294Sstas * All rights reserved. 5233294Sstas * 672445Sassar * Redistribution and use in source and binary forms, with or without 7233294Sstas * modification, are permitted provided that the following conditions 8233294Sstas * are met: 9233294Sstas * 1. Redistributions of source code must retain the above copyright 1072445Sassar * notice unmodified, this list of conditions, and the following 11233294Sstas * disclaimer. 12233294Sstas * 2. Redistributions in binary form must reproduce the above copyright 1372445Sassar * notice, this list of conditions and the following disclaimer in the 14233294Sstas * documentation and/or other materials provided with the distribution. 15233294Sstas * 16233294Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1772445Sassar * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18233294Sstas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19233294Sstas * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20233294Sstas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2172445Sassar * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22233294Sstas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23233294Sstas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24233294Sstas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25233294Sstas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26233294Sstas * SUCH DAMAGE. 27233294Sstas * 28233294Sstas */ 29233294Sstas 30233294Sstas#include <sys/cdefs.h> 31233294Sstas__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 129780 2004-05-27 14:36:58Z yar $"); 32233294Sstas 3372445Sassar/* 3472445Sassar * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 3572445Sassar */ 3672445Sassar 3772445Sassar#include <sys/param.h> 3872445Sassar#include <sys/systm.h> 3972445Sassar#include <sys/endian.h> 4072445Sassar#include <sys/mbuf.h> 4172445Sassar /* #include <sys/mutex.h> */ 4272445Sassar#include <sys/kernel.h> 4372445Sassar#include <sys/socket.h> 4472445Sassar#include <sys/sysctl.h> 4572445Sassar 4672445Sassar#include <net/if.h> 4772445Sassar#include <net/if_dl.h> 4872445Sassar#include <net/if_media.h> 49233294Sstas 50233294Sstas#include <net/bpf.h> 51233294Sstas#include <sys/sockio.h> 5272445Sassar#include <sys/bus.h> 5372445Sassar#include <machine/bus.h> 5472445Sassar#include <sys/rman.h> 5572445Sassar#include <machine/resource.h> 5672445Sassar 5772445Sassar#include <net/ethernet.h> 5872445Sassar#include <net/if_arp.h> 5972445Sassar 6072445Sassar#include <machine/clock.h> /* for DELAY */ 6172445Sassar 6272445Sassar#include <net/if_types.h> 6372445Sassar#include <net/if_vlan_var.h> 6472445Sassar 65233294Sstas#ifdef FXP_IP_CSUM_WAR 6672445Sassar#include <netinet/in.h> 6772445Sassar#include <netinet/in_systm.h> 6872445Sassar#include <netinet/ip.h> 6972445Sassar#include <machine/in_cksum.h> 7072445Sassar#endif 7172445Sassar 7272445Sassar#include <dev/pci/pcivar.h> 7372445Sassar#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 7472445Sassar 7572445Sassar#include <dev/mii/mii.h> 7672445Sassar#include <dev/mii/miivar.h> 7772445Sassar 7872445Sassar#include <dev/fxp/if_fxpreg.h> 7972445Sassar#include <dev/fxp/if_fxpvar.h> 8072445Sassar#include <dev/fxp/rcvbundl.h> 81178825Sdfr 82178825SdfrMODULE_DEPEND(fxp, pci, 1, 1, 1); 8372445SassarMODULE_DEPEND(fxp, ether, 1, 1, 1); 8472445SassarMODULE_DEPEND(fxp, miibus, 1, 1, 1); 8572445Sassar#include "miibus_if.h" 8672445Sassar 87178825Sdfr/* 88178825Sdfr * NOTE! On the Alpha, we have an alignment constraint. The 8972445Sassar * card DMAs the packet immediately following the RFA. However, 9072445Sassar * the first thing in the packet is a 14-byte Ethernet header. 9172445Sassar * This means that the packet is misaligned. To compensate, 9272445Sassar * we actually offset the RFA 2 bytes into the cluster. This 9372445Sassar * alignes the packet after the Ethernet header at a 32-bit 9472445Sassar * boundary. HOWEVER! This means that the RFA is misaligned! 9572445Sassar */ 9672445Sassar#define RFA_ALIGNMENT_FUDGE 2 9772445Sassar 98233294Sstas/* 9972445Sassar * Set initial transmit threshold at 64 (512 bytes). This is 10072445Sassar * increased by 64 (512 bytes) at a time, to maximum of 192 10172445Sassar * (1536 bytes), if an underrun occurs. 10272445Sassar */ 10372445Sassarstatic int tx_threshold = 64; 104178825Sdfr 105178825Sdfr/* 106178825Sdfr * The configuration byte map has several undefined fields which 107178825Sdfr * must be one or must be zero. Set up a template for these bits 10872445Sassar * only, (assuming a 82557 chip) leaving the actual configuration 10972445Sassar * to fxp_init. 11072445Sassar * 11172445Sassar * See struct fxp_cb_config for the bit definitions. 11272445Sassar */ 113178825Sdfrstatic u_char fxp_cb_config_template[] = { 114178825Sdfr 0x0, 0x0, /* cb_status */ 11572445Sassar 0x0, 0x0, /* cb_command */ 11672445Sassar 0x0, 0x0, 0x0, 0x0, /* link_addr */ 11772445Sassar 0x0, /* 0 */ 11872445Sassar 0x0, /* 1 */ 11972445Sassar 0x0, /* 2 */ 120233294Sstas 0x0, /* 3 */ 121178825Sdfr 0x0, /* 4 */ 122178825Sdfr 0x0, /* 5 */ 12372445Sassar 0x32, /* 6 */ 12472445Sassar 0x0, /* 7 */ 12572445Sassar 0x0, /* 8 */ 12672445Sassar 0x0, /* 9 */ 12772445Sassar 0x6, /* 10 */ 128178825Sdfr 0x0, /* 11 */ 129178825Sdfr 0x0, /* 12 */ 13072445Sassar 0x0, /* 13 */ 13172445Sassar 0xf2, /* 14 */ 13272445Sassar 0x48, /* 15 */ 13372445Sassar 0x0, /* 16 */ 13472445Sassar 0x40, /* 17 */ 13572445Sassar 0xf0, /* 18 */ 13672445Sassar 0x0, /* 19 */ 13772445Sassar 0x3f, /* 20 */ 13872445Sassar 0x5 /* 21 */ 13972445Sassar}; 14072445Sassar 14172445Sassarstruct fxp_ident { 14272445Sassar u_int16_t devid; 14372445Sassar int16_t revid; /* -1 matches anything */ 14472445Sassar char *name; 14572445Sassar}; 14672445Sassar 14772445Sassar/* 14872445Sassar * Claim various Intel PCI device identifiers for this driver. The 149178825Sdfr * sub-vendor and sub-device field are extensively used to identify 15072445Sassar * particular variants, but we don't currently differentiate between 15172445Sassar * them. 15272445Sassar */ 15372445Sassarstatic struct fxp_ident fxp_ident_table[] = { 15472445Sassar { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 15572445Sassar { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 15672445Sassar { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 15772445Sassar { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 15872445Sassar { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 15972445Sassar { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 16072445Sassar { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 16172445Sassar { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162178825Sdfr { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 16372445Sassar { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164178825Sdfr { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165178825Sdfr { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166178825Sdfr { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167178825Sdfr { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 16872445Sassar { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 16972445Sassar { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 17072445Sassar { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 17172445Sassar { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 17272445Sassar { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173233294Sstas { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 17472445Sassar { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 190 { 0, -1, NULL }, 191}; 192 193#ifdef FXP_IP_CSUM_WAR 194#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 195#else 196#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 197#endif 198 199static int fxp_probe(device_t dev); 200static int fxp_attach(device_t dev); 201static int fxp_detach(device_t dev); 202static int fxp_shutdown(device_t dev); 203static int fxp_suspend(device_t dev); 204static int fxp_resume(device_t dev); 205 206static void fxp_intr(void *xsc); 207static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 208 u_int8_t statack, int count); 209static void fxp_init(void *xsc); 210static void fxp_init_body(struct fxp_softc *sc); 211static void fxp_tick(void *xsc); 212#ifndef BURN_BRIDGES 213static void fxp_powerstate_d0(device_t dev); 214#endif 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static void fxp_stop(struct fxp_softc *sc); 218static void fxp_release(struct fxp_softc *sc); 219static int fxp_ioctl(struct ifnet *ifp, u_long command, 220 caddr_t data); 221static void fxp_watchdog(struct ifnet *ifp); 222static int fxp_add_rfabuf(struct fxp_softc *sc, 223 struct fxp_rx *rxp); 224static int fxp_mc_addrs(struct fxp_softc *sc); 225static void fxp_mc_setup(struct fxp_softc *sc); 226static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 227 int autosize); 228static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 229 u_int16_t data); 230static void fxp_autosize_eeprom(struct fxp_softc *sc); 231static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235static int fxp_ifmedia_upd(struct ifnet *ifp); 236static void fxp_ifmedia_sts(struct ifnet *ifp, 237 struct ifmediareq *ifmr); 238static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 239static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 240 struct ifmediareq *ifmr); 241static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 242static void fxp_miibus_writereg(device_t dev, int phy, int reg, 243 int value); 244static void fxp_load_ucode(struct fxp_softc *sc); 245static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 246 int low, int high); 247static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 248static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 249static void fxp_scb_wait(struct fxp_softc *sc); 250static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 251static void fxp_dma_wait(struct fxp_softc *sc, 252 volatile u_int16_t *status, bus_dma_tag_t dmat, 253 bus_dmamap_t map); 254 255static device_method_t fxp_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, fxp_probe), 258 DEVMETHOD(device_attach, fxp_attach), 259 DEVMETHOD(device_detach, fxp_detach), 260 DEVMETHOD(device_shutdown, fxp_shutdown), 261 DEVMETHOD(device_suspend, fxp_suspend), 262 DEVMETHOD(device_resume, fxp_resume), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 267 268 { 0, 0 } 269}; 270 271static driver_t fxp_driver = { 272 "fxp", 273 fxp_methods, 274 sizeof(struct fxp_softc), 275}; 276 277static devclass_t fxp_devclass; 278 279DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 280DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 282 283static int fxp_rnr; 284SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 285 286static int fxp_noflow; 287SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 288TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 289 290/* 291 * Wait for the previous command to be accepted (but not necessarily 292 * completed). 293 */ 294static void 295fxp_scb_wait(struct fxp_softc *sc) 296{ 297 int i = 10000; 298 299 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 300 DELAY(2); 301 if (i == 0) 302 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 303 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 304 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 305 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 306 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 307} 308 309static void 310fxp_scb_cmd(struct fxp_softc *sc, int cmd) 311{ 312 313 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 314 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 315 fxp_scb_wait(sc); 316 } 317 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 318} 319 320static void 321fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 322 bus_dma_tag_t dmat, bus_dmamap_t map) 323{ 324 int i = 10000; 325 326 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 327 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 328 DELAY(2); 329 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 330 } 331 if (i == 0) 332 device_printf(sc->dev, "DMA timeout\n"); 333} 334 335/* 336 * Return identification string if this device is ours. 337 */ 338static int 339fxp_probe(device_t dev) 340{ 341 u_int16_t devid; 342 u_int8_t revid; 343 struct fxp_ident *ident; 344 345 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 346 devid = pci_get_device(dev); 347 revid = pci_get_revid(dev); 348 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 349 if (ident->devid == devid && 350 (ident->revid == revid || ident->revid == -1)) { 351 device_set_desc(dev, ident->name); 352 return (0); 353 } 354 } 355 } 356 return (ENXIO); 357} 358 359#ifndef BURN_BRIDGES 360static void 361fxp_powerstate_d0(device_t dev) 362{ 363#if __FreeBSD_version >= 430002 364 u_int32_t iobase, membase, irq; 365 366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 367 /* Save important PCI config data. */ 368 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 369 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 370 irq = pci_read_config(dev, PCIR_INTLINE, 4); 371 372 /* Reset the power state. */ 373 device_printf(dev, "chip is in D%d power mode " 374 "-- setting to D0\n", pci_get_powerstate(dev)); 375 376 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 377 378 /* Restore PCI config data. */ 379 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 380 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 381 pci_write_config(dev, PCIR_INTLINE, irq, 4); 382 } 383#endif 384} 385#endif 386 387static void 388fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 389{ 390 u_int32_t *addr; 391 392 if (error) 393 return; 394 395 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 396 addr = arg; 397 *addr = segs->ds_addr; 398} 399 400static int 401fxp_attach(device_t dev) 402{ 403 int error = 0; 404 struct fxp_softc *sc = device_get_softc(dev); 405 struct ifnet *ifp; 406 struct fxp_rx *rxp; 407 u_int32_t val; 408 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 409 int i, rid, m1, m2, prefer_iomap, maxtxseg; 410 int s, ipcbxmit_disable; 411 412 sc->dev = dev; 413 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 414 sysctl_ctx_init(&sc->sysctl_ctx); 415 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 416 MTX_DEF); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 s = splimp(); 421 422 /* 423 * Enable bus mastering. 424 */ 425 pci_enable_busmaster(dev); 426 val = pci_read_config(dev, PCIR_COMMAND, 2); 427#ifndef BURN_BRIDGES 428 fxp_powerstate_d0(dev); 429#endif 430 /* 431 * Figure out which we should try first - memory mapping or i/o mapping? 432 * We default to memory mapping. Then we accept an override from the 433 * command line. Then we check to see which one is enabled. 434 */ 435 m1 = PCIM_CMD_MEMEN; 436 m2 = PCIM_CMD_PORTEN; 437 prefer_iomap = 0; 438 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 439 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 440 m1 = PCIM_CMD_PORTEN; 441 m2 = PCIM_CMD_MEMEN; 442 } 443 444 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 445 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 446 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 447 if (sc->mem == NULL) { 448 sc->rtp = 449 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 450 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 451 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 452 RF_ACTIVE); 453 } 454 455 if (!sc->mem) { 456 error = ENXIO; 457 goto fail; 458 } 459 if (bootverbose) { 460 device_printf(dev, "using %s space register mapping\n", 461 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 462 } 463 464 sc->sc_st = rman_get_bustag(sc->mem); 465 sc->sc_sh = rman_get_bushandle(sc->mem); 466 467 /* 468 * Allocate our interrupt. 469 */ 470 rid = 0; 471 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->irq == NULL) { 474 device_printf(dev, "could not map interrupt\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 /* 480 * Reset to a stable state. 481 */ 482 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 483 DELAY(10); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Determine whether we must use the 503 serial interface. 492 */ 493 fxp_read_eeprom(sc, &data, 6, 1); 494 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 495 (data & FXP_PHY_SERIAL_ONLY)) 496 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 497 498 /* 499 * Create the sysctl tree 500 */ 501 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 502 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 503 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 504 if (sc->sysctl_tree == NULL) { 505 error = ENXIO; 506 goto fail; 507 } 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573#if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579#endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 599 /* enable reception of long frames for VLAN */ 600 sc->flags |= FXP_FLAG_LONG_PKT_EN; 601 } else { 602 /* a hack to get long VLAN frames on a 82557 */ 603 sc->flags |= FXP_FLAG_SAVE_BAD; 604 } 605 606 /* 607 * Enable use of extended RFDs and TCBs for 82550 608 * and later chips. Note: we need extended TXCB support 609 * too, but that's already enabled by the code above. 610 * Be careful to do this only on the right devices. 611 * 612 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 613 * truncate packets that end with an mbuf containing 1 to 3 bytes 614 * when used with this feature enabled in the previous version of the 615 * driver. This problem appears to be fixed now that the driver 616 * always sets the hardware parse bit in the IPCB structure, which 617 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 618 * Source Software Developer Manual" says is necessary in the 619 * cases where packet truncation was observed. 620 * 621 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 622 * allows this feature to be disabled at boot time. 623 * 624 * If fxp is not compiled into the kernel, this feature may also 625 * be disabled at run time: 626 * # kldunload fxp 627 * # kenv hint.fxp.0.ipcbxmit_disable=1 628 * # kldload fxp 629 */ 630 631 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 632 &ipcbxmit_disable) != 0) 633 ipcbxmit_disable = 0; 634 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 635 sc->revision == FXP_REV_82550_C)) { 636 sc->rfa_size = sizeof (struct fxp_rfa); 637 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 638 sc->flags |= FXP_FLAG_EXT_RFA; 639 } else { 640 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 641 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 642 } 643 644 /* 645 * Allocate DMA tags and DMA safe memory. 646 */ 647 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 648 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 649 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 650 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 651 if (error) { 652 device_printf(dev, "could not allocate dma tag\n"); 653 goto fail; 654 } 655 656 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 657 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 658 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 659 &sc->fxp_stag); 660 if (error) { 661 device_printf(dev, "could not allocate dma tag\n"); 662 goto fail; 663 } 664 665 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 666 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 667 if (error) 668 goto fail; 669 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 670 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 671 if (error) { 672 device_printf(dev, "could not map the stats buffer\n"); 673 goto fail; 674 } 675 676 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 677 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 678 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 679 if (error) { 680 device_printf(dev, "could not allocate dma tag\n"); 681 goto fail; 682 } 683 684 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 685 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 686 if (error) 687 goto fail; 688 689 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 690 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 691 &sc->fxp_desc.cbl_addr, 0); 692 if (error) { 693 device_printf(dev, "could not map DMA memory\n"); 694 goto fail; 695 } 696 697 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 698 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 699 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 700 &sc->mcs_tag); 701 if (error) { 702 device_printf(dev, "could not allocate dma tag\n"); 703 goto fail; 704 } 705 706 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 707 BUS_DMA_NOWAIT, &sc->mcs_map); 708 if (error) 709 goto fail; 710 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 711 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 712 if (error) { 713 device_printf(dev, "can't map the multicast setup command\n"); 714 goto fail; 715 } 716 717 /* 718 * Pre-allocate the TX DMA maps. 719 */ 720 for (i = 0; i < FXP_NTXCB; i++) { 721 error = bus_dmamap_create(sc->fxp_mtag, 0, 722 &sc->fxp_desc.tx_list[i].tx_map); 723 if (error) { 724 device_printf(dev, "can't create DMA map for TX\n"); 725 goto fail; 726 } 727 } 728 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 729 if (error) { 730 device_printf(dev, "can't create spare DMA map\n"); 731 goto fail; 732 } 733 734 /* 735 * Pre-allocate our receive buffers. 736 */ 737 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 738 for (i = 0; i < FXP_NRFABUFS; i++) { 739 rxp = &sc->fxp_desc.rx_list[i]; 740 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 741 if (error) { 742 device_printf(dev, "can't create DMA map for RX\n"); 743 goto fail; 744 } 745 if (fxp_add_rfabuf(sc, rxp) != 0) { 746 error = ENOMEM; 747 goto fail; 748 } 749 } 750 751 /* 752 * Read MAC address. 753 */ 754 fxp_read_eeprom(sc, myea, 0, 3); 755 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 756 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 757 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 758 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 759 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 760 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 761 if (bootverbose) { 762 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 763 pci_get_vendor(dev), pci_get_device(dev), 764 pci_get_subvendor(dev), pci_get_subdevice(dev), 765 pci_get_revid(dev)); 766 fxp_read_eeprom(sc, &data, 10, 1); 767 device_printf(dev, "Dynamic Standby mode is %s\n", 768 data & 0x02 ? "enabled" : "disabled"); 769 } 770 771 /* 772 * If this is only a 10Mbps device, then there is no MII, and 773 * the PHY will use a serial interface instead. 774 * 775 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 776 * doesn't have a programming interface of any sort. The 777 * media is sensed automatically based on how the link partner 778 * is configured. This is, in essence, manual configuration. 779 */ 780 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 781 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 782 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 783 } else { 784 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 785 fxp_ifmedia_sts)) { 786 device_printf(dev, "MII without any PHY!\n"); 787 error = ENXIO; 788 goto fail; 789 } 790 } 791 792 ifp = &sc->arpcom.ac_if; 793 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 794 ifp->if_baudrate = 100000000; 795 ifp->if_init = fxp_init; 796 ifp->if_softc = sc; 797 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 798 ifp->if_ioctl = fxp_ioctl; 799 ifp->if_start = fxp_start; 800 ifp->if_watchdog = fxp_watchdog; 801 802 ifp->if_capabilities = ifp->if_capenable = 0; 803 804 /* Enable checksum offload for 82550 or better chips */ 805 if (sc->flags & FXP_FLAG_EXT_RFA) { 806 ifp->if_hwassist = FXP_CSUM_FEATURES; 807 ifp->if_capabilities |= IFCAP_HWCSUM; 808 ifp->if_capenable |= IFCAP_HWCSUM; 809 } 810 811#ifdef DEVICE_POLLING 812 /* Inform the world we support polling. */ 813 ifp->if_capabilities |= IFCAP_POLLING; 814 ifp->if_capenable |= IFCAP_POLLING; 815#endif 816 817 /* 818 * Attach the interface. 819 */ 820 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 821 822 /* 823 * Tell the upper layer(s) we support long frames. 824 * Must appear after the call to ether_ifattach() because 825 * ether_ifattach() sets ifi_hdrlen to the default value. 826 */ 827 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 828 ifp->if_capabilities |= IFCAP_VLAN_MTU; 829 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 830 831 /* 832 * Let the system queue as many packets as we have available 833 * TX descriptors. 834 */ 835 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 836 837 /* 838 * Hook our interrupt after all initialization is complete. 839 * XXX This driver has been tested with the INTR_MPSAFFE flag set 840 * however, ifp and its functions are not fully locked so MPSAFE 841 * should not be used unless you can handle potential data loss. 842 */ 843 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 844 fxp_intr, sc, &sc->ih); 845 if (error) { 846 device_printf(dev, "could not setup irq\n"); 847 ether_ifdetach(&sc->arpcom.ac_if); 848 goto fail; 849 } 850 851fail: 852 splx(s); 853 if (error) 854 fxp_release(sc); 855 return (error); 856} 857 858/* 859 * Release all resources. The softc lock should not be held and the 860 * interrupt should already be torn down. 861 */ 862static void 863fxp_release(struct fxp_softc *sc) 864{ 865 struct fxp_rx *rxp; 866 struct fxp_tx *txp; 867 int i; 868 869 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 870 KASSERT(sc->ih == NULL, 871 ("fxp_release() called with intr handle still active")); 872 if (sc->miibus) 873 device_delete_child(sc->dev, sc->miibus); 874 bus_generic_detach(sc->dev); 875 ifmedia_removeall(&sc->sc_media); 876 if (sc->fxp_desc.cbl_list) { 877 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 878 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 879 sc->cbl_map); 880 } 881 if (sc->fxp_stats) { 882 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 883 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 884 } 885 if (sc->mcsp) { 886 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 887 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 888 } 889 if (sc->irq) 890 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 891 if (sc->mem) 892 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 893 if (sc->fxp_mtag) { 894 for (i = 0; i < FXP_NRFABUFS; i++) { 895 rxp = &sc->fxp_desc.rx_list[i]; 896 if (rxp->rx_mbuf != NULL) { 897 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 898 BUS_DMASYNC_POSTREAD); 899 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 900 m_freem(rxp->rx_mbuf); 901 } 902 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 903 } 904 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 905 bus_dma_tag_destroy(sc->fxp_mtag); 906 } 907 if (sc->fxp_stag) { 908 for (i = 0; i < FXP_NTXCB; i++) { 909 txp = &sc->fxp_desc.tx_list[i]; 910 if (txp->tx_mbuf != NULL) { 911 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 912 BUS_DMASYNC_POSTWRITE); 913 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 914 m_freem(txp->tx_mbuf); 915 } 916 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 917 } 918 bus_dma_tag_destroy(sc->fxp_stag); 919 } 920 if (sc->cbl_tag) 921 bus_dma_tag_destroy(sc->cbl_tag); 922 if (sc->mcs_tag) 923 bus_dma_tag_destroy(sc->mcs_tag); 924 925 sysctl_ctx_free(&sc->sysctl_ctx); 926 927 mtx_destroy(&sc->sc_mtx); 928} 929 930/* 931 * Detach interface. 932 */ 933static int 934fxp_detach(device_t dev) 935{ 936 struct fxp_softc *sc = device_get_softc(dev); 937 int s; 938 939 FXP_LOCK(sc); 940 s = splimp(); 941 942 sc->suspended = 1; /* Do same thing as we do for suspend */ 943 /* 944 * Close down routes etc. 945 */ 946 ether_ifdetach(&sc->arpcom.ac_if); 947 948 /* 949 * Stop DMA and drop transmit queue, but disable interrupts first. 950 */ 951 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 952 fxp_stop(sc); 953 FXP_UNLOCK(sc); 954 955 /* 956 * Unhook interrupt before dropping lock. This is to prevent 957 * races with fxp_intr(). 958 */ 959 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 960 sc->ih = NULL; 961 962 splx(s); 963 964 /* Release our allocated resources. */ 965 fxp_release(sc); 966 return (0); 967} 968 969/* 970 * Device shutdown routine. Called at system shutdown after sync. The 971 * main purpose of this routine is to shut off receiver DMA so that 972 * kernel memory doesn't get clobbered during warmboot. 973 */ 974static int 975fxp_shutdown(device_t dev) 976{ 977 /* 978 * Make sure that DMA is disabled prior to reboot. Not doing 979 * do could allow DMA to corrupt kernel memory during the 980 * reboot before the driver initializes. 981 */ 982 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 983 return (0); 984} 985 986/* 987 * Device suspend routine. Stop the interface and save some PCI 988 * settings in case the BIOS doesn't restore them properly on 989 * resume. 990 */ 991static int 992fxp_suspend(device_t dev) 993{ 994 struct fxp_softc *sc = device_get_softc(dev); 995 int i, s; 996 997 FXP_LOCK(sc); 998 s = splimp(); 999 1000 fxp_stop(sc); 1001 1002 for (i = 0; i < 5; i++) 1003 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1004 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1005 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1006 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1007 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1008 1009 sc->suspended = 1; 1010 1011 FXP_UNLOCK(sc); 1012 splx(s); 1013 return (0); 1014} 1015 1016/* 1017 * Device resume routine. Restore some PCI settings in case the BIOS 1018 * doesn't, re-enable busmastering, and restart the interface if 1019 * appropriate. 1020 */ 1021static int 1022fxp_resume(device_t dev) 1023{ 1024 struct fxp_softc *sc = device_get_softc(dev); 1025 struct ifnet *ifp = &sc->sc_if; 1026 u_int16_t pci_command; 1027 int i, s; 1028 1029 FXP_LOCK(sc); 1030 s = splimp(); 1031#ifndef BURN_BRIDGES 1032 fxp_powerstate_d0(dev); 1033#endif 1034 /* better way to do this? */ 1035 for (i = 0; i < 5; i++) 1036 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1037 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1038 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1039 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1040 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1041 1042 /* reenable busmastering */ 1043 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1044 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1045 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1046 1047 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1048 DELAY(10); 1049 1050 /* reinitialize interface if necessary */ 1051 if (ifp->if_flags & IFF_UP) 1052 fxp_init_body(sc); 1053 1054 sc->suspended = 0; 1055 1056 FXP_UNLOCK(sc); 1057 splx(s); 1058 return (0); 1059} 1060 1061static void 1062fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1063{ 1064 u_int16_t reg; 1065 int x; 1066 1067 /* 1068 * Shift in data. 1069 */ 1070 for (x = 1 << (length - 1); x; x >>= 1) { 1071 if (data & x) 1072 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1073 else 1074 reg = FXP_EEPROM_EECS; 1075 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1076 DELAY(1); 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1078 DELAY(1); 1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1080 DELAY(1); 1081 } 1082} 1083 1084/* 1085 * Read from the serial EEPROM. Basically, you manually shift in 1086 * the read opcode (one bit at a time) and then shift in the address, 1087 * and then you shift out the data (all of this one bit at a time). 1088 * The word size is 16 bits, so you have to provide the address for 1089 * every 16 bits of data. 1090 */ 1091static u_int16_t 1092fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1093{ 1094 u_int16_t reg, data; 1095 int x; 1096 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1098 /* 1099 * Shift in read opcode. 1100 */ 1101 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1102 /* 1103 * Shift in address. 1104 */ 1105 data = 0; 1106 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1107 if (offset & x) 1108 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1109 else 1110 reg = FXP_EEPROM_EECS; 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1112 DELAY(1); 1113 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1114 DELAY(1); 1115 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1116 DELAY(1); 1117 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1118 data++; 1119 if (autosize && reg == 0) { 1120 sc->eeprom_size = data; 1121 break; 1122 } 1123 } 1124 /* 1125 * Shift out data. 1126 */ 1127 data = 0; 1128 reg = FXP_EEPROM_EECS; 1129 for (x = 1 << 15; x; x >>= 1) { 1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1131 DELAY(1); 1132 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1133 data |= x; 1134 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1135 DELAY(1); 1136 } 1137 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1138 DELAY(1); 1139 1140 return (data); 1141} 1142 1143static void 1144fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1145{ 1146 int i; 1147 1148 /* 1149 * Erase/write enable. 1150 */ 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1152 fxp_eeprom_shiftin(sc, 0x4, 3); 1153 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1154 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1155 DELAY(1); 1156 /* 1157 * Shift in write opcode, address, data. 1158 */ 1159 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1160 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1161 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1162 fxp_eeprom_shiftin(sc, data, 16); 1163 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1164 DELAY(1); 1165 /* 1166 * Wait for EEPROM to finish up. 1167 */ 1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1169 DELAY(1); 1170 for (i = 0; i < 1000; i++) { 1171 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1172 break; 1173 DELAY(50); 1174 } 1175 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1176 DELAY(1); 1177 /* 1178 * Erase/write disable. 1179 */ 1180 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1181 fxp_eeprom_shiftin(sc, 0x4, 3); 1182 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1183 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1184 DELAY(1); 1185} 1186 1187/* 1188 * From NetBSD: 1189 * 1190 * Figure out EEPROM size. 1191 * 1192 * 559's can have either 64-word or 256-word EEPROMs, the 558 1193 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1194 * talks about the existance of 16 to 256 word EEPROMs. 1195 * 1196 * The only known sizes are 64 and 256, where the 256 version is used 1197 * by CardBus cards to store CIS information. 1198 * 1199 * The address is shifted in msb-to-lsb, and after the last 1200 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1201 * after which follows the actual data. We try to detect this zero, by 1202 * probing the data-out bit in the EEPROM control register just after 1203 * having shifted in a bit. If the bit is zero, we assume we've 1204 * shifted enough address bits. The data-out should be tri-state, 1205 * before this, which should translate to a logical one. 1206 */ 1207static void 1208fxp_autosize_eeprom(struct fxp_softc *sc) 1209{ 1210 1211 /* guess maximum size of 256 words */ 1212 sc->eeprom_size = 8; 1213 1214 /* autosize */ 1215 (void) fxp_eeprom_getword(sc, 0, 1); 1216} 1217 1218static void 1219fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1220{ 1221 int i; 1222 1223 for (i = 0; i < words; i++) 1224 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1225} 1226 1227static void 1228fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1229{ 1230 int i; 1231 1232 for (i = 0; i < words; i++) 1233 fxp_eeprom_putword(sc, offset + i, data[i]); 1234} 1235 1236static void 1237fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1238 bus_size_t mapsize, int error) 1239{ 1240 struct fxp_softc *sc; 1241 struct fxp_cb_tx *txp; 1242 int i; 1243 1244 if (error) 1245 return; 1246 1247 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1248 1249 sc = arg; 1250 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1251 for (i = 0; i < nseg; i++) { 1252 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1253 /* 1254 * If this is an 82550/82551, then we're using extended 1255 * TxCBs _and_ we're using checksum offload. This means 1256 * that the TxCB is really an IPCB. One major difference 1257 * between the two is that with plain extended TxCBs, 1258 * the bottom half of the TxCB contains two entries from 1259 * the TBD array, whereas IPCBs contain just one entry: 1260 * one entry (8 bytes) has been sacrificed for the TCP/IP 1261 * checksum offload control bits. So to make things work 1262 * right, we have to start filling in the TBD array 1263 * starting from a different place depending on whether 1264 * the chip is an 82550/82551 or not. 1265 */ 1266 if (sc->flags & FXP_FLAG_EXT_RFA) { 1267 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1268 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1269 } else { 1270 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1271 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1272 } 1273 } 1274 txp->tbd_number = nseg; 1275} 1276 1277/* 1278 * Grab the softc lock and call the real fxp_start_body() routine 1279 */ 1280static void 1281fxp_start(struct ifnet *ifp) 1282{ 1283 struct fxp_softc *sc = ifp->if_softc; 1284 1285 FXP_LOCK(sc); 1286 fxp_start_body(ifp); 1287 FXP_UNLOCK(sc); 1288} 1289 1290/* 1291 * Start packet transmission on the interface. 1292 * This routine must be called with the softc lock held, and is an 1293 * internal entry point only. 1294 */ 1295static void 1296fxp_start_body(struct ifnet *ifp) 1297{ 1298 struct fxp_softc *sc = ifp->if_softc; 1299 struct fxp_tx *txp; 1300 struct mbuf *mb_head; 1301 int error; 1302 1303 mtx_assert(&sc->sc_mtx, MA_OWNED); 1304 /* 1305 * See if we need to suspend xmit until the multicast filter 1306 * has been reprogrammed (which can only be done at the head 1307 * of the command chain). 1308 */ 1309 if (sc->need_mcsetup) { 1310 return; 1311 } 1312 1313 txp = NULL; 1314 1315 /* 1316 * We're finished if there is nothing more to add to the list or if 1317 * we're all filled up with buffers to transmit. 1318 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1319 * a NOP command when needed. 1320 */ 1321 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1322 1323 /* 1324 * Grab a packet to transmit. 1325 */ 1326 IF_DEQUEUE(&ifp->if_snd, mb_head); 1327 1328 /* 1329 * Get pointer to next available tx desc. 1330 */ 1331 txp = sc->fxp_desc.tx_last->tx_next; 1332 1333 /* 1334 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1335 * Ethernet Controller Family Open Source Software 1336 * Developer Manual says: 1337 * Using software parsing is only allowed with legal 1338 * TCP/IP or UDP/IP packets. 1339 * ... 1340 * For all other datagrams, hardware parsing must 1341 * be used. 1342 * Software parsing appears to truncate ICMP and 1343 * fragmented UDP packets that contain one to three 1344 * bytes in the second (and final) mbuf of the packet. 1345 */ 1346 if (sc->flags & FXP_FLAG_EXT_RFA) 1347 txp->tx_cb->ipcb_ip_activation_high = 1348 FXP_IPCB_HARDWAREPARSING_ENABLE; 1349 1350 /* 1351 * Deal with TCP/IP checksum offload. Note that 1352 * in order for TCP checksum offload to work, 1353 * the pseudo header checksum must have already 1354 * been computed and stored in the checksum field 1355 * in the TCP header. The stack should have 1356 * already done this for us. 1357 */ 1358 1359 if (mb_head->m_pkthdr.csum_flags) { 1360 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1361 txp->tx_cb->ipcb_ip_schedule = 1362 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1363 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1364 txp->tx_cb->ipcb_ip_schedule |= 1365 FXP_IPCB_TCP_PACKET; 1366 } 1367#ifdef FXP_IP_CSUM_WAR 1368 /* 1369 * XXX The 82550 chip appears to have trouble 1370 * dealing with IP header checksums in very small 1371 * datagrams, namely fragments from 1 to 3 bytes 1372 * in size. For example, say you want to transmit 1373 * a UDP packet of 1473 bytes. The packet will be 1374 * fragmented over two IP datagrams, the latter 1375 * containing only one byte of data. The 82550 will 1376 * botch the header checksum on the 1-byte fragment. 1377 * As long as the datagram contains 4 or more bytes 1378 * of data, you're ok. 1379 * 1380 * The following code attempts to work around this 1381 * problem: if the datagram is less than 38 bytes 1382 * in size (14 bytes ether header, 20 bytes IP header, 1383 * plus 4 bytes of data), we punt and compute the IP 1384 * header checksum by hand. This workaround doesn't 1385 * work very well, however, since it can be fooled 1386 * by things like VLAN tags and IP options that make 1387 * the header sizes/offsets vary. 1388 */ 1389 1390 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1391 if (mb_head->m_pkthdr.len < 38) { 1392 struct ip *ip; 1393 mb_head->m_data += ETHER_HDR_LEN; 1394 ip = mtod(mb_head, struct ip *); 1395 ip->ip_sum = in_cksum(mb_head, 1396 ip->ip_hl << 2); 1397 mb_head->m_data -= ETHER_HDR_LEN; 1398 } else { 1399 txp->tx_cb->ipcb_ip_activation_high = 1400 FXP_IPCB_HARDWAREPARSING_ENABLE; 1401 txp->tx_cb->ipcb_ip_schedule |= 1402 FXP_IPCB_IP_CHECKSUM_ENABLE; 1403 } 1404 } 1405#endif 1406 } 1407 1408 /* 1409 * Go through each of the mbufs in the chain and initialize 1410 * the transmit buffer descriptors with the physical address 1411 * and size of the mbuf. 1412 */ 1413 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1414 mb_head, fxp_dma_map_txbuf, sc, 0); 1415 1416 if (error && error != EFBIG) { 1417 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1418 error); 1419 m_freem(mb_head); 1420 break; 1421 } 1422 1423 if (error) { 1424 struct mbuf *mn; 1425 1426 /* 1427 * We ran out of segments. We have to recopy this 1428 * mbuf chain first. Bail out if we can't get the 1429 * new buffers. 1430 */ 1431 mn = m_defrag(mb_head, M_DONTWAIT); 1432 if (mn == NULL) { 1433 m_freem(mb_head); 1434 break; 1435 } else { 1436 mb_head = mn; 1437 } 1438 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1439 mb_head, fxp_dma_map_txbuf, sc, 0); 1440 if (error) { 1441 device_printf(sc->dev, 1442 "can't map mbuf (error %d)\n", error); 1443 m_freem(mb_head); 1444 break; 1445 } 1446 } 1447 1448 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1449 BUS_DMASYNC_PREWRITE); 1450 1451 txp->tx_mbuf = mb_head; 1452 txp->tx_cb->cb_status = 0; 1453 txp->tx_cb->byte_count = 0; 1454 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1455 txp->tx_cb->cb_command = 1456 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1457 FXP_CB_COMMAND_S); 1458 } else { 1459 txp->tx_cb->cb_command = 1460 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1461 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1462 /* 1463 * Set a 5 second timer just in case we don't hear 1464 * from the card again. 1465 */ 1466 ifp->if_timer = 5; 1467 } 1468 txp->tx_cb->tx_threshold = tx_threshold; 1469 1470 /* 1471 * Advance the end of list forward. 1472 */ 1473 1474#ifdef __alpha__ 1475 /* 1476 * On platforms which can't access memory in 16-bit 1477 * granularities, we must prevent the card from DMA'ing 1478 * up the status while we update the command field. 1479 * This could cause us to overwrite the completion status. 1480 * XXX This is probably bogus and we're _not_ looking 1481 * for atomicity here. 1482 */ 1483 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1484 htole16(FXP_CB_COMMAND_S)); 1485#else 1486 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1487 htole16(~FXP_CB_COMMAND_S); 1488#endif /*__alpha__*/ 1489 sc->fxp_desc.tx_last = txp; 1490 1491 /* 1492 * Advance the beginning of the list forward if there are 1493 * no other packets queued (when nothing is queued, tx_first 1494 * sits on the last TxCB that was sent out). 1495 */ 1496 if (sc->tx_queued == 0) 1497 sc->fxp_desc.tx_first = txp; 1498 1499 sc->tx_queued++; 1500 1501 /* 1502 * Pass packet to bpf if there is a listener. 1503 */ 1504 BPF_MTAP(ifp, mb_head); 1505 } 1506 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1507 1508 /* 1509 * We're finished. If we added to the list, issue a RESUME to get DMA 1510 * going again if suspended. 1511 */ 1512 if (txp != NULL) { 1513 fxp_scb_wait(sc); 1514 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1515 } 1516} 1517 1518#ifdef DEVICE_POLLING 1519static poll_handler_t fxp_poll; 1520 1521static void 1522fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1523{ 1524 struct fxp_softc *sc = ifp->if_softc; 1525 u_int8_t statack; 1526 1527 FXP_LOCK(sc); 1528 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1529 ether_poll_deregister(ifp); 1530 cmd = POLL_DEREGISTER; 1531 } 1532 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1533 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1534 FXP_UNLOCK(sc); 1535 return; 1536 } 1537 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1538 FXP_SCB_STATACK_FR; 1539 if (cmd == POLL_AND_CHECK_STATUS) { 1540 u_int8_t tmp; 1541 1542 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1543 if (tmp == 0xff || tmp == 0) { 1544 FXP_UNLOCK(sc); 1545 return; /* nothing to do */ 1546 } 1547 tmp &= ~statack; 1548 /* ack what we can */ 1549 if (tmp != 0) 1550 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1551 statack |= tmp; 1552 } 1553 fxp_intr_body(sc, ifp, statack, count); 1554 FXP_UNLOCK(sc); 1555} 1556#endif /* DEVICE_POLLING */ 1557 1558/* 1559 * Process interface interrupts. 1560 */ 1561static void 1562fxp_intr(void *xsc) 1563{ 1564 struct fxp_softc *sc = xsc; 1565 struct ifnet *ifp = &sc->sc_if; 1566 u_int8_t statack; 1567 1568 FXP_LOCK(sc); 1569 if (sc->suspended) { 1570 FXP_UNLOCK(sc); 1571 return; 1572 } 1573 1574#ifdef DEVICE_POLLING 1575 if (ifp->if_flags & IFF_POLLING) { 1576 FXP_UNLOCK(sc); 1577 return; 1578 } 1579 if ((ifp->if_capenable & IFCAP_POLLING) && 1580 ether_poll_register(fxp_poll, ifp)) { 1581 /* disable interrupts */ 1582 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1583 FXP_UNLOCK(sc); 1584 fxp_poll(ifp, 0, 1); 1585 return; 1586 } 1587#endif 1588 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1589 /* 1590 * It should not be possible to have all bits set; the 1591 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1592 * all bits are set, this may indicate that the card has 1593 * been physically ejected, so ignore it. 1594 */ 1595 if (statack == 0xff) { 1596 FXP_UNLOCK(sc); 1597 return; 1598 } 1599 1600 /* 1601 * First ACK all the interrupts in this pass. 1602 */ 1603 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1604 fxp_intr_body(sc, ifp, statack, -1); 1605 } 1606 FXP_UNLOCK(sc); 1607} 1608 1609static void 1610fxp_txeof(struct fxp_softc *sc) 1611{ 1612 struct fxp_tx *txp; 1613 1614 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1615 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1616 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1617 txp = txp->tx_next) { 1618 if (txp->tx_mbuf != NULL) { 1619 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1620 BUS_DMASYNC_POSTWRITE); 1621 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1622 m_freem(txp->tx_mbuf); 1623 txp->tx_mbuf = NULL; 1624 /* clear this to reset csum offload bits */ 1625 txp->tx_cb->tbd[0].tb_addr = 0; 1626 } 1627 sc->tx_queued--; 1628 } 1629 sc->fxp_desc.tx_first = txp; 1630 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1631} 1632 1633static void 1634fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1635 int count) 1636{ 1637 struct mbuf *m; 1638 struct fxp_rx *rxp; 1639 struct fxp_rfa *rfa; 1640 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1641 1642 mtx_assert(&sc->sc_mtx, MA_OWNED); 1643 if (rnr) 1644 fxp_rnr++; 1645#ifdef DEVICE_POLLING 1646 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1647 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1648 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1649 rnr = 1; 1650 } 1651#endif 1652 1653 /* 1654 * Free any finished transmit mbuf chains. 1655 * 1656 * Handle the CNA event likt a CXTNO event. It used to 1657 * be that this event (control unit not ready) was not 1658 * encountered, but it is now with the SMPng modifications. 1659 * The exact sequence of events that occur when the interface 1660 * is brought up are different now, and if this event 1661 * goes unhandled, the configuration/rxfilter setup sequence 1662 * can stall for several seconds. The result is that no 1663 * packets go out onto the wire for about 5 to 10 seconds 1664 * after the interface is ifconfig'ed for the first time. 1665 */ 1666 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1667 fxp_txeof(sc); 1668 1669 ifp->if_timer = 0; 1670 if (sc->tx_queued == 0) { 1671 if (sc->need_mcsetup) 1672 fxp_mc_setup(sc); 1673 } 1674 /* 1675 * Try to start more packets transmitting. 1676 */ 1677 if (ifp->if_snd.ifq_head != NULL) 1678 fxp_start_body(ifp); 1679 } 1680 1681 /* 1682 * Just return if nothing happened on the receive side. 1683 */ 1684 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1685 return; 1686 1687 /* 1688 * Process receiver interrupts. If a no-resource (RNR) 1689 * condition exists, get whatever packets we can and 1690 * re-start the receiver. 1691 * 1692 * When using polling, we do not process the list to completion, 1693 * so when we get an RNR interrupt we must defer the restart 1694 * until we hit the last buffer with the C bit set. 1695 * If we run out of cycles and rfa_headm has the C bit set, 1696 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1697 * that the info will be used in the subsequent polling cycle. 1698 */ 1699 for (;;) { 1700 rxp = sc->fxp_desc.rx_head; 1701 m = rxp->rx_mbuf; 1702 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1703 RFA_ALIGNMENT_FUDGE); 1704 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1705 BUS_DMASYNC_POSTREAD); 1706 1707#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1708 if (count >= 0 && count-- == 0) { 1709 if (rnr) { 1710 /* Defer RNR processing until the next time. */ 1711 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1712 rnr = 0; 1713 } 1714 break; 1715 } 1716#endif /* DEVICE_POLLING */ 1717 1718 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1719 break; 1720 1721 /* 1722 * Advance head forward. 1723 */ 1724 sc->fxp_desc.rx_head = rxp->rx_next; 1725 1726 /* 1727 * Add a new buffer to the receive chain. 1728 * If this fails, the old buffer is recycled 1729 * instead. 1730 */ 1731 if (fxp_add_rfabuf(sc, rxp) == 0) { 1732 int total_len; 1733 1734 /* 1735 * Fetch packet length (the top 2 bits of 1736 * actual_size are flags set by the controller 1737 * upon completion), and drop the packet in case 1738 * of bogus length or CRC errors. 1739 */ 1740 total_len = le16toh(rfa->actual_size) & 0x3fff; 1741 if (total_len < sizeof(struct ether_header) || 1742 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1743 sc->rfa_size || 1744 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1745 m_freem(m); 1746 continue; 1747 } 1748 1749 /* Do IP checksum checking. */ 1750 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1751 if (rfa->rfax_csum_sts & 1752 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1753 m->m_pkthdr.csum_flags |= 1754 CSUM_IP_CHECKED; 1755 if (rfa->rfax_csum_sts & 1756 FXP_RFDX_CS_IP_CSUM_VALID) 1757 m->m_pkthdr.csum_flags |= 1758 CSUM_IP_VALID; 1759 if ((rfa->rfax_csum_sts & 1760 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1761 (rfa->rfax_csum_sts & 1762 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1763 m->m_pkthdr.csum_flags |= 1764 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1765 m->m_pkthdr.csum_data = 0xffff; 1766 } 1767 } 1768 1769 m->m_pkthdr.len = m->m_len = total_len; 1770 m->m_pkthdr.rcvif = ifp; 1771 1772 /* 1773 * Drop locks before calling if_input() since it 1774 * may re-enter fxp_start() in the netisr case. 1775 * This would result in a lock reversal. Better 1776 * performance might be obtained by chaining all 1777 * packets received, dropping the lock, and then 1778 * calling if_input() on each one. 1779 */ 1780 FXP_UNLOCK(sc); 1781 (*ifp->if_input)(ifp, m); 1782 FXP_LOCK(sc); 1783 } 1784 } 1785 if (rnr) { 1786 fxp_scb_wait(sc); 1787 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1788 sc->fxp_desc.rx_head->rx_addr); 1789 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1790 } 1791} 1792 1793/* 1794 * Update packet in/out/collision statistics. The i82557 doesn't 1795 * allow you to access these counters without doing a fairly 1796 * expensive DMA to get _all_ of the statistics it maintains, so 1797 * we do this operation here only once per second. The statistics 1798 * counters in the kernel are updated from the previous dump-stats 1799 * DMA and then a new dump-stats DMA is started. The on-chip 1800 * counters are zeroed when the DMA completes. If we can't start 1801 * the DMA immediately, we don't wait - we just prepare to read 1802 * them again next time. 1803 */ 1804static void 1805fxp_tick(void *xsc) 1806{ 1807 struct fxp_softc *sc = xsc; 1808 struct ifnet *ifp = &sc->sc_if; 1809 struct fxp_stats *sp = sc->fxp_stats; 1810 int s; 1811 1812 FXP_LOCK(sc); 1813 s = splimp(); 1814 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1815 ifp->if_opackets += le32toh(sp->tx_good); 1816 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1817 if (sp->rx_good) { 1818 ifp->if_ipackets += le32toh(sp->rx_good); 1819 sc->rx_idle_secs = 0; 1820 } else { 1821 /* 1822 * Receiver's been idle for another second. 1823 */ 1824 sc->rx_idle_secs++; 1825 } 1826 ifp->if_ierrors += 1827 le32toh(sp->rx_crc_errors) + 1828 le32toh(sp->rx_alignment_errors) + 1829 le32toh(sp->rx_rnr_errors) + 1830 le32toh(sp->rx_overrun_errors); 1831 /* 1832 * If any transmit underruns occured, bump up the transmit 1833 * threshold by another 512 bytes (64 * 8). 1834 */ 1835 if (sp->tx_underruns) { 1836 ifp->if_oerrors += le32toh(sp->tx_underruns); 1837 if (tx_threshold < 192) 1838 tx_threshold += 64; 1839 } 1840 1841 /* 1842 * Release any xmit buffers that have completed DMA. This isn't 1843 * strictly necessary to do here, but it's advantagous for mbufs 1844 * with external storage to be released in a timely manner rather 1845 * than being defered for a potentially long time. This limits 1846 * the delay to a maximum of one second. 1847 */ 1848 fxp_txeof(sc); 1849 1850 /* 1851 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1852 * then assume the receiver has locked up and attempt to clear 1853 * the condition by reprogramming the multicast filter. This is 1854 * a work-around for a bug in the 82557 where the receiver locks 1855 * up if it gets certain types of garbage in the syncronization 1856 * bits prior to the packet header. This bug is supposed to only 1857 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1858 * mode as well (perhaps due to a 10/100 speed transition). 1859 */ 1860 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1861 sc->rx_idle_secs = 0; 1862 fxp_mc_setup(sc); 1863 } 1864 /* 1865 * If there is no pending command, start another stats 1866 * dump. Otherwise punt for now. 1867 */ 1868 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1869 /* 1870 * Start another stats dump. 1871 */ 1872 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1873 BUS_DMASYNC_PREREAD); 1874 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1875 } else { 1876 /* 1877 * A previous command is still waiting to be accepted. 1878 * Just zero our copy of the stats and wait for the 1879 * next timer event to update them. 1880 */ 1881 sp->tx_good = 0; 1882 sp->tx_underruns = 0; 1883 sp->tx_total_collisions = 0; 1884 1885 sp->rx_good = 0; 1886 sp->rx_crc_errors = 0; 1887 sp->rx_alignment_errors = 0; 1888 sp->rx_rnr_errors = 0; 1889 sp->rx_overrun_errors = 0; 1890 } 1891 if (sc->miibus != NULL) 1892 mii_tick(device_get_softc(sc->miibus)); 1893 1894 /* 1895 * Schedule another timeout one second from now. 1896 */ 1897 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1898 FXP_UNLOCK(sc); 1899 splx(s); 1900} 1901 1902/* 1903 * Stop the interface. Cancels the statistics updater and resets 1904 * the interface. 1905 */ 1906static void 1907fxp_stop(struct fxp_softc *sc) 1908{ 1909 struct ifnet *ifp = &sc->sc_if; 1910 struct fxp_tx *txp; 1911 int i; 1912 1913 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1914 ifp->if_timer = 0; 1915 1916#ifdef DEVICE_POLLING 1917 ether_poll_deregister(ifp); 1918#endif 1919 /* 1920 * Cancel stats updater. 1921 */ 1922 callout_stop(&sc->stat_ch); 1923 1924 /* 1925 * Issue software reset, which also unloads the microcode. 1926 */ 1927 sc->flags &= ~FXP_FLAG_UCODE; 1928 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1929 DELAY(50); 1930 1931 /* 1932 * Release any xmit buffers. 1933 */ 1934 txp = sc->fxp_desc.tx_list; 1935 if (txp != NULL) { 1936 for (i = 0; i < FXP_NTXCB; i++) { 1937 if (txp[i].tx_mbuf != NULL) { 1938 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1939 BUS_DMASYNC_POSTWRITE); 1940 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1941 m_freem(txp[i].tx_mbuf); 1942 txp[i].tx_mbuf = NULL; 1943 /* clear this to reset csum offload bits */ 1944 txp[i].tx_cb->tbd[0].tb_addr = 0; 1945 } 1946 } 1947 } 1948 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1949 sc->tx_queued = 0; 1950} 1951 1952/* 1953 * Watchdog/transmission transmit timeout handler. Called when a 1954 * transmission is started on the interface, but no interrupt is 1955 * received before the timeout. This usually indicates that the 1956 * card has wedged for some reason. 1957 */ 1958static void 1959fxp_watchdog(struct ifnet *ifp) 1960{ 1961 struct fxp_softc *sc = ifp->if_softc; 1962 1963 FXP_LOCK(sc); 1964 device_printf(sc->dev, "device timeout\n"); 1965 ifp->if_oerrors++; 1966 1967 fxp_init_body(sc); 1968 FXP_UNLOCK(sc); 1969} 1970 1971/* 1972 * Acquire locks and then call the real initialization function. This 1973 * is necessary because ether_ioctl() calls if_init() and this would 1974 * result in mutex recursion if the mutex was held. 1975 */ 1976static void 1977fxp_init(void *xsc) 1978{ 1979 struct fxp_softc *sc = xsc; 1980 1981 FXP_LOCK(sc); 1982 fxp_init_body(sc); 1983 FXP_UNLOCK(sc); 1984} 1985 1986/* 1987 * Perform device initialization. This routine must be called with the 1988 * softc lock held. 1989 */ 1990static void 1991fxp_init_body(struct fxp_softc *sc) 1992{ 1993 struct ifnet *ifp = &sc->sc_if; 1994 struct fxp_cb_config *cbp; 1995 struct fxp_cb_ias *cb_ias; 1996 struct fxp_cb_tx *tcbp; 1997 struct fxp_tx *txp; 1998 struct fxp_cb_mcs *mcsp; 1999 int i, prm, s; 2000 2001 mtx_assert(&sc->sc_mtx, MA_OWNED); 2002 s = splimp(); 2003 /* 2004 * Cancel any pending I/O 2005 */ 2006 fxp_stop(sc); 2007 2008 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2009 2010 /* 2011 * Initialize base of CBL and RFA memory. Loading with zero 2012 * sets it up for regular linear addressing. 2013 */ 2014 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2015 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2016 2017 fxp_scb_wait(sc); 2018 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2019 2020 /* 2021 * Initialize base of dump-stats buffer. 2022 */ 2023 fxp_scb_wait(sc); 2024 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2025 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2026 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2027 2028 /* 2029 * Attempt to load microcode if requested. 2030 */ 2031 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2032 fxp_load_ucode(sc); 2033 2034 /* 2035 * Initialize the multicast address list. 2036 */ 2037 if (fxp_mc_addrs(sc)) { 2038 mcsp = sc->mcsp; 2039 mcsp->cb_status = 0; 2040 mcsp->cb_command = 2041 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2042 mcsp->link_addr = 0xffffffff; 2043 /* 2044 * Start the multicast setup command. 2045 */ 2046 fxp_scb_wait(sc); 2047 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2048 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2049 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2050 /* ...and wait for it to complete. */ 2051 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2052 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2053 BUS_DMASYNC_POSTWRITE); 2054 } 2055 2056 /* 2057 * We temporarily use memory that contains the TxCB list to 2058 * construct the config CB. The TxCB list memory is rebuilt 2059 * later. 2060 */ 2061 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2062 2063 /* 2064 * This bcopy is kind of disgusting, but there are a bunch of must be 2065 * zero and must be one bits in this structure and this is the easiest 2066 * way to initialize them all to proper values. 2067 */ 2068 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2069 2070 cbp->cb_status = 0; 2071 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2072 FXP_CB_COMMAND_EL); 2073 cbp->link_addr = 0xffffffff; /* (no) next command */ 2074 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2075 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2076 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2077 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2078 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2079 cbp->type_enable = 0; /* actually reserved */ 2080 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2081 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2082 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2083 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2084 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2085 cbp->late_scb = 0; /* (don't) defer SCB update */ 2086 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2087 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2088 cbp->ci_int = 1; /* interrupt on CU idle */ 2089 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2090 cbp->ext_stats_dis = 1; /* disable extended counters */ 2091 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2092 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2093 cbp->disc_short_rx = !prm; /* discard short packets */ 2094 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2095 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2096 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2097 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2098 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2099 cbp->csma_dis = 0; /* (don't) disable link */ 2100 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2101 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2102 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2103 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2104 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2105 cbp->nsai = 1; /* (don't) disable source addr insert */ 2106 cbp->preamble_length = 2; /* (7 byte) preamble */ 2107 cbp->loopback = 0; /* (don't) loopback */ 2108 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2109 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2110 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2111 cbp->promiscuous = prm; /* promiscuous mode */ 2112 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2113 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2114 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2115 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2116 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2117 2118 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2119 cbp->padding = 1; /* (do) pad short tx packets */ 2120 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2121 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2122 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2123 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2124 /* must set wake_en in PMCSR also */ 2125 cbp->force_fdx = 0; /* (don't) force full duplex */ 2126 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2127 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2128 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2129 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2130 2131 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2132 /* 2133 * The 82557 has no hardware flow control, the values 2134 * below are the defaults for the chip. 2135 */ 2136 cbp->fc_delay_lsb = 0; 2137 cbp->fc_delay_msb = 0x40; 2138 cbp->pri_fc_thresh = 3; 2139 cbp->tx_fc_dis = 0; 2140 cbp->rx_fc_restop = 0; 2141 cbp->rx_fc_restart = 0; 2142 cbp->fc_filter = 0; 2143 cbp->pri_fc_loc = 1; 2144 } else { 2145 cbp->fc_delay_lsb = 0x1f; 2146 cbp->fc_delay_msb = 0x01; 2147 cbp->pri_fc_thresh = 3; 2148 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2149 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2150 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2151 cbp->fc_filter = !prm; /* drop FC frames to host */ 2152 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2153 } 2154 2155 /* 2156 * Start the config command/DMA. 2157 */ 2158 fxp_scb_wait(sc); 2159 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2160 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2162 /* ...and wait for it to complete. */ 2163 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2164 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2165 2166 /* 2167 * Now initialize the station address. Temporarily use the TxCB 2168 * memory area like we did above for the config CB. 2169 */ 2170 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2171 cb_ias->cb_status = 0; 2172 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2173 cb_ias->link_addr = 0xffffffff; 2174 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2175 sizeof(sc->arpcom.ac_enaddr)); 2176 2177 /* 2178 * Start the IAS (Individual Address Setup) command/DMA. 2179 */ 2180 fxp_scb_wait(sc); 2181 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2182 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2183 /* ...and wait for it to complete. */ 2184 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2185 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2186 2187 /* 2188 * Initialize transmit control block (TxCB) list. 2189 */ 2190 txp = sc->fxp_desc.tx_list; 2191 tcbp = sc->fxp_desc.cbl_list; 2192 bzero(tcbp, FXP_TXCB_SZ); 2193 for (i = 0; i < FXP_NTXCB; i++) { 2194 txp[i].tx_cb = tcbp + i; 2195 txp[i].tx_mbuf = NULL; 2196 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2197 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2198 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2199 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2200 if (sc->flags & FXP_FLAG_EXT_TXCB) 2201 tcbp[i].tbd_array_addr = 2202 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2203 else 2204 tcbp[i].tbd_array_addr = 2205 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2206 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2207 } 2208 /* 2209 * Set the suspend flag on the first TxCB and start the control 2210 * unit. It will execute the NOP and then suspend. 2211 */ 2212 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2213 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2214 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2215 sc->tx_queued = 1; 2216 2217 fxp_scb_wait(sc); 2218 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2219 2220 /* 2221 * Initialize receiver buffer area - RFA. 2222 */ 2223 fxp_scb_wait(sc); 2224 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2225 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2226 2227 /* 2228 * Set current media. 2229 */ 2230 if (sc->miibus != NULL) 2231 mii_mediachg(device_get_softc(sc->miibus)); 2232 2233 ifp->if_flags |= IFF_RUNNING; 2234 ifp->if_flags &= ~IFF_OACTIVE; 2235 2236 /* 2237 * Enable interrupts. 2238 */ 2239#ifdef DEVICE_POLLING 2240 /* 2241 * ... but only do that if we are not polling. And because (presumably) 2242 * the default is interrupts on, we need to disable them explicitly! 2243 */ 2244 if ( ifp->if_flags & IFF_POLLING ) 2245 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2246 else 2247#endif /* DEVICE_POLLING */ 2248 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2249 2250 /* 2251 * Start stats updater. 2252 */ 2253 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2254 splx(s); 2255} 2256 2257static int 2258fxp_serial_ifmedia_upd(struct ifnet *ifp) 2259{ 2260 2261 return (0); 2262} 2263 2264static void 2265fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2266{ 2267 2268 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2269} 2270 2271/* 2272 * Change media according to request. 2273 */ 2274static int 2275fxp_ifmedia_upd(struct ifnet *ifp) 2276{ 2277 struct fxp_softc *sc = ifp->if_softc; 2278 struct mii_data *mii; 2279 2280 mii = device_get_softc(sc->miibus); 2281 mii_mediachg(mii); 2282 return (0); 2283} 2284 2285/* 2286 * Notify the world which media we're using. 2287 */ 2288static void 2289fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2290{ 2291 struct fxp_softc *sc = ifp->if_softc; 2292 struct mii_data *mii; 2293 2294 mii = device_get_softc(sc->miibus); 2295 mii_pollstat(mii); 2296 ifmr->ifm_active = mii->mii_media_active; 2297 ifmr->ifm_status = mii->mii_media_status; 2298 2299 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2300 sc->cu_resume_bug = 1; 2301 else 2302 sc->cu_resume_bug = 0; 2303} 2304 2305/* 2306 * Add a buffer to the end of the RFA buffer list. 2307 * Return 0 if successful, 1 for failure. A failure results in 2308 * adding the 'oldm' (if non-NULL) on to the end of the list - 2309 * tossing out its old contents and recycling it. 2310 * The RFA struct is stuck at the beginning of mbuf cluster and the 2311 * data pointer is fixed up to point just past it. 2312 */ 2313static int 2314fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2315{ 2316 struct mbuf *m; 2317 struct fxp_rfa *rfa, *p_rfa; 2318 struct fxp_rx *p_rx; 2319 bus_dmamap_t tmp_map; 2320 int error; 2321 2322 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2323 if (m == NULL) 2324 return (ENOBUFS); 2325 2326 /* 2327 * Move the data pointer up so that the incoming data packet 2328 * will be 32-bit aligned. 2329 */ 2330 m->m_data += RFA_ALIGNMENT_FUDGE; 2331 2332 /* 2333 * Get a pointer to the base of the mbuf cluster and move 2334 * data start past it. 2335 */ 2336 rfa = mtod(m, struct fxp_rfa *); 2337 m->m_data += sc->rfa_size; 2338 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2339 2340 rfa->rfa_status = 0; 2341 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2342 rfa->actual_size = 0; 2343 2344 /* 2345 * Initialize the rest of the RFA. Note that since the RFA 2346 * is misaligned, we cannot store values directly. We're thus 2347 * using the le32enc() function which handles endianness and 2348 * is also alignment-safe. 2349 */ 2350 le32enc(&rfa->link_addr, 0xffffffff); 2351 le32enc(&rfa->rbd_addr, 0xffffffff); 2352 2353 /* Map the RFA into DMA memory. */ 2354 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2355 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2356 &rxp->rx_addr, 0); 2357 if (error) { 2358 m_freem(m); 2359 return (error); 2360 } 2361 2362 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2363 tmp_map = sc->spare_map; 2364 sc->spare_map = rxp->rx_map; 2365 rxp->rx_map = tmp_map; 2366 rxp->rx_mbuf = m; 2367 2368 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2369 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2370 2371 /* 2372 * If there are other buffers already on the list, attach this 2373 * one to the end by fixing up the tail to point to this one. 2374 */ 2375 if (sc->fxp_desc.rx_head != NULL) { 2376 p_rx = sc->fxp_desc.rx_tail; 2377 p_rfa = (struct fxp_rfa *) 2378 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2379 p_rx->rx_next = rxp; 2380 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2381 p_rfa->rfa_control = 0; 2382 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2383 BUS_DMASYNC_PREWRITE); 2384 } else { 2385 rxp->rx_next = NULL; 2386 sc->fxp_desc.rx_head = rxp; 2387 } 2388 sc->fxp_desc.rx_tail = rxp; 2389 return (0); 2390} 2391 2392static volatile int 2393fxp_miibus_readreg(device_t dev, int phy, int reg) 2394{ 2395 struct fxp_softc *sc = device_get_softc(dev); 2396 int count = 10000; 2397 int value; 2398 2399 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2400 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2401 2402 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2403 && count--) 2404 DELAY(10); 2405 2406 if (count <= 0) 2407 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2408 2409 return (value & 0xffff); 2410} 2411 2412static void 2413fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2414{ 2415 struct fxp_softc *sc = device_get_softc(dev); 2416 int count = 10000; 2417 2418 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2419 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2420 (value & 0xffff)); 2421 2422 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2423 count--) 2424 DELAY(10); 2425 2426 if (count <= 0) 2427 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2428} 2429 2430static int 2431fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2432{ 2433 struct fxp_softc *sc = ifp->if_softc; 2434 struct ifreq *ifr = (struct ifreq *)data; 2435 struct mii_data *mii; 2436 int flag, mask, s, error = 0; 2437 2438 /* 2439 * Detaching causes us to call ioctl with the mutex owned. Preclude 2440 * that by saying we're busy if the lock is already held. 2441 */ 2442 if (mtx_owned(&sc->sc_mtx)) 2443 return (EBUSY); 2444 2445 FXP_LOCK(sc); 2446 s = splimp(); 2447 2448 switch (command) { 2449 case SIOCSIFFLAGS: 2450 if (ifp->if_flags & IFF_ALLMULTI) 2451 sc->flags |= FXP_FLAG_ALL_MCAST; 2452 else 2453 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2454 2455 /* 2456 * If interface is marked up and not running, then start it. 2457 * If it is marked down and running, stop it. 2458 * XXX If it's up then re-initialize it. This is so flags 2459 * such as IFF_PROMISC are handled. 2460 */ 2461 if (ifp->if_flags & IFF_UP) { 2462 fxp_init_body(sc); 2463 } else { 2464 if (ifp->if_flags & IFF_RUNNING) 2465 fxp_stop(sc); 2466 } 2467 break; 2468 2469 case SIOCADDMULTI: 2470 case SIOCDELMULTI: 2471 if (ifp->if_flags & IFF_ALLMULTI) 2472 sc->flags |= FXP_FLAG_ALL_MCAST; 2473 else 2474 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2475 /* 2476 * Multicast list has changed; set the hardware filter 2477 * accordingly. 2478 */ 2479 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2480 fxp_mc_setup(sc); 2481 /* 2482 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2483 * again rather than else {}. 2484 */ 2485 if (sc->flags & FXP_FLAG_ALL_MCAST) 2486 fxp_init_body(sc); 2487 error = 0; 2488 break; 2489 2490 case SIOCSIFMEDIA: 2491 case SIOCGIFMEDIA: 2492 if (sc->miibus != NULL) { 2493 mii = device_get_softc(sc->miibus); 2494 error = ifmedia_ioctl(ifp, ifr, 2495 &mii->mii_media, command); 2496 } else { 2497 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2498 } 2499 break; 2500 2501 case SIOCSIFCAP: 2502 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2503 if (mask & IFCAP_POLLING) 2504 ifp->if_capenable ^= IFCAP_POLLING; 2505 if (mask & IFCAP_VLAN_MTU) { 2506 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2507 if (sc->revision != FXP_REV_82557) 2508 flag = FXP_FLAG_LONG_PKT_EN; 2509 else /* a hack to get long frames on the old chip */ 2510 flag = FXP_FLAG_SAVE_BAD; 2511 sc->flags ^= flag; 2512 if (ifp->if_flags & IFF_UP) 2513 fxp_init_body(sc); 2514 } 2515 break; 2516 2517 default: 2518 /* 2519 * ether_ioctl() will eventually call fxp_start() which 2520 * will result in mutex recursion so drop it first. 2521 */ 2522 FXP_UNLOCK(sc); 2523 error = ether_ioctl(ifp, command, data); 2524 } 2525 if (mtx_owned(&sc->sc_mtx)) 2526 FXP_UNLOCK(sc); 2527 splx(s); 2528 return (error); 2529} 2530 2531/* 2532 * Fill in the multicast address list and return number of entries. 2533 */ 2534static int 2535fxp_mc_addrs(struct fxp_softc *sc) 2536{ 2537 struct fxp_cb_mcs *mcsp = sc->mcsp; 2538 struct ifnet *ifp = &sc->sc_if; 2539 struct ifmultiaddr *ifma; 2540 int nmcasts; 2541 2542 nmcasts = 0; 2543 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2544#if __FreeBSD_version < 500000 2545 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2546#else 2547 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2548#endif 2549 if (ifma->ifma_addr->sa_family != AF_LINK) 2550 continue; 2551 if (nmcasts >= MAXMCADDR) { 2552 sc->flags |= FXP_FLAG_ALL_MCAST; 2553 nmcasts = 0; 2554 break; 2555 } 2556 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2557 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2558 nmcasts++; 2559 } 2560 } 2561 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2562 return (nmcasts); 2563} 2564 2565/* 2566 * Program the multicast filter. 2567 * 2568 * We have an artificial restriction that the multicast setup command 2569 * must be the first command in the chain, so we take steps to ensure 2570 * this. By requiring this, it allows us to keep up the performance of 2571 * the pre-initialized command ring (esp. link pointers) by not actually 2572 * inserting the mcsetup command in the ring - i.e. its link pointer 2573 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2574 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2575 * lead into the regular TxCB ring when it completes. 2576 * 2577 * This function must be called at splimp. 2578 */ 2579static void 2580fxp_mc_setup(struct fxp_softc *sc) 2581{ 2582 struct fxp_cb_mcs *mcsp = sc->mcsp; 2583 struct ifnet *ifp = &sc->sc_if; 2584 struct fxp_tx *txp; 2585 int count; 2586 2587 /* 2588 * If there are queued commands, we must wait until they are all 2589 * completed. If we are already waiting, then add a NOP command 2590 * with interrupt option so that we're notified when all commands 2591 * have been completed - fxp_start() ensures that no additional 2592 * TX commands will be added when need_mcsetup is true. 2593 */ 2594 if (sc->tx_queued) { 2595 /* 2596 * need_mcsetup will be true if we are already waiting for the 2597 * NOP command to be completed (see below). In this case, bail. 2598 */ 2599 if (sc->need_mcsetup) 2600 return; 2601 sc->need_mcsetup = 1; 2602 2603 /* 2604 * Add a NOP command with interrupt so that we are notified 2605 * when all TX commands have been processed. 2606 */ 2607 txp = sc->fxp_desc.tx_last->tx_next; 2608 txp->tx_mbuf = NULL; 2609 txp->tx_cb->cb_status = 0; 2610 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2611 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2612 /* 2613 * Advance the end of list forward. 2614 */ 2615 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2616 htole16(~FXP_CB_COMMAND_S); 2617 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2618 sc->fxp_desc.tx_last = txp; 2619 sc->tx_queued++; 2620 /* 2621 * Issue a resume in case the CU has just suspended. 2622 */ 2623 fxp_scb_wait(sc); 2624 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2625 /* 2626 * Set a 5 second timer just in case we don't hear from the 2627 * card again. 2628 */ 2629 ifp->if_timer = 5; 2630 2631 return; 2632 } 2633 sc->need_mcsetup = 0; 2634 2635 /* 2636 * Initialize multicast setup descriptor. 2637 */ 2638 mcsp->cb_status = 0; 2639 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2640 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2641 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2642 txp = &sc->fxp_desc.mcs_tx; 2643 txp->tx_mbuf = NULL; 2644 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2645 txp->tx_next = sc->fxp_desc.tx_list; 2646 (void) fxp_mc_addrs(sc); 2647 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2648 sc->tx_queued = 1; 2649 2650 /* 2651 * Wait until command unit is not active. This should never 2652 * be the case when nothing is queued, but make sure anyway. 2653 */ 2654 count = 100; 2655 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2656 FXP_SCB_CUS_ACTIVE && --count) 2657 DELAY(10); 2658 if (count == 0) { 2659 device_printf(sc->dev, "command queue timeout\n"); 2660 return; 2661 } 2662 2663 /* 2664 * Start the multicast setup command. 2665 */ 2666 fxp_scb_wait(sc); 2667 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2668 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2669 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2670 2671 ifp->if_timer = 2; 2672 return; 2673} 2674 2675static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2676static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2677static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2678static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2679static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2680static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2681 2682#define UCODE(x) x, sizeof(x) 2683 2684struct ucode { 2685 u_int32_t revision; 2686 u_int32_t *ucode; 2687 int length; 2688 u_short int_delay_offset; 2689 u_short bundle_max_offset; 2690} ucode_table[] = { 2691 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2692 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2693 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2694 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2695 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2696 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2697 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2698 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2699 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2700 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2701 { 0, NULL, 0, 0, 0 } 2702}; 2703 2704static void 2705fxp_load_ucode(struct fxp_softc *sc) 2706{ 2707 struct ucode *uc; 2708 struct fxp_cb_ucode *cbp; 2709 2710 for (uc = ucode_table; uc->ucode != NULL; uc++) 2711 if (sc->revision == uc->revision) 2712 break; 2713 if (uc->ucode == NULL) 2714 return; 2715 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2716 cbp->cb_status = 0; 2717 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2718 cbp->link_addr = 0xffffffff; /* (no) next command */ 2719 memcpy(cbp->ucode, uc->ucode, uc->length); 2720 if (uc->int_delay_offset) 2721 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2722 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2723 if (uc->bundle_max_offset) 2724 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2725 htole16(sc->tunable_bundle_max); 2726 /* 2727 * Download the ucode to the chip. 2728 */ 2729 fxp_scb_wait(sc); 2730 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2732 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2733 /* ...and wait for it to complete. */ 2734 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2735 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2736 device_printf(sc->dev, 2737 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2738 sc->tunable_int_delay, 2739 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2740 sc->flags |= FXP_FLAG_UCODE; 2741} 2742 2743static int 2744sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2745{ 2746 int error, value; 2747 2748 value = *(int *)arg1; 2749 error = sysctl_handle_int(oidp, &value, 0, req); 2750 if (error || !req->newptr) 2751 return (error); 2752 if (value < low || value > high) 2753 return (EINVAL); 2754 *(int *)arg1 = value; 2755 return (0); 2756} 2757 2758/* 2759 * Interrupt delay is expressed in microseconds, a multiplier is used 2760 * to convert this to the appropriate clock ticks before using. 2761 */ 2762static int 2763sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2764{ 2765 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2766} 2767 2768static int 2769sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2770{ 2771 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2772} 2773