if_fxp.c revision 129616
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 129616 2004-05-23 16:11:53Z mux $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49 50#include <net/bpf.h> 51#include <sys/sockio.h> 52#include <sys/bus.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if_arp.h> 59 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <dev/pci/pcivar.h> 73#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, pci, 1, 1, 1); 83MODULE_DEPEND(fxp, ether, 1, 1, 1); 84MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85#include "miibus_if.h" 86 87/* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96#define RFA_ALIGNMENT_FUDGE 2 97 98/* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103static int tx_threshold = 64; 104 105/* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139}; 140 141struct fxp_ident { 142 u_int16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145}; 146 147/* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 172 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 190 { 0, -1, NULL }, 191}; 192 193#ifdef FXP_IP_CSUM_WAR 194#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 195#else 196#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 197#endif 198 199static int fxp_probe(device_t dev); 200static int fxp_attach(device_t dev); 201static int fxp_detach(device_t dev); 202static int fxp_shutdown(device_t dev); 203static int fxp_suspend(device_t dev); 204static int fxp_resume(device_t dev); 205 206static void fxp_intr(void *xsc); 207static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 208 u_int8_t statack, int count); 209static void fxp_init(void *xsc); 210static void fxp_init_body(struct fxp_softc *sc); 211static void fxp_tick(void *xsc); 212#ifndef BURN_BRIDGES 213static void fxp_powerstate_d0(device_t dev); 214#endif 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static void fxp_stop(struct fxp_softc *sc); 218static void fxp_release(struct fxp_softc *sc); 219static int fxp_ioctl(struct ifnet *ifp, u_long command, 220 caddr_t data); 221static void fxp_watchdog(struct ifnet *ifp); 222static int fxp_add_rfabuf(struct fxp_softc *sc, 223 struct fxp_rx *rxp); 224static int fxp_mc_addrs(struct fxp_softc *sc); 225static void fxp_mc_setup(struct fxp_softc *sc); 226static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 227 int autosize); 228static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 229 u_int16_t data); 230static void fxp_autosize_eeprom(struct fxp_softc *sc); 231static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235static int fxp_ifmedia_upd(struct ifnet *ifp); 236static void fxp_ifmedia_sts(struct ifnet *ifp, 237 struct ifmediareq *ifmr); 238static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 239static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 240 struct ifmediareq *ifmr); 241static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 242static void fxp_miibus_writereg(device_t dev, int phy, int reg, 243 int value); 244static void fxp_load_ucode(struct fxp_softc *sc); 245static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 246 int low, int high); 247static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 248static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 249static void fxp_scb_wait(struct fxp_softc *sc); 250static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 251static void fxp_dma_wait(struct fxp_softc *sc, 252 volatile u_int16_t *status, bus_dma_tag_t dmat, 253 bus_dmamap_t map); 254 255static device_method_t fxp_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, fxp_probe), 258 DEVMETHOD(device_attach, fxp_attach), 259 DEVMETHOD(device_detach, fxp_detach), 260 DEVMETHOD(device_shutdown, fxp_shutdown), 261 DEVMETHOD(device_suspend, fxp_suspend), 262 DEVMETHOD(device_resume, fxp_resume), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 267 268 { 0, 0 } 269}; 270 271static driver_t fxp_driver = { 272 "fxp", 273 fxp_methods, 274 sizeof(struct fxp_softc), 275}; 276 277static devclass_t fxp_devclass; 278 279DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 280DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 282 283static int fxp_rnr; 284SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 285 286static int fxp_noflow; 287SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 288TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 289 290/* 291 * Wait for the previous command to be accepted (but not necessarily 292 * completed). 293 */ 294static void 295fxp_scb_wait(struct fxp_softc *sc) 296{ 297 int i = 10000; 298 299 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 300 DELAY(2); 301 if (i == 0) 302 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 303 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 304 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 305 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 306 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 307} 308 309static void 310fxp_scb_cmd(struct fxp_softc *sc, int cmd) 311{ 312 313 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 314 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 315 fxp_scb_wait(sc); 316 } 317 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 318} 319 320static void 321fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 322 bus_dma_tag_t dmat, bus_dmamap_t map) 323{ 324 int i = 10000; 325 326 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 327 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 328 DELAY(2); 329 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 330 } 331 if (i == 0) 332 device_printf(sc->dev, "DMA timeout\n"); 333} 334 335/* 336 * Return identification string if this device is ours. 337 */ 338static int 339fxp_probe(device_t dev) 340{ 341 u_int16_t devid; 342 u_int8_t revid; 343 struct fxp_ident *ident; 344 345 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 346 devid = pci_get_device(dev); 347 revid = pci_get_revid(dev); 348 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 349 if (ident->devid == devid && 350 (ident->revid == revid || ident->revid == -1)) { 351 device_set_desc(dev, ident->name); 352 return (0); 353 } 354 } 355 } 356 return (ENXIO); 357} 358 359#ifndef BURN_BRIDGES 360static void 361fxp_powerstate_d0(device_t dev) 362{ 363#if __FreeBSD_version >= 430002 364 u_int32_t iobase, membase, irq; 365 366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 367 /* Save important PCI config data. */ 368 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 369 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 370 irq = pci_read_config(dev, PCIR_INTLINE, 4); 371 372 /* Reset the power state. */ 373 device_printf(dev, "chip is in D%d power mode " 374 "-- setting to D0\n", pci_get_powerstate(dev)); 375 376 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 377 378 /* Restore PCI config data. */ 379 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 380 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 381 pci_write_config(dev, PCIR_INTLINE, irq, 4); 382 } 383#endif 384} 385#endif 386 387static void 388fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 389{ 390 u_int32_t *addr; 391 392 if (error) 393 return; 394 395 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 396 addr = arg; 397 *addr = segs->ds_addr; 398} 399 400static int 401fxp_attach(device_t dev) 402{ 403 int error = 0; 404 struct fxp_softc *sc = device_get_softc(dev); 405 struct ifnet *ifp; 406 struct fxp_rx *rxp; 407 u_int32_t val; 408 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 409 int i, rid, m1, m2, prefer_iomap, maxtxseg; 410 int s, ipcbxmit_disable; 411 412 sc->dev = dev; 413 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 414 sysctl_ctx_init(&sc->sysctl_ctx); 415 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 416 MTX_DEF); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 s = splimp(); 421 422 /* 423 * Enable bus mastering. 424 */ 425 pci_enable_busmaster(dev); 426 val = pci_read_config(dev, PCIR_COMMAND, 2); 427#ifndef BURN_BRIDGES 428 fxp_powerstate_d0(dev); 429#endif 430 /* 431 * Figure out which we should try first - memory mapping or i/o mapping? 432 * We default to memory mapping. Then we accept an override from the 433 * command line. Then we check to see which one is enabled. 434 */ 435 m1 = PCIM_CMD_MEMEN; 436 m2 = PCIM_CMD_PORTEN; 437 prefer_iomap = 0; 438 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 439 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 440 m1 = PCIM_CMD_PORTEN; 441 m2 = PCIM_CMD_MEMEN; 442 } 443 444 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 445 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 446 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 447 if (sc->mem == NULL) { 448 sc->rtp = 449 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 450 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 451 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 452 RF_ACTIVE); 453 } 454 455 if (!sc->mem) { 456 error = ENXIO; 457 goto fail; 458 } 459 if (bootverbose) { 460 device_printf(dev, "using %s space register mapping\n", 461 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 462 } 463 464 sc->sc_st = rman_get_bustag(sc->mem); 465 sc->sc_sh = rman_get_bushandle(sc->mem); 466 467 /* 468 * Allocate our interrupt. 469 */ 470 rid = 0; 471 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->irq == NULL) { 474 device_printf(dev, "could not map interrupt\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 /* 480 * Reset to a stable state. 481 */ 482 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 483 DELAY(10); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Determine whether we must use the 503 serial interface. 492 */ 493 fxp_read_eeprom(sc, &data, 6, 1); 494 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 495 (data & FXP_PHY_SERIAL_ONLY)) 496 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 497 498 /* 499 * Create the sysctl tree 500 */ 501 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 502 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 503 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 504 if (sc->sysctl_tree == NULL) { 505 error = ENXIO; 506 goto fail; 507 } 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573#if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579#endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 599 /* enable reception of long frames for VLAN */ 600 sc->flags |= FXP_FLAG_LONG_PKT_EN; 601 } 602 603 /* 604 * Enable use of extended RFDs and TCBs for 82550 605 * and later chips. Note: we need extended TXCB support 606 * too, but that's already enabled by the code above. 607 * Be careful to do this only on the right devices. 608 * 609 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 610 * truncate packets that end with an mbuf containing 1 to 3 bytes 611 * when used with this feature enabled in the previous version of the 612 * driver. This problem appears to be fixed now that the driver 613 * always sets the hardware parse bit in the IPCB structure, which 614 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 615 * Source Software Developer Manual" says is necessary in the 616 * cases where packet truncation was observed. 617 * 618 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 619 * allows this feature to be disabled at boot time. 620 * 621 * If fxp is not compiled into the kernel, this feature may also 622 * be disabled at run time: 623 * # kldunload fxp 624 * # kenv hint.fxp.0.ipcbxmit_disable=1 625 * # kldload fxp 626 */ 627 628 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 629 &ipcbxmit_disable) != 0) 630 ipcbxmit_disable = 0; 631 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 632 sc->revision == FXP_REV_82550_C)) { 633 sc->rfa_size = sizeof (struct fxp_rfa); 634 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 635 sc->flags |= FXP_FLAG_EXT_RFA; 636 } else { 637 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 638 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 639 } 640 641 /* 642 * Allocate DMA tags and DMA safe memory. 643 */ 644 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 645 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 646 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 647 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 648 if (error) { 649 device_printf(dev, "could not allocate dma tag\n"); 650 goto fail; 651 } 652 653 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 654 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 655 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 656 &sc->fxp_stag); 657 if (error) { 658 device_printf(dev, "could not allocate dma tag\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 663 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 664 if (error) 665 goto fail; 666 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 667 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 668 if (error) { 669 device_printf(dev, "could not map the stats buffer\n"); 670 goto fail; 671 } 672 673 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 674 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 675 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 676 if (error) { 677 device_printf(dev, "could not allocate dma tag\n"); 678 goto fail; 679 } 680 681 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 682 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 683 if (error) 684 goto fail; 685 686 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 687 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 688 &sc->fxp_desc.cbl_addr, 0); 689 if (error) { 690 device_printf(dev, "could not map DMA memory\n"); 691 goto fail; 692 } 693 694 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 695 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 696 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 697 &sc->mcs_tag); 698 if (error) { 699 device_printf(dev, "could not allocate dma tag\n"); 700 goto fail; 701 } 702 703 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 704 BUS_DMA_NOWAIT, &sc->mcs_map); 705 if (error) 706 goto fail; 707 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 708 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 709 if (error) { 710 device_printf(dev, "can't map the multicast setup command\n"); 711 goto fail; 712 } 713 714 /* 715 * Pre-allocate the TX DMA maps. 716 */ 717 for (i = 0; i < FXP_NTXCB; i++) { 718 error = bus_dmamap_create(sc->fxp_mtag, 0, 719 &sc->fxp_desc.tx_list[i].tx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for TX\n"); 722 goto fail; 723 } 724 } 725 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 726 if (error) { 727 device_printf(dev, "can't create spare DMA map\n"); 728 goto fail; 729 } 730 731 /* 732 * Pre-allocate our receive buffers. 733 */ 734 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 735 for (i = 0; i < FXP_NRFABUFS; i++) { 736 rxp = &sc->fxp_desc.rx_list[i]; 737 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 738 if (error) { 739 device_printf(dev, "can't create DMA map for RX\n"); 740 goto fail; 741 } 742 if (fxp_add_rfabuf(sc, rxp) != 0) { 743 error = ENOMEM; 744 goto fail; 745 } 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 753 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 754 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 755 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 756 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 757 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 758 if (bootverbose) { 759 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 760 pci_get_vendor(dev), pci_get_device(dev), 761 pci_get_subvendor(dev), pci_get_subdevice(dev), 762 pci_get_revid(dev)); 763 fxp_read_eeprom(sc, &data, 10, 1); 764 device_printf(dev, "Dynamic Standby mode is %s\n", 765 data & 0x02 ? "enabled" : "disabled"); 766 } 767 768 /* 769 * If this is only a 10Mbps device, then there is no MII, and 770 * the PHY will use a serial interface instead. 771 * 772 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 773 * doesn't have a programming interface of any sort. The 774 * media is sensed automatically based on how the link partner 775 * is configured. This is, in essence, manual configuration. 776 */ 777 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 778 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 780 } else { 781 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 782 fxp_ifmedia_sts)) { 783 device_printf(dev, "MII without any PHY!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 } 788 789 ifp = &sc->arpcom.ac_if; 790 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 791 ifp->if_baudrate = 100000000; 792 ifp->if_init = fxp_init; 793 ifp->if_softc = sc; 794 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 795 ifp->if_ioctl = fxp_ioctl; 796 ifp->if_start = fxp_start; 797 ifp->if_watchdog = fxp_watchdog; 798 799 ifp->if_capabilities = ifp->if_capenable = 0; 800 801 /* Enable checksum offload for 82550 or better chips */ 802 if (sc->flags & FXP_FLAG_EXT_RFA) { 803 ifp->if_hwassist = FXP_CSUM_FEATURES; 804 ifp->if_capabilities |= IFCAP_HWCSUM; 805 ifp->if_capenable |= IFCAP_HWCSUM; 806 } 807 808#ifdef DEVICE_POLLING 809 /* Inform the world we support polling. */ 810 ifp->if_capabilities |= IFCAP_POLLING; 811 ifp->if_capenable |= IFCAP_POLLING; 812#endif 813 814 /* 815 * Attach the interface. 816 */ 817 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 818 819 /* 820 * Tell the upper layer(s) we support long frames. 821 * Must appear after the call to ether_ifattach() because 822 * ether_ifattach() sets ifi_hdrlen to the default value. 823 */ 824 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 825 ifp->if_capabilities |= IFCAP_VLAN_MTU; 826 ifp->if_capenable |= IFCAP_VLAN_MTU; 827 828 /* 829 * Let the system queue as many packets as we have available 830 * TX descriptors. 831 */ 832 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 833 834 /* 835 * Hook our interrupt after all initialization is complete. 836 * XXX This driver has been tested with the INTR_MPSAFFE flag set 837 * however, ifp and its functions are not fully locked so MPSAFE 838 * should not be used unless you can handle potential data loss. 839 */ 840 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 841 fxp_intr, sc, &sc->ih); 842 if (error) { 843 device_printf(dev, "could not setup irq\n"); 844 ether_ifdetach(&sc->arpcom.ac_if); 845 goto fail; 846 } 847 848fail: 849 splx(s); 850 if (error) 851 fxp_release(sc); 852 return (error); 853} 854 855/* 856 * Release all resources. The softc lock should not be held and the 857 * interrupt should already be torn down. 858 */ 859static void 860fxp_release(struct fxp_softc *sc) 861{ 862 struct fxp_rx *rxp; 863 struct fxp_tx *txp; 864 int i; 865 866 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 867 if (sc->ih) 868 panic("fxp_release() called with intr handle still active"); 869 if (sc->miibus) 870 device_delete_child(sc->dev, sc->miibus); 871 bus_generic_detach(sc->dev); 872 ifmedia_removeall(&sc->sc_media); 873 if (sc->fxp_desc.cbl_list) { 874 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 875 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 876 sc->cbl_map); 877 } 878 if (sc->fxp_stats) { 879 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 880 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 881 } 882 if (sc->mcsp) { 883 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 884 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 885 } 886 if (sc->irq) 887 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 888 if (sc->mem) 889 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 890 if (sc->fxp_mtag) { 891 for (i = 0; i < FXP_NRFABUFS; i++) { 892 rxp = &sc->fxp_desc.rx_list[i]; 893 if (rxp->rx_mbuf != NULL) { 894 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 895 BUS_DMASYNC_POSTREAD); 896 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 897 m_freem(rxp->rx_mbuf); 898 } 899 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 900 } 901 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 902 bus_dma_tag_destroy(sc->fxp_mtag); 903 } 904 if (sc->fxp_stag) { 905 for (i = 0; i < FXP_NTXCB; i++) { 906 txp = &sc->fxp_desc.tx_list[i]; 907 if (txp->tx_mbuf != NULL) { 908 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 909 BUS_DMASYNC_POSTWRITE); 910 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 911 m_freem(txp->tx_mbuf); 912 } 913 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 914 } 915 bus_dma_tag_destroy(sc->fxp_stag); 916 } 917 if (sc->cbl_tag) 918 bus_dma_tag_destroy(sc->cbl_tag); 919 if (sc->mcs_tag) 920 bus_dma_tag_destroy(sc->mcs_tag); 921 922 sysctl_ctx_free(&sc->sysctl_ctx); 923 924 mtx_destroy(&sc->sc_mtx); 925} 926 927/* 928 * Detach interface. 929 */ 930static int 931fxp_detach(device_t dev) 932{ 933 struct fxp_softc *sc = device_get_softc(dev); 934 int s; 935 936 FXP_LOCK(sc); 937 s = splimp(); 938 939 sc->suspended = 1; /* Do same thing as we do for suspend */ 940 /* 941 * Close down routes etc. 942 */ 943 ether_ifdetach(&sc->arpcom.ac_if); 944 945 /* 946 * Stop DMA and drop transmit queue, but disable interrupts first. 947 */ 948 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 949 fxp_stop(sc); 950 FXP_UNLOCK(sc); 951 952 /* 953 * Unhook interrupt before dropping lock. This is to prevent 954 * races with fxp_intr(). 955 */ 956 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 957 sc->ih = NULL; 958 959 splx(s); 960 961 /* Release our allocated resources. */ 962 fxp_release(sc); 963 return (0); 964} 965 966/* 967 * Device shutdown routine. Called at system shutdown after sync. The 968 * main purpose of this routine is to shut off receiver DMA so that 969 * kernel memory doesn't get clobbered during warmboot. 970 */ 971static int 972fxp_shutdown(device_t dev) 973{ 974 /* 975 * Make sure that DMA is disabled prior to reboot. Not doing 976 * do could allow DMA to corrupt kernel memory during the 977 * reboot before the driver initializes. 978 */ 979 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 980 return (0); 981} 982 983/* 984 * Device suspend routine. Stop the interface and save some PCI 985 * settings in case the BIOS doesn't restore them properly on 986 * resume. 987 */ 988static int 989fxp_suspend(device_t dev) 990{ 991 struct fxp_softc *sc = device_get_softc(dev); 992 int i, s; 993 994 FXP_LOCK(sc); 995 s = splimp(); 996 997 fxp_stop(sc); 998 999 for (i = 0; i < 5; i++) 1000 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1001 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1002 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1003 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1004 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1005 1006 sc->suspended = 1; 1007 1008 FXP_UNLOCK(sc); 1009 splx(s); 1010 return (0); 1011} 1012 1013/* 1014 * Device resume routine. Restore some PCI settings in case the BIOS 1015 * doesn't, re-enable busmastering, and restart the interface if 1016 * appropriate. 1017 */ 1018static int 1019fxp_resume(device_t dev) 1020{ 1021 struct fxp_softc *sc = device_get_softc(dev); 1022 struct ifnet *ifp = &sc->sc_if; 1023 u_int16_t pci_command; 1024 int i, s; 1025 1026 FXP_LOCK(sc); 1027 s = splimp(); 1028#ifndef BURN_BRIDGES 1029 fxp_powerstate_d0(dev); 1030#endif 1031 /* better way to do this? */ 1032 for (i = 0; i < 5; i++) 1033 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1034 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1035 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1036 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1037 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1038 1039 /* reenable busmastering */ 1040 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1041 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1042 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1043 1044 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1045 DELAY(10); 1046 1047 /* reinitialize interface if necessary */ 1048 if (ifp->if_flags & IFF_UP) 1049 fxp_init_body(sc); 1050 1051 sc->suspended = 0; 1052 1053 FXP_UNLOCK(sc); 1054 splx(s); 1055 return (0); 1056} 1057 1058static void 1059fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1060{ 1061 u_int16_t reg; 1062 int x; 1063 1064 /* 1065 * Shift in data. 1066 */ 1067 for (x = 1 << (length - 1); x; x >>= 1) { 1068 if (data & x) 1069 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1070 else 1071 reg = FXP_EEPROM_EECS; 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1073 DELAY(1); 1074 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1075 DELAY(1); 1076 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1077 DELAY(1); 1078 } 1079} 1080 1081/* 1082 * Read from the serial EEPROM. Basically, you manually shift in 1083 * the read opcode (one bit at a time) and then shift in the address, 1084 * and then you shift out the data (all of this one bit at a time). 1085 * The word size is 16 bits, so you have to provide the address for 1086 * every 16 bits of data. 1087 */ 1088static u_int16_t 1089fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1090{ 1091 u_int16_t reg, data; 1092 int x; 1093 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1095 /* 1096 * Shift in read opcode. 1097 */ 1098 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1099 /* 1100 * Shift in address. 1101 */ 1102 data = 0; 1103 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1104 if (offset & x) 1105 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1106 else 1107 reg = FXP_EEPROM_EECS; 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1109 DELAY(1); 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1111 DELAY(1); 1112 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1113 DELAY(1); 1114 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1115 data++; 1116 if (autosize && reg == 0) { 1117 sc->eeprom_size = data; 1118 break; 1119 } 1120 } 1121 /* 1122 * Shift out data. 1123 */ 1124 data = 0; 1125 reg = FXP_EEPROM_EECS; 1126 for (x = 1 << 15; x; x >>= 1) { 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1128 DELAY(1); 1129 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1130 data |= x; 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1132 DELAY(1); 1133 } 1134 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1135 DELAY(1); 1136 1137 return (data); 1138} 1139 1140static void 1141fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1142{ 1143 int i; 1144 1145 /* 1146 * Erase/write enable. 1147 */ 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1149 fxp_eeprom_shiftin(sc, 0x4, 3); 1150 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1152 DELAY(1); 1153 /* 1154 * Shift in write opcode, address, data. 1155 */ 1156 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1157 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1158 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1159 fxp_eeprom_shiftin(sc, data, 16); 1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1161 DELAY(1); 1162 /* 1163 * Wait for EEPROM to finish up. 1164 */ 1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1166 DELAY(1); 1167 for (i = 0; i < 1000; i++) { 1168 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1169 break; 1170 DELAY(50); 1171 } 1172 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1173 DELAY(1); 1174 /* 1175 * Erase/write disable. 1176 */ 1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1178 fxp_eeprom_shiftin(sc, 0x4, 3); 1179 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1180 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1181 DELAY(1); 1182} 1183 1184/* 1185 * From NetBSD: 1186 * 1187 * Figure out EEPROM size. 1188 * 1189 * 559's can have either 64-word or 256-word EEPROMs, the 558 1190 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1191 * talks about the existance of 16 to 256 word EEPROMs. 1192 * 1193 * The only known sizes are 64 and 256, where the 256 version is used 1194 * by CardBus cards to store CIS information. 1195 * 1196 * The address is shifted in msb-to-lsb, and after the last 1197 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1198 * after which follows the actual data. We try to detect this zero, by 1199 * probing the data-out bit in the EEPROM control register just after 1200 * having shifted in a bit. If the bit is zero, we assume we've 1201 * shifted enough address bits. The data-out should be tri-state, 1202 * before this, which should translate to a logical one. 1203 */ 1204static void 1205fxp_autosize_eeprom(struct fxp_softc *sc) 1206{ 1207 1208 /* guess maximum size of 256 words */ 1209 sc->eeprom_size = 8; 1210 1211 /* autosize */ 1212 (void) fxp_eeprom_getword(sc, 0, 1); 1213} 1214 1215static void 1216fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1217{ 1218 int i; 1219 1220 for (i = 0; i < words; i++) 1221 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1222} 1223 1224static void 1225fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1226{ 1227 int i; 1228 1229 for (i = 0; i < words; i++) 1230 fxp_eeprom_putword(sc, offset + i, data[i]); 1231} 1232 1233static void 1234fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1235 bus_size_t mapsize, int error) 1236{ 1237 struct fxp_softc *sc; 1238 struct fxp_cb_tx *txp; 1239 int i; 1240 1241 if (error) 1242 return; 1243 1244 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1245 1246 sc = arg; 1247 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1248 for (i = 0; i < nseg; i++) { 1249 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1250 /* 1251 * If this is an 82550/82551, then we're using extended 1252 * TxCBs _and_ we're using checksum offload. This means 1253 * that the TxCB is really an IPCB. One major difference 1254 * between the two is that with plain extended TxCBs, 1255 * the bottom half of the TxCB contains two entries from 1256 * the TBD array, whereas IPCBs contain just one entry: 1257 * one entry (8 bytes) has been sacrificed for the TCP/IP 1258 * checksum offload control bits. So to make things work 1259 * right, we have to start filling in the TBD array 1260 * starting from a different place depending on whether 1261 * the chip is an 82550/82551 or not. 1262 */ 1263 if (sc->flags & FXP_FLAG_EXT_RFA) { 1264 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1265 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1266 } else { 1267 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1268 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1269 } 1270 } 1271 txp->tbd_number = nseg; 1272} 1273 1274/* 1275 * Grab the softc lock and call the real fxp_start_body() routine 1276 */ 1277static void 1278fxp_start(struct ifnet *ifp) 1279{ 1280 struct fxp_softc *sc = ifp->if_softc; 1281 1282 FXP_LOCK(sc); 1283 fxp_start_body(ifp); 1284 FXP_UNLOCK(sc); 1285} 1286 1287/* 1288 * Start packet transmission on the interface. 1289 * This routine must be called with the softc lock held, and is an 1290 * internal entry point only. 1291 */ 1292static void 1293fxp_start_body(struct ifnet *ifp) 1294{ 1295 struct fxp_softc *sc = ifp->if_softc; 1296 struct fxp_tx *txp; 1297 struct mbuf *mb_head; 1298 int error; 1299 1300 mtx_assert(&sc->sc_mtx, MA_OWNED); 1301 /* 1302 * See if we need to suspend xmit until the multicast filter 1303 * has been reprogrammed (which can only be done at the head 1304 * of the command chain). 1305 */ 1306 if (sc->need_mcsetup) { 1307 return; 1308 } 1309 1310 txp = NULL; 1311 1312 /* 1313 * We're finished if there is nothing more to add to the list or if 1314 * we're all filled up with buffers to transmit. 1315 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1316 * a NOP command when needed. 1317 */ 1318 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1319 1320 /* 1321 * Grab a packet to transmit. 1322 */ 1323 IF_DEQUEUE(&ifp->if_snd, mb_head); 1324 1325 /* 1326 * Get pointer to next available tx desc. 1327 */ 1328 txp = sc->fxp_desc.tx_last->tx_next; 1329 1330 /* 1331 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1332 * Ethernet Controller Family Open Source Software 1333 * Developer Manual says: 1334 * Using software parsing is only allowed with legal 1335 * TCP/IP or UDP/IP packets. 1336 * ... 1337 * For all other datagrams, hardware parsing must 1338 * be used. 1339 * Software parsing appears to truncate ICMP and 1340 * fragmented UDP packets that contain one to three 1341 * bytes in the second (and final) mbuf of the packet. 1342 */ 1343 if (sc->flags & FXP_FLAG_EXT_RFA) 1344 txp->tx_cb->ipcb_ip_activation_high = 1345 FXP_IPCB_HARDWAREPARSING_ENABLE; 1346 1347 /* 1348 * Deal with TCP/IP checksum offload. Note that 1349 * in order for TCP checksum offload to work, 1350 * the pseudo header checksum must have already 1351 * been computed and stored in the checksum field 1352 * in the TCP header. The stack should have 1353 * already done this for us. 1354 */ 1355 1356 if (mb_head->m_pkthdr.csum_flags) { 1357 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1358 txp->tx_cb->ipcb_ip_schedule = 1359 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1360 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1361 txp->tx_cb->ipcb_ip_schedule |= 1362 FXP_IPCB_TCP_PACKET; 1363 } 1364#ifdef FXP_IP_CSUM_WAR 1365 /* 1366 * XXX The 82550 chip appears to have trouble 1367 * dealing with IP header checksums in very small 1368 * datagrams, namely fragments from 1 to 3 bytes 1369 * in size. For example, say you want to transmit 1370 * a UDP packet of 1473 bytes. The packet will be 1371 * fragmented over two IP datagrams, the latter 1372 * containing only one byte of data. The 82550 will 1373 * botch the header checksum on the 1-byte fragment. 1374 * As long as the datagram contains 4 or more bytes 1375 * of data, you're ok. 1376 * 1377 * The following code attempts to work around this 1378 * problem: if the datagram is less than 38 bytes 1379 * in size (14 bytes ether header, 20 bytes IP header, 1380 * plus 4 bytes of data), we punt and compute the IP 1381 * header checksum by hand. This workaround doesn't 1382 * work very well, however, since it can be fooled 1383 * by things like VLAN tags and IP options that make 1384 * the header sizes/offsets vary. 1385 */ 1386 1387 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1388 if (mb_head->m_pkthdr.len < 38) { 1389 struct ip *ip; 1390 mb_head->m_data += ETHER_HDR_LEN; 1391 ip = mtod(mb_head, struct ip *); 1392 ip->ip_sum = in_cksum(mb_head, 1393 ip->ip_hl << 2); 1394 mb_head->m_data -= ETHER_HDR_LEN; 1395 } else { 1396 txp->tx_cb->ipcb_ip_activation_high = 1397 FXP_IPCB_HARDWAREPARSING_ENABLE; 1398 txp->tx_cb->ipcb_ip_schedule |= 1399 FXP_IPCB_IP_CHECKSUM_ENABLE; 1400 } 1401 } 1402#endif 1403 } 1404 1405 /* 1406 * Go through each of the mbufs in the chain and initialize 1407 * the transmit buffer descriptors with the physical address 1408 * and size of the mbuf. 1409 */ 1410 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1411 mb_head, fxp_dma_map_txbuf, sc, 0); 1412 1413 if (error && error != EFBIG) { 1414 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1415 error); 1416 m_freem(mb_head); 1417 break; 1418 } 1419 1420 if (error) { 1421 struct mbuf *mn; 1422 1423 /* 1424 * We ran out of segments. We have to recopy this 1425 * mbuf chain first. Bail out if we can't get the 1426 * new buffers. 1427 */ 1428 mn = m_defrag(mb_head, M_DONTWAIT); 1429 if (mn == NULL) { 1430 m_freem(mb_head); 1431 break; 1432 } else { 1433 mb_head = mn; 1434 } 1435 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1436 mb_head, fxp_dma_map_txbuf, sc, 0); 1437 if (error) { 1438 device_printf(sc->dev, 1439 "can't map mbuf (error %d)\n", error); 1440 m_freem(mb_head); 1441 break; 1442 } 1443 } 1444 1445 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1446 BUS_DMASYNC_PREWRITE); 1447 1448 txp->tx_mbuf = mb_head; 1449 txp->tx_cb->cb_status = 0; 1450 txp->tx_cb->byte_count = 0; 1451 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1452 txp->tx_cb->cb_command = 1453 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1454 FXP_CB_COMMAND_S); 1455 } else { 1456 txp->tx_cb->cb_command = 1457 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1458 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1459 /* 1460 * Set a 5 second timer just in case we don't hear 1461 * from the card again. 1462 */ 1463 ifp->if_timer = 5; 1464 } 1465 txp->tx_cb->tx_threshold = tx_threshold; 1466 1467 /* 1468 * Advance the end of list forward. 1469 */ 1470 1471#ifdef __alpha__ 1472 /* 1473 * On platforms which can't access memory in 16-bit 1474 * granularities, we must prevent the card from DMA'ing 1475 * up the status while we update the command field. 1476 * This could cause us to overwrite the completion status. 1477 * XXX This is probably bogus and we're _not_ looking 1478 * for atomicity here. 1479 */ 1480 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1481 htole16(FXP_CB_COMMAND_S)); 1482#else 1483 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1484 htole16(~FXP_CB_COMMAND_S); 1485#endif /*__alpha__*/ 1486 sc->fxp_desc.tx_last = txp; 1487 1488 /* 1489 * Advance the beginning of the list forward if there are 1490 * no other packets queued (when nothing is queued, tx_first 1491 * sits on the last TxCB that was sent out). 1492 */ 1493 if (sc->tx_queued == 0) 1494 sc->fxp_desc.tx_first = txp; 1495 1496 sc->tx_queued++; 1497 1498 /* 1499 * Pass packet to bpf if there is a listener. 1500 */ 1501 BPF_MTAP(ifp, mb_head); 1502 } 1503 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1504 1505 /* 1506 * We're finished. If we added to the list, issue a RESUME to get DMA 1507 * going again if suspended. 1508 */ 1509 if (txp != NULL) { 1510 fxp_scb_wait(sc); 1511 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1512 } 1513} 1514 1515#ifdef DEVICE_POLLING 1516static poll_handler_t fxp_poll; 1517 1518static void 1519fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1520{ 1521 struct fxp_softc *sc = ifp->if_softc; 1522 u_int8_t statack; 1523 1524 FXP_LOCK(sc); 1525 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1526 ether_poll_deregister(ifp); 1527 cmd = POLL_DEREGISTER; 1528 } 1529 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1530 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1531 FXP_UNLOCK(sc); 1532 return; 1533 } 1534 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1535 FXP_SCB_STATACK_FR; 1536 if (cmd == POLL_AND_CHECK_STATUS) { 1537 u_int8_t tmp; 1538 1539 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1540 if (tmp == 0xff || tmp == 0) { 1541 FXP_UNLOCK(sc); 1542 return; /* nothing to do */ 1543 } 1544 tmp &= ~statack; 1545 /* ack what we can */ 1546 if (tmp != 0) 1547 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1548 statack |= tmp; 1549 } 1550 fxp_intr_body(sc, ifp, statack, count); 1551 FXP_UNLOCK(sc); 1552} 1553#endif /* DEVICE_POLLING */ 1554 1555/* 1556 * Process interface interrupts. 1557 */ 1558static void 1559fxp_intr(void *xsc) 1560{ 1561 struct fxp_softc *sc = xsc; 1562 struct ifnet *ifp = &sc->sc_if; 1563 u_int8_t statack; 1564 1565 FXP_LOCK(sc); 1566 if (sc->suspended) { 1567 FXP_UNLOCK(sc); 1568 return; 1569 } 1570 1571#ifdef DEVICE_POLLING 1572 if (ifp->if_flags & IFF_POLLING) { 1573 FXP_UNLOCK(sc); 1574 return; 1575 } 1576 if ((ifp->if_capenable & IFCAP_POLLING) && 1577 ether_poll_register(fxp_poll, ifp)) { 1578 /* disable interrupts */ 1579 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1580 FXP_UNLOCK(sc); 1581 fxp_poll(ifp, 0, 1); 1582 return; 1583 } 1584#endif 1585 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1586 /* 1587 * It should not be possible to have all bits set; the 1588 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1589 * all bits are set, this may indicate that the card has 1590 * been physically ejected, so ignore it. 1591 */ 1592 if (statack == 0xff) { 1593 FXP_UNLOCK(sc); 1594 return; 1595 } 1596 1597 /* 1598 * First ACK all the interrupts in this pass. 1599 */ 1600 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1601 fxp_intr_body(sc, ifp, statack, -1); 1602 } 1603 FXP_UNLOCK(sc); 1604} 1605 1606static void 1607fxp_txeof(struct fxp_softc *sc) 1608{ 1609 struct fxp_tx *txp; 1610 1611 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1612 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1613 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1614 txp = txp->tx_next) { 1615 if (txp->tx_mbuf != NULL) { 1616 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1617 BUS_DMASYNC_POSTWRITE); 1618 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1619 m_freem(txp->tx_mbuf); 1620 txp->tx_mbuf = NULL; 1621 /* clear this to reset csum offload bits */ 1622 txp->tx_cb->tbd[0].tb_addr = 0; 1623 } 1624 sc->tx_queued--; 1625 } 1626 sc->fxp_desc.tx_first = txp; 1627 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1628} 1629 1630static void 1631fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1632 int count) 1633{ 1634 struct mbuf *m; 1635 struct fxp_rx *rxp; 1636 struct fxp_rfa *rfa; 1637 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1638 1639 mtx_assert(&sc->sc_mtx, MA_OWNED); 1640 if (rnr) 1641 fxp_rnr++; 1642#ifdef DEVICE_POLLING 1643 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1644 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1645 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1646 rnr = 1; 1647 } 1648#endif 1649 1650 /* 1651 * Free any finished transmit mbuf chains. 1652 * 1653 * Handle the CNA event likt a CXTNO event. It used to 1654 * be that this event (control unit not ready) was not 1655 * encountered, but it is now with the SMPng modifications. 1656 * The exact sequence of events that occur when the interface 1657 * is brought up are different now, and if this event 1658 * goes unhandled, the configuration/rxfilter setup sequence 1659 * can stall for several seconds. The result is that no 1660 * packets go out onto the wire for about 5 to 10 seconds 1661 * after the interface is ifconfig'ed for the first time. 1662 */ 1663 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1664 fxp_txeof(sc); 1665 1666 ifp->if_timer = 0; 1667 if (sc->tx_queued == 0) { 1668 if (sc->need_mcsetup) 1669 fxp_mc_setup(sc); 1670 } 1671 /* 1672 * Try to start more packets transmitting. 1673 */ 1674 if (ifp->if_snd.ifq_head != NULL) 1675 fxp_start_body(ifp); 1676 } 1677 1678 /* 1679 * Just return if nothing happened on the receive side. 1680 */ 1681 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1682 return; 1683 1684 /* 1685 * Process receiver interrupts. If a no-resource (RNR) 1686 * condition exists, get whatever packets we can and 1687 * re-start the receiver. 1688 * 1689 * When using polling, we do not process the list to completion, 1690 * so when we get an RNR interrupt we must defer the restart 1691 * until we hit the last buffer with the C bit set. 1692 * If we run out of cycles and rfa_headm has the C bit set, 1693 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1694 * that the info will be used in the subsequent polling cycle. 1695 */ 1696 for (;;) { 1697 rxp = sc->fxp_desc.rx_head; 1698 m = rxp->rx_mbuf; 1699 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1700 RFA_ALIGNMENT_FUDGE); 1701 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1702 BUS_DMASYNC_POSTREAD); 1703 1704#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1705 if (count >= 0 && count-- == 0) { 1706 if (rnr) { 1707 /* Defer RNR processing until the next time. */ 1708 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1709 rnr = 0; 1710 } 1711 break; 1712 } 1713#endif /* DEVICE_POLLING */ 1714 1715 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1716 break; 1717 1718 /* 1719 * Advance head forward. 1720 */ 1721 sc->fxp_desc.rx_head = rxp->rx_next; 1722 1723 /* 1724 * Add a new buffer to the receive chain. 1725 * If this fails, the old buffer is recycled 1726 * instead. 1727 */ 1728 if (fxp_add_rfabuf(sc, rxp) == 0) { 1729 int total_len; 1730 1731 /* 1732 * Fetch packet length (the top 2 bits of 1733 * actual_size are flags set by the controller 1734 * upon completion), and drop the packet in case 1735 * of bogus length or CRC errors. 1736 */ 1737 total_len = le16toh(rfa->actual_size) & 0x3fff; 1738 if (total_len < sizeof(struct ether_header) || 1739 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1740 sc->rfa_size || 1741 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1742 m_freem(m); 1743 continue; 1744 } 1745 1746 /* Do IP checksum checking. */ 1747 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1748 if (rfa->rfax_csum_sts & 1749 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1750 m->m_pkthdr.csum_flags |= 1751 CSUM_IP_CHECKED; 1752 if (rfa->rfax_csum_sts & 1753 FXP_RFDX_CS_IP_CSUM_VALID) 1754 m->m_pkthdr.csum_flags |= 1755 CSUM_IP_VALID; 1756 if ((rfa->rfax_csum_sts & 1757 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1758 (rfa->rfax_csum_sts & 1759 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1760 m->m_pkthdr.csum_flags |= 1761 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1762 m->m_pkthdr.csum_data = 0xffff; 1763 } 1764 } 1765 1766 m->m_pkthdr.len = m->m_len = total_len; 1767 m->m_pkthdr.rcvif = ifp; 1768 1769 /* 1770 * Drop locks before calling if_input() since it 1771 * may re-enter fxp_start() in the netisr case. 1772 * This would result in a lock reversal. Better 1773 * performance might be obtained by chaining all 1774 * packets received, dropping the lock, and then 1775 * calling if_input() on each one. 1776 */ 1777 FXP_UNLOCK(sc); 1778 (*ifp->if_input)(ifp, m); 1779 FXP_LOCK(sc); 1780 } 1781 } 1782 if (rnr) { 1783 fxp_scb_wait(sc); 1784 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1785 sc->fxp_desc.rx_head->rx_addr); 1786 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1787 } 1788} 1789 1790/* 1791 * Update packet in/out/collision statistics. The i82557 doesn't 1792 * allow you to access these counters without doing a fairly 1793 * expensive DMA to get _all_ of the statistics it maintains, so 1794 * we do this operation here only once per second. The statistics 1795 * counters in the kernel are updated from the previous dump-stats 1796 * DMA and then a new dump-stats DMA is started. The on-chip 1797 * counters are zeroed when the DMA completes. If we can't start 1798 * the DMA immediately, we don't wait - we just prepare to read 1799 * them again next time. 1800 */ 1801static void 1802fxp_tick(void *xsc) 1803{ 1804 struct fxp_softc *sc = xsc; 1805 struct ifnet *ifp = &sc->sc_if; 1806 struct fxp_stats *sp = sc->fxp_stats; 1807 int s; 1808 1809 FXP_LOCK(sc); 1810 s = splimp(); 1811 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1812 ifp->if_opackets += le32toh(sp->tx_good); 1813 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1814 if (sp->rx_good) { 1815 ifp->if_ipackets += le32toh(sp->rx_good); 1816 sc->rx_idle_secs = 0; 1817 } else { 1818 /* 1819 * Receiver's been idle for another second. 1820 */ 1821 sc->rx_idle_secs++; 1822 } 1823 ifp->if_ierrors += 1824 le32toh(sp->rx_crc_errors) + 1825 le32toh(sp->rx_alignment_errors) + 1826 le32toh(sp->rx_rnr_errors) + 1827 le32toh(sp->rx_overrun_errors); 1828 /* 1829 * If any transmit underruns occured, bump up the transmit 1830 * threshold by another 512 bytes (64 * 8). 1831 */ 1832 if (sp->tx_underruns) { 1833 ifp->if_oerrors += le32toh(sp->tx_underruns); 1834 if (tx_threshold < 192) 1835 tx_threshold += 64; 1836 } 1837 1838 /* 1839 * Release any xmit buffers that have completed DMA. This isn't 1840 * strictly necessary to do here, but it's advantagous for mbufs 1841 * with external storage to be released in a timely manner rather 1842 * than being defered for a potentially long time. This limits 1843 * the delay to a maximum of one second. 1844 */ 1845 fxp_txeof(sc); 1846 1847 /* 1848 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1849 * then assume the receiver has locked up and attempt to clear 1850 * the condition by reprogramming the multicast filter. This is 1851 * a work-around for a bug in the 82557 where the receiver locks 1852 * up if it gets certain types of garbage in the syncronization 1853 * bits prior to the packet header. This bug is supposed to only 1854 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1855 * mode as well (perhaps due to a 10/100 speed transition). 1856 */ 1857 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1858 sc->rx_idle_secs = 0; 1859 fxp_mc_setup(sc); 1860 } 1861 /* 1862 * If there is no pending command, start another stats 1863 * dump. Otherwise punt for now. 1864 */ 1865 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1866 /* 1867 * Start another stats dump. 1868 */ 1869 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1870 BUS_DMASYNC_PREREAD); 1871 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1872 } else { 1873 /* 1874 * A previous command is still waiting to be accepted. 1875 * Just zero our copy of the stats and wait for the 1876 * next timer event to update them. 1877 */ 1878 sp->tx_good = 0; 1879 sp->tx_underruns = 0; 1880 sp->tx_total_collisions = 0; 1881 1882 sp->rx_good = 0; 1883 sp->rx_crc_errors = 0; 1884 sp->rx_alignment_errors = 0; 1885 sp->rx_rnr_errors = 0; 1886 sp->rx_overrun_errors = 0; 1887 } 1888 if (sc->miibus != NULL) 1889 mii_tick(device_get_softc(sc->miibus)); 1890 1891 /* 1892 * Schedule another timeout one second from now. 1893 */ 1894 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1895 FXP_UNLOCK(sc); 1896 splx(s); 1897} 1898 1899/* 1900 * Stop the interface. Cancels the statistics updater and resets 1901 * the interface. 1902 */ 1903static void 1904fxp_stop(struct fxp_softc *sc) 1905{ 1906 struct ifnet *ifp = &sc->sc_if; 1907 struct fxp_tx *txp; 1908 int i; 1909 1910 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1911 ifp->if_timer = 0; 1912 1913#ifdef DEVICE_POLLING 1914 ether_poll_deregister(ifp); 1915#endif 1916 /* 1917 * Cancel stats updater. 1918 */ 1919 callout_stop(&sc->stat_ch); 1920 1921 /* 1922 * Issue software reset, which also unloads the microcode. 1923 */ 1924 sc->flags &= ~FXP_FLAG_UCODE; 1925 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1926 DELAY(50); 1927 1928 /* 1929 * Release any xmit buffers. 1930 */ 1931 txp = sc->fxp_desc.tx_list; 1932 if (txp != NULL) { 1933 for (i = 0; i < FXP_NTXCB; i++) { 1934 if (txp[i].tx_mbuf != NULL) { 1935 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1936 BUS_DMASYNC_POSTWRITE); 1937 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1938 m_freem(txp[i].tx_mbuf); 1939 txp[i].tx_mbuf = NULL; 1940 /* clear this to reset csum offload bits */ 1941 txp[i].tx_cb->tbd[0].tb_addr = 0; 1942 } 1943 } 1944 } 1945 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1946 sc->tx_queued = 0; 1947} 1948 1949/* 1950 * Watchdog/transmission transmit timeout handler. Called when a 1951 * transmission is started on the interface, but no interrupt is 1952 * received before the timeout. This usually indicates that the 1953 * card has wedged for some reason. 1954 */ 1955static void 1956fxp_watchdog(struct ifnet *ifp) 1957{ 1958 struct fxp_softc *sc = ifp->if_softc; 1959 1960 FXP_LOCK(sc); 1961 device_printf(sc->dev, "device timeout\n"); 1962 ifp->if_oerrors++; 1963 1964 fxp_init_body(sc); 1965 FXP_UNLOCK(sc); 1966} 1967 1968/* 1969 * Acquire locks and then call the real initialization function. This 1970 * is necessary because ether_ioctl() calls if_init() and this would 1971 * result in mutex recursion if the mutex was held. 1972 */ 1973static void 1974fxp_init(void *xsc) 1975{ 1976 struct fxp_softc *sc = xsc; 1977 1978 FXP_LOCK(sc); 1979 fxp_init_body(sc); 1980 FXP_UNLOCK(sc); 1981} 1982 1983/* 1984 * Perform device initialization. This routine must be called with the 1985 * softc lock held. 1986 */ 1987static void 1988fxp_init_body(struct fxp_softc *sc) 1989{ 1990 struct ifnet *ifp = &sc->sc_if; 1991 struct fxp_cb_config *cbp; 1992 struct fxp_cb_ias *cb_ias; 1993 struct fxp_cb_tx *tcbp; 1994 struct fxp_tx *txp; 1995 struct fxp_cb_mcs *mcsp; 1996 int i, prm, s; 1997 1998 mtx_assert(&sc->sc_mtx, MA_OWNED); 1999 s = splimp(); 2000 /* 2001 * Cancel any pending I/O 2002 */ 2003 fxp_stop(sc); 2004 2005 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2006 2007 /* 2008 * Initialize base of CBL and RFA memory. Loading with zero 2009 * sets it up for regular linear addressing. 2010 */ 2011 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2012 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2013 2014 fxp_scb_wait(sc); 2015 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2016 2017 /* 2018 * Initialize base of dump-stats buffer. 2019 */ 2020 fxp_scb_wait(sc); 2021 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2022 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2023 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2024 2025 /* 2026 * Attempt to load microcode if requested. 2027 */ 2028 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2029 fxp_load_ucode(sc); 2030 2031 /* 2032 * Initialize the multicast address list. 2033 */ 2034 if (fxp_mc_addrs(sc)) { 2035 mcsp = sc->mcsp; 2036 mcsp->cb_status = 0; 2037 mcsp->cb_command = 2038 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2039 mcsp->link_addr = 0xffffffff; 2040 /* 2041 * Start the multicast setup command. 2042 */ 2043 fxp_scb_wait(sc); 2044 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2045 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2046 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2047 /* ...and wait for it to complete. */ 2048 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2049 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2050 BUS_DMASYNC_POSTWRITE); 2051 } 2052 2053 /* 2054 * We temporarily use memory that contains the TxCB list to 2055 * construct the config CB. The TxCB list memory is rebuilt 2056 * later. 2057 */ 2058 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2059 2060 /* 2061 * This bcopy is kind of disgusting, but there are a bunch of must be 2062 * zero and must be one bits in this structure and this is the easiest 2063 * way to initialize them all to proper values. 2064 */ 2065 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2066 2067 cbp->cb_status = 0; 2068 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2069 FXP_CB_COMMAND_EL); 2070 cbp->link_addr = 0xffffffff; /* (no) next command */ 2071 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2072 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2073 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2074 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2075 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2076 cbp->type_enable = 0; /* actually reserved */ 2077 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2078 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2079 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2080 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2081 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2082 cbp->late_scb = 0; /* (don't) defer SCB update */ 2083 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2084 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2085 cbp->ci_int = 1; /* interrupt on CU idle */ 2086 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2087 cbp->ext_stats_dis = 1; /* disable extended counters */ 2088 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2089 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2090 cbp->disc_short_rx = !prm; /* discard short packets */ 2091 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2092 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2093 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2094 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2095 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2096 cbp->csma_dis = 0; /* (don't) disable link */ 2097 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2098 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2099 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2100 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2101 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2102 cbp->nsai = 1; /* (don't) disable source addr insert */ 2103 cbp->preamble_length = 2; /* (7 byte) preamble */ 2104 cbp->loopback = 0; /* (don't) loopback */ 2105 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2106 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2107 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2108 cbp->promiscuous = prm; /* promiscuous mode */ 2109 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2110 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2111 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2112 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2113 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2114 2115 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2116 cbp->padding = 1; /* (do) pad short tx packets */ 2117 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2118 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2119 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2120 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2121 /* must set wake_en in PMCSR also */ 2122 cbp->force_fdx = 0; /* (don't) force full duplex */ 2123 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2124 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2125 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2126 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2127 2128 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2129 /* 2130 * The 82557 has no hardware flow control, the values 2131 * below are the defaults for the chip. 2132 */ 2133 cbp->fc_delay_lsb = 0; 2134 cbp->fc_delay_msb = 0x40; 2135 cbp->pri_fc_thresh = 3; 2136 cbp->tx_fc_dis = 0; 2137 cbp->rx_fc_restop = 0; 2138 cbp->rx_fc_restart = 0; 2139 cbp->fc_filter = 0; 2140 cbp->pri_fc_loc = 1; 2141 } else { 2142 cbp->fc_delay_lsb = 0x1f; 2143 cbp->fc_delay_msb = 0x01; 2144 cbp->pri_fc_thresh = 3; 2145 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2146 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2147 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2148 cbp->fc_filter = !prm; /* drop FC frames to host */ 2149 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2150 } 2151 2152 /* 2153 * Start the config command/DMA. 2154 */ 2155 fxp_scb_wait(sc); 2156 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2157 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2158 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2159 /* ...and wait for it to complete. */ 2160 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2161 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2162 2163 /* 2164 * Now initialize the station address. Temporarily use the TxCB 2165 * memory area like we did above for the config CB. 2166 */ 2167 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2168 cb_ias->cb_status = 0; 2169 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2170 cb_ias->link_addr = 0xffffffff; 2171 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2172 sizeof(sc->arpcom.ac_enaddr)); 2173 2174 /* 2175 * Start the IAS (Individual Address Setup) command/DMA. 2176 */ 2177 fxp_scb_wait(sc); 2178 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2179 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2180 /* ...and wait for it to complete. */ 2181 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2182 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2183 2184 /* 2185 * Initialize transmit control block (TxCB) list. 2186 */ 2187 txp = sc->fxp_desc.tx_list; 2188 tcbp = sc->fxp_desc.cbl_list; 2189 bzero(tcbp, FXP_TXCB_SZ); 2190 for (i = 0; i < FXP_NTXCB; i++) { 2191 txp[i].tx_cb = tcbp + i; 2192 txp[i].tx_mbuf = NULL; 2193 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2194 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2195 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2196 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2197 if (sc->flags & FXP_FLAG_EXT_TXCB) 2198 tcbp[i].tbd_array_addr = 2199 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2200 else 2201 tcbp[i].tbd_array_addr = 2202 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2203 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2204 } 2205 /* 2206 * Set the suspend flag on the first TxCB and start the control 2207 * unit. It will execute the NOP and then suspend. 2208 */ 2209 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2210 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2211 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2212 sc->tx_queued = 1; 2213 2214 fxp_scb_wait(sc); 2215 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2216 2217 /* 2218 * Initialize receiver buffer area - RFA. 2219 */ 2220 fxp_scb_wait(sc); 2221 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2222 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2223 2224 /* 2225 * Set current media. 2226 */ 2227 if (sc->miibus != NULL) 2228 mii_mediachg(device_get_softc(sc->miibus)); 2229 2230 ifp->if_flags |= IFF_RUNNING; 2231 ifp->if_flags &= ~IFF_OACTIVE; 2232 2233 /* 2234 * Enable interrupts. 2235 */ 2236#ifdef DEVICE_POLLING 2237 /* 2238 * ... but only do that if we are not polling. And because (presumably) 2239 * the default is interrupts on, we need to disable them explicitly! 2240 */ 2241 if ( ifp->if_flags & IFF_POLLING ) 2242 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2243 else 2244#endif /* DEVICE_POLLING */ 2245 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2246 2247 /* 2248 * Start stats updater. 2249 */ 2250 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2251 splx(s); 2252} 2253 2254static int 2255fxp_serial_ifmedia_upd(struct ifnet *ifp) 2256{ 2257 2258 return (0); 2259} 2260 2261static void 2262fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2263{ 2264 2265 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2266} 2267 2268/* 2269 * Change media according to request. 2270 */ 2271static int 2272fxp_ifmedia_upd(struct ifnet *ifp) 2273{ 2274 struct fxp_softc *sc = ifp->if_softc; 2275 struct mii_data *mii; 2276 2277 mii = device_get_softc(sc->miibus); 2278 mii_mediachg(mii); 2279 return (0); 2280} 2281 2282/* 2283 * Notify the world which media we're using. 2284 */ 2285static void 2286fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2287{ 2288 struct fxp_softc *sc = ifp->if_softc; 2289 struct mii_data *mii; 2290 2291 mii = device_get_softc(sc->miibus); 2292 mii_pollstat(mii); 2293 ifmr->ifm_active = mii->mii_media_active; 2294 ifmr->ifm_status = mii->mii_media_status; 2295 2296 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2297 sc->cu_resume_bug = 1; 2298 else 2299 sc->cu_resume_bug = 0; 2300} 2301 2302/* 2303 * Add a buffer to the end of the RFA buffer list. 2304 * Return 0 if successful, 1 for failure. A failure results in 2305 * adding the 'oldm' (if non-NULL) on to the end of the list - 2306 * tossing out its old contents and recycling it. 2307 * The RFA struct is stuck at the beginning of mbuf cluster and the 2308 * data pointer is fixed up to point just past it. 2309 */ 2310static int 2311fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2312{ 2313 struct mbuf *m; 2314 struct fxp_rfa *rfa, *p_rfa; 2315 struct fxp_rx *p_rx; 2316 bus_dmamap_t tmp_map; 2317 int error; 2318 2319 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2320 if (m == NULL) 2321 return (ENOBUFS); 2322 2323 /* 2324 * Move the data pointer up so that the incoming data packet 2325 * will be 32-bit aligned. 2326 */ 2327 m->m_data += RFA_ALIGNMENT_FUDGE; 2328 2329 /* 2330 * Get a pointer to the base of the mbuf cluster and move 2331 * data start past it. 2332 */ 2333 rfa = mtod(m, struct fxp_rfa *); 2334 m->m_data += sc->rfa_size; 2335 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2336 2337 rfa->rfa_status = 0; 2338 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2339 rfa->actual_size = 0; 2340 2341 /* 2342 * Initialize the rest of the RFA. Note that since the RFA 2343 * is misaligned, we cannot store values directly. We're thus 2344 * using the le32enc() function which handles endianness and 2345 * is also alignment-safe. 2346 */ 2347 le32enc(&rfa->link_addr, 0xffffffff); 2348 le32enc(&rfa->rbd_addr, 0xffffffff); 2349 2350 /* Map the RFA into DMA memory. */ 2351 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2352 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2353 &rxp->rx_addr, 0); 2354 if (error) { 2355 m_freem(m); 2356 return (error); 2357 } 2358 2359 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2360 tmp_map = sc->spare_map; 2361 sc->spare_map = rxp->rx_map; 2362 rxp->rx_map = tmp_map; 2363 rxp->rx_mbuf = m; 2364 2365 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2366 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2367 2368 /* 2369 * If there are other buffers already on the list, attach this 2370 * one to the end by fixing up the tail to point to this one. 2371 */ 2372 if (sc->fxp_desc.rx_head != NULL) { 2373 p_rx = sc->fxp_desc.rx_tail; 2374 p_rfa = (struct fxp_rfa *) 2375 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2376 p_rx->rx_next = rxp; 2377 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2378 p_rfa->rfa_control = 0; 2379 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2380 BUS_DMASYNC_PREWRITE); 2381 } else { 2382 rxp->rx_next = NULL; 2383 sc->fxp_desc.rx_head = rxp; 2384 } 2385 sc->fxp_desc.rx_tail = rxp; 2386 return (0); 2387} 2388 2389static volatile int 2390fxp_miibus_readreg(device_t dev, int phy, int reg) 2391{ 2392 struct fxp_softc *sc = device_get_softc(dev); 2393 int count = 10000; 2394 int value; 2395 2396 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2397 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2398 2399 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2400 && count--) 2401 DELAY(10); 2402 2403 if (count <= 0) 2404 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2405 2406 return (value & 0xffff); 2407} 2408 2409static void 2410fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2411{ 2412 struct fxp_softc *sc = device_get_softc(dev); 2413 int count = 10000; 2414 2415 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2416 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2417 (value & 0xffff)); 2418 2419 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2420 count--) 2421 DELAY(10); 2422 2423 if (count <= 0) 2424 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2425} 2426 2427static int 2428fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2429{ 2430 struct fxp_softc *sc = ifp->if_softc; 2431 struct ifreq *ifr = (struct ifreq *)data; 2432 struct mii_data *mii; 2433 int s, error = 0; 2434 2435 /* 2436 * Detaching causes us to call ioctl with the mutex owned. Preclude 2437 * that by saying we're busy if the lock is already held. 2438 */ 2439 if (mtx_owned(&sc->sc_mtx)) 2440 return (EBUSY); 2441 2442 FXP_LOCK(sc); 2443 s = splimp(); 2444 2445 switch (command) { 2446 case SIOCSIFFLAGS: 2447 if (ifp->if_flags & IFF_ALLMULTI) 2448 sc->flags |= FXP_FLAG_ALL_MCAST; 2449 else 2450 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2451 2452 /* 2453 * If interface is marked up and not running, then start it. 2454 * If it is marked down and running, stop it. 2455 * XXX If it's up then re-initialize it. This is so flags 2456 * such as IFF_PROMISC are handled. 2457 */ 2458 if (ifp->if_flags & IFF_UP) { 2459 fxp_init_body(sc); 2460 } else { 2461 if (ifp->if_flags & IFF_RUNNING) 2462 fxp_stop(sc); 2463 } 2464 break; 2465 2466 case SIOCADDMULTI: 2467 case SIOCDELMULTI: 2468 if (ifp->if_flags & IFF_ALLMULTI) 2469 sc->flags |= FXP_FLAG_ALL_MCAST; 2470 else 2471 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2472 /* 2473 * Multicast list has changed; set the hardware filter 2474 * accordingly. 2475 */ 2476 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2477 fxp_mc_setup(sc); 2478 /* 2479 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2480 * again rather than else {}. 2481 */ 2482 if (sc->flags & FXP_FLAG_ALL_MCAST) 2483 fxp_init_body(sc); 2484 error = 0; 2485 break; 2486 2487 case SIOCSIFMEDIA: 2488 case SIOCGIFMEDIA: 2489 if (sc->miibus != NULL) { 2490 mii = device_get_softc(sc->miibus); 2491 error = ifmedia_ioctl(ifp, ifr, 2492 &mii->mii_media, command); 2493 } else { 2494 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2495 } 2496 break; 2497 2498 case SIOCSIFCAP: 2499 ifp->if_capenable = ifr->ifr_reqcap; 2500 break; 2501 2502 default: 2503 /* 2504 * ether_ioctl() will eventually call fxp_start() which 2505 * will result in mutex recursion so drop it first. 2506 */ 2507 FXP_UNLOCK(sc); 2508 error = ether_ioctl(ifp, command, data); 2509 } 2510 if (mtx_owned(&sc->sc_mtx)) 2511 FXP_UNLOCK(sc); 2512 splx(s); 2513 return (error); 2514} 2515 2516/* 2517 * Fill in the multicast address list and return number of entries. 2518 */ 2519static int 2520fxp_mc_addrs(struct fxp_softc *sc) 2521{ 2522 struct fxp_cb_mcs *mcsp = sc->mcsp; 2523 struct ifnet *ifp = &sc->sc_if; 2524 struct ifmultiaddr *ifma; 2525 int nmcasts; 2526 2527 nmcasts = 0; 2528 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2529#if __FreeBSD_version < 500000 2530 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2531#else 2532 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2533#endif 2534 if (ifma->ifma_addr->sa_family != AF_LINK) 2535 continue; 2536 if (nmcasts >= MAXMCADDR) { 2537 sc->flags |= FXP_FLAG_ALL_MCAST; 2538 nmcasts = 0; 2539 break; 2540 } 2541 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2542 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2543 nmcasts++; 2544 } 2545 } 2546 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2547 return (nmcasts); 2548} 2549 2550/* 2551 * Program the multicast filter. 2552 * 2553 * We have an artificial restriction that the multicast setup command 2554 * must be the first command in the chain, so we take steps to ensure 2555 * this. By requiring this, it allows us to keep up the performance of 2556 * the pre-initialized command ring (esp. link pointers) by not actually 2557 * inserting the mcsetup command in the ring - i.e. its link pointer 2558 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2559 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2560 * lead into the regular TxCB ring when it completes. 2561 * 2562 * This function must be called at splimp. 2563 */ 2564static void 2565fxp_mc_setup(struct fxp_softc *sc) 2566{ 2567 struct fxp_cb_mcs *mcsp = sc->mcsp; 2568 struct ifnet *ifp = &sc->sc_if; 2569 struct fxp_tx *txp; 2570 int count; 2571 2572 /* 2573 * If there are queued commands, we must wait until they are all 2574 * completed. If we are already waiting, then add a NOP command 2575 * with interrupt option so that we're notified when all commands 2576 * have been completed - fxp_start() ensures that no additional 2577 * TX commands will be added when need_mcsetup is true. 2578 */ 2579 if (sc->tx_queued) { 2580 /* 2581 * need_mcsetup will be true if we are already waiting for the 2582 * NOP command to be completed (see below). In this case, bail. 2583 */ 2584 if (sc->need_mcsetup) 2585 return; 2586 sc->need_mcsetup = 1; 2587 2588 /* 2589 * Add a NOP command with interrupt so that we are notified 2590 * when all TX commands have been processed. 2591 */ 2592 txp = sc->fxp_desc.tx_last->tx_next; 2593 txp->tx_mbuf = NULL; 2594 txp->tx_cb->cb_status = 0; 2595 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2596 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2597 /* 2598 * Advance the end of list forward. 2599 */ 2600 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2601 htole16(~FXP_CB_COMMAND_S); 2602 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2603 sc->fxp_desc.tx_last = txp; 2604 sc->tx_queued++; 2605 /* 2606 * Issue a resume in case the CU has just suspended. 2607 */ 2608 fxp_scb_wait(sc); 2609 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2610 /* 2611 * Set a 5 second timer just in case we don't hear from the 2612 * card again. 2613 */ 2614 ifp->if_timer = 5; 2615 2616 return; 2617 } 2618 sc->need_mcsetup = 0; 2619 2620 /* 2621 * Initialize multicast setup descriptor. 2622 */ 2623 mcsp->cb_status = 0; 2624 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2625 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2626 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2627 txp = &sc->fxp_desc.mcs_tx; 2628 txp->tx_mbuf = NULL; 2629 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2630 txp->tx_next = sc->fxp_desc.tx_list; 2631 (void) fxp_mc_addrs(sc); 2632 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2633 sc->tx_queued = 1; 2634 2635 /* 2636 * Wait until command unit is not active. This should never 2637 * be the case when nothing is queued, but make sure anyway. 2638 */ 2639 count = 100; 2640 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2641 FXP_SCB_CUS_ACTIVE && --count) 2642 DELAY(10); 2643 if (count == 0) { 2644 device_printf(sc->dev, "command queue timeout\n"); 2645 return; 2646 } 2647 2648 /* 2649 * Start the multicast setup command. 2650 */ 2651 fxp_scb_wait(sc); 2652 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2653 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2654 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2655 2656 ifp->if_timer = 2; 2657 return; 2658} 2659 2660static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2661static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2662static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2663static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2664static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2665static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2666 2667#define UCODE(x) x, sizeof(x) 2668 2669struct ucode { 2670 u_int32_t revision; 2671 u_int32_t *ucode; 2672 int length; 2673 u_short int_delay_offset; 2674 u_short bundle_max_offset; 2675} ucode_table[] = { 2676 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2677 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2678 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2679 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2680 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2681 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2682 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2683 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2684 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2685 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2686 { 0, NULL, 0, 0, 0 } 2687}; 2688 2689static void 2690fxp_load_ucode(struct fxp_softc *sc) 2691{ 2692 struct ucode *uc; 2693 struct fxp_cb_ucode *cbp; 2694 2695 for (uc = ucode_table; uc->ucode != NULL; uc++) 2696 if (sc->revision == uc->revision) 2697 break; 2698 if (uc->ucode == NULL) 2699 return; 2700 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2701 cbp->cb_status = 0; 2702 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2703 cbp->link_addr = 0xffffffff; /* (no) next command */ 2704 memcpy(cbp->ucode, uc->ucode, uc->length); 2705 if (uc->int_delay_offset) 2706 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2707 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2708 if (uc->bundle_max_offset) 2709 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2710 htole16(sc->tunable_bundle_max); 2711 /* 2712 * Download the ucode to the chip. 2713 */ 2714 fxp_scb_wait(sc); 2715 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2716 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2717 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2718 /* ...and wait for it to complete. */ 2719 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2720 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2721 device_printf(sc->dev, 2722 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2723 sc->tunable_int_delay, 2724 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2725 sc->flags |= FXP_FLAG_UCODE; 2726} 2727 2728static int 2729sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2730{ 2731 int error, value; 2732 2733 value = *(int *)arg1; 2734 error = sysctl_handle_int(oidp, &value, 0, req); 2735 if (error || !req->newptr) 2736 return (error); 2737 if (value < low || value > high) 2738 return (EINVAL); 2739 *(int *)arg1 = value; 2740 return (0); 2741} 2742 2743/* 2744 * Interrupt delay is expressed in microseconds, a multiplier is used 2745 * to convert this to the appropriate clock ticks before using. 2746 */ 2747static int 2748sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2749{ 2750 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2751} 2752 2753static int 2754sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2755{ 2756 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2757} 2758