if_fxp.c revision 129557
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 129557 2004-05-21 20:34:04Z yar $"); 32 33/* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49 50#include <net/bpf.h> 51#include <sys/sockio.h> 52#include <sys/bus.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if_arp.h> 59 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <dev/pci/pcivar.h> 73#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, pci, 1, 1, 1); 83MODULE_DEPEND(fxp, ether, 1, 1, 1); 84MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85#include "miibus_if.h" 86 87/* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96#define RFA_ALIGNMENT_FUDGE 2 97 98/* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103static int tx_threshold = 64; 104 105/* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139}; 140 141struct fxp_ident { 142 u_int16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145}; 146 147/* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 172 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 190 { 0, -1, NULL }, 191}; 192 193#ifdef FXP_IP_CSUM_WAR 194#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 195#else 196#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 197#endif 198 199static int fxp_probe(device_t dev); 200static int fxp_attach(device_t dev); 201static int fxp_detach(device_t dev); 202static int fxp_shutdown(device_t dev); 203static int fxp_suspend(device_t dev); 204static int fxp_resume(device_t dev); 205 206static void fxp_intr(void *xsc); 207static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 208 u_int8_t statack, int count); 209static void fxp_init(void *xsc); 210static void fxp_init_body(struct fxp_softc *sc); 211static void fxp_tick(void *xsc); 212#ifndef BURN_BRIDGES 213static void fxp_powerstate_d0(device_t dev); 214#endif 215static void fxp_start(struct ifnet *ifp); 216static void fxp_start_body(struct ifnet *ifp); 217static void fxp_stop(struct fxp_softc *sc); 218static void fxp_release(struct fxp_softc *sc); 219static int fxp_ioctl(struct ifnet *ifp, u_long command, 220 caddr_t data); 221static void fxp_watchdog(struct ifnet *ifp); 222static int fxp_add_rfabuf(struct fxp_softc *sc, 223 struct fxp_rx *rxp); 224static int fxp_mc_addrs(struct fxp_softc *sc); 225static void fxp_mc_setup(struct fxp_softc *sc); 226static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 227 int autosize); 228static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 229 u_int16_t data); 230static void fxp_autosize_eeprom(struct fxp_softc *sc); 231static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235static int fxp_ifmedia_upd(struct ifnet *ifp); 236static void fxp_ifmedia_sts(struct ifnet *ifp, 237 struct ifmediareq *ifmr); 238static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 239static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 240 struct ifmediareq *ifmr); 241static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 242static void fxp_miibus_writereg(device_t dev, int phy, int reg, 243 int value); 244static void fxp_load_ucode(struct fxp_softc *sc); 245static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 246 int low, int high); 247static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 248static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 249static void fxp_scb_wait(struct fxp_softc *sc); 250static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 251static void fxp_dma_wait(struct fxp_softc *sc, 252 volatile u_int16_t *status, bus_dma_tag_t dmat, 253 bus_dmamap_t map); 254 255static device_method_t fxp_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, fxp_probe), 258 DEVMETHOD(device_attach, fxp_attach), 259 DEVMETHOD(device_detach, fxp_detach), 260 DEVMETHOD(device_shutdown, fxp_shutdown), 261 DEVMETHOD(device_suspend, fxp_suspend), 262 DEVMETHOD(device_resume, fxp_resume), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 267 268 { 0, 0 } 269}; 270 271static driver_t fxp_driver = { 272 "fxp", 273 fxp_methods, 274 sizeof(struct fxp_softc), 275}; 276 277static devclass_t fxp_devclass; 278 279DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 280DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 281DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 282 283static int fxp_rnr; 284SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 285 286static int fxp_noflow; 287SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 288TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 289 290/* 291 * Wait for the previous command to be accepted (but not necessarily 292 * completed). 293 */ 294static void 295fxp_scb_wait(struct fxp_softc *sc) 296{ 297 int i = 10000; 298 299 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 300 DELAY(2); 301 if (i == 0) 302 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 303 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 304 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 305 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 306 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 307} 308 309static void 310fxp_scb_cmd(struct fxp_softc *sc, int cmd) 311{ 312 313 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 314 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 315 fxp_scb_wait(sc); 316 } 317 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 318} 319 320static void 321fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 322 bus_dma_tag_t dmat, bus_dmamap_t map) 323{ 324 int i = 10000; 325 326 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 327 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 328 DELAY(2); 329 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 330 } 331 if (i == 0) 332 device_printf(sc->dev, "DMA timeout\n"); 333} 334 335/* 336 * Return identification string if this device is ours. 337 */ 338static int 339fxp_probe(device_t dev) 340{ 341 u_int16_t devid; 342 u_int8_t revid; 343 struct fxp_ident *ident; 344 345 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 346 devid = pci_get_device(dev); 347 revid = pci_get_revid(dev); 348 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 349 if (ident->devid == devid && 350 (ident->revid == revid || ident->revid == -1)) { 351 device_set_desc(dev, ident->name); 352 return (0); 353 } 354 } 355 } 356 return (ENXIO); 357} 358 359#ifndef BURN_BRIDGES 360static void 361fxp_powerstate_d0(device_t dev) 362{ 363#if __FreeBSD_version >= 430002 364 u_int32_t iobase, membase, irq; 365 366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 367 /* Save important PCI config data. */ 368 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 369 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 370 irq = pci_read_config(dev, PCIR_INTLINE, 4); 371 372 /* Reset the power state. */ 373 device_printf(dev, "chip is in D%d power mode " 374 "-- setting to D0\n", pci_get_powerstate(dev)); 375 376 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 377 378 /* Restore PCI config data. */ 379 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 380 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 381 pci_write_config(dev, PCIR_INTLINE, irq, 4); 382 } 383#endif 384} 385#endif 386 387static void 388fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 389{ 390 u_int32_t *addr; 391 392 if (error) 393 return; 394 395 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 396 addr = arg; 397 *addr = segs->ds_addr; 398} 399 400static int 401fxp_attach(device_t dev) 402{ 403 int error = 0; 404 struct fxp_softc *sc = device_get_softc(dev); 405 struct ifnet *ifp; 406 struct fxp_rx *rxp; 407 u_int32_t val; 408 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 409 int i, rid, m1, m2, prefer_iomap, maxtxseg; 410 int s, ipcbxmit_disable; 411 412 sc->dev = dev; 413 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 414 sysctl_ctx_init(&sc->sysctl_ctx); 415 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 416 MTX_DEF); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 s = splimp(); 421 422 /* 423 * Enable bus mastering. 424 */ 425 pci_enable_busmaster(dev); 426 val = pci_read_config(dev, PCIR_COMMAND, 2); 427#ifndef BURN_BRIDGES 428 fxp_powerstate_d0(dev); 429#endif 430 /* 431 * Figure out which we should try first - memory mapping or i/o mapping? 432 * We default to memory mapping. Then we accept an override from the 433 * command line. Then we check to see which one is enabled. 434 */ 435 m1 = PCIM_CMD_MEMEN; 436 m2 = PCIM_CMD_PORTEN; 437 prefer_iomap = 0; 438 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 439 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 440 m1 = PCIM_CMD_PORTEN; 441 m2 = PCIM_CMD_MEMEN; 442 } 443 444 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 445 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 446 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 447 if (sc->mem == NULL) { 448 sc->rtp = 449 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 450 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 451 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 452 RF_ACTIVE); 453 } 454 455 if (!sc->mem) { 456 error = ENXIO; 457 goto fail; 458 } 459 if (bootverbose) { 460 device_printf(dev, "using %s space register mapping\n", 461 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 462 } 463 464 sc->sc_st = rman_get_bustag(sc->mem); 465 sc->sc_sh = rman_get_bushandle(sc->mem); 466 467 /* 468 * Allocate our interrupt. 469 */ 470 rid = 0; 471 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->irq == NULL) { 474 device_printf(dev, "could not map interrupt\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 /* 480 * Reset to a stable state. 481 */ 482 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 483 DELAY(10); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Determine whether we must use the 503 serial interface. 492 */ 493 fxp_read_eeprom(sc, &data, 6, 1); 494 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 495 (data & FXP_PHY_SERIAL_ONLY)) 496 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 497 498 /* 499 * Create the sysctl tree 500 */ 501 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 502 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 503 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 504 if (sc->sysctl_tree == NULL) { 505 error = ENXIO; 506 goto fail; 507 } 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573#if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579#endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 599 /* enable reception of long frames for VLAN */ 600 sc->flags |= FXP_FLAG_LONG_PKT_EN; 601 } 602 603 /* 604 * Enable use of extended RFDs and TCBs for 82550 605 * and later chips. Note: we need extended TXCB support 606 * too, but that's already enabled by the code above. 607 * Be careful to do this only on the right devices. 608 * 609 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 610 * truncate packets that end with an mbuf containing 1 to 3 bytes 611 * when used with this feature enabled in the previous version of the 612 * driver. This problem appears to be fixed now that the driver 613 * always sets the hardware parse bit in the IPCB structure, which 614 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 615 * Source Software Developer Manual" says is necessary in the 616 * cases where packet truncation was observed. 617 * 618 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 619 * allows this feature to be disabled at boot time. 620 * 621 * If fxp is not compiled into the kernel, this feature may also 622 * be disabled at run time: 623 * # kldunload fxp 624 * # kenv hint.fxp.0.ipcbxmit_disable=1 625 * # kldload fxp 626 */ 627 628 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 629 &ipcbxmit_disable) != 0) 630 ipcbxmit_disable = 0; 631 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 632 sc->revision == FXP_REV_82550_C)) { 633 sc->rfa_size = sizeof (struct fxp_rfa); 634 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 635 sc->flags |= FXP_FLAG_EXT_RFA; 636 } else { 637 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 638 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 639 } 640 641 /* 642 * Allocate DMA tags and DMA safe memory. 643 */ 644 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 645 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 646 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 647 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 648 if (error) { 649 device_printf(dev, "could not allocate dma tag\n"); 650 goto fail; 651 } 652 653 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 654 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 655 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 656 &sc->fxp_stag); 657 if (error) { 658 device_printf(dev, "could not allocate dma tag\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 663 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 664 if (error) 665 goto fail; 666 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 667 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 668 if (error) { 669 device_printf(dev, "could not map the stats buffer\n"); 670 goto fail; 671 } 672 673 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 674 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 675 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 676 if (error) { 677 device_printf(dev, "could not allocate dma tag\n"); 678 goto fail; 679 } 680 681 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 682 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 683 if (error) 684 goto fail; 685 686 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 687 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 688 &sc->fxp_desc.cbl_addr, 0); 689 if (error) { 690 device_printf(dev, "could not map DMA memory\n"); 691 goto fail; 692 } 693 694 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 695 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 696 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 697 &sc->mcs_tag); 698 if (error) { 699 device_printf(dev, "could not allocate dma tag\n"); 700 goto fail; 701 } 702 703 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 704 BUS_DMA_NOWAIT, &sc->mcs_map); 705 if (error) 706 goto fail; 707 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 708 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 709 if (error) { 710 device_printf(dev, "can't map the multicast setup command\n"); 711 goto fail; 712 } 713 714 /* 715 * Pre-allocate the TX DMA maps. 716 */ 717 for (i = 0; i < FXP_NTXCB; i++) { 718 error = bus_dmamap_create(sc->fxp_mtag, 0, 719 &sc->fxp_desc.tx_list[i].tx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for TX\n"); 722 goto fail; 723 } 724 } 725 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 726 if (error) { 727 device_printf(dev, "can't create spare DMA map\n"); 728 goto fail; 729 } 730 731 /* 732 * Pre-allocate our receive buffers. 733 */ 734 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 735 for (i = 0; i < FXP_NRFABUFS; i++) { 736 rxp = &sc->fxp_desc.rx_list[i]; 737 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 738 if (error) { 739 device_printf(dev, "can't create DMA map for RX\n"); 740 goto fail; 741 } 742 if (fxp_add_rfabuf(sc, rxp) != 0) { 743 error = ENOMEM; 744 goto fail; 745 } 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 753 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 754 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 755 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 756 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 757 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 758 if (bootverbose) { 759 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 760 pci_get_vendor(dev), pci_get_device(dev), 761 pci_get_subvendor(dev), pci_get_subdevice(dev), 762 pci_get_revid(dev)); 763 fxp_read_eeprom(sc, &data, 10, 1); 764 device_printf(dev, "Dynamic Standby mode is %s\n", 765 data & 0x02 ? "enabled" : "disabled"); 766 } 767 768 /* 769 * If this is only a 10Mbps device, then there is no MII, and 770 * the PHY will use a serial interface instead. 771 * 772 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 773 * doesn't have a programming interface of any sort. The 774 * media is sensed automatically based on how the link partner 775 * is configured. This is, in essence, manual configuration. 776 */ 777 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 778 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 780 } else { 781 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 782 fxp_ifmedia_sts)) { 783 device_printf(dev, "MII without any PHY!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 } 788 789 ifp = &sc->arpcom.ac_if; 790 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 791 ifp->if_output = ether_output; 792 ifp->if_baudrate = 100000000; 793 ifp->if_init = fxp_init; 794 ifp->if_softc = sc; 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_ioctl = fxp_ioctl; 797 ifp->if_start = fxp_start; 798 ifp->if_watchdog = fxp_watchdog; 799 800 ifp->if_capabilities = ifp->if_capenable = 0; 801 802 /* Enable checksum offload for 82550 or better chips */ 803 if (sc->flags & FXP_FLAG_EXT_RFA) { 804 ifp->if_hwassist = FXP_CSUM_FEATURES; 805 ifp->if_capabilities |= IFCAP_HWCSUM; 806 ifp->if_capenable |= IFCAP_HWCSUM; 807 } 808 809#ifdef DEVICE_POLLING 810 /* Inform the world we support polling. */ 811 ifp->if_capabilities |= IFCAP_POLLING; 812 ifp->if_capenable |= IFCAP_POLLING; 813#endif 814 815 /* 816 * Attach the interface. 817 */ 818 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 819 820 /* 821 * Tell the upper layer(s) we support long frames. 822 * Must appear after the call to ether_ifattach() because 823 * ether_ifattach() sets ifi_hdrlen to the default value. 824 */ 825 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 826 ifp->if_capabilities |= IFCAP_VLAN_MTU; 827 ifp->if_capenable |= IFCAP_VLAN_MTU; 828 829 /* 830 * Let the system queue as many packets as we have available 831 * TX descriptors. 832 */ 833 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 834 835 /* 836 * Hook our interrupt after all initialization is complete. 837 * XXX This driver has been tested with the INTR_MPSAFFE flag set 838 * however, ifp and its functions are not fully locked so MPSAFE 839 * should not be used unless you can handle potential data loss. 840 */ 841 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 842 fxp_intr, sc, &sc->ih); 843 if (error) { 844 device_printf(dev, "could not setup irq\n"); 845 ether_ifdetach(&sc->arpcom.ac_if); 846 goto fail; 847 } 848 849fail: 850 splx(s); 851 if (error) 852 fxp_release(sc); 853 return (error); 854} 855 856/* 857 * Release all resources. The softc lock should not be held and the 858 * interrupt should already be torn down. 859 */ 860static void 861fxp_release(struct fxp_softc *sc) 862{ 863 struct fxp_rx *rxp; 864 struct fxp_tx *txp; 865 int i; 866 867 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 868 if (sc->ih) 869 panic("fxp_release() called with intr handle still active"); 870 if (sc->miibus) 871 device_delete_child(sc->dev, sc->miibus); 872 bus_generic_detach(sc->dev); 873 ifmedia_removeall(&sc->sc_media); 874 if (sc->fxp_desc.cbl_list) { 875 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 876 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 877 sc->cbl_map); 878 } 879 if (sc->fxp_stats) { 880 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 881 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 882 } 883 if (sc->mcsp) { 884 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 885 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 886 } 887 if (sc->irq) 888 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 889 if (sc->mem) 890 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 891 if (sc->fxp_mtag) { 892 for (i = 0; i < FXP_NRFABUFS; i++) { 893 rxp = &sc->fxp_desc.rx_list[i]; 894 if (rxp->rx_mbuf != NULL) { 895 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 896 BUS_DMASYNC_POSTREAD); 897 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 898 m_freem(rxp->rx_mbuf); 899 } 900 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 901 } 902 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 903 bus_dma_tag_destroy(sc->fxp_mtag); 904 } 905 if (sc->fxp_stag) { 906 for (i = 0; i < FXP_NTXCB; i++) { 907 txp = &sc->fxp_desc.tx_list[i]; 908 if (txp->tx_mbuf != NULL) { 909 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 910 BUS_DMASYNC_POSTWRITE); 911 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 912 m_freem(txp->tx_mbuf); 913 } 914 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 915 } 916 bus_dma_tag_destroy(sc->fxp_stag); 917 } 918 if (sc->cbl_tag) 919 bus_dma_tag_destroy(sc->cbl_tag); 920 if (sc->mcs_tag) 921 bus_dma_tag_destroy(sc->mcs_tag); 922 923 sysctl_ctx_free(&sc->sysctl_ctx); 924 925 mtx_destroy(&sc->sc_mtx); 926} 927 928/* 929 * Detach interface. 930 */ 931static int 932fxp_detach(device_t dev) 933{ 934 struct fxp_softc *sc = device_get_softc(dev); 935 int s; 936 937 FXP_LOCK(sc); 938 s = splimp(); 939 940 sc->suspended = 1; /* Do same thing as we do for suspend */ 941 /* 942 * Close down routes etc. 943 */ 944 ether_ifdetach(&sc->arpcom.ac_if); 945 946 /* 947 * Stop DMA and drop transmit queue, but disable interrupts first. 948 */ 949 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 950 fxp_stop(sc); 951 FXP_UNLOCK(sc); 952 953 /* 954 * Unhook interrupt before dropping lock. This is to prevent 955 * races with fxp_intr(). 956 */ 957 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 958 sc->ih = NULL; 959 960 splx(s); 961 962 /* Release our allocated resources. */ 963 fxp_release(sc); 964 return (0); 965} 966 967/* 968 * Device shutdown routine. Called at system shutdown after sync. The 969 * main purpose of this routine is to shut off receiver DMA so that 970 * kernel memory doesn't get clobbered during warmboot. 971 */ 972static int 973fxp_shutdown(device_t dev) 974{ 975 /* 976 * Make sure that DMA is disabled prior to reboot. Not doing 977 * do could allow DMA to corrupt kernel memory during the 978 * reboot before the driver initializes. 979 */ 980 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 981 return (0); 982} 983 984/* 985 * Device suspend routine. Stop the interface and save some PCI 986 * settings in case the BIOS doesn't restore them properly on 987 * resume. 988 */ 989static int 990fxp_suspend(device_t dev) 991{ 992 struct fxp_softc *sc = device_get_softc(dev); 993 int i, s; 994 995 FXP_LOCK(sc); 996 s = splimp(); 997 998 fxp_stop(sc); 999 1000 for (i = 0; i < 5; i++) 1001 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1002 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1003 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1004 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1005 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1006 1007 sc->suspended = 1; 1008 1009 FXP_UNLOCK(sc); 1010 splx(s); 1011 return (0); 1012} 1013 1014/* 1015 * Device resume routine. Restore some PCI settings in case the BIOS 1016 * doesn't, re-enable busmastering, and restart the interface if 1017 * appropriate. 1018 */ 1019static int 1020fxp_resume(device_t dev) 1021{ 1022 struct fxp_softc *sc = device_get_softc(dev); 1023 struct ifnet *ifp = &sc->sc_if; 1024 u_int16_t pci_command; 1025 int i, s; 1026 1027 FXP_LOCK(sc); 1028 s = splimp(); 1029#ifndef BURN_BRIDGES 1030 fxp_powerstate_d0(dev); 1031#endif 1032 /* better way to do this? */ 1033 for (i = 0; i < 5; i++) 1034 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1035 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1036 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1037 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1038 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1039 1040 /* reenable busmastering */ 1041 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1042 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1043 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1044 1045 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1046 DELAY(10); 1047 1048 /* reinitialize interface if necessary */ 1049 if (ifp->if_flags & IFF_UP) 1050 fxp_init_body(sc); 1051 1052 sc->suspended = 0; 1053 1054 FXP_UNLOCK(sc); 1055 splx(s); 1056 return (0); 1057} 1058 1059static void 1060fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1061{ 1062 u_int16_t reg; 1063 int x; 1064 1065 /* 1066 * Shift in data. 1067 */ 1068 for (x = 1 << (length - 1); x; x >>= 1) { 1069 if (data & x) 1070 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1071 else 1072 reg = FXP_EEPROM_EECS; 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1074 DELAY(1); 1075 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1076 DELAY(1); 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1078 DELAY(1); 1079 } 1080} 1081 1082/* 1083 * Read from the serial EEPROM. Basically, you manually shift in 1084 * the read opcode (one bit at a time) and then shift in the address, 1085 * and then you shift out the data (all of this one bit at a time). 1086 * The word size is 16 bits, so you have to provide the address for 1087 * every 16 bits of data. 1088 */ 1089static u_int16_t 1090fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1091{ 1092 u_int16_t reg, data; 1093 int x; 1094 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1096 /* 1097 * Shift in read opcode. 1098 */ 1099 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1100 /* 1101 * Shift in address. 1102 */ 1103 data = 0; 1104 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1105 if (offset & x) 1106 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1107 else 1108 reg = FXP_EEPROM_EECS; 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1110 DELAY(1); 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1112 DELAY(1); 1113 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1114 DELAY(1); 1115 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1116 data++; 1117 if (autosize && reg == 0) { 1118 sc->eeprom_size = data; 1119 break; 1120 } 1121 } 1122 /* 1123 * Shift out data. 1124 */ 1125 data = 0; 1126 reg = FXP_EEPROM_EECS; 1127 for (x = 1 << 15; x; x >>= 1) { 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1129 DELAY(1); 1130 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1131 data |= x; 1132 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1133 DELAY(1); 1134 } 1135 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1136 DELAY(1); 1137 1138 return (data); 1139} 1140 1141static void 1142fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1143{ 1144 int i; 1145 1146 /* 1147 * Erase/write enable. 1148 */ 1149 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1150 fxp_eeprom_shiftin(sc, 0x4, 3); 1151 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1153 DELAY(1); 1154 /* 1155 * Shift in write opcode, address, data. 1156 */ 1157 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1158 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1159 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1160 fxp_eeprom_shiftin(sc, data, 16); 1161 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1162 DELAY(1); 1163 /* 1164 * Wait for EEPROM to finish up. 1165 */ 1166 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1167 DELAY(1); 1168 for (i = 0; i < 1000; i++) { 1169 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1170 break; 1171 DELAY(50); 1172 } 1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1174 DELAY(1); 1175 /* 1176 * Erase/write disable. 1177 */ 1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1179 fxp_eeprom_shiftin(sc, 0x4, 3); 1180 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1182 DELAY(1); 1183} 1184 1185/* 1186 * From NetBSD: 1187 * 1188 * Figure out EEPROM size. 1189 * 1190 * 559's can have either 64-word or 256-word EEPROMs, the 558 1191 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1192 * talks about the existance of 16 to 256 word EEPROMs. 1193 * 1194 * The only known sizes are 64 and 256, where the 256 version is used 1195 * by CardBus cards to store CIS information. 1196 * 1197 * The address is shifted in msb-to-lsb, and after the last 1198 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1199 * after which follows the actual data. We try to detect this zero, by 1200 * probing the data-out bit in the EEPROM control register just after 1201 * having shifted in a bit. If the bit is zero, we assume we've 1202 * shifted enough address bits. The data-out should be tri-state, 1203 * before this, which should translate to a logical one. 1204 */ 1205static void 1206fxp_autosize_eeprom(struct fxp_softc *sc) 1207{ 1208 1209 /* guess maximum size of 256 words */ 1210 sc->eeprom_size = 8; 1211 1212 /* autosize */ 1213 (void) fxp_eeprom_getword(sc, 0, 1); 1214} 1215 1216static void 1217fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1218{ 1219 int i; 1220 1221 for (i = 0; i < words; i++) 1222 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1223} 1224 1225static void 1226fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1227{ 1228 int i; 1229 1230 for (i = 0; i < words; i++) 1231 fxp_eeprom_putword(sc, offset + i, data[i]); 1232} 1233 1234static void 1235fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1236 bus_size_t mapsize, int error) 1237{ 1238 struct fxp_softc *sc; 1239 struct fxp_cb_tx *txp; 1240 int i; 1241 1242 if (error) 1243 return; 1244 1245 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1246 1247 sc = arg; 1248 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1249 for (i = 0; i < nseg; i++) { 1250 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1251 /* 1252 * If this is an 82550/82551, then we're using extended 1253 * TxCBs _and_ we're using checksum offload. This means 1254 * that the TxCB is really an IPCB. One major difference 1255 * between the two is that with plain extended TxCBs, 1256 * the bottom half of the TxCB contains two entries from 1257 * the TBD array, whereas IPCBs contain just one entry: 1258 * one entry (8 bytes) has been sacrificed for the TCP/IP 1259 * checksum offload control bits. So to make things work 1260 * right, we have to start filling in the TBD array 1261 * starting from a different place depending on whether 1262 * the chip is an 82550/82551 or not. 1263 */ 1264 if (sc->flags & FXP_FLAG_EXT_RFA) { 1265 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1266 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1267 } else { 1268 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1269 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1270 } 1271 } 1272 txp->tbd_number = nseg; 1273} 1274 1275/* 1276 * Grab the softc lock and call the real fxp_start_body() routine 1277 */ 1278static void 1279fxp_start(struct ifnet *ifp) 1280{ 1281 struct fxp_softc *sc = ifp->if_softc; 1282 1283 FXP_LOCK(sc); 1284 fxp_start_body(ifp); 1285 FXP_UNLOCK(sc); 1286} 1287 1288/* 1289 * Start packet transmission on the interface. 1290 * This routine must be called with the softc lock held, and is an 1291 * internal entry point only. 1292 */ 1293static void 1294fxp_start_body(struct ifnet *ifp) 1295{ 1296 struct fxp_softc *sc = ifp->if_softc; 1297 struct fxp_tx *txp; 1298 struct mbuf *mb_head; 1299 int error; 1300 1301 mtx_assert(&sc->sc_mtx, MA_OWNED); 1302 /* 1303 * See if we need to suspend xmit until the multicast filter 1304 * has been reprogrammed (which can only be done at the head 1305 * of the command chain). 1306 */ 1307 if (sc->need_mcsetup) { 1308 return; 1309 } 1310 1311 txp = NULL; 1312 1313 /* 1314 * We're finished if there is nothing more to add to the list or if 1315 * we're all filled up with buffers to transmit. 1316 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1317 * a NOP command when needed. 1318 */ 1319 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1320 1321 /* 1322 * Grab a packet to transmit. 1323 */ 1324 IF_DEQUEUE(&ifp->if_snd, mb_head); 1325 1326 /* 1327 * Get pointer to next available tx desc. 1328 */ 1329 txp = sc->fxp_desc.tx_last->tx_next; 1330 1331 /* 1332 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1333 * Ethernet Controller Family Open Source Software 1334 * Developer Manual says: 1335 * Using software parsing is only allowed with legal 1336 * TCP/IP or UDP/IP packets. 1337 * ... 1338 * For all other datagrams, hardware parsing must 1339 * be used. 1340 * Software parsing appears to truncate ICMP and 1341 * fragmented UDP packets that contain one to three 1342 * bytes in the second (and final) mbuf of the packet. 1343 */ 1344 if (sc->flags & FXP_FLAG_EXT_RFA) 1345 txp->tx_cb->ipcb_ip_activation_high = 1346 FXP_IPCB_HARDWAREPARSING_ENABLE; 1347 1348 /* 1349 * Deal with TCP/IP checksum offload. Note that 1350 * in order for TCP checksum offload to work, 1351 * the pseudo header checksum must have already 1352 * been computed and stored in the checksum field 1353 * in the TCP header. The stack should have 1354 * already done this for us. 1355 */ 1356 1357 if (mb_head->m_pkthdr.csum_flags) { 1358 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1359 txp->tx_cb->ipcb_ip_schedule = 1360 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1361 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1362 txp->tx_cb->ipcb_ip_schedule |= 1363 FXP_IPCB_TCP_PACKET; 1364 } 1365#ifdef FXP_IP_CSUM_WAR 1366 /* 1367 * XXX The 82550 chip appears to have trouble 1368 * dealing with IP header checksums in very small 1369 * datagrams, namely fragments from 1 to 3 bytes 1370 * in size. For example, say you want to transmit 1371 * a UDP packet of 1473 bytes. The packet will be 1372 * fragmented over two IP datagrams, the latter 1373 * containing only one byte of data. The 82550 will 1374 * botch the header checksum on the 1-byte fragment. 1375 * As long as the datagram contains 4 or more bytes 1376 * of data, you're ok. 1377 * 1378 * The following code attempts to work around this 1379 * problem: if the datagram is less than 38 bytes 1380 * in size (14 bytes ether header, 20 bytes IP header, 1381 * plus 4 bytes of data), we punt and compute the IP 1382 * header checksum by hand. This workaround doesn't 1383 * work very well, however, since it can be fooled 1384 * by things like VLAN tags and IP options that make 1385 * the header sizes/offsets vary. 1386 */ 1387 1388 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1389 if (mb_head->m_pkthdr.len < 38) { 1390 struct ip *ip; 1391 mb_head->m_data += ETHER_HDR_LEN; 1392 ip = mtod(mb_head, struct ip *); 1393 ip->ip_sum = in_cksum(mb_head, 1394 ip->ip_hl << 2); 1395 mb_head->m_data -= ETHER_HDR_LEN; 1396 } else { 1397 txp->tx_cb->ipcb_ip_activation_high = 1398 FXP_IPCB_HARDWAREPARSING_ENABLE; 1399 txp->tx_cb->ipcb_ip_schedule |= 1400 FXP_IPCB_IP_CHECKSUM_ENABLE; 1401 } 1402 } 1403#endif 1404 } 1405 1406 /* 1407 * Go through each of the mbufs in the chain and initialize 1408 * the transmit buffer descriptors with the physical address 1409 * and size of the mbuf. 1410 */ 1411 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1412 mb_head, fxp_dma_map_txbuf, sc, 0); 1413 1414 if (error && error != EFBIG) { 1415 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1416 error); 1417 m_freem(mb_head); 1418 break; 1419 } 1420 1421 if (error) { 1422 struct mbuf *mn; 1423 1424 /* 1425 * We ran out of segments. We have to recopy this 1426 * mbuf chain first. Bail out if we can't get the 1427 * new buffers. 1428 */ 1429 mn = m_defrag(mb_head, M_DONTWAIT); 1430 if (mn == NULL) { 1431 m_freem(mb_head); 1432 break; 1433 } else { 1434 mb_head = mn; 1435 } 1436 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1437 mb_head, fxp_dma_map_txbuf, sc, 0); 1438 if (error) { 1439 device_printf(sc->dev, 1440 "can't map mbuf (error %d)\n", error); 1441 m_freem(mb_head); 1442 break; 1443 } 1444 } 1445 1446 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1447 BUS_DMASYNC_PREWRITE); 1448 1449 txp->tx_mbuf = mb_head; 1450 txp->tx_cb->cb_status = 0; 1451 txp->tx_cb->byte_count = 0; 1452 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1453 txp->tx_cb->cb_command = 1454 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1455 FXP_CB_COMMAND_S); 1456 } else { 1457 txp->tx_cb->cb_command = 1458 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1459 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1460 /* 1461 * Set a 5 second timer just in case we don't hear 1462 * from the card again. 1463 */ 1464 ifp->if_timer = 5; 1465 } 1466 txp->tx_cb->tx_threshold = tx_threshold; 1467 1468 /* 1469 * Advance the end of list forward. 1470 */ 1471 1472#ifdef __alpha__ 1473 /* 1474 * On platforms which can't access memory in 16-bit 1475 * granularities, we must prevent the card from DMA'ing 1476 * up the status while we update the command field. 1477 * This could cause us to overwrite the completion status. 1478 * XXX This is probably bogus and we're _not_ looking 1479 * for atomicity here. 1480 */ 1481 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1482 htole16(FXP_CB_COMMAND_S)); 1483#else 1484 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1485 htole16(~FXP_CB_COMMAND_S); 1486#endif /*__alpha__*/ 1487 sc->fxp_desc.tx_last = txp; 1488 1489 /* 1490 * Advance the beginning of the list forward if there are 1491 * no other packets queued (when nothing is queued, tx_first 1492 * sits on the last TxCB that was sent out). 1493 */ 1494 if (sc->tx_queued == 0) 1495 sc->fxp_desc.tx_first = txp; 1496 1497 sc->tx_queued++; 1498 1499 /* 1500 * Pass packet to bpf if there is a listener. 1501 */ 1502 BPF_MTAP(ifp, mb_head); 1503 } 1504 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1505 1506 /* 1507 * We're finished. If we added to the list, issue a RESUME to get DMA 1508 * going again if suspended. 1509 */ 1510 if (txp != NULL) { 1511 fxp_scb_wait(sc); 1512 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1513 } 1514} 1515 1516#ifdef DEVICE_POLLING 1517static poll_handler_t fxp_poll; 1518 1519static void 1520fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1521{ 1522 struct fxp_softc *sc = ifp->if_softc; 1523 u_int8_t statack; 1524 1525 FXP_LOCK(sc); 1526 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1527 ether_poll_deregister(ifp); 1528 cmd = POLL_DEREGISTER; 1529 } 1530 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1531 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1532 FXP_UNLOCK(sc); 1533 return; 1534 } 1535 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1536 FXP_SCB_STATACK_FR; 1537 if (cmd == POLL_AND_CHECK_STATUS) { 1538 u_int8_t tmp; 1539 1540 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1541 if (tmp == 0xff || tmp == 0) { 1542 FXP_UNLOCK(sc); 1543 return; /* nothing to do */ 1544 } 1545 tmp &= ~statack; 1546 /* ack what we can */ 1547 if (tmp != 0) 1548 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1549 statack |= tmp; 1550 } 1551 fxp_intr_body(sc, ifp, statack, count); 1552 FXP_UNLOCK(sc); 1553} 1554#endif /* DEVICE_POLLING */ 1555 1556/* 1557 * Process interface interrupts. 1558 */ 1559static void 1560fxp_intr(void *xsc) 1561{ 1562 struct fxp_softc *sc = xsc; 1563 struct ifnet *ifp = &sc->sc_if; 1564 u_int8_t statack; 1565 1566 FXP_LOCK(sc); 1567 if (sc->suspended) { 1568 FXP_UNLOCK(sc); 1569 return; 1570 } 1571 1572#ifdef DEVICE_POLLING 1573 if (ifp->if_flags & IFF_POLLING) { 1574 FXP_UNLOCK(sc); 1575 return; 1576 } 1577 if ((ifp->if_capenable & IFCAP_POLLING) && 1578 ether_poll_register(fxp_poll, ifp)) { 1579 /* disable interrupts */ 1580 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1581 FXP_UNLOCK(sc); 1582 fxp_poll(ifp, 0, 1); 1583 return; 1584 } 1585#endif 1586 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1587 /* 1588 * It should not be possible to have all bits set; the 1589 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1590 * all bits are set, this may indicate that the card has 1591 * been physically ejected, so ignore it. 1592 */ 1593 if (statack == 0xff) { 1594 FXP_UNLOCK(sc); 1595 return; 1596 } 1597 1598 /* 1599 * First ACK all the interrupts in this pass. 1600 */ 1601 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1602 fxp_intr_body(sc, ifp, statack, -1); 1603 } 1604 FXP_UNLOCK(sc); 1605} 1606 1607static void 1608fxp_txeof(struct fxp_softc *sc) 1609{ 1610 struct fxp_tx *txp; 1611 1612 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1613 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1614 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1615 txp = txp->tx_next) { 1616 if (txp->tx_mbuf != NULL) { 1617 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1618 BUS_DMASYNC_POSTWRITE); 1619 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1620 m_freem(txp->tx_mbuf); 1621 txp->tx_mbuf = NULL; 1622 /* clear this to reset csum offload bits */ 1623 txp->tx_cb->tbd[0].tb_addr = 0; 1624 } 1625 sc->tx_queued--; 1626 } 1627 sc->fxp_desc.tx_first = txp; 1628 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1629} 1630 1631static void 1632fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1633 int count) 1634{ 1635 struct mbuf *m; 1636 struct fxp_rx *rxp; 1637 struct fxp_rfa *rfa; 1638 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1639 1640 mtx_assert(&sc->sc_mtx, MA_OWNED); 1641 if (rnr) 1642 fxp_rnr++; 1643#ifdef DEVICE_POLLING 1644 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1645 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1646 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1647 rnr = 1; 1648 } 1649#endif 1650 1651 /* 1652 * Free any finished transmit mbuf chains. 1653 * 1654 * Handle the CNA event likt a CXTNO event. It used to 1655 * be that this event (control unit not ready) was not 1656 * encountered, but it is now with the SMPng modifications. 1657 * The exact sequence of events that occur when the interface 1658 * is brought up are different now, and if this event 1659 * goes unhandled, the configuration/rxfilter setup sequence 1660 * can stall for several seconds. The result is that no 1661 * packets go out onto the wire for about 5 to 10 seconds 1662 * after the interface is ifconfig'ed for the first time. 1663 */ 1664 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1665 fxp_txeof(sc); 1666 1667 ifp->if_timer = 0; 1668 if (sc->tx_queued == 0) { 1669 if (sc->need_mcsetup) 1670 fxp_mc_setup(sc); 1671 } 1672 /* 1673 * Try to start more packets transmitting. 1674 */ 1675 if (ifp->if_snd.ifq_head != NULL) 1676 fxp_start_body(ifp); 1677 } 1678 1679 /* 1680 * Just return if nothing happened on the receive side. 1681 */ 1682 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1683 return; 1684 1685 /* 1686 * Process receiver interrupts. If a no-resource (RNR) 1687 * condition exists, get whatever packets we can and 1688 * re-start the receiver. 1689 * 1690 * When using polling, we do not process the list to completion, 1691 * so when we get an RNR interrupt we must defer the restart 1692 * until we hit the last buffer with the C bit set. 1693 * If we run out of cycles and rfa_headm has the C bit set, 1694 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1695 * that the info will be used in the subsequent polling cycle. 1696 */ 1697 for (;;) { 1698 rxp = sc->fxp_desc.rx_head; 1699 m = rxp->rx_mbuf; 1700 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1701 RFA_ALIGNMENT_FUDGE); 1702 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1703 BUS_DMASYNC_POSTREAD); 1704 1705#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1706 if (count >= 0 && count-- == 0) { 1707 if (rnr) { 1708 /* Defer RNR processing until the next time. */ 1709 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1710 rnr = 0; 1711 } 1712 break; 1713 } 1714#endif /* DEVICE_POLLING */ 1715 1716 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1717 break; 1718 1719 /* 1720 * Advance head forward. 1721 */ 1722 sc->fxp_desc.rx_head = rxp->rx_next; 1723 1724 /* 1725 * Add a new buffer to the receive chain. 1726 * If this fails, the old buffer is recycled 1727 * instead. 1728 */ 1729 if (fxp_add_rfabuf(sc, rxp) == 0) { 1730 int total_len; 1731 1732 /* 1733 * Fetch packet length (the top 2 bits of 1734 * actual_size are flags set by the controller 1735 * upon completion), and drop the packet in case 1736 * of bogus length or CRC errors. 1737 */ 1738 total_len = le16toh(rfa->actual_size) & 0x3fff; 1739 if (total_len < sizeof(struct ether_header) || 1740 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1741 sc->rfa_size || 1742 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1743 m_freem(m); 1744 continue; 1745 } 1746 1747 /* Do IP checksum checking. */ 1748 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1749 if (rfa->rfax_csum_sts & 1750 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1751 m->m_pkthdr.csum_flags |= 1752 CSUM_IP_CHECKED; 1753 if (rfa->rfax_csum_sts & 1754 FXP_RFDX_CS_IP_CSUM_VALID) 1755 m->m_pkthdr.csum_flags |= 1756 CSUM_IP_VALID; 1757 if ((rfa->rfax_csum_sts & 1758 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1759 (rfa->rfax_csum_sts & 1760 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1761 m->m_pkthdr.csum_flags |= 1762 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1763 m->m_pkthdr.csum_data = 0xffff; 1764 } 1765 } 1766 1767 m->m_pkthdr.len = m->m_len = total_len; 1768 m->m_pkthdr.rcvif = ifp; 1769 1770 /* 1771 * Drop locks before calling if_input() since it 1772 * may re-enter fxp_start() in the netisr case. 1773 * This would result in a lock reversal. Better 1774 * performance might be obtained by chaining all 1775 * packets received, dropping the lock, and then 1776 * calling if_input() on each one. 1777 */ 1778 FXP_UNLOCK(sc); 1779 (*ifp->if_input)(ifp, m); 1780 FXP_LOCK(sc); 1781 } 1782 } 1783 if (rnr) { 1784 fxp_scb_wait(sc); 1785 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1786 sc->fxp_desc.rx_head->rx_addr); 1787 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1788 } 1789} 1790 1791/* 1792 * Update packet in/out/collision statistics. The i82557 doesn't 1793 * allow you to access these counters without doing a fairly 1794 * expensive DMA to get _all_ of the statistics it maintains, so 1795 * we do this operation here only once per second. The statistics 1796 * counters in the kernel are updated from the previous dump-stats 1797 * DMA and then a new dump-stats DMA is started. The on-chip 1798 * counters are zeroed when the DMA completes. If we can't start 1799 * the DMA immediately, we don't wait - we just prepare to read 1800 * them again next time. 1801 */ 1802static void 1803fxp_tick(void *xsc) 1804{ 1805 struct fxp_softc *sc = xsc; 1806 struct ifnet *ifp = &sc->sc_if; 1807 struct fxp_stats *sp = sc->fxp_stats; 1808 int s; 1809 1810 FXP_LOCK(sc); 1811 s = splimp(); 1812 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1813 ifp->if_opackets += le32toh(sp->tx_good); 1814 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1815 if (sp->rx_good) { 1816 ifp->if_ipackets += le32toh(sp->rx_good); 1817 sc->rx_idle_secs = 0; 1818 } else { 1819 /* 1820 * Receiver's been idle for another second. 1821 */ 1822 sc->rx_idle_secs++; 1823 } 1824 ifp->if_ierrors += 1825 le32toh(sp->rx_crc_errors) + 1826 le32toh(sp->rx_alignment_errors) + 1827 le32toh(sp->rx_rnr_errors) + 1828 le32toh(sp->rx_overrun_errors); 1829 /* 1830 * If any transmit underruns occured, bump up the transmit 1831 * threshold by another 512 bytes (64 * 8). 1832 */ 1833 if (sp->tx_underruns) { 1834 ifp->if_oerrors += le32toh(sp->tx_underruns); 1835 if (tx_threshold < 192) 1836 tx_threshold += 64; 1837 } 1838 1839 /* 1840 * Release any xmit buffers that have completed DMA. This isn't 1841 * strictly necessary to do here, but it's advantagous for mbufs 1842 * with external storage to be released in a timely manner rather 1843 * than being defered for a potentially long time. This limits 1844 * the delay to a maximum of one second. 1845 */ 1846 fxp_txeof(sc); 1847 1848 /* 1849 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1850 * then assume the receiver has locked up and attempt to clear 1851 * the condition by reprogramming the multicast filter. This is 1852 * a work-around for a bug in the 82557 where the receiver locks 1853 * up if it gets certain types of garbage in the syncronization 1854 * bits prior to the packet header. This bug is supposed to only 1855 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1856 * mode as well (perhaps due to a 10/100 speed transition). 1857 */ 1858 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1859 sc->rx_idle_secs = 0; 1860 fxp_mc_setup(sc); 1861 } 1862 /* 1863 * If there is no pending command, start another stats 1864 * dump. Otherwise punt for now. 1865 */ 1866 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1867 /* 1868 * Start another stats dump. 1869 */ 1870 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1871 BUS_DMASYNC_PREREAD); 1872 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1873 } else { 1874 /* 1875 * A previous command is still waiting to be accepted. 1876 * Just zero our copy of the stats and wait for the 1877 * next timer event to update them. 1878 */ 1879 sp->tx_good = 0; 1880 sp->tx_underruns = 0; 1881 sp->tx_total_collisions = 0; 1882 1883 sp->rx_good = 0; 1884 sp->rx_crc_errors = 0; 1885 sp->rx_alignment_errors = 0; 1886 sp->rx_rnr_errors = 0; 1887 sp->rx_overrun_errors = 0; 1888 } 1889 if (sc->miibus != NULL) 1890 mii_tick(device_get_softc(sc->miibus)); 1891 1892 /* 1893 * Schedule another timeout one second from now. 1894 */ 1895 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1896 FXP_UNLOCK(sc); 1897 splx(s); 1898} 1899 1900/* 1901 * Stop the interface. Cancels the statistics updater and resets 1902 * the interface. 1903 */ 1904static void 1905fxp_stop(struct fxp_softc *sc) 1906{ 1907 struct ifnet *ifp = &sc->sc_if; 1908 struct fxp_tx *txp; 1909 int i; 1910 1911 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1912 ifp->if_timer = 0; 1913 1914#ifdef DEVICE_POLLING 1915 ether_poll_deregister(ifp); 1916#endif 1917 /* 1918 * Cancel stats updater. 1919 */ 1920 callout_stop(&sc->stat_ch); 1921 1922 /* 1923 * Issue software reset, which also unloads the microcode. 1924 */ 1925 sc->flags &= ~FXP_FLAG_UCODE; 1926 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1927 DELAY(50); 1928 1929 /* 1930 * Release any xmit buffers. 1931 */ 1932 txp = sc->fxp_desc.tx_list; 1933 if (txp != NULL) { 1934 for (i = 0; i < FXP_NTXCB; i++) { 1935 if (txp[i].tx_mbuf != NULL) { 1936 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1937 BUS_DMASYNC_POSTWRITE); 1938 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1939 m_freem(txp[i].tx_mbuf); 1940 txp[i].tx_mbuf = NULL; 1941 /* clear this to reset csum offload bits */ 1942 txp[i].tx_cb->tbd[0].tb_addr = 0; 1943 } 1944 } 1945 } 1946 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1947 sc->tx_queued = 0; 1948} 1949 1950/* 1951 * Watchdog/transmission transmit timeout handler. Called when a 1952 * transmission is started on the interface, but no interrupt is 1953 * received before the timeout. This usually indicates that the 1954 * card has wedged for some reason. 1955 */ 1956static void 1957fxp_watchdog(struct ifnet *ifp) 1958{ 1959 struct fxp_softc *sc = ifp->if_softc; 1960 1961 FXP_LOCK(sc); 1962 device_printf(sc->dev, "device timeout\n"); 1963 ifp->if_oerrors++; 1964 1965 fxp_init_body(sc); 1966 FXP_UNLOCK(sc); 1967} 1968 1969/* 1970 * Acquire locks and then call the real initialization function. This 1971 * is necessary because ether_ioctl() calls if_init() and this would 1972 * result in mutex recursion if the mutex was held. 1973 */ 1974static void 1975fxp_init(void *xsc) 1976{ 1977 struct fxp_softc *sc = xsc; 1978 1979 FXP_LOCK(sc); 1980 fxp_init_body(sc); 1981 FXP_UNLOCK(sc); 1982} 1983 1984/* 1985 * Perform device initialization. This routine must be called with the 1986 * softc lock held. 1987 */ 1988static void 1989fxp_init_body(struct fxp_softc *sc) 1990{ 1991 struct ifnet *ifp = &sc->sc_if; 1992 struct fxp_cb_config *cbp; 1993 struct fxp_cb_ias *cb_ias; 1994 struct fxp_cb_tx *tcbp; 1995 struct fxp_tx *txp; 1996 struct fxp_cb_mcs *mcsp; 1997 int i, prm, s; 1998 1999 mtx_assert(&sc->sc_mtx, MA_OWNED); 2000 s = splimp(); 2001 /* 2002 * Cancel any pending I/O 2003 */ 2004 fxp_stop(sc); 2005 2006 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2007 2008 /* 2009 * Initialize base of CBL and RFA memory. Loading with zero 2010 * sets it up for regular linear addressing. 2011 */ 2012 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2013 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2014 2015 fxp_scb_wait(sc); 2016 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2017 2018 /* 2019 * Initialize base of dump-stats buffer. 2020 */ 2021 fxp_scb_wait(sc); 2022 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2023 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2024 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2025 2026 /* 2027 * Attempt to load microcode if requested. 2028 */ 2029 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2030 fxp_load_ucode(sc); 2031 2032 /* 2033 * Initialize the multicast address list. 2034 */ 2035 if (fxp_mc_addrs(sc)) { 2036 mcsp = sc->mcsp; 2037 mcsp->cb_status = 0; 2038 mcsp->cb_command = 2039 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2040 mcsp->link_addr = 0xffffffff; 2041 /* 2042 * Start the multicast setup command. 2043 */ 2044 fxp_scb_wait(sc); 2045 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2046 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2047 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2048 /* ...and wait for it to complete. */ 2049 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2050 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2051 BUS_DMASYNC_POSTWRITE); 2052 } 2053 2054 /* 2055 * We temporarily use memory that contains the TxCB list to 2056 * construct the config CB. The TxCB list memory is rebuilt 2057 * later. 2058 */ 2059 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2060 2061 /* 2062 * This bcopy is kind of disgusting, but there are a bunch of must be 2063 * zero and must be one bits in this structure and this is the easiest 2064 * way to initialize them all to proper values. 2065 */ 2066 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2067 2068 cbp->cb_status = 0; 2069 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2070 FXP_CB_COMMAND_EL); 2071 cbp->link_addr = 0xffffffff; /* (no) next command */ 2072 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2073 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2074 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2075 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2076 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2077 cbp->type_enable = 0; /* actually reserved */ 2078 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2079 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2080 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2081 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2082 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2083 cbp->late_scb = 0; /* (don't) defer SCB update */ 2084 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2085 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2086 cbp->ci_int = 1; /* interrupt on CU idle */ 2087 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2088 cbp->ext_stats_dis = 1; /* disable extended counters */ 2089 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2090 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2091 cbp->disc_short_rx = !prm; /* discard short packets */ 2092 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2093 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2094 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2095 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2096 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2097 cbp->csma_dis = 0; /* (don't) disable link */ 2098 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2099 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2100 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2101 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2102 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2103 cbp->nsai = 1; /* (don't) disable source addr insert */ 2104 cbp->preamble_length = 2; /* (7 byte) preamble */ 2105 cbp->loopback = 0; /* (don't) loopback */ 2106 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2107 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2108 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2109 cbp->promiscuous = prm; /* promiscuous mode */ 2110 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2111 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2112 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2113 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2114 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2115 2116 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2117 cbp->padding = 1; /* (do) pad short tx packets */ 2118 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2119 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2120 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2121 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2122 /* must set wake_en in PMCSR also */ 2123 cbp->force_fdx = 0; /* (don't) force full duplex */ 2124 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2125 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2126 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2127 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2128 2129 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2130 /* 2131 * The 82557 has no hardware flow control, the values 2132 * below are the defaults for the chip. 2133 */ 2134 cbp->fc_delay_lsb = 0; 2135 cbp->fc_delay_msb = 0x40; 2136 cbp->pri_fc_thresh = 3; 2137 cbp->tx_fc_dis = 0; 2138 cbp->rx_fc_restop = 0; 2139 cbp->rx_fc_restart = 0; 2140 cbp->fc_filter = 0; 2141 cbp->pri_fc_loc = 1; 2142 } else { 2143 cbp->fc_delay_lsb = 0x1f; 2144 cbp->fc_delay_msb = 0x01; 2145 cbp->pri_fc_thresh = 3; 2146 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2147 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2148 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2149 cbp->fc_filter = !prm; /* drop FC frames to host */ 2150 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2151 } 2152 2153 /* 2154 * Start the config command/DMA. 2155 */ 2156 fxp_scb_wait(sc); 2157 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2158 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2159 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2160 /* ...and wait for it to complete. */ 2161 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2162 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2163 2164 /* 2165 * Now initialize the station address. Temporarily use the TxCB 2166 * memory area like we did above for the config CB. 2167 */ 2168 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2169 cb_ias->cb_status = 0; 2170 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2171 cb_ias->link_addr = 0xffffffff; 2172 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2173 sizeof(sc->arpcom.ac_enaddr)); 2174 2175 /* 2176 * Start the IAS (Individual Address Setup) command/DMA. 2177 */ 2178 fxp_scb_wait(sc); 2179 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2180 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2181 /* ...and wait for it to complete. */ 2182 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2183 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2184 2185 /* 2186 * Initialize transmit control block (TxCB) list. 2187 */ 2188 txp = sc->fxp_desc.tx_list; 2189 tcbp = sc->fxp_desc.cbl_list; 2190 bzero(tcbp, FXP_TXCB_SZ); 2191 for (i = 0; i < FXP_NTXCB; i++) { 2192 txp[i].tx_cb = tcbp + i; 2193 txp[i].tx_mbuf = NULL; 2194 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2195 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2196 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2197 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2198 if (sc->flags & FXP_FLAG_EXT_TXCB) 2199 tcbp[i].tbd_array_addr = 2200 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2201 else 2202 tcbp[i].tbd_array_addr = 2203 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2204 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2205 } 2206 /* 2207 * Set the suspend flag on the first TxCB and start the control 2208 * unit. It will execute the NOP and then suspend. 2209 */ 2210 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2211 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2212 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2213 sc->tx_queued = 1; 2214 2215 fxp_scb_wait(sc); 2216 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2217 2218 /* 2219 * Initialize receiver buffer area - RFA. 2220 */ 2221 fxp_scb_wait(sc); 2222 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2223 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2224 2225 /* 2226 * Set current media. 2227 */ 2228 if (sc->miibus != NULL) 2229 mii_mediachg(device_get_softc(sc->miibus)); 2230 2231 ifp->if_flags |= IFF_RUNNING; 2232 ifp->if_flags &= ~IFF_OACTIVE; 2233 2234 /* 2235 * Enable interrupts. 2236 */ 2237#ifdef DEVICE_POLLING 2238 /* 2239 * ... but only do that if we are not polling. And because (presumably) 2240 * the default is interrupts on, we need to disable them explicitly! 2241 */ 2242 if ( ifp->if_flags & IFF_POLLING ) 2243 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2244 else 2245#endif /* DEVICE_POLLING */ 2246 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2247 2248 /* 2249 * Start stats updater. 2250 */ 2251 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2252 splx(s); 2253} 2254 2255static int 2256fxp_serial_ifmedia_upd(struct ifnet *ifp) 2257{ 2258 2259 return (0); 2260} 2261 2262static void 2263fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2264{ 2265 2266 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2267} 2268 2269/* 2270 * Change media according to request. 2271 */ 2272static int 2273fxp_ifmedia_upd(struct ifnet *ifp) 2274{ 2275 struct fxp_softc *sc = ifp->if_softc; 2276 struct mii_data *mii; 2277 2278 mii = device_get_softc(sc->miibus); 2279 mii_mediachg(mii); 2280 return (0); 2281} 2282 2283/* 2284 * Notify the world which media we're using. 2285 */ 2286static void 2287fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2288{ 2289 struct fxp_softc *sc = ifp->if_softc; 2290 struct mii_data *mii; 2291 2292 mii = device_get_softc(sc->miibus); 2293 mii_pollstat(mii); 2294 ifmr->ifm_active = mii->mii_media_active; 2295 ifmr->ifm_status = mii->mii_media_status; 2296 2297 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2298 sc->cu_resume_bug = 1; 2299 else 2300 sc->cu_resume_bug = 0; 2301} 2302 2303/* 2304 * Add a buffer to the end of the RFA buffer list. 2305 * Return 0 if successful, 1 for failure. A failure results in 2306 * adding the 'oldm' (if non-NULL) on to the end of the list - 2307 * tossing out its old contents and recycling it. 2308 * The RFA struct is stuck at the beginning of mbuf cluster and the 2309 * data pointer is fixed up to point just past it. 2310 */ 2311static int 2312fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2313{ 2314 struct mbuf *m; 2315 struct fxp_rfa *rfa, *p_rfa; 2316 struct fxp_rx *p_rx; 2317 bus_dmamap_t tmp_map; 2318 int error; 2319 2320 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2321 if (m == NULL) 2322 return (ENOBUFS); 2323 2324 /* 2325 * Move the data pointer up so that the incoming data packet 2326 * will be 32-bit aligned. 2327 */ 2328 m->m_data += RFA_ALIGNMENT_FUDGE; 2329 2330 /* 2331 * Get a pointer to the base of the mbuf cluster and move 2332 * data start past it. 2333 */ 2334 rfa = mtod(m, struct fxp_rfa *); 2335 m->m_data += sc->rfa_size; 2336 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2337 2338 rfa->rfa_status = 0; 2339 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2340 rfa->actual_size = 0; 2341 2342 /* 2343 * Initialize the rest of the RFA. Note that since the RFA 2344 * is misaligned, we cannot store values directly. We're thus 2345 * using the le32enc() function which handles endianness and 2346 * is also alignment-safe. 2347 */ 2348 le32enc(&rfa->link_addr, 0xffffffff); 2349 le32enc(&rfa->rbd_addr, 0xffffffff); 2350 2351 /* Map the RFA into DMA memory. */ 2352 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2353 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2354 &rxp->rx_addr, 0); 2355 if (error) { 2356 m_freem(m); 2357 return (error); 2358 } 2359 2360 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2361 tmp_map = sc->spare_map; 2362 sc->spare_map = rxp->rx_map; 2363 rxp->rx_map = tmp_map; 2364 rxp->rx_mbuf = m; 2365 2366 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2368 2369 /* 2370 * If there are other buffers already on the list, attach this 2371 * one to the end by fixing up the tail to point to this one. 2372 */ 2373 if (sc->fxp_desc.rx_head != NULL) { 2374 p_rx = sc->fxp_desc.rx_tail; 2375 p_rfa = (struct fxp_rfa *) 2376 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2377 p_rx->rx_next = rxp; 2378 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2379 p_rfa->rfa_control = 0; 2380 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2381 BUS_DMASYNC_PREWRITE); 2382 } else { 2383 rxp->rx_next = NULL; 2384 sc->fxp_desc.rx_head = rxp; 2385 } 2386 sc->fxp_desc.rx_tail = rxp; 2387 return (0); 2388} 2389 2390static volatile int 2391fxp_miibus_readreg(device_t dev, int phy, int reg) 2392{ 2393 struct fxp_softc *sc = device_get_softc(dev); 2394 int count = 10000; 2395 int value; 2396 2397 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2398 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2399 2400 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2401 && count--) 2402 DELAY(10); 2403 2404 if (count <= 0) 2405 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2406 2407 return (value & 0xffff); 2408} 2409 2410static void 2411fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2412{ 2413 struct fxp_softc *sc = device_get_softc(dev); 2414 int count = 10000; 2415 2416 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2417 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2418 (value & 0xffff)); 2419 2420 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2421 count--) 2422 DELAY(10); 2423 2424 if (count <= 0) 2425 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2426} 2427 2428static int 2429fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2430{ 2431 struct fxp_softc *sc = ifp->if_softc; 2432 struct ifreq *ifr = (struct ifreq *)data; 2433 struct mii_data *mii; 2434 int s, error = 0; 2435 2436 /* 2437 * Detaching causes us to call ioctl with the mutex owned. Preclude 2438 * that by saying we're busy if the lock is already held. 2439 */ 2440 if (mtx_owned(&sc->sc_mtx)) 2441 return (EBUSY); 2442 2443 FXP_LOCK(sc); 2444 s = splimp(); 2445 2446 switch (command) { 2447 case SIOCSIFFLAGS: 2448 if (ifp->if_flags & IFF_ALLMULTI) 2449 sc->flags |= FXP_FLAG_ALL_MCAST; 2450 else 2451 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2452 2453 /* 2454 * If interface is marked up and not running, then start it. 2455 * If it is marked down and running, stop it. 2456 * XXX If it's up then re-initialize it. This is so flags 2457 * such as IFF_PROMISC are handled. 2458 */ 2459 if (ifp->if_flags & IFF_UP) { 2460 fxp_init_body(sc); 2461 } else { 2462 if (ifp->if_flags & IFF_RUNNING) 2463 fxp_stop(sc); 2464 } 2465 break; 2466 2467 case SIOCADDMULTI: 2468 case SIOCDELMULTI: 2469 if (ifp->if_flags & IFF_ALLMULTI) 2470 sc->flags |= FXP_FLAG_ALL_MCAST; 2471 else 2472 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2473 /* 2474 * Multicast list has changed; set the hardware filter 2475 * accordingly. 2476 */ 2477 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2478 fxp_mc_setup(sc); 2479 /* 2480 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2481 * again rather than else {}. 2482 */ 2483 if (sc->flags & FXP_FLAG_ALL_MCAST) 2484 fxp_init_body(sc); 2485 error = 0; 2486 break; 2487 2488 case SIOCSIFMEDIA: 2489 case SIOCGIFMEDIA: 2490 if (sc->miibus != NULL) { 2491 mii = device_get_softc(sc->miibus); 2492 error = ifmedia_ioctl(ifp, ifr, 2493 &mii->mii_media, command); 2494 } else { 2495 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2496 } 2497 break; 2498 2499 case SIOCSIFCAP: 2500 ifp->if_capenable = ifr->ifr_reqcap; 2501 break; 2502 2503 default: 2504 /* 2505 * ether_ioctl() will eventually call fxp_start() which 2506 * will result in mutex recursion so drop it first. 2507 */ 2508 FXP_UNLOCK(sc); 2509 error = ether_ioctl(ifp, command, data); 2510 } 2511 if (mtx_owned(&sc->sc_mtx)) 2512 FXP_UNLOCK(sc); 2513 splx(s); 2514 return (error); 2515} 2516 2517/* 2518 * Fill in the multicast address list and return number of entries. 2519 */ 2520static int 2521fxp_mc_addrs(struct fxp_softc *sc) 2522{ 2523 struct fxp_cb_mcs *mcsp = sc->mcsp; 2524 struct ifnet *ifp = &sc->sc_if; 2525 struct ifmultiaddr *ifma; 2526 int nmcasts; 2527 2528 nmcasts = 0; 2529 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2530#if __FreeBSD_version < 500000 2531 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2532#else 2533 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2534#endif 2535 if (ifma->ifma_addr->sa_family != AF_LINK) 2536 continue; 2537 if (nmcasts >= MAXMCADDR) { 2538 sc->flags |= FXP_FLAG_ALL_MCAST; 2539 nmcasts = 0; 2540 break; 2541 } 2542 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2543 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2544 nmcasts++; 2545 } 2546 } 2547 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2548 return (nmcasts); 2549} 2550 2551/* 2552 * Program the multicast filter. 2553 * 2554 * We have an artificial restriction that the multicast setup command 2555 * must be the first command in the chain, so we take steps to ensure 2556 * this. By requiring this, it allows us to keep up the performance of 2557 * the pre-initialized command ring (esp. link pointers) by not actually 2558 * inserting the mcsetup command in the ring - i.e. its link pointer 2559 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2560 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2561 * lead into the regular TxCB ring when it completes. 2562 * 2563 * This function must be called at splimp. 2564 */ 2565static void 2566fxp_mc_setup(struct fxp_softc *sc) 2567{ 2568 struct fxp_cb_mcs *mcsp = sc->mcsp; 2569 struct ifnet *ifp = &sc->sc_if; 2570 struct fxp_tx *txp; 2571 int count; 2572 2573 /* 2574 * If there are queued commands, we must wait until they are all 2575 * completed. If we are already waiting, then add a NOP command 2576 * with interrupt option so that we're notified when all commands 2577 * have been completed - fxp_start() ensures that no additional 2578 * TX commands will be added when need_mcsetup is true. 2579 */ 2580 if (sc->tx_queued) { 2581 /* 2582 * need_mcsetup will be true if we are already waiting for the 2583 * NOP command to be completed (see below). In this case, bail. 2584 */ 2585 if (sc->need_mcsetup) 2586 return; 2587 sc->need_mcsetup = 1; 2588 2589 /* 2590 * Add a NOP command with interrupt so that we are notified 2591 * when all TX commands have been processed. 2592 */ 2593 txp = sc->fxp_desc.tx_last->tx_next; 2594 txp->tx_mbuf = NULL; 2595 txp->tx_cb->cb_status = 0; 2596 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2597 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2598 /* 2599 * Advance the end of list forward. 2600 */ 2601 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2602 htole16(~FXP_CB_COMMAND_S); 2603 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2604 sc->fxp_desc.tx_last = txp; 2605 sc->tx_queued++; 2606 /* 2607 * Issue a resume in case the CU has just suspended. 2608 */ 2609 fxp_scb_wait(sc); 2610 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2611 /* 2612 * Set a 5 second timer just in case we don't hear from the 2613 * card again. 2614 */ 2615 ifp->if_timer = 5; 2616 2617 return; 2618 } 2619 sc->need_mcsetup = 0; 2620 2621 /* 2622 * Initialize multicast setup descriptor. 2623 */ 2624 mcsp->cb_status = 0; 2625 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2626 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2627 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2628 txp = &sc->fxp_desc.mcs_tx; 2629 txp->tx_mbuf = NULL; 2630 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2631 txp->tx_next = sc->fxp_desc.tx_list; 2632 (void) fxp_mc_addrs(sc); 2633 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2634 sc->tx_queued = 1; 2635 2636 /* 2637 * Wait until command unit is not active. This should never 2638 * be the case when nothing is queued, but make sure anyway. 2639 */ 2640 count = 100; 2641 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2642 FXP_SCB_CUS_ACTIVE && --count) 2643 DELAY(10); 2644 if (count == 0) { 2645 device_printf(sc->dev, "command queue timeout\n"); 2646 return; 2647 } 2648 2649 /* 2650 * Start the multicast setup command. 2651 */ 2652 fxp_scb_wait(sc); 2653 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2654 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2655 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2656 2657 ifp->if_timer = 2; 2658 return; 2659} 2660 2661static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2662static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2663static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2664static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2665static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2666static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2667 2668#define UCODE(x) x, sizeof(x) 2669 2670struct ucode { 2671 u_int32_t revision; 2672 u_int32_t *ucode; 2673 int length; 2674 u_short int_delay_offset; 2675 u_short bundle_max_offset; 2676} ucode_table[] = { 2677 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2678 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2679 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2680 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2681 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2682 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2683 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2684 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2685 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2686 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2687 { 0, NULL, 0, 0, 0 } 2688}; 2689 2690static void 2691fxp_load_ucode(struct fxp_softc *sc) 2692{ 2693 struct ucode *uc; 2694 struct fxp_cb_ucode *cbp; 2695 2696 for (uc = ucode_table; uc->ucode != NULL; uc++) 2697 if (sc->revision == uc->revision) 2698 break; 2699 if (uc->ucode == NULL) 2700 return; 2701 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2702 cbp->cb_status = 0; 2703 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2704 cbp->link_addr = 0xffffffff; /* (no) next command */ 2705 memcpy(cbp->ucode, uc->ucode, uc->length); 2706 if (uc->int_delay_offset) 2707 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2708 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2709 if (uc->bundle_max_offset) 2710 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2711 htole16(sc->tunable_bundle_max); 2712 /* 2713 * Download the ucode to the chip. 2714 */ 2715 fxp_scb_wait(sc); 2716 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2717 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2718 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2719 /* ...and wait for it to complete. */ 2720 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2721 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2722 device_printf(sc->dev, 2723 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2724 sc->tunable_int_delay, 2725 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2726 sc->flags |= FXP_FLAG_UCODE; 2727} 2728 2729static int 2730sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2731{ 2732 int error, value; 2733 2734 value = *(int *)arg1; 2735 error = sysctl_handle_int(oidp, &value, 0, req); 2736 if (error || !req->newptr) 2737 return (error); 2738 if (value < low || value > high) 2739 return (EINVAL); 2740 *(int *)arg1 = value; 2741 return (0); 2742} 2743 2744/* 2745 * Interrupt delay is expressed in microseconds, a multiplier is used 2746 * to convert this to the appropriate clock ticks before using. 2747 */ 2748static int 2749sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2750{ 2751 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2752} 2753 2754static int 2755sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2756{ 2757 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2758} 2759