if_fxp.c revision 119277
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30/* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 119277 2003-08-22 05:54:52Z imp $"); 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49 50#include <net/bpf.h> 51#include <sys/sockio.h> 52#include <sys/bus.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if_arp.h> 59 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <dev/pci/pcivar.h> 73#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, pci, 1, 1, 1); 83MODULE_DEPEND(fxp, ether, 1, 1, 1); 84MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85#include "miibus_if.h" 86 87/* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96#define RFA_ALIGNMENT_FUDGE 2 97 98/* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103static int tx_threshold = 64; 104 105/* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139}; 140 141struct fxp_ident { 142 u_int16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145}; 146 147/* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 172 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 173 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 177 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 182 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 186 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 188 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 189 { 0, -1, NULL }, 190}; 191 192#ifdef FXP_IP_CSUM_WAR 193#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 194#else 195#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 196#endif 197 198static int fxp_probe(device_t dev); 199static int fxp_attach(device_t dev); 200static int fxp_detach(device_t dev); 201static int fxp_shutdown(device_t dev); 202static int fxp_suspend(device_t dev); 203static int fxp_resume(device_t dev); 204 205static void fxp_intr(void *xsc); 206static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 207 u_int8_t statack, int count); 208static void fxp_init(void *xsc); 209static void fxp_init_body(struct fxp_softc *sc); 210static void fxp_tick(void *xsc); 211#ifndef BURN_BRIDGES 212static void fxp_powerstate_d0(device_t dev); 213#endif 214static void fxp_start(struct ifnet *ifp); 215static void fxp_start_body(struct ifnet *ifp); 216static void fxp_stop(struct fxp_softc *sc); 217static void fxp_release(struct fxp_softc *sc); 218static int fxp_ioctl(struct ifnet *ifp, u_long command, 219 caddr_t data); 220static void fxp_watchdog(struct ifnet *ifp); 221static int fxp_add_rfabuf(struct fxp_softc *sc, 222 struct fxp_rx *rxp); 223static int fxp_mc_addrs(struct fxp_softc *sc); 224static void fxp_mc_setup(struct fxp_softc *sc); 225static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 226 int autosize); 227static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 228 u_int16_t data); 229static void fxp_autosize_eeprom(struct fxp_softc *sc); 230static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 231 int offset, int words); 232static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234static int fxp_ifmedia_upd(struct ifnet *ifp); 235static void fxp_ifmedia_sts(struct ifnet *ifp, 236 struct ifmediareq *ifmr); 237static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 238static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 241static void fxp_miibus_writereg(device_t dev, int phy, int reg, 242 int value); 243static void fxp_load_ucode(struct fxp_softc *sc); 244static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 245 int low, int high); 246static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 247static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 248static void fxp_scb_wait(struct fxp_softc *sc); 249static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 250static void fxp_dma_wait(struct fxp_softc *sc, 251 volatile u_int16_t *status, bus_dma_tag_t dmat, 252 bus_dmamap_t map); 253 254static device_method_t fxp_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, fxp_probe), 257 DEVMETHOD(device_attach, fxp_attach), 258 DEVMETHOD(device_detach, fxp_detach), 259 DEVMETHOD(device_shutdown, fxp_shutdown), 260 DEVMETHOD(device_suspend, fxp_suspend), 261 DEVMETHOD(device_resume, fxp_resume), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 265 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 266 267 { 0, 0 } 268}; 269 270static driver_t fxp_driver = { 271 "fxp", 272 fxp_methods, 273 sizeof(struct fxp_softc), 274}; 275 276static devclass_t fxp_devclass; 277 278DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 279DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 280DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 281 282static int fxp_rnr; 283SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 284 285static int fxp_noflow; 286SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 287TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 288 289/* 290 * Wait for the previous command to be accepted (but not necessarily 291 * completed). 292 */ 293static void 294fxp_scb_wait(struct fxp_softc *sc) 295{ 296 int i = 10000; 297 298 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 299 DELAY(2); 300 if (i == 0) 301 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 302 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 303 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 304 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 305 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 306} 307 308static void 309fxp_scb_cmd(struct fxp_softc *sc, int cmd) 310{ 311 312 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 313 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 314 fxp_scb_wait(sc); 315 } 316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 317} 318 319static void 320fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 321 bus_dma_tag_t dmat, bus_dmamap_t map) 322{ 323 int i = 10000; 324 325 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 326 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 327 DELAY(2); 328 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 329 } 330 if (i == 0) 331 device_printf(sc->dev, "DMA timeout\n"); 332} 333 334/* 335 * Return identification string if this device is ours. 336 */ 337static int 338fxp_probe(device_t dev) 339{ 340 u_int16_t devid; 341 u_int8_t revid; 342 struct fxp_ident *ident; 343 344 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 345 devid = pci_get_device(dev); 346 revid = pci_get_revid(dev); 347 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 348 if (ident->devid == devid && 349 (ident->revid == revid || ident->revid == -1)) { 350 device_set_desc(dev, ident->name); 351 return (0); 352 } 353 } 354 } 355 return (ENXIO); 356} 357 358#ifndef BURN_BRIDGES 359static void 360fxp_powerstate_d0(device_t dev) 361{ 362#if __FreeBSD_version >= 430002 363 u_int32_t iobase, membase, irq; 364 365 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 366 /* Save important PCI config data. */ 367 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 368 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 369 irq = pci_read_config(dev, PCIR_INTLINE, 4); 370 371 /* Reset the power state. */ 372 device_printf(dev, "chip is in D%d power mode " 373 "-- setting to D0\n", pci_get_powerstate(dev)); 374 375 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 376 377 /* Restore PCI config data. */ 378 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 379 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 380 pci_write_config(dev, PCIR_INTLINE, irq, 4); 381 } 382#endif 383} 384#endif 385 386static void 387fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 388{ 389 u_int32_t *addr; 390 391 if (error) 392 return; 393 394 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 395 addr = arg; 396 *addr = segs->ds_addr; 397} 398 399static int 400fxp_attach(device_t dev) 401{ 402 int error = 0; 403 struct fxp_softc *sc = device_get_softc(dev); 404 struct ifnet *ifp; 405 struct fxp_rx *rxp; 406 u_int32_t val; 407 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 408 int i, rid, m1, m2, prefer_iomap, maxtxseg; 409 int s, ipcbxmit_disable; 410 411 sc->dev = dev; 412 callout_handle_init(&sc->stat_ch); 413 sysctl_ctx_init(&sc->sysctl_ctx); 414 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 415 MTX_DEF); 416 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 417 fxp_serial_ifmedia_sts); 418 419 s = splimp(); 420 421 /* 422 * Enable bus mastering. 423 */ 424 pci_enable_busmaster(dev); 425 val = pci_read_config(dev, PCIR_COMMAND, 2); 426#ifndef BURN_BRIDGES 427 fxp_powerstate_d0(dev); 428#endif 429 /* 430 * Figure out which we should try first - memory mapping or i/o mapping? 431 * We default to memory mapping. Then we accept an override from the 432 * command line. Then we check to see which one is enabled. 433 */ 434 m1 = PCIM_CMD_MEMEN; 435 m2 = PCIM_CMD_PORTEN; 436 prefer_iomap = 0; 437 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 438 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 439 m1 = PCIM_CMD_PORTEN; 440 m2 = PCIM_CMD_MEMEN; 441 } 442 443 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 444 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 445 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 446 0, ~0, 1, RF_ACTIVE); 447 if (sc->mem == NULL) { 448 sc->rtp = 449 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 450 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 451 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 452 0, ~0, 1, RF_ACTIVE); 453 } 454 455 if (!sc->mem) { 456 error = ENXIO; 457 goto fail; 458 } 459 if (bootverbose) { 460 device_printf(dev, "using %s space register mapping\n", 461 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 462 } 463 464 sc->sc_st = rman_get_bustag(sc->mem); 465 sc->sc_sh = rman_get_bushandle(sc->mem); 466 467 /* 468 * Allocate our interrupt. 469 */ 470 rid = 0; 471 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->irq == NULL) { 474 device_printf(dev, "could not map interrupt\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 /* 480 * Reset to a stable state. 481 */ 482 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 483 DELAY(10); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Determine whether we must use the 503 serial interface. 492 */ 493 fxp_read_eeprom(sc, &data, 6, 1); 494 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 495 (data & FXP_PHY_SERIAL_ONLY)) 496 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 497 498 /* 499 * Create the sysctl tree 500 */ 501 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 502 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 503 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 504 if (sc->sysctl_tree == NULL) { 505 error = ENXIO; 506 goto fail; 507 } 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573#if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579#endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 599 /* enable reception of long frames for VLAN */ 600 sc->flags |= FXP_FLAG_LONG_PKT_EN; 601 } 602 603 /* 604 * Enable use of extended RFDs and TCBs for 82550 605 * and later chips. Note: we need extended TXCB support 606 * too, but that's already enabled by the code above. 607 * Be careful to do this only on the right devices. 608 * 609 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 610 * truncate packets that end with an mbuf containing 1 to 3 bytes 611 * when used with this feature enabled in the previous version of the 612 * driver. This problem appears to be fixed now that the driver 613 * always sets the hardware parse bit in the IPCB structure, which 614 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 615 * Source Software Developer Manual" says is necessary in the 616 * cases where packet truncation was observed. 617 * 618 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 619 * allows this feature to be disabled at boot time. 620 * 621 * If fxp is not compiled into the kernel, this feature may also 622 * be disabled at run time: 623 * # kldunload fxp 624 * # kenv hint.fxp.0.ipcbxmit_disable=1 625 * # kldload fxp 626 */ 627 628 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 629 &ipcbxmit_disable) != 0) 630 ipcbxmit_disable = 0; 631 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 632 sc->revision == FXP_REV_82550_C)) { 633 sc->rfa_size = sizeof (struct fxp_rfa); 634 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 635 sc->flags |= FXP_FLAG_EXT_RFA; 636 } else { 637 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 638 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 639 } 640 641 /* 642 * Allocate DMA tags and DMA safe memory. 643 */ 644 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 645 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 646 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 647 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 648 if (error) { 649 device_printf(dev, "could not allocate dma tag\n"); 650 goto fail; 651 } 652 653 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 654 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 655 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 656 &sc->fxp_stag); 657 if (error) { 658 device_printf(dev, "could not allocate dma tag\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 663 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 664 if (error) 665 goto fail; 666 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 667 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 668 if (error) { 669 device_printf(dev, "could not map the stats buffer\n"); 670 goto fail; 671 } 672 673 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 674 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 675 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 676 if (error) { 677 device_printf(dev, "could not allocate dma tag\n"); 678 goto fail; 679 } 680 681 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 682 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 683 if (error) 684 goto fail; 685 686 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 687 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 688 &sc->fxp_desc.cbl_addr, 0); 689 if (error) { 690 device_printf(dev, "could not map DMA memory\n"); 691 goto fail; 692 } 693 694 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 695 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 696 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 697 &sc->mcs_tag); 698 if (error) { 699 device_printf(dev, "could not allocate dma tag\n"); 700 goto fail; 701 } 702 703 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 704 BUS_DMA_NOWAIT, &sc->mcs_map); 705 if (error) 706 goto fail; 707 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 708 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 709 if (error) { 710 device_printf(dev, "can't map the multicast setup command\n"); 711 goto fail; 712 } 713 714 /* 715 * Pre-allocate the TX DMA maps. 716 */ 717 for (i = 0; i < FXP_NTXCB; i++) { 718 error = bus_dmamap_create(sc->fxp_mtag, 0, 719 &sc->fxp_desc.tx_list[i].tx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for TX\n"); 722 goto fail; 723 } 724 } 725 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 726 if (error) { 727 device_printf(dev, "can't create spare DMA map\n"); 728 goto fail; 729 } 730 731 /* 732 * Pre-allocate our receive buffers. 733 */ 734 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 735 for (i = 0; i < FXP_NRFABUFS; i++) { 736 rxp = &sc->fxp_desc.rx_list[i]; 737 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 738 if (error) { 739 device_printf(dev, "can't create DMA map for RX\n"); 740 goto fail; 741 } 742 if (fxp_add_rfabuf(sc, rxp) != 0) { 743 error = ENOMEM; 744 goto fail; 745 } 746 } 747 748 /* 749 * Read MAC address. 750 */ 751 fxp_read_eeprom(sc, myea, 0, 3); 752 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 753 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 754 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 755 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 756 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 757 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 758 device_printf(dev, "Ethernet address %6D%s\n", 759 sc->arpcom.ac_enaddr, ":", 760 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 761 if (bootverbose) { 762 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 763 pci_get_vendor(dev), pci_get_device(dev), 764 pci_get_subvendor(dev), pci_get_subdevice(dev), 765 pci_get_revid(dev)); 766 fxp_read_eeprom(sc, &data, 10, 1); 767 device_printf(dev, "Dynamic Standby mode is %s\n", 768 data & 0x02 ? "enabled" : "disabled"); 769 } 770 771 /* 772 * If this is only a 10Mbps device, then there is no MII, and 773 * the PHY will use a serial interface instead. 774 * 775 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 776 * doesn't have a programming interface of any sort. The 777 * media is sensed automatically based on how the link partner 778 * is configured. This is, in essence, manual configuration. 779 */ 780 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 781 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 782 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 783 } else { 784 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 785 fxp_ifmedia_sts)) { 786 device_printf(dev, "MII without any PHY!\n"); 787 error = ENXIO; 788 goto fail; 789 } 790 } 791 792 ifp = &sc->arpcom.ac_if; 793 ifp->if_unit = device_get_unit(dev); 794 ifp->if_name = "fxp"; 795 ifp->if_output = ether_output; 796 ifp->if_baudrate = 100000000; 797 ifp->if_init = fxp_init; 798 ifp->if_softc = sc; 799 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 800 ifp->if_ioctl = fxp_ioctl; 801 ifp->if_start = fxp_start; 802 ifp->if_watchdog = fxp_watchdog; 803 804 /* Enable checksum offload for 82550 or better chips */ 805 if (sc->flags & FXP_FLAG_EXT_RFA) { 806 ifp->if_hwassist = FXP_CSUM_FEATURES; 807 ifp->if_capabilities = IFCAP_HWCSUM; 808 ifp->if_capenable = ifp->if_capabilities; 809 } 810 811 /* 812 * Attach the interface. 813 */ 814 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 815 816 /* 817 * Tell the upper layer(s) we support long frames. 818 */ 819 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 820 ifp->if_capabilities |= IFCAP_VLAN_MTU; 821 822 /* 823 * Let the system queue as many packets as we have available 824 * TX descriptors. 825 */ 826 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 827 828 /* 829 * Hook our interrupt after all initialization is complete. 830 * XXX This driver has been tested with the INTR_MPSAFFE flag set 831 * however, ifp and its functions are not fully locked so MPSAFE 832 * should not be used unless you can handle potential data loss. 833 */ 834 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, 835 fxp_intr, sc, &sc->ih); 836 if (error) { 837 device_printf(dev, "could not setup irq\n"); 838 ether_ifdetach(&sc->arpcom.ac_if); 839 goto fail; 840 } 841 842fail: 843 splx(s); 844 if (error) 845 fxp_release(sc); 846 return (error); 847} 848 849/* 850 * Release all resources. The softc lock should not be held and the 851 * interrupt should already be torn down. 852 */ 853static void 854fxp_release(struct fxp_softc *sc) 855{ 856 struct fxp_rx *rxp; 857 struct fxp_tx *txp; 858 int i; 859 860 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 861 if (sc->ih) 862 panic("fxp_release() called with intr handle still active"); 863 if (sc->miibus) 864 device_delete_child(sc->dev, sc->miibus); 865 bus_generic_detach(sc->dev); 866 ifmedia_removeall(&sc->sc_media); 867 if (sc->fxp_desc.cbl_list) { 868 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 869 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 870 sc->cbl_map); 871 } 872 if (sc->fxp_stats) { 873 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 874 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 875 } 876 if (sc->mcsp) { 877 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 878 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 879 } 880 if (sc->irq) 881 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 882 if (sc->mem) 883 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 884 if (sc->fxp_mtag) { 885 for (i = 0; i < FXP_NRFABUFS; i++) { 886 rxp = &sc->fxp_desc.rx_list[i]; 887 if (rxp->rx_mbuf != NULL) { 888 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 889 BUS_DMASYNC_POSTREAD); 890 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 891 m_freem(rxp->rx_mbuf); 892 } 893 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 894 } 895 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 896 bus_dma_tag_destroy(sc->fxp_mtag); 897 } 898 if (sc->fxp_stag) { 899 for (i = 0; i < FXP_NTXCB; i++) { 900 txp = &sc->fxp_desc.tx_list[i]; 901 if (txp->tx_mbuf != NULL) { 902 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 903 BUS_DMASYNC_POSTWRITE); 904 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 905 m_freem(txp->tx_mbuf); 906 } 907 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 908 } 909 bus_dma_tag_destroy(sc->fxp_stag); 910 } 911 if (sc->cbl_tag) 912 bus_dma_tag_destroy(sc->cbl_tag); 913 if (sc->mcs_tag) 914 bus_dma_tag_destroy(sc->mcs_tag); 915 916 sysctl_ctx_free(&sc->sysctl_ctx); 917 918 mtx_destroy(&sc->sc_mtx); 919} 920 921/* 922 * Detach interface. 923 */ 924static int 925fxp_detach(device_t dev) 926{ 927 struct fxp_softc *sc = device_get_softc(dev); 928 int s; 929 930 FXP_LOCK(sc); 931 s = splimp(); 932 933 sc->suspended = 1; /* Do same thing as we do for suspend */ 934 /* 935 * Close down routes etc. 936 */ 937 ether_ifdetach(&sc->arpcom.ac_if); 938 939 /* 940 * Stop DMA and drop transmit queue, but disable interrupts first. 941 */ 942 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 943 fxp_stop(sc); 944 FXP_UNLOCK(sc); 945 946 /* 947 * Unhook interrupt before dropping lock. This is to prevent 948 * races with fxp_intr(). 949 */ 950 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 951 sc->ih = NULL; 952 953 splx(s); 954 955 /* Release our allocated resources. */ 956 fxp_release(sc); 957 return (0); 958} 959 960/* 961 * Device shutdown routine. Called at system shutdown after sync. The 962 * main purpose of this routine is to shut off receiver DMA so that 963 * kernel memory doesn't get clobbered during warmboot. 964 */ 965static int 966fxp_shutdown(device_t dev) 967{ 968 /* 969 * Make sure that DMA is disabled prior to reboot. Not doing 970 * do could allow DMA to corrupt kernel memory during the 971 * reboot before the driver initializes. 972 */ 973 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 974 return (0); 975} 976 977/* 978 * Device suspend routine. Stop the interface and save some PCI 979 * settings in case the BIOS doesn't restore them properly on 980 * resume. 981 */ 982static int 983fxp_suspend(device_t dev) 984{ 985 struct fxp_softc *sc = device_get_softc(dev); 986 int i, s; 987 988 FXP_LOCK(sc); 989 s = splimp(); 990 991 fxp_stop(sc); 992 993 for (i = 0; i < 5; i++) 994 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 995 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 996 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 997 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 998 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 999 1000 sc->suspended = 1; 1001 1002 FXP_UNLOCK(sc); 1003 splx(s); 1004 return (0); 1005} 1006 1007/* 1008 * Device resume routine. Restore some PCI settings in case the BIOS 1009 * doesn't, re-enable busmastering, and restart the interface if 1010 * appropriate. 1011 */ 1012static int 1013fxp_resume(device_t dev) 1014{ 1015 struct fxp_softc *sc = device_get_softc(dev); 1016 struct ifnet *ifp = &sc->sc_if; 1017 u_int16_t pci_command; 1018 int i, s; 1019 1020 FXP_LOCK(sc); 1021 s = splimp(); 1022#ifndef BURN_BRIDGES 1023 fxp_powerstate_d0(dev); 1024#endif 1025 /* better way to do this? */ 1026 for (i = 0; i < 5; i++) 1027 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1028 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1029 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1030 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1031 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1032 1033 /* reenable busmastering */ 1034 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1035 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1036 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1037 1038 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1039 DELAY(10); 1040 1041 /* reinitialize interface if necessary */ 1042 if (ifp->if_flags & IFF_UP) 1043 fxp_init_body(sc); 1044 1045 sc->suspended = 0; 1046 1047 FXP_UNLOCK(sc); 1048 splx(s); 1049 return (0); 1050} 1051 1052static void 1053fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1054{ 1055 u_int16_t reg; 1056 int x; 1057 1058 /* 1059 * Shift in data. 1060 */ 1061 for (x = 1 << (length - 1); x; x >>= 1) { 1062 if (data & x) 1063 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1064 else 1065 reg = FXP_EEPROM_EECS; 1066 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1067 DELAY(1); 1068 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1069 DELAY(1); 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1071 DELAY(1); 1072 } 1073} 1074 1075/* 1076 * Read from the serial EEPROM. Basically, you manually shift in 1077 * the read opcode (one bit at a time) and then shift in the address, 1078 * and then you shift out the data (all of this one bit at a time). 1079 * The word size is 16 bits, so you have to provide the address for 1080 * every 16 bits of data. 1081 */ 1082static u_int16_t 1083fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1084{ 1085 u_int16_t reg, data; 1086 int x; 1087 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1089 /* 1090 * Shift in read opcode. 1091 */ 1092 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1093 /* 1094 * Shift in address. 1095 */ 1096 data = 0; 1097 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1098 if (offset & x) 1099 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1100 else 1101 reg = FXP_EEPROM_EECS; 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1103 DELAY(1); 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1105 DELAY(1); 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1107 DELAY(1); 1108 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1109 data++; 1110 if (autosize && reg == 0) { 1111 sc->eeprom_size = data; 1112 break; 1113 } 1114 } 1115 /* 1116 * Shift out data. 1117 */ 1118 data = 0; 1119 reg = FXP_EEPROM_EECS; 1120 for (x = 1 << 15; x; x >>= 1) { 1121 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1122 DELAY(1); 1123 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1124 data |= x; 1125 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1126 DELAY(1); 1127 } 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1129 DELAY(1); 1130 1131 return (data); 1132} 1133 1134static void 1135fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1136{ 1137 int i; 1138 1139 /* 1140 * Erase/write enable. 1141 */ 1142 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1143 fxp_eeprom_shiftin(sc, 0x4, 3); 1144 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1146 DELAY(1); 1147 /* 1148 * Shift in write opcode, address, data. 1149 */ 1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1151 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1152 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1153 fxp_eeprom_shiftin(sc, data, 16); 1154 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1155 DELAY(1); 1156 /* 1157 * Wait for EEPROM to finish up. 1158 */ 1159 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1160 DELAY(1); 1161 for (i = 0; i < 1000; i++) { 1162 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1163 break; 1164 DELAY(50); 1165 } 1166 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1167 DELAY(1); 1168 /* 1169 * Erase/write disable. 1170 */ 1171 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1172 fxp_eeprom_shiftin(sc, 0x4, 3); 1173 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1175 DELAY(1); 1176} 1177 1178/* 1179 * From NetBSD: 1180 * 1181 * Figure out EEPROM size. 1182 * 1183 * 559's can have either 64-word or 256-word EEPROMs, the 558 1184 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1185 * talks about the existance of 16 to 256 word EEPROMs. 1186 * 1187 * The only known sizes are 64 and 256, where the 256 version is used 1188 * by CardBus cards to store CIS information. 1189 * 1190 * The address is shifted in msb-to-lsb, and after the last 1191 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1192 * after which follows the actual data. We try to detect this zero, by 1193 * probing the data-out bit in the EEPROM control register just after 1194 * having shifted in a bit. If the bit is zero, we assume we've 1195 * shifted enough address bits. The data-out should be tri-state, 1196 * before this, which should translate to a logical one. 1197 */ 1198static void 1199fxp_autosize_eeprom(struct fxp_softc *sc) 1200{ 1201 1202 /* guess maximum size of 256 words */ 1203 sc->eeprom_size = 8; 1204 1205 /* autosize */ 1206 (void) fxp_eeprom_getword(sc, 0, 1); 1207} 1208 1209static void 1210fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1211{ 1212 int i; 1213 1214 for (i = 0; i < words; i++) 1215 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1216} 1217 1218static void 1219fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1220{ 1221 int i; 1222 1223 for (i = 0; i < words; i++) 1224 fxp_eeprom_putword(sc, offset + i, data[i]); 1225} 1226 1227static void 1228fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1229 bus_size_t mapsize, int error) 1230{ 1231 struct fxp_softc *sc; 1232 struct fxp_cb_tx *txp; 1233 int i; 1234 1235 if (error) 1236 return; 1237 1238 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1239 1240 sc = arg; 1241 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1242 for (i = 0; i < nseg; i++) { 1243 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1244 /* 1245 * If this is an 82550/82551, then we're using extended 1246 * TxCBs _and_ we're using checksum offload. This means 1247 * that the TxCB is really an IPCB. One major difference 1248 * between the two is that with plain extended TxCBs, 1249 * the bottom half of the TxCB contains two entries from 1250 * the TBD array, whereas IPCBs contain just one entry: 1251 * one entry (8 bytes) has been sacrificed for the TCP/IP 1252 * checksum offload control bits. So to make things work 1253 * right, we have to start filling in the TBD array 1254 * starting from a different place depending on whether 1255 * the chip is an 82550/82551 or not. 1256 */ 1257 if (sc->flags & FXP_FLAG_EXT_RFA) { 1258 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1259 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1260 } else { 1261 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1262 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1263 } 1264 } 1265 txp->tbd_number = nseg; 1266} 1267 1268/* 1269 * Grab the softc lock and call the real fxp_start_body() routine 1270 */ 1271static void 1272fxp_start(struct ifnet *ifp) 1273{ 1274 struct fxp_softc *sc = ifp->if_softc; 1275 1276 FXP_LOCK(sc); 1277 fxp_start_body(ifp); 1278 FXP_UNLOCK(sc); 1279} 1280 1281/* 1282 * Start packet transmission on the interface. 1283 * This routine must be called with the softc lock held, and is an 1284 * internal entry point only. 1285 */ 1286static void 1287fxp_start_body(struct ifnet *ifp) 1288{ 1289 struct fxp_softc *sc = ifp->if_softc; 1290 struct fxp_tx *txp; 1291 struct mbuf *mb_head; 1292 int error; 1293 1294 mtx_assert(&sc->sc_mtx, MA_OWNED); 1295 /* 1296 * See if we need to suspend xmit until the multicast filter 1297 * has been reprogrammed (which can only be done at the head 1298 * of the command chain). 1299 */ 1300 if (sc->need_mcsetup) { 1301 return; 1302 } 1303 1304 txp = NULL; 1305 1306 /* 1307 * We're finished if there is nothing more to add to the list or if 1308 * we're all filled up with buffers to transmit. 1309 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1310 * a NOP command when needed. 1311 */ 1312 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1313 1314 /* 1315 * Grab a packet to transmit. 1316 */ 1317 IF_DEQUEUE(&ifp->if_snd, mb_head); 1318 1319 /* 1320 * Get pointer to next available tx desc. 1321 */ 1322 txp = sc->fxp_desc.tx_last->tx_next; 1323 1324 /* 1325 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1326 * Ethernet Controller Family Open Source Software 1327 * Developer Manual says: 1328 * Using software parsing is only allowed with legal 1329 * TCP/IP or UDP/IP packets. 1330 * ... 1331 * For all other datagrams, hardware parsing must 1332 * be used. 1333 * Software parsing appears to truncate ICMP and 1334 * fragmented UDP packets that contain one to three 1335 * bytes in the second (and final) mbuf of the packet. 1336 */ 1337 if (sc->flags & FXP_FLAG_EXT_RFA) 1338 txp->tx_cb->ipcb_ip_activation_high = 1339 FXP_IPCB_HARDWAREPARSING_ENABLE; 1340 1341 /* 1342 * Deal with TCP/IP checksum offload. Note that 1343 * in order for TCP checksum offload to work, 1344 * the pseudo header checksum must have already 1345 * been computed and stored in the checksum field 1346 * in the TCP header. The stack should have 1347 * already done this for us. 1348 */ 1349 1350 if (mb_head->m_pkthdr.csum_flags) { 1351 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1352 txp->tx_cb->ipcb_ip_schedule = 1353 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1354 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1355 txp->tx_cb->ipcb_ip_schedule |= 1356 FXP_IPCB_TCP_PACKET; 1357 } 1358#ifdef FXP_IP_CSUM_WAR 1359 /* 1360 * XXX The 82550 chip appears to have trouble 1361 * dealing with IP header checksums in very small 1362 * datagrams, namely fragments from 1 to 3 bytes 1363 * in size. For example, say you want to transmit 1364 * a UDP packet of 1473 bytes. The packet will be 1365 * fragmented over two IP datagrams, the latter 1366 * containing only one byte of data. The 82550 will 1367 * botch the header checksum on the 1-byte fragment. 1368 * As long as the datagram contains 4 or more bytes 1369 * of data, you're ok. 1370 * 1371 * The following code attempts to work around this 1372 * problem: if the datagram is less than 38 bytes 1373 * in size (14 bytes ether header, 20 bytes IP header, 1374 * plus 4 bytes of data), we punt and compute the IP 1375 * header checksum by hand. This workaround doesn't 1376 * work very well, however, since it can be fooled 1377 * by things like VLAN tags and IP options that make 1378 * the header sizes/offsets vary. 1379 */ 1380 1381 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1382 if (mb_head->m_pkthdr.len < 38) { 1383 struct ip *ip; 1384 mb_head->m_data += ETHER_HDR_LEN; 1385 ip = mtod(mb_head, struct ip *); 1386 ip->ip_sum = in_cksum(mb_head, 1387 ip->ip_hl << 2); 1388 mb_head->m_data -= ETHER_HDR_LEN; 1389 } else { 1390 txp->tx_cb->ipcb_ip_activation_high = 1391 FXP_IPCB_HARDWAREPARSING_ENABLE; 1392 txp->tx_cb->ipcb_ip_schedule |= 1393 FXP_IPCB_IP_CHECKSUM_ENABLE; 1394 } 1395 } 1396#endif 1397 } 1398 1399 /* 1400 * Go through each of the mbufs in the chain and initialize 1401 * the transmit buffer descriptors with the physical address 1402 * and size of the mbuf. 1403 */ 1404 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1405 mb_head, fxp_dma_map_txbuf, sc, 0); 1406 1407 if (error && error != EFBIG) { 1408 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1409 error); 1410 m_freem(mb_head); 1411 break; 1412 } 1413 1414 if (error) { 1415 struct mbuf *mn; 1416 1417 /* 1418 * We ran out of segments. We have to recopy this 1419 * mbuf chain first. Bail out if we can't get the 1420 * new buffers. 1421 */ 1422 mn = m_defrag(mb_head, M_DONTWAIT); 1423 if (mn == NULL) { 1424 m_freem(mb_head); 1425 break; 1426 } else { 1427 mb_head = mn; 1428 } 1429 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1430 mb_head, fxp_dma_map_txbuf, sc, 0); 1431 if (error) { 1432 device_printf(sc->dev, 1433 "can't map mbuf (error %d)\n", error); 1434 m_freem(mb_head); 1435 break; 1436 } 1437 } 1438 1439 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1440 BUS_DMASYNC_PREWRITE); 1441 1442 txp->tx_mbuf = mb_head; 1443 txp->tx_cb->cb_status = 0; 1444 txp->tx_cb->byte_count = 0; 1445 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1446 txp->tx_cb->cb_command = 1447 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1448 FXP_CB_COMMAND_S); 1449 } else { 1450 txp->tx_cb->cb_command = 1451 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1452 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1453 /* 1454 * Set a 5 second timer just in case we don't hear 1455 * from the card again. 1456 */ 1457 ifp->if_timer = 5; 1458 } 1459 txp->tx_cb->tx_threshold = tx_threshold; 1460 1461 /* 1462 * Advance the end of list forward. 1463 */ 1464 1465#ifdef __alpha__ 1466 /* 1467 * On platforms which can't access memory in 16-bit 1468 * granularities, we must prevent the card from DMA'ing 1469 * up the status while we update the command field. 1470 * This could cause us to overwrite the completion status. 1471 * XXX This is probably bogus and we're _not_ looking 1472 * for atomicity here. 1473 */ 1474 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1475 htole16(FXP_CB_COMMAND_S)); 1476#else 1477 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1478 htole16(~FXP_CB_COMMAND_S); 1479#endif /*__alpha__*/ 1480 sc->fxp_desc.tx_last = txp; 1481 1482 /* 1483 * Advance the beginning of the list forward if there are 1484 * no other packets queued (when nothing is queued, tx_first 1485 * sits on the last TxCB that was sent out). 1486 */ 1487 if (sc->tx_queued == 0) 1488 sc->fxp_desc.tx_first = txp; 1489 1490 sc->tx_queued++; 1491 1492 /* 1493 * Pass packet to bpf if there is a listener. 1494 */ 1495 BPF_MTAP(ifp, mb_head); 1496 } 1497 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1498 1499 /* 1500 * We're finished. If we added to the list, issue a RESUME to get DMA 1501 * going again if suspended. 1502 */ 1503 if (txp != NULL) { 1504 fxp_scb_wait(sc); 1505 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1506 } 1507} 1508 1509#ifdef DEVICE_POLLING 1510static poll_handler_t fxp_poll; 1511 1512static void 1513fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1514{ 1515 struct fxp_softc *sc = ifp->if_softc; 1516 u_int8_t statack; 1517 1518 FXP_LOCK(sc); 1519 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1520 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1521 FXP_UNLOCK(sc); 1522 return; 1523 } 1524 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1525 FXP_SCB_STATACK_FR; 1526 if (cmd == POLL_AND_CHECK_STATUS) { 1527 u_int8_t tmp; 1528 1529 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1530 if (tmp == 0xff || tmp == 0) { 1531 FXP_UNLOCK(sc); 1532 return; /* nothing to do */ 1533 } 1534 tmp &= ~statack; 1535 /* ack what we can */ 1536 if (tmp != 0) 1537 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1538 statack |= tmp; 1539 } 1540 fxp_intr_body(sc, ifp, statack, count); 1541 FXP_UNLOCK(sc); 1542} 1543#endif /* DEVICE_POLLING */ 1544 1545/* 1546 * Process interface interrupts. 1547 */ 1548static void 1549fxp_intr(void *xsc) 1550{ 1551 struct fxp_softc *sc = xsc; 1552 struct ifnet *ifp = &sc->sc_if; 1553 u_int8_t statack; 1554 1555 FXP_LOCK(sc); 1556 if (sc->suspended) { 1557 FXP_UNLOCK(sc); 1558 return; 1559 } 1560 1561#ifdef DEVICE_POLLING 1562 if (ifp->if_flags & IFF_POLLING) { 1563 FXP_UNLOCK(sc); 1564 return; 1565 } 1566 if (ether_poll_register(fxp_poll, ifp)) { 1567 /* disable interrupts */ 1568 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1569 FXP_UNLOCK(sc); 1570 fxp_poll(ifp, 0, 1); 1571 return; 1572 } 1573#endif 1574 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1575 /* 1576 * It should not be possible to have all bits set; the 1577 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1578 * all bits are set, this may indicate that the card has 1579 * been physically ejected, so ignore it. 1580 */ 1581 if (statack == 0xff) { 1582 FXP_UNLOCK(sc); 1583 return; 1584 } 1585 1586 /* 1587 * First ACK all the interrupts in this pass. 1588 */ 1589 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1590 fxp_intr_body(sc, ifp, statack, -1); 1591 } 1592 FXP_UNLOCK(sc); 1593} 1594 1595static void 1596fxp_txeof(struct fxp_softc *sc) 1597{ 1598 struct fxp_tx *txp; 1599 1600 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1601 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1602 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1603 txp = txp->tx_next) { 1604 if (txp->tx_mbuf != NULL) { 1605 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1606 BUS_DMASYNC_POSTWRITE); 1607 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1608 m_freem(txp->tx_mbuf); 1609 txp->tx_mbuf = NULL; 1610 /* clear this to reset csum offload bits */ 1611 txp->tx_cb->tbd[0].tb_addr = 0; 1612 } 1613 sc->tx_queued--; 1614 } 1615 sc->fxp_desc.tx_first = txp; 1616 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1617} 1618 1619static void 1620fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1621 int count) 1622{ 1623 struct mbuf *m; 1624 struct fxp_rx *rxp; 1625 struct fxp_rfa *rfa; 1626 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1627 1628 mtx_assert(&sc->sc_mtx, MA_OWNED); 1629 if (rnr) 1630 fxp_rnr++; 1631#ifdef DEVICE_POLLING 1632 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1633 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1634 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1635 rnr = 1; 1636 } 1637#endif 1638 1639 /* 1640 * Free any finished transmit mbuf chains. 1641 * 1642 * Handle the CNA event likt a CXTNO event. It used to 1643 * be that this event (control unit not ready) was not 1644 * encountered, but it is now with the SMPng modifications. 1645 * The exact sequence of events that occur when the interface 1646 * is brought up are different now, and if this event 1647 * goes unhandled, the configuration/rxfilter setup sequence 1648 * can stall for several seconds. The result is that no 1649 * packets go out onto the wire for about 5 to 10 seconds 1650 * after the interface is ifconfig'ed for the first time. 1651 */ 1652 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1653 fxp_txeof(sc); 1654 1655 ifp->if_timer = 0; 1656 if (sc->tx_queued == 0) { 1657 if (sc->need_mcsetup) 1658 fxp_mc_setup(sc); 1659 } 1660 /* 1661 * Try to start more packets transmitting. 1662 */ 1663 if (ifp->if_snd.ifq_head != NULL) 1664 fxp_start_body(ifp); 1665 } 1666 1667 /* 1668 * Just return if nothing happened on the receive side. 1669 */ 1670 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1671 return; 1672 1673 /* 1674 * Process receiver interrupts. If a no-resource (RNR) 1675 * condition exists, get whatever packets we can and 1676 * re-start the receiver. 1677 * 1678 * When using polling, we do not process the list to completion, 1679 * so when we get an RNR interrupt we must defer the restart 1680 * until we hit the last buffer with the C bit set. 1681 * If we run out of cycles and rfa_headm has the C bit set, 1682 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1683 * that the info will be used in the subsequent polling cycle. 1684 */ 1685 for (;;) { 1686 rxp = sc->fxp_desc.rx_head; 1687 m = rxp->rx_mbuf; 1688 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1689 RFA_ALIGNMENT_FUDGE); 1690 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1691 BUS_DMASYNC_POSTREAD); 1692 1693#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1694 if (count >= 0 && count-- == 0) { 1695 if (rnr) { 1696 /* Defer RNR processing until the next time. */ 1697 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1698 rnr = 0; 1699 } 1700 break; 1701 } 1702#endif /* DEVICE_POLLING */ 1703 1704 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1705 break; 1706 1707 /* 1708 * Advance head forward. 1709 */ 1710 sc->fxp_desc.rx_head = rxp->rx_next; 1711 1712 /* 1713 * Add a new buffer to the receive chain. 1714 * If this fails, the old buffer is recycled 1715 * instead. 1716 */ 1717 if (fxp_add_rfabuf(sc, rxp) == 0) { 1718 int total_len; 1719 1720 /* 1721 * Fetch packet length (the top 2 bits of 1722 * actual_size are flags set by the controller 1723 * upon completion), and drop the packet in case 1724 * of bogus length or CRC errors. 1725 */ 1726 total_len = le16toh(rfa->actual_size) & 0x3fff; 1727 if (total_len < sizeof(struct ether_header) || 1728 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1729 sc->rfa_size || 1730 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1731 m_freem(m); 1732 continue; 1733 } 1734 1735 /* Do IP checksum checking. */ 1736 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1737 if (rfa->rfax_csum_sts & 1738 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1739 m->m_pkthdr.csum_flags |= 1740 CSUM_IP_CHECKED; 1741 if (rfa->rfax_csum_sts & 1742 FXP_RFDX_CS_IP_CSUM_VALID) 1743 m->m_pkthdr.csum_flags |= 1744 CSUM_IP_VALID; 1745 if ((rfa->rfax_csum_sts & 1746 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1747 (rfa->rfax_csum_sts & 1748 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1749 m->m_pkthdr.csum_flags |= 1750 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1751 m->m_pkthdr.csum_data = 0xffff; 1752 } 1753 } 1754 1755 m->m_pkthdr.len = m->m_len = total_len; 1756 m->m_pkthdr.rcvif = ifp; 1757 1758 /* 1759 * Drop locks before calling if_input() since it 1760 * may re-enter fxp_start() in the netisr case. 1761 * This would result in a lock reversal. Better 1762 * performance might be obtained by chaining all 1763 * packets received, dropping the lock, and then 1764 * calling if_input() on each one. 1765 */ 1766 FXP_UNLOCK(sc); 1767 (*ifp->if_input)(ifp, m); 1768 FXP_LOCK(sc); 1769 } 1770 } 1771 if (rnr) { 1772 fxp_scb_wait(sc); 1773 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1774 sc->fxp_desc.rx_head->rx_addr); 1775 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1776 } 1777} 1778 1779/* 1780 * Update packet in/out/collision statistics. The i82557 doesn't 1781 * allow you to access these counters without doing a fairly 1782 * expensive DMA to get _all_ of the statistics it maintains, so 1783 * we do this operation here only once per second. The statistics 1784 * counters in the kernel are updated from the previous dump-stats 1785 * DMA and then a new dump-stats DMA is started. The on-chip 1786 * counters are zeroed when the DMA completes. If we can't start 1787 * the DMA immediately, we don't wait - we just prepare to read 1788 * them again next time. 1789 */ 1790static void 1791fxp_tick(void *xsc) 1792{ 1793 struct fxp_softc *sc = xsc; 1794 struct ifnet *ifp = &sc->sc_if; 1795 struct fxp_stats *sp = sc->fxp_stats; 1796 int s; 1797 1798 FXP_LOCK(sc); 1799 s = splimp(); 1800 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1801 ifp->if_opackets += le32toh(sp->tx_good); 1802 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1803 if (sp->rx_good) { 1804 ifp->if_ipackets += le32toh(sp->rx_good); 1805 sc->rx_idle_secs = 0; 1806 } else { 1807 /* 1808 * Receiver's been idle for another second. 1809 */ 1810 sc->rx_idle_secs++; 1811 } 1812 ifp->if_ierrors += 1813 le32toh(sp->rx_crc_errors) + 1814 le32toh(sp->rx_alignment_errors) + 1815 le32toh(sp->rx_rnr_errors) + 1816 le32toh(sp->rx_overrun_errors); 1817 /* 1818 * If any transmit underruns occured, bump up the transmit 1819 * threshold by another 512 bytes (64 * 8). 1820 */ 1821 if (sp->tx_underruns) { 1822 ifp->if_oerrors += le32toh(sp->tx_underruns); 1823 if (tx_threshold < 192) 1824 tx_threshold += 64; 1825 } 1826 1827 /* 1828 * Release any xmit buffers that have completed DMA. This isn't 1829 * strictly necessary to do here, but it's advantagous for mbufs 1830 * with external storage to be released in a timely manner rather 1831 * than being defered for a potentially long time. This limits 1832 * the delay to a maximum of one second. 1833 */ 1834 fxp_txeof(sc); 1835 1836 /* 1837 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1838 * then assume the receiver has locked up and attempt to clear 1839 * the condition by reprogramming the multicast filter. This is 1840 * a work-around for a bug in the 82557 where the receiver locks 1841 * up if it gets certain types of garbage in the syncronization 1842 * bits prior to the packet header. This bug is supposed to only 1843 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1844 * mode as well (perhaps due to a 10/100 speed transition). 1845 */ 1846 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1847 sc->rx_idle_secs = 0; 1848 fxp_mc_setup(sc); 1849 } 1850 /* 1851 * If there is no pending command, start another stats 1852 * dump. Otherwise punt for now. 1853 */ 1854 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1855 /* 1856 * Start another stats dump. 1857 */ 1858 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1859 BUS_DMASYNC_PREREAD); 1860 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1861 } else { 1862 /* 1863 * A previous command is still waiting to be accepted. 1864 * Just zero our copy of the stats and wait for the 1865 * next timer event to update them. 1866 */ 1867 sp->tx_good = 0; 1868 sp->tx_underruns = 0; 1869 sp->tx_total_collisions = 0; 1870 1871 sp->rx_good = 0; 1872 sp->rx_crc_errors = 0; 1873 sp->rx_alignment_errors = 0; 1874 sp->rx_rnr_errors = 0; 1875 sp->rx_overrun_errors = 0; 1876 } 1877 if (sc->miibus != NULL) 1878 mii_tick(device_get_softc(sc->miibus)); 1879 1880 /* 1881 * Schedule another timeout one second from now. 1882 */ 1883 sc->stat_ch = timeout(fxp_tick, sc, hz); 1884 FXP_UNLOCK(sc); 1885 splx(s); 1886} 1887 1888/* 1889 * Stop the interface. Cancels the statistics updater and resets 1890 * the interface. 1891 */ 1892static void 1893fxp_stop(struct fxp_softc *sc) 1894{ 1895 struct ifnet *ifp = &sc->sc_if; 1896 struct fxp_tx *txp; 1897 int i; 1898 1899 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1900 ifp->if_timer = 0; 1901 1902#ifdef DEVICE_POLLING 1903 ether_poll_deregister(ifp); 1904#endif 1905 /* 1906 * Cancel stats updater. 1907 */ 1908 untimeout(fxp_tick, sc, sc->stat_ch); 1909 1910 /* 1911 * Issue software reset, which also unloads the microcode. 1912 */ 1913 sc->flags &= ~FXP_FLAG_UCODE; 1914 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1915 DELAY(50); 1916 1917 /* 1918 * Release any xmit buffers. 1919 */ 1920 txp = sc->fxp_desc.tx_list; 1921 if (txp != NULL) { 1922 for (i = 0; i < FXP_NTXCB; i++) { 1923 if (txp[i].tx_mbuf != NULL) { 1924 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1925 BUS_DMASYNC_POSTWRITE); 1926 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1927 m_freem(txp[i].tx_mbuf); 1928 txp[i].tx_mbuf = NULL; 1929 /* clear this to reset csum offload bits */ 1930 txp[i].tx_cb->tbd[0].tb_addr = 0; 1931 } 1932 } 1933 } 1934 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1935 sc->tx_queued = 0; 1936} 1937 1938/* 1939 * Watchdog/transmission transmit timeout handler. Called when a 1940 * transmission is started on the interface, but no interrupt is 1941 * received before the timeout. This usually indicates that the 1942 * card has wedged for some reason. 1943 */ 1944static void 1945fxp_watchdog(struct ifnet *ifp) 1946{ 1947 struct fxp_softc *sc = ifp->if_softc; 1948 1949 FXP_LOCK(sc); 1950 device_printf(sc->dev, "device timeout\n"); 1951 ifp->if_oerrors++; 1952 1953 fxp_init_body(sc); 1954 FXP_UNLOCK(sc); 1955} 1956 1957/* 1958 * Acquire locks and then call the real initialization function. This 1959 * is necessary because ether_ioctl() calls if_init() and this would 1960 * result in mutex recursion if the mutex was held. 1961 */ 1962static void 1963fxp_init(void *xsc) 1964{ 1965 struct fxp_softc *sc = xsc; 1966 1967 FXP_LOCK(sc); 1968 fxp_init_body(sc); 1969 FXP_UNLOCK(sc); 1970} 1971 1972/* 1973 * Perform device initialization. This routine must be called with the 1974 * softc lock held. 1975 */ 1976static void 1977fxp_init_body(struct fxp_softc *sc) 1978{ 1979 struct ifnet *ifp = &sc->sc_if; 1980 struct fxp_cb_config *cbp; 1981 struct fxp_cb_ias *cb_ias; 1982 struct fxp_cb_tx *tcbp; 1983 struct fxp_tx *txp; 1984 struct fxp_cb_mcs *mcsp; 1985 int i, prm, s; 1986 1987 mtx_assert(&sc->sc_mtx, MA_OWNED); 1988 s = splimp(); 1989 /* 1990 * Cancel any pending I/O 1991 */ 1992 fxp_stop(sc); 1993 1994 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1995 1996 /* 1997 * Initialize base of CBL and RFA memory. Loading with zero 1998 * sets it up for regular linear addressing. 1999 */ 2000 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2001 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2002 2003 fxp_scb_wait(sc); 2004 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2005 2006 /* 2007 * Initialize base of dump-stats buffer. 2008 */ 2009 fxp_scb_wait(sc); 2010 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2011 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2012 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2013 2014 /* 2015 * Attempt to load microcode if requested. 2016 */ 2017 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2018 fxp_load_ucode(sc); 2019 2020 /* 2021 * Initialize the multicast address list. 2022 */ 2023 if (fxp_mc_addrs(sc)) { 2024 mcsp = sc->mcsp; 2025 mcsp->cb_status = 0; 2026 mcsp->cb_command = 2027 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2028 mcsp->link_addr = 0xffffffff; 2029 /* 2030 * Start the multicast setup command. 2031 */ 2032 fxp_scb_wait(sc); 2033 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2034 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2035 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2036 /* ...and wait for it to complete. */ 2037 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2038 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2039 BUS_DMASYNC_POSTWRITE); 2040 } 2041 2042 /* 2043 * We temporarily use memory that contains the TxCB list to 2044 * construct the config CB. The TxCB list memory is rebuilt 2045 * later. 2046 */ 2047 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2048 2049 /* 2050 * This bcopy is kind of disgusting, but there are a bunch of must be 2051 * zero and must be one bits in this structure and this is the easiest 2052 * way to initialize them all to proper values. 2053 */ 2054 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2055 2056 cbp->cb_status = 0; 2057 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2058 FXP_CB_COMMAND_EL); 2059 cbp->link_addr = 0xffffffff; /* (no) next command */ 2060 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2061 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2062 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2063 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2064 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2065 cbp->type_enable = 0; /* actually reserved */ 2066 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2067 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2068 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2069 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2070 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2071 cbp->late_scb = 0; /* (don't) defer SCB update */ 2072 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2073 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2074 cbp->ci_int = 1; /* interrupt on CU idle */ 2075 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2076 cbp->ext_stats_dis = 1; /* disable extended counters */ 2077 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2078 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2079 cbp->disc_short_rx = !prm; /* discard short packets */ 2080 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2081 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2082 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2083 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2084 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2085 cbp->csma_dis = 0; /* (don't) disable link */ 2086 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2087 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2088 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2089 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2090 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2091 cbp->nsai = 1; /* (don't) disable source addr insert */ 2092 cbp->preamble_length = 2; /* (7 byte) preamble */ 2093 cbp->loopback = 0; /* (don't) loopback */ 2094 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2095 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2096 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2097 cbp->promiscuous = prm; /* promiscuous mode */ 2098 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2099 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2100 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2101 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2102 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2103 2104 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2105 cbp->padding = 1; /* (do) pad short tx packets */ 2106 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2107 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2108 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2109 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2110 /* must set wake_en in PMCSR also */ 2111 cbp->force_fdx = 0; /* (don't) force full duplex */ 2112 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2113 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2114 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2115 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2116 2117 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2118 /* 2119 * The 82557 has no hardware flow control, the values 2120 * below are the defaults for the chip. 2121 */ 2122 cbp->fc_delay_lsb = 0; 2123 cbp->fc_delay_msb = 0x40; 2124 cbp->pri_fc_thresh = 3; 2125 cbp->tx_fc_dis = 0; 2126 cbp->rx_fc_restop = 0; 2127 cbp->rx_fc_restart = 0; 2128 cbp->fc_filter = 0; 2129 cbp->pri_fc_loc = 1; 2130 } else { 2131 cbp->fc_delay_lsb = 0x1f; 2132 cbp->fc_delay_msb = 0x01; 2133 cbp->pri_fc_thresh = 3; 2134 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2135 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2136 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2137 cbp->fc_filter = !prm; /* drop FC frames to host */ 2138 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2139 } 2140 2141 /* 2142 * Start the config command/DMA. 2143 */ 2144 fxp_scb_wait(sc); 2145 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2146 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2148 /* ...and wait for it to complete. */ 2149 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2150 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2151 2152 /* 2153 * Now initialize the station address. Temporarily use the TxCB 2154 * memory area like we did above for the config CB. 2155 */ 2156 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2157 cb_ias->cb_status = 0; 2158 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2159 cb_ias->link_addr = 0xffffffff; 2160 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2161 sizeof(sc->arpcom.ac_enaddr)); 2162 2163 /* 2164 * Start the IAS (Individual Address Setup) command/DMA. 2165 */ 2166 fxp_scb_wait(sc); 2167 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2168 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2169 /* ...and wait for it to complete. */ 2170 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2171 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2172 2173 /* 2174 * Initialize transmit control block (TxCB) list. 2175 */ 2176 txp = sc->fxp_desc.tx_list; 2177 tcbp = sc->fxp_desc.cbl_list; 2178 bzero(tcbp, FXP_TXCB_SZ); 2179 for (i = 0; i < FXP_NTXCB; i++) { 2180 txp[i].tx_cb = tcbp + i; 2181 txp[i].tx_mbuf = NULL; 2182 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2183 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2184 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2185 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2186 if (sc->flags & FXP_FLAG_EXT_TXCB) 2187 tcbp[i].tbd_array_addr = 2188 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2189 else 2190 tcbp[i].tbd_array_addr = 2191 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2192 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2193 } 2194 /* 2195 * Set the suspend flag on the first TxCB and start the control 2196 * unit. It will execute the NOP and then suspend. 2197 */ 2198 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2199 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2200 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2201 sc->tx_queued = 1; 2202 2203 fxp_scb_wait(sc); 2204 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2205 2206 /* 2207 * Initialize receiver buffer area - RFA. 2208 */ 2209 fxp_scb_wait(sc); 2210 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2211 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2212 2213 /* 2214 * Set current media. 2215 */ 2216 if (sc->miibus != NULL) 2217 mii_mediachg(device_get_softc(sc->miibus)); 2218 2219 ifp->if_flags |= IFF_RUNNING; 2220 ifp->if_flags &= ~IFF_OACTIVE; 2221 2222 /* 2223 * Enable interrupts. 2224 */ 2225#ifdef DEVICE_POLLING 2226 /* 2227 * ... but only do that if we are not polling. And because (presumably) 2228 * the default is interrupts on, we need to disable them explicitly! 2229 */ 2230 if ( ifp->if_flags & IFF_POLLING ) 2231 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2232 else 2233#endif /* DEVICE_POLLING */ 2234 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2235 2236 /* 2237 * Start stats updater. 2238 */ 2239 sc->stat_ch = timeout(fxp_tick, sc, hz); 2240 splx(s); 2241} 2242 2243static int 2244fxp_serial_ifmedia_upd(struct ifnet *ifp) 2245{ 2246 2247 return (0); 2248} 2249 2250static void 2251fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2252{ 2253 2254 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2255} 2256 2257/* 2258 * Change media according to request. 2259 */ 2260static int 2261fxp_ifmedia_upd(struct ifnet *ifp) 2262{ 2263 struct fxp_softc *sc = ifp->if_softc; 2264 struct mii_data *mii; 2265 2266 mii = device_get_softc(sc->miibus); 2267 mii_mediachg(mii); 2268 return (0); 2269} 2270 2271/* 2272 * Notify the world which media we're using. 2273 */ 2274static void 2275fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2276{ 2277 struct fxp_softc *sc = ifp->if_softc; 2278 struct mii_data *mii; 2279 2280 mii = device_get_softc(sc->miibus); 2281 mii_pollstat(mii); 2282 ifmr->ifm_active = mii->mii_media_active; 2283 ifmr->ifm_status = mii->mii_media_status; 2284 2285 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2286 sc->cu_resume_bug = 1; 2287 else 2288 sc->cu_resume_bug = 0; 2289} 2290 2291/* 2292 * Add a buffer to the end of the RFA buffer list. 2293 * Return 0 if successful, 1 for failure. A failure results in 2294 * adding the 'oldm' (if non-NULL) on to the end of the list - 2295 * tossing out its old contents and recycling it. 2296 * The RFA struct is stuck at the beginning of mbuf cluster and the 2297 * data pointer is fixed up to point just past it. 2298 */ 2299static int 2300fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2301{ 2302 struct mbuf *m; 2303 struct fxp_rfa *rfa, *p_rfa; 2304 struct fxp_rx *p_rx; 2305 bus_dmamap_t tmp_map; 2306 int error; 2307 2308 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2309 if (m == NULL) 2310 return (ENOBUFS); 2311 2312 /* 2313 * Move the data pointer up so that the incoming data packet 2314 * will be 32-bit aligned. 2315 */ 2316 m->m_data += RFA_ALIGNMENT_FUDGE; 2317 2318 /* 2319 * Get a pointer to the base of the mbuf cluster and move 2320 * data start past it. 2321 */ 2322 rfa = mtod(m, struct fxp_rfa *); 2323 m->m_data += sc->rfa_size; 2324 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2325 2326 rfa->rfa_status = 0; 2327 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2328 rfa->actual_size = 0; 2329 2330 /* 2331 * Initialize the rest of the RFA. Note that since the RFA 2332 * is misaligned, we cannot store values directly. We're thus 2333 * using the le32enc() function which handles endianness and 2334 * is also alignment-safe. 2335 */ 2336 le32enc(&rfa->link_addr, 0xffffffff); 2337 le32enc(&rfa->rbd_addr, 0xffffffff); 2338 2339 /* Map the RFA into DMA memory. */ 2340 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2341 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2342 &rxp->rx_addr, 0); 2343 if (error) { 2344 m_freem(m); 2345 return (error); 2346 } 2347 2348 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2349 tmp_map = sc->spare_map; 2350 sc->spare_map = rxp->rx_map; 2351 rxp->rx_map = tmp_map; 2352 rxp->rx_mbuf = m; 2353 2354 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2356 2357 /* 2358 * If there are other buffers already on the list, attach this 2359 * one to the end by fixing up the tail to point to this one. 2360 */ 2361 if (sc->fxp_desc.rx_head != NULL) { 2362 p_rx = sc->fxp_desc.rx_tail; 2363 p_rfa = (struct fxp_rfa *) 2364 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2365 p_rx->rx_next = rxp; 2366 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2367 p_rfa->rfa_control = 0; 2368 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2369 BUS_DMASYNC_PREWRITE); 2370 } else { 2371 rxp->rx_next = NULL; 2372 sc->fxp_desc.rx_head = rxp; 2373 } 2374 sc->fxp_desc.rx_tail = rxp; 2375 return (0); 2376} 2377 2378static volatile int 2379fxp_miibus_readreg(device_t dev, int phy, int reg) 2380{ 2381 struct fxp_softc *sc = device_get_softc(dev); 2382 int count = 10000; 2383 int value; 2384 2385 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2386 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2387 2388 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2389 && count--) 2390 DELAY(10); 2391 2392 if (count <= 0) 2393 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2394 2395 return (value & 0xffff); 2396} 2397 2398static void 2399fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2400{ 2401 struct fxp_softc *sc = device_get_softc(dev); 2402 int count = 10000; 2403 2404 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2405 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2406 (value & 0xffff)); 2407 2408 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2409 count--) 2410 DELAY(10); 2411 2412 if (count <= 0) 2413 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2414} 2415 2416static int 2417fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2418{ 2419 struct fxp_softc *sc = ifp->if_softc; 2420 struct ifreq *ifr = (struct ifreq *)data; 2421 struct mii_data *mii; 2422 int s, error = 0; 2423 2424 /* 2425 * Detaching causes us to call ioctl with the mutex owned. Preclude 2426 * that by saying we're busy if the lock is already held. 2427 */ 2428 if (mtx_owned(&sc->sc_mtx)) 2429 return (EBUSY); 2430 2431 FXP_LOCK(sc); 2432 s = splimp(); 2433 2434 switch (command) { 2435 case SIOCSIFFLAGS: 2436 if (ifp->if_flags & IFF_ALLMULTI) 2437 sc->flags |= FXP_FLAG_ALL_MCAST; 2438 else 2439 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2440 2441 /* 2442 * If interface is marked up and not running, then start it. 2443 * If it is marked down and running, stop it. 2444 * XXX If it's up then re-initialize it. This is so flags 2445 * such as IFF_PROMISC are handled. 2446 */ 2447 if (ifp->if_flags & IFF_UP) { 2448 fxp_init_body(sc); 2449 } else { 2450 if (ifp->if_flags & IFF_RUNNING) 2451 fxp_stop(sc); 2452 } 2453 break; 2454 2455 case SIOCADDMULTI: 2456 case SIOCDELMULTI: 2457 if (ifp->if_flags & IFF_ALLMULTI) 2458 sc->flags |= FXP_FLAG_ALL_MCAST; 2459 else 2460 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2461 /* 2462 * Multicast list has changed; set the hardware filter 2463 * accordingly. 2464 */ 2465 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2466 fxp_mc_setup(sc); 2467 /* 2468 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2469 * again rather than else {}. 2470 */ 2471 if (sc->flags & FXP_FLAG_ALL_MCAST) 2472 fxp_init_body(sc); 2473 error = 0; 2474 break; 2475 2476 case SIOCSIFMEDIA: 2477 case SIOCGIFMEDIA: 2478 if (sc->miibus != NULL) { 2479 mii = device_get_softc(sc->miibus); 2480 error = ifmedia_ioctl(ifp, ifr, 2481 &mii->mii_media, command); 2482 } else { 2483 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2484 } 2485 break; 2486 2487 default: 2488 /* 2489 * ether_ioctl() will eventually call fxp_start() which 2490 * will result in mutex recursion so drop it first. 2491 */ 2492 FXP_UNLOCK(sc); 2493 error = ether_ioctl(ifp, command, data); 2494 } 2495 if (mtx_owned(&sc->sc_mtx)) 2496 FXP_UNLOCK(sc); 2497 splx(s); 2498 return (error); 2499} 2500 2501/* 2502 * Fill in the multicast address list and return number of entries. 2503 */ 2504static int 2505fxp_mc_addrs(struct fxp_softc *sc) 2506{ 2507 struct fxp_cb_mcs *mcsp = sc->mcsp; 2508 struct ifnet *ifp = &sc->sc_if; 2509 struct ifmultiaddr *ifma; 2510 int nmcasts; 2511 2512 nmcasts = 0; 2513 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2514#if __FreeBSD_version < 500000 2515 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2516#else 2517 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2518#endif 2519 if (ifma->ifma_addr->sa_family != AF_LINK) 2520 continue; 2521 if (nmcasts >= MAXMCADDR) { 2522 sc->flags |= FXP_FLAG_ALL_MCAST; 2523 nmcasts = 0; 2524 break; 2525 } 2526 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2527 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2528 nmcasts++; 2529 } 2530 } 2531 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2532 return (nmcasts); 2533} 2534 2535/* 2536 * Program the multicast filter. 2537 * 2538 * We have an artificial restriction that the multicast setup command 2539 * must be the first command in the chain, so we take steps to ensure 2540 * this. By requiring this, it allows us to keep up the performance of 2541 * the pre-initialized command ring (esp. link pointers) by not actually 2542 * inserting the mcsetup command in the ring - i.e. its link pointer 2543 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2544 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2545 * lead into the regular TxCB ring when it completes. 2546 * 2547 * This function must be called at splimp. 2548 */ 2549static void 2550fxp_mc_setup(struct fxp_softc *sc) 2551{ 2552 struct fxp_cb_mcs *mcsp = sc->mcsp; 2553 struct ifnet *ifp = &sc->sc_if; 2554 struct fxp_tx *txp; 2555 int count; 2556 2557 /* 2558 * If there are queued commands, we must wait until they are all 2559 * completed. If we are already waiting, then add a NOP command 2560 * with interrupt option so that we're notified when all commands 2561 * have been completed - fxp_start() ensures that no additional 2562 * TX commands will be added when need_mcsetup is true. 2563 */ 2564 if (sc->tx_queued) { 2565 /* 2566 * need_mcsetup will be true if we are already waiting for the 2567 * NOP command to be completed (see below). In this case, bail. 2568 */ 2569 if (sc->need_mcsetup) 2570 return; 2571 sc->need_mcsetup = 1; 2572 2573 /* 2574 * Add a NOP command with interrupt so that we are notified 2575 * when all TX commands have been processed. 2576 */ 2577 txp = sc->fxp_desc.tx_last->tx_next; 2578 txp->tx_mbuf = NULL; 2579 txp->tx_cb->cb_status = 0; 2580 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2581 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2582 /* 2583 * Advance the end of list forward. 2584 */ 2585 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2586 htole16(~FXP_CB_COMMAND_S); 2587 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2588 sc->fxp_desc.tx_last = txp; 2589 sc->tx_queued++; 2590 /* 2591 * Issue a resume in case the CU has just suspended. 2592 */ 2593 fxp_scb_wait(sc); 2594 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2595 /* 2596 * Set a 5 second timer just in case we don't hear from the 2597 * card again. 2598 */ 2599 ifp->if_timer = 5; 2600 2601 return; 2602 } 2603 sc->need_mcsetup = 0; 2604 2605 /* 2606 * Initialize multicast setup descriptor. 2607 */ 2608 mcsp->cb_status = 0; 2609 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2610 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2611 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2612 txp = &sc->fxp_desc.mcs_tx; 2613 txp->tx_mbuf = NULL; 2614 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2615 txp->tx_next = sc->fxp_desc.tx_list; 2616 (void) fxp_mc_addrs(sc); 2617 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2618 sc->tx_queued = 1; 2619 2620 /* 2621 * Wait until command unit is not active. This should never 2622 * be the case when nothing is queued, but make sure anyway. 2623 */ 2624 count = 100; 2625 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2626 FXP_SCB_CUS_ACTIVE && --count) 2627 DELAY(10); 2628 if (count == 0) { 2629 device_printf(sc->dev, "command queue timeout\n"); 2630 return; 2631 } 2632 2633 /* 2634 * Start the multicast setup command. 2635 */ 2636 fxp_scb_wait(sc); 2637 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2638 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2639 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2640 2641 ifp->if_timer = 2; 2642 return; 2643} 2644 2645static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2646static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2647static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2648static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2649static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2650static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2651 2652#define UCODE(x) x, sizeof(x) 2653 2654struct ucode { 2655 u_int32_t revision; 2656 u_int32_t *ucode; 2657 int length; 2658 u_short int_delay_offset; 2659 u_short bundle_max_offset; 2660} ucode_table[] = { 2661 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2662 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2663 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2664 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2665 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2666 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2667 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2668 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2669 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2670 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2671 { 0, NULL, 0, 0, 0 } 2672}; 2673 2674static void 2675fxp_load_ucode(struct fxp_softc *sc) 2676{ 2677 struct ucode *uc; 2678 struct fxp_cb_ucode *cbp; 2679 2680 for (uc = ucode_table; uc->ucode != NULL; uc++) 2681 if (sc->revision == uc->revision) 2682 break; 2683 if (uc->ucode == NULL) 2684 return; 2685 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2686 cbp->cb_status = 0; 2687 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2688 cbp->link_addr = 0xffffffff; /* (no) next command */ 2689 memcpy(cbp->ucode, uc->ucode, uc->length); 2690 if (uc->int_delay_offset) 2691 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2692 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2693 if (uc->bundle_max_offset) 2694 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2695 htole16(sc->tunable_bundle_max); 2696 /* 2697 * Download the ucode to the chip. 2698 */ 2699 fxp_scb_wait(sc); 2700 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2701 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2702 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2703 /* ...and wait for it to complete. */ 2704 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2705 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2706 device_printf(sc->dev, 2707 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2708 sc->tunable_int_delay, 2709 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2710 sc->flags |= FXP_FLAG_UCODE; 2711} 2712 2713static int 2714sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2715{ 2716 int error, value; 2717 2718 value = *(int *)arg1; 2719 error = sysctl_handle_int(oidp, &value, 0, req); 2720 if (error || !req->newptr) 2721 return (error); 2722 if (value < low || value > high) 2723 return (EINVAL); 2724 *(int *)arg1 = value; 2725 return (0); 2726} 2727 2728/* 2729 * Interrupt delay is expressed in microseconds, a multiplier is used 2730 * to convert this to the appropriate clock ticks before using. 2731 */ 2732static int 2733sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2734{ 2735 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2736} 2737 2738static int 2739sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2740{ 2741 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2742} 2743