if_fxp.c revision 118084
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30/* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 118084 2003-07-27 14:00:02Z mux $"); 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49 50#include <net/bpf.h> 51#include <sys/sockio.h> 52#include <sys/bus.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if_arp.h> 59 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <pci/pcivar.h> 73#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, pci, 1, 1, 1); 83MODULE_DEPEND(fxp, ether, 1, 1, 1); 84MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85#include "miibus_if.h" 86 87/* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96#define RFA_ALIGNMENT_FUDGE 2 97 98/* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103static int tx_threshold = 64; 104 105/* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139}; 140 141struct fxp_ident { 142 u_int16_t devid; 143 char *name; 144}; 145 146/* 147 * Claim various Intel PCI device identifiers for this driver. The 148 * sub-vendor and sub-device field are extensively used to identify 149 * particular variants, but we don't currently differentiate between 150 * them. 151 */ 152static struct fxp_ident fxp_ident_table[] = { 153 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 154 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 155 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 164 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x1050, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 170 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 171 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 172 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 173 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 174 { 0, NULL }, 175}; 176 177#ifdef FXP_IP_CSUM_WAR 178#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 179#else 180#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 181#endif 182 183static int fxp_probe(device_t dev); 184static int fxp_attach(device_t dev); 185static int fxp_detach(device_t dev); 186static int fxp_shutdown(device_t dev); 187static int fxp_suspend(device_t dev); 188static int fxp_resume(device_t dev); 189 190static void fxp_intr(void *xsc); 191static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 192 u_int8_t statack, int count); 193static void fxp_init(void *xsc); 194static void fxp_init_body(struct fxp_softc *sc); 195static void fxp_tick(void *xsc); 196#ifndef BURN_BRIDGES 197static void fxp_powerstate_d0(device_t dev); 198#endif 199static void fxp_start(struct ifnet *ifp); 200static void fxp_start_body(struct ifnet *ifp); 201static void fxp_stop(struct fxp_softc *sc); 202static void fxp_release(struct fxp_softc *sc); 203static int fxp_ioctl(struct ifnet *ifp, u_long command, 204 caddr_t data); 205static void fxp_watchdog(struct ifnet *ifp); 206static int fxp_add_rfabuf(struct fxp_softc *sc, 207 struct fxp_rx *rxp); 208static int fxp_mc_addrs(struct fxp_softc *sc); 209static void fxp_mc_setup(struct fxp_softc *sc); 210static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 211 int autosize); 212static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 213 u_int16_t data); 214static void fxp_autosize_eeprom(struct fxp_softc *sc); 215static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 216 int offset, int words); 217static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 218 int offset, int words); 219static int fxp_ifmedia_upd(struct ifnet *ifp); 220static void fxp_ifmedia_sts(struct ifnet *ifp, 221 struct ifmediareq *ifmr); 222static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 223static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 224 struct ifmediareq *ifmr); 225static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 226static void fxp_miibus_writereg(device_t dev, int phy, int reg, 227 int value); 228static void fxp_load_ucode(struct fxp_softc *sc); 229static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 230 int low, int high); 231static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 232static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 233static void fxp_scb_wait(struct fxp_softc *sc); 234static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 235static void fxp_dma_wait(struct fxp_softc *sc, 236 volatile u_int16_t *status, bus_dma_tag_t dmat, 237 bus_dmamap_t map); 238 239static device_method_t fxp_methods[] = { 240 /* Device interface */ 241 DEVMETHOD(device_probe, fxp_probe), 242 DEVMETHOD(device_attach, fxp_attach), 243 DEVMETHOD(device_detach, fxp_detach), 244 DEVMETHOD(device_shutdown, fxp_shutdown), 245 DEVMETHOD(device_suspend, fxp_suspend), 246 DEVMETHOD(device_resume, fxp_resume), 247 248 /* MII interface */ 249 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 250 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 251 252 { 0, 0 } 253}; 254 255static driver_t fxp_driver = { 256 "fxp", 257 fxp_methods, 258 sizeof(struct fxp_softc), 259}; 260 261static devclass_t fxp_devclass; 262 263DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 264DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 265DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 266 267static int fxp_rnr; 268SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 269 270static int fxp_noflow; 271SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 272TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 273 274/* 275 * Wait for the previous command to be accepted (but not necessarily 276 * completed). 277 */ 278static void 279fxp_scb_wait(struct fxp_softc *sc) 280{ 281 int i = 10000; 282 283 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 284 DELAY(2); 285 if (i == 0) 286 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 287 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 288 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 289 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 290 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 291} 292 293static void 294fxp_scb_cmd(struct fxp_softc *sc, int cmd) 295{ 296 297 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 298 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 299 fxp_scb_wait(sc); 300 } 301 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 302} 303 304static void 305fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 306 bus_dma_tag_t dmat, bus_dmamap_t map) 307{ 308 int i = 10000; 309 310 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 311 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 312 DELAY(2); 313 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 314 } 315 if (i == 0) 316 device_printf(sc->dev, "DMA timeout\n"); 317} 318 319/* 320 * Return identification string if this device is ours. 321 */ 322static int 323fxp_probe(device_t dev) 324{ 325 u_int16_t devid; 326 struct fxp_ident *ident; 327 328 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 329 devid = pci_get_device(dev); 330 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 331 if (ident->devid == devid) { 332 device_set_desc(dev, ident->name); 333 return (0); 334 } 335 } 336 } 337 return (ENXIO); 338} 339 340#ifndef BURN_BRIDGES 341static void 342fxp_powerstate_d0(device_t dev) 343{ 344#if __FreeBSD_version >= 430002 345 u_int32_t iobase, membase, irq; 346 347 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 348 /* Save important PCI config data. */ 349 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 350 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 351 irq = pci_read_config(dev, PCIR_INTLINE, 4); 352 353 /* Reset the power state. */ 354 device_printf(dev, "chip is in D%d power mode " 355 "-- setting to D0\n", pci_get_powerstate(dev)); 356 357 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 358 359 /* Restore PCI config data. */ 360 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 361 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 362 pci_write_config(dev, PCIR_INTLINE, irq, 4); 363 } 364#endif 365} 366#endif 367 368static void 369fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 370{ 371 u_int32_t *addr; 372 373 if (error) 374 return; 375 376 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 377 addr = arg; 378 *addr = segs->ds_addr; 379} 380 381static int 382fxp_attach(device_t dev) 383{ 384 int error = 0; 385 struct fxp_softc *sc = device_get_softc(dev); 386 struct ifnet *ifp; 387 struct fxp_rx *rxp; 388 u_int32_t val; 389 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 390 int i, rid, m1, m2, prefer_iomap, maxtxseg; 391 int s, ipcbxmit_disable; 392 393 sc->dev = dev; 394 callout_handle_init(&sc->stat_ch); 395 sysctl_ctx_init(&sc->sysctl_ctx); 396 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 397 MTX_DEF); 398 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 399 fxp_serial_ifmedia_sts); 400 401 s = splimp(); 402 403 /* 404 * Enable bus mastering. 405 */ 406 pci_enable_busmaster(dev); 407 val = pci_read_config(dev, PCIR_COMMAND, 2); 408#ifndef BURN_BRIDGES 409 fxp_powerstate_d0(dev); 410#endif 411 /* 412 * Figure out which we should try first - memory mapping or i/o mapping? 413 * We default to memory mapping. Then we accept an override from the 414 * command line. Then we check to see which one is enabled. 415 */ 416 m1 = PCIM_CMD_MEMEN; 417 m2 = PCIM_CMD_PORTEN; 418 prefer_iomap = 0; 419 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 420 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 421 m1 = PCIM_CMD_PORTEN; 422 m2 = PCIM_CMD_MEMEN; 423 } 424 425 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 426 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 427 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 428 0, ~0, 1, RF_ACTIVE); 429 if (sc->mem == NULL) { 430 sc->rtp = 431 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 432 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 433 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 434 0, ~0, 1, RF_ACTIVE); 435 } 436 437 if (!sc->mem) { 438 error = ENXIO; 439 goto fail; 440 } 441 if (bootverbose) { 442 device_printf(dev, "using %s space register mapping\n", 443 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 444 } 445 446 sc->sc_st = rman_get_bustag(sc->mem); 447 sc->sc_sh = rman_get_bushandle(sc->mem); 448 449 /* 450 * Allocate our interrupt. 451 */ 452 rid = 0; 453 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 454 RF_SHAREABLE | RF_ACTIVE); 455 if (sc->irq == NULL) { 456 device_printf(dev, "could not map interrupt\n"); 457 error = ENXIO; 458 goto fail; 459 } 460 461 /* 462 * Reset to a stable state. 463 */ 464 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 465 DELAY(10); 466 467 /* 468 * Find out how large of an SEEPROM we have. 469 */ 470 fxp_autosize_eeprom(sc); 471 472 /* 473 * Determine whether we must use the 503 serial interface. 474 */ 475 fxp_read_eeprom(sc, &data, 6, 1); 476 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 477 (data & FXP_PHY_SERIAL_ONLY)) 478 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 479 480 /* 481 * Create the sysctl tree 482 */ 483 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 484 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 485 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 486 if (sc->sysctl_tree == NULL) { 487 error = ENXIO; 488 goto fail; 489 } 490 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 491 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 492 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 493 "FXP driver receive interrupt microcode bundling delay"); 494 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 495 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 496 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 497 "FXP driver receive interrupt microcode bundle size limit"); 498 499 /* 500 * Pull in device tunables. 501 */ 502 sc->tunable_int_delay = TUNABLE_INT_DELAY; 503 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 504 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 505 "int_delay", &sc->tunable_int_delay); 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "bundle_max", &sc->tunable_bundle_max); 508 509 /* 510 * Find out the chip revision; lump all 82557 revs together. 511 */ 512 fxp_read_eeprom(sc, &data, 5, 1); 513 if ((data >> 8) == 1) 514 sc->revision = FXP_REV_82557; 515 else 516 sc->revision = pci_get_revid(dev); 517 518 /* 519 * Enable workarounds for certain chip revision deficiencies. 520 * 521 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 522 * some systems based a normal 82559 design, have a defect where 523 * the chip can cause a PCI protocol violation if it receives 524 * a CU_RESUME command when it is entering the IDLE state. The 525 * workaround is to disable Dynamic Standby Mode, so the chip never 526 * deasserts CLKRUN#, and always remains in an active state. 527 * 528 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 529 */ 530 i = pci_get_device(dev); 531 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 532 sc->revision >= FXP_REV_82559_A0) { 533 fxp_read_eeprom(sc, &data, 10, 1); 534 if (data & 0x02) { /* STB enable */ 535 u_int16_t cksum; 536 int i; 537 538 device_printf(dev, 539 "Disabling dynamic standby mode in EEPROM\n"); 540 data &= ~0x02; 541 fxp_write_eeprom(sc, &data, 10, 1); 542 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 543 cksum = 0; 544 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 545 fxp_read_eeprom(sc, &data, i, 1); 546 cksum += data; 547 } 548 i = (1 << sc->eeprom_size) - 1; 549 cksum = 0xBABA - cksum; 550 fxp_read_eeprom(sc, &data, i, 1); 551 fxp_write_eeprom(sc, &cksum, i, 1); 552 device_printf(dev, 553 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 554 i, data, cksum); 555#if 1 556 /* 557 * If the user elects to continue, try the software 558 * workaround, as it is better than nothing. 559 */ 560 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 561#endif 562 } 563 } 564 565 /* 566 * If we are not a 82557 chip, we can enable extended features. 567 */ 568 if (sc->revision != FXP_REV_82557) { 569 /* 570 * If MWI is enabled in the PCI configuration, and there 571 * is a valid cacheline size (8 or 16 dwords), then tell 572 * the board to turn on MWI. 573 */ 574 if (val & PCIM_CMD_MWRICEN && 575 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 576 sc->flags |= FXP_FLAG_MWI_ENABLE; 577 578 /* turn on the extended TxCB feature */ 579 sc->flags |= FXP_FLAG_EXT_TXCB; 580 581 /* enable reception of long frames for VLAN */ 582 sc->flags |= FXP_FLAG_LONG_PKT_EN; 583 } 584 585 /* 586 * Enable use of extended RFDs and TCBs for 82550 587 * and later chips. Note: we need extended TXCB support 588 * too, but that's already enabled by the code above. 589 * Be careful to do this only on the right devices. 590 * 591 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 592 * truncate packets that end with an mbuf containing 1 to 3 bytes 593 * when used with this feature enabled in the previous version of the 594 * driver. This problem appears to be fixed now that the driver 595 * always sets the hardware parse bit in the IPCB structure, which 596 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 597 * Source Software Developer Manual" says is necessary in the 598 * cases where packet truncation was observed. 599 * 600 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 601 * allows this feature to be disabled at boot time. 602 * 603 * If fxp is not compiled into the kernel, this feature may also 604 * be disabled at run time: 605 * # kldunload fxp 606 * # kenv hint.fxp.0.ipcbxmit_disable=1 607 * # kldload fxp 608 */ 609 610 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 611 &ipcbxmit_disable) != 0) 612 ipcbxmit_disable = 0; 613 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 614 sc->revision == FXP_REV_82550_C)) { 615 sc->rfa_size = sizeof (struct fxp_rfa); 616 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 617 sc->flags |= FXP_FLAG_EXT_RFA; 618 } else { 619 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 620 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 621 } 622 623 /* 624 * Allocate DMA tags and DMA safe memory. 625 */ 626 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 627 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 628 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 629 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 630 if (error) { 631 device_printf(dev, "could not allocate dma tag\n"); 632 goto fail; 633 } 634 635 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 636 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 637 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 638 &sc->fxp_stag); 639 if (error) { 640 device_printf(dev, "could not allocate dma tag\n"); 641 goto fail; 642 } 643 644 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 645 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 646 if (error) 647 goto fail; 648 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 649 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 650 if (error) { 651 device_printf(dev, "could not map the stats buffer\n"); 652 goto fail; 653 } 654 655 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 656 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 657 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 658 if (error) { 659 device_printf(dev, "could not allocate dma tag\n"); 660 goto fail; 661 } 662 663 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 664 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 665 if (error) 666 goto fail; 667 668 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 669 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 670 &sc->fxp_desc.cbl_addr, 0); 671 if (error) { 672 device_printf(dev, "could not map DMA memory\n"); 673 goto fail; 674 } 675 676 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 677 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 678 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 679 &sc->mcs_tag); 680 if (error) { 681 device_printf(dev, "could not allocate dma tag\n"); 682 goto fail; 683 } 684 685 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 686 BUS_DMA_NOWAIT, &sc->mcs_map); 687 if (error) 688 goto fail; 689 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 690 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 691 if (error) { 692 device_printf(dev, "can't map the multicast setup command\n"); 693 goto fail; 694 } 695 696 /* 697 * Pre-allocate the TX DMA maps. 698 */ 699 for (i = 0; i < FXP_NTXCB; i++) { 700 error = bus_dmamap_create(sc->fxp_mtag, 0, 701 &sc->fxp_desc.tx_list[i].tx_map); 702 if (error) { 703 device_printf(dev, "can't create DMA map for TX\n"); 704 goto fail; 705 } 706 } 707 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 708 if (error) { 709 device_printf(dev, "can't create spare DMA map\n"); 710 goto fail; 711 } 712 713 /* 714 * Pre-allocate our receive buffers. 715 */ 716 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 717 for (i = 0; i < FXP_NRFABUFS; i++) { 718 rxp = &sc->fxp_desc.rx_list[i]; 719 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for RX\n"); 722 goto fail; 723 } 724 if (fxp_add_rfabuf(sc, rxp) != 0) { 725 error = ENOMEM; 726 goto fail; 727 } 728 } 729 730 /* 731 * Read MAC address. 732 */ 733 fxp_read_eeprom(sc, myea, 0, 3); 734 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 735 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 736 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 737 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 738 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 739 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 740 device_printf(dev, "Ethernet address %6D%s\n", 741 sc->arpcom.ac_enaddr, ":", 742 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 743 if (bootverbose) { 744 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 745 pci_get_vendor(dev), pci_get_device(dev), 746 pci_get_subvendor(dev), pci_get_subdevice(dev), 747 pci_get_revid(dev)); 748 fxp_read_eeprom(sc, &data, 10, 1); 749 device_printf(dev, "Dynamic Standby mode is %s\n", 750 data & 0x02 ? "enabled" : "disabled"); 751 } 752 753 /* 754 * If this is only a 10Mbps device, then there is no MII, and 755 * the PHY will use a serial interface instead. 756 * 757 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 758 * doesn't have a programming interface of any sort. The 759 * media is sensed automatically based on how the link partner 760 * is configured. This is, in essence, manual configuration. 761 */ 762 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 763 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 764 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 765 } else { 766 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 767 fxp_ifmedia_sts)) { 768 device_printf(dev, "MII without any PHY!\n"); 769 error = ENXIO; 770 goto fail; 771 } 772 } 773 774 ifp = &sc->arpcom.ac_if; 775 ifp->if_unit = device_get_unit(dev); 776 ifp->if_name = "fxp"; 777 ifp->if_output = ether_output; 778 ifp->if_baudrate = 100000000; 779 ifp->if_init = fxp_init; 780 ifp->if_softc = sc; 781 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 782 ifp->if_ioctl = fxp_ioctl; 783 ifp->if_start = fxp_start; 784 ifp->if_watchdog = fxp_watchdog; 785 786 /* Enable checksum offload for 82550 or better chips */ 787 if (sc->flags & FXP_FLAG_EXT_RFA) { 788 ifp->if_hwassist = FXP_CSUM_FEATURES; 789 ifp->if_capabilities = IFCAP_HWCSUM; 790 ifp->if_capenable = ifp->if_capabilities; 791 } 792 793 /* 794 * Attach the interface. 795 */ 796 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 797 798 /* 799 * Tell the upper layer(s) we support long frames. 800 */ 801 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 802 ifp->if_capabilities |= IFCAP_VLAN_MTU; 803 804 /* 805 * Let the system queue as many packets as we have available 806 * TX descriptors. 807 */ 808 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 809 810 /* 811 * Hook our interrupt after all initialization is complete. 812 * XXX This driver has been tested with the INTR_MPSAFFE flag set 813 * however, ifp and its functions are not fully locked so MPSAFE 814 * should not be used unless you can handle potential data loss. 815 */ 816 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, 817 fxp_intr, sc, &sc->ih); 818 if (error) { 819 device_printf(dev, "could not setup irq\n"); 820 ether_ifdetach(&sc->arpcom.ac_if); 821 goto fail; 822 } 823 824fail: 825 splx(s); 826 if (error) 827 fxp_release(sc); 828 return (error); 829} 830 831/* 832 * Release all resources. The softc lock should not be held and the 833 * interrupt should already be torn down. 834 */ 835static void 836fxp_release(struct fxp_softc *sc) 837{ 838 struct fxp_rx *rxp; 839 struct fxp_tx *txp; 840 int i; 841 842 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 843 if (sc->ih) 844 panic("fxp_release() called with intr handle still active"); 845 if (sc->miibus) 846 device_delete_child(sc->dev, sc->miibus); 847 bus_generic_detach(sc->dev); 848 ifmedia_removeall(&sc->sc_media); 849 if (sc->fxp_desc.cbl_list) { 850 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 851 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 852 sc->cbl_map); 853 } 854 if (sc->fxp_stats) { 855 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 856 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 857 } 858 if (sc->mcsp) { 859 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 860 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 861 } 862 if (sc->irq) 863 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 864 if (sc->mem) 865 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 866 if (sc->fxp_mtag) { 867 for (i = 0; i < FXP_NRFABUFS; i++) { 868 rxp = &sc->fxp_desc.rx_list[i]; 869 if (rxp->rx_mbuf != NULL) { 870 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 871 BUS_DMASYNC_POSTREAD); 872 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 873 m_freem(rxp->rx_mbuf); 874 } 875 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 876 } 877 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 878 bus_dma_tag_destroy(sc->fxp_mtag); 879 } 880 if (sc->fxp_stag) { 881 for (i = 0; i < FXP_NTXCB; i++) { 882 txp = &sc->fxp_desc.tx_list[i]; 883 if (txp->tx_mbuf != NULL) { 884 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 885 BUS_DMASYNC_POSTWRITE); 886 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 887 m_freem(txp->tx_mbuf); 888 } 889 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 890 } 891 bus_dma_tag_destroy(sc->fxp_stag); 892 } 893 if (sc->cbl_tag) 894 bus_dma_tag_destroy(sc->cbl_tag); 895 if (sc->mcs_tag) 896 bus_dma_tag_destroy(sc->mcs_tag); 897 898 sysctl_ctx_free(&sc->sysctl_ctx); 899 900 mtx_destroy(&sc->sc_mtx); 901} 902 903/* 904 * Detach interface. 905 */ 906static int 907fxp_detach(device_t dev) 908{ 909 struct fxp_softc *sc = device_get_softc(dev); 910 int s; 911 912 FXP_LOCK(sc); 913 s = splimp(); 914 915 sc->suspended = 1; /* Do same thing as we do for suspend */ 916 /* 917 * Close down routes etc. 918 */ 919 ether_ifdetach(&sc->arpcom.ac_if); 920 921 /* 922 * Stop DMA and drop transmit queue, but disable interrupts first. 923 */ 924 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 925 fxp_stop(sc); 926 FXP_UNLOCK(sc); 927 928 /* 929 * Unhook interrupt before dropping lock. This is to prevent 930 * races with fxp_intr(). 931 */ 932 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 933 sc->ih = NULL; 934 935 splx(s); 936 937 /* Release our allocated resources. */ 938 fxp_release(sc); 939 return (0); 940} 941 942/* 943 * Device shutdown routine. Called at system shutdown after sync. The 944 * main purpose of this routine is to shut off receiver DMA so that 945 * kernel memory doesn't get clobbered during warmboot. 946 */ 947static int 948fxp_shutdown(device_t dev) 949{ 950 /* 951 * Make sure that DMA is disabled prior to reboot. Not doing 952 * do could allow DMA to corrupt kernel memory during the 953 * reboot before the driver initializes. 954 */ 955 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 956 return (0); 957} 958 959/* 960 * Device suspend routine. Stop the interface and save some PCI 961 * settings in case the BIOS doesn't restore them properly on 962 * resume. 963 */ 964static int 965fxp_suspend(device_t dev) 966{ 967 struct fxp_softc *sc = device_get_softc(dev); 968 int i, s; 969 970 FXP_LOCK(sc); 971 s = splimp(); 972 973 fxp_stop(sc); 974 975 for (i = 0; i < 5; i++) 976 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 977 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 978 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 979 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 980 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 981 982 sc->suspended = 1; 983 984 FXP_UNLOCK(sc); 985 splx(s); 986 return (0); 987} 988 989/* 990 * Device resume routine. Restore some PCI settings in case the BIOS 991 * doesn't, re-enable busmastering, and restart the interface if 992 * appropriate. 993 */ 994static int 995fxp_resume(device_t dev) 996{ 997 struct fxp_softc *sc = device_get_softc(dev); 998 struct ifnet *ifp = &sc->sc_if; 999 u_int16_t pci_command; 1000 int i, s; 1001 1002 FXP_LOCK(sc); 1003 s = splimp(); 1004#ifndef BURN_BRIDGES 1005 fxp_powerstate_d0(dev); 1006#endif 1007 /* better way to do this? */ 1008 for (i = 0; i < 5; i++) 1009 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1010 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1011 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1012 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1013 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1014 1015 /* reenable busmastering */ 1016 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1017 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1018 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1019 1020 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1021 DELAY(10); 1022 1023 /* reinitialize interface if necessary */ 1024 if (ifp->if_flags & IFF_UP) 1025 fxp_init_body(sc); 1026 1027 sc->suspended = 0; 1028 1029 FXP_UNLOCK(sc); 1030 splx(s); 1031 return (0); 1032} 1033 1034static void 1035fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1036{ 1037 u_int16_t reg; 1038 int x; 1039 1040 /* 1041 * Shift in data. 1042 */ 1043 for (x = 1 << (length - 1); x; x >>= 1) { 1044 if (data & x) 1045 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1046 else 1047 reg = FXP_EEPROM_EECS; 1048 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1049 DELAY(1); 1050 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1051 DELAY(1); 1052 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1053 DELAY(1); 1054 } 1055} 1056 1057/* 1058 * Read from the serial EEPROM. Basically, you manually shift in 1059 * the read opcode (one bit at a time) and then shift in the address, 1060 * and then you shift out the data (all of this one bit at a time). 1061 * The word size is 16 bits, so you have to provide the address for 1062 * every 16 bits of data. 1063 */ 1064static u_int16_t 1065fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1066{ 1067 u_int16_t reg, data; 1068 int x; 1069 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1071 /* 1072 * Shift in read opcode. 1073 */ 1074 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1075 /* 1076 * Shift in address. 1077 */ 1078 data = 0; 1079 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1080 if (offset & x) 1081 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1082 else 1083 reg = FXP_EEPROM_EECS; 1084 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1085 DELAY(1); 1086 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1087 DELAY(1); 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1089 DELAY(1); 1090 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1091 data++; 1092 if (autosize && reg == 0) { 1093 sc->eeprom_size = data; 1094 break; 1095 } 1096 } 1097 /* 1098 * Shift out data. 1099 */ 1100 data = 0; 1101 reg = FXP_EEPROM_EECS; 1102 for (x = 1 << 15; x; x >>= 1) { 1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1104 DELAY(1); 1105 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1106 data |= x; 1107 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1108 DELAY(1); 1109 } 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1111 DELAY(1); 1112 1113 return (data); 1114} 1115 1116static void 1117fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1118{ 1119 int i; 1120 1121 /* 1122 * Erase/write enable. 1123 */ 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1125 fxp_eeprom_shiftin(sc, 0x4, 3); 1126 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1128 DELAY(1); 1129 /* 1130 * Shift in write opcode, address, data. 1131 */ 1132 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1133 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1134 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1135 fxp_eeprom_shiftin(sc, data, 16); 1136 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1137 DELAY(1); 1138 /* 1139 * Wait for EEPROM to finish up. 1140 */ 1141 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1142 DELAY(1); 1143 for (i = 0; i < 1000; i++) { 1144 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1145 break; 1146 DELAY(50); 1147 } 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1149 DELAY(1); 1150 /* 1151 * Erase/write disable. 1152 */ 1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1154 fxp_eeprom_shiftin(sc, 0x4, 3); 1155 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1156 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1157 DELAY(1); 1158} 1159 1160/* 1161 * From NetBSD: 1162 * 1163 * Figure out EEPROM size. 1164 * 1165 * 559's can have either 64-word or 256-word EEPROMs, the 558 1166 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1167 * talks about the existance of 16 to 256 word EEPROMs. 1168 * 1169 * The only known sizes are 64 and 256, where the 256 version is used 1170 * by CardBus cards to store CIS information. 1171 * 1172 * The address is shifted in msb-to-lsb, and after the last 1173 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1174 * after which follows the actual data. We try to detect this zero, by 1175 * probing the data-out bit in the EEPROM control register just after 1176 * having shifted in a bit. If the bit is zero, we assume we've 1177 * shifted enough address bits. The data-out should be tri-state, 1178 * before this, which should translate to a logical one. 1179 */ 1180static void 1181fxp_autosize_eeprom(struct fxp_softc *sc) 1182{ 1183 1184 /* guess maximum size of 256 words */ 1185 sc->eeprom_size = 8; 1186 1187 /* autosize */ 1188 (void) fxp_eeprom_getword(sc, 0, 1); 1189} 1190 1191static void 1192fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1193{ 1194 int i; 1195 1196 for (i = 0; i < words; i++) 1197 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1198} 1199 1200static void 1201fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1202{ 1203 int i; 1204 1205 for (i = 0; i < words; i++) 1206 fxp_eeprom_putword(sc, offset + i, data[i]); 1207} 1208 1209static void 1210fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1211 bus_size_t mapsize, int error) 1212{ 1213 struct fxp_softc *sc; 1214 struct fxp_cb_tx *txp; 1215 int i; 1216 1217 if (error) 1218 return; 1219 1220 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1221 1222 sc = arg; 1223 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1224 for (i = 0; i < nseg; i++) { 1225 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1226 /* 1227 * If this is an 82550/82551, then we're using extended 1228 * TxCBs _and_ we're using checksum offload. This means 1229 * that the TxCB is really an IPCB. One major difference 1230 * between the two is that with plain extended TxCBs, 1231 * the bottom half of the TxCB contains two entries from 1232 * the TBD array, whereas IPCBs contain just one entry: 1233 * one entry (8 bytes) has been sacrificed for the TCP/IP 1234 * checksum offload control bits. So to make things work 1235 * right, we have to start filling in the TBD array 1236 * starting from a different place depending on whether 1237 * the chip is an 82550/82551 or not. 1238 */ 1239 if (sc->flags & FXP_FLAG_EXT_RFA) { 1240 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1241 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1242 } else { 1243 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1244 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1245 } 1246 } 1247 txp->tbd_number = nseg; 1248} 1249 1250/* 1251 * Grab the softc lock and call the real fxp_start_body() routine 1252 */ 1253static void 1254fxp_start(struct ifnet *ifp) 1255{ 1256 struct fxp_softc *sc = ifp->if_softc; 1257 1258 FXP_LOCK(sc); 1259 fxp_start_body(ifp); 1260 FXP_UNLOCK(sc); 1261} 1262 1263/* 1264 * Start packet transmission on the interface. 1265 * This routine must be called with the softc lock held, and is an 1266 * internal entry point only. 1267 */ 1268static void 1269fxp_start_body(struct ifnet *ifp) 1270{ 1271 struct fxp_softc *sc = ifp->if_softc; 1272 struct fxp_tx *txp; 1273 struct mbuf *mb_head; 1274 int error; 1275 1276 mtx_assert(&sc->sc_mtx, MA_OWNED); 1277 /* 1278 * See if we need to suspend xmit until the multicast filter 1279 * has been reprogrammed (which can only be done at the head 1280 * of the command chain). 1281 */ 1282 if (sc->need_mcsetup) { 1283 return; 1284 } 1285 1286 txp = NULL; 1287 1288 /* 1289 * We're finished if there is nothing more to add to the list or if 1290 * we're all filled up with buffers to transmit. 1291 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1292 * a NOP command when needed. 1293 */ 1294 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1295 1296 /* 1297 * Grab a packet to transmit. 1298 */ 1299 IF_DEQUEUE(&ifp->if_snd, mb_head); 1300 1301 /* 1302 * Get pointer to next available tx desc. 1303 */ 1304 txp = sc->fxp_desc.tx_last->tx_next; 1305 1306 /* 1307 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1308 * Ethernet Controller Family Open Source Software 1309 * Developer Manual says: 1310 * Using software parsing is only allowed with legal 1311 * TCP/IP or UDP/IP packets. 1312 * ... 1313 * For all other datagrams, hardware parsing must 1314 * be used. 1315 * Software parsing appears to truncate ICMP and 1316 * fragmented UDP packets that contain one to three 1317 * bytes in the second (and final) mbuf of the packet. 1318 */ 1319 if (sc->flags & FXP_FLAG_EXT_RFA) 1320 txp->tx_cb->ipcb_ip_activation_high = 1321 FXP_IPCB_HARDWAREPARSING_ENABLE; 1322 1323 /* 1324 * Deal with TCP/IP checksum offload. Note that 1325 * in order for TCP checksum offload to work, 1326 * the pseudo header checksum must have already 1327 * been computed and stored in the checksum field 1328 * in the TCP header. The stack should have 1329 * already done this for us. 1330 */ 1331 1332 if (mb_head->m_pkthdr.csum_flags) { 1333 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1334 txp->tx_cb->ipcb_ip_schedule = 1335 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1336 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1337 txp->tx_cb->ipcb_ip_schedule |= 1338 FXP_IPCB_TCP_PACKET; 1339 } 1340#ifdef FXP_IP_CSUM_WAR 1341 /* 1342 * XXX The 82550 chip appears to have trouble 1343 * dealing with IP header checksums in very small 1344 * datagrams, namely fragments from 1 to 3 bytes 1345 * in size. For example, say you want to transmit 1346 * a UDP packet of 1473 bytes. The packet will be 1347 * fragmented over two IP datagrams, the latter 1348 * containing only one byte of data. The 82550 will 1349 * botch the header checksum on the 1-byte fragment. 1350 * As long as the datagram contains 4 or more bytes 1351 * of data, you're ok. 1352 * 1353 * The following code attempts to work around this 1354 * problem: if the datagram is less than 38 bytes 1355 * in size (14 bytes ether header, 20 bytes IP header, 1356 * plus 4 bytes of data), we punt and compute the IP 1357 * header checksum by hand. This workaround doesn't 1358 * work very well, however, since it can be fooled 1359 * by things like VLAN tags and IP options that make 1360 * the header sizes/offsets vary. 1361 */ 1362 1363 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1364 if (mb_head->m_pkthdr.len < 38) { 1365 struct ip *ip; 1366 mb_head->m_data += ETHER_HDR_LEN; 1367 ip = mtod(mb_head, struct ip *); 1368 ip->ip_sum = in_cksum(mb_head, 1369 ip->ip_hl << 2); 1370 mb_head->m_data -= ETHER_HDR_LEN; 1371 } else { 1372 txp->tx_cb->ipcb_ip_activation_high = 1373 FXP_IPCB_HARDWAREPARSING_ENABLE; 1374 txp->tx_cb->ipcb_ip_schedule |= 1375 FXP_IPCB_IP_CHECKSUM_ENABLE; 1376 } 1377 } 1378#endif 1379 } 1380 1381 /* 1382 * Go through each of the mbufs in the chain and initialize 1383 * the transmit buffer descriptors with the physical address 1384 * and size of the mbuf. 1385 */ 1386 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1387 mb_head, fxp_dma_map_txbuf, sc, 0); 1388 1389 if (error && error != EFBIG) { 1390 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1391 error); 1392 m_freem(mb_head); 1393 break; 1394 } 1395 1396 if (error) { 1397 struct mbuf *mn; 1398 1399 /* 1400 * We ran out of segments. We have to recopy this 1401 * mbuf chain first. Bail out if we can't get the 1402 * new buffers. 1403 */ 1404 mn = m_defrag(mb_head, M_DONTWAIT); 1405 if (mn == NULL) { 1406 m_freem(mb_head); 1407 break; 1408 } else { 1409 mb_head = mn; 1410 } 1411 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1412 mb_head, fxp_dma_map_txbuf, sc, 0); 1413 if (error) { 1414 device_printf(sc->dev, 1415 "can't map mbuf (error %d)\n", error); 1416 m_freem(mb_head); 1417 break; 1418 } 1419 } 1420 1421 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1422 BUS_DMASYNC_PREWRITE); 1423 1424 txp->tx_mbuf = mb_head; 1425 txp->tx_cb->cb_status = 0; 1426 txp->tx_cb->byte_count = 0; 1427 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1428 txp->tx_cb->cb_command = 1429 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1430 FXP_CB_COMMAND_S); 1431 } else { 1432 txp->tx_cb->cb_command = 1433 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1434 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1435 /* 1436 * Set a 5 second timer just in case we don't hear 1437 * from the card again. 1438 */ 1439 ifp->if_timer = 5; 1440 } 1441 txp->tx_cb->tx_threshold = tx_threshold; 1442 1443 /* 1444 * Advance the end of list forward. 1445 */ 1446 1447#ifdef __alpha__ 1448 /* 1449 * On platforms which can't access memory in 16-bit 1450 * granularities, we must prevent the card from DMA'ing 1451 * up the status while we update the command field. 1452 * This could cause us to overwrite the completion status. 1453 * XXX This is probably bogus and we're _not_ looking 1454 * for atomicity here. 1455 */ 1456 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1457 htole16(FXP_CB_COMMAND_S)); 1458#else 1459 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1460 htole16(~FXP_CB_COMMAND_S); 1461#endif /*__alpha__*/ 1462 sc->fxp_desc.tx_last = txp; 1463 1464 /* 1465 * Advance the beginning of the list forward if there are 1466 * no other packets queued (when nothing is queued, tx_first 1467 * sits on the last TxCB that was sent out). 1468 */ 1469 if (sc->tx_queued == 0) 1470 sc->fxp_desc.tx_first = txp; 1471 1472 sc->tx_queued++; 1473 1474 /* 1475 * Pass packet to bpf if there is a listener. 1476 */ 1477 BPF_MTAP(ifp, mb_head); 1478 } 1479 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1480 1481 /* 1482 * We're finished. If we added to the list, issue a RESUME to get DMA 1483 * going again if suspended. 1484 */ 1485 if (txp != NULL) { 1486 fxp_scb_wait(sc); 1487 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1488 } 1489} 1490 1491#ifdef DEVICE_POLLING 1492static poll_handler_t fxp_poll; 1493 1494static void 1495fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1496{ 1497 struct fxp_softc *sc = ifp->if_softc; 1498 u_int8_t statack; 1499 1500 FXP_LOCK(sc); 1501 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1502 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1503 FXP_UNLOCK(sc); 1504 return; 1505 } 1506 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1507 FXP_SCB_STATACK_FR; 1508 if (cmd == POLL_AND_CHECK_STATUS) { 1509 u_int8_t tmp; 1510 1511 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1512 if (tmp == 0xff || tmp == 0) { 1513 FXP_UNLOCK(sc); 1514 return; /* nothing to do */ 1515 } 1516 tmp &= ~statack; 1517 /* ack what we can */ 1518 if (tmp != 0) 1519 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1520 statack |= tmp; 1521 } 1522 fxp_intr_body(sc, ifp, statack, count); 1523 FXP_UNLOCK(sc); 1524} 1525#endif /* DEVICE_POLLING */ 1526 1527/* 1528 * Process interface interrupts. 1529 */ 1530static void 1531fxp_intr(void *xsc) 1532{ 1533 struct fxp_softc *sc = xsc; 1534 struct ifnet *ifp = &sc->sc_if; 1535 u_int8_t statack; 1536 1537 FXP_LOCK(sc); 1538 if (sc->suspended) { 1539 FXP_UNLOCK(sc); 1540 return; 1541 } 1542 1543#ifdef DEVICE_POLLING 1544 if (ifp->if_flags & IFF_POLLING) { 1545 FXP_UNLOCK(sc); 1546 return; 1547 } 1548 if (ether_poll_register(fxp_poll, ifp)) { 1549 /* disable interrupts */ 1550 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1551 FXP_UNLOCK(sc); 1552 fxp_poll(ifp, 0, 1); 1553 return; 1554 } 1555#endif 1556 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1557 /* 1558 * It should not be possible to have all bits set; the 1559 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1560 * all bits are set, this may indicate that the card has 1561 * been physically ejected, so ignore it. 1562 */ 1563 if (statack == 0xff) { 1564 FXP_UNLOCK(sc); 1565 return; 1566 } 1567 1568 /* 1569 * First ACK all the interrupts in this pass. 1570 */ 1571 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1572 fxp_intr_body(sc, ifp, statack, -1); 1573 } 1574 FXP_UNLOCK(sc); 1575} 1576 1577static void 1578fxp_txeof(struct fxp_softc *sc) 1579{ 1580 struct fxp_tx *txp; 1581 1582 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1583 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1584 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1585 txp = txp->tx_next) { 1586 if (txp->tx_mbuf != NULL) { 1587 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1588 BUS_DMASYNC_POSTWRITE); 1589 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1590 m_freem(txp->tx_mbuf); 1591 txp->tx_mbuf = NULL; 1592 /* clear this to reset csum offload bits */ 1593 txp->tx_cb->tbd[0].tb_addr = 0; 1594 } 1595 sc->tx_queued--; 1596 } 1597 sc->fxp_desc.tx_first = txp; 1598 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1599} 1600 1601static void 1602fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1603 int count) 1604{ 1605 struct mbuf *m; 1606 struct fxp_rx *rxp; 1607 struct fxp_rfa *rfa; 1608 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1609 1610 mtx_assert(&sc->sc_mtx, MA_OWNED); 1611 if (rnr) 1612 fxp_rnr++; 1613#ifdef DEVICE_POLLING 1614 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1615 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1616 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1617 rnr = 1; 1618 } 1619#endif 1620 1621 /* 1622 * Free any finished transmit mbuf chains. 1623 * 1624 * Handle the CNA event likt a CXTNO event. It used to 1625 * be that this event (control unit not ready) was not 1626 * encountered, but it is now with the SMPng modifications. 1627 * The exact sequence of events that occur when the interface 1628 * is brought up are different now, and if this event 1629 * goes unhandled, the configuration/rxfilter setup sequence 1630 * can stall for several seconds. The result is that no 1631 * packets go out onto the wire for about 5 to 10 seconds 1632 * after the interface is ifconfig'ed for the first time. 1633 */ 1634 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1635 fxp_txeof(sc); 1636 1637 ifp->if_timer = 0; 1638 if (sc->tx_queued == 0) { 1639 if (sc->need_mcsetup) 1640 fxp_mc_setup(sc); 1641 } 1642 /* 1643 * Try to start more packets transmitting. 1644 */ 1645 if (ifp->if_snd.ifq_head != NULL) 1646 fxp_start_body(ifp); 1647 } 1648 1649 /* 1650 * Just return if nothing happened on the receive side. 1651 */ 1652 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1653 return; 1654 1655 /* 1656 * Process receiver interrupts. If a no-resource (RNR) 1657 * condition exists, get whatever packets we can and 1658 * re-start the receiver. 1659 * 1660 * When using polling, we do not process the list to completion, 1661 * so when we get an RNR interrupt we must defer the restart 1662 * until we hit the last buffer with the C bit set. 1663 * If we run out of cycles and rfa_headm has the C bit set, 1664 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1665 * that the info will be used in the subsequent polling cycle. 1666 */ 1667 for (;;) { 1668 rxp = sc->fxp_desc.rx_head; 1669 m = rxp->rx_mbuf; 1670 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1671 RFA_ALIGNMENT_FUDGE); 1672 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1673 BUS_DMASYNC_POSTREAD); 1674 1675#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1676 if (count >= 0 && count-- == 0) { 1677 if (rnr) { 1678 /* Defer RNR processing until the next time. */ 1679 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1680 rnr = 0; 1681 } 1682 break; 1683 } 1684#endif /* DEVICE_POLLING */ 1685 1686 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1687 break; 1688 1689 /* 1690 * Advance head forward. 1691 */ 1692 sc->fxp_desc.rx_head = rxp->rx_next; 1693 1694 /* 1695 * Add a new buffer to the receive chain. 1696 * If this fails, the old buffer is recycled 1697 * instead. 1698 */ 1699 if (fxp_add_rfabuf(sc, rxp) == 0) { 1700 int total_len; 1701 1702 /* 1703 * Fetch packet length (the top 2 bits of 1704 * actual_size are flags set by the controller 1705 * upon completion), and drop the packet in case 1706 * of bogus length or CRC errors. 1707 */ 1708 total_len = le16toh(rfa->actual_size) & 0x3fff; 1709 if (total_len < sizeof(struct ether_header) || 1710 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1711 sc->rfa_size || 1712 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1713 m_freem(m); 1714 continue; 1715 } 1716 1717 /* Do IP checksum checking. */ 1718 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1719 if (rfa->rfax_csum_sts & 1720 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1721 m->m_pkthdr.csum_flags |= 1722 CSUM_IP_CHECKED; 1723 if (rfa->rfax_csum_sts & 1724 FXP_RFDX_CS_IP_CSUM_VALID) 1725 m->m_pkthdr.csum_flags |= 1726 CSUM_IP_VALID; 1727 if ((rfa->rfax_csum_sts & 1728 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1729 (rfa->rfax_csum_sts & 1730 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1731 m->m_pkthdr.csum_flags |= 1732 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1733 m->m_pkthdr.csum_data = 0xffff; 1734 } 1735 } 1736 1737 m->m_pkthdr.len = m->m_len = total_len; 1738 m->m_pkthdr.rcvif = ifp; 1739 1740 /* 1741 * Drop locks before calling if_input() since it 1742 * may re-enter fxp_start() in the netisr case. 1743 * This would result in a lock reversal. Better 1744 * performance might be obtained by chaining all 1745 * packets received, dropping the lock, and then 1746 * calling if_input() on each one. 1747 */ 1748 FXP_UNLOCK(sc); 1749 (*ifp->if_input)(ifp, m); 1750 FXP_LOCK(sc); 1751 } 1752 } 1753 if (rnr) { 1754 fxp_scb_wait(sc); 1755 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1756 sc->fxp_desc.rx_head->rx_addr); 1757 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1758 } 1759} 1760 1761/* 1762 * Update packet in/out/collision statistics. The i82557 doesn't 1763 * allow you to access these counters without doing a fairly 1764 * expensive DMA to get _all_ of the statistics it maintains, so 1765 * we do this operation here only once per second. The statistics 1766 * counters in the kernel are updated from the previous dump-stats 1767 * DMA and then a new dump-stats DMA is started. The on-chip 1768 * counters are zeroed when the DMA completes. If we can't start 1769 * the DMA immediately, we don't wait - we just prepare to read 1770 * them again next time. 1771 */ 1772static void 1773fxp_tick(void *xsc) 1774{ 1775 struct fxp_softc *sc = xsc; 1776 struct ifnet *ifp = &sc->sc_if; 1777 struct fxp_stats *sp = sc->fxp_stats; 1778 int s; 1779 1780 FXP_LOCK(sc); 1781 s = splimp(); 1782 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1783 ifp->if_opackets += le32toh(sp->tx_good); 1784 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1785 if (sp->rx_good) { 1786 ifp->if_ipackets += le32toh(sp->rx_good); 1787 sc->rx_idle_secs = 0; 1788 } else { 1789 /* 1790 * Receiver's been idle for another second. 1791 */ 1792 sc->rx_idle_secs++; 1793 } 1794 ifp->if_ierrors += 1795 le32toh(sp->rx_crc_errors) + 1796 le32toh(sp->rx_alignment_errors) + 1797 le32toh(sp->rx_rnr_errors) + 1798 le32toh(sp->rx_overrun_errors); 1799 /* 1800 * If any transmit underruns occured, bump up the transmit 1801 * threshold by another 512 bytes (64 * 8). 1802 */ 1803 if (sp->tx_underruns) { 1804 ifp->if_oerrors += le32toh(sp->tx_underruns); 1805 if (tx_threshold < 192) 1806 tx_threshold += 64; 1807 } 1808 1809 /* 1810 * Release any xmit buffers that have completed DMA. This isn't 1811 * strictly necessary to do here, but it's advantagous for mbufs 1812 * with external storage to be released in a timely manner rather 1813 * than being defered for a potentially long time. This limits 1814 * the delay to a maximum of one second. 1815 */ 1816 fxp_txeof(sc); 1817 1818 /* 1819 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1820 * then assume the receiver has locked up and attempt to clear 1821 * the condition by reprogramming the multicast filter. This is 1822 * a work-around for a bug in the 82557 where the receiver locks 1823 * up if it gets certain types of garbage in the syncronization 1824 * bits prior to the packet header. This bug is supposed to only 1825 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1826 * mode as well (perhaps due to a 10/100 speed transition). 1827 */ 1828 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1829 sc->rx_idle_secs = 0; 1830 fxp_mc_setup(sc); 1831 } 1832 /* 1833 * If there is no pending command, start another stats 1834 * dump. Otherwise punt for now. 1835 */ 1836 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1837 /* 1838 * Start another stats dump. 1839 */ 1840 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1841 BUS_DMASYNC_PREREAD); 1842 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1843 } else { 1844 /* 1845 * A previous command is still waiting to be accepted. 1846 * Just zero our copy of the stats and wait for the 1847 * next timer event to update them. 1848 */ 1849 sp->tx_good = 0; 1850 sp->tx_underruns = 0; 1851 sp->tx_total_collisions = 0; 1852 1853 sp->rx_good = 0; 1854 sp->rx_crc_errors = 0; 1855 sp->rx_alignment_errors = 0; 1856 sp->rx_rnr_errors = 0; 1857 sp->rx_overrun_errors = 0; 1858 } 1859 if (sc->miibus != NULL) 1860 mii_tick(device_get_softc(sc->miibus)); 1861 1862 /* 1863 * Schedule another timeout one second from now. 1864 */ 1865 sc->stat_ch = timeout(fxp_tick, sc, hz); 1866 FXP_UNLOCK(sc); 1867 splx(s); 1868} 1869 1870/* 1871 * Stop the interface. Cancels the statistics updater and resets 1872 * the interface. 1873 */ 1874static void 1875fxp_stop(struct fxp_softc *sc) 1876{ 1877 struct ifnet *ifp = &sc->sc_if; 1878 struct fxp_tx *txp; 1879 int i; 1880 1881 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1882 ifp->if_timer = 0; 1883 1884#ifdef DEVICE_POLLING 1885 ether_poll_deregister(ifp); 1886#endif 1887 /* 1888 * Cancel stats updater. 1889 */ 1890 untimeout(fxp_tick, sc, sc->stat_ch); 1891 1892 /* 1893 * Issue software reset, which also unloads the microcode. 1894 */ 1895 sc->flags &= ~FXP_FLAG_UCODE; 1896 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1897 DELAY(50); 1898 1899 /* 1900 * Release any xmit buffers. 1901 */ 1902 txp = sc->fxp_desc.tx_list; 1903 if (txp != NULL) { 1904 for (i = 0; i < FXP_NTXCB; i++) { 1905 if (txp[i].tx_mbuf != NULL) { 1906 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1907 BUS_DMASYNC_POSTWRITE); 1908 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1909 m_freem(txp[i].tx_mbuf); 1910 txp[i].tx_mbuf = NULL; 1911 /* clear this to reset csum offload bits */ 1912 txp[i].tx_cb->tbd[0].tb_addr = 0; 1913 } 1914 } 1915 } 1916 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1917 sc->tx_queued = 0; 1918} 1919 1920/* 1921 * Watchdog/transmission transmit timeout handler. Called when a 1922 * transmission is started on the interface, but no interrupt is 1923 * received before the timeout. This usually indicates that the 1924 * card has wedged for some reason. 1925 */ 1926static void 1927fxp_watchdog(struct ifnet *ifp) 1928{ 1929 struct fxp_softc *sc = ifp->if_softc; 1930 1931 FXP_LOCK(sc); 1932 device_printf(sc->dev, "device timeout\n"); 1933 ifp->if_oerrors++; 1934 1935 fxp_init_body(sc); 1936 FXP_UNLOCK(sc); 1937} 1938 1939/* 1940 * Acquire locks and then call the real initialization function. This 1941 * is necessary because ether_ioctl() calls if_init() and this would 1942 * result in mutex recursion if the mutex was held. 1943 */ 1944static void 1945fxp_init(void *xsc) 1946{ 1947 struct fxp_softc *sc = xsc; 1948 1949 FXP_LOCK(sc); 1950 fxp_init_body(sc); 1951 FXP_UNLOCK(sc); 1952} 1953 1954/* 1955 * Perform device initialization. This routine must be called with the 1956 * softc lock held. 1957 */ 1958static void 1959fxp_init_body(struct fxp_softc *sc) 1960{ 1961 struct ifnet *ifp = &sc->sc_if; 1962 struct fxp_cb_config *cbp; 1963 struct fxp_cb_ias *cb_ias; 1964 struct fxp_cb_tx *tcbp; 1965 struct fxp_tx *txp; 1966 struct fxp_cb_mcs *mcsp; 1967 int i, prm, s; 1968 1969 mtx_assert(&sc->sc_mtx, MA_OWNED); 1970 s = splimp(); 1971 /* 1972 * Cancel any pending I/O 1973 */ 1974 fxp_stop(sc); 1975 1976 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1977 1978 /* 1979 * Initialize base of CBL and RFA memory. Loading with zero 1980 * sets it up for regular linear addressing. 1981 */ 1982 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1983 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1984 1985 fxp_scb_wait(sc); 1986 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1987 1988 /* 1989 * Initialize base of dump-stats buffer. 1990 */ 1991 fxp_scb_wait(sc); 1992 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1993 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1994 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1995 1996 /* 1997 * Attempt to load microcode if requested. 1998 */ 1999 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2000 fxp_load_ucode(sc); 2001 2002 /* 2003 * Initialize the multicast address list. 2004 */ 2005 if (fxp_mc_addrs(sc)) { 2006 mcsp = sc->mcsp; 2007 mcsp->cb_status = 0; 2008 mcsp->cb_command = 2009 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2010 mcsp->link_addr = 0xffffffff; 2011 /* 2012 * Start the multicast setup command. 2013 */ 2014 fxp_scb_wait(sc); 2015 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2016 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2017 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2018 /* ...and wait for it to complete. */ 2019 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2020 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2021 BUS_DMASYNC_POSTWRITE); 2022 } 2023 2024 /* 2025 * We temporarily use memory that contains the TxCB list to 2026 * construct the config CB. The TxCB list memory is rebuilt 2027 * later. 2028 */ 2029 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2030 2031 /* 2032 * This bcopy is kind of disgusting, but there are a bunch of must be 2033 * zero and must be one bits in this structure and this is the easiest 2034 * way to initialize them all to proper values. 2035 */ 2036 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2037 2038 cbp->cb_status = 0; 2039 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2040 FXP_CB_COMMAND_EL); 2041 cbp->link_addr = 0xffffffff; /* (no) next command */ 2042 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2043 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2044 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2045 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2046 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2047 cbp->type_enable = 0; /* actually reserved */ 2048 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2049 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2050 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2051 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2052 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2053 cbp->late_scb = 0; /* (don't) defer SCB update */ 2054 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2055 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2056 cbp->ci_int = 1; /* interrupt on CU idle */ 2057 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2058 cbp->ext_stats_dis = 1; /* disable extended counters */ 2059 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2060 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2061 cbp->disc_short_rx = !prm; /* discard short packets */ 2062 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2063 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2064 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2065 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2066 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2067 cbp->csma_dis = 0; /* (don't) disable link */ 2068 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2069 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2070 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2071 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2072 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2073 cbp->nsai = 1; /* (don't) disable source addr insert */ 2074 cbp->preamble_length = 2; /* (7 byte) preamble */ 2075 cbp->loopback = 0; /* (don't) loopback */ 2076 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2077 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2078 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2079 cbp->promiscuous = prm; /* promiscuous mode */ 2080 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2081 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2082 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2083 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2084 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2085 2086 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2087 cbp->padding = 1; /* (do) pad short tx packets */ 2088 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2089 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2090 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2091 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2092 /* must set wake_en in PMCSR also */ 2093 cbp->force_fdx = 0; /* (don't) force full duplex */ 2094 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2095 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2096 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2097 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2098 2099 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2100 /* 2101 * The 82557 has no hardware flow control, the values 2102 * below are the defaults for the chip. 2103 */ 2104 cbp->fc_delay_lsb = 0; 2105 cbp->fc_delay_msb = 0x40; 2106 cbp->pri_fc_thresh = 3; 2107 cbp->tx_fc_dis = 0; 2108 cbp->rx_fc_restop = 0; 2109 cbp->rx_fc_restart = 0; 2110 cbp->fc_filter = 0; 2111 cbp->pri_fc_loc = 1; 2112 } else { 2113 cbp->fc_delay_lsb = 0x1f; 2114 cbp->fc_delay_msb = 0x01; 2115 cbp->pri_fc_thresh = 3; 2116 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2117 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2118 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2119 cbp->fc_filter = !prm; /* drop FC frames to host */ 2120 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2121 } 2122 2123 /* 2124 * Start the config command/DMA. 2125 */ 2126 fxp_scb_wait(sc); 2127 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2128 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2129 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2130 /* ...and wait for it to complete. */ 2131 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2132 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2133 2134 /* 2135 * Now initialize the station address. Temporarily use the TxCB 2136 * memory area like we did above for the config CB. 2137 */ 2138 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2139 cb_ias->cb_status = 0; 2140 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2141 cb_ias->link_addr = 0xffffffff; 2142 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2143 sizeof(sc->arpcom.ac_enaddr)); 2144 2145 /* 2146 * Start the IAS (Individual Address Setup) command/DMA. 2147 */ 2148 fxp_scb_wait(sc); 2149 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2150 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2151 /* ...and wait for it to complete. */ 2152 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2153 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2154 2155 /* 2156 * Initialize transmit control block (TxCB) list. 2157 */ 2158 txp = sc->fxp_desc.tx_list; 2159 tcbp = sc->fxp_desc.cbl_list; 2160 bzero(tcbp, FXP_TXCB_SZ); 2161 for (i = 0; i < FXP_NTXCB; i++) { 2162 txp[i].tx_cb = tcbp + i; 2163 txp[i].tx_mbuf = NULL; 2164 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2165 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2166 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2167 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2168 if (sc->flags & FXP_FLAG_EXT_TXCB) 2169 tcbp[i].tbd_array_addr = 2170 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2171 else 2172 tcbp[i].tbd_array_addr = 2173 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2174 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2175 } 2176 /* 2177 * Set the suspend flag on the first TxCB and start the control 2178 * unit. It will execute the NOP and then suspend. 2179 */ 2180 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2181 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2182 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2183 sc->tx_queued = 1; 2184 2185 fxp_scb_wait(sc); 2186 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2187 2188 /* 2189 * Initialize receiver buffer area - RFA. 2190 */ 2191 fxp_scb_wait(sc); 2192 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2193 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2194 2195 /* 2196 * Set current media. 2197 */ 2198 if (sc->miibus != NULL) 2199 mii_mediachg(device_get_softc(sc->miibus)); 2200 2201 ifp->if_flags |= IFF_RUNNING; 2202 ifp->if_flags &= ~IFF_OACTIVE; 2203 2204 /* 2205 * Enable interrupts. 2206 */ 2207#ifdef DEVICE_POLLING 2208 /* 2209 * ... but only do that if we are not polling. And because (presumably) 2210 * the default is interrupts on, we need to disable them explicitly! 2211 */ 2212 if ( ifp->if_flags & IFF_POLLING ) 2213 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2214 else 2215#endif /* DEVICE_POLLING */ 2216 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2217 2218 /* 2219 * Start stats updater. 2220 */ 2221 sc->stat_ch = timeout(fxp_tick, sc, hz); 2222 splx(s); 2223} 2224 2225static int 2226fxp_serial_ifmedia_upd(struct ifnet *ifp) 2227{ 2228 2229 return (0); 2230} 2231 2232static void 2233fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2234{ 2235 2236 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2237} 2238 2239/* 2240 * Change media according to request. 2241 */ 2242static int 2243fxp_ifmedia_upd(struct ifnet *ifp) 2244{ 2245 struct fxp_softc *sc = ifp->if_softc; 2246 struct mii_data *mii; 2247 2248 mii = device_get_softc(sc->miibus); 2249 mii_mediachg(mii); 2250 return (0); 2251} 2252 2253/* 2254 * Notify the world which media we're using. 2255 */ 2256static void 2257fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2258{ 2259 struct fxp_softc *sc = ifp->if_softc; 2260 struct mii_data *mii; 2261 2262 mii = device_get_softc(sc->miibus); 2263 mii_pollstat(mii); 2264 ifmr->ifm_active = mii->mii_media_active; 2265 ifmr->ifm_status = mii->mii_media_status; 2266 2267 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2268 sc->cu_resume_bug = 1; 2269 else 2270 sc->cu_resume_bug = 0; 2271} 2272 2273/* 2274 * Add a buffer to the end of the RFA buffer list. 2275 * Return 0 if successful, 1 for failure. A failure results in 2276 * adding the 'oldm' (if non-NULL) on to the end of the list - 2277 * tossing out its old contents and recycling it. 2278 * The RFA struct is stuck at the beginning of mbuf cluster and the 2279 * data pointer is fixed up to point just past it. 2280 */ 2281static int 2282fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2283{ 2284 struct mbuf *m; 2285 struct fxp_rfa *rfa, *p_rfa; 2286 struct fxp_rx *p_rx; 2287 bus_dmamap_t tmp_map; 2288 int error; 2289 2290 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2291 if (m == NULL) 2292 return (ENOBUFS); 2293 2294 /* 2295 * Move the data pointer up so that the incoming data packet 2296 * will be 32-bit aligned. 2297 */ 2298 m->m_data += RFA_ALIGNMENT_FUDGE; 2299 2300 /* 2301 * Get a pointer to the base of the mbuf cluster and move 2302 * data start past it. 2303 */ 2304 rfa = mtod(m, struct fxp_rfa *); 2305 m->m_data += sc->rfa_size; 2306 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2307 2308 rfa->rfa_status = 0; 2309 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2310 rfa->actual_size = 0; 2311 2312 /* 2313 * Initialize the rest of the RFA. Note that since the RFA 2314 * is misaligned, we cannot store values directly. We're thus 2315 * using the le32enc() function which handles endianness and 2316 * is also alignment-safe. 2317 */ 2318 le32enc(&rfa->link_addr, 0xffffffff); 2319 le32enc(&rfa->rbd_addr, 0xffffffff); 2320 2321 /* Map the RFA into DMA memory. */ 2322 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2323 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2324 &rxp->rx_addr, 0); 2325 if (error) { 2326 m_freem(m); 2327 return (error); 2328 } 2329 2330 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2331 tmp_map = sc->spare_map; 2332 sc->spare_map = rxp->rx_map; 2333 rxp->rx_map = tmp_map; 2334 rxp->rx_mbuf = m; 2335 2336 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2337 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2338 2339 /* 2340 * If there are other buffers already on the list, attach this 2341 * one to the end by fixing up the tail to point to this one. 2342 */ 2343 if (sc->fxp_desc.rx_head != NULL) { 2344 p_rx = sc->fxp_desc.rx_tail; 2345 p_rfa = (struct fxp_rfa *) 2346 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2347 p_rx->rx_next = rxp; 2348 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2349 p_rfa->rfa_control = 0; 2350 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2351 BUS_DMASYNC_PREWRITE); 2352 } else { 2353 rxp->rx_next = NULL; 2354 sc->fxp_desc.rx_head = rxp; 2355 } 2356 sc->fxp_desc.rx_tail = rxp; 2357 return (0); 2358} 2359 2360static volatile int 2361fxp_miibus_readreg(device_t dev, int phy, int reg) 2362{ 2363 struct fxp_softc *sc = device_get_softc(dev); 2364 int count = 10000; 2365 int value; 2366 2367 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2368 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2369 2370 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2371 && count--) 2372 DELAY(10); 2373 2374 if (count <= 0) 2375 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2376 2377 return (value & 0xffff); 2378} 2379 2380static void 2381fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2382{ 2383 struct fxp_softc *sc = device_get_softc(dev); 2384 int count = 10000; 2385 2386 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2387 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2388 (value & 0xffff)); 2389 2390 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2391 count--) 2392 DELAY(10); 2393 2394 if (count <= 0) 2395 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2396} 2397 2398static int 2399fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2400{ 2401 struct fxp_softc *sc = ifp->if_softc; 2402 struct ifreq *ifr = (struct ifreq *)data; 2403 struct mii_data *mii; 2404 int s, error = 0; 2405 2406 /* 2407 * Detaching causes us to call ioctl with the mutex owned. Preclude 2408 * that by saying we're busy if the lock is already held. 2409 */ 2410 if (mtx_owned(&sc->sc_mtx)) 2411 return (EBUSY); 2412 2413 FXP_LOCK(sc); 2414 s = splimp(); 2415 2416 switch (command) { 2417 case SIOCSIFFLAGS: 2418 if (ifp->if_flags & IFF_ALLMULTI) 2419 sc->flags |= FXP_FLAG_ALL_MCAST; 2420 else 2421 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2422 2423 /* 2424 * If interface is marked up and not running, then start it. 2425 * If it is marked down and running, stop it. 2426 * XXX If it's up then re-initialize it. This is so flags 2427 * such as IFF_PROMISC are handled. 2428 */ 2429 if (ifp->if_flags & IFF_UP) { 2430 fxp_init_body(sc); 2431 } else { 2432 if (ifp->if_flags & IFF_RUNNING) 2433 fxp_stop(sc); 2434 } 2435 break; 2436 2437 case SIOCADDMULTI: 2438 case SIOCDELMULTI: 2439 if (ifp->if_flags & IFF_ALLMULTI) 2440 sc->flags |= FXP_FLAG_ALL_MCAST; 2441 else 2442 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2443 /* 2444 * Multicast list has changed; set the hardware filter 2445 * accordingly. 2446 */ 2447 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2448 fxp_mc_setup(sc); 2449 /* 2450 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2451 * again rather than else {}. 2452 */ 2453 if (sc->flags & FXP_FLAG_ALL_MCAST) 2454 fxp_init_body(sc); 2455 error = 0; 2456 break; 2457 2458 case SIOCSIFMEDIA: 2459 case SIOCGIFMEDIA: 2460 if (sc->miibus != NULL) { 2461 mii = device_get_softc(sc->miibus); 2462 error = ifmedia_ioctl(ifp, ifr, 2463 &mii->mii_media, command); 2464 } else { 2465 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2466 } 2467 break; 2468 2469 default: 2470 /* 2471 * ether_ioctl() will eventually call fxp_start() which 2472 * will result in mutex recursion so drop it first. 2473 */ 2474 FXP_UNLOCK(sc); 2475 error = ether_ioctl(ifp, command, data); 2476 } 2477 if (mtx_owned(&sc->sc_mtx)) 2478 FXP_UNLOCK(sc); 2479 splx(s); 2480 return (error); 2481} 2482 2483/* 2484 * Fill in the multicast address list and return number of entries. 2485 */ 2486static int 2487fxp_mc_addrs(struct fxp_softc *sc) 2488{ 2489 struct fxp_cb_mcs *mcsp = sc->mcsp; 2490 struct ifnet *ifp = &sc->sc_if; 2491 struct ifmultiaddr *ifma; 2492 int nmcasts; 2493 2494 nmcasts = 0; 2495 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2496#if __FreeBSD_version < 500000 2497 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2498#else 2499 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2500#endif 2501 if (ifma->ifma_addr->sa_family != AF_LINK) 2502 continue; 2503 if (nmcasts >= MAXMCADDR) { 2504 sc->flags |= FXP_FLAG_ALL_MCAST; 2505 nmcasts = 0; 2506 break; 2507 } 2508 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2509 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2510 nmcasts++; 2511 } 2512 } 2513 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2514 return (nmcasts); 2515} 2516 2517/* 2518 * Program the multicast filter. 2519 * 2520 * We have an artificial restriction that the multicast setup command 2521 * must be the first command in the chain, so we take steps to ensure 2522 * this. By requiring this, it allows us to keep up the performance of 2523 * the pre-initialized command ring (esp. link pointers) by not actually 2524 * inserting the mcsetup command in the ring - i.e. its link pointer 2525 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2526 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2527 * lead into the regular TxCB ring when it completes. 2528 * 2529 * This function must be called at splimp. 2530 */ 2531static void 2532fxp_mc_setup(struct fxp_softc *sc) 2533{ 2534 struct fxp_cb_mcs *mcsp = sc->mcsp; 2535 struct ifnet *ifp = &sc->sc_if; 2536 struct fxp_tx *txp; 2537 int count; 2538 2539 /* 2540 * If there are queued commands, we must wait until they are all 2541 * completed. If we are already waiting, then add a NOP command 2542 * with interrupt option so that we're notified when all commands 2543 * have been completed - fxp_start() ensures that no additional 2544 * TX commands will be added when need_mcsetup is true. 2545 */ 2546 if (sc->tx_queued) { 2547 /* 2548 * need_mcsetup will be true if we are already waiting for the 2549 * NOP command to be completed (see below). In this case, bail. 2550 */ 2551 if (sc->need_mcsetup) 2552 return; 2553 sc->need_mcsetup = 1; 2554 2555 /* 2556 * Add a NOP command with interrupt so that we are notified 2557 * when all TX commands have been processed. 2558 */ 2559 txp = sc->fxp_desc.tx_last->tx_next; 2560 txp->tx_mbuf = NULL; 2561 txp->tx_cb->cb_status = 0; 2562 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2563 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2564 /* 2565 * Advance the end of list forward. 2566 */ 2567 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2568 htole16(~FXP_CB_COMMAND_S); 2569 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2570 sc->fxp_desc.tx_last = txp; 2571 sc->tx_queued++; 2572 /* 2573 * Issue a resume in case the CU has just suspended. 2574 */ 2575 fxp_scb_wait(sc); 2576 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2577 /* 2578 * Set a 5 second timer just in case we don't hear from the 2579 * card again. 2580 */ 2581 ifp->if_timer = 5; 2582 2583 return; 2584 } 2585 sc->need_mcsetup = 0; 2586 2587 /* 2588 * Initialize multicast setup descriptor. 2589 */ 2590 mcsp->cb_status = 0; 2591 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2592 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2593 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2594 txp = &sc->fxp_desc.mcs_tx; 2595 txp->tx_mbuf = NULL; 2596 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2597 txp->tx_next = sc->fxp_desc.tx_list; 2598 (void) fxp_mc_addrs(sc); 2599 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2600 sc->tx_queued = 1; 2601 2602 /* 2603 * Wait until command unit is not active. This should never 2604 * be the case when nothing is queued, but make sure anyway. 2605 */ 2606 count = 100; 2607 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2608 FXP_SCB_CUS_ACTIVE && --count) 2609 DELAY(10); 2610 if (count == 0) { 2611 device_printf(sc->dev, "command queue timeout\n"); 2612 return; 2613 } 2614 2615 /* 2616 * Start the multicast setup command. 2617 */ 2618 fxp_scb_wait(sc); 2619 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2620 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2621 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2622 2623 ifp->if_timer = 2; 2624 return; 2625} 2626 2627static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2628static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2629static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2630static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2631static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2632static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2633 2634#define UCODE(x) x, sizeof(x) 2635 2636struct ucode { 2637 u_int32_t revision; 2638 u_int32_t *ucode; 2639 int length; 2640 u_short int_delay_offset; 2641 u_short bundle_max_offset; 2642} ucode_table[] = { 2643 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2644 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2645 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2646 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2647 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2648 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2649 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2650 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2651 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2652 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2653 { 0, NULL, 0, 0, 0 } 2654}; 2655 2656static void 2657fxp_load_ucode(struct fxp_softc *sc) 2658{ 2659 struct ucode *uc; 2660 struct fxp_cb_ucode *cbp; 2661 2662 for (uc = ucode_table; uc->ucode != NULL; uc++) 2663 if (sc->revision == uc->revision) 2664 break; 2665 if (uc->ucode == NULL) 2666 return; 2667 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2668 cbp->cb_status = 0; 2669 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2670 cbp->link_addr = 0xffffffff; /* (no) next command */ 2671 memcpy(cbp->ucode, uc->ucode, uc->length); 2672 if (uc->int_delay_offset) 2673 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2674 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2675 if (uc->bundle_max_offset) 2676 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2677 htole16(sc->tunable_bundle_max); 2678 /* 2679 * Download the ucode to the chip. 2680 */ 2681 fxp_scb_wait(sc); 2682 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2683 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2684 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2685 /* ...and wait for it to complete. */ 2686 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2687 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2688 device_printf(sc->dev, 2689 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2690 sc->tunable_int_delay, 2691 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2692 sc->flags |= FXP_FLAG_UCODE; 2693} 2694 2695static int 2696sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2697{ 2698 int error, value; 2699 2700 value = *(int *)arg1; 2701 error = sysctl_handle_int(oidp, &value, 0, req); 2702 if (error || !req->newptr) 2703 return (error); 2704 if (value < low || value > high) 2705 return (EINVAL); 2706 *(int *)arg1 = value; 2707 return (0); 2708} 2709 2710/* 2711 * Interrupt delay is expressed in microseconds, a multiplier is used 2712 * to convert this to the appropriate clock ticks before using. 2713 */ 2714static int 2715sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2716{ 2717 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2718} 2719 2720static int 2721sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2722{ 2723 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2724} 2725