if_fxp.c revision 113506
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30/* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 113506 2003-04-15 06:37:30Z mdodd $"); 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49 50#include <net/bpf.h> 51#include <sys/sockio.h> 52#include <sys/bus.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if_arp.h> 59 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <pci/pcivar.h> 73#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, pci, 1, 1, 1); 83MODULE_DEPEND(fxp, ether, 1, 1, 1); 84MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85#include "miibus_if.h" 86 87/* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96#define RFA_ALIGNMENT_FUDGE 2 97 98/* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103static int tx_threshold = 64; 104 105/* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139}; 140 141struct fxp_ident { 142 u_int16_t devid; 143 char *name; 144}; 145 146/* 147 * Claim various Intel PCI device identifiers for this driver. The 148 * sub-vendor and sub-device field are extensively used to identify 149 * particular variants, but we don't currently differentiate between 150 * them. 151 */ 152static struct fxp_ident fxp_ident_table[] = { 153 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 154 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 155 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 164 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 170 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 172 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 173 { 0, NULL }, 174}; 175 176#ifdef FXP_IP_CSUM_WAR 177#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 178#else 179#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 180#endif 181 182static int fxp_probe(device_t dev); 183static int fxp_attach(device_t dev); 184static int fxp_detach(device_t dev); 185static int fxp_shutdown(device_t dev); 186static int fxp_suspend(device_t dev); 187static int fxp_resume(device_t dev); 188 189static void fxp_intr(void *xsc); 190static void fxp_init(void *xsc); 191static void fxp_tick(void *xsc); 192static void fxp_powerstate_d0(device_t dev); 193static void fxp_start(struct ifnet *ifp); 194static void fxp_stop(struct fxp_softc *sc); 195static void fxp_release(struct fxp_softc *sc); 196static int fxp_ioctl(struct ifnet *ifp, u_long command, 197 caddr_t data); 198static void fxp_watchdog(struct ifnet *ifp); 199static int fxp_add_rfabuf(struct fxp_softc *sc, 200 struct fxp_rx *rxp); 201static int fxp_mc_addrs(struct fxp_softc *sc); 202static void fxp_mc_setup(struct fxp_softc *sc); 203static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 204 int autosize); 205static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 206 u_int16_t data); 207static void fxp_autosize_eeprom(struct fxp_softc *sc); 208static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 209 int offset, int words); 210static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 211 int offset, int words); 212static int fxp_ifmedia_upd(struct ifnet *ifp); 213static void fxp_ifmedia_sts(struct ifnet *ifp, 214 struct ifmediareq *ifmr); 215static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 216static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 217 struct ifmediareq *ifmr); 218static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 219static void fxp_miibus_writereg(device_t dev, int phy, int reg, 220 int value); 221static void fxp_load_ucode(struct fxp_softc *sc); 222static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 223 int low, int high); 224static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 225static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 226static __inline void fxp_scb_wait(struct fxp_softc *sc); 227static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 228static __inline void fxp_dma_wait(struct fxp_softc *sc, 229 volatile u_int16_t *status, bus_dma_tag_t dmat, 230 bus_dmamap_t map); 231 232static device_method_t fxp_methods[] = { 233 /* Device interface */ 234 DEVMETHOD(device_probe, fxp_probe), 235 DEVMETHOD(device_attach, fxp_attach), 236 DEVMETHOD(device_detach, fxp_detach), 237 DEVMETHOD(device_shutdown, fxp_shutdown), 238 DEVMETHOD(device_suspend, fxp_suspend), 239 DEVMETHOD(device_resume, fxp_resume), 240 241 /* MII interface */ 242 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 243 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 244 245 { 0, 0 } 246}; 247 248static driver_t fxp_driver = { 249 "fxp", 250 fxp_methods, 251 sizeof(struct fxp_softc), 252}; 253 254static devclass_t fxp_devclass; 255 256DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 257DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 258DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 259 260static int fxp_rnr; 261SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 262 263/* 264 * Wait for the previous command to be accepted (but not necessarily 265 * completed). 266 */ 267static __inline void 268fxp_scb_wait(struct fxp_softc *sc) 269{ 270 int i = 10000; 271 272 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 273 DELAY(2); 274 if (i == 0) 275 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 276 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 277 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 278 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 279 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 280} 281 282static __inline void 283fxp_scb_cmd(struct fxp_softc *sc, int cmd) 284{ 285 286 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 287 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 288 fxp_scb_wait(sc); 289 } 290 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 291} 292 293static __inline void 294fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 295 bus_dma_tag_t dmat, bus_dmamap_t map) 296{ 297 int i = 10000; 298 299 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 300 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 301 DELAY(2); 302 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 303 } 304 if (i == 0) 305 device_printf(sc->dev, "DMA timeout\n"); 306} 307 308/* 309 * Return identification string if this is device is ours. 310 */ 311static int 312fxp_probe(device_t dev) 313{ 314 u_int16_t devid; 315 struct fxp_ident *ident; 316 317 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 318 devid = pci_get_device(dev); 319 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 320 if (ident->devid == devid) { 321 device_set_desc(dev, ident->name); 322 return (0); 323 } 324 } 325 } 326 return (ENXIO); 327} 328 329static void 330fxp_powerstate_d0(device_t dev) 331{ 332#if __FreeBSD_version >= 430002 333 u_int32_t iobase, membase, irq; 334 335 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 336 /* Save important PCI config data. */ 337 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 338 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 339 irq = pci_read_config(dev, PCIR_INTLINE, 4); 340 341 /* Reset the power state. */ 342 device_printf(dev, "chip is in D%d power mode " 343 "-- setting to D0\n", pci_get_powerstate(dev)); 344 345 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 346 347 /* Restore PCI config data. */ 348 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 349 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 350 pci_write_config(dev, PCIR_INTLINE, irq, 4); 351 } 352#endif 353} 354 355static void 356fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 357{ 358 u_int32_t *addr; 359 360 if (error) 361 return; 362 363 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 364 addr = arg; 365 *addr = segs->ds_addr; 366} 367 368static int 369fxp_attach(device_t dev) 370{ 371 int error = 0; 372 struct fxp_softc *sc = device_get_softc(dev); 373 struct ifnet *ifp; 374 struct fxp_rx *rxp; 375 u_int32_t val; 376 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 377 int i, rid, m1, m2, prefer_iomap, maxtxseg; 378 int s; 379 380 bzero(sc, sizeof(*sc)); 381 sc->dev = dev; 382 callout_handle_init(&sc->stat_ch); 383 sysctl_ctx_init(&sc->sysctl_ctx); 384 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF | MTX_RECURSE); 386 387 s = splimp(); 388 389 /* 390 * Enable bus mastering. Enable memory/port space too, in case 391 * BIOS/Prom forgot about it. 392 */ 393 pci_enable_busmaster(dev); 394 pci_enable_io(dev, SYS_RES_IOPORT); 395 pci_enable_io(dev, SYS_RES_MEMORY); 396 val = pci_read_config(dev, PCIR_COMMAND, 2); 397 398 fxp_powerstate_d0(dev); 399 400 /* 401 * Figure out which we should try first - memory mapping or i/o mapping? 402 * We default to memory mapping. Then we accept an override from the 403 * command line. Then we check to see which one is enabled. 404 */ 405 m1 = PCIM_CMD_MEMEN; 406 m2 = PCIM_CMD_PORTEN; 407 prefer_iomap = 0; 408 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 409 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 410 m1 = PCIM_CMD_PORTEN; 411 m2 = PCIM_CMD_MEMEN; 412 } 413 414 if (val & m1) { 415 sc->rtp = 416 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 417 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 418 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 419 0, ~0, 1, RF_ACTIVE); 420 } 421 if (sc->mem == NULL && (val & m2)) { 422 sc->rtp = 423 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 424 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 425 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 426 0, ~0, 1, RF_ACTIVE); 427 } 428 429 if (!sc->mem) { 430 device_printf(dev, "could not map device registers\n"); 431 error = ENXIO; 432 goto fail; 433 } 434 if (bootverbose) { 435 device_printf(dev, "using %s space register mapping\n", 436 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 437 } 438 439 sc->sc_st = rman_get_bustag(sc->mem); 440 sc->sc_sh = rman_get_bushandle(sc->mem); 441 442 /* 443 * Allocate our interrupt. 444 */ 445 rid = 0; 446 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 447 RF_SHAREABLE | RF_ACTIVE); 448 if (sc->irq == NULL) { 449 device_printf(dev, "could not map interrupt\n"); 450 error = ENXIO; 451 goto fail; 452 } 453 454 /* 455 * Reset to a stable state. 456 */ 457 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 458 DELAY(10); 459 460 /* 461 * Find out how large of an SEEPROM we have. 462 */ 463 fxp_autosize_eeprom(sc); 464 465 /* 466 * Determine whether we must use the 503 serial interface. 467 */ 468 fxp_read_eeprom(sc, &data, 6, 1); 469 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 470 (data & FXP_PHY_SERIAL_ONLY)) 471 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 472 473 /* 474 * Create the sysctl tree 475 */ 476 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 477 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 478 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 479 if (sc->sysctl_tree == NULL) 480 goto fail; 481 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 482 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 483 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 484 "FXP driver receive interrupt microcode bundling delay"); 485 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 486 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 487 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 488 "FXP driver receive interrupt microcode bundle size limit"); 489 490 /* 491 * Pull in device tunables. 492 */ 493 sc->tunable_int_delay = TUNABLE_INT_DELAY; 494 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 495 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 496 "int_delay", &sc->tunable_int_delay); 497 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 498 "bundle_max", &sc->tunable_bundle_max); 499 500 /* 501 * Find out the chip revision; lump all 82557 revs together. 502 */ 503 fxp_read_eeprom(sc, &data, 5, 1); 504 if ((data >> 8) == 1) 505 sc->revision = FXP_REV_82557; 506 else 507 sc->revision = pci_get_revid(dev); 508 509 /* 510 * Enable workarounds for certain chip revision deficiencies. 511 * 512 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 513 * some systems based a normal 82559 design, have a defect where 514 * the chip can cause a PCI protocol violation if it receives 515 * a CU_RESUME command when it is entering the IDLE state. The 516 * workaround is to disable Dynamic Standby Mode, so the chip never 517 * deasserts CLKRUN#, and always remains in an active state. 518 * 519 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 520 */ 521 i = pci_get_device(dev); 522 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 523 sc->revision >= FXP_REV_82559_A0) { 524 fxp_read_eeprom(sc, &data, 10, 1); 525 if (data & 0x02) { /* STB enable */ 526 u_int16_t cksum; 527 int i; 528 529 device_printf(dev, 530 "Disabling dynamic standby mode in EEPROM\n"); 531 data &= ~0x02; 532 fxp_write_eeprom(sc, &data, 10, 1); 533 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 534 cksum = 0; 535 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 536 fxp_read_eeprom(sc, &data, i, 1); 537 cksum += data; 538 } 539 i = (1 << sc->eeprom_size) - 1; 540 cksum = 0xBABA - cksum; 541 fxp_read_eeprom(sc, &data, i, 1); 542 fxp_write_eeprom(sc, &cksum, i, 1); 543 device_printf(dev, 544 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 545 i, data, cksum); 546#if 1 547 /* 548 * If the user elects to continue, try the software 549 * workaround, as it is better than nothing. 550 */ 551 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 552#endif 553 } 554 } 555 556 /* 557 * If we are not a 82557 chip, we can enable extended features. 558 */ 559 if (sc->revision != FXP_REV_82557) { 560 /* 561 * If MWI is enabled in the PCI configuration, and there 562 * is a valid cacheline size (8 or 16 dwords), then tell 563 * the board to turn on MWI. 564 */ 565 if (val & PCIM_CMD_MWRICEN && 566 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 567 sc->flags |= FXP_FLAG_MWI_ENABLE; 568 569 /* turn on the extended TxCB feature */ 570 sc->flags |= FXP_FLAG_EXT_TXCB; 571 572 /* enable reception of long frames for VLAN */ 573 sc->flags |= FXP_FLAG_LONG_PKT_EN; 574 } 575 576 /* 577 * Enable use of extended RFDs and TCBs for 82550 578 * and later chips. Note: we need extended TXCB support 579 * too, but that's already enabled by the code above. 580 * Be careful to do this only on the right devices. 581 */ 582 583 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 584 sc->rfa_size = sizeof (struct fxp_rfa); 585 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 586 sc->flags |= FXP_FLAG_EXT_RFA; 587 } else { 588 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 589 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 590 } 591 592 /* 593 * Allocate DMA tags and DMA safe memory. 594 */ 595 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 596 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 597 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 598 maxtxseg, MCLBYTES, 0, &sc->fxp_mtag); 599 if (error) { 600 device_printf(dev, "could not allocate dma tag\n"); 601 goto fail; 602 } 603 604 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 605 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 606 sizeof(struct fxp_stats), 0, &sc->fxp_stag); 607 if (error) { 608 device_printf(dev, "could not allocate dma tag\n"); 609 goto fail; 610 } 611 612 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 613 BUS_DMA_NOWAIT, &sc->fxp_smap); 614 if (error) 615 goto failmem; 616 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 617 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 618 if (error) { 619 device_printf(dev, "could not map the stats buffer\n"); 620 goto fail; 621 } 622 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 623 624 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 625 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 626 FXP_TXCB_SZ, 0, &sc->cbl_tag); 627 if (error) { 628 device_printf(dev, "could not allocate dma tag\n"); 629 goto fail; 630 } 631 632 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 633 BUS_DMA_NOWAIT, &sc->cbl_map); 634 if (error) 635 goto failmem; 636 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ); 637 638 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 639 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 640 &sc->fxp_desc.cbl_addr, 0); 641 if (error) { 642 device_printf(dev, "could not map DMA memory\n"); 643 goto fail; 644 } 645 646 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 647 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 648 sizeof(struct fxp_cb_mcs), 0, &sc->mcs_tag); 649 if (error) { 650 device_printf(dev, "could not allocate dma tag\n"); 651 goto fail; 652 } 653 654 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 655 BUS_DMA_NOWAIT, &sc->mcs_map); 656 if (error) 657 goto failmem; 658 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 659 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 660 if (error) { 661 device_printf(dev, "can't map the multicast setup command\n"); 662 goto fail; 663 } 664 665 /* 666 * Pre-allocate the TX DMA maps. 667 */ 668 for (i = 0; i < FXP_NTXCB; i++) { 669 error = bus_dmamap_create(sc->fxp_mtag, 0, 670 &sc->fxp_desc.tx_list[i].tx_map); 671 if (error) { 672 device_printf(dev, "can't create DMA map for TX\n"); 673 goto fail; 674 } 675 } 676 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 677 if (error) { 678 device_printf(dev, "can't create spare DMA map\n"); 679 goto fail; 680 } 681 682 /* 683 * Pre-allocate our receive buffers. 684 */ 685 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 686 for (i = 0; i < FXP_NRFABUFS; i++) { 687 rxp = &sc->fxp_desc.rx_list[i]; 688 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 689 if (error) { 690 device_printf(dev, "can't create DMA map for RX\n"); 691 goto fail; 692 } 693 if (fxp_add_rfabuf(sc, rxp) != 0) 694 goto failmem; 695 } 696 697 /* 698 * Read MAC address. 699 */ 700 fxp_read_eeprom(sc, myea, 0, 3); 701 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 702 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 703 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 704 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 705 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 706 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 707 device_printf(dev, "Ethernet address %6D%s\n", 708 sc->arpcom.ac_enaddr, ":", 709 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 710 if (bootverbose) { 711 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 712 pci_get_vendor(dev), pci_get_device(dev), 713 pci_get_subvendor(dev), pci_get_subdevice(dev), 714 pci_get_revid(dev)); 715 fxp_read_eeprom(sc, &data, 10, 1); 716 device_printf(dev, "Dynamic Standby mode is %s\n", 717 data & 0x02 ? "enabled" : "disabled"); 718 } 719 720 /* 721 * If this is only a 10Mbps device, then there is no MII, and 722 * the PHY will use a serial interface instead. 723 * 724 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 725 * doesn't have a programming interface of any sort. The 726 * media is sensed automatically based on how the link partner 727 * is configured. This is, in essence, manual configuration. 728 */ 729 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 730 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 731 fxp_serial_ifmedia_sts); 732 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 733 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 734 } else { 735 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 736 fxp_ifmedia_sts)) { 737 device_printf(dev, "MII without any PHY!\n"); 738 error = ENXIO; 739 goto fail; 740 } 741 } 742 743 ifp = &sc->arpcom.ac_if; 744 ifp->if_unit = device_get_unit(dev); 745 ifp->if_name = "fxp"; 746 ifp->if_output = ether_output; 747 ifp->if_baudrate = 100000000; 748 ifp->if_init = fxp_init; 749 ifp->if_softc = sc; 750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 751 ifp->if_ioctl = fxp_ioctl; 752 ifp->if_start = fxp_start; 753 ifp->if_watchdog = fxp_watchdog; 754 755 /* Enable checksum offload for 82550 or better chips */ 756 757 if (sc->flags & FXP_FLAG_EXT_RFA) { 758 ifp->if_hwassist = FXP_CSUM_FEATURES; 759 ifp->if_capabilities = IFCAP_HWCSUM; 760 ifp->if_capenable = ifp->if_capabilities; 761 } 762 763 /* 764 * Tell the upper layer(s) we support long frames. 765 */ 766 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 767 ifp->if_capabilities |= IFCAP_VLAN_MTU; 768 769 /* 770 * Let the system queue as many packets as we have available 771 * TX descriptors. 772 */ 773 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 774 775 /* 776 * Attach the interface. 777 */ 778 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 779 780 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 781 fxp_intr, sc, &sc->ih); 782 if (error) { 783 device_printf(dev, "could not setup irq\n"); 784 goto fail; 785 } 786 787 splx(s); 788 return (0); 789 790failmem: 791 device_printf(dev, "Failed to malloc memory\n"); 792 error = ENOMEM; 793fail: 794 splx(s); 795 fxp_release(sc); 796 return (error); 797} 798 799/* 800 * release all resources 801 */ 802static void 803fxp_release(struct fxp_softc *sc) 804{ 805 struct fxp_rx *rxp; 806 struct fxp_tx *txp; 807 int i; 808 809 if (sc->ih) 810 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 811 if (sc->fxp_desc.cbl_list) { 812 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 813 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 814 sc->cbl_map); 815 } 816 if (sc->fxp_stats) { 817 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 818 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 819 } 820 if (sc->mcsp) { 821 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 822 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 823 } 824 if (sc->irq) 825 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 826 if (sc->mem) 827 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 828 if (sc->fxp_mtag) { 829 for (i = 0; i < FXP_NRFABUFS; i++) { 830 rxp = &sc->fxp_desc.rx_list[i]; 831 if (rxp->rx_mbuf != NULL) { 832 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 833 BUS_DMASYNC_POSTREAD); 834 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 835 m_freem(rxp->rx_mbuf); 836 } 837 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 838 } 839 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 840 bus_dma_tag_destroy(sc->fxp_mtag); 841 } 842 if (sc->fxp_stag) { 843 for (i = 0; i < FXP_NTXCB; i++) { 844 txp = &sc->fxp_desc.tx_list[i]; 845 if (txp->tx_mbuf != NULL) { 846 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 847 BUS_DMASYNC_POSTWRITE); 848 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 849 m_freem(txp->tx_mbuf); 850 } 851 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 852 } 853 bus_dma_tag_destroy(sc->fxp_stag); 854 } 855 if (sc->cbl_tag) 856 bus_dma_tag_destroy(sc->cbl_tag); 857 if (sc->mcs_tag) 858 bus_dma_tag_destroy(sc->mcs_tag); 859 860 sysctl_ctx_free(&sc->sysctl_ctx); 861 862 mtx_destroy(&sc->sc_mtx); 863} 864 865/* 866 * Detach interface. 867 */ 868static int 869fxp_detach(device_t dev) 870{ 871 struct fxp_softc *sc = device_get_softc(dev); 872 int s; 873 874 s = splimp(); 875 /* 876 * Close down routes etc. 877 */ 878 ether_ifdetach(&sc->arpcom.ac_if); 879 880 /* 881 * Stop DMA and drop transmit queue. 882 */ 883 if (bus_child_present(dev)) { 884 /* disable interrupts */ 885 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 886 fxp_stop(sc); 887 } 888 889 device_delete_child(dev, sc->miibus); 890 bus_generic_detach(dev); 891 /* 892 * Free all media structures. 893 */ 894 ifmedia_removeall(&sc->sc_media); 895 896 splx(s); 897 898 /* Release our allocated resources. */ 899 fxp_release(sc); 900 return (0); 901} 902 903/* 904 * Device shutdown routine. Called at system shutdown after sync. The 905 * main purpose of this routine is to shut off receiver DMA so that 906 * kernel memory doesn't get clobbered during warmboot. 907 */ 908static int 909fxp_shutdown(device_t dev) 910{ 911 /* 912 * Make sure that DMA is disabled prior to reboot. Not doing 913 * do could allow DMA to corrupt kernel memory during the 914 * reboot before the driver initializes. 915 */ 916 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 917 return (0); 918} 919 920/* 921 * Device suspend routine. Stop the interface and save some PCI 922 * settings in case the BIOS doesn't restore them properly on 923 * resume. 924 */ 925static int 926fxp_suspend(device_t dev) 927{ 928 struct fxp_softc *sc = device_get_softc(dev); 929 int i, s; 930 931 s = splimp(); 932 933 fxp_stop(sc); 934 935 for (i = 0; i < 5; i++) 936 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 937 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 938 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 939 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 940 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 941 942 sc->suspended = 1; 943 944 splx(s); 945 return (0); 946} 947 948/* 949 * Device resume routine. Restore some PCI settings in case the BIOS 950 * doesn't, re-enable busmastering, and restart the interface if 951 * appropriate. 952 */ 953static int 954fxp_resume(device_t dev) 955{ 956 struct fxp_softc *sc = device_get_softc(dev); 957 struct ifnet *ifp = &sc->sc_if; 958 u_int16_t pci_command; 959 int i, s; 960 961 s = splimp(); 962 963 fxp_powerstate_d0(dev); 964 965 /* better way to do this? */ 966 for (i = 0; i < 5; i++) 967 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 968 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 969 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 970 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 971 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 972 973 /* reenable busmastering */ 974 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 975 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 976 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 977 978 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 979 DELAY(10); 980 981 /* reinitialize interface if necessary */ 982 if (ifp->if_flags & IFF_UP) 983 fxp_init(sc); 984 985 sc->suspended = 0; 986 987 splx(s); 988 return (0); 989} 990 991static void 992fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 993{ 994 u_int16_t reg; 995 int x; 996 997 /* 998 * Shift in data. 999 */ 1000 for (x = 1 << (length - 1); x; x >>= 1) { 1001 if (data & x) 1002 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1003 else 1004 reg = FXP_EEPROM_EECS; 1005 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1006 DELAY(1); 1007 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1008 DELAY(1); 1009 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1010 DELAY(1); 1011 } 1012} 1013 1014/* 1015 * Read from the serial EEPROM. Basically, you manually shift in 1016 * the read opcode (one bit at a time) and then shift in the address, 1017 * and then you shift out the data (all of this one bit at a time). 1018 * The word size is 16 bits, so you have to provide the address for 1019 * every 16 bits of data. 1020 */ 1021static u_int16_t 1022fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1023{ 1024 u_int16_t reg, data; 1025 int x; 1026 1027 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1028 /* 1029 * Shift in read opcode. 1030 */ 1031 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1032 /* 1033 * Shift in address. 1034 */ 1035 data = 0; 1036 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1037 if (offset & x) 1038 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1039 else 1040 reg = FXP_EEPROM_EECS; 1041 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1042 DELAY(1); 1043 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1044 DELAY(1); 1045 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1046 DELAY(1); 1047 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1048 data++; 1049 if (autosize && reg == 0) { 1050 sc->eeprom_size = data; 1051 break; 1052 } 1053 } 1054 /* 1055 * Shift out data. 1056 */ 1057 data = 0; 1058 reg = FXP_EEPROM_EECS; 1059 for (x = 1 << 15; x; x >>= 1) { 1060 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1061 DELAY(1); 1062 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1063 data |= x; 1064 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1065 DELAY(1); 1066 } 1067 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1068 DELAY(1); 1069 1070 return (data); 1071} 1072 1073static void 1074fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1075{ 1076 int i; 1077 1078 /* 1079 * Erase/write enable. 1080 */ 1081 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1082 fxp_eeprom_shiftin(sc, 0x4, 3); 1083 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1084 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1085 DELAY(1); 1086 /* 1087 * Shift in write opcode, address, data. 1088 */ 1089 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1090 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1091 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1092 fxp_eeprom_shiftin(sc, data, 16); 1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1094 DELAY(1); 1095 /* 1096 * Wait for EEPROM to finish up. 1097 */ 1098 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1099 DELAY(1); 1100 for (i = 0; i < 1000; i++) { 1101 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1102 break; 1103 DELAY(50); 1104 } 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1106 DELAY(1); 1107 /* 1108 * Erase/write disable. 1109 */ 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1111 fxp_eeprom_shiftin(sc, 0x4, 3); 1112 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1113 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1114 DELAY(1); 1115} 1116 1117/* 1118 * From NetBSD: 1119 * 1120 * Figure out EEPROM size. 1121 * 1122 * 559's can have either 64-word or 256-word EEPROMs, the 558 1123 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1124 * talks about the existance of 16 to 256 word EEPROMs. 1125 * 1126 * The only known sizes are 64 and 256, where the 256 version is used 1127 * by CardBus cards to store CIS information. 1128 * 1129 * The address is shifted in msb-to-lsb, and after the last 1130 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1131 * after which follows the actual data. We try to detect this zero, by 1132 * probing the data-out bit in the EEPROM control register just after 1133 * having shifted in a bit. If the bit is zero, we assume we've 1134 * shifted enough address bits. The data-out should be tri-state, 1135 * before this, which should translate to a logical one. 1136 */ 1137static void 1138fxp_autosize_eeprom(struct fxp_softc *sc) 1139{ 1140 1141 /* guess maximum size of 256 words */ 1142 sc->eeprom_size = 8; 1143 1144 /* autosize */ 1145 (void) fxp_eeprom_getword(sc, 0, 1); 1146} 1147 1148static void 1149fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1150{ 1151 int i; 1152 1153 for (i = 0; i < words; i++) 1154 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1155} 1156 1157static void 1158fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1159{ 1160 int i; 1161 1162 for (i = 0; i < words; i++) 1163 fxp_eeprom_putword(sc, offset + i, data[i]); 1164} 1165 1166static void 1167fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1168 bus_size_t mapsize, int error) 1169{ 1170 struct fxp_softc *sc; 1171 struct fxp_cb_tx *txp; 1172 int i; 1173 1174 if (error) 1175 return; 1176 1177 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1178 1179 sc = arg; 1180 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1181 for (i = 0; i < nseg; i++) { 1182 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1183 /* 1184 * If this is an 82550/82551, then we're using extended 1185 * TxCBs _and_ we're using checksum offload. This means 1186 * that the TxCB is really an IPCB. One major difference 1187 * between the two is that with plain extended TxCBs, 1188 * the bottom half of the TxCB contains two entries from 1189 * the TBD array, whereas IPCBs contain just one entry: 1190 * one entry (8 bytes) has been sacrificed for the TCP/IP 1191 * checksum offload control bits. So to make things work 1192 * right, we have to start filling in the TBD array 1193 * starting from a different place depending on whether 1194 * the chip is an 82550/82551 or not. 1195 */ 1196 if (sc->flags & FXP_FLAG_EXT_RFA) { 1197 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1198 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1199 } else { 1200 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1201 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1202 } 1203 } 1204 txp->tbd_number = nseg; 1205} 1206 1207/* 1208 * Start packet transmission on the interface. 1209 */ 1210static void 1211fxp_start(struct ifnet *ifp) 1212{ 1213 struct fxp_softc *sc = ifp->if_softc; 1214 struct fxp_tx *txp; 1215 struct mbuf *mb_head; 1216 int error; 1217 1218 /* 1219 * See if we need to suspend xmit until the multicast filter 1220 * has been reprogrammed (which can only be done at the head 1221 * of the command chain). 1222 */ 1223 if (sc->need_mcsetup) { 1224 return; 1225 } 1226 1227 txp = NULL; 1228 1229 /* 1230 * We're finished if there is nothing more to add to the list or if 1231 * we're all filled up with buffers to transmit. 1232 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1233 * a NOP command when needed. 1234 */ 1235 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1236 1237 /* 1238 * Grab a packet to transmit. 1239 */ 1240 IF_DEQUEUE(&ifp->if_snd, mb_head); 1241 1242 /* 1243 * Get pointer to next available tx desc. 1244 */ 1245 txp = sc->fxp_desc.tx_last->tx_next; 1246 1247 /* 1248 * Deal with TCP/IP checksum offload. Note that 1249 * in order for TCP checksum offload to work, 1250 * the pseudo header checksum must have already 1251 * been computed and stored in the checksum field 1252 * in the TCP header. The stack should have 1253 * already done this for us. 1254 */ 1255 1256 if (mb_head->m_pkthdr.csum_flags) { 1257 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1258 txp->tx_cb->ipcb_ip_activation_high = 1259 FXP_IPCB_HARDWAREPARSING_ENABLE; 1260 txp->tx_cb->ipcb_ip_schedule = 1261 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1262 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1263 txp->tx_cb->ipcb_ip_schedule |= 1264 FXP_IPCB_TCP_PACKET; 1265 } 1266#ifdef FXP_IP_CSUM_WAR 1267 /* 1268 * XXX The 82550 chip appears to have trouble 1269 * dealing with IP header checksums in very small 1270 * datagrams, namely fragments from 1 to 3 bytes 1271 * in size. For example, say you want to transmit 1272 * a UDP packet of 1473 bytes. The packet will be 1273 * fragmented over two IP datagrams, the latter 1274 * containing only one byte of data. The 82550 will 1275 * botch the header checksum on the 1-byte fragment. 1276 * As long as the datagram contains 4 or more bytes 1277 * of data, you're ok. 1278 * 1279 * The following code attempts to work around this 1280 * problem: if the datagram is less than 38 bytes 1281 * in size (14 bytes ether header, 20 bytes IP header, 1282 * plus 4 bytes of data), we punt and compute the IP 1283 * header checksum by hand. This workaround doesn't 1284 * work very well, however, since it can be fooled 1285 * by things like VLAN tags and IP options that make 1286 * the header sizes/offsets vary. 1287 */ 1288 1289 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1290 if (mb_head->m_pkthdr.len < 38) { 1291 struct ip *ip; 1292 mb_head->m_data += ETHER_HDR_LEN; 1293 ip = mtod(mb_head, struct ip *); 1294 ip->ip_sum = in_cksum(mb_head, 1295 ip->ip_hl << 2); 1296 mb_head->m_data -= ETHER_HDR_LEN; 1297 } else { 1298 txp->tx_cb->ipcb_ip_activation_high = 1299 FXP_IPCB_HARDWAREPARSING_ENABLE; 1300 txp->tx_cb->ipcb_ip_schedule |= 1301 FXP_IPCB_IP_CHECKSUM_ENABLE; 1302 } 1303 } 1304#endif 1305 } 1306 1307 /* 1308 * Go through each of the mbufs in the chain and initialize 1309 * the transmit buffer descriptors with the physical address 1310 * and size of the mbuf. 1311 */ 1312 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1313 mb_head, fxp_dma_map_txbuf, sc, 0); 1314 1315 if (error && error != EFBIG) { 1316 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1317 error); 1318 m_freem(mb_head); 1319 break; 1320 } 1321 1322 if (error) { 1323 struct mbuf *mn; 1324 1325 /* 1326 * We ran out of segments. We have to recopy this 1327 * mbuf chain first. Bail out if we can't get the 1328 * new buffers. 1329 */ 1330 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1331 if (mn == NULL) { 1332 m_freem(mb_head); 1333 break; 1334 } 1335 if (mb_head->m_pkthdr.len > MHLEN) { 1336 MCLGET(mn, M_DONTWAIT); 1337 if ((mn->m_flags & M_EXT) == 0) { 1338 m_freem(mn); 1339 m_freem(mb_head); 1340 break; 1341 } 1342 } 1343 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1344 mtod(mn, caddr_t)); 1345 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1346 m_freem(mb_head); 1347 mb_head = mn; 1348 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1349 mb_head, fxp_dma_map_txbuf, sc, 0); 1350 if (error) { 1351 device_printf(sc->dev, 1352 "can't map mbuf (error %d)\n", error); 1353 m_freem(mb_head); 1354 break; 1355 } 1356 } 1357 1358 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1359 BUS_DMASYNC_PREWRITE); 1360 1361 txp->tx_mbuf = mb_head; 1362 txp->tx_cb->cb_status = 0; 1363 txp->tx_cb->byte_count = 0; 1364 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1365 txp->tx_cb->cb_command = 1366 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1367 FXP_CB_COMMAND_S); 1368 } else { 1369 txp->tx_cb->cb_command = 1370 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1371 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1372 /* 1373 * Set a 5 second timer just in case we don't hear 1374 * from the card again. 1375 */ 1376 ifp->if_timer = 5; 1377 } 1378 txp->tx_cb->tx_threshold = tx_threshold; 1379 1380 /* 1381 * Advance the end of list forward. 1382 */ 1383 1384#ifdef __alpha__ 1385 /* 1386 * On platforms which can't access memory in 16-bit 1387 * granularities, we must prevent the card from DMA'ing 1388 * up the status while we update the command field. 1389 * This could cause us to overwrite the completion status. 1390 * XXX This is probably bogus and we're _not_ looking 1391 * for atomicity here. 1392 */ 1393 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1394 htole16(FXP_CB_COMMAND_S)); 1395#else 1396 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1397 htole16(~FXP_CB_COMMAND_S); 1398#endif /*__alpha__*/ 1399 sc->fxp_desc.tx_last = txp; 1400 1401 /* 1402 * Advance the beginning of the list forward if there are 1403 * no other packets queued (when nothing is queued, tx_first 1404 * sits on the last TxCB that was sent out). 1405 */ 1406 if (sc->tx_queued == 0) 1407 sc->fxp_desc.tx_first = txp; 1408 1409 sc->tx_queued++; 1410 1411 /* 1412 * Pass packet to bpf if there is a listener. 1413 */ 1414 BPF_MTAP(ifp, mb_head); 1415 } 1416 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1417 1418 /* 1419 * We're finished. If we added to the list, issue a RESUME to get DMA 1420 * going again if suspended. 1421 */ 1422 if (txp != NULL) { 1423 fxp_scb_wait(sc); 1424 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1425 } 1426} 1427 1428static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1429 1430#ifdef DEVICE_POLLING 1431static poll_handler_t fxp_poll; 1432 1433static void 1434fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1435{ 1436 struct fxp_softc *sc = ifp->if_softc; 1437 u_int8_t statack; 1438 1439 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1440 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1441 return; 1442 } 1443 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1444 FXP_SCB_STATACK_FR; 1445 if (cmd == POLL_AND_CHECK_STATUS) { 1446 u_int8_t tmp; 1447 1448 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1449 if (tmp == 0xff || tmp == 0) 1450 return; /* nothing to do */ 1451 tmp &= ~statack; 1452 /* ack what we can */ 1453 if (tmp != 0) 1454 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1455 statack |= tmp; 1456 } 1457 fxp_intr_body(sc, statack, count); 1458} 1459#endif /* DEVICE_POLLING */ 1460 1461/* 1462 * Process interface interrupts. 1463 */ 1464static void 1465fxp_intr(void *xsc) 1466{ 1467 struct fxp_softc *sc = xsc; 1468 u_int8_t statack; 1469 1470#ifdef DEVICE_POLLING 1471 struct ifnet *ifp = &sc->sc_if; 1472 1473 if (ifp->if_flags & IFF_POLLING) 1474 return; 1475 if (ether_poll_register(fxp_poll, ifp)) { 1476 /* disable interrupts */ 1477 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1478 fxp_poll(ifp, 0, 1); 1479 return; 1480 } 1481#endif 1482 1483 if (sc->suspended) { 1484 return; 1485 } 1486 1487 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1488 /* 1489 * It should not be possible to have all bits set; the 1490 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1491 * all bits are set, this may indicate that the card has 1492 * been physically ejected, so ignore it. 1493 */ 1494 if (statack == 0xff) 1495 return; 1496 1497 /* 1498 * First ACK all the interrupts in this pass. 1499 */ 1500 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1501 fxp_intr_body(sc, statack, -1); 1502 } 1503} 1504 1505static void 1506fxp_txeof(struct fxp_softc *sc) 1507{ 1508 struct fxp_tx *txp; 1509 1510 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1511 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1512 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1513 txp = txp->tx_next) { 1514 if (txp->tx_mbuf != NULL) { 1515 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1516 BUS_DMASYNC_POSTWRITE); 1517 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1518 m_freem(txp->tx_mbuf); 1519 txp->tx_mbuf = NULL; 1520 /* clear this to reset csum offload bits */ 1521 txp->tx_cb->tbd[0].tb_addr = 0; 1522 } 1523 sc->tx_queued--; 1524 } 1525 sc->fxp_desc.tx_first = txp; 1526 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1527} 1528 1529static void 1530fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1531{ 1532 struct ifnet *ifp = &sc->sc_if; 1533 struct mbuf *m; 1534 struct fxp_rx *rxp; 1535 struct fxp_rfa *rfa; 1536 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1537 1538 if (rnr) 1539 fxp_rnr++; 1540#ifdef DEVICE_POLLING 1541 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1542 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1543 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1544 rnr = 1; 1545 } 1546#endif 1547 1548 /* 1549 * Free any finished transmit mbuf chains. 1550 * 1551 * Handle the CNA event likt a CXTNO event. It used to 1552 * be that this event (control unit not ready) was not 1553 * encountered, but it is now with the SMPng modifications. 1554 * The exact sequence of events that occur when the interface 1555 * is brought up are different now, and if this event 1556 * goes unhandled, the configuration/rxfilter setup sequence 1557 * can stall for several seconds. The result is that no 1558 * packets go out onto the wire for about 5 to 10 seconds 1559 * after the interface is ifconfig'ed for the first time. 1560 */ 1561 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1562 fxp_txeof(sc); 1563 1564 ifp->if_timer = 0; 1565 if (sc->tx_queued == 0) { 1566 if (sc->need_mcsetup) 1567 fxp_mc_setup(sc); 1568 } 1569 /* 1570 * Try to start more packets transmitting. 1571 */ 1572 if (ifp->if_snd.ifq_head != NULL) 1573 fxp_start(ifp); 1574 } 1575 1576 /* 1577 * Just return if nothing happened on the receive side. 1578 */ 1579 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1580 return; 1581 1582 /* 1583 * Process receiver interrupts. If a no-resource (RNR) 1584 * condition exists, get whatever packets we can and 1585 * re-start the receiver. 1586 * 1587 * When using polling, we do not process the list to completion, 1588 * so when we get an RNR interrupt we must defer the restart 1589 * until we hit the last buffer with the C bit set. 1590 * If we run out of cycles and rfa_headm has the C bit set, 1591 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1592 * that the info will be used in the subsequent polling cycle. 1593 */ 1594 for (;;) { 1595 rxp = sc->fxp_desc.rx_head; 1596 m = rxp->rx_mbuf; 1597 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1598 RFA_ALIGNMENT_FUDGE); 1599 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1600 BUS_DMASYNC_POSTREAD); 1601 1602#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1603 if (count >= 0 && count-- == 0) { 1604 if (rnr) { 1605 /* Defer RNR processing until the next time. */ 1606 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1607 rnr = 0; 1608 } 1609 break; 1610 } 1611#endif /* DEVICE_POLLING */ 1612 1613 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1614 break; 1615 1616 /* 1617 * Advance head forward. 1618 */ 1619 sc->fxp_desc.rx_head = rxp->rx_next; 1620 1621 /* 1622 * Add a new buffer to the receive chain. 1623 * If this fails, the old buffer is recycled 1624 * instead. 1625 */ 1626 if (fxp_add_rfabuf(sc, rxp) == 0) { 1627 int total_len; 1628 1629 /* 1630 * Fetch packet length (the top 2 bits of 1631 * actual_size are flags set by the controller 1632 * upon completion), and drop the packet in case 1633 * of bogus length or CRC errors. 1634 */ 1635 total_len = le16toh(rfa->actual_size) & 0x3fff; 1636 if (total_len < sizeof(struct ether_header) || 1637 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1638 sc->rfa_size || 1639 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1640 m_freem(m); 1641 continue; 1642 } 1643 1644 /* Do IP checksum checking. */ 1645 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1646 if (rfa->rfax_csum_sts & 1647 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1648 m->m_pkthdr.csum_flags |= 1649 CSUM_IP_CHECKED; 1650 if (rfa->rfax_csum_sts & 1651 FXP_RFDX_CS_IP_CSUM_VALID) 1652 m->m_pkthdr.csum_flags |= 1653 CSUM_IP_VALID; 1654 if ((rfa->rfax_csum_sts & 1655 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1656 (rfa->rfax_csum_sts & 1657 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1658 m->m_pkthdr.csum_flags |= 1659 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1660 m->m_pkthdr.csum_data = 0xffff; 1661 } 1662 } 1663 1664 m->m_pkthdr.len = m->m_len = total_len; 1665 m->m_pkthdr.rcvif = ifp; 1666 1667 (*ifp->if_input)(ifp, m); 1668 } 1669 } 1670 if (rnr) { 1671 fxp_scb_wait(sc); 1672 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1673 sc->fxp_desc.rx_head->rx_addr); 1674 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1675 } 1676} 1677 1678/* 1679 * Update packet in/out/collision statistics. The i82557 doesn't 1680 * allow you to access these counters without doing a fairly 1681 * expensive DMA to get _all_ of the statistics it maintains, so 1682 * we do this operation here only once per second. The statistics 1683 * counters in the kernel are updated from the previous dump-stats 1684 * DMA and then a new dump-stats DMA is started. The on-chip 1685 * counters are zeroed when the DMA completes. If we can't start 1686 * the DMA immediately, we don't wait - we just prepare to read 1687 * them again next time. 1688 */ 1689static void 1690fxp_tick(void *xsc) 1691{ 1692 struct fxp_softc *sc = xsc; 1693 struct ifnet *ifp = &sc->sc_if; 1694 struct fxp_stats *sp = sc->fxp_stats; 1695 int s; 1696 1697 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1698 ifp->if_opackets += le32toh(sp->tx_good); 1699 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1700 if (sp->rx_good) { 1701 ifp->if_ipackets += le32toh(sp->rx_good); 1702 sc->rx_idle_secs = 0; 1703 } else { 1704 /* 1705 * Receiver's been idle for another second. 1706 */ 1707 sc->rx_idle_secs++; 1708 } 1709 ifp->if_ierrors += 1710 le32toh(sp->rx_crc_errors) + 1711 le32toh(sp->rx_alignment_errors) + 1712 le32toh(sp->rx_rnr_errors) + 1713 le32toh(sp->rx_overrun_errors); 1714 /* 1715 * If any transmit underruns occured, bump up the transmit 1716 * threshold by another 512 bytes (64 * 8). 1717 */ 1718 if (sp->tx_underruns) { 1719 ifp->if_oerrors += le32toh(sp->tx_underruns); 1720 if (tx_threshold < 192) 1721 tx_threshold += 64; 1722 } 1723 s = splimp(); 1724 /* 1725 * Release any xmit buffers that have completed DMA. This isn't 1726 * strictly necessary to do here, but it's advantagous for mbufs 1727 * with external storage to be released in a timely manner rather 1728 * than being defered for a potentially long time. This limits 1729 * the delay to a maximum of one second. 1730 */ 1731 fxp_txeof(sc); 1732 1733 /* 1734 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1735 * then assume the receiver has locked up and attempt to clear 1736 * the condition by reprogramming the multicast filter. This is 1737 * a work-around for a bug in the 82557 where the receiver locks 1738 * up if it gets certain types of garbage in the syncronization 1739 * bits prior to the packet header. This bug is supposed to only 1740 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1741 * mode as well (perhaps due to a 10/100 speed transition). 1742 */ 1743 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1744 sc->rx_idle_secs = 0; 1745 fxp_mc_setup(sc); 1746 } 1747 /* 1748 * If there is no pending command, start another stats 1749 * dump. Otherwise punt for now. 1750 */ 1751 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1752 /* 1753 * Start another stats dump. 1754 */ 1755 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1756 BUS_DMASYNC_PREREAD); 1757 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1758 } else { 1759 /* 1760 * A previous command is still waiting to be accepted. 1761 * Just zero our copy of the stats and wait for the 1762 * next timer event to update them. 1763 */ 1764 sp->tx_good = 0; 1765 sp->tx_underruns = 0; 1766 sp->tx_total_collisions = 0; 1767 1768 sp->rx_good = 0; 1769 sp->rx_crc_errors = 0; 1770 sp->rx_alignment_errors = 0; 1771 sp->rx_rnr_errors = 0; 1772 sp->rx_overrun_errors = 0; 1773 } 1774 if (sc->miibus != NULL) 1775 mii_tick(device_get_softc(sc->miibus)); 1776 splx(s); 1777 /* 1778 * Schedule another timeout one second from now. 1779 */ 1780 sc->stat_ch = timeout(fxp_tick, sc, hz); 1781} 1782 1783/* 1784 * Stop the interface. Cancels the statistics updater and resets 1785 * the interface. 1786 */ 1787static void 1788fxp_stop(struct fxp_softc *sc) 1789{ 1790 struct ifnet *ifp = &sc->sc_if; 1791 struct fxp_tx *txp; 1792 int i; 1793 1794 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1795 ifp->if_timer = 0; 1796 1797#ifdef DEVICE_POLLING 1798 ether_poll_deregister(ifp); 1799#endif 1800 /* 1801 * Cancel stats updater. 1802 */ 1803 untimeout(fxp_tick, sc, sc->stat_ch); 1804 1805 /* 1806 * Issue software reset, which also unloads the microcode. 1807 */ 1808 sc->flags &= ~FXP_FLAG_UCODE; 1809 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1810 DELAY(50); 1811 1812 /* 1813 * Release any xmit buffers. 1814 */ 1815 txp = sc->fxp_desc.tx_list; 1816 if (txp != NULL) { 1817 for (i = 0; i < FXP_NTXCB; i++) { 1818 if (txp[i].tx_mbuf != NULL) { 1819 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1820 BUS_DMASYNC_POSTWRITE); 1821 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1822 m_freem(txp[i].tx_mbuf); 1823 txp[i].tx_mbuf = NULL; 1824 /* clear this to reset csum offload bits */ 1825 txp[i].tx_cb->tbd[0].tb_addr = 0; 1826 } 1827 } 1828 } 1829 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1830 sc->tx_queued = 0; 1831} 1832 1833/* 1834 * Watchdog/transmission transmit timeout handler. Called when a 1835 * transmission is started on the interface, but no interrupt is 1836 * received before the timeout. This usually indicates that the 1837 * card has wedged for some reason. 1838 */ 1839static void 1840fxp_watchdog(struct ifnet *ifp) 1841{ 1842 struct fxp_softc *sc = ifp->if_softc; 1843 1844 device_printf(sc->dev, "device timeout\n"); 1845 ifp->if_oerrors++; 1846 1847 fxp_init(sc); 1848} 1849 1850static void 1851fxp_init(void *xsc) 1852{ 1853 struct fxp_softc *sc = xsc; 1854 struct ifnet *ifp = &sc->sc_if; 1855 struct fxp_cb_config *cbp; 1856 struct fxp_cb_ias *cb_ias; 1857 struct fxp_cb_tx *tcbp; 1858 struct fxp_tx *txp; 1859 struct fxp_cb_mcs *mcsp; 1860 int i, prm, s; 1861 1862 s = splimp(); 1863 /* 1864 * Cancel any pending I/O 1865 */ 1866 fxp_stop(sc); 1867 1868 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1869 1870 /* 1871 * Initialize base of CBL and RFA memory. Loading with zero 1872 * sets it up for regular linear addressing. 1873 */ 1874 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1875 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1876 1877 fxp_scb_wait(sc); 1878 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1879 1880 /* 1881 * Initialize base of dump-stats buffer. 1882 */ 1883 fxp_scb_wait(sc); 1884 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1885 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1886 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1887 1888 /* 1889 * Attempt to load microcode if requested. 1890 */ 1891 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1892 fxp_load_ucode(sc); 1893 1894 /* 1895 * Initialize the multicast address list. 1896 */ 1897 if (fxp_mc_addrs(sc)) { 1898 mcsp = sc->mcsp; 1899 mcsp->cb_status = 0; 1900 mcsp->cb_command = 1901 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1902 mcsp->link_addr = 0xffffffff; 1903 /* 1904 * Start the multicast setup command. 1905 */ 1906 fxp_scb_wait(sc); 1907 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1908 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1909 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1910 /* ...and wait for it to complete. */ 1911 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1912 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1913 BUS_DMASYNC_POSTWRITE); 1914 } 1915 1916 /* 1917 * We temporarily use memory that contains the TxCB list to 1918 * construct the config CB. The TxCB list memory is rebuilt 1919 * later. 1920 */ 1921 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1922 1923 /* 1924 * This bcopy is kind of disgusting, but there are a bunch of must be 1925 * zero and must be one bits in this structure and this is the easiest 1926 * way to initialize them all to proper values. 1927 */ 1928 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1929 1930 cbp->cb_status = 0; 1931 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1932 FXP_CB_COMMAND_EL); 1933 cbp->link_addr = 0xffffffff; /* (no) next command */ 1934 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1935 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1936 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1937 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1938 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1939 cbp->type_enable = 0; /* actually reserved */ 1940 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1941 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1942 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1943 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1944 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1945 cbp->late_scb = 0; /* (don't) defer SCB update */ 1946 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1947 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1948 cbp->ci_int = 1; /* interrupt on CU idle */ 1949 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1950 cbp->ext_stats_dis = 1; /* disable extended counters */ 1951 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1952 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1953 cbp->disc_short_rx = !prm; /* discard short packets */ 1954 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1955 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1956 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1957 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1958 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1959 cbp->csma_dis = 0; /* (don't) disable link */ 1960 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1961 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1962 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1963 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1964 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1965 cbp->nsai = 1; /* (don't) disable source addr insert */ 1966 cbp->preamble_length = 2; /* (7 byte) preamble */ 1967 cbp->loopback = 0; /* (don't) loopback */ 1968 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1969 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1970 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1971 cbp->promiscuous = prm; /* promiscuous mode */ 1972 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1973 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1974 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1975 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1976 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1977 1978 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1979 cbp->padding = 1; /* (do) pad short tx packets */ 1980 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1981 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1982 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1983 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1984 /* must set wake_en in PMCSR also */ 1985 cbp->force_fdx = 0; /* (don't) force full duplex */ 1986 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1987 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1988 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1989 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1990 1991 if (sc->revision == FXP_REV_82557) { 1992 /* 1993 * The 82557 has no hardware flow control, the values 1994 * below are the defaults for the chip. 1995 */ 1996 cbp->fc_delay_lsb = 0; 1997 cbp->fc_delay_msb = 0x40; 1998 cbp->pri_fc_thresh = 3; 1999 cbp->tx_fc_dis = 0; 2000 cbp->rx_fc_restop = 0; 2001 cbp->rx_fc_restart = 0; 2002 cbp->fc_filter = 0; 2003 cbp->pri_fc_loc = 1; 2004 } else { 2005 cbp->fc_delay_lsb = 0x1f; 2006 cbp->fc_delay_msb = 0x01; 2007 cbp->pri_fc_thresh = 3; 2008 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2009 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2010 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2011 cbp->fc_filter = !prm; /* drop FC frames to host */ 2012 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2013 } 2014 2015 /* 2016 * Start the config command/DMA. 2017 */ 2018 fxp_scb_wait(sc); 2019 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2020 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2021 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2022 /* ...and wait for it to complete. */ 2023 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2024 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2025 2026 /* 2027 * Now initialize the station address. Temporarily use the TxCB 2028 * memory area like we did above for the config CB. 2029 */ 2030 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2031 cb_ias->cb_status = 0; 2032 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2033 cb_ias->link_addr = 0xffffffff; 2034 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2035 sizeof(sc->arpcom.ac_enaddr)); 2036 2037 /* 2038 * Start the IAS (Individual Address Setup) command/DMA. 2039 */ 2040 fxp_scb_wait(sc); 2041 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2042 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2043 /* ...and wait for it to complete. */ 2044 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2045 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2046 2047 /* 2048 * Initialize transmit control block (TxCB) list. 2049 */ 2050 txp = sc->fxp_desc.tx_list; 2051 tcbp = sc->fxp_desc.cbl_list; 2052 bzero(tcbp, FXP_TXCB_SZ); 2053 for (i = 0; i < FXP_NTXCB; i++) { 2054 txp[i].tx_cb = tcbp + i; 2055 txp[i].tx_mbuf = NULL; 2056 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2057 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2058 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2059 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2060 if (sc->flags & FXP_FLAG_EXT_TXCB) 2061 tcbp[i].tbd_array_addr = 2062 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2063 else 2064 tcbp[i].tbd_array_addr = 2065 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2066 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2067 } 2068 /* 2069 * Set the suspend flag on the first TxCB and start the control 2070 * unit. It will execute the NOP and then suspend. 2071 */ 2072 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2073 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2074 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2075 sc->tx_queued = 1; 2076 2077 fxp_scb_wait(sc); 2078 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2079 2080 /* 2081 * Initialize receiver buffer area - RFA. 2082 */ 2083 fxp_scb_wait(sc); 2084 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2085 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2086 2087 /* 2088 * Set current media. 2089 */ 2090 if (sc->miibus != NULL) 2091 mii_mediachg(device_get_softc(sc->miibus)); 2092 2093 ifp->if_flags |= IFF_RUNNING; 2094 ifp->if_flags &= ~IFF_OACTIVE; 2095 2096 /* 2097 * Enable interrupts. 2098 */ 2099#ifdef DEVICE_POLLING 2100 /* 2101 * ... but only do that if we are not polling. And because (presumably) 2102 * the default is interrupts on, we need to disable them explicitly! 2103 */ 2104 if ( ifp->if_flags & IFF_POLLING ) 2105 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2106 else 2107#endif /* DEVICE_POLLING */ 2108 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2109 splx(s); 2110 2111 /* 2112 * Start stats updater. 2113 */ 2114 sc->stat_ch = timeout(fxp_tick, sc, hz); 2115} 2116 2117static int 2118fxp_serial_ifmedia_upd(struct ifnet *ifp) 2119{ 2120 2121 return (0); 2122} 2123 2124static void 2125fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2126{ 2127 2128 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2129} 2130 2131/* 2132 * Change media according to request. 2133 */ 2134static int 2135fxp_ifmedia_upd(struct ifnet *ifp) 2136{ 2137 struct fxp_softc *sc = ifp->if_softc; 2138 struct mii_data *mii; 2139 2140 mii = device_get_softc(sc->miibus); 2141 mii_mediachg(mii); 2142 return (0); 2143} 2144 2145/* 2146 * Notify the world which media we're using. 2147 */ 2148static void 2149fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2150{ 2151 struct fxp_softc *sc = ifp->if_softc; 2152 struct mii_data *mii; 2153 2154 mii = device_get_softc(sc->miibus); 2155 mii_pollstat(mii); 2156 ifmr->ifm_active = mii->mii_media_active; 2157 ifmr->ifm_status = mii->mii_media_status; 2158 2159 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2160 sc->cu_resume_bug = 1; 2161 else 2162 sc->cu_resume_bug = 0; 2163} 2164 2165/* 2166 * Add a buffer to the end of the RFA buffer list. 2167 * Return 0 if successful, 1 for failure. A failure results in 2168 * adding the 'oldm' (if non-NULL) on to the end of the list - 2169 * tossing out its old contents and recycling it. 2170 * The RFA struct is stuck at the beginning of mbuf cluster and the 2171 * data pointer is fixed up to point just past it. 2172 */ 2173static int 2174fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2175{ 2176 struct mbuf *m; 2177 struct fxp_rfa *rfa, *p_rfa; 2178 struct fxp_rx *p_rx; 2179 bus_dmamap_t tmp_map; 2180 int error; 2181 2182 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2183 if (m == NULL) 2184 return (ENOBUFS); 2185 2186 /* 2187 * Move the data pointer up so that the incoming data packet 2188 * will be 32-bit aligned. 2189 */ 2190 m->m_data += RFA_ALIGNMENT_FUDGE; 2191 2192 /* 2193 * Get a pointer to the base of the mbuf cluster and move 2194 * data start past it. 2195 */ 2196 rfa = mtod(m, struct fxp_rfa *); 2197 m->m_data += sc->rfa_size; 2198 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2199 2200 /* 2201 * Initialize the rest of the RFA. Note that since the RFA 2202 * is misaligned, we cannot store values directly. Instead, 2203 * we use an optimized, inline copy. 2204 */ 2205 2206 rfa->rfa_status = 0; 2207 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2208 rfa->actual_size = 0; 2209 2210 le32enc(&rfa->link_addr, 0xffffffff); 2211 le32enc(&rfa->rbd_addr, 0xffffffff); 2212 2213 /* Map the RFA into DMA memory. */ 2214 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2215 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2216 &rxp->rx_addr, 0); 2217 if (error) { 2218 m_freem(m); 2219 return (error); 2220 } 2221 2222 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2223 tmp_map = sc->spare_map; 2224 sc->spare_map = rxp->rx_map; 2225 rxp->rx_map = tmp_map; 2226 rxp->rx_mbuf = m; 2227 2228 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2230 2231 /* 2232 * If there are other buffers already on the list, attach this 2233 * one to the end by fixing up the tail to point to this one. 2234 */ 2235 if (sc->fxp_desc.rx_head != NULL) { 2236 p_rx = sc->fxp_desc.rx_tail; 2237 p_rfa = (struct fxp_rfa *) 2238 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2239 p_rx->rx_next = rxp; 2240 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2241 p_rfa->rfa_control = 0; 2242 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2243 BUS_DMASYNC_PREWRITE); 2244 } else { 2245 rxp->rx_next = NULL; 2246 sc->fxp_desc.rx_head = rxp; 2247 } 2248 sc->fxp_desc.rx_tail = rxp; 2249 return (0); 2250} 2251 2252static volatile int 2253fxp_miibus_readreg(device_t dev, int phy, int reg) 2254{ 2255 struct fxp_softc *sc = device_get_softc(dev); 2256 int count = 10000; 2257 int value; 2258 2259 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2260 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2261 2262 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2263 && count--) 2264 DELAY(10); 2265 2266 if (count <= 0) 2267 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2268 2269 return (value & 0xffff); 2270} 2271 2272static void 2273fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2274{ 2275 struct fxp_softc *sc = device_get_softc(dev); 2276 int count = 10000; 2277 2278 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2279 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2280 (value & 0xffff)); 2281 2282 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2283 count--) 2284 DELAY(10); 2285 2286 if (count <= 0) 2287 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2288} 2289 2290static int 2291fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2292{ 2293 struct fxp_softc *sc = ifp->if_softc; 2294 struct ifreq *ifr = (struct ifreq *)data; 2295 struct mii_data *mii; 2296 int s, error = 0; 2297 2298 s = splimp(); 2299 2300 switch (command) { 2301 case SIOCSIFFLAGS: 2302 if (ifp->if_flags & IFF_ALLMULTI) 2303 sc->flags |= FXP_FLAG_ALL_MCAST; 2304 else 2305 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2306 2307 /* 2308 * If interface is marked up and not running, then start it. 2309 * If it is marked down and running, stop it. 2310 * XXX If it's up then re-initialize it. This is so flags 2311 * such as IFF_PROMISC are handled. 2312 */ 2313 if (ifp->if_flags & IFF_UP) { 2314 fxp_init(sc); 2315 } else { 2316 if (ifp->if_flags & IFF_RUNNING) 2317 fxp_stop(sc); 2318 } 2319 break; 2320 2321 case SIOCADDMULTI: 2322 case SIOCDELMULTI: 2323 if (ifp->if_flags & IFF_ALLMULTI) 2324 sc->flags |= FXP_FLAG_ALL_MCAST; 2325 else 2326 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2327 /* 2328 * Multicast list has changed; set the hardware filter 2329 * accordingly. 2330 */ 2331 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2332 fxp_mc_setup(sc); 2333 /* 2334 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2335 * again rather than else {}. 2336 */ 2337 if (sc->flags & FXP_FLAG_ALL_MCAST) 2338 fxp_init(sc); 2339 error = 0; 2340 break; 2341 2342 case SIOCSIFMEDIA: 2343 case SIOCGIFMEDIA: 2344 if (sc->miibus != NULL) { 2345 mii = device_get_softc(sc->miibus); 2346 error = ifmedia_ioctl(ifp, ifr, 2347 &mii->mii_media, command); 2348 } else { 2349 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2350 } 2351 break; 2352 2353 default: 2354 error = ether_ioctl(ifp, command, data); 2355 } 2356 splx(s); 2357 return (error); 2358} 2359 2360/* 2361 * Fill in the multicast address list and return number of entries. 2362 */ 2363static int 2364fxp_mc_addrs(struct fxp_softc *sc) 2365{ 2366 struct fxp_cb_mcs *mcsp = sc->mcsp; 2367 struct ifnet *ifp = &sc->sc_if; 2368 struct ifmultiaddr *ifma; 2369 int nmcasts; 2370 2371 nmcasts = 0; 2372 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2373#if __FreeBSD_version < 500000 2374 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2375#else 2376 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2377#endif 2378 if (ifma->ifma_addr->sa_family != AF_LINK) 2379 continue; 2380 if (nmcasts >= MAXMCADDR) { 2381 sc->flags |= FXP_FLAG_ALL_MCAST; 2382 nmcasts = 0; 2383 break; 2384 } 2385 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2386 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2387 nmcasts++; 2388 } 2389 } 2390 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2391 return (nmcasts); 2392} 2393 2394/* 2395 * Program the multicast filter. 2396 * 2397 * We have an artificial restriction that the multicast setup command 2398 * must be the first command in the chain, so we take steps to ensure 2399 * this. By requiring this, it allows us to keep up the performance of 2400 * the pre-initialized command ring (esp. link pointers) by not actually 2401 * inserting the mcsetup command in the ring - i.e. its link pointer 2402 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2403 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2404 * lead into the regular TxCB ring when it completes. 2405 * 2406 * This function must be called at splimp. 2407 */ 2408static void 2409fxp_mc_setup(struct fxp_softc *sc) 2410{ 2411 struct fxp_cb_mcs *mcsp = sc->mcsp; 2412 struct ifnet *ifp = &sc->sc_if; 2413 struct fxp_tx *txp; 2414 int count; 2415 2416 /* 2417 * If there are queued commands, we must wait until they are all 2418 * completed. If we are already waiting, then add a NOP command 2419 * with interrupt option so that we're notified when all commands 2420 * have been completed - fxp_start() ensures that no additional 2421 * TX commands will be added when need_mcsetup is true. 2422 */ 2423 if (sc->tx_queued) { 2424 /* 2425 * need_mcsetup will be true if we are already waiting for the 2426 * NOP command to be completed (see below). In this case, bail. 2427 */ 2428 if (sc->need_mcsetup) 2429 return; 2430 sc->need_mcsetup = 1; 2431 2432 /* 2433 * Add a NOP command with interrupt so that we are notified 2434 * when all TX commands have been processed. 2435 */ 2436 txp = sc->fxp_desc.tx_last->tx_next; 2437 txp->tx_mbuf = NULL; 2438 txp->tx_cb->cb_status = 0; 2439 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2440 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2441 /* 2442 * Advance the end of list forward. 2443 */ 2444 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2445 htole16(~FXP_CB_COMMAND_S); 2446 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2447 sc->fxp_desc.tx_last = txp; 2448 sc->tx_queued++; 2449 /* 2450 * Issue a resume in case the CU has just suspended. 2451 */ 2452 fxp_scb_wait(sc); 2453 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2454 /* 2455 * Set a 5 second timer just in case we don't hear from the 2456 * card again. 2457 */ 2458 ifp->if_timer = 5; 2459 2460 return; 2461 } 2462 sc->need_mcsetup = 0; 2463 2464 /* 2465 * Initialize multicast setup descriptor. 2466 */ 2467 mcsp->cb_status = 0; 2468 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2469 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2470 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2471 txp = &sc->fxp_desc.mcs_tx; 2472 txp->tx_mbuf = NULL; 2473 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2474 txp->tx_next = sc->fxp_desc.tx_list; 2475 (void) fxp_mc_addrs(sc); 2476 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2477 sc->tx_queued = 1; 2478 2479 /* 2480 * Wait until command unit is not active. This should never 2481 * be the case when nothing is queued, but make sure anyway. 2482 */ 2483 count = 100; 2484 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2485 FXP_SCB_CUS_ACTIVE && --count) 2486 DELAY(10); 2487 if (count == 0) { 2488 device_printf(sc->dev, "command queue timeout\n"); 2489 return; 2490 } 2491 2492 /* 2493 * Start the multicast setup command. 2494 */ 2495 fxp_scb_wait(sc); 2496 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2497 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2498 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2499 2500 ifp->if_timer = 2; 2501 return; 2502} 2503 2504static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2505static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2506static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2507static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2508static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2509static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2510 2511#define UCODE(x) x, sizeof(x) 2512 2513struct ucode { 2514 u_int32_t revision; 2515 u_int32_t *ucode; 2516 int length; 2517 u_short int_delay_offset; 2518 u_short bundle_max_offset; 2519} ucode_table[] = { 2520 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2521 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2522 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2523 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2524 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2525 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2526 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2527 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2528 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2529 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2530 { 0, NULL, 0, 0, 0 } 2531}; 2532 2533static void 2534fxp_load_ucode(struct fxp_softc *sc) 2535{ 2536 struct ucode *uc; 2537 struct fxp_cb_ucode *cbp; 2538 2539 for (uc = ucode_table; uc->ucode != NULL; uc++) 2540 if (sc->revision == uc->revision) 2541 break; 2542 if (uc->ucode == NULL) 2543 return; 2544 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2545 cbp->cb_status = 0; 2546 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2547 cbp->link_addr = 0xffffffff; /* (no) next command */ 2548 memcpy(cbp->ucode, uc->ucode, uc->length); 2549 if (uc->int_delay_offset) 2550 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2551 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2552 if (uc->bundle_max_offset) 2553 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2554 htole16(sc->tunable_bundle_max); 2555 /* 2556 * Download the ucode to the chip. 2557 */ 2558 fxp_scb_wait(sc); 2559 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2560 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2561 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2562 /* ...and wait for it to complete. */ 2563 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2564 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2565 device_printf(sc->dev, 2566 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2567 sc->tunable_int_delay, 2568 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2569 sc->flags |= FXP_FLAG_UCODE; 2570} 2571 2572static int 2573sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2574{ 2575 int error, value; 2576 2577 value = *(int *)arg1; 2578 error = sysctl_handle_int(oidp, &value, 0, req); 2579 if (error || !req->newptr) 2580 return (error); 2581 if (value < low || value > high) 2582 return (EINVAL); 2583 *(int *)arg1 = value; 2584 return (0); 2585} 2586 2587/* 2588 * Interrupt delay is expressed in microseconds, a multiplier is used 2589 * to convert this to the appropriate clock ticks before using. 2590 */ 2591static int 2592sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2593{ 2594 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2595} 2596 2597static int 2598sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2599{ 2600 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2601} 2602