if_fxp.c revision 113360
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30/* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 113360 2003-04-11 12:52:52Z mux $"); 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/endian.h> 40#include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42#include <sys/kernel.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49 50#include <net/bpf.h> 51#include <sys/sockio.h> 52#include <sys/bus.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if_arp.h> 59 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <pci/pcivar.h> 73#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, miibus, 1, 1, 1); 83#include "miibus_if.h" 84 85/* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94#define RFA_ALIGNMENT_FUDGE 2 95 96/* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101static int tx_threshold = 64; 102 103/* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137}; 138 139struct fxp_ident { 140 u_int16_t devid; 141 char *name; 142}; 143 144/* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150static struct fxp_ident fxp_ident_table[] = { 151 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 152 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 153 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 162 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 163 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 164 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 168 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 169 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 170 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 171 { 0, NULL }, 172}; 173 174#ifdef FXP_IP_CSUM_WAR 175#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 176#else 177#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 178#endif 179 180static int fxp_probe(device_t dev); 181static int fxp_attach(device_t dev); 182static int fxp_detach(device_t dev); 183static int fxp_shutdown(device_t dev); 184static int fxp_suspend(device_t dev); 185static int fxp_resume(device_t dev); 186 187static void fxp_intr(void *xsc); 188static void fxp_init(void *xsc); 189static void fxp_tick(void *xsc); 190static void fxp_powerstate_d0(device_t dev); 191static void fxp_start(struct ifnet *ifp); 192static void fxp_stop(struct fxp_softc *sc); 193static void fxp_release(struct fxp_softc *sc); 194static int fxp_ioctl(struct ifnet *ifp, u_long command, 195 caddr_t data); 196static void fxp_watchdog(struct ifnet *ifp); 197static int fxp_add_rfabuf(struct fxp_softc *sc, 198 struct fxp_rx *rxp); 199static int fxp_mc_addrs(struct fxp_softc *sc); 200static void fxp_mc_setup(struct fxp_softc *sc); 201static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 202 int autosize); 203static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 204 u_int16_t data); 205static void fxp_autosize_eeprom(struct fxp_softc *sc); 206static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 207 int offset, int words); 208static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 209 int offset, int words); 210static int fxp_ifmedia_upd(struct ifnet *ifp); 211static void fxp_ifmedia_sts(struct ifnet *ifp, 212 struct ifmediareq *ifmr); 213static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 214static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 215 struct ifmediareq *ifmr); 216static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 217static void fxp_miibus_writereg(device_t dev, int phy, int reg, 218 int value); 219static void fxp_load_ucode(struct fxp_softc *sc); 220static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 221 int low, int high); 222static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 223static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 224static __inline void fxp_scb_wait(struct fxp_softc *sc); 225static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 226static __inline void fxp_dma_wait(struct fxp_softc *sc, 227 volatile u_int16_t *status, bus_dma_tag_t dmat, 228 bus_dmamap_t map); 229 230static device_method_t fxp_methods[] = { 231 /* Device interface */ 232 DEVMETHOD(device_probe, fxp_probe), 233 DEVMETHOD(device_attach, fxp_attach), 234 DEVMETHOD(device_detach, fxp_detach), 235 DEVMETHOD(device_shutdown, fxp_shutdown), 236 DEVMETHOD(device_suspend, fxp_suspend), 237 DEVMETHOD(device_resume, fxp_resume), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 241 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 242 243 { 0, 0 } 244}; 245 246static driver_t fxp_driver = { 247 "fxp", 248 fxp_methods, 249 sizeof(struct fxp_softc), 250}; 251 252static devclass_t fxp_devclass; 253 254DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 255DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 256DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 257 258static int fxp_rnr; 259SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 260 261/* 262 * Wait for the previous command to be accepted (but not necessarily 263 * completed). 264 */ 265static __inline void 266fxp_scb_wait(struct fxp_softc *sc) 267{ 268 int i = 10000; 269 270 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 271 DELAY(2); 272 if (i == 0) 273 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 274 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 275 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 276 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 277 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 278} 279 280static __inline void 281fxp_scb_cmd(struct fxp_softc *sc, int cmd) 282{ 283 284 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 285 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 286 fxp_scb_wait(sc); 287 } 288 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 289} 290 291static __inline void 292fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 293 bus_dma_tag_t dmat, bus_dmamap_t map) 294{ 295 int i = 10000; 296 297 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 298 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 299 DELAY(2); 300 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 301 } 302 if (i == 0) 303 device_printf(sc->dev, "DMA timeout\n"); 304} 305 306/* 307 * Return identification string if this is device is ours. 308 */ 309static int 310fxp_probe(device_t dev) 311{ 312 u_int16_t devid; 313 struct fxp_ident *ident; 314 315 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 316 devid = pci_get_device(dev); 317 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 318 if (ident->devid == devid) { 319 device_set_desc(dev, ident->name); 320 return (0); 321 } 322 } 323 } 324 return (ENXIO); 325} 326 327static void 328fxp_powerstate_d0(device_t dev) 329{ 330#if __FreeBSD_version >= 430002 331 u_int32_t iobase, membase, irq; 332 333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 334 /* Save important PCI config data. */ 335 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 336 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 337 irq = pci_read_config(dev, PCIR_INTLINE, 4); 338 339 /* Reset the power state. */ 340 device_printf(dev, "chip is in D%d power mode " 341 "-- setting to D0\n", pci_get_powerstate(dev)); 342 343 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 344 345 /* Restore PCI config data. */ 346 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 347 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 348 pci_write_config(dev, PCIR_INTLINE, irq, 4); 349 } 350#endif 351} 352 353static void 354fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355{ 356 u_int32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 int error = 0; 370 struct fxp_softc *sc = device_get_softc(dev); 371 struct ifnet *ifp; 372 struct fxp_rx *rxp; 373 u_int32_t val; 374 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 375 int i, rid, m1, m2, prefer_iomap, maxtxseg; 376 int s; 377 378 bzero(sc, sizeof(*sc)); 379 sc->dev = dev; 380 callout_handle_init(&sc->stat_ch); 381 sysctl_ctx_init(&sc->sysctl_ctx); 382 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 383 MTX_DEF | MTX_RECURSE); 384 385 s = splimp(); 386 387 /* 388 * Enable bus mastering. Enable memory space too, in case 389 * BIOS/Prom forgot about it. 390 */ 391 val = pci_read_config(dev, PCIR_COMMAND, 2); 392 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 393 pci_write_config(dev, PCIR_COMMAND, val, 2); 394 val = pci_read_config(dev, PCIR_COMMAND, 2); 395 396 fxp_powerstate_d0(dev); 397 398 /* 399 * Figure out which we should try first - memory mapping or i/o mapping? 400 * We default to memory mapping. Then we accept an override from the 401 * command line. Then we check to see which one is enabled. 402 */ 403 m1 = PCIM_CMD_MEMEN; 404 m2 = PCIM_CMD_PORTEN; 405 prefer_iomap = 0; 406 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 407 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 408 m1 = PCIM_CMD_PORTEN; 409 m2 = PCIM_CMD_MEMEN; 410 } 411 412 if (val & m1) { 413 sc->rtp = 414 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 415 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 416 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 417 0, ~0, 1, RF_ACTIVE); 418 } 419 if (sc->mem == NULL && (val & m2)) { 420 sc->rtp = 421 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 422 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 423 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 424 0, ~0, 1, RF_ACTIVE); 425 } 426 427 if (!sc->mem) { 428 device_printf(dev, "could not map device registers\n"); 429 error = ENXIO; 430 goto fail; 431 } 432 if (bootverbose) { 433 device_printf(dev, "using %s space register mapping\n", 434 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 435 } 436 437 sc->sc_st = rman_get_bustag(sc->mem); 438 sc->sc_sh = rman_get_bushandle(sc->mem); 439 440 /* 441 * Allocate our interrupt. 442 */ 443 rid = 0; 444 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 445 RF_SHAREABLE | RF_ACTIVE); 446 if (sc->irq == NULL) { 447 device_printf(dev, "could not map interrupt\n"); 448 error = ENXIO; 449 goto fail; 450 } 451 452 /* 453 * Reset to a stable state. 454 */ 455 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 456 DELAY(10); 457 458 /* 459 * Find out how large of an SEEPROM we have. 460 */ 461 fxp_autosize_eeprom(sc); 462 463 /* 464 * Determine whether we must use the 503 serial interface. 465 */ 466 fxp_read_eeprom(sc, &data, 6, 1); 467 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 468 (data & FXP_PHY_SERIAL_ONLY)) 469 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 470 471 /* 472 * Create the sysctl tree 473 */ 474 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 475 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 476 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 477 if (sc->sysctl_tree == NULL) 478 goto fail; 479 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 480 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 481 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 482 "FXP driver receive interrupt microcode bundling delay"); 483 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 484 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 485 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 486 "FXP driver receive interrupt microcode bundle size limit"); 487 488 /* 489 * Pull in device tunables. 490 */ 491 sc->tunable_int_delay = TUNABLE_INT_DELAY; 492 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 494 "int_delay", &sc->tunable_int_delay); 495 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 496 "bundle_max", &sc->tunable_bundle_max); 497 498 /* 499 * Find out the chip revision; lump all 82557 revs together. 500 */ 501 fxp_read_eeprom(sc, &data, 5, 1); 502 if ((data >> 8) == 1) 503 sc->revision = FXP_REV_82557; 504 else 505 sc->revision = pci_get_revid(dev); 506 507 /* 508 * Enable workarounds for certain chip revision deficiencies. 509 * 510 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 511 * some systems based a normal 82559 design, have a defect where 512 * the chip can cause a PCI protocol violation if it receives 513 * a CU_RESUME command when it is entering the IDLE state. The 514 * workaround is to disable Dynamic Standby Mode, so the chip never 515 * deasserts CLKRUN#, and always remains in an active state. 516 * 517 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 518 */ 519 i = pci_get_device(dev); 520 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 521 sc->revision >= FXP_REV_82559_A0) { 522 fxp_read_eeprom(sc, &data, 10, 1); 523 if (data & 0x02) { /* STB enable */ 524 u_int16_t cksum; 525 int i; 526 527 device_printf(dev, 528 "Disabling dynamic standby mode in EEPROM\n"); 529 data &= ~0x02; 530 fxp_write_eeprom(sc, &data, 10, 1); 531 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 532 cksum = 0; 533 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 534 fxp_read_eeprom(sc, &data, i, 1); 535 cksum += data; 536 } 537 i = (1 << sc->eeprom_size) - 1; 538 cksum = 0xBABA - cksum; 539 fxp_read_eeprom(sc, &data, i, 1); 540 fxp_write_eeprom(sc, &cksum, i, 1); 541 device_printf(dev, 542 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 543 i, data, cksum); 544#if 1 545 /* 546 * If the user elects to continue, try the software 547 * workaround, as it is better than nothing. 548 */ 549 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 550#endif 551 } 552 } 553 554 /* 555 * If we are not a 82557 chip, we can enable extended features. 556 */ 557 if (sc->revision != FXP_REV_82557) { 558 /* 559 * If MWI is enabled in the PCI configuration, and there 560 * is a valid cacheline size (8 or 16 dwords), then tell 561 * the board to turn on MWI. 562 */ 563 if (val & PCIM_CMD_MWRICEN && 564 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 565 sc->flags |= FXP_FLAG_MWI_ENABLE; 566 567 /* turn on the extended TxCB feature */ 568 sc->flags |= FXP_FLAG_EXT_TXCB; 569 570 /* enable reception of long frames for VLAN */ 571 sc->flags |= FXP_FLAG_LONG_PKT_EN; 572 } 573 574 /* 575 * Enable use of extended RFDs and TCBs for 82550 576 * and later chips. Note: we need extended TXCB support 577 * too, but that's already enabled by the code above. 578 * Be careful to do this only on the right devices. 579 */ 580 581 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 582 sc->rfa_size = sizeof (struct fxp_rfa); 583 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 584 sc->flags |= FXP_FLAG_EXT_RFA; 585 } else { 586 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 587 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 588 } 589 590 /* 591 * Allocate DMA tags and DMA safe memory. 592 */ 593 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 594 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 595 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 596 maxtxseg, MCLBYTES, 0, &sc->fxp_mtag); 597 if (error) { 598 device_printf(dev, "could not allocate dma tag\n"); 599 goto fail; 600 } 601 602 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 603 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 604 sizeof(struct fxp_stats), 0, &sc->fxp_stag); 605 if (error) { 606 device_printf(dev, "could not allocate dma tag\n"); 607 goto fail; 608 } 609 610 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 611 BUS_DMA_NOWAIT, &sc->fxp_smap); 612 if (error) 613 goto failmem; 614 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 615 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 616 if (error) { 617 device_printf(dev, "could not map the stats buffer\n"); 618 goto fail; 619 } 620 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 621 622 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 623 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 624 FXP_TXCB_SZ, 0, &sc->cbl_tag); 625 if (error) { 626 device_printf(dev, "could not allocate dma tag\n"); 627 goto fail; 628 } 629 630 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 631 BUS_DMA_NOWAIT, &sc->cbl_map); 632 if (error) 633 goto failmem; 634 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ); 635 636 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 637 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 638 &sc->fxp_desc.cbl_addr, 0); 639 if (error) { 640 device_printf(dev, "could not map DMA memory\n"); 641 goto fail; 642 } 643 644 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 645 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 646 sizeof(struct fxp_cb_mcs), 0, &sc->mcs_tag); 647 if (error) { 648 device_printf(dev, "could not allocate dma tag\n"); 649 goto fail; 650 } 651 652 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 653 BUS_DMA_NOWAIT, &sc->mcs_map); 654 if (error) 655 goto failmem; 656 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 657 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 658 if (error) { 659 device_printf(dev, "can't map the multicast setup command\n"); 660 goto fail; 661 } 662 663 /* 664 * Pre-allocate the TX DMA maps. 665 */ 666 for (i = 0; i < FXP_NTXCB; i++) { 667 error = bus_dmamap_create(sc->fxp_mtag, 0, 668 &sc->fxp_desc.tx_list[i].tx_map); 669 if (error) { 670 device_printf(dev, "can't create DMA map for TX\n"); 671 goto fail; 672 } 673 } 674 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 675 if (error) { 676 device_printf(dev, "can't create spare DMA map\n"); 677 goto fail; 678 } 679 680 /* 681 * Pre-allocate our receive buffers. 682 */ 683 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 684 for (i = 0; i < FXP_NRFABUFS; i++) { 685 rxp = &sc->fxp_desc.rx_list[i]; 686 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 687 if (error) { 688 device_printf(dev, "can't create DMA map for RX\n"); 689 goto fail; 690 } 691 if (fxp_add_rfabuf(sc, rxp) != 0) 692 goto failmem; 693 } 694 695 /* 696 * Read MAC address. 697 */ 698 fxp_read_eeprom(sc, myea, 0, 3); 699 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 700 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 701 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 702 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 703 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 704 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 705 device_printf(dev, "Ethernet address %6D%s\n", 706 sc->arpcom.ac_enaddr, ":", 707 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 708 if (bootverbose) { 709 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 710 pci_get_vendor(dev), pci_get_device(dev), 711 pci_get_subvendor(dev), pci_get_subdevice(dev), 712 pci_get_revid(dev)); 713 fxp_read_eeprom(sc, &data, 10, 1); 714 device_printf(dev, "Dynamic Standby mode is %s\n", 715 data & 0x02 ? "enabled" : "disabled"); 716 } 717 718 /* 719 * If this is only a 10Mbps device, then there is no MII, and 720 * the PHY will use a serial interface instead. 721 * 722 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 723 * doesn't have a programming interface of any sort. The 724 * media is sensed automatically based on how the link partner 725 * is configured. This is, in essence, manual configuration. 726 */ 727 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 728 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 729 fxp_serial_ifmedia_sts); 730 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 731 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 732 } else { 733 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 734 fxp_ifmedia_sts)) { 735 device_printf(dev, "MII without any PHY!\n"); 736 error = ENXIO; 737 goto fail; 738 } 739 } 740 741 ifp = &sc->arpcom.ac_if; 742 ifp->if_unit = device_get_unit(dev); 743 ifp->if_name = "fxp"; 744 ifp->if_output = ether_output; 745 ifp->if_baudrate = 100000000; 746 ifp->if_init = fxp_init; 747 ifp->if_softc = sc; 748 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 749 ifp->if_ioctl = fxp_ioctl; 750 ifp->if_start = fxp_start; 751 ifp->if_watchdog = fxp_watchdog; 752 753 /* Enable checksum offload for 82550 or better chips */ 754 755 if (sc->flags & FXP_FLAG_EXT_RFA) { 756 ifp->if_hwassist = FXP_CSUM_FEATURES; 757 ifp->if_capabilities = IFCAP_HWCSUM; 758 ifp->if_capenable = ifp->if_capabilities; 759 } 760 761 /* 762 * Tell the upper layer(s) we support long frames. 763 */ 764 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 765 ifp->if_capabilities |= IFCAP_VLAN_MTU; 766 767 /* 768 * Let the system queue as many packets as we have available 769 * TX descriptors. 770 */ 771 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 772 773 /* 774 * Attach the interface. 775 */ 776 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 777 778 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 779 fxp_intr, sc, &sc->ih); 780 if (error) { 781 device_printf(dev, "could not setup irq\n"); 782 goto fail; 783 } 784 785 splx(s); 786 return (0); 787 788failmem: 789 device_printf(dev, "Failed to malloc memory\n"); 790 error = ENOMEM; 791fail: 792 splx(s); 793 fxp_release(sc); 794 return (error); 795} 796 797/* 798 * release all resources 799 */ 800static void 801fxp_release(struct fxp_softc *sc) 802{ 803 struct fxp_rx *rxp; 804 struct fxp_tx *txp; 805 int i; 806 807 if (sc->ih) 808 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 809 if (sc->fxp_desc.cbl_list) { 810 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 811 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 812 sc->cbl_map); 813 } 814 if (sc->fxp_stats) { 815 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 816 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 817 } 818 if (sc->mcsp) { 819 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 820 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 821 } 822 if (sc->irq) 823 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 824 if (sc->mem) 825 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 826 if (sc->fxp_mtag) { 827 for (i = 0; i < FXP_NRFABUFS; i++) { 828 rxp = &sc->fxp_desc.rx_list[i]; 829 if (rxp->rx_mbuf != NULL) { 830 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 831 BUS_DMASYNC_POSTREAD); 832 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 833 m_freem(rxp->rx_mbuf); 834 } 835 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 836 } 837 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 838 bus_dma_tag_destroy(sc->fxp_mtag); 839 } 840 if (sc->fxp_stag) { 841 for (i = 0; i < FXP_NTXCB; i++) { 842 txp = &sc->fxp_desc.tx_list[i]; 843 if (txp->tx_mbuf != NULL) { 844 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 845 BUS_DMASYNC_POSTWRITE); 846 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 847 m_freem(txp->tx_mbuf); 848 } 849 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 850 } 851 bus_dma_tag_destroy(sc->fxp_stag); 852 } 853 if (sc->cbl_tag) 854 bus_dma_tag_destroy(sc->cbl_tag); 855 if (sc->mcs_tag) 856 bus_dma_tag_destroy(sc->mcs_tag); 857 858 sysctl_ctx_free(&sc->sysctl_ctx); 859 860 mtx_destroy(&sc->sc_mtx); 861} 862 863/* 864 * Detach interface. 865 */ 866static int 867fxp_detach(device_t dev) 868{ 869 struct fxp_softc *sc = device_get_softc(dev); 870 int s; 871 872 s = splimp(); 873 /* 874 * Close down routes etc. 875 */ 876 ether_ifdetach(&sc->arpcom.ac_if); 877 878 /* 879 * Stop DMA and drop transmit queue. 880 */ 881 if (bus_child_present(dev)) { 882 /* disable interrupts */ 883 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 884 fxp_stop(sc); 885 } 886 887 device_delete_child(dev, sc->miibus); 888 bus_generic_detach(dev); 889 /* 890 * Free all media structures. 891 */ 892 ifmedia_removeall(&sc->sc_media); 893 894 splx(s); 895 896 /* Release our allocated resources. */ 897 fxp_release(sc); 898 return (0); 899} 900 901/* 902 * Device shutdown routine. Called at system shutdown after sync. The 903 * main purpose of this routine is to shut off receiver DMA so that 904 * kernel memory doesn't get clobbered during warmboot. 905 */ 906static int 907fxp_shutdown(device_t dev) 908{ 909 /* 910 * Make sure that DMA is disabled prior to reboot. Not doing 911 * do could allow DMA to corrupt kernel memory during the 912 * reboot before the driver initializes. 913 */ 914 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 915 return (0); 916} 917 918/* 919 * Device suspend routine. Stop the interface and save some PCI 920 * settings in case the BIOS doesn't restore them properly on 921 * resume. 922 */ 923static int 924fxp_suspend(device_t dev) 925{ 926 struct fxp_softc *sc = device_get_softc(dev); 927 int i, s; 928 929 s = splimp(); 930 931 fxp_stop(sc); 932 933 for (i = 0; i < 5; i++) 934 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 935 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 936 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 937 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 938 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 939 940 sc->suspended = 1; 941 942 splx(s); 943 return (0); 944} 945 946/* 947 * Device resume routine. Restore some PCI settings in case the BIOS 948 * doesn't, re-enable busmastering, and restart the interface if 949 * appropriate. 950 */ 951static int 952fxp_resume(device_t dev) 953{ 954 struct fxp_softc *sc = device_get_softc(dev); 955 struct ifnet *ifp = &sc->sc_if; 956 u_int16_t pci_command; 957 int i, s; 958 959 s = splimp(); 960 961 fxp_powerstate_d0(dev); 962 963 /* better way to do this? */ 964 for (i = 0; i < 5; i++) 965 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 966 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 967 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 968 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 969 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 970 971 /* reenable busmastering */ 972 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 973 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 974 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 975 976 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 977 DELAY(10); 978 979 /* reinitialize interface if necessary */ 980 if (ifp->if_flags & IFF_UP) 981 fxp_init(sc); 982 983 sc->suspended = 0; 984 985 splx(s); 986 return (0); 987} 988 989static void 990fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 991{ 992 u_int16_t reg; 993 int x; 994 995 /* 996 * Shift in data. 997 */ 998 for (x = 1 << (length - 1); x; x >>= 1) { 999 if (data & x) 1000 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1001 else 1002 reg = FXP_EEPROM_EECS; 1003 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1004 DELAY(1); 1005 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1006 DELAY(1); 1007 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1008 DELAY(1); 1009 } 1010} 1011 1012/* 1013 * Read from the serial EEPROM. Basically, you manually shift in 1014 * the read opcode (one bit at a time) and then shift in the address, 1015 * and then you shift out the data (all of this one bit at a time). 1016 * The word size is 16 bits, so you have to provide the address for 1017 * every 16 bits of data. 1018 */ 1019static u_int16_t 1020fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1021{ 1022 u_int16_t reg, data; 1023 int x; 1024 1025 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1026 /* 1027 * Shift in read opcode. 1028 */ 1029 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1030 /* 1031 * Shift in address. 1032 */ 1033 data = 0; 1034 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1035 if (offset & x) 1036 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1037 else 1038 reg = FXP_EEPROM_EECS; 1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1040 DELAY(1); 1041 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1042 DELAY(1); 1043 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1044 DELAY(1); 1045 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1046 data++; 1047 if (autosize && reg == 0) { 1048 sc->eeprom_size = data; 1049 break; 1050 } 1051 } 1052 /* 1053 * Shift out data. 1054 */ 1055 data = 0; 1056 reg = FXP_EEPROM_EECS; 1057 for (x = 1 << 15; x; x >>= 1) { 1058 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1059 DELAY(1); 1060 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1061 data |= x; 1062 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1063 DELAY(1); 1064 } 1065 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1066 DELAY(1); 1067 1068 return (data); 1069} 1070 1071static void 1072fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1073{ 1074 int i; 1075 1076 /* 1077 * Erase/write enable. 1078 */ 1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1080 fxp_eeprom_shiftin(sc, 0x4, 3); 1081 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1082 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1083 DELAY(1); 1084 /* 1085 * Shift in write opcode, address, data. 1086 */ 1087 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1088 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1089 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1090 fxp_eeprom_shiftin(sc, data, 16); 1091 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1092 DELAY(1); 1093 /* 1094 * Wait for EEPROM to finish up. 1095 */ 1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1097 DELAY(1); 1098 for (i = 0; i < 1000; i++) { 1099 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1100 break; 1101 DELAY(50); 1102 } 1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1104 DELAY(1); 1105 /* 1106 * Erase/write disable. 1107 */ 1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1109 fxp_eeprom_shiftin(sc, 0x4, 3); 1110 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1112 DELAY(1); 1113} 1114 1115/* 1116 * From NetBSD: 1117 * 1118 * Figure out EEPROM size. 1119 * 1120 * 559's can have either 64-word or 256-word EEPROMs, the 558 1121 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1122 * talks about the existance of 16 to 256 word EEPROMs. 1123 * 1124 * The only known sizes are 64 and 256, where the 256 version is used 1125 * by CardBus cards to store CIS information. 1126 * 1127 * The address is shifted in msb-to-lsb, and after the last 1128 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1129 * after which follows the actual data. We try to detect this zero, by 1130 * probing the data-out bit in the EEPROM control register just after 1131 * having shifted in a bit. If the bit is zero, we assume we've 1132 * shifted enough address bits. The data-out should be tri-state, 1133 * before this, which should translate to a logical one. 1134 */ 1135static void 1136fxp_autosize_eeprom(struct fxp_softc *sc) 1137{ 1138 1139 /* guess maximum size of 256 words */ 1140 sc->eeprom_size = 8; 1141 1142 /* autosize */ 1143 (void) fxp_eeprom_getword(sc, 0, 1); 1144} 1145 1146static void 1147fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1148{ 1149 int i; 1150 1151 for (i = 0; i < words; i++) 1152 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1153} 1154 1155static void 1156fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1157{ 1158 int i; 1159 1160 for (i = 0; i < words; i++) 1161 fxp_eeprom_putword(sc, offset + i, data[i]); 1162} 1163 1164static void 1165fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1166 bus_size_t mapsize, int error) 1167{ 1168 struct fxp_softc *sc; 1169 struct fxp_cb_tx *txp; 1170 int i; 1171 1172 if (error) 1173 return; 1174 1175 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1176 1177 sc = arg; 1178 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1179 for (i = 0; i < nseg; i++) { 1180 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1181 /* 1182 * If this is an 82550/82551, then we're using extended 1183 * TxCBs _and_ we're using checksum offload. This means 1184 * that the TxCB is really an IPCB. One major difference 1185 * between the two is that with plain extended TxCBs, 1186 * the bottom half of the TxCB contains two entries from 1187 * the TBD array, whereas IPCBs contain just one entry: 1188 * one entry (8 bytes) has been sacrificed for the TCP/IP 1189 * checksum offload control bits. So to make things work 1190 * right, we have to start filling in the TBD array 1191 * starting from a different place depending on whether 1192 * the chip is an 82550/82551 or not. 1193 */ 1194 if (sc->flags & FXP_FLAG_EXT_RFA) { 1195 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1196 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1197 } else { 1198 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1199 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1200 } 1201 } 1202 txp->tbd_number = nseg; 1203} 1204 1205/* 1206 * Start packet transmission on the interface. 1207 */ 1208static void 1209fxp_start(struct ifnet *ifp) 1210{ 1211 struct fxp_softc *sc = ifp->if_softc; 1212 struct fxp_tx *txp; 1213 struct mbuf *mb_head; 1214 int error; 1215 1216 /* 1217 * See if we need to suspend xmit until the multicast filter 1218 * has been reprogrammed (which can only be done at the head 1219 * of the command chain). 1220 */ 1221 if (sc->need_mcsetup) { 1222 return; 1223 } 1224 1225 txp = NULL; 1226 1227 /* 1228 * We're finished if there is nothing more to add to the list or if 1229 * we're all filled up with buffers to transmit. 1230 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1231 * a NOP command when needed. 1232 */ 1233 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1234 1235 /* 1236 * Grab a packet to transmit. 1237 */ 1238 IF_DEQUEUE(&ifp->if_snd, mb_head); 1239 1240 /* 1241 * Get pointer to next available tx desc. 1242 */ 1243 txp = sc->fxp_desc.tx_last->tx_next; 1244 1245 /* 1246 * Deal with TCP/IP checksum offload. Note that 1247 * in order for TCP checksum offload to work, 1248 * the pseudo header checksum must have already 1249 * been computed and stored in the checksum field 1250 * in the TCP header. The stack should have 1251 * already done this for us. 1252 */ 1253 1254 if (mb_head->m_pkthdr.csum_flags) { 1255 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1256 txp->tx_cb->ipcb_ip_activation_high = 1257 FXP_IPCB_HARDWAREPARSING_ENABLE; 1258 txp->tx_cb->ipcb_ip_schedule = 1259 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1260 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1261 txp->tx_cb->ipcb_ip_schedule |= 1262 FXP_IPCB_TCP_PACKET; 1263 } 1264#ifdef FXP_IP_CSUM_WAR 1265 /* 1266 * XXX The 82550 chip appears to have trouble 1267 * dealing with IP header checksums in very small 1268 * datagrams, namely fragments from 1 to 3 bytes 1269 * in size. For example, say you want to transmit 1270 * a UDP packet of 1473 bytes. The packet will be 1271 * fragmented over two IP datagrams, the latter 1272 * containing only one byte of data. The 82550 will 1273 * botch the header checksum on the 1-byte fragment. 1274 * As long as the datagram contains 4 or more bytes 1275 * of data, you're ok. 1276 * 1277 * The following code attempts to work around this 1278 * problem: if the datagram is less than 38 bytes 1279 * in size (14 bytes ether header, 20 bytes IP header, 1280 * plus 4 bytes of data), we punt and compute the IP 1281 * header checksum by hand. This workaround doesn't 1282 * work very well, however, since it can be fooled 1283 * by things like VLAN tags and IP options that make 1284 * the header sizes/offsets vary. 1285 */ 1286 1287 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1288 if (mb_head->m_pkthdr.len < 38) { 1289 struct ip *ip; 1290 mb_head->m_data += ETHER_HDR_LEN; 1291 ip = mtod(mb_head, struct ip *); 1292 ip->ip_sum = in_cksum(mb_head, 1293 ip->ip_hl << 2); 1294 mb_head->m_data -= ETHER_HDR_LEN; 1295 } else { 1296 txp->tx_cb->ipcb_ip_activation_high = 1297 FXP_IPCB_HARDWAREPARSING_ENABLE; 1298 txp->tx_cb->ipcb_ip_schedule |= 1299 FXP_IPCB_IP_CHECKSUM_ENABLE; 1300 } 1301 } 1302#endif 1303 } 1304 1305 /* 1306 * Go through each of the mbufs in the chain and initialize 1307 * the transmit buffer descriptors with the physical address 1308 * and size of the mbuf. 1309 */ 1310 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1311 mb_head, fxp_dma_map_txbuf, sc, 0); 1312 1313 if (error && error != EFBIG) { 1314 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1315 error); 1316 m_freem(mb_head); 1317 break; 1318 } 1319 1320 if (error) { 1321 struct mbuf *mn; 1322 1323 /* 1324 * We ran out of segments. We have to recopy this 1325 * mbuf chain first. Bail out if we can't get the 1326 * new buffers. 1327 */ 1328 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1329 if (mn == NULL) { 1330 m_freem(mb_head); 1331 break; 1332 } 1333 if (mb_head->m_pkthdr.len > MHLEN) { 1334 MCLGET(mn, M_DONTWAIT); 1335 if ((mn->m_flags & M_EXT) == 0) { 1336 m_freem(mn); 1337 m_freem(mb_head); 1338 break; 1339 } 1340 } 1341 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1342 mtod(mn, caddr_t)); 1343 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1344 m_freem(mb_head); 1345 mb_head = mn; 1346 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1347 mb_head, fxp_dma_map_txbuf, sc, 0); 1348 if (error) { 1349 device_printf(sc->dev, 1350 "can't map mbuf (error %d)\n", error); 1351 m_freem(mb_head); 1352 break; 1353 } 1354 } 1355 1356 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1357 BUS_DMASYNC_PREWRITE); 1358 1359 txp->tx_mbuf = mb_head; 1360 txp->tx_cb->cb_status = 0; 1361 txp->tx_cb->byte_count = 0; 1362 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1363 txp->tx_cb->cb_command = 1364 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1365 FXP_CB_COMMAND_S); 1366 } else { 1367 txp->tx_cb->cb_command = 1368 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1369 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1370 /* 1371 * Set a 5 second timer just in case we don't hear 1372 * from the card again. 1373 */ 1374 ifp->if_timer = 5; 1375 } 1376 txp->tx_cb->tx_threshold = tx_threshold; 1377 1378 /* 1379 * Advance the end of list forward. 1380 */ 1381 1382#ifdef __alpha__ 1383 /* 1384 * On platforms which can't access memory in 16-bit 1385 * granularities, we must prevent the card from DMA'ing 1386 * up the status while we update the command field. 1387 * This could cause us to overwrite the completion status. 1388 * XXX This is probably bogus and we're _not_ looking 1389 * for atomicity here. 1390 */ 1391 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1392 htole16(FXP_CB_COMMAND_S)); 1393#else 1394 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1395 htole16(~FXP_CB_COMMAND_S); 1396#endif /*__alpha__*/ 1397 sc->fxp_desc.tx_last = txp; 1398 1399 /* 1400 * Advance the beginning of the list forward if there are 1401 * no other packets queued (when nothing is queued, tx_first 1402 * sits on the last TxCB that was sent out). 1403 */ 1404 if (sc->tx_queued == 0) 1405 sc->fxp_desc.tx_first = txp; 1406 1407 sc->tx_queued++; 1408 1409 /* 1410 * Pass packet to bpf if there is a listener. 1411 */ 1412 BPF_MTAP(ifp, mb_head); 1413 } 1414 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1415 1416 /* 1417 * We're finished. If we added to the list, issue a RESUME to get DMA 1418 * going again if suspended. 1419 */ 1420 if (txp != NULL) { 1421 fxp_scb_wait(sc); 1422 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1423 } 1424} 1425 1426static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1427 1428#ifdef DEVICE_POLLING 1429static poll_handler_t fxp_poll; 1430 1431static void 1432fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1433{ 1434 struct fxp_softc *sc = ifp->if_softc; 1435 u_int8_t statack; 1436 1437 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1438 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1439 return; 1440 } 1441 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1442 FXP_SCB_STATACK_FR; 1443 if (cmd == POLL_AND_CHECK_STATUS) { 1444 u_int8_t tmp; 1445 1446 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1447 if (tmp == 0xff || tmp == 0) 1448 return; /* nothing to do */ 1449 tmp &= ~statack; 1450 /* ack what we can */ 1451 if (tmp != 0) 1452 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1453 statack |= tmp; 1454 } 1455 fxp_intr_body(sc, statack, count); 1456} 1457#endif /* DEVICE_POLLING */ 1458 1459/* 1460 * Process interface interrupts. 1461 */ 1462static void 1463fxp_intr(void *xsc) 1464{ 1465 struct fxp_softc *sc = xsc; 1466 u_int8_t statack; 1467 1468#ifdef DEVICE_POLLING 1469 struct ifnet *ifp = &sc->sc_if; 1470 1471 if (ifp->if_flags & IFF_POLLING) 1472 return; 1473 if (ether_poll_register(fxp_poll, ifp)) { 1474 /* disable interrupts */ 1475 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1476 fxp_poll(ifp, 0, 1); 1477 return; 1478 } 1479#endif 1480 1481 if (sc->suspended) { 1482 return; 1483 } 1484 1485 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1486 /* 1487 * It should not be possible to have all bits set; the 1488 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1489 * all bits are set, this may indicate that the card has 1490 * been physically ejected, so ignore it. 1491 */ 1492 if (statack == 0xff) 1493 return; 1494 1495 /* 1496 * First ACK all the interrupts in this pass. 1497 */ 1498 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1499 fxp_intr_body(sc, statack, -1); 1500 } 1501} 1502 1503static void 1504fxp_txeof(struct fxp_softc *sc) 1505{ 1506 struct fxp_tx *txp; 1507 1508 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1509 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1510 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1511 txp = txp->tx_next) { 1512 if (txp->tx_mbuf != NULL) { 1513 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1514 BUS_DMASYNC_POSTWRITE); 1515 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1516 m_freem(txp->tx_mbuf); 1517 txp->tx_mbuf = NULL; 1518 /* clear this to reset csum offload bits */ 1519 txp->tx_cb->tbd[0].tb_addr = 0; 1520 } 1521 sc->tx_queued--; 1522 } 1523 sc->fxp_desc.tx_first = txp; 1524 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1525} 1526 1527static void 1528fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1529{ 1530 struct ifnet *ifp = &sc->sc_if; 1531 struct mbuf *m; 1532 struct fxp_rx *rxp; 1533 struct fxp_rfa *rfa; 1534 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1535 1536 if (rnr) 1537 fxp_rnr++; 1538#ifdef DEVICE_POLLING 1539 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1540 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1541 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1542 rnr = 1; 1543 } 1544#endif 1545 1546 /* 1547 * Free any finished transmit mbuf chains. 1548 * 1549 * Handle the CNA event likt a CXTNO event. It used to 1550 * be that this event (control unit not ready) was not 1551 * encountered, but it is now with the SMPng modifications. 1552 * The exact sequence of events that occur when the interface 1553 * is brought up are different now, and if this event 1554 * goes unhandled, the configuration/rxfilter setup sequence 1555 * can stall for several seconds. The result is that no 1556 * packets go out onto the wire for about 5 to 10 seconds 1557 * after the interface is ifconfig'ed for the first time. 1558 */ 1559 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1560 fxp_txeof(sc); 1561 1562 ifp->if_timer = 0; 1563 if (sc->tx_queued == 0) { 1564 if (sc->need_mcsetup) 1565 fxp_mc_setup(sc); 1566 } 1567 /* 1568 * Try to start more packets transmitting. 1569 */ 1570 if (ifp->if_snd.ifq_head != NULL) 1571 fxp_start(ifp); 1572 } 1573 1574 /* 1575 * Just return if nothing happened on the receive side. 1576 */ 1577 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1578 return; 1579 1580 /* 1581 * Process receiver interrupts. If a no-resource (RNR) 1582 * condition exists, get whatever packets we can and 1583 * re-start the receiver. 1584 * 1585 * When using polling, we do not process the list to completion, 1586 * so when we get an RNR interrupt we must defer the restart 1587 * until we hit the last buffer with the C bit set. 1588 * If we run out of cycles and rfa_headm has the C bit set, 1589 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1590 * that the info will be used in the subsequent polling cycle. 1591 */ 1592 for (;;) { 1593 rxp = sc->fxp_desc.rx_head; 1594 m = rxp->rx_mbuf; 1595 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1596 RFA_ALIGNMENT_FUDGE); 1597 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1598 BUS_DMASYNC_POSTREAD); 1599 1600#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1601 if (count >= 0 && count-- == 0) { 1602 if (rnr) { 1603 /* Defer RNR processing until the next time. */ 1604 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1605 rnr = 0; 1606 } 1607 break; 1608 } 1609#endif /* DEVICE_POLLING */ 1610 1611 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1612 break; 1613 1614 /* 1615 * Advance head forward. 1616 */ 1617 sc->fxp_desc.rx_head = rxp->rx_next; 1618 1619 /* 1620 * Add a new buffer to the receive chain. 1621 * If this fails, the old buffer is recycled 1622 * instead. 1623 */ 1624 if (fxp_add_rfabuf(sc, rxp) == 0) { 1625 int total_len; 1626 1627 /* 1628 * Fetch packet length (the top 2 bits of 1629 * actual_size are flags set by the controller 1630 * upon completion), and drop the packet in case 1631 * of bogus length or CRC errors. 1632 */ 1633 total_len = le16toh(rfa->actual_size) & 0x3fff; 1634 if (total_len < sizeof(struct ether_header) || 1635 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1636 sc->rfa_size || 1637 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1638 m_freem(m); 1639 continue; 1640 } 1641 1642 /* Do IP checksum checking. */ 1643 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1644 if (rfa->rfax_csum_sts & 1645 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1646 m->m_pkthdr.csum_flags |= 1647 CSUM_IP_CHECKED; 1648 if (rfa->rfax_csum_sts & 1649 FXP_RFDX_CS_IP_CSUM_VALID) 1650 m->m_pkthdr.csum_flags |= 1651 CSUM_IP_VALID; 1652 if ((rfa->rfax_csum_sts & 1653 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1654 (rfa->rfax_csum_sts & 1655 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1656 m->m_pkthdr.csum_flags |= 1657 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1658 m->m_pkthdr.csum_data = 0xffff; 1659 } 1660 } 1661 1662 m->m_pkthdr.len = m->m_len = total_len; 1663 m->m_pkthdr.rcvif = ifp; 1664 1665 (*ifp->if_input)(ifp, m); 1666 } 1667 } 1668 if (rnr) { 1669 fxp_scb_wait(sc); 1670 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1671 sc->fxp_desc.rx_head->rx_addr); 1672 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1673 } 1674} 1675 1676/* 1677 * Update packet in/out/collision statistics. The i82557 doesn't 1678 * allow you to access these counters without doing a fairly 1679 * expensive DMA to get _all_ of the statistics it maintains, so 1680 * we do this operation here only once per second. The statistics 1681 * counters in the kernel are updated from the previous dump-stats 1682 * DMA and then a new dump-stats DMA is started. The on-chip 1683 * counters are zeroed when the DMA completes. If we can't start 1684 * the DMA immediately, we don't wait - we just prepare to read 1685 * them again next time. 1686 */ 1687static void 1688fxp_tick(void *xsc) 1689{ 1690 struct fxp_softc *sc = xsc; 1691 struct ifnet *ifp = &sc->sc_if; 1692 struct fxp_stats *sp = sc->fxp_stats; 1693 int s; 1694 1695 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1696 ifp->if_opackets += le32toh(sp->tx_good); 1697 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1698 if (sp->rx_good) { 1699 ifp->if_ipackets += le32toh(sp->rx_good); 1700 sc->rx_idle_secs = 0; 1701 } else { 1702 /* 1703 * Receiver's been idle for another second. 1704 */ 1705 sc->rx_idle_secs++; 1706 } 1707 ifp->if_ierrors += 1708 le32toh(sp->rx_crc_errors) + 1709 le32toh(sp->rx_alignment_errors) + 1710 le32toh(sp->rx_rnr_errors) + 1711 le32toh(sp->rx_overrun_errors); 1712 /* 1713 * If any transmit underruns occured, bump up the transmit 1714 * threshold by another 512 bytes (64 * 8). 1715 */ 1716 if (sp->tx_underruns) { 1717 ifp->if_oerrors += le32toh(sp->tx_underruns); 1718 if (tx_threshold < 192) 1719 tx_threshold += 64; 1720 } 1721 s = splimp(); 1722 /* 1723 * Release any xmit buffers that have completed DMA. This isn't 1724 * strictly necessary to do here, but it's advantagous for mbufs 1725 * with external storage to be released in a timely manner rather 1726 * than being defered for a potentially long time. This limits 1727 * the delay to a maximum of one second. 1728 */ 1729 fxp_txeof(sc); 1730 1731 /* 1732 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1733 * then assume the receiver has locked up and attempt to clear 1734 * the condition by reprogramming the multicast filter. This is 1735 * a work-around for a bug in the 82557 where the receiver locks 1736 * up if it gets certain types of garbage in the syncronization 1737 * bits prior to the packet header. This bug is supposed to only 1738 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1739 * mode as well (perhaps due to a 10/100 speed transition). 1740 */ 1741 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1742 sc->rx_idle_secs = 0; 1743 fxp_mc_setup(sc); 1744 } 1745 /* 1746 * If there is no pending command, start another stats 1747 * dump. Otherwise punt for now. 1748 */ 1749 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1750 /* 1751 * Start another stats dump. 1752 */ 1753 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1754 BUS_DMASYNC_PREREAD); 1755 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1756 } else { 1757 /* 1758 * A previous command is still waiting to be accepted. 1759 * Just zero our copy of the stats and wait for the 1760 * next timer event to update them. 1761 */ 1762 sp->tx_good = 0; 1763 sp->tx_underruns = 0; 1764 sp->tx_total_collisions = 0; 1765 1766 sp->rx_good = 0; 1767 sp->rx_crc_errors = 0; 1768 sp->rx_alignment_errors = 0; 1769 sp->rx_rnr_errors = 0; 1770 sp->rx_overrun_errors = 0; 1771 } 1772 if (sc->miibus != NULL) 1773 mii_tick(device_get_softc(sc->miibus)); 1774 splx(s); 1775 /* 1776 * Schedule another timeout one second from now. 1777 */ 1778 sc->stat_ch = timeout(fxp_tick, sc, hz); 1779} 1780 1781/* 1782 * Stop the interface. Cancels the statistics updater and resets 1783 * the interface. 1784 */ 1785static void 1786fxp_stop(struct fxp_softc *sc) 1787{ 1788 struct ifnet *ifp = &sc->sc_if; 1789 struct fxp_tx *txp; 1790 int i; 1791 1792 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1793 ifp->if_timer = 0; 1794 1795#ifdef DEVICE_POLLING 1796 ether_poll_deregister(ifp); 1797#endif 1798 /* 1799 * Cancel stats updater. 1800 */ 1801 untimeout(fxp_tick, sc, sc->stat_ch); 1802 1803 /* 1804 * Issue software reset, which also unloads the microcode. 1805 */ 1806 sc->flags &= ~FXP_FLAG_UCODE; 1807 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1808 DELAY(50); 1809 1810 /* 1811 * Release any xmit buffers. 1812 */ 1813 txp = sc->fxp_desc.tx_list; 1814 if (txp != NULL) { 1815 for (i = 0; i < FXP_NTXCB; i++) { 1816 if (txp[i].tx_mbuf != NULL) { 1817 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1818 BUS_DMASYNC_POSTWRITE); 1819 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1820 m_freem(txp[i].tx_mbuf); 1821 txp[i].tx_mbuf = NULL; 1822 /* clear this to reset csum offload bits */ 1823 txp[i].tx_cb->tbd[0].tb_addr = 0; 1824 } 1825 } 1826 } 1827 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1828 sc->tx_queued = 0; 1829} 1830 1831/* 1832 * Watchdog/transmission transmit timeout handler. Called when a 1833 * transmission is started on the interface, but no interrupt is 1834 * received before the timeout. This usually indicates that the 1835 * card has wedged for some reason. 1836 */ 1837static void 1838fxp_watchdog(struct ifnet *ifp) 1839{ 1840 struct fxp_softc *sc = ifp->if_softc; 1841 1842 device_printf(sc->dev, "device timeout\n"); 1843 ifp->if_oerrors++; 1844 1845 fxp_init(sc); 1846} 1847 1848static void 1849fxp_init(void *xsc) 1850{ 1851 struct fxp_softc *sc = xsc; 1852 struct ifnet *ifp = &sc->sc_if; 1853 struct fxp_cb_config *cbp; 1854 struct fxp_cb_ias *cb_ias; 1855 struct fxp_cb_tx *tcbp; 1856 struct fxp_tx *txp; 1857 struct fxp_cb_mcs *mcsp; 1858 int i, prm, s; 1859 1860 s = splimp(); 1861 /* 1862 * Cancel any pending I/O 1863 */ 1864 fxp_stop(sc); 1865 1866 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1867 1868 /* 1869 * Initialize base of CBL and RFA memory. Loading with zero 1870 * sets it up for regular linear addressing. 1871 */ 1872 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1873 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1874 1875 fxp_scb_wait(sc); 1876 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1877 1878 /* 1879 * Initialize base of dump-stats buffer. 1880 */ 1881 fxp_scb_wait(sc); 1882 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1883 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1884 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1885 1886 /* 1887 * Attempt to load microcode if requested. 1888 */ 1889 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1890 fxp_load_ucode(sc); 1891 1892 /* 1893 * Initialize the multicast address list. 1894 */ 1895 if (fxp_mc_addrs(sc)) { 1896 mcsp = sc->mcsp; 1897 mcsp->cb_status = 0; 1898 mcsp->cb_command = 1899 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1900 mcsp->link_addr = 0xffffffff; 1901 /* 1902 * Start the multicast setup command. 1903 */ 1904 fxp_scb_wait(sc); 1905 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1906 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1907 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1908 /* ...and wait for it to complete. */ 1909 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1910 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1911 BUS_DMASYNC_POSTWRITE); 1912 } 1913 1914 /* 1915 * We temporarily use memory that contains the TxCB list to 1916 * construct the config CB. The TxCB list memory is rebuilt 1917 * later. 1918 */ 1919 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1920 1921 /* 1922 * This bcopy is kind of disgusting, but there are a bunch of must be 1923 * zero and must be one bits in this structure and this is the easiest 1924 * way to initialize them all to proper values. 1925 */ 1926 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1927 1928 cbp->cb_status = 0; 1929 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1930 FXP_CB_COMMAND_EL); 1931 cbp->link_addr = 0xffffffff; /* (no) next command */ 1932 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1933 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1934 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1935 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1936 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1937 cbp->type_enable = 0; /* actually reserved */ 1938 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1939 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1940 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1941 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1942 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1943 cbp->late_scb = 0; /* (don't) defer SCB update */ 1944 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1945 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1946 cbp->ci_int = 1; /* interrupt on CU idle */ 1947 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1948 cbp->ext_stats_dis = 1; /* disable extended counters */ 1949 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1950 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1951 cbp->disc_short_rx = !prm; /* discard short packets */ 1952 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1953 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1954 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1955 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1956 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1957 cbp->csma_dis = 0; /* (don't) disable link */ 1958 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1959 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1960 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1961 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1962 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1963 cbp->nsai = 1; /* (don't) disable source addr insert */ 1964 cbp->preamble_length = 2; /* (7 byte) preamble */ 1965 cbp->loopback = 0; /* (don't) loopback */ 1966 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1967 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1968 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1969 cbp->promiscuous = prm; /* promiscuous mode */ 1970 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1971 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1972 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1973 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1974 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1975 1976 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1977 cbp->padding = 1; /* (do) pad short tx packets */ 1978 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1979 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1980 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1981 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1982 /* must set wake_en in PMCSR also */ 1983 cbp->force_fdx = 0; /* (don't) force full duplex */ 1984 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1985 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1986 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1987 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1988 1989 if (sc->revision == FXP_REV_82557) { 1990 /* 1991 * The 82557 has no hardware flow control, the values 1992 * below are the defaults for the chip. 1993 */ 1994 cbp->fc_delay_lsb = 0; 1995 cbp->fc_delay_msb = 0x40; 1996 cbp->pri_fc_thresh = 3; 1997 cbp->tx_fc_dis = 0; 1998 cbp->rx_fc_restop = 0; 1999 cbp->rx_fc_restart = 0; 2000 cbp->fc_filter = 0; 2001 cbp->pri_fc_loc = 1; 2002 } else { 2003 cbp->fc_delay_lsb = 0x1f; 2004 cbp->fc_delay_msb = 0x01; 2005 cbp->pri_fc_thresh = 3; 2006 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2007 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2008 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2009 cbp->fc_filter = !prm; /* drop FC frames to host */ 2010 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2011 } 2012 2013 /* 2014 * Start the config command/DMA. 2015 */ 2016 fxp_scb_wait(sc); 2017 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2018 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2019 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2020 /* ...and wait for it to complete. */ 2021 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2022 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2023 2024 /* 2025 * Now initialize the station address. Temporarily use the TxCB 2026 * memory area like we did above for the config CB. 2027 */ 2028 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2029 cb_ias->cb_status = 0; 2030 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2031 cb_ias->link_addr = 0xffffffff; 2032 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2033 sizeof(sc->arpcom.ac_enaddr)); 2034 2035 /* 2036 * Start the IAS (Individual Address Setup) command/DMA. 2037 */ 2038 fxp_scb_wait(sc); 2039 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2040 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2041 /* ...and wait for it to complete. */ 2042 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2043 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2044 2045 /* 2046 * Initialize transmit control block (TxCB) list. 2047 */ 2048 txp = sc->fxp_desc.tx_list; 2049 tcbp = sc->fxp_desc.cbl_list; 2050 bzero(tcbp, FXP_TXCB_SZ); 2051 for (i = 0; i < FXP_NTXCB; i++) { 2052 txp[i].tx_cb = tcbp + i; 2053 txp[i].tx_mbuf = NULL; 2054 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2055 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2056 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2057 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2058 if (sc->flags & FXP_FLAG_EXT_TXCB) 2059 tcbp[i].tbd_array_addr = 2060 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2061 else 2062 tcbp[i].tbd_array_addr = 2063 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2064 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2065 } 2066 /* 2067 * Set the suspend flag on the first TxCB and start the control 2068 * unit. It will execute the NOP and then suspend. 2069 */ 2070 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2071 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2072 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2073 sc->tx_queued = 1; 2074 2075 fxp_scb_wait(sc); 2076 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2077 2078 /* 2079 * Initialize receiver buffer area - RFA. 2080 */ 2081 fxp_scb_wait(sc); 2082 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2083 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2084 2085 /* 2086 * Set current media. 2087 */ 2088 if (sc->miibus != NULL) 2089 mii_mediachg(device_get_softc(sc->miibus)); 2090 2091 ifp->if_flags |= IFF_RUNNING; 2092 ifp->if_flags &= ~IFF_OACTIVE; 2093 2094 /* 2095 * Enable interrupts. 2096 */ 2097#ifdef DEVICE_POLLING 2098 /* 2099 * ... but only do that if we are not polling. And because (presumably) 2100 * the default is interrupts on, we need to disable them explicitly! 2101 */ 2102 if ( ifp->if_flags & IFF_POLLING ) 2103 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2104 else 2105#endif /* DEVICE_POLLING */ 2106 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2107 splx(s); 2108 2109 /* 2110 * Start stats updater. 2111 */ 2112 sc->stat_ch = timeout(fxp_tick, sc, hz); 2113} 2114 2115static int 2116fxp_serial_ifmedia_upd(struct ifnet *ifp) 2117{ 2118 2119 return (0); 2120} 2121 2122static void 2123fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2124{ 2125 2126 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2127} 2128 2129/* 2130 * Change media according to request. 2131 */ 2132static int 2133fxp_ifmedia_upd(struct ifnet *ifp) 2134{ 2135 struct fxp_softc *sc = ifp->if_softc; 2136 struct mii_data *mii; 2137 2138 mii = device_get_softc(sc->miibus); 2139 mii_mediachg(mii); 2140 return (0); 2141} 2142 2143/* 2144 * Notify the world which media we're using. 2145 */ 2146static void 2147fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2148{ 2149 struct fxp_softc *sc = ifp->if_softc; 2150 struct mii_data *mii; 2151 2152 mii = device_get_softc(sc->miibus); 2153 mii_pollstat(mii); 2154 ifmr->ifm_active = mii->mii_media_active; 2155 ifmr->ifm_status = mii->mii_media_status; 2156 2157 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2158 sc->cu_resume_bug = 1; 2159 else 2160 sc->cu_resume_bug = 0; 2161} 2162 2163/* 2164 * Add a buffer to the end of the RFA buffer list. 2165 * Return 0 if successful, 1 for failure. A failure results in 2166 * adding the 'oldm' (if non-NULL) on to the end of the list - 2167 * tossing out its old contents and recycling it. 2168 * The RFA struct is stuck at the beginning of mbuf cluster and the 2169 * data pointer is fixed up to point just past it. 2170 */ 2171static int 2172fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2173{ 2174 struct mbuf *m; 2175 struct fxp_rfa *rfa, *p_rfa; 2176 struct fxp_rx *p_rx; 2177 bus_dmamap_t tmp_map; 2178 int error; 2179 2180 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2181 if (m == NULL) 2182 return (ENOBUFS); 2183 2184 /* 2185 * Move the data pointer up so that the incoming data packet 2186 * will be 32-bit aligned. 2187 */ 2188 m->m_data += RFA_ALIGNMENT_FUDGE; 2189 2190 /* 2191 * Get a pointer to the base of the mbuf cluster and move 2192 * data start past it. 2193 */ 2194 rfa = mtod(m, struct fxp_rfa *); 2195 m->m_data += sc->rfa_size; 2196 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2197 2198 /* 2199 * Initialize the rest of the RFA. Note that since the RFA 2200 * is misaligned, we cannot store values directly. Instead, 2201 * we use an optimized, inline copy. 2202 */ 2203 2204 rfa->rfa_status = 0; 2205 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2206 rfa->actual_size = 0; 2207 2208 le32enc(&rfa->link_addr, 0xffffffff); 2209 le32enc(&rfa->rbd_addr, 0xffffffff); 2210 2211 /* Map the RFA into DMA memory. */ 2212 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2213 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2214 &rxp->rx_addr, 0); 2215 if (error) { 2216 m_freem(m); 2217 return (error); 2218 } 2219 2220 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2221 tmp_map = sc->spare_map; 2222 sc->spare_map = rxp->rx_map; 2223 rxp->rx_map = tmp_map; 2224 rxp->rx_mbuf = m; 2225 2226 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2227 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2228 2229 /* 2230 * If there are other buffers already on the list, attach this 2231 * one to the end by fixing up the tail to point to this one. 2232 */ 2233 if (sc->fxp_desc.rx_head != NULL) { 2234 p_rx = sc->fxp_desc.rx_tail; 2235 p_rfa = (struct fxp_rfa *) 2236 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2237 p_rx->rx_next = rxp; 2238 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2239 p_rfa->rfa_control = 0; 2240 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2241 BUS_DMASYNC_PREWRITE); 2242 } else { 2243 rxp->rx_next = NULL; 2244 sc->fxp_desc.rx_head = rxp; 2245 } 2246 sc->fxp_desc.rx_tail = rxp; 2247 return (0); 2248} 2249 2250static volatile int 2251fxp_miibus_readreg(device_t dev, int phy, int reg) 2252{ 2253 struct fxp_softc *sc = device_get_softc(dev); 2254 int count = 10000; 2255 int value; 2256 2257 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2258 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2259 2260 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2261 && count--) 2262 DELAY(10); 2263 2264 if (count <= 0) 2265 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2266 2267 return (value & 0xffff); 2268} 2269 2270static void 2271fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2272{ 2273 struct fxp_softc *sc = device_get_softc(dev); 2274 int count = 10000; 2275 2276 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2277 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2278 (value & 0xffff)); 2279 2280 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2281 count--) 2282 DELAY(10); 2283 2284 if (count <= 0) 2285 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2286} 2287 2288static int 2289fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2290{ 2291 struct fxp_softc *sc = ifp->if_softc; 2292 struct ifreq *ifr = (struct ifreq *)data; 2293 struct mii_data *mii; 2294 int s, error = 0; 2295 2296 s = splimp(); 2297 2298 switch (command) { 2299 case SIOCSIFFLAGS: 2300 if (ifp->if_flags & IFF_ALLMULTI) 2301 sc->flags |= FXP_FLAG_ALL_MCAST; 2302 else 2303 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2304 2305 /* 2306 * If interface is marked up and not running, then start it. 2307 * If it is marked down and running, stop it. 2308 * XXX If it's up then re-initialize it. This is so flags 2309 * such as IFF_PROMISC are handled. 2310 */ 2311 if (ifp->if_flags & IFF_UP) { 2312 fxp_init(sc); 2313 } else { 2314 if (ifp->if_flags & IFF_RUNNING) 2315 fxp_stop(sc); 2316 } 2317 break; 2318 2319 case SIOCADDMULTI: 2320 case SIOCDELMULTI: 2321 if (ifp->if_flags & IFF_ALLMULTI) 2322 sc->flags |= FXP_FLAG_ALL_MCAST; 2323 else 2324 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2325 /* 2326 * Multicast list has changed; set the hardware filter 2327 * accordingly. 2328 */ 2329 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2330 fxp_mc_setup(sc); 2331 /* 2332 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2333 * again rather than else {}. 2334 */ 2335 if (sc->flags & FXP_FLAG_ALL_MCAST) 2336 fxp_init(sc); 2337 error = 0; 2338 break; 2339 2340 case SIOCSIFMEDIA: 2341 case SIOCGIFMEDIA: 2342 if (sc->miibus != NULL) { 2343 mii = device_get_softc(sc->miibus); 2344 error = ifmedia_ioctl(ifp, ifr, 2345 &mii->mii_media, command); 2346 } else { 2347 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2348 } 2349 break; 2350 2351 default: 2352 error = ether_ioctl(ifp, command, data); 2353 } 2354 splx(s); 2355 return (error); 2356} 2357 2358/* 2359 * Fill in the multicast address list and return number of entries. 2360 */ 2361static int 2362fxp_mc_addrs(struct fxp_softc *sc) 2363{ 2364 struct fxp_cb_mcs *mcsp = sc->mcsp; 2365 struct ifnet *ifp = &sc->sc_if; 2366 struct ifmultiaddr *ifma; 2367 int nmcasts; 2368 2369 nmcasts = 0; 2370 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2371#if __FreeBSD_version < 500000 2372 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2373#else 2374 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2375#endif 2376 if (ifma->ifma_addr->sa_family != AF_LINK) 2377 continue; 2378 if (nmcasts >= MAXMCADDR) { 2379 sc->flags |= FXP_FLAG_ALL_MCAST; 2380 nmcasts = 0; 2381 break; 2382 } 2383 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2384 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2385 nmcasts++; 2386 } 2387 } 2388 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2389 return (nmcasts); 2390} 2391 2392/* 2393 * Program the multicast filter. 2394 * 2395 * We have an artificial restriction that the multicast setup command 2396 * must be the first command in the chain, so we take steps to ensure 2397 * this. By requiring this, it allows us to keep up the performance of 2398 * the pre-initialized command ring (esp. link pointers) by not actually 2399 * inserting the mcsetup command in the ring - i.e. its link pointer 2400 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2401 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2402 * lead into the regular TxCB ring when it completes. 2403 * 2404 * This function must be called at splimp. 2405 */ 2406static void 2407fxp_mc_setup(struct fxp_softc *sc) 2408{ 2409 struct fxp_cb_mcs *mcsp = sc->mcsp; 2410 struct ifnet *ifp = &sc->sc_if; 2411 struct fxp_tx *txp; 2412 int count; 2413 2414 /* 2415 * If there are queued commands, we must wait until they are all 2416 * completed. If we are already waiting, then add a NOP command 2417 * with interrupt option so that we're notified when all commands 2418 * have been completed - fxp_start() ensures that no additional 2419 * TX commands will be added when need_mcsetup is true. 2420 */ 2421 if (sc->tx_queued) { 2422 /* 2423 * need_mcsetup will be true if we are already waiting for the 2424 * NOP command to be completed (see below). In this case, bail. 2425 */ 2426 if (sc->need_mcsetup) 2427 return; 2428 sc->need_mcsetup = 1; 2429 2430 /* 2431 * Add a NOP command with interrupt so that we are notified 2432 * when all TX commands have been processed. 2433 */ 2434 txp = sc->fxp_desc.tx_last->tx_next; 2435 txp->tx_mbuf = NULL; 2436 txp->tx_cb->cb_status = 0; 2437 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2438 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2439 /* 2440 * Advance the end of list forward. 2441 */ 2442 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2443 htole16(~FXP_CB_COMMAND_S); 2444 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2445 sc->fxp_desc.tx_last = txp; 2446 sc->tx_queued++; 2447 /* 2448 * Issue a resume in case the CU has just suspended. 2449 */ 2450 fxp_scb_wait(sc); 2451 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2452 /* 2453 * Set a 5 second timer just in case we don't hear from the 2454 * card again. 2455 */ 2456 ifp->if_timer = 5; 2457 2458 return; 2459 } 2460 sc->need_mcsetup = 0; 2461 2462 /* 2463 * Initialize multicast setup descriptor. 2464 */ 2465 mcsp->cb_status = 0; 2466 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2467 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2468 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2469 txp = &sc->fxp_desc.mcs_tx; 2470 txp->tx_mbuf = NULL; 2471 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2472 txp->tx_next = sc->fxp_desc.tx_list; 2473 (void) fxp_mc_addrs(sc); 2474 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2475 sc->tx_queued = 1; 2476 2477 /* 2478 * Wait until command unit is not active. This should never 2479 * be the case when nothing is queued, but make sure anyway. 2480 */ 2481 count = 100; 2482 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2483 FXP_SCB_CUS_ACTIVE && --count) 2484 DELAY(10); 2485 if (count == 0) { 2486 device_printf(sc->dev, "command queue timeout\n"); 2487 return; 2488 } 2489 2490 /* 2491 * Start the multicast setup command. 2492 */ 2493 fxp_scb_wait(sc); 2494 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2495 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2496 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2497 2498 ifp->if_timer = 2; 2499 return; 2500} 2501 2502static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2503static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2504static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2505static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2506static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2507static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2508 2509#define UCODE(x) x, sizeof(x) 2510 2511struct ucode { 2512 u_int32_t revision; 2513 u_int32_t *ucode; 2514 int length; 2515 u_short int_delay_offset; 2516 u_short bundle_max_offset; 2517} ucode_table[] = { 2518 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2519 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2520 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2521 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2522 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2523 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2524 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2525 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2526 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2527 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2528 { 0, NULL, 0, 0, 0 } 2529}; 2530 2531static void 2532fxp_load_ucode(struct fxp_softc *sc) 2533{ 2534 struct ucode *uc; 2535 struct fxp_cb_ucode *cbp; 2536 2537 for (uc = ucode_table; uc->ucode != NULL; uc++) 2538 if (sc->revision == uc->revision) 2539 break; 2540 if (uc->ucode == NULL) 2541 return; 2542 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2543 cbp->cb_status = 0; 2544 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2545 cbp->link_addr = 0xffffffff; /* (no) next command */ 2546 memcpy(cbp->ucode, uc->ucode, uc->length); 2547 if (uc->int_delay_offset) 2548 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2549 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2550 if (uc->bundle_max_offset) 2551 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2552 htole16(sc->tunable_bundle_max); 2553 /* 2554 * Download the ucode to the chip. 2555 */ 2556 fxp_scb_wait(sc); 2557 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2558 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2559 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2560 /* ...and wait for it to complete. */ 2561 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2562 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2563 device_printf(sc->dev, 2564 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2565 sc->tunable_int_delay, 2566 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2567 sc->flags |= FXP_FLAG_UCODE; 2568} 2569 2570static int 2571sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2572{ 2573 int error, value; 2574 2575 value = *(int *)arg1; 2576 error = sysctl_handle_int(oidp, &value, 0, req); 2577 if (error || !req->newptr) 2578 return (error); 2579 if (value < low || value > high) 2580 return (EINVAL); 2581 *(int *)arg1 = value; 2582 return (0); 2583} 2584 2585/* 2586 * Interrupt delay is expressed in microseconds, a multiplier is used 2587 * to convert this to the appropriate clock ticks before using. 2588 */ 2589static int 2590sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2591{ 2592 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2593} 2594 2595static int 2596sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2597{ 2598 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2599} 2600