if_fxp.c revision 113231
1/*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice unmodified, this list of conditions, and the following
11 *    disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30/*
31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 113231 2003-04-07 17:02:44Z mux $");
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/endian.h>
40#include <sys/mbuf.h>
41		/* #include <sys/mutex.h> */
42#include <sys/kernel.h>
43#include <sys/socket.h>
44#include <sys/sysctl.h>
45
46#include <net/if.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
49
50#include <net/bpf.h>
51#include <sys/sockio.h>
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56
57#include <net/ethernet.h>
58#include <net/if_arp.h>
59
60#include <machine/atomic.h>
61#include <machine/clock.h>	/* for DELAY */
62
63#include <net/if_types.h>
64#include <net/if_vlan_var.h>
65
66#ifdef FXP_IP_CSUM_WAR
67#include <netinet/in.h>
68#include <netinet/in_systm.h>
69#include <netinet/ip.h>
70#include <machine/in_cksum.h>
71#endif
72
73#include <pci/pcivar.h>
74#include <pci/pcireg.h>		/* for PCIM_CMD_xxx */
75
76#include <dev/mii/mii.h>
77#include <dev/mii/miivar.h>
78
79#include <dev/fxp/if_fxpreg.h>
80#include <dev/fxp/if_fxpvar.h>
81#include <dev/fxp/rcvbundl.h>
82
83MODULE_DEPEND(fxp, miibus, 1, 1, 1);
84#include "miibus_if.h"
85
86/*
87 * NOTE!  On the Alpha, we have an alignment constraint.  The
88 * card DMAs the packet immediately following the RFA.  However,
89 * the first thing in the packet is a 14-byte Ethernet header.
90 * This means that the packet is misaligned.  To compensate,
91 * we actually offset the RFA 2 bytes into the cluster.  This
92 * alignes the packet after the Ethernet header at a 32-bit
93 * boundary.  HOWEVER!  This means that the RFA is misaligned!
94 */
95#define	RFA_ALIGNMENT_FUDGE	2
96
97/*
98 * Set initial transmit threshold at 64 (512 bytes). This is
99 * increased by 64 (512 bytes) at a time, to maximum of 192
100 * (1536 bytes), if an underrun occurs.
101 */
102static int tx_threshold = 64;
103
104/*
105 * The configuration byte map has several undefined fields which
106 * must be one or must be zero.  Set up a template for these bits
107 * only, (assuming a 82557 chip) leaving the actual configuration
108 * to fxp_init.
109 *
110 * See struct fxp_cb_config for the bit definitions.
111 */
112static u_char fxp_cb_config_template[] = {
113	0x0, 0x0,		/* cb_status */
114	0x0, 0x0,		/* cb_command */
115	0x0, 0x0, 0x0, 0x0,	/* link_addr */
116	0x0,	/*  0 */
117	0x0,	/*  1 */
118	0x0,	/*  2 */
119	0x0,	/*  3 */
120	0x0,	/*  4 */
121	0x0,	/*  5 */
122	0x32,	/*  6 */
123	0x0,	/*  7 */
124	0x0,	/*  8 */
125	0x0,	/*  9 */
126	0x6,	/* 10 */
127	0x0,	/* 11 */
128	0x0,	/* 12 */
129	0x0,	/* 13 */
130	0xf2,	/* 14 */
131	0x48,	/* 15 */
132	0x0,	/* 16 */
133	0x40,	/* 17 */
134	0xf0,	/* 18 */
135	0x0,	/* 19 */
136	0x3f,	/* 20 */
137	0x5	/* 21 */
138};
139
140struct fxp_ident {
141	u_int16_t	devid;
142	char 		*name;
143};
144
145/*
146 * Claim various Intel PCI device identifiers for this driver.  The
147 * sub-vendor and sub-device field are extensively used to identify
148 * particular variants, but we don't currently differentiate between
149 * them.
150 */
151static struct fxp_ident fxp_ident_table[] = {
152    { 0x1029,		"Intel 82559 PCI/CardBus Pro/100" },
153    { 0x1030,		"Intel 82559 Pro/100 Ethernet" },
154    { 0x1031,		"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
155    { 0x1032,		"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
156    { 0x1033,		"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
157    { 0x1034,		"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
158    { 0x1035,		"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159    { 0x1036,		"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
160    { 0x1037,		"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
161    { 0x1038,		"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
162    { 0x1039,		"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
163    { 0x103A,		"Intel 82801DB (ICH4) Pro/100 Ethernet" },
164    { 0x103B,		"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
165    { 0x103C,		"Intel 82801DB (ICH4) Pro/100 Ethernet" },
166    { 0x103D,		"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
167    { 0x103E,		"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
168    { 0x1059,		"Intel 82551QM Pro/100 M Mobile Connection" },
169    { 0x1209,		"Intel 82559ER Embedded 10/100 Ethernet" },
170    { 0x1229,		"Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" },
171    { 0x2449,		"Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
172    { 0,		NULL },
173};
174
175#ifdef FXP_IP_CSUM_WAR
176#define FXP_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
177#else
178#define FXP_CSUM_FEATURES    (CSUM_TCP | CSUM_UDP)
179#endif
180
181static int		fxp_probe(device_t dev);
182static int		fxp_attach(device_t dev);
183static int		fxp_detach(device_t dev);
184static int		fxp_shutdown(device_t dev);
185static int		fxp_suspend(device_t dev);
186static int		fxp_resume(device_t dev);
187
188static void		fxp_intr(void *xsc);
189static void 		fxp_init(void *xsc);
190static void 		fxp_tick(void *xsc);
191static void		fxp_powerstate_d0(device_t dev);
192static void 		fxp_start(struct ifnet *ifp);
193static void		fxp_stop(struct fxp_softc *sc);
194static void 		fxp_release(struct fxp_softc *sc);
195static int		fxp_ioctl(struct ifnet *ifp, u_long command,
196			    caddr_t data);
197static void 		fxp_watchdog(struct ifnet *ifp);
198static int		fxp_add_rfabuf(struct fxp_softc *sc,
199    			    struct fxp_rx *rxp);
200static int		fxp_mc_addrs(struct fxp_softc *sc);
201static void		fxp_mc_setup(struct fxp_softc *sc);
202static u_int16_t	fxp_eeprom_getword(struct fxp_softc *sc, int offset,
203			    int autosize);
204static void 		fxp_eeprom_putword(struct fxp_softc *sc, int offset,
205			    u_int16_t data);
206static void		fxp_autosize_eeprom(struct fxp_softc *sc);
207static void		fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
208			    int offset, int words);
209static void		fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
210			    int offset, int words);
211static int		fxp_ifmedia_upd(struct ifnet *ifp);
212static void		fxp_ifmedia_sts(struct ifnet *ifp,
213			    struct ifmediareq *ifmr);
214static int		fxp_serial_ifmedia_upd(struct ifnet *ifp);
215static void		fxp_serial_ifmedia_sts(struct ifnet *ifp,
216			    struct ifmediareq *ifmr);
217static volatile int	fxp_miibus_readreg(device_t dev, int phy, int reg);
218static void		fxp_miibus_writereg(device_t dev, int phy, int reg,
219			    int value);
220static void		fxp_load_ucode(struct fxp_softc *sc);
221static int		sysctl_int_range(SYSCTL_HANDLER_ARGS,
222			    int low, int high);
223static int		sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
224static int		sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
225static __inline void 	fxp_scb_wait(struct fxp_softc *sc);
226static __inline void	fxp_scb_cmd(struct fxp_softc *sc, int cmd);
227static __inline void	fxp_dma_wait(volatile u_int16_t *status,
228			    struct fxp_softc *sc);
229
230static device_method_t fxp_methods[] = {
231	/* Device interface */
232	DEVMETHOD(device_probe,		fxp_probe),
233	DEVMETHOD(device_attach,	fxp_attach),
234	DEVMETHOD(device_detach,	fxp_detach),
235	DEVMETHOD(device_shutdown,	fxp_shutdown),
236	DEVMETHOD(device_suspend,	fxp_suspend),
237	DEVMETHOD(device_resume,	fxp_resume),
238
239	/* MII interface */
240	DEVMETHOD(miibus_readreg,	fxp_miibus_readreg),
241	DEVMETHOD(miibus_writereg,	fxp_miibus_writereg),
242
243	{ 0, 0 }
244};
245
246static driver_t fxp_driver = {
247	"fxp",
248	fxp_methods,
249	sizeof(struct fxp_softc),
250};
251
252static devclass_t fxp_devclass;
253
254DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
255DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
256DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
257
258static int fxp_rnr;
259SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
260
261/*
262 * Wait for the previous command to be accepted (but not necessarily
263 * completed).
264 */
265static __inline void
266fxp_scb_wait(struct fxp_softc *sc)
267{
268	int i = 10000;
269
270	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
271		DELAY(2);
272	if (i == 0)
273		device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
274		    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
275		    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
276		    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
277		    CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
278}
279
280static __inline void
281fxp_scb_cmd(struct fxp_softc *sc, int cmd)
282{
283
284	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
285		CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
286		fxp_scb_wait(sc);
287	}
288	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
289}
290
291static __inline void
292fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
293{
294	int i = 10000;
295
296	while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i)
297		DELAY(2);
298	if (i == 0)
299		device_printf(sc->dev, "DMA timeout\n");
300}
301
302/*
303 * Return identification string if this is device is ours.
304 */
305static int
306fxp_probe(device_t dev)
307{
308	u_int16_t devid;
309	struct fxp_ident *ident;
310
311	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
312		devid = pci_get_device(dev);
313		for (ident = fxp_ident_table; ident->name != NULL; ident++) {
314			if (ident->devid == devid) {
315				device_set_desc(dev, ident->name);
316				return (0);
317			}
318		}
319	}
320	return (ENXIO);
321}
322
323static void
324fxp_powerstate_d0(device_t dev)
325{
326#if __FreeBSD_version >= 430002
327	u_int32_t iobase, membase, irq;
328
329	if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
330		/* Save important PCI config data. */
331		iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
332		membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
333		irq = pci_read_config(dev, PCIR_INTLINE, 4);
334
335		/* Reset the power state. */
336		device_printf(dev, "chip is in D%d power mode "
337		    "-- setting to D0\n", pci_get_powerstate(dev));
338
339		pci_set_powerstate(dev, PCI_POWERSTATE_D0);
340
341		/* Restore PCI config data. */
342		pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
343		pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
344		pci_write_config(dev, PCIR_INTLINE, irq, 4);
345	}
346#endif
347}
348
349static void
350fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
351{
352	u_int32_t *addr;
353
354	if (error)
355		return;
356
357	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
358	addr = arg;
359	*addr = segs->ds_addr;
360}
361
362static int
363fxp_attach(device_t dev)
364{
365	int error = 0;
366	struct fxp_softc *sc = device_get_softc(dev);
367	struct ifnet *ifp;
368	struct fxp_rx *rxp;
369	u_int32_t val;
370	u_int16_t data, myea[ETHER_ADDR_LEN / 2];
371	int i, rid, m1, m2, prefer_iomap, maxtxseg;
372	int s;
373
374	bzero(sc, sizeof(*sc));
375	sc->dev = dev;
376	callout_handle_init(&sc->stat_ch);
377	sysctl_ctx_init(&sc->sysctl_ctx);
378	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
379	    MTX_DEF | MTX_RECURSE);
380
381	s = splimp();
382
383	/*
384	 * Enable bus mastering. Enable memory space too, in case
385	 * BIOS/Prom forgot about it.
386	 */
387	val = pci_read_config(dev, PCIR_COMMAND, 2);
388	val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
389	pci_write_config(dev, PCIR_COMMAND, val, 2);
390	val = pci_read_config(dev, PCIR_COMMAND, 2);
391
392	fxp_powerstate_d0(dev);
393
394	/*
395	 * Figure out which we should try first - memory mapping or i/o mapping?
396	 * We default to memory mapping. Then we accept an override from the
397	 * command line. Then we check to see which one is enabled.
398	 */
399	m1 = PCIM_CMD_MEMEN;
400	m2 = PCIM_CMD_PORTEN;
401	prefer_iomap = 0;
402	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
403	    "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
404		m1 = PCIM_CMD_PORTEN;
405		m2 = PCIM_CMD_MEMEN;
406	}
407
408	if (val & m1) {
409		sc->rtp =
410		    (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
411		sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
412		sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
413	                                     0, ~0, 1, RF_ACTIVE);
414	}
415	if (sc->mem == NULL && (val & m2)) {
416		sc->rtp =
417		    (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
418		sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
419		sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
420                                            0, ~0, 1, RF_ACTIVE);
421	}
422
423	if (!sc->mem) {
424		device_printf(dev, "could not map device registers\n");
425		error = ENXIO;
426		goto fail;
427        }
428	if (bootverbose) {
429		device_printf(dev, "using %s space register mapping\n",
430		   sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
431	}
432
433	sc->sc_st = rman_get_bustag(sc->mem);
434	sc->sc_sh = rman_get_bushandle(sc->mem);
435
436	/*
437	 * Allocate our interrupt.
438	 */
439	rid = 0;
440	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
441				 RF_SHAREABLE | RF_ACTIVE);
442	if (sc->irq == NULL) {
443		device_printf(dev, "could not map interrupt\n");
444		error = ENXIO;
445		goto fail;
446	}
447
448	/*
449	 * Reset to a stable state.
450	 */
451	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
452	DELAY(10);
453
454	/*
455	 * Find out how large of an SEEPROM we have.
456	 */
457	fxp_autosize_eeprom(sc);
458
459	/*
460	 * Determine whether we must use the 503 serial interface.
461	 */
462	fxp_read_eeprom(sc, &data, 6, 1);
463	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
464	    (data & FXP_PHY_SERIAL_ONLY))
465		sc->flags |= FXP_FLAG_SERIAL_MEDIA;
466
467	/*
468	 * Create the sysctl tree
469	 */
470	sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
471	    SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
472	    device_get_nameunit(dev), CTLFLAG_RD, 0, "");
473	if (sc->sysctl_tree == NULL)
474		goto fail;
475	SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
476	    OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
477	    &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
478	    "FXP driver receive interrupt microcode bundling delay");
479	SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
480	    OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
481	    &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
482	    "FXP driver receive interrupt microcode bundle size limit");
483
484	/*
485	 * Pull in device tunables.
486	 */
487	sc->tunable_int_delay = TUNABLE_INT_DELAY;
488	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
489	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
490	    "int_delay", &sc->tunable_int_delay);
491	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
492	    "bundle_max", &sc->tunable_bundle_max);
493
494	/*
495	 * Find out the chip revision; lump all 82557 revs together.
496	 */
497	fxp_read_eeprom(sc, &data, 5, 1);
498	if ((data >> 8) == 1)
499		sc->revision = FXP_REV_82557;
500	else
501		sc->revision = pci_get_revid(dev);
502
503	/*
504	 * Enable workarounds for certain chip revision deficiencies.
505	 *
506	 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
507	 * some systems based a normal 82559 design, have a defect where
508	 * the chip can cause a PCI protocol violation if it receives
509	 * a CU_RESUME command when it is entering the IDLE state.  The
510	 * workaround is to disable Dynamic Standby Mode, so the chip never
511	 * deasserts CLKRUN#, and always remains in an active state.
512	 *
513	 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
514	 */
515	i = pci_get_device(dev);
516	if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
517	    sc->revision >= FXP_REV_82559_A0) {
518		fxp_read_eeprom(sc, &data, 10, 1);
519		if (data & 0x02) {			/* STB enable */
520			u_int16_t cksum;
521			int i;
522
523			device_printf(dev,
524			    "Disabling dynamic standby mode in EEPROM\n");
525			data &= ~0x02;
526			fxp_write_eeprom(sc, &data, 10, 1);
527			device_printf(dev, "New EEPROM ID: 0x%x\n", data);
528			cksum = 0;
529			for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
530				fxp_read_eeprom(sc, &data, i, 1);
531				cksum += data;
532			}
533			i = (1 << sc->eeprom_size) - 1;
534			cksum = 0xBABA - cksum;
535			fxp_read_eeprom(sc, &data, i, 1);
536			fxp_write_eeprom(sc, &cksum, i, 1);
537			device_printf(dev,
538			    "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
539			    i, data, cksum);
540#if 1
541			/*
542			 * If the user elects to continue, try the software
543			 * workaround, as it is better than nothing.
544			 */
545			sc->flags |= FXP_FLAG_CU_RESUME_BUG;
546#endif
547		}
548	}
549
550	/*
551	 * If we are not a 82557 chip, we can enable extended features.
552	 */
553	if (sc->revision != FXP_REV_82557) {
554		/*
555		 * If MWI is enabled in the PCI configuration, and there
556		 * is a valid cacheline size (8 or 16 dwords), then tell
557		 * the board to turn on MWI.
558		 */
559		if (val & PCIM_CMD_MWRICEN &&
560		    pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
561			sc->flags |= FXP_FLAG_MWI_ENABLE;
562
563		/* turn on the extended TxCB feature */
564		sc->flags |= FXP_FLAG_EXT_TXCB;
565
566		/* enable reception of long frames for VLAN */
567		sc->flags |= FXP_FLAG_LONG_PKT_EN;
568	}
569
570	/*
571	 * Enable use of extended RFDs and TCBs for 82550
572	 * and later chips. Note: we need extended TXCB support
573	 * too, but that's already enabled by the code above.
574	 * Be careful to do this only on the right devices.
575	 */
576
577	if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) {
578		sc->rfa_size = sizeof (struct fxp_rfa);
579		sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
580		sc->flags |= FXP_FLAG_EXT_RFA;
581	} else {
582		sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
583		sc->tx_cmd = FXP_CB_COMMAND_XMIT;
584	}
585
586	/*
587	 * Allocate DMA tags and DMA safe memory.
588	 */
589	maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG;
590	error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT,
591	    BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg,
592	    maxtxseg, MCLBYTES, 0, &sc->fxp_mtag);
593	if (error) {
594		device_printf(dev, "could not allocate dma tag\n");
595		goto fail;
596	}
597
598	error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
599	    BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1,
600	    sizeof(struct fxp_stats), 0, &sc->fxp_stag);
601	if (error) {
602		device_printf(dev, "could not allocate dma tag\n");
603		goto fail;
604	}
605
606	error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
607	    BUS_DMA_NOWAIT, &sc->fxp_smap);
608	if (error)
609		goto failmem;
610	error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
611	    sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
612	if (error) {
613		device_printf(dev, "could not map the stats buffer\n");
614		goto fail;
615	}
616	bzero(sc->fxp_stats, sizeof(struct fxp_stats));
617
618	error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
619	    BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1,
620	    FXP_TXCB_SZ, 0, &sc->cbl_tag);
621	if (error) {
622		device_printf(dev, "could not allocate dma tag\n");
623		goto fail;
624	}
625
626	error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
627	    BUS_DMA_NOWAIT, &sc->cbl_map);
628	if (error)
629		goto failmem;
630	bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ);
631
632	error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
633	    sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
634	    &sc->fxp_desc.cbl_addr, 0);
635	if (error) {
636		device_printf(dev, "could not map DMA memory\n");
637		goto fail;
638	}
639
640	error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
641	    BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1,
642	    sizeof(struct fxp_cb_mcs), 0, &sc->mcs_tag);
643	if (error) {
644		device_printf(dev, "could not allocate dma tag\n");
645		goto fail;
646	}
647
648	error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
649	    BUS_DMA_NOWAIT, &sc->mcs_map);
650	if (error)
651		goto failmem;
652	error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
653	    sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
654	if (error) {
655		device_printf(dev, "can't map the multicast setup command\n");
656		goto fail;
657	}
658
659	/*
660	 * Pre-allocate the TX DMA maps.
661	 */
662	for (i = 0; i < FXP_NTXCB; i++) {
663		error = bus_dmamap_create(sc->fxp_mtag, 0,
664		    &sc->fxp_desc.tx_list[i].tx_map);
665		if (error) {
666			device_printf(dev, "can't create DMA map for TX\n");
667			goto fail;
668		}
669	}
670	error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
671	if (error) {
672		device_printf(dev, "can't create spare DMA map\n");
673		goto fail;
674	}
675
676	/*
677	 * Pre-allocate our receive buffers.
678	 */
679	sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
680	for (i = 0; i < FXP_NRFABUFS; i++) {
681		rxp = &sc->fxp_desc.rx_list[i];
682		error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
683		if (error) {
684			device_printf(dev, "can't create DMA map for RX\n");
685			goto fail;
686		}
687		if (fxp_add_rfabuf(sc, rxp) != 0)
688			goto failmem;
689	}
690
691	/*
692	 * Read MAC address.
693	 */
694	fxp_read_eeprom(sc, myea, 0, 3);
695	sc->arpcom.ac_enaddr[0] = myea[0] & 0xff;
696	sc->arpcom.ac_enaddr[1] = myea[0] >> 8;
697	sc->arpcom.ac_enaddr[2] = myea[1] & 0xff;
698	sc->arpcom.ac_enaddr[3] = myea[1] >> 8;
699	sc->arpcom.ac_enaddr[4] = myea[2] & 0xff;
700	sc->arpcom.ac_enaddr[5] = myea[2] >> 8;
701	device_printf(dev, "Ethernet address %6D%s\n",
702	    sc->arpcom.ac_enaddr, ":",
703	    sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
704	if (bootverbose) {
705		device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
706		    pci_get_vendor(dev), pci_get_device(dev),
707		    pci_get_subvendor(dev), pci_get_subdevice(dev),
708		    pci_get_revid(dev));
709		fxp_read_eeprom(sc, &data, 10, 1);
710		device_printf(dev, "Dynamic Standby mode is %s\n",
711		    data & 0x02 ? "enabled" : "disabled");
712	}
713
714	/*
715	 * If this is only a 10Mbps device, then there is no MII, and
716	 * the PHY will use a serial interface instead.
717	 *
718	 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
719	 * doesn't have a programming interface of any sort.  The
720	 * media is sensed automatically based on how the link partner
721	 * is configured.  This is, in essence, manual configuration.
722	 */
723	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
724		ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
725		    fxp_serial_ifmedia_sts);
726		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
727		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
728	} else {
729		if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
730		    fxp_ifmedia_sts)) {
731	                device_printf(dev, "MII without any PHY!\n");
732			error = ENXIO;
733			goto fail;
734		}
735	}
736
737	ifp = &sc->arpcom.ac_if;
738	ifp->if_unit = device_get_unit(dev);
739	ifp->if_name = "fxp";
740	ifp->if_output = ether_output;
741	ifp->if_baudrate = 100000000;
742	ifp->if_init = fxp_init;
743	ifp->if_softc = sc;
744	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
745	ifp->if_ioctl = fxp_ioctl;
746	ifp->if_start = fxp_start;
747	ifp->if_watchdog = fxp_watchdog;
748
749	/* Enable checksum offload for 82550 or better chips */
750
751	if (sc->flags & FXP_FLAG_EXT_RFA) {
752		ifp->if_hwassist = FXP_CSUM_FEATURES;
753		ifp->if_capabilities = IFCAP_HWCSUM;
754		ifp->if_capenable = ifp->if_capabilities;
755	}
756
757	/*
758	 * Tell the upper layer(s) we support long frames.
759	 */
760	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
761	ifp->if_capabilities |= IFCAP_VLAN_MTU;
762
763	/*
764	 * Let the system queue as many packets as we have available
765	 * TX descriptors.
766	 */
767	ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
768
769	/*
770	 * Attach the interface.
771	 */
772	ether_ifattach(ifp, sc->arpcom.ac_enaddr);
773
774	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
775	    fxp_intr, sc, &sc->ih);
776	if (error) {
777		device_printf(dev, "could not setup irq\n");
778		goto fail;
779	}
780
781	splx(s);
782	return (0);
783
784failmem:
785	device_printf(dev, "Failed to malloc memory\n");
786	error = ENOMEM;
787fail:
788	splx(s);
789	fxp_release(sc);
790	return (error);
791}
792
793/*
794 * release all resources
795 */
796static void
797fxp_release(struct fxp_softc *sc)
798{
799	struct fxp_rx *rxp;
800	struct fxp_tx *txp;
801	int i;
802
803	for (i = 0; i < FXP_NRFABUFS; i++) {
804		rxp = &sc->fxp_desc.rx_list[i];
805		if (rxp->rx_mbuf != NULL) {
806			bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
807			    BUS_DMASYNC_POSTREAD);
808			bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
809			m_freem(rxp->rx_mbuf);
810		}
811		bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
812	}
813	bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
814
815	for (i = 0; i < FXP_NTXCB; i++) {
816		txp = &sc->fxp_desc.tx_list[i];
817		if (txp->tx_mbuf != NULL) {
818			bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
819			    BUS_DMASYNC_POSTWRITE);
820			bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
821			m_freem(txp->tx_mbuf);
822		}
823		bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
824	}
825
826	bus_generic_detach(sc->dev);
827	if (sc->miibus)
828		device_delete_child(sc->dev, sc->miibus);
829
830	if (sc->fxp_desc.cbl_list) {
831		bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
832		bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
833		    sc->cbl_map);
834	}
835	if (sc->fxp_stats) {
836		bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
837		bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
838	}
839	if (sc->mcsp) {
840		bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
841		bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
842	}
843	if (sc->ih)
844		bus_teardown_intr(sc->dev, sc->irq, sc->ih);
845	if (sc->irq)
846		bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
847	if (sc->mem)
848		bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
849	if (sc->fxp_mtag)
850		bus_dma_tag_destroy(sc->fxp_mtag);
851	if (sc->fxp_stag)
852		bus_dma_tag_destroy(sc->fxp_stag);
853	if (sc->cbl_tag)
854		bus_dma_tag_destroy(sc->cbl_tag);
855	if (sc->mcs_tag)
856		bus_dma_tag_destroy(sc->mcs_tag);
857
858        sysctl_ctx_free(&sc->sysctl_ctx);
859
860	mtx_destroy(&sc->sc_mtx);
861}
862
863/*
864 * Detach interface.
865 */
866static int
867fxp_detach(device_t dev)
868{
869	struct fxp_softc *sc = device_get_softc(dev);
870	int s;
871
872	/* disable interrupts */
873	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
874
875	s = splimp();
876
877	/*
878	 * Stop DMA and drop transmit queue.
879	 */
880	fxp_stop(sc);
881
882	/*
883	 * Close down routes etc.
884	 */
885	ether_ifdetach(&sc->arpcom.ac_if);
886
887	/*
888	 * Free all media structures.
889	 */
890	ifmedia_removeall(&sc->sc_media);
891
892	splx(s);
893
894	/* Release our allocated resources. */
895	fxp_release(sc);
896
897	return (0);
898}
899
900/*
901 * Device shutdown routine. Called at system shutdown after sync. The
902 * main purpose of this routine is to shut off receiver DMA so that
903 * kernel memory doesn't get clobbered during warmboot.
904 */
905static int
906fxp_shutdown(device_t dev)
907{
908	/*
909	 * Make sure that DMA is disabled prior to reboot. Not doing
910	 * do could allow DMA to corrupt kernel memory during the
911	 * reboot before the driver initializes.
912	 */
913	fxp_stop((struct fxp_softc *) device_get_softc(dev));
914	return (0);
915}
916
917/*
918 * Device suspend routine.  Stop the interface and save some PCI
919 * settings in case the BIOS doesn't restore them properly on
920 * resume.
921 */
922static int
923fxp_suspend(device_t dev)
924{
925	struct fxp_softc *sc = device_get_softc(dev);
926	int i, s;
927
928	s = splimp();
929
930	fxp_stop(sc);
931
932	for (i = 0; i < 5; i++)
933		sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
934	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
935	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
936	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
937	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
938
939	sc->suspended = 1;
940
941	splx(s);
942	return (0);
943}
944
945/*
946 * Device resume routine.  Restore some PCI settings in case the BIOS
947 * doesn't, re-enable busmastering, and restart the interface if
948 * appropriate.
949 */
950static int
951fxp_resume(device_t dev)
952{
953	struct fxp_softc *sc = device_get_softc(dev);
954	struct ifnet *ifp = &sc->sc_if;
955	u_int16_t pci_command;
956	int i, s;
957
958	s = splimp();
959
960	fxp_powerstate_d0(dev);
961
962	/* better way to do this? */
963	for (i = 0; i < 5; i++)
964		pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
965	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
966	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
967	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
968	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
969
970	/* reenable busmastering */
971	pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
972	pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
973	pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
974
975	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
976	DELAY(10);
977
978	/* reinitialize interface if necessary */
979	if (ifp->if_flags & IFF_UP)
980		fxp_init(sc);
981
982	sc->suspended = 0;
983
984	splx(s);
985	return (0);
986}
987
988static void
989fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
990{
991	u_int16_t reg;
992	int x;
993
994	/*
995	 * Shift in data.
996	 */
997	for (x = 1 << (length - 1); x; x >>= 1) {
998		if (data & x)
999			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1000		else
1001			reg = FXP_EEPROM_EECS;
1002		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1003		DELAY(1);
1004		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1005		DELAY(1);
1006		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1007		DELAY(1);
1008	}
1009}
1010
1011/*
1012 * Read from the serial EEPROM. Basically, you manually shift in
1013 * the read opcode (one bit at a time) and then shift in the address,
1014 * and then you shift out the data (all of this one bit at a time).
1015 * The word size is 16 bits, so you have to provide the address for
1016 * every 16 bits of data.
1017 */
1018static u_int16_t
1019fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1020{
1021	u_int16_t reg, data;
1022	int x;
1023
1024	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1025	/*
1026	 * Shift in read opcode.
1027	 */
1028	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1029	/*
1030	 * Shift in address.
1031	 */
1032	data = 0;
1033	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1034		if (offset & x)
1035			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1036		else
1037			reg = FXP_EEPROM_EECS;
1038		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1039		DELAY(1);
1040		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1041		DELAY(1);
1042		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1043		DELAY(1);
1044		reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1045		data++;
1046		if (autosize && reg == 0) {
1047			sc->eeprom_size = data;
1048			break;
1049		}
1050	}
1051	/*
1052	 * Shift out data.
1053	 */
1054	data = 0;
1055	reg = FXP_EEPROM_EECS;
1056	for (x = 1 << 15; x; x >>= 1) {
1057		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1058		DELAY(1);
1059		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1060			data |= x;
1061		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1062		DELAY(1);
1063	}
1064	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1065	DELAY(1);
1066
1067	return (data);
1068}
1069
1070static void
1071fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1072{
1073	int i;
1074
1075	/*
1076	 * Erase/write enable.
1077	 */
1078	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1079	fxp_eeprom_shiftin(sc, 0x4, 3);
1080	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1081	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1082	DELAY(1);
1083	/*
1084	 * Shift in write opcode, address, data.
1085	 */
1086	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1087	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1088	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1089	fxp_eeprom_shiftin(sc, data, 16);
1090	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1091	DELAY(1);
1092	/*
1093	 * Wait for EEPROM to finish up.
1094	 */
1095	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1096	DELAY(1);
1097	for (i = 0; i < 1000; i++) {
1098		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1099			break;
1100		DELAY(50);
1101	}
1102	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1103	DELAY(1);
1104	/*
1105	 * Erase/write disable.
1106	 */
1107	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1108	fxp_eeprom_shiftin(sc, 0x4, 3);
1109	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1110	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1111	DELAY(1);
1112}
1113
1114/*
1115 * From NetBSD:
1116 *
1117 * Figure out EEPROM size.
1118 *
1119 * 559's can have either 64-word or 256-word EEPROMs, the 558
1120 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1121 * talks about the existance of 16 to 256 word EEPROMs.
1122 *
1123 * The only known sizes are 64 and 256, where the 256 version is used
1124 * by CardBus cards to store CIS information.
1125 *
1126 * The address is shifted in msb-to-lsb, and after the last
1127 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1128 * after which follows the actual data. We try to detect this zero, by
1129 * probing the data-out bit in the EEPROM control register just after
1130 * having shifted in a bit. If the bit is zero, we assume we've
1131 * shifted enough address bits. The data-out should be tri-state,
1132 * before this, which should translate to a logical one.
1133 */
1134static void
1135fxp_autosize_eeprom(struct fxp_softc *sc)
1136{
1137
1138	/* guess maximum size of 256 words */
1139	sc->eeprom_size = 8;
1140
1141	/* autosize */
1142	(void) fxp_eeprom_getword(sc, 0, 1);
1143}
1144
1145static void
1146fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1147{
1148	int i;
1149
1150	for (i = 0; i < words; i++)
1151		data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1152}
1153
1154static void
1155fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1156{
1157	int i;
1158
1159	for (i = 0; i < words; i++)
1160		fxp_eeprom_putword(sc, offset + i, data[i]);
1161}
1162
1163static void
1164fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
1165    bus_size_t mapsize, int error)
1166{
1167	struct fxp_softc *sc;
1168	struct fxp_cb_tx *txp;
1169	int i;
1170
1171	if (error)
1172		return;
1173
1174	KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments"));
1175
1176	sc = arg;
1177	txp = sc->fxp_desc.tx_last->tx_next->tx_cb;
1178	for (i = 0; i < nseg; i++) {
1179		KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
1180		/*
1181		 * If this is an 82550/82551, then we're using extended
1182		 * TxCBs _and_ we're using checksum offload. This means
1183		 * that the TxCB is really an IPCB. One major difference
1184		 * between the two is that with plain extended TxCBs,
1185		 * the bottom half of the TxCB contains two entries from
1186		 * the TBD array, whereas IPCBs contain just one entry:
1187		 * one entry (8 bytes) has been sacrificed for the TCP/IP
1188		 * checksum offload control bits. So to make things work
1189		 * right, we have to start filling in the TBD array
1190		 * starting from a different place depending on whether
1191		 * the chip is an 82550/82551 or not.
1192		 */
1193		if (sc->flags & FXP_FLAG_EXT_RFA) {
1194			txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1195			txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1196		} else {
1197			txp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1198			txp->tbd[i].tb_size = htole32(segs[i].ds_len);
1199		}
1200	}
1201	txp->tbd_number = nseg;
1202}
1203
1204/*
1205 * Start packet transmission on the interface.
1206 */
1207static void
1208fxp_start(struct ifnet *ifp)
1209{
1210	struct fxp_softc *sc = ifp->if_softc;
1211	struct fxp_tx *txp, *last;
1212	struct mbuf *mb_head;
1213	int error;
1214
1215	/*
1216	 * See if we need to suspend xmit until the multicast filter
1217	 * has been reprogrammed (which can only be done at the head
1218	 * of the command chain).
1219	 */
1220	if (sc->need_mcsetup) {
1221		return;
1222	}
1223
1224	txp = NULL;
1225
1226	/*
1227	 * We're finished if there is nothing more to add to the list or if
1228	 * we're all filled up with buffers to transmit.
1229	 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1230	 *       a NOP command when needed.
1231	 */
1232	while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1233
1234		/*
1235		 * Grab a packet to transmit.
1236		 */
1237		IF_DEQUEUE(&ifp->if_snd, mb_head);
1238
1239		/*
1240		 * Get pointer to next available tx desc.
1241		 */
1242		txp = sc->fxp_desc.tx_last->tx_next;
1243
1244		/*
1245		 * Deal with TCP/IP checksum offload. Note that
1246		 * in order for TCP checksum offload to work,
1247		 * the pseudo header checksum must have already
1248		 * been computed and stored in the checksum field
1249		 * in the TCP header. The stack should have
1250		 * already done this for us.
1251		 */
1252
1253		if (mb_head->m_pkthdr.csum_flags) {
1254			if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1255				txp->tx_cb->ipcb_ip_activation_high =
1256				    FXP_IPCB_HARDWAREPARSING_ENABLE;
1257				txp->tx_cb->ipcb_ip_schedule =
1258				    FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1259				if (mb_head->m_pkthdr.csum_flags & CSUM_TCP)
1260					txp->tx_cb->ipcb_ip_schedule |=
1261					    FXP_IPCB_TCP_PACKET;
1262			}
1263#ifdef FXP_IP_CSUM_WAR
1264		/*
1265		 * XXX The 82550 chip appears to have trouble
1266		 * dealing with IP header checksums in very small
1267		 * datagrams, namely fragments from 1 to 3 bytes
1268		 * in size. For example, say you want to transmit
1269		 * a UDP packet of 1473 bytes. The packet will be
1270		 * fragmented over two IP datagrams, the latter
1271		 * containing only one byte of data. The 82550 will
1272		 * botch the header checksum on the 1-byte fragment.
1273		 * As long as the datagram contains 4 or more bytes
1274		 * of data, you're ok.
1275		 *
1276                 * The following code attempts to work around this
1277		 * problem: if the datagram is less than 38 bytes
1278		 * in size (14 bytes ether header, 20 bytes IP header,
1279		 * plus 4 bytes of data), we punt and compute the IP
1280		 * header checksum by hand. This workaround doesn't
1281		 * work very well, however, since it can be fooled
1282		 * by things like VLAN tags and IP options that make
1283		 * the header sizes/offsets vary.
1284		 */
1285
1286			if (mb_head->m_pkthdr.csum_flags & CSUM_IP) {
1287				if (mb_head->m_pkthdr.len < 38) {
1288					struct ip *ip;
1289					mb_head->m_data += ETHER_HDR_LEN;
1290					ip = mtod(mb_head, struct ip *);
1291					ip->ip_sum = in_cksum(mb_head,
1292					    ip->ip_hl << 2);
1293					mb_head->m_data -= ETHER_HDR_LEN;
1294				} else {
1295					txp->tx_cb->ipcb_ip_activation_high =
1296					    FXP_IPCB_HARDWAREPARSING_ENABLE;
1297					txp->tx_cb->ipcb_ip_schedule |=
1298					    FXP_IPCB_IP_CHECKSUM_ENABLE;
1299				}
1300			}
1301#endif
1302		}
1303
1304		/*
1305		 * Go through each of the mbufs in the chain and initialize
1306		 * the transmit buffer descriptors with the physical address
1307		 * and size of the mbuf.
1308		 */
1309		error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1310		    mb_head, fxp_dma_map_txbuf, sc, 0);
1311
1312		if (error && error != EFBIG) {
1313			device_printf(sc->dev, "can't map mbuf (error %d)\n",
1314			    error);
1315			m_freem(mb_head);
1316			break;
1317		}
1318
1319		if (error) {
1320			struct mbuf *mn;
1321
1322			/*
1323			 * We ran out of segments. We have to recopy this
1324			 * mbuf chain first. Bail out if we can't get the
1325			 * new buffers.
1326			 */
1327			MGETHDR(mn, M_DONTWAIT, MT_DATA);
1328			if (mn == NULL) {
1329				m_freem(mb_head);
1330				break;
1331			}
1332			if (mb_head->m_pkthdr.len > MHLEN) {
1333				MCLGET(mn, M_DONTWAIT);
1334				if ((mn->m_flags & M_EXT) == 0) {
1335					m_freem(mn);
1336					m_freem(mb_head);
1337					break;
1338				}
1339			}
1340			m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1341			    mtod(mn, caddr_t));
1342			mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1343			m_freem(mb_head);
1344			mb_head = mn;
1345			error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1346			    mb_head, fxp_dma_map_txbuf, sc, 0);
1347			if (error) {
1348				device_printf(sc->dev,
1349				    "can't map mbuf (error %d)\n", error);
1350				m_freem(mb_head);
1351				break;
1352			}
1353		}
1354
1355		bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1356		    BUS_DMASYNC_PREWRITE);
1357
1358		txp->tx_mbuf = mb_head;
1359		txp->tx_cb->cb_status = 0;
1360		txp->tx_cb->byte_count = 0;
1361		if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1362			txp->tx_cb->cb_command =
1363			    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1364			    FXP_CB_COMMAND_S);
1365		} else {
1366			txp->tx_cb->cb_command =
1367			    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1368			    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1369			/*
1370			 * Set a 5 second timer just in case we don't hear
1371			 * from the card again.
1372			 */
1373			ifp->if_timer = 5;
1374		}
1375		txp->tx_cb->tx_threshold = tx_threshold;
1376
1377		/*
1378		 * Advance the end of list forward.
1379		 */
1380
1381		/*
1382		 * On platforms which can't access memory in 16-bit
1383		 * granularities, we must prevent the card from DMA'ing
1384		 * up the status while we update the command field.
1385		 * This could cause us to overwrite the completion status.
1386		 *
1387		 * This is a bit tricky, because we want to avoid using
1388		 * atomic operations on 16bits values, since they may not
1389		 * be available on any architecture or may be very
1390		 * inefficient.
1391		 */
1392		last = sc->fxp_desc.tx_last;
1393		atomic_clear_32((u_int32_t *)&last->tx_cb->cb_status,
1394		    htobe32(bswap16(FXP_CB_COMMAND_S)));
1395
1396		sc->fxp_desc.tx_last = txp;
1397
1398		/*
1399		 * Advance the beginning of the list forward if there are
1400		 * no other packets queued (when nothing is queued, tx_first
1401		 * sits on the last TxCB that was sent out).
1402		 */
1403		if (sc->tx_queued == 0)
1404			sc->fxp_desc.tx_first = txp;
1405
1406		sc->tx_queued++;
1407
1408		/*
1409		 * Pass packet to bpf if there is a listener.
1410		 */
1411		BPF_MTAP(ifp, mb_head);
1412	}
1413	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1414
1415	/*
1416	 * We're finished. If we added to the list, issue a RESUME to get DMA
1417	 * going again if suspended.
1418	 */
1419	if (txp != NULL) {
1420		fxp_scb_wait(sc);
1421		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1422	}
1423}
1424
1425static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count);
1426
1427#ifdef DEVICE_POLLING
1428static poll_handler_t fxp_poll;
1429
1430static void
1431fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1432{
1433	struct fxp_softc *sc = ifp->if_softc;
1434	u_int8_t statack;
1435
1436	if (cmd == POLL_DEREGISTER) {	/* final call, enable interrupts */
1437		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1438		return;
1439	}
1440	statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1441	    FXP_SCB_STATACK_FR;
1442	if (cmd == POLL_AND_CHECK_STATUS) {
1443		u_int8_t tmp;
1444
1445		tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1446		if (tmp == 0xff || tmp == 0)
1447			return; /* nothing to do */
1448		tmp &= ~statack;
1449		/* ack what we can */
1450		if (tmp != 0)
1451			CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1452		statack |= tmp;
1453	}
1454	fxp_intr_body(sc, statack, count);
1455}
1456#endif /* DEVICE_POLLING */
1457
1458/*
1459 * Process interface interrupts.
1460 */
1461static void
1462fxp_intr(void *xsc)
1463{
1464	struct fxp_softc *sc = xsc;
1465	u_int8_t statack;
1466
1467#ifdef DEVICE_POLLING
1468	struct ifnet *ifp = &sc->sc_if;
1469
1470	if (ifp->if_flags & IFF_POLLING)
1471		return;
1472	if (ether_poll_register(fxp_poll, ifp)) {
1473		/* disable interrupts */
1474		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1475		fxp_poll(ifp, 0, 1);
1476		return;
1477	}
1478#endif
1479
1480	if (sc->suspended) {
1481		return;
1482	}
1483
1484	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1485		/*
1486		 * It should not be possible to have all bits set; the
1487		 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1488		 * all bits are set, this may indicate that the card has
1489		 * been physically ejected, so ignore it.
1490		 */
1491		if (statack == 0xff)
1492			return;
1493
1494		/*
1495		 * First ACK all the interrupts in this pass.
1496		 */
1497		CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1498		fxp_intr_body(sc, statack, -1);
1499	}
1500}
1501
1502static void
1503fxp_txeof(struct fxp_softc *sc)
1504{
1505	struct fxp_tx *txp;
1506
1507	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1508	for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1509	    (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1510	    txp = txp->tx_next) {
1511		if (txp->tx_mbuf != NULL) {
1512			bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1513			    BUS_DMASYNC_POSTWRITE);
1514			bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1515			m_freem(txp->tx_mbuf);
1516			txp->tx_mbuf = NULL;
1517			/* clear this to reset csum offload bits */
1518			txp->tx_cb->tbd[0].tb_addr = 0;
1519		}
1520		sc->tx_queued--;
1521	}
1522	sc->fxp_desc.tx_first = txp;
1523	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1524}
1525
1526static void
1527fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1528{
1529	struct ifnet *ifp = &sc->sc_if;
1530	struct mbuf *m;
1531	struct fxp_rx *rxp;
1532	struct fxp_rfa *rfa;
1533	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1534
1535	if (rnr)
1536		fxp_rnr++;
1537#ifdef DEVICE_POLLING
1538	/* Pick up a deferred RNR condition if `count' ran out last time. */
1539	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1540		sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1541		rnr = 1;
1542	}
1543#endif
1544
1545	/*
1546	 * Free any finished transmit mbuf chains.
1547	 *
1548	 * Handle the CNA event likt a CXTNO event. It used to
1549	 * be that this event (control unit not ready) was not
1550	 * encountered, but it is now with the SMPng modifications.
1551	 * The exact sequence of events that occur when the interface
1552	 * is brought up are different now, and if this event
1553	 * goes unhandled, the configuration/rxfilter setup sequence
1554	 * can stall for several seconds. The result is that no
1555	 * packets go out onto the wire for about 5 to 10 seconds
1556	 * after the interface is ifconfig'ed for the first time.
1557	 */
1558	if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1559		fxp_txeof(sc);
1560
1561		ifp->if_timer = 0;
1562		if (sc->tx_queued == 0) {
1563			if (sc->need_mcsetup)
1564				fxp_mc_setup(sc);
1565		}
1566		/*
1567		 * Try to start more packets transmitting.
1568		 */
1569		if (ifp->if_snd.ifq_head != NULL)
1570			fxp_start(ifp);
1571	}
1572
1573	/*
1574	 * Just return if nothing happened on the receive side.
1575	 */
1576	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1577		return;
1578
1579	/*
1580	 * Process receiver interrupts. If a no-resource (RNR)
1581	 * condition exists, get whatever packets we can and
1582	 * re-start the receiver.
1583	 *
1584	 * When using polling, we do not process the list to completion,
1585	 * so when we get an RNR interrupt we must defer the restart
1586	 * until we hit the last buffer with the C bit set.
1587	 * If we run out of cycles and rfa_headm has the C bit set,
1588	 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1589	 * that the info will be used in the subsequent polling cycle.
1590	 */
1591	for (;;) {
1592		rxp = sc->fxp_desc.rx_head;
1593		m = rxp->rx_mbuf;
1594		rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1595		    RFA_ALIGNMENT_FUDGE);
1596		bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1597		    BUS_DMASYNC_POSTREAD);
1598
1599#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1600		if (count >= 0 && count-- == 0) {
1601			if (rnr) {
1602				/* Defer RNR processing until the next time. */
1603				sc->flags |= FXP_FLAG_DEFERRED_RNR;
1604				rnr = 0;
1605			}
1606			break;
1607		}
1608#endif /* DEVICE_POLLING */
1609
1610		if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0)
1611			break;
1612
1613		/*
1614		 * Advance head forward.
1615		 */
1616		sc->fxp_desc.rx_head = rxp->rx_next;
1617
1618		/*
1619		 * Add a new buffer to the receive chain.
1620		 * If this fails, the old buffer is recycled
1621		 * instead.
1622		 */
1623		if (fxp_add_rfabuf(sc, rxp) == 0) {
1624			int total_len;
1625
1626			/*
1627			 * Fetch packet length (the top 2 bits of
1628			 * actual_size are flags set by the controller
1629			 * upon completion), and drop the packet in case
1630			 * of bogus length or CRC errors.
1631			 */
1632			total_len = le16toh(rfa->actual_size & 0x3fff);
1633			if (total_len < sizeof(struct ether_header) ||
1634			    total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1635				sc->rfa_size ||
1636			    le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) {
1637				m_freem(m);
1638				continue;
1639			}
1640
1641                        /* Do IP checksum checking. */
1642			if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) {
1643				if (rfa->rfax_csum_sts &
1644				    FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1645					m->m_pkthdr.csum_flags |=
1646					    CSUM_IP_CHECKED;
1647				if (rfa->rfax_csum_sts &
1648				    FXP_RFDX_CS_IP_CSUM_VALID)
1649					m->m_pkthdr.csum_flags |=
1650					    CSUM_IP_VALID;
1651				if ((rfa->rfax_csum_sts &
1652				    FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1653				    (rfa->rfax_csum_sts &
1654				    FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1655					m->m_pkthdr.csum_flags |=
1656					    CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1657					m->m_pkthdr.csum_data = 0xffff;
1658				}
1659			}
1660
1661			m->m_pkthdr.len = m->m_len = total_len;
1662			m->m_pkthdr.rcvif = ifp;
1663
1664			(*ifp->if_input)(ifp, m);
1665		}
1666	}
1667	if (rnr) {
1668		fxp_scb_wait(sc);
1669		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1670		    sc->fxp_desc.rx_head->rx_addr);
1671		fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1672	}
1673}
1674
1675/*
1676 * Update packet in/out/collision statistics. The i82557 doesn't
1677 * allow you to access these counters without doing a fairly
1678 * expensive DMA to get _all_ of the statistics it maintains, so
1679 * we do this operation here only once per second. The statistics
1680 * counters in the kernel are updated from the previous dump-stats
1681 * DMA and then a new dump-stats DMA is started. The on-chip
1682 * counters are zeroed when the DMA completes. If we can't start
1683 * the DMA immediately, we don't wait - we just prepare to read
1684 * them again next time.
1685 */
1686static void
1687fxp_tick(void *xsc)
1688{
1689	struct fxp_softc *sc = xsc;
1690	struct ifnet *ifp = &sc->sc_if;
1691	struct fxp_stats *sp = sc->fxp_stats;
1692	int s;
1693
1694	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1695	ifp->if_opackets += le32toh(sp->tx_good);
1696	ifp->if_collisions += le32toh(sp->tx_total_collisions);
1697	if (sp->rx_good) {
1698		ifp->if_ipackets += le32toh(sp->rx_good);
1699		sc->rx_idle_secs = 0;
1700	} else {
1701		/*
1702		 * Receiver's been idle for another second.
1703		 */
1704		sc->rx_idle_secs++;
1705	}
1706	ifp->if_ierrors +=
1707	    le32toh(sp->rx_crc_errors) +
1708	    le32toh(sp->rx_alignment_errors) +
1709	    le32toh(sp->rx_rnr_errors) +
1710	    le32toh(sp->rx_overrun_errors);
1711	/*
1712	 * If any transmit underruns occured, bump up the transmit
1713	 * threshold by another 512 bytes (64 * 8).
1714	 */
1715	if (sp->tx_underruns) {
1716		ifp->if_oerrors += le32toh(sp->tx_underruns);
1717		if (tx_threshold < 192)
1718			tx_threshold += 64;
1719	}
1720	s = splimp();
1721	/*
1722	 * Release any xmit buffers that have completed DMA. This isn't
1723	 * strictly necessary to do here, but it's advantagous for mbufs
1724	 * with external storage to be released in a timely manner rather
1725	 * than being defered for a potentially long time. This limits
1726	 * the delay to a maximum of one second.
1727	 */
1728	fxp_txeof(sc);
1729
1730	/*
1731	 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1732	 * then assume the receiver has locked up and attempt to clear
1733	 * the condition by reprogramming the multicast filter. This is
1734	 * a work-around for a bug in the 82557 where the receiver locks
1735	 * up if it gets certain types of garbage in the syncronization
1736	 * bits prior to the packet header. This bug is supposed to only
1737	 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1738	 * mode as well (perhaps due to a 10/100 speed transition).
1739	 */
1740	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1741		sc->rx_idle_secs = 0;
1742		fxp_mc_setup(sc);
1743	}
1744	/*
1745	 * If there is no pending command, start another stats
1746	 * dump. Otherwise punt for now.
1747	 */
1748	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1749		/*
1750		 * Start another stats dump.
1751		 */
1752		bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
1753		    BUS_DMASYNC_PREREAD);
1754		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1755	} else {
1756		/*
1757		 * A previous command is still waiting to be accepted.
1758		 * Just zero our copy of the stats and wait for the
1759		 * next timer event to update them.
1760		 */
1761		sp->tx_good = 0;
1762		sp->tx_underruns = 0;
1763		sp->tx_total_collisions = 0;
1764
1765		sp->rx_good = 0;
1766		sp->rx_crc_errors = 0;
1767		sp->rx_alignment_errors = 0;
1768		sp->rx_rnr_errors = 0;
1769		sp->rx_overrun_errors = 0;
1770	}
1771	if (sc->miibus != NULL)
1772		mii_tick(device_get_softc(sc->miibus));
1773	splx(s);
1774	/*
1775	 * Schedule another timeout one second from now.
1776	 */
1777	sc->stat_ch = timeout(fxp_tick, sc, hz);
1778}
1779
1780/*
1781 * Stop the interface. Cancels the statistics updater and resets
1782 * the interface.
1783 */
1784static void
1785fxp_stop(struct fxp_softc *sc)
1786{
1787	struct ifnet *ifp = &sc->sc_if;
1788	struct fxp_tx *txp;
1789	int i;
1790
1791	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1792	ifp->if_timer = 0;
1793
1794#ifdef DEVICE_POLLING
1795	ether_poll_deregister(ifp);
1796#endif
1797	/*
1798	 * Cancel stats updater.
1799	 */
1800	untimeout(fxp_tick, sc, sc->stat_ch);
1801
1802	/*
1803	 * Issue software reset, which also unloads the microcode.
1804	 */
1805	sc->flags &= ~FXP_FLAG_UCODE;
1806	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1807	DELAY(50);
1808
1809	/*
1810	 * Release any xmit buffers.
1811	 */
1812	txp = sc->fxp_desc.tx_list;
1813	if (txp != NULL) {
1814		for (i = 0; i < FXP_NTXCB; i++) {
1815			if (txp[i].tx_mbuf != NULL) {
1816				bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
1817				    BUS_DMASYNC_POSTWRITE);
1818				bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
1819				m_freem(txp[i].tx_mbuf);
1820				txp[i].tx_mbuf = NULL;
1821				/* clear this to reset csum offload bits */
1822				txp[i].tx_cb->tbd[0].tb_addr = 0;
1823			}
1824		}
1825	}
1826	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1827	sc->tx_queued = 0;
1828}
1829
1830/*
1831 * Watchdog/transmission transmit timeout handler. Called when a
1832 * transmission is started on the interface, but no interrupt is
1833 * received before the timeout. This usually indicates that the
1834 * card has wedged for some reason.
1835 */
1836static void
1837fxp_watchdog(struct ifnet *ifp)
1838{
1839	struct fxp_softc *sc = ifp->if_softc;
1840
1841	device_printf(sc->dev, "device timeout\n");
1842	ifp->if_oerrors++;
1843
1844	fxp_init(sc);
1845}
1846
1847static void
1848fxp_init(void *xsc)
1849{
1850	struct fxp_softc *sc = xsc;
1851	struct ifnet *ifp = &sc->sc_if;
1852	struct fxp_cb_config *cbp;
1853	struct fxp_cb_ias *cb_ias;
1854	struct fxp_cb_tx *tcbp;
1855	struct fxp_tx *txp;
1856	struct fxp_cb_mcs *mcsp;
1857	int i, prm, s;
1858
1859	s = splimp();
1860	/*
1861	 * Cancel any pending I/O
1862	 */
1863	fxp_stop(sc);
1864
1865	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1866
1867	/*
1868	 * Initialize base of CBL and RFA memory. Loading with zero
1869	 * sets it up for regular linear addressing.
1870	 */
1871	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1872	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1873
1874	fxp_scb_wait(sc);
1875	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1876
1877	/*
1878	 * Initialize base of dump-stats buffer.
1879	 */
1880	fxp_scb_wait(sc);
1881	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
1882	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
1883	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1884
1885	/*
1886	 * Attempt to load microcode if requested.
1887	 */
1888	if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1889		fxp_load_ucode(sc);
1890
1891	/*
1892	 * Initialize the multicast address list.
1893	 */
1894	if (fxp_mc_addrs(sc)) {
1895		mcsp = sc->mcsp;
1896		mcsp->cb_status = 0;
1897		mcsp->cb_command =
1898		    htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
1899		mcsp->link_addr = 0xffffffff;
1900		/*
1901	 	 * Start the multicast setup command.
1902		 */
1903		fxp_scb_wait(sc);
1904		bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
1905		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
1906		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1907		/* ...and wait for it to complete. */
1908		fxp_dma_wait(&mcsp->cb_status, sc);
1909		bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
1910		    BUS_DMASYNC_POSTWRITE);
1911	}
1912
1913	/*
1914	 * We temporarily use memory that contains the TxCB list to
1915	 * construct the config CB. The TxCB list memory is rebuilt
1916	 * later.
1917	 */
1918	cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
1919
1920	/*
1921	 * This bcopy is kind of disgusting, but there are a bunch of must be
1922	 * zero and must be one bits in this structure and this is the easiest
1923	 * way to initialize them all to proper values.
1924	 */
1925	bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
1926
1927	cbp->cb_status =	0;
1928	cbp->cb_command =	htole16(FXP_CB_COMMAND_CONFIG |
1929	    FXP_CB_COMMAND_EL);
1930	cbp->link_addr =	0xffffffff;	/* (no) next command */
1931	cbp->byte_count =	sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
1932	cbp->rx_fifo_limit =	8;	/* rx fifo threshold (32 bytes) */
1933	cbp->tx_fifo_limit =	0;	/* tx fifo threshold (0 bytes) */
1934	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
1935	cbp->mwi_enable =	sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1936	cbp->type_enable =	0;	/* actually reserved */
1937	cbp->read_align_en =	sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1938	cbp->end_wr_on_cl =	sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1939	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
1940	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
1941	cbp->dma_mbce =		0;	/* (disable) dma max counters */
1942	cbp->late_scb =		0;	/* (don't) defer SCB update */
1943	cbp->direct_dma_dis =	1;	/* disable direct rcv dma mode */
1944	cbp->tno_int_or_tco_en =0;	/* (disable) tx not okay interrupt */
1945	cbp->ci_int =		1;	/* interrupt on CU idle */
1946	cbp->ext_txcb_dis = 	sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1947	cbp->ext_stats_dis = 	1;	/* disable extended counters */
1948	cbp->keep_overrun_rx = 	0;	/* don't pass overrun frames to host */
1949	cbp->save_bf =		sc->revision == FXP_REV_82557 ? 1 : prm;
1950	cbp->disc_short_rx =	!prm;	/* discard short packets */
1951	cbp->underrun_retry =	1;	/* retry mode (once) on DMA underrun */
1952	cbp->two_frames =	0;	/* do not limit FIFO to 2 frames */
1953	cbp->dyn_tbd =		0;	/* (no) dynamic TBD mode */
1954	cbp->ext_rfa =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
1955	cbp->mediatype =	sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1956	cbp->csma_dis =		0;	/* (don't) disable link */
1957	cbp->tcp_udp_cksum =	0;	/* (don't) enable checksum */
1958	cbp->vlan_tco =		0;	/* (don't) enable vlan wakeup */
1959	cbp->link_wake_en =	0;	/* (don't) assert PME# on link change */
1960	cbp->arp_wake_en =	0;	/* (don't) assert PME# on arp */
1961	cbp->mc_wake_en =	0;	/* (don't) enable PME# on mcmatch */
1962	cbp->nsai =		1;	/* (don't) disable source addr insert */
1963	cbp->preamble_length =	2;	/* (7 byte) preamble */
1964	cbp->loopback =		0;	/* (don't) loopback */
1965	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
1966	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
1967	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
1968	cbp->promiscuous =	prm;	/* promiscuous mode */
1969	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
1970	cbp->wait_after_win =	0;	/* (don't) enable modified backoff alg*/
1971	cbp->ignore_ul =	0;	/* consider U/L bit in IA matching */
1972	cbp->crc16_en =		0;	/* (don't) enable crc-16 algorithm */
1973	cbp->crscdt =		sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1974
1975	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
1976	cbp->padding =		1;	/* (do) pad short tx packets */
1977	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
1978	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1979	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
1980	cbp->magic_pkt_dis =	0;	/* (don't) disable magic packet */
1981					/* must set wake_en in PMCSR also */
1982	cbp->force_fdx =	0;	/* (don't) force full duplex */
1983	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
1984	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
1985	cbp->mc_all =		sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1986	cbp->gamla_rx =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
1987
1988	if (sc->revision == FXP_REV_82557) {
1989		/*
1990		 * The 82557 has no hardware flow control, the values
1991		 * below are the defaults for the chip.
1992		 */
1993		cbp->fc_delay_lsb =	0;
1994		cbp->fc_delay_msb =	0x40;
1995		cbp->pri_fc_thresh =	3;
1996		cbp->tx_fc_dis =	0;
1997		cbp->rx_fc_restop =	0;
1998		cbp->rx_fc_restart =	0;
1999		cbp->fc_filter =	0;
2000		cbp->pri_fc_loc =	1;
2001	} else {
2002		cbp->fc_delay_lsb =	0x1f;
2003		cbp->fc_delay_msb =	0x01;
2004		cbp->pri_fc_thresh =	3;
2005		cbp->tx_fc_dis =	0;	/* enable transmit FC */
2006		cbp->rx_fc_restop =	1;	/* enable FC restop frames */
2007		cbp->rx_fc_restart =	1;	/* enable FC restart frames */
2008		cbp->fc_filter =	!prm;	/* drop FC frames to host */
2009		cbp->pri_fc_loc =	1;	/* FC pri location (byte31) */
2010	}
2011
2012	/*
2013	 * Start the config command/DMA.
2014	 */
2015	fxp_scb_wait(sc);
2016	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2017	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2018	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2019	/* ...and wait for it to complete. */
2020	fxp_dma_wait(&cbp->cb_status, sc);
2021	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2022
2023	/*
2024	 * Now initialize the station address. Temporarily use the TxCB
2025	 * memory area like we did above for the config CB.
2026	 */
2027	cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2028	cb_ias->cb_status = 0;
2029	cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2030	cb_ias->link_addr = 0xffffffff;
2031	bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr,
2032	    sizeof(sc->arpcom.ac_enaddr));
2033
2034	/*
2035	 * Start the IAS (Individual Address Setup) command/DMA.
2036	 */
2037	fxp_scb_wait(sc);
2038	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2039	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2040	/* ...and wait for it to complete. */
2041	fxp_dma_wait(&cb_ias->cb_status, sc);
2042	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2043
2044	/*
2045	 * Initialize transmit control block (TxCB) list.
2046	 */
2047	txp = sc->fxp_desc.tx_list;
2048	tcbp = sc->fxp_desc.cbl_list;
2049	bzero(tcbp, FXP_TXCB_SZ);
2050	for (i = 0; i < FXP_NTXCB; i++) {
2051		txp[i].tx_cb = tcbp + i;
2052		txp[i].tx_mbuf = NULL;
2053		tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2054		tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2055		tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2056		    (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2057		if (sc->flags & FXP_FLAG_EXT_TXCB)
2058			tcbp[i].tbd_array_addr =
2059			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2060		else
2061			tcbp[i].tbd_array_addr =
2062			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2063		txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2064	}
2065	/*
2066	 * Set the suspend flag on the first TxCB and start the control
2067	 * unit. It will execute the NOP and then suspend.
2068	 */
2069	tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2070	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2071	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2072	sc->tx_queued = 1;
2073
2074	fxp_scb_wait(sc);
2075	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2076
2077	/*
2078	 * Initialize receiver buffer area - RFA.
2079	 */
2080	fxp_scb_wait(sc);
2081	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2082	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2083
2084	/*
2085	 * Set current media.
2086	 */
2087	if (sc->miibus != NULL)
2088		mii_mediachg(device_get_softc(sc->miibus));
2089
2090	ifp->if_flags |= IFF_RUNNING;
2091	ifp->if_flags &= ~IFF_OACTIVE;
2092
2093	/*
2094	 * Enable interrupts.
2095	 */
2096#ifdef DEVICE_POLLING
2097	/*
2098	 * ... but only do that if we are not polling. And because (presumably)
2099	 * the default is interrupts on, we need to disable them explicitly!
2100	 */
2101	if ( ifp->if_flags & IFF_POLLING )
2102		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2103	else
2104#endif /* DEVICE_POLLING */
2105	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2106	splx(s);
2107
2108	/*
2109	 * Start stats updater.
2110	 */
2111	sc->stat_ch = timeout(fxp_tick, sc, hz);
2112}
2113
2114static int
2115fxp_serial_ifmedia_upd(struct ifnet *ifp)
2116{
2117
2118	return (0);
2119}
2120
2121static void
2122fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2123{
2124
2125	ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2126}
2127
2128/*
2129 * Change media according to request.
2130 */
2131static int
2132fxp_ifmedia_upd(struct ifnet *ifp)
2133{
2134	struct fxp_softc *sc = ifp->if_softc;
2135	struct mii_data *mii;
2136
2137	mii = device_get_softc(sc->miibus);
2138	mii_mediachg(mii);
2139	return (0);
2140}
2141
2142/*
2143 * Notify the world which media we're using.
2144 */
2145static void
2146fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2147{
2148	struct fxp_softc *sc = ifp->if_softc;
2149	struct mii_data *mii;
2150
2151	mii = device_get_softc(sc->miibus);
2152	mii_pollstat(mii);
2153	ifmr->ifm_active = mii->mii_media_active;
2154	ifmr->ifm_status = mii->mii_media_status;
2155
2156	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
2157		sc->cu_resume_bug = 1;
2158	else
2159		sc->cu_resume_bug = 0;
2160}
2161
2162/*
2163 * Add a buffer to the end of the RFA buffer list.
2164 * Return 0 if successful, 1 for failure. A failure results in
2165 * adding the 'oldm' (if non-NULL) on to the end of the list -
2166 * tossing out its old contents and recycling it.
2167 * The RFA struct is stuck at the beginning of mbuf cluster and the
2168 * data pointer is fixed up to point just past it.
2169 */
2170static int
2171fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2172{
2173	struct mbuf *m;
2174	struct fxp_rfa *rfa, *p_rfa;
2175	struct fxp_rx *p_rx;
2176	bus_dmamap_t tmp_map;
2177	int error;
2178
2179	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2180	if (m == NULL)
2181		return (ENOBUFS);
2182
2183	/*
2184	 * Move the data pointer up so that the incoming data packet
2185	 * will be 32-bit aligned.
2186	 */
2187	m->m_data += RFA_ALIGNMENT_FUDGE;
2188
2189	/*
2190	 * Get a pointer to the base of the mbuf cluster and move
2191	 * data start past it.
2192	 */
2193	rfa = mtod(m, struct fxp_rfa *);
2194	m->m_data += sc->rfa_size;
2195	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2196
2197	/*
2198	 * Initialize the rest of the RFA.  Note that since the RFA
2199	 * is misaligned, we cannot store values directly.  Instead,
2200	 * we use an optimized, inline copy.
2201	 */
2202
2203	rfa->rfa_status = 0;
2204	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2205	rfa->actual_size = 0;
2206
2207	le32enc(&rfa->link_addr, 0xffffffff);
2208	le32enc(&rfa->rbd_addr, 0xffffffff);
2209
2210	/* Map the RFA into DMA memory. */
2211	error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2212	    MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2213	    &rxp->rx_addr, 0);
2214	if (error) {
2215		m_freem(m);
2216		return (error);
2217	}
2218
2219	bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2220	tmp_map = sc->spare_map;
2221	sc->spare_map = rxp->rx_map;
2222	rxp->rx_map = tmp_map;
2223	rxp->rx_mbuf = m;
2224
2225	bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, BUS_DMASYNC_PREWRITE);
2226
2227	/*
2228	 * If there are other buffers already on the list, attach this
2229	 * one to the end by fixing up the tail to point to this one.
2230	 */
2231	if (sc->fxp_desc.rx_head != NULL) {
2232		p_rx = sc->fxp_desc.rx_tail;
2233		p_rfa = (struct fxp_rfa *)
2234		    (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2235		p_rx->rx_next = rxp;
2236		le32enc(&p_rfa->link_addr, rxp->rx_addr);
2237		p_rfa->rfa_control = 0;
2238		bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2239		    BUS_DMASYNC_PREWRITE);
2240	} else {
2241		rxp->rx_next = NULL;
2242		sc->fxp_desc.rx_head = rxp;
2243	}
2244	sc->fxp_desc.rx_tail = rxp;
2245	return (0);
2246}
2247
2248static volatile int
2249fxp_miibus_readreg(device_t dev, int phy, int reg)
2250{
2251	struct fxp_softc *sc = device_get_softc(dev);
2252	int count = 10000;
2253	int value;
2254
2255	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2256	    (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2257
2258	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2259	    && count--)
2260		DELAY(10);
2261
2262	if (count <= 0)
2263		device_printf(dev, "fxp_miibus_readreg: timed out\n");
2264
2265	return (value & 0xffff);
2266}
2267
2268static void
2269fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2270{
2271	struct fxp_softc *sc = device_get_softc(dev);
2272	int count = 10000;
2273
2274	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2275	    (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2276	    (value & 0xffff));
2277
2278	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2279	    count--)
2280		DELAY(10);
2281
2282	if (count <= 0)
2283		device_printf(dev, "fxp_miibus_writereg: timed out\n");
2284}
2285
2286static int
2287fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2288{
2289	struct fxp_softc *sc = ifp->if_softc;
2290	struct ifreq *ifr = (struct ifreq *)data;
2291	struct mii_data *mii;
2292	int s, error = 0;
2293
2294	s = splimp();
2295
2296	switch (command) {
2297	case SIOCSIFFLAGS:
2298		if (ifp->if_flags & IFF_ALLMULTI)
2299			sc->flags |= FXP_FLAG_ALL_MCAST;
2300		else
2301			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2302
2303		/*
2304		 * If interface is marked up and not running, then start it.
2305		 * If it is marked down and running, stop it.
2306		 * XXX If it's up then re-initialize it. This is so flags
2307		 * such as IFF_PROMISC are handled.
2308		 */
2309		if (ifp->if_flags & IFF_UP) {
2310			fxp_init(sc);
2311		} else {
2312			if (ifp->if_flags & IFF_RUNNING)
2313				fxp_stop(sc);
2314		}
2315		break;
2316
2317	case SIOCADDMULTI:
2318	case SIOCDELMULTI:
2319		if (ifp->if_flags & IFF_ALLMULTI)
2320			sc->flags |= FXP_FLAG_ALL_MCAST;
2321		else
2322			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2323		/*
2324		 * Multicast list has changed; set the hardware filter
2325		 * accordingly.
2326		 */
2327		if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2328			fxp_mc_setup(sc);
2329		/*
2330		 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2331		 * again rather than else {}.
2332		 */
2333		if (sc->flags & FXP_FLAG_ALL_MCAST)
2334			fxp_init(sc);
2335		error = 0;
2336		break;
2337
2338	case SIOCSIFMEDIA:
2339	case SIOCGIFMEDIA:
2340		if (sc->miibus != NULL) {
2341			mii = device_get_softc(sc->miibus);
2342                        error = ifmedia_ioctl(ifp, ifr,
2343                            &mii->mii_media, command);
2344		} else {
2345                        error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2346		}
2347		break;
2348
2349	default:
2350		error = ether_ioctl(ifp, command, data);
2351	}
2352	splx(s);
2353	return (error);
2354}
2355
2356/*
2357 * Fill in the multicast address list and return number of entries.
2358 */
2359static int
2360fxp_mc_addrs(struct fxp_softc *sc)
2361{
2362	struct fxp_cb_mcs *mcsp = sc->mcsp;
2363	struct ifnet *ifp = &sc->sc_if;
2364	struct ifmultiaddr *ifma;
2365	int nmcasts;
2366
2367	nmcasts = 0;
2368	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2369#if __FreeBSD_version < 500000
2370		LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2371#else
2372		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2373#endif
2374			if (ifma->ifma_addr->sa_family != AF_LINK)
2375				continue;
2376			if (nmcasts >= MAXMCADDR) {
2377				sc->flags |= FXP_FLAG_ALL_MCAST;
2378				nmcasts = 0;
2379				break;
2380			}
2381			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2382			    &sc->mcsp->mc_addr[nmcasts][0], 6);
2383			nmcasts++;
2384		}
2385	}
2386	mcsp->mc_cnt = htole16(nmcasts * 6);
2387	return (nmcasts);
2388}
2389
2390/*
2391 * Program the multicast filter.
2392 *
2393 * We have an artificial restriction that the multicast setup command
2394 * must be the first command in the chain, so we take steps to ensure
2395 * this. By requiring this, it allows us to keep up the performance of
2396 * the pre-initialized command ring (esp. link pointers) by not actually
2397 * inserting the mcsetup command in the ring - i.e. its link pointer
2398 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2399 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2400 * lead into the regular TxCB ring when it completes.
2401 *
2402 * This function must be called at splimp.
2403 */
2404static void
2405fxp_mc_setup(struct fxp_softc *sc)
2406{
2407	struct fxp_cb_mcs *mcsp = sc->mcsp;
2408	struct ifnet *ifp = &sc->sc_if;
2409	struct fxp_tx *txp;
2410	int count;
2411
2412	/*
2413	 * If there are queued commands, we must wait until they are all
2414	 * completed. If we are already waiting, then add a NOP command
2415	 * with interrupt option so that we're notified when all commands
2416	 * have been completed - fxp_start() ensures that no additional
2417	 * TX commands will be added when need_mcsetup is true.
2418	 */
2419	if (sc->tx_queued) {
2420		/*
2421		 * need_mcsetup will be true if we are already waiting for the
2422		 * NOP command to be completed (see below). In this case, bail.
2423		 */
2424		if (sc->need_mcsetup)
2425			return;
2426		sc->need_mcsetup = 1;
2427
2428		/*
2429		 * Add a NOP command with interrupt so that we are notified
2430		 * when all TX commands have been processed.
2431		 */
2432		txp = sc->fxp_desc.tx_last->tx_next;
2433		txp->tx_mbuf = NULL;
2434		txp->tx_cb->cb_status = 0;
2435		txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2436		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2437		/*
2438		 * Advance the end of list forward.
2439		 */
2440		sc->fxp_desc.tx_last->tx_cb->cb_command &=
2441		    htole16(~FXP_CB_COMMAND_S);
2442		bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2443		sc->fxp_desc.tx_last = txp;
2444		sc->tx_queued++;
2445		/*
2446		 * Issue a resume in case the CU has just suspended.
2447		 */
2448		fxp_scb_wait(sc);
2449		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2450		/*
2451		 * Set a 5 second timer just in case we don't hear from the
2452		 * card again.
2453		 */
2454		ifp->if_timer = 5;
2455
2456		return;
2457	}
2458	sc->need_mcsetup = 0;
2459
2460	/*
2461	 * Initialize multicast setup descriptor.
2462	 */
2463	mcsp->cb_status = 0;
2464	mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2465	    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2466	mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2467	txp = &sc->fxp_desc.mcs_tx;
2468	txp->tx_mbuf = NULL;
2469	txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2470	txp->tx_next = sc->fxp_desc.tx_list;
2471	(void) fxp_mc_addrs(sc);
2472	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2473	sc->tx_queued = 1;
2474
2475	/*
2476	 * Wait until command unit is not active. This should never
2477	 * be the case when nothing is queued, but make sure anyway.
2478	 */
2479	count = 100;
2480	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2481	    FXP_SCB_CUS_ACTIVE && --count)
2482		DELAY(10);
2483	if (count == 0) {
2484		device_printf(sc->dev, "command queue timeout\n");
2485		return;
2486	}
2487
2488	/*
2489	 * Start the multicast setup command.
2490	 */
2491	fxp_scb_wait(sc);
2492	bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2493	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2494	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2495
2496	ifp->if_timer = 2;
2497	return;
2498}
2499
2500static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2501static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2502static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2503static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2504static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2505static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2506
2507#define UCODE(x)	x, sizeof(x)
2508
2509struct ucode {
2510	u_int32_t	revision;
2511	u_int32_t	*ucode;
2512	int		length;
2513	u_short		int_delay_offset;
2514	u_short		bundle_max_offset;
2515} ucode_table[] = {
2516	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2517	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2518	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2519	    D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2520	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2521	    D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2522	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
2523	    D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2524	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2525	    D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2526	{ 0, NULL, 0, 0, 0 }
2527};
2528
2529static void
2530fxp_load_ucode(struct fxp_softc *sc)
2531{
2532	struct ucode *uc;
2533	struct fxp_cb_ucode *cbp;
2534
2535	for (uc = ucode_table; uc->ucode != NULL; uc++)
2536		if (sc->revision == uc->revision)
2537			break;
2538	if (uc->ucode == NULL)
2539		return;
2540	cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2541	cbp->cb_status = 0;
2542	cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2543	cbp->link_addr = 0xffffffff;    	/* (no) next command */
2544	memcpy(cbp->ucode, uc->ucode, uc->length);
2545	if (uc->int_delay_offset)
2546		*(u_int16_t *)&cbp->ucode[uc->int_delay_offset] =
2547		    htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2548	if (uc->bundle_max_offset)
2549		*(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] =
2550		    htole16(sc->tunable_bundle_max);
2551	/*
2552	 * Download the ucode to the chip.
2553	 */
2554	fxp_scb_wait(sc);
2555	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2556	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2557	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2558	/* ...and wait for it to complete. */
2559	fxp_dma_wait(&cbp->cb_status, sc);
2560	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2561	device_printf(sc->dev,
2562	    "Microcode loaded, int_delay: %d usec  bundle_max: %d\n",
2563	    sc->tunable_int_delay,
2564	    uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2565	sc->flags |= FXP_FLAG_UCODE;
2566}
2567
2568static int
2569sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2570{
2571	int error, value;
2572
2573	value = *(int *)arg1;
2574	error = sysctl_handle_int(oidp, &value, 0, req);
2575	if (error || !req->newptr)
2576		return (error);
2577	if (value < low || value > high)
2578		return (EINVAL);
2579	*(int *)arg1 = value;
2580	return (0);
2581}
2582
2583/*
2584 * Interrupt delay is expressed in microseconds, a multiplier is used
2585 * to convert this to the appropriate clock ticks before using.
2586 */
2587static int
2588sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2589{
2590	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2591}
2592
2593static int
2594sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2595{
2596	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2597}
2598