if_fxp.c revision 112005
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 112005 2003-03-08 21:44:21Z jdp $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/sysctl.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#include <net/bpf.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <net/ethernet.h> 56#include <net/if_arp.h> 57 58#include <vm/vm.h> /* for vtophys */ 59#include <vm/pmap.h> /* for vtophys */ 60#include <machine/clock.h> /* for DELAY */ 61 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#ifdef FXP_IP_CSUM_WAR 66#include <netinet/in.h> 67#include <netinet/in_systm.h> 68#include <netinet/ip.h> 69#include <machine/in_cksum.h> 70#endif 71 72#include <pci/pcivar.h> 73#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75#include <dev/mii/mii.h> 76#include <dev/mii/miivar.h> 77 78#include <dev/fxp/if_fxpreg.h> 79#include <dev/fxp/if_fxpvar.h> 80#include <dev/fxp/rcvbundl.h> 81 82MODULE_DEPEND(fxp, miibus, 1, 1, 1); 83#include "miibus_if.h" 84 85/* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94#define RFA_ALIGNMENT_FUDGE 2 95 96/* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101static int tx_threshold = 64; 102 103/* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137}; 138 139struct fxp_ident { 140 u_int16_t devid; 141 char *name; 142}; 143 144/* 145 * Claim various Intel PCI device identifiers for this driver. The 146 * sub-vendor and sub-device field are extensively used to identify 147 * particular variants, but we don't currently differentiate between 148 * them. 149 */ 150static struct fxp_ident fxp_ident_table[] = { 151 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 152 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 153 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 162 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 163 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 164 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 168 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 169 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 170 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 171 { 0, NULL }, 172}; 173 174#ifdef FXP_IP_CSUM_WAR 175#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 176#else 177#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 178#endif 179 180static int fxp_probe(device_t dev); 181static int fxp_attach(device_t dev); 182static int fxp_detach(device_t dev); 183static int fxp_shutdown(device_t dev); 184static int fxp_suspend(device_t dev); 185static int fxp_resume(device_t dev); 186 187static void fxp_intr(void *xsc); 188static void fxp_init(void *xsc); 189static void fxp_tick(void *xsc); 190static void fxp_powerstate_d0(device_t dev); 191static void fxp_start(struct ifnet *ifp); 192static void fxp_stop(struct fxp_softc *sc); 193static void fxp_release(struct fxp_softc *sc); 194static int fxp_ioctl(struct ifnet *ifp, u_long command, 195 caddr_t data); 196static void fxp_watchdog(struct ifnet *ifp); 197static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 198static int fxp_mc_addrs(struct fxp_softc *sc); 199static void fxp_mc_setup(struct fxp_softc *sc); 200static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 201 int autosize); 202static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 203 u_int16_t data); 204static void fxp_autosize_eeprom(struct fxp_softc *sc); 205static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 206 int offset, int words); 207static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 208 int offset, int words); 209static int fxp_ifmedia_upd(struct ifnet *ifp); 210static void fxp_ifmedia_sts(struct ifnet *ifp, 211 struct ifmediareq *ifmr); 212static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 213static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 214 struct ifmediareq *ifmr); 215static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 216static void fxp_miibus_writereg(device_t dev, int phy, int reg, 217 int value); 218static void fxp_load_ucode(struct fxp_softc *sc); 219static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 220 int low, int high); 221static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 222static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 223static __inline void fxp_lwcopy(volatile u_int32_t *src, 224 volatile u_int32_t *dst); 225static __inline void fxp_scb_wait(struct fxp_softc *sc); 226static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 227static __inline void fxp_dma_wait(volatile u_int16_t *status, 228 struct fxp_softc *sc); 229 230static device_method_t fxp_methods[] = { 231 /* Device interface */ 232 DEVMETHOD(device_probe, fxp_probe), 233 DEVMETHOD(device_attach, fxp_attach), 234 DEVMETHOD(device_detach, fxp_detach), 235 DEVMETHOD(device_shutdown, fxp_shutdown), 236 DEVMETHOD(device_suspend, fxp_suspend), 237 DEVMETHOD(device_resume, fxp_resume), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 241 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 242 243 { 0, 0 } 244}; 245 246static driver_t fxp_driver = { 247 "fxp", 248 fxp_methods, 249 sizeof(struct fxp_softc), 250}; 251 252static devclass_t fxp_devclass; 253 254DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 255DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 256DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 257 258static int fxp_rnr; 259SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 260 261/* 262 * Inline function to copy a 16-bit aligned 32-bit quantity. 263 */ 264static __inline void 265fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 266{ 267#ifdef __i386__ 268 *dst = *src; 269#else 270 volatile u_int16_t *a = (volatile u_int16_t *)src; 271 volatile u_int16_t *b = (volatile u_int16_t *)dst; 272 273 b[0] = a[0]; 274 b[1] = a[1]; 275#endif 276} 277 278/* 279 * Wait for the previous command to be accepted (but not necessarily 280 * completed). 281 */ 282static __inline void 283fxp_scb_wait(struct fxp_softc *sc) 284{ 285 int i = 10000; 286 287 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 288 DELAY(2); 289 if (i == 0) 290 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 291 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 292 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 293 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 294 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 295} 296 297static __inline void 298fxp_scb_cmd(struct fxp_softc *sc, int cmd) 299{ 300 301 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 302 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 303 fxp_scb_wait(sc); 304 } 305 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 306} 307 308static __inline void 309fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 310{ 311 int i = 10000; 312 313 while (!(*status & FXP_CB_STATUS_C) && --i) 314 DELAY(2); 315 if (i == 0) 316 device_printf(sc->dev, "DMA timeout\n"); 317} 318 319/* 320 * Return identification string if this is device is ours. 321 */ 322static int 323fxp_probe(device_t dev) 324{ 325 u_int16_t devid; 326 struct fxp_ident *ident; 327 328 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 329 devid = pci_get_device(dev); 330 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 331 if (ident->devid == devid) { 332 device_set_desc(dev, ident->name); 333 return (0); 334 } 335 } 336 } 337 return (ENXIO); 338} 339 340static void 341fxp_powerstate_d0(device_t dev) 342{ 343#if __FreeBSD_version >= 430002 344 u_int32_t iobase, membase, irq; 345 346 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 347 /* Save important PCI config data. */ 348 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 349 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 350 irq = pci_read_config(dev, PCIR_INTLINE, 4); 351 352 /* Reset the power state. */ 353 device_printf(dev, "chip is in D%d power mode " 354 "-- setting to D0\n", pci_get_powerstate(dev)); 355 356 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 357 358 /* Restore PCI config data. */ 359 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 360 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 361 pci_write_config(dev, PCIR_INTLINE, irq, 4); 362 } 363#endif 364} 365 366static int 367fxp_attach(device_t dev) 368{ 369 int error = 0; 370 struct fxp_softc *sc = device_get_softc(dev); 371 struct ifnet *ifp; 372 u_int32_t val; 373 u_int16_t data; 374 int i, rid, m1, m2, prefer_iomap; 375 int s; 376 377 bzero(sc, sizeof(*sc)); 378 sc->dev = dev; 379 callout_handle_init(&sc->stat_ch); 380 sysctl_ctx_init(&sc->sysctl_ctx); 381 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 382 MTX_DEF | MTX_RECURSE); 383 384 s = splimp(); 385 386 /* 387 * Enable bus mastering. Enable memory space too, in case 388 * BIOS/Prom forgot about it. 389 */ 390 val = pci_read_config(dev, PCIR_COMMAND, 2); 391 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 392 pci_write_config(dev, PCIR_COMMAND, val, 2); 393 val = pci_read_config(dev, PCIR_COMMAND, 2); 394 395 fxp_powerstate_d0(dev); 396 397 /* 398 * Figure out which we should try first - memory mapping or i/o mapping? 399 * We default to memory mapping. Then we accept an override from the 400 * command line. Then we check to see which one is enabled. 401 */ 402 m1 = PCIM_CMD_MEMEN; 403 m2 = PCIM_CMD_PORTEN; 404 prefer_iomap = 0; 405 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 406 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 407 m1 = PCIM_CMD_PORTEN; 408 m2 = PCIM_CMD_MEMEN; 409 } 410 411 if (val & m1) { 412 sc->rtp = 413 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 414 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 415 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 416 0, ~0, 1, RF_ACTIVE); 417 } 418 if (sc->mem == NULL && (val & m2)) { 419 sc->rtp = 420 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 421 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 422 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 423 0, ~0, 1, RF_ACTIVE); 424 } 425 426 if (!sc->mem) { 427 device_printf(dev, "could not map device registers\n"); 428 error = ENXIO; 429 goto fail; 430 } 431 if (bootverbose) { 432 device_printf(dev, "using %s space register mapping\n", 433 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 434 } 435 436 sc->sc_st = rman_get_bustag(sc->mem); 437 sc->sc_sh = rman_get_bushandle(sc->mem); 438 439 /* 440 * Allocate our interrupt. 441 */ 442 rid = 0; 443 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 444 RF_SHAREABLE | RF_ACTIVE); 445 if (sc->irq == NULL) { 446 device_printf(dev, "could not map interrupt\n"); 447 error = ENXIO; 448 goto fail; 449 } 450 451 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 452 fxp_intr, sc, &sc->ih); 453 if (error) { 454 device_printf(dev, "could not setup irq\n"); 455 goto fail; 456 } 457 458 /* 459 * Reset to a stable state. 460 */ 461 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 462 DELAY(10); 463 464 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 465 M_DEVBUF, M_NOWAIT | M_ZERO); 466 if (sc->cbl_base == NULL) 467 goto failmem; 468 469 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 470 M_NOWAIT | M_ZERO); 471 if (sc->fxp_stats == NULL) 472 goto failmem; 473 474 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 475 if (sc->mcsp == NULL) 476 goto failmem; 477 478 /* 479 * Pre-allocate our receive buffers. 480 */ 481 for (i = 0; i < FXP_NRFABUFS; i++) { 482 if (fxp_add_rfabuf(sc, NULL) != 0) { 483 goto failmem; 484 } 485 } 486 487 /* 488 * Find out how large of an SEEPROM we have. 489 */ 490 fxp_autosize_eeprom(sc); 491 492 /* 493 * Determine whether we must use the 503 serial interface. 494 */ 495 fxp_read_eeprom(sc, &data, 6, 1); 496 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 497 (data & FXP_PHY_SERIAL_ONLY)) 498 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 499 500 /* 501 * Create the sysctl tree 502 */ 503 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 504 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 505 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 506 if (sc->sysctl_tree == NULL) 507 goto fail; 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573#if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579#endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 599 /* enable reception of long frames for VLAN */ 600 sc->flags |= FXP_FLAG_LONG_PKT_EN; 601 } 602 603 /* 604 * Enable use of extended RFDs and TCBs for 82550 605 * and later chips. Note: we need extended TXCB support 606 * too, but that's already enabled by the code above. 607 * Be careful to do this only on the right devices. 608 */ 609 610 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 611 sc->rfa_size = sizeof (struct fxp_rfa); 612 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 613 sc->flags |= FXP_FLAG_EXT_RFA; 614 } else { 615 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 616 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 617 } 618 619 /* 620 * Read MAC address. 621 */ 622 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 623 device_printf(dev, "Ethernet address %6D%s\n", 624 sc->arpcom.ac_enaddr, ":", 625 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 626 if (bootverbose) { 627 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 628 pci_get_vendor(dev), pci_get_device(dev), 629 pci_get_subvendor(dev), pci_get_subdevice(dev), 630 pci_get_revid(dev)); 631 fxp_read_eeprom(sc, &data, 10, 1); 632 device_printf(dev, "Dynamic Standby mode is %s\n", 633 data & 0x02 ? "enabled" : "disabled"); 634 } 635 636 /* 637 * If this is only a 10Mbps device, then there is no MII, and 638 * the PHY will use a serial interface instead. 639 * 640 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 641 * doesn't have a programming interface of any sort. The 642 * media is sensed automatically based on how the link partner 643 * is configured. This is, in essence, manual configuration. 644 */ 645 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 646 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 647 fxp_serial_ifmedia_sts); 648 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 649 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 650 } else { 651 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 652 fxp_ifmedia_sts)) { 653 device_printf(dev, "MII without any PHY!\n"); 654 error = ENXIO; 655 goto fail; 656 } 657 } 658 659 ifp = &sc->arpcom.ac_if; 660 ifp->if_unit = device_get_unit(dev); 661 ifp->if_name = "fxp"; 662 ifp->if_output = ether_output; 663 ifp->if_baudrate = 100000000; 664 ifp->if_init = fxp_init; 665 ifp->if_softc = sc; 666 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 667 ifp->if_ioctl = fxp_ioctl; 668 ifp->if_start = fxp_start; 669 ifp->if_watchdog = fxp_watchdog; 670 671 /* Enable checksum offload for 82550 or better chips */ 672 673 if (sc->flags & FXP_FLAG_EXT_RFA) { 674 ifp->if_hwassist = FXP_CSUM_FEATURES; 675 ifp->if_capabilities = IFCAP_HWCSUM; 676 ifp->if_capenable = ifp->if_capabilities; 677 } 678 679 /* 680 * Attach the interface. 681 */ 682 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 683 684 /* 685 * Tell the upper layer(s) we support long frames. 686 */ 687 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 688 ifp->if_capabilities |= IFCAP_VLAN_MTU; 689 690 /* 691 * Let the system queue as many packets as we have available 692 * TX descriptors. 693 */ 694 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 695 696 splx(s); 697 return (0); 698 699failmem: 700 device_printf(dev, "Failed to malloc memory\n"); 701 error = ENOMEM; 702fail: 703 splx(s); 704 fxp_release(sc); 705 return (error); 706} 707 708/* 709 * release all resources 710 */ 711static void 712fxp_release(struct fxp_softc *sc) 713{ 714 715 bus_generic_detach(sc->dev); 716 if (sc->miibus) 717 device_delete_child(sc->dev, sc->miibus); 718 719 if (sc->cbl_base) 720 free(sc->cbl_base, M_DEVBUF); 721 if (sc->fxp_stats) 722 free(sc->fxp_stats, M_DEVBUF); 723 if (sc->mcsp) 724 free(sc->mcsp, M_DEVBUF); 725 if (sc->rfa_headm) 726 m_freem(sc->rfa_headm); 727 728 if (sc->ih) 729 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 730 if (sc->irq) 731 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 732 if (sc->mem) 733 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 734 735 sysctl_ctx_free(&sc->sysctl_ctx); 736 737 mtx_destroy(&sc->sc_mtx); 738} 739 740/* 741 * Detach interface. 742 */ 743static int 744fxp_detach(device_t dev) 745{ 746 struct fxp_softc *sc = device_get_softc(dev); 747 int s; 748 749 /* disable interrupts */ 750 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 751 752 s = splimp(); 753 754 /* 755 * Stop DMA and drop transmit queue. 756 */ 757 fxp_stop(sc); 758 759 /* 760 * Close down routes etc. 761 */ 762 ether_ifdetach(&sc->arpcom.ac_if); 763 764 /* 765 * Free all media structures. 766 */ 767 ifmedia_removeall(&sc->sc_media); 768 769 splx(s); 770 771 /* Release our allocated resources. */ 772 fxp_release(sc); 773 774 return (0); 775} 776 777/* 778 * Device shutdown routine. Called at system shutdown after sync. The 779 * main purpose of this routine is to shut off receiver DMA so that 780 * kernel memory doesn't get clobbered during warmboot. 781 */ 782static int 783fxp_shutdown(device_t dev) 784{ 785 /* 786 * Make sure that DMA is disabled prior to reboot. Not doing 787 * do could allow DMA to corrupt kernel memory during the 788 * reboot before the driver initializes. 789 */ 790 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 791 return (0); 792} 793 794/* 795 * Device suspend routine. Stop the interface and save some PCI 796 * settings in case the BIOS doesn't restore them properly on 797 * resume. 798 */ 799static int 800fxp_suspend(device_t dev) 801{ 802 struct fxp_softc *sc = device_get_softc(dev); 803 int i, s; 804 805 s = splimp(); 806 807 fxp_stop(sc); 808 809 for (i = 0; i < 5; i++) 810 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 811 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 812 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 813 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 814 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 815 816 sc->suspended = 1; 817 818 splx(s); 819 return (0); 820} 821 822/* 823 * Device resume routine. Restore some PCI settings in case the BIOS 824 * doesn't, re-enable busmastering, and restart the interface if 825 * appropriate. 826 */ 827static int 828fxp_resume(device_t dev) 829{ 830 struct fxp_softc *sc = device_get_softc(dev); 831 struct ifnet *ifp = &sc->sc_if; 832 u_int16_t pci_command; 833 int i, s; 834 835 s = splimp(); 836 837 fxp_powerstate_d0(dev); 838 839 /* better way to do this? */ 840 for (i = 0; i < 5; i++) 841 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 842 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 843 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 844 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 845 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 846 847 /* reenable busmastering */ 848 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 849 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 850 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 851 852 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 853 DELAY(10); 854 855 /* reinitialize interface if necessary */ 856 if (ifp->if_flags & IFF_UP) 857 fxp_init(sc); 858 859 sc->suspended = 0; 860 861 splx(s); 862 return (0); 863} 864 865static void 866fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 867{ 868 u_int16_t reg; 869 int x; 870 871 /* 872 * Shift in data. 873 */ 874 for (x = 1 << (length - 1); x; x >>= 1) { 875 if (data & x) 876 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 877 else 878 reg = FXP_EEPROM_EECS; 879 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 880 DELAY(1); 881 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 882 DELAY(1); 883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 884 DELAY(1); 885 } 886} 887 888/* 889 * Read from the serial EEPROM. Basically, you manually shift in 890 * the read opcode (one bit at a time) and then shift in the address, 891 * and then you shift out the data (all of this one bit at a time). 892 * The word size is 16 bits, so you have to provide the address for 893 * every 16 bits of data. 894 */ 895static u_int16_t 896fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 897{ 898 u_int16_t reg, data; 899 int x; 900 901 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 902 /* 903 * Shift in read opcode. 904 */ 905 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 906 /* 907 * Shift in address. 908 */ 909 data = 0; 910 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 911 if (offset & x) 912 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 913 else 914 reg = FXP_EEPROM_EECS; 915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 916 DELAY(1); 917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 918 DELAY(1); 919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 920 DELAY(1); 921 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 922 data++; 923 if (autosize && reg == 0) { 924 sc->eeprom_size = data; 925 break; 926 } 927 } 928 /* 929 * Shift out data. 930 */ 931 data = 0; 932 reg = FXP_EEPROM_EECS; 933 for (x = 1 << 15; x; x >>= 1) { 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 935 DELAY(1); 936 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 937 data |= x; 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 939 DELAY(1); 940 } 941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 942 DELAY(1); 943 944 return (data); 945} 946 947static void 948fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 949{ 950 int i; 951 952 /* 953 * Erase/write enable. 954 */ 955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 956 fxp_eeprom_shiftin(sc, 0x4, 3); 957 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 959 DELAY(1); 960 /* 961 * Shift in write opcode, address, data. 962 */ 963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 964 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 965 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 966 fxp_eeprom_shiftin(sc, data, 16); 967 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 968 DELAY(1); 969 /* 970 * Wait for EEPROM to finish up. 971 */ 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 973 DELAY(1); 974 for (i = 0; i < 1000; i++) { 975 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 976 break; 977 DELAY(50); 978 } 979 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 980 DELAY(1); 981 /* 982 * Erase/write disable. 983 */ 984 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 985 fxp_eeprom_shiftin(sc, 0x4, 3); 986 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 987 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 988 DELAY(1); 989} 990 991/* 992 * From NetBSD: 993 * 994 * Figure out EEPROM size. 995 * 996 * 559's can have either 64-word or 256-word EEPROMs, the 558 997 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 998 * talks about the existance of 16 to 256 word EEPROMs. 999 * 1000 * The only known sizes are 64 and 256, where the 256 version is used 1001 * by CardBus cards to store CIS information. 1002 * 1003 * The address is shifted in msb-to-lsb, and after the last 1004 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1005 * after which follows the actual data. We try to detect this zero, by 1006 * probing the data-out bit in the EEPROM control register just after 1007 * having shifted in a bit. If the bit is zero, we assume we've 1008 * shifted enough address bits. The data-out should be tri-state, 1009 * before this, which should translate to a logical one. 1010 */ 1011static void 1012fxp_autosize_eeprom(struct fxp_softc *sc) 1013{ 1014 1015 /* guess maximum size of 256 words */ 1016 sc->eeprom_size = 8; 1017 1018 /* autosize */ 1019 (void) fxp_eeprom_getword(sc, 0, 1); 1020} 1021 1022static void 1023fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1024{ 1025 int i; 1026 1027 for (i = 0; i < words; i++) 1028 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1029} 1030 1031static void 1032fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1033{ 1034 int i; 1035 1036 for (i = 0; i < words; i++) 1037 fxp_eeprom_putword(sc, offset + i, data[i]); 1038} 1039 1040/* 1041 * Start packet transmission on the interface. 1042 */ 1043static void 1044fxp_start(struct ifnet *ifp) 1045{ 1046 struct fxp_softc *sc = ifp->if_softc; 1047 struct fxp_cb_tx *txp; 1048 volatile struct fxp_tbd *bdptr; 1049 1050 /* 1051 * See if we need to suspend xmit until the multicast filter 1052 * has been reprogrammed (which can only be done at the head 1053 * of the command chain). 1054 */ 1055 if (sc->need_mcsetup) { 1056 return; 1057 } 1058 1059 txp = NULL; 1060 1061 /* 1062 * We're finished if there is nothing more to add to the list or if 1063 * we're all filled up with buffers to transmit. 1064 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1065 * a NOP command when needed. 1066 */ 1067 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1068 struct mbuf *m, *mb_head; 1069 int segment; 1070 1071 /* 1072 * Grab a packet to transmit. 1073 */ 1074 IF_DEQUEUE(&ifp->if_snd, mb_head); 1075 1076 /* 1077 * Get pointer to next available tx desc. 1078 */ 1079 txp = sc->cbl_last->next; 1080 1081 /* 1082 * If this is an 82550/82551, then we're using extended 1083 * TxCBs _and_ we're using checksum offload. This means 1084 * that the TxCB is really an IPCB. One major difference 1085 * between the two is that with plain extended TxCBs, 1086 * the bottom half of the TxCB contains two entries from 1087 * the TBD array, whereas IPCBs contain just one entry: 1088 * one entry (8 bytes) has been sacrificed for the TCP/IP 1089 * checksum offload control bits. So to make things work 1090 * right, we have to start filling in the TBD array 1091 * starting from a different place depending on whether 1092 * the chip is an 82550/82551 or not. 1093 */ 1094 1095 bdptr = &txp->tbd[0]; 1096 if (sc->flags & FXP_FLAG_EXT_RFA) 1097 bdptr++; 1098 1099 /* 1100 * Deal with TCP/IP checksum offload. Note that 1101 * in order for TCP checksum offload to work, 1102 * the pseudo header checksum must have already 1103 * been computed and stored in the checksum field 1104 * in the TCP header. The stack should have 1105 * already done this for us. 1106 */ 1107 1108 if (mb_head->m_pkthdr.csum_flags) { 1109 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1110 txp->ipcb_ip_activation_high = 1111 FXP_IPCB_HARDWAREPARSING_ENABLE; 1112 txp->ipcb_ip_schedule = 1113 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1114 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1115 txp->ipcb_ip_schedule |= 1116 FXP_IPCB_TCP_PACKET; 1117 } 1118#ifdef FXP_IP_CSUM_WAR 1119 /* 1120 * XXX The 82550 chip appears to have trouble 1121 * dealing with IP header checksums in very small 1122 * datagrams, namely fragments from 1 to 3 bytes 1123 * in size. For example, say you want to transmit 1124 * a UDP packet of 1473 bytes. The packet will be 1125 * fragmented over two IP datagrams, the latter 1126 * containing only one byte of data. The 82550 will 1127 * botch the header checksum on the 1-byte fragment. 1128 * As long as the datagram contains 4 or more bytes 1129 * of data, you're ok. 1130 * 1131 * The following code attempts to work around this 1132 * problem: if the datagram is less than 38 bytes 1133 * in size (14 bytes ether header, 20 bytes IP header, 1134 * plus 4 bytes of data), we punt and compute the IP 1135 * header checksum by hand. This workaround doesn't 1136 * work very well, however, since it can be fooled 1137 * by things like VLAN tags and IP options that make 1138 * the header sizes/offsets vary. 1139 */ 1140 1141 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1142 if (mb_head->m_pkthdr.len < 38) { 1143 struct ip *ip; 1144 mb_head->m_data += ETHER_HDR_LEN; 1145 ip = mtod(mb_head, struct ip *); 1146 ip->ip_sum = in_cksum(mb_head, 1147 ip->ip_hl << 2); 1148 mb_head->m_data -= ETHER_HDR_LEN; 1149 } else { 1150 txp->ipcb_ip_activation_high = 1151 FXP_IPCB_HARDWAREPARSING_ENABLE; 1152 txp->ipcb_ip_schedule |= 1153 FXP_IPCB_IP_CHECKSUM_ENABLE; 1154 } 1155 } 1156#endif 1157 } 1158 1159 /* 1160 * Go through each of the mbufs in the chain and initialize 1161 * the transmit buffer descriptors with the physical address 1162 * and size of the mbuf. 1163 */ 1164tbdinit: 1165 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1166 if (m->m_len != 0) { 1167 if (segment == (FXP_NTXSEG - 1)) 1168 break; 1169 bdptr[segment].tb_addr = 1170 vtophys(mtod(m, vm_offset_t)); 1171 bdptr[segment].tb_size = m->m_len; 1172 segment++; 1173 } 1174 } 1175 if (m != NULL) { 1176 struct mbuf *mn; 1177 1178 /* 1179 * We ran out of segments. We have to recopy this 1180 * mbuf chain first. Bail out if we can't get the 1181 * new buffers. 1182 */ 1183 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1184 if (mn == NULL) { 1185 m_freem(mb_head); 1186 break; 1187 } 1188 if (mb_head->m_pkthdr.len > MHLEN) { 1189 MCLGET(mn, M_DONTWAIT); 1190 if ((mn->m_flags & M_EXT) == 0) { 1191 m_freem(mn); 1192 m_freem(mb_head); 1193 break; 1194 } 1195 } 1196 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1197 mtod(mn, caddr_t)); 1198 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1199 m_freem(mb_head); 1200 mb_head = mn; 1201 goto tbdinit; 1202 } 1203 1204 txp->byte_count = 0; 1205 txp->tbd_number = segment; 1206 txp->mb_head = mb_head; 1207 txp->cb_status = 0; 1208 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1209 txp->cb_command = 1210 sc->tx_cmd | FXP_CB_COMMAND_SF | 1211 FXP_CB_COMMAND_S; 1212 } else { 1213 txp->cb_command = 1214 sc->tx_cmd | FXP_CB_COMMAND_SF | 1215 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1216 /* 1217 * Set a 5 second timer just in case we don't hear 1218 * from the card again. 1219 */ 1220 ifp->if_timer = 5; 1221 } 1222 txp->tx_threshold = tx_threshold; 1223 1224 /* 1225 * Advance the end of list forward. 1226 */ 1227 1228#ifdef __alpha__ 1229 /* 1230 * On platforms which can't access memory in 16-bit 1231 * granularities, we must prevent the card from DMA'ing 1232 * up the status while we update the command field. 1233 * This could cause us to overwrite the completion status. 1234 */ 1235 atomic_clear_short(&sc->cbl_last->cb_command, 1236 FXP_CB_COMMAND_S); 1237#else 1238 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1239#endif /*__alpha__*/ 1240 sc->cbl_last = txp; 1241 1242 /* 1243 * Advance the beginning of the list forward if there are 1244 * no other packets queued (when nothing is queued, cbl_first 1245 * sits on the last TxCB that was sent out). 1246 */ 1247 if (sc->tx_queued == 0) 1248 sc->cbl_first = txp; 1249 1250 sc->tx_queued++; 1251 1252 /* 1253 * Pass packet to bpf if there is a listener. 1254 */ 1255 BPF_MTAP(ifp, mb_head); 1256 } 1257 1258 /* 1259 * We're finished. If we added to the list, issue a RESUME to get DMA 1260 * going again if suspended. 1261 */ 1262 if (txp != NULL) { 1263 fxp_scb_wait(sc); 1264 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1265 } 1266} 1267 1268static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1269 1270#ifdef DEVICE_POLLING 1271static poll_handler_t fxp_poll; 1272 1273static void 1274fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1275{ 1276 struct fxp_softc *sc = ifp->if_softc; 1277 u_int8_t statack; 1278 1279 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1280 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1281 return; 1282 } 1283 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1284 FXP_SCB_STATACK_FR; 1285 if (cmd == POLL_AND_CHECK_STATUS) { 1286 u_int8_t tmp; 1287 1288 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1289 if (tmp == 0xff || tmp == 0) 1290 return; /* nothing to do */ 1291 tmp &= ~statack; 1292 /* ack what we can */ 1293 if (tmp != 0) 1294 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1295 statack |= tmp; 1296 } 1297 fxp_intr_body(sc, statack, count); 1298} 1299#endif /* DEVICE_POLLING */ 1300 1301/* 1302 * Process interface interrupts. 1303 */ 1304static void 1305fxp_intr(void *xsc) 1306{ 1307 struct fxp_softc *sc = xsc; 1308 u_int8_t statack; 1309 1310#ifdef DEVICE_POLLING 1311 struct ifnet *ifp = &sc->sc_if; 1312 1313 if (ifp->if_flags & IFF_POLLING) 1314 return; 1315 if (ether_poll_register(fxp_poll, ifp)) { 1316 /* disable interrupts */ 1317 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1318 fxp_poll(ifp, 0, 1); 1319 return; 1320 } 1321#endif 1322 1323 if (sc->suspended) { 1324 return; 1325 } 1326 1327 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1328 /* 1329 * It should not be possible to have all bits set; the 1330 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1331 * all bits are set, this may indicate that the card has 1332 * been physically ejected, so ignore it. 1333 */ 1334 if (statack == 0xff) 1335 return; 1336 1337 /* 1338 * First ACK all the interrupts in this pass. 1339 */ 1340 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1341 fxp_intr_body(sc, statack, -1); 1342 } 1343} 1344 1345static void 1346fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1347{ 1348 struct ifnet *ifp = &sc->sc_if; 1349 struct mbuf *m; 1350 struct fxp_rfa *rfa; 1351 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1352 1353 if (rnr) 1354 fxp_rnr++; 1355#ifdef DEVICE_POLLING 1356 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1357 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1358 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1359 rnr = 1; 1360 } 1361#endif 1362 1363 /* 1364 * Free any finished transmit mbuf chains. 1365 * 1366 * Handle the CNA event likt a CXTNO event. It used to 1367 * be that this event (control unit not ready) was not 1368 * encountered, but it is now with the SMPng modifications. 1369 * The exact sequence of events that occur when the interface 1370 * is brought up are different now, and if this event 1371 * goes unhandled, the configuration/rxfilter setup sequence 1372 * can stall for several seconds. The result is that no 1373 * packets go out onto the wire for about 5 to 10 seconds 1374 * after the interface is ifconfig'ed for the first time. 1375 */ 1376 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1377 struct fxp_cb_tx *txp; 1378 1379 for (txp = sc->cbl_first; sc->tx_queued && 1380 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1381 txp = txp->next) { 1382 if (txp->mb_head != NULL) { 1383 m_freem(txp->mb_head); 1384 txp->mb_head = NULL; 1385 /* clear this to reset csum offload bits */ 1386 txp->tbd[0].tb_addr = 0; 1387 } 1388 sc->tx_queued--; 1389 } 1390 sc->cbl_first = txp; 1391 ifp->if_timer = 0; 1392 if (sc->tx_queued == 0) { 1393 if (sc->need_mcsetup) 1394 fxp_mc_setup(sc); 1395 } 1396 /* 1397 * Try to start more packets transmitting. 1398 */ 1399 if (ifp->if_snd.ifq_head != NULL) 1400 fxp_start(ifp); 1401 } 1402 1403 /* 1404 * Just return if nothing happened on the receive side. 1405 */ 1406 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1407 return; 1408 1409 /* 1410 * Process receiver interrupts. If a no-resource (RNR) 1411 * condition exists, get whatever packets we can and 1412 * re-start the receiver. 1413 * 1414 * When using polling, we do not process the list to completion, 1415 * so when we get an RNR interrupt we must defer the restart 1416 * until we hit the last buffer with the C bit set. 1417 * If we run out of cycles and rfa_headm has the C bit set, 1418 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1419 * that the info will be used in the subsequent polling cycle. 1420 */ 1421 for (;;) { 1422 m = sc->rfa_headm; 1423 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1424 RFA_ALIGNMENT_FUDGE); 1425 1426#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1427 if (count >= 0 && count-- == 0) { 1428 if (rnr) { 1429 /* Defer RNR processing until the next time. */ 1430 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1431 rnr = 0; 1432 } 1433 break; 1434 } 1435#endif /* DEVICE_POLLING */ 1436 1437 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1438 break; 1439 1440 /* 1441 * Remove first packet from the chain. 1442 */ 1443 sc->rfa_headm = m->m_next; 1444 m->m_next = NULL; 1445 1446 /* 1447 * Add a new buffer to the receive chain. 1448 * If this fails, the old buffer is recycled 1449 * instead. 1450 */ 1451 if (fxp_add_rfabuf(sc, m) == 0) { 1452 int total_len; 1453 1454 /* 1455 * Fetch packet length (the top 2 bits of 1456 * actual_size are flags set by the controller 1457 * upon completion), and drop the packet in case 1458 * of bogus length or CRC errors. 1459 */ 1460 total_len = rfa->actual_size & 0x3fff; 1461 if (total_len < sizeof(struct ether_header) || 1462 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1463 sizeof(struct fxp_rfa) || 1464 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1465 m_freem(m); 1466 continue; 1467 } 1468 1469 /* Do IP checksum checking. */ 1470 if (rfa->rfa_status & FXP_RFA_STATUS_PARSE) { 1471 if (rfa->rfax_csum_sts & 1472 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1473 m->m_pkthdr.csum_flags |= 1474 CSUM_IP_CHECKED; 1475 if (rfa->rfax_csum_sts & 1476 FXP_RFDX_CS_IP_CSUM_VALID) 1477 m->m_pkthdr.csum_flags |= 1478 CSUM_IP_VALID; 1479 if ((rfa->rfax_csum_sts & 1480 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1481 (rfa->rfax_csum_sts & 1482 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1483 m->m_pkthdr.csum_flags |= 1484 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1485 m->m_pkthdr.csum_data = 0xffff; 1486 } 1487 } 1488 1489 m->m_pkthdr.len = m->m_len = total_len; 1490 m->m_pkthdr.rcvif = ifp; 1491 1492 (*ifp->if_input)(ifp, m); 1493 } 1494 } 1495 if (rnr) { 1496 fxp_scb_wait(sc); 1497 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1498 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1499 RFA_ALIGNMENT_FUDGE); 1500 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1501 } 1502} 1503 1504/* 1505 * Update packet in/out/collision statistics. The i82557 doesn't 1506 * allow you to access these counters without doing a fairly 1507 * expensive DMA to get _all_ of the statistics it maintains, so 1508 * we do this operation here only once per second. The statistics 1509 * counters in the kernel are updated from the previous dump-stats 1510 * DMA and then a new dump-stats DMA is started. The on-chip 1511 * counters are zeroed when the DMA completes. If we can't start 1512 * the DMA immediately, we don't wait - we just prepare to read 1513 * them again next time. 1514 */ 1515static void 1516fxp_tick(void *xsc) 1517{ 1518 struct fxp_softc *sc = xsc; 1519 struct ifnet *ifp = &sc->sc_if; 1520 struct fxp_stats *sp = sc->fxp_stats; 1521 struct fxp_cb_tx *txp; 1522 int s; 1523 1524 ifp->if_opackets += sp->tx_good; 1525 ifp->if_collisions += sp->tx_total_collisions; 1526 if (sp->rx_good) { 1527 ifp->if_ipackets += sp->rx_good; 1528 sc->rx_idle_secs = 0; 1529 } else { 1530 /* 1531 * Receiver's been idle for another second. 1532 */ 1533 sc->rx_idle_secs++; 1534 } 1535 ifp->if_ierrors += 1536 sp->rx_crc_errors + 1537 sp->rx_alignment_errors + 1538 sp->rx_rnr_errors + 1539 sp->rx_overrun_errors; 1540 /* 1541 * If any transmit underruns occured, bump up the transmit 1542 * threshold by another 512 bytes (64 * 8). 1543 */ 1544 if (sp->tx_underruns) { 1545 ifp->if_oerrors += sp->tx_underruns; 1546 if (tx_threshold < 192) 1547 tx_threshold += 64; 1548 } 1549 s = splimp(); 1550 /* 1551 * Release any xmit buffers that have completed DMA. This isn't 1552 * strictly necessary to do here, but it's advantagous for mbufs 1553 * with external storage to be released in a timely manner rather 1554 * than being defered for a potentially long time. This limits 1555 * the delay to a maximum of one second. 1556 */ 1557 for (txp = sc->cbl_first; sc->tx_queued && 1558 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1559 txp = txp->next) { 1560 if (txp->mb_head != NULL) { 1561 m_freem(txp->mb_head); 1562 txp->mb_head = NULL; 1563 /* clear this to reset csum offload bits */ 1564 txp->tbd[0].tb_addr = 0; 1565 } 1566 sc->tx_queued--; 1567 } 1568 sc->cbl_first = txp; 1569 /* 1570 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1571 * then assume the receiver has locked up and attempt to clear 1572 * the condition by reprogramming the multicast filter. This is 1573 * a work-around for a bug in the 82557 where the receiver locks 1574 * up if it gets certain types of garbage in the syncronization 1575 * bits prior to the packet header. This bug is supposed to only 1576 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1577 * mode as well (perhaps due to a 10/100 speed transition). 1578 */ 1579 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1580 sc->rx_idle_secs = 0; 1581 fxp_mc_setup(sc); 1582 } 1583 /* 1584 * If there is no pending command, start another stats 1585 * dump. Otherwise punt for now. 1586 */ 1587 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1588 /* 1589 * Start another stats dump. 1590 */ 1591 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1592 } else { 1593 /* 1594 * A previous command is still waiting to be accepted. 1595 * Just zero our copy of the stats and wait for the 1596 * next timer event to update them. 1597 */ 1598 sp->tx_good = 0; 1599 sp->tx_underruns = 0; 1600 sp->tx_total_collisions = 0; 1601 1602 sp->rx_good = 0; 1603 sp->rx_crc_errors = 0; 1604 sp->rx_alignment_errors = 0; 1605 sp->rx_rnr_errors = 0; 1606 sp->rx_overrun_errors = 0; 1607 } 1608 if (sc->miibus != NULL) 1609 mii_tick(device_get_softc(sc->miibus)); 1610 splx(s); 1611 /* 1612 * Schedule another timeout one second from now. 1613 */ 1614 sc->stat_ch = timeout(fxp_tick, sc, hz); 1615} 1616 1617/* 1618 * Stop the interface. Cancels the statistics updater and resets 1619 * the interface. 1620 */ 1621static void 1622fxp_stop(struct fxp_softc *sc) 1623{ 1624 struct ifnet *ifp = &sc->sc_if; 1625 struct fxp_cb_tx *txp; 1626 int i; 1627 1628 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1629 ifp->if_timer = 0; 1630 1631#ifdef DEVICE_POLLING 1632 ether_poll_deregister(ifp); 1633#endif 1634 /* 1635 * Cancel stats updater. 1636 */ 1637 untimeout(fxp_tick, sc, sc->stat_ch); 1638 1639 /* 1640 * Issue software reset, which also unloads the microcode. 1641 */ 1642 sc->flags &= ~FXP_FLAG_UCODE; 1643 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1644 DELAY(50); 1645 1646 /* 1647 * Release any xmit buffers. 1648 */ 1649 txp = sc->cbl_base; 1650 if (txp != NULL) { 1651 for (i = 0; i < FXP_NTXCB; i++) { 1652 if (txp[i].mb_head != NULL) { 1653 m_freem(txp[i].mb_head); 1654 txp[i].mb_head = NULL; 1655 /* clear this to reset csum offload bits */ 1656 txp[i].tbd[0].tb_addr = 0; 1657 } 1658 } 1659 } 1660 sc->tx_queued = 0; 1661 1662 /* 1663 * Free all the receive buffers then reallocate/reinitialize 1664 */ 1665 if (sc->rfa_headm != NULL) 1666 m_freem(sc->rfa_headm); 1667 sc->rfa_headm = NULL; 1668 sc->rfa_tailm = NULL; 1669 for (i = 0; i < FXP_NRFABUFS; i++) { 1670 if (fxp_add_rfabuf(sc, NULL) != 0) { 1671 /* 1672 * This "can't happen" - we're at splimp() 1673 * and we just freed all the buffers we need 1674 * above. 1675 */ 1676 panic("fxp_stop: no buffers!"); 1677 } 1678 } 1679} 1680 1681/* 1682 * Watchdog/transmission transmit timeout handler. Called when a 1683 * transmission is started on the interface, but no interrupt is 1684 * received before the timeout. This usually indicates that the 1685 * card has wedged for some reason. 1686 */ 1687static void 1688fxp_watchdog(struct ifnet *ifp) 1689{ 1690 struct fxp_softc *sc = ifp->if_softc; 1691 1692 device_printf(sc->dev, "device timeout\n"); 1693 ifp->if_oerrors++; 1694 1695 fxp_init(sc); 1696} 1697 1698static void 1699fxp_init(void *xsc) 1700{ 1701 struct fxp_softc *sc = xsc; 1702 struct ifnet *ifp = &sc->sc_if; 1703 struct fxp_cb_config *cbp; 1704 struct fxp_cb_ias *cb_ias; 1705 struct fxp_cb_tx *txp; 1706 struct fxp_cb_mcs *mcsp; 1707 int i, prm, s; 1708 1709 s = splimp(); 1710 /* 1711 * Cancel any pending I/O 1712 */ 1713 fxp_stop(sc); 1714 1715 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1716 1717 /* 1718 * Initialize base of CBL and RFA memory. Loading with zero 1719 * sets it up for regular linear addressing. 1720 */ 1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1723 1724 fxp_scb_wait(sc); 1725 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1726 1727 /* 1728 * Initialize base of dump-stats buffer. 1729 */ 1730 fxp_scb_wait(sc); 1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1732 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1733 1734 /* 1735 * Attempt to load microcode if requested. 1736 */ 1737 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1738 fxp_load_ucode(sc); 1739 1740 /* 1741 * Initialize the multicast address list. 1742 */ 1743 if (fxp_mc_addrs(sc)) { 1744 mcsp = sc->mcsp; 1745 mcsp->cb_status = 0; 1746 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1747 mcsp->link_addr = -1; 1748 /* 1749 * Start the multicast setup command. 1750 */ 1751 fxp_scb_wait(sc); 1752 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1753 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1754 /* ...and wait for it to complete. */ 1755 fxp_dma_wait(&mcsp->cb_status, sc); 1756 } 1757 1758 /* 1759 * We temporarily use memory that contains the TxCB list to 1760 * construct the config CB. The TxCB list memory is rebuilt 1761 * later. 1762 */ 1763 cbp = (struct fxp_cb_config *) sc->cbl_base; 1764 1765 /* 1766 * This bcopy is kind of disgusting, but there are a bunch of must be 1767 * zero and must be one bits in this structure and this is the easiest 1768 * way to initialize them all to proper values. 1769 */ 1770 bcopy(fxp_cb_config_template, 1771 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1772 sizeof(fxp_cb_config_template)); 1773 1774 cbp->cb_status = 0; 1775 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1776 cbp->link_addr = -1; /* (no) next command */ 1777 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1778 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1779 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1780 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1781 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1782 cbp->type_enable = 0; /* actually reserved */ 1783 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1784 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1785 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1786 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1787 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1788 cbp->late_scb = 0; /* (don't) defer SCB update */ 1789 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1790 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1791 cbp->ci_int = 1; /* interrupt on CU idle */ 1792 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1793 cbp->ext_stats_dis = 1; /* disable extended counters */ 1794 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1795 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1796 cbp->disc_short_rx = !prm; /* discard short packets */ 1797 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1798 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1799 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1800 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1801 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1802 cbp->csma_dis = 0; /* (don't) disable link */ 1803 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1804 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1805 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1806 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1807 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1808 cbp->nsai = 1; /* (don't) disable source addr insert */ 1809 cbp->preamble_length = 2; /* (7 byte) preamble */ 1810 cbp->loopback = 0; /* (don't) loopback */ 1811 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1812 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1813 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1814 cbp->promiscuous = prm; /* promiscuous mode */ 1815 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1816 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1817 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1818 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1819 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1820 1821 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1822 cbp->padding = 1; /* (do) pad short tx packets */ 1823 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1824 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1825 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1826 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1827 /* must set wake_en in PMCSR also */ 1828 cbp->force_fdx = 0; /* (don't) force full duplex */ 1829 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1830 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1831 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1832 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1833 1834 if (sc->revision == FXP_REV_82557) { 1835 /* 1836 * The 82557 has no hardware flow control, the values 1837 * below are the defaults for the chip. 1838 */ 1839 cbp->fc_delay_lsb = 0; 1840 cbp->fc_delay_msb = 0x40; 1841 cbp->pri_fc_thresh = 3; 1842 cbp->tx_fc_dis = 0; 1843 cbp->rx_fc_restop = 0; 1844 cbp->rx_fc_restart = 0; 1845 cbp->fc_filter = 0; 1846 cbp->pri_fc_loc = 1; 1847 } else { 1848 cbp->fc_delay_lsb = 0x1f; 1849 cbp->fc_delay_msb = 0x01; 1850 cbp->pri_fc_thresh = 3; 1851 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1852 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1853 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1854 cbp->fc_filter = !prm; /* drop FC frames to host */ 1855 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1856 } 1857 1858 /* 1859 * Start the config command/DMA. 1860 */ 1861 fxp_scb_wait(sc); 1862 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1863 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1864 /* ...and wait for it to complete. */ 1865 fxp_dma_wait(&cbp->cb_status, sc); 1866 1867 /* 1868 * Now initialize the station address. Temporarily use the TxCB 1869 * memory area like we did above for the config CB. 1870 */ 1871 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1872 cb_ias->cb_status = 0; 1873 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1874 cb_ias->link_addr = -1; 1875 bcopy(sc->arpcom.ac_enaddr, 1876 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1877 sizeof(sc->arpcom.ac_enaddr)); 1878 1879 /* 1880 * Start the IAS (Individual Address Setup) command/DMA. 1881 */ 1882 fxp_scb_wait(sc); 1883 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1884 /* ...and wait for it to complete. */ 1885 fxp_dma_wait(&cb_ias->cb_status, sc); 1886 1887 /* 1888 * Initialize transmit control block (TxCB) list. 1889 */ 1890 1891 txp = sc->cbl_base; 1892 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1893 for (i = 0; i < FXP_NTXCB; i++) { 1894 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1895 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1896 txp[i].link_addr = 1897 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1898 if (sc->flags & FXP_FLAG_EXT_TXCB) 1899 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1900 else 1901 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1902 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1903 } 1904 /* 1905 * Set the suspend flag on the first TxCB and start the control 1906 * unit. It will execute the NOP and then suspend. 1907 */ 1908 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1909 sc->cbl_first = sc->cbl_last = txp; 1910 sc->tx_queued = 1; 1911 1912 fxp_scb_wait(sc); 1913 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1914 1915 /* 1916 * Initialize receiver buffer area - RFA. 1917 */ 1918 fxp_scb_wait(sc); 1919 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1920 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1921 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1922 1923 /* 1924 * Set current media. 1925 */ 1926 if (sc->miibus != NULL) 1927 mii_mediachg(device_get_softc(sc->miibus)); 1928 1929 ifp->if_flags |= IFF_RUNNING; 1930 ifp->if_flags &= ~IFF_OACTIVE; 1931 1932 /* 1933 * Enable interrupts. 1934 */ 1935#ifdef DEVICE_POLLING 1936 /* 1937 * ... but only do that if we are not polling. And because (presumably) 1938 * the default is interrupts on, we need to disable them explicitly! 1939 */ 1940 if ( ifp->if_flags & IFF_POLLING ) 1941 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1942 else 1943#endif /* DEVICE_POLLING */ 1944 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1945 splx(s); 1946 1947 /* 1948 * Start stats updater. 1949 */ 1950 sc->stat_ch = timeout(fxp_tick, sc, hz); 1951} 1952 1953static int 1954fxp_serial_ifmedia_upd(struct ifnet *ifp) 1955{ 1956 1957 return (0); 1958} 1959 1960static void 1961fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1962{ 1963 1964 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1965} 1966 1967/* 1968 * Change media according to request. 1969 */ 1970static int 1971fxp_ifmedia_upd(struct ifnet *ifp) 1972{ 1973 struct fxp_softc *sc = ifp->if_softc; 1974 struct mii_data *mii; 1975 1976 mii = device_get_softc(sc->miibus); 1977 mii_mediachg(mii); 1978 return (0); 1979} 1980 1981/* 1982 * Notify the world which media we're using. 1983 */ 1984static void 1985fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1986{ 1987 struct fxp_softc *sc = ifp->if_softc; 1988 struct mii_data *mii; 1989 1990 mii = device_get_softc(sc->miibus); 1991 mii_pollstat(mii); 1992 ifmr->ifm_active = mii->mii_media_active; 1993 ifmr->ifm_status = mii->mii_media_status; 1994 1995 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1996 sc->cu_resume_bug = 1; 1997 else 1998 sc->cu_resume_bug = 0; 1999} 2000 2001/* 2002 * Add a buffer to the end of the RFA buffer list. 2003 * Return 0 if successful, 1 for failure. A failure results in 2004 * adding the 'oldm' (if non-NULL) on to the end of the list - 2005 * tossing out its old contents and recycling it. 2006 * The RFA struct is stuck at the beginning of mbuf cluster and the 2007 * data pointer is fixed up to point just past it. 2008 */ 2009static int 2010fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 2011{ 2012 u_int32_t v; 2013 struct mbuf *m; 2014 struct fxp_rfa *rfa, *p_rfa; 2015 2016 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2017 if (m == NULL) { /* try to recycle the old mbuf instead */ 2018 if (oldm == NULL) 2019 return 1; 2020 m = oldm; 2021 m->m_data = m->m_ext.ext_buf; 2022 } 2023 2024 /* 2025 * Move the data pointer up so that the incoming data packet 2026 * will be 32-bit aligned. 2027 */ 2028 m->m_data += RFA_ALIGNMENT_FUDGE; 2029 2030 /* 2031 * Get a pointer to the base of the mbuf cluster and move 2032 * data start past it. 2033 */ 2034 rfa = mtod(m, struct fxp_rfa *); 2035 m->m_data += sc->rfa_size; 2036 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - 2037 RFA_ALIGNMENT_FUDGE); 2038 2039 /* 2040 * Initialize the rest of the RFA. Note that since the RFA 2041 * is misaligned, we cannot store values directly. Instead, 2042 * we use an optimized, inline copy. 2043 */ 2044 2045 rfa->rfa_status = 0; 2046 rfa->rfa_control = FXP_RFA_CONTROL_EL; 2047 rfa->actual_size = 0; 2048 2049 v = -1; 2050 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 2051 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 2052 2053 /* 2054 * If there are other buffers already on the list, attach this 2055 * one to the end by fixing up the tail to point to this one. 2056 */ 2057 if (sc->rfa_headm != NULL) { 2058 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 2059 RFA_ALIGNMENT_FUDGE); 2060 sc->rfa_tailm->m_next = m; 2061 v = vtophys(rfa); 2062 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 2063 p_rfa->rfa_control = 0; 2064 } else { 2065 sc->rfa_headm = m; 2066 } 2067 sc->rfa_tailm = m; 2068 2069 return (m == oldm); 2070} 2071 2072static volatile int 2073fxp_miibus_readreg(device_t dev, int phy, int reg) 2074{ 2075 struct fxp_softc *sc = device_get_softc(dev); 2076 int count = 10000; 2077 int value; 2078 2079 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2080 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2081 2082 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2083 && count--) 2084 DELAY(10); 2085 2086 if (count <= 0) 2087 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2088 2089 return (value & 0xffff); 2090} 2091 2092static void 2093fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2094{ 2095 struct fxp_softc *sc = device_get_softc(dev); 2096 int count = 10000; 2097 2098 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2099 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2100 (value & 0xffff)); 2101 2102 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2103 count--) 2104 DELAY(10); 2105 2106 if (count <= 0) 2107 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2108} 2109 2110static int 2111fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2112{ 2113 struct fxp_softc *sc = ifp->if_softc; 2114 struct ifreq *ifr = (struct ifreq *)data; 2115 struct mii_data *mii; 2116 int s, error = 0; 2117 2118 s = splimp(); 2119 2120 switch (command) { 2121 case SIOCSIFFLAGS: 2122 if (ifp->if_flags & IFF_ALLMULTI) 2123 sc->flags |= FXP_FLAG_ALL_MCAST; 2124 else 2125 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2126 2127 /* 2128 * If interface is marked up and not running, then start it. 2129 * If it is marked down and running, stop it. 2130 * XXX If it's up then re-initialize it. This is so flags 2131 * such as IFF_PROMISC are handled. 2132 */ 2133 if (ifp->if_flags & IFF_UP) { 2134 fxp_init(sc); 2135 } else { 2136 if (ifp->if_flags & IFF_RUNNING) 2137 fxp_stop(sc); 2138 } 2139 break; 2140 2141 case SIOCADDMULTI: 2142 case SIOCDELMULTI: 2143 if (ifp->if_flags & IFF_ALLMULTI) 2144 sc->flags |= FXP_FLAG_ALL_MCAST; 2145 else 2146 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2147 /* 2148 * Multicast list has changed; set the hardware filter 2149 * accordingly. 2150 */ 2151 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2152 fxp_mc_setup(sc); 2153 /* 2154 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2155 * again rather than else {}. 2156 */ 2157 if (sc->flags & FXP_FLAG_ALL_MCAST) 2158 fxp_init(sc); 2159 error = 0; 2160 break; 2161 2162 case SIOCSIFMEDIA: 2163 case SIOCGIFMEDIA: 2164 if (sc->miibus != NULL) { 2165 mii = device_get_softc(sc->miibus); 2166 error = ifmedia_ioctl(ifp, ifr, 2167 &mii->mii_media, command); 2168 } else { 2169 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2170 } 2171 break; 2172 2173 default: 2174 error = ether_ioctl(ifp, command, data); 2175 } 2176 splx(s); 2177 return (error); 2178} 2179 2180/* 2181 * Fill in the multicast address list and return number of entries. 2182 */ 2183static int 2184fxp_mc_addrs(struct fxp_softc *sc) 2185{ 2186 struct fxp_cb_mcs *mcsp = sc->mcsp; 2187 struct ifnet *ifp = &sc->sc_if; 2188 struct ifmultiaddr *ifma; 2189 int nmcasts; 2190 2191 nmcasts = 0; 2192 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2193#if __FreeBSD_version < 500000 2194 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2195#else 2196 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2197#endif 2198 if (ifma->ifma_addr->sa_family != AF_LINK) 2199 continue; 2200 if (nmcasts >= MAXMCADDR) { 2201 sc->flags |= FXP_FLAG_ALL_MCAST; 2202 nmcasts = 0; 2203 break; 2204 } 2205 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2206 (void *)(uintptr_t)(volatile void *) 2207 &sc->mcsp->mc_addr[nmcasts][0], 6); 2208 nmcasts++; 2209 } 2210 } 2211 mcsp->mc_cnt = nmcasts * 6; 2212 return (nmcasts); 2213} 2214 2215/* 2216 * Program the multicast filter. 2217 * 2218 * We have an artificial restriction that the multicast setup command 2219 * must be the first command in the chain, so we take steps to ensure 2220 * this. By requiring this, it allows us to keep up the performance of 2221 * the pre-initialized command ring (esp. link pointers) by not actually 2222 * inserting the mcsetup command in the ring - i.e. its link pointer 2223 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2224 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2225 * lead into the regular TxCB ring when it completes. 2226 * 2227 * This function must be called at splimp. 2228 */ 2229static void 2230fxp_mc_setup(struct fxp_softc *sc) 2231{ 2232 struct fxp_cb_mcs *mcsp = sc->mcsp; 2233 struct ifnet *ifp = &sc->sc_if; 2234 int count; 2235 2236 /* 2237 * If there are queued commands, we must wait until they are all 2238 * completed. If we are already waiting, then add a NOP command 2239 * with interrupt option so that we're notified when all commands 2240 * have been completed - fxp_start() ensures that no additional 2241 * TX commands will be added when need_mcsetup is true. 2242 */ 2243 if (sc->tx_queued) { 2244 struct fxp_cb_tx *txp; 2245 2246 /* 2247 * need_mcsetup will be true if we are already waiting for the 2248 * NOP command to be completed (see below). In this case, bail. 2249 */ 2250 if (sc->need_mcsetup) 2251 return; 2252 sc->need_mcsetup = 1; 2253 2254 /* 2255 * Add a NOP command with interrupt so that we are notified 2256 * when all TX commands have been processed. 2257 */ 2258 txp = sc->cbl_last->next; 2259 txp->mb_head = NULL; 2260 txp->cb_status = 0; 2261 txp->cb_command = FXP_CB_COMMAND_NOP | 2262 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2263 /* 2264 * Advance the end of list forward. 2265 */ 2266 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2267 sc->cbl_last = txp; 2268 sc->tx_queued++; 2269 /* 2270 * Issue a resume in case the CU has just suspended. 2271 */ 2272 fxp_scb_wait(sc); 2273 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2274 /* 2275 * Set a 5 second timer just in case we don't hear from the 2276 * card again. 2277 */ 2278 ifp->if_timer = 5; 2279 2280 return; 2281 } 2282 sc->need_mcsetup = 0; 2283 2284 /* 2285 * Initialize multicast setup descriptor. 2286 */ 2287 mcsp->next = sc->cbl_base; 2288 mcsp->mb_head = NULL; 2289 mcsp->cb_status = 0; 2290 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2291 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2292 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2293 (void) fxp_mc_addrs(sc); 2294 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2295 sc->tx_queued = 1; 2296 2297 /* 2298 * Wait until command unit is not active. This should never 2299 * be the case when nothing is queued, but make sure anyway. 2300 */ 2301 count = 100; 2302 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2303 FXP_SCB_CUS_ACTIVE && --count) 2304 DELAY(10); 2305 if (count == 0) { 2306 device_printf(sc->dev, "command queue timeout\n"); 2307 return; 2308 } 2309 2310 /* 2311 * Start the multicast setup command. 2312 */ 2313 fxp_scb_wait(sc); 2314 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2315 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2316 2317 ifp->if_timer = 2; 2318 return; 2319} 2320 2321static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2322static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2323static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2324static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2325static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2326static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2327 2328#define UCODE(x) x, sizeof(x) 2329 2330struct ucode { 2331 u_int32_t revision; 2332 u_int32_t *ucode; 2333 int length; 2334 u_short int_delay_offset; 2335 u_short bundle_max_offset; 2336} ucode_table[] = { 2337 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2338 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2339 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2340 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2341 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2342 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2343 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2344 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2345 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2346 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2347 { 0, NULL, 0, 0, 0 } 2348}; 2349 2350static void 2351fxp_load_ucode(struct fxp_softc *sc) 2352{ 2353 struct ucode *uc; 2354 struct fxp_cb_ucode *cbp; 2355 2356 for (uc = ucode_table; uc->ucode != NULL; uc++) 2357 if (sc->revision == uc->revision) 2358 break; 2359 if (uc->ucode == NULL) 2360 return; 2361 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2362 cbp->cb_status = 0; 2363 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2364 cbp->link_addr = -1; /* (no) next command */ 2365 memcpy(cbp->ucode, uc->ucode, uc->length); 2366 if (uc->int_delay_offset) 2367 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2368 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2369 if (uc->bundle_max_offset) 2370 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2371 sc->tunable_bundle_max; 2372 /* 2373 * Download the ucode to the chip. 2374 */ 2375 fxp_scb_wait(sc); 2376 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2377 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2378 /* ...and wait for it to complete. */ 2379 fxp_dma_wait(&cbp->cb_status, sc); 2380 device_printf(sc->dev, 2381 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2382 sc->tunable_int_delay, 2383 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2384 sc->flags |= FXP_FLAG_UCODE; 2385} 2386 2387static int 2388sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2389{ 2390 int error, value; 2391 2392 value = *(int *)arg1; 2393 error = sysctl_handle_int(oidp, &value, 0, req); 2394 if (error || !req->newptr) 2395 return (error); 2396 if (value < low || value > high) 2397 return (EINVAL); 2398 *(int *)arg1 = value; 2399 return (0); 2400} 2401 2402/* 2403 * Interrupt delay is expressed in microseconds, a multiplier is used 2404 * to convert this to the appropriate clock ticks before using. 2405 */ 2406static int 2407sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2408{ 2409 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2410} 2411 2412static int 2413sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2414{ 2415 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2416} 2417