if_fxp.c revision 111119
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 111119 2003-02-19 05:47:46Z imp $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/sysctl.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <net/ethernet.h> 61#include <net/if_arp.h> 62 63#include <vm/vm.h> /* for vtophys */ 64#include <vm/pmap.h> /* for vtophys */ 65#include <machine/clock.h> /* for DELAY */ 66 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73#include <dev/mii/mii.h> 74#include <dev/mii/miivar.h> 75 76#include <dev/fxp/if_fxpreg.h> 77#include <dev/fxp/if_fxpvar.h> 78#include <dev/fxp/rcvbundl.h> 79 80MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81#include "miibus_if.h" 82 83/* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92#define RFA_ALIGNMENT_FUDGE 2 93 94/* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99static int tx_threshold = 64; 100 101/* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135}; 136 137struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140}; 141 142/* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0x1039, "Intel Pro/100 Ethernet" }, 163 { 0x103A, "Intel Pro/100 Ethernet" }, 164 { 0x103B, "Intel Pro/100 Ethernet" }, 165 { 0x103C, "Intel Pro/100 Ethernet" }, 166 { 0x103D, "Intel Pro/100 Ethernet" }, 167 { 0x103E, "Intel Pro/100 Ethernet" }, 168 { 0x1059, "Intel Pro/100 M Mobile Connection" }, 169 { 0, NULL }, 170}; 171 172static int fxp_probe(device_t dev); 173static int fxp_attach(device_t dev); 174static int fxp_detach(device_t dev); 175static int fxp_shutdown(device_t dev); 176static int fxp_suspend(device_t dev); 177static int fxp_resume(device_t dev); 178 179static void fxp_intr(void *xsc); 180static void fxp_init(void *xsc); 181static void fxp_tick(void *xsc); 182static void fxp_powerstate_d0(device_t dev); 183static void fxp_start(struct ifnet *ifp); 184static void fxp_stop(struct fxp_softc *sc); 185static void fxp_release(struct fxp_softc *sc); 186static int fxp_ioctl(struct ifnet *ifp, u_long command, 187 caddr_t data); 188static void fxp_watchdog(struct ifnet *ifp); 189static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 190static int fxp_mc_addrs(struct fxp_softc *sc); 191static void fxp_mc_setup(struct fxp_softc *sc); 192static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 193 int autosize); 194static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 195 u_int16_t data); 196static void fxp_autosize_eeprom(struct fxp_softc *sc); 197static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 198 int offset, int words); 199static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 200 int offset, int words); 201static int fxp_ifmedia_upd(struct ifnet *ifp); 202static void fxp_ifmedia_sts(struct ifnet *ifp, 203 struct ifmediareq *ifmr); 204static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 205static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 206 struct ifmediareq *ifmr); 207static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 208static void fxp_miibus_writereg(device_t dev, int phy, int reg, 209 int value); 210static void fxp_load_ucode(struct fxp_softc *sc); 211static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 212 int low, int high); 213static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 214static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 215static __inline void fxp_lwcopy(volatile u_int32_t *src, 216 volatile u_int32_t *dst); 217static __inline void fxp_scb_wait(struct fxp_softc *sc); 218static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 219static __inline void fxp_dma_wait(volatile u_int16_t *status, 220 struct fxp_softc *sc); 221 222static device_method_t fxp_methods[] = { 223 /* Device interface */ 224 DEVMETHOD(device_probe, fxp_probe), 225 DEVMETHOD(device_attach, fxp_attach), 226 DEVMETHOD(device_detach, fxp_detach), 227 DEVMETHOD(device_shutdown, fxp_shutdown), 228 DEVMETHOD(device_suspend, fxp_suspend), 229 DEVMETHOD(device_resume, fxp_resume), 230 231 /* MII interface */ 232 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 233 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 234 235 { 0, 0 } 236}; 237 238static driver_t fxp_driver = { 239 "fxp", 240 fxp_methods, 241 sizeof(struct fxp_softc), 242}; 243 244static devclass_t fxp_devclass; 245 246DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 247DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 248DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 249 250static int fxp_rnr; 251SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 252 253/* 254 * Inline function to copy a 16-bit aligned 32-bit quantity. 255 */ 256static __inline void 257fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 258{ 259#ifdef __i386__ 260 *dst = *src; 261#else 262 volatile u_int16_t *a = (volatile u_int16_t *)src; 263 volatile u_int16_t *b = (volatile u_int16_t *)dst; 264 265 b[0] = a[0]; 266 b[1] = a[1]; 267#endif 268} 269 270/* 271 * Wait for the previous command to be accepted (but not necessarily 272 * completed). 273 */ 274static __inline void 275fxp_scb_wait(struct fxp_softc *sc) 276{ 277 int i = 10000; 278 279 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 280 DELAY(2); 281 if (i == 0) 282 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 283 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 284 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 285 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 286 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 287} 288 289static __inline void 290fxp_scb_cmd(struct fxp_softc *sc, int cmd) 291{ 292 293 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 294 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 295 fxp_scb_wait(sc); 296 } 297 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 298} 299 300static __inline void 301fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 302{ 303 int i = 10000; 304 305 while (!(*status & FXP_CB_STATUS_C) && --i) 306 DELAY(2); 307 if (i == 0) 308 device_printf(sc->dev, "DMA timeout\n"); 309} 310 311/* 312 * Return identification string if this is device is ours. 313 */ 314static int 315fxp_probe(device_t dev) 316{ 317 u_int16_t devid; 318 struct fxp_ident *ident; 319 320 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 321 devid = pci_get_device(dev); 322 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 323 if (ident->devid == devid) { 324 device_set_desc(dev, ident->name); 325 return (0); 326 } 327 } 328 } 329 return (ENXIO); 330} 331 332static void 333fxp_powerstate_d0(device_t dev) 334{ 335#if __FreeBSD_version >= 430002 336 u_int32_t iobase, membase, irq; 337 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 /* Save important PCI config data. */ 340 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 341 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 342 irq = pci_read_config(dev, PCIR_INTLINE, 4); 343 344 /* Reset the power state. */ 345 device_printf(dev, "chip is in D%d power mode " 346 "-- setting to D0\n", pci_get_powerstate(dev)); 347 348 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 349 350 /* Restore PCI config data. */ 351 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 352 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 353 pci_write_config(dev, PCIR_INTLINE, irq, 4); 354 } 355#endif 356} 357 358static int 359fxp_attach(device_t dev) 360{ 361 int error = 0; 362 struct fxp_softc *sc = device_get_softc(dev); 363 struct ifnet *ifp; 364 u_int32_t val; 365 u_int16_t data; 366 int i, rid, m1, m2, prefer_iomap; 367 int s; 368 369 bzero(sc, sizeof(*sc)); 370 sc->dev = dev; 371 callout_handle_init(&sc->stat_ch); 372 sysctl_ctx_init(&sc->sysctl_ctx); 373 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 374 MTX_DEF | MTX_RECURSE); 375 376 s = splimp(); 377 378 /* 379 * Enable bus mastering. Enable memory space too, in case 380 * BIOS/Prom forgot about it. 381 */ 382 val = pci_read_config(dev, PCIR_COMMAND, 2); 383 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 384 pci_write_config(dev, PCIR_COMMAND, val, 2); 385 val = pci_read_config(dev, PCIR_COMMAND, 2); 386 387 fxp_powerstate_d0(dev); 388 389 /* 390 * Figure out which we should try first - memory mapping or i/o mapping? 391 * We default to memory mapping. Then we accept an override from the 392 * command line. Then we check to see which one is enabled. 393 */ 394 m1 = PCIM_CMD_MEMEN; 395 m2 = PCIM_CMD_PORTEN; 396 prefer_iomap = 0; 397 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 398 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 399 m1 = PCIM_CMD_PORTEN; 400 m2 = PCIM_CMD_MEMEN; 401 } 402 403 if (val & m1) { 404 sc->rtp = 405 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 406 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 407 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 408 0, ~0, 1, RF_ACTIVE); 409 } 410 if (sc->mem == NULL && (val & m2)) { 411 sc->rtp = 412 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 413 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 414 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 415 0, ~0, 1, RF_ACTIVE); 416 } 417 418 if (!sc->mem) { 419 device_printf(dev, "could not map device registers\n"); 420 error = ENXIO; 421 goto fail; 422 } 423 if (bootverbose) { 424 device_printf(dev, "using %s space register mapping\n", 425 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 426 } 427 428 sc->sc_st = rman_get_bustag(sc->mem); 429 sc->sc_sh = rman_get_bushandle(sc->mem); 430 431 /* 432 * Allocate our interrupt. 433 */ 434 rid = 0; 435 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 436 RF_SHAREABLE | RF_ACTIVE); 437 if (sc->irq == NULL) { 438 device_printf(dev, "could not map interrupt\n"); 439 error = ENXIO; 440 goto fail; 441 } 442 443 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 444 fxp_intr, sc, &sc->ih); 445 if (error) { 446 device_printf(dev, "could not setup irq\n"); 447 goto fail; 448 } 449 450 /* 451 * Reset to a stable state. 452 */ 453 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 454 DELAY(10); 455 456 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 457 M_DEVBUF, M_NOWAIT | M_ZERO); 458 if (sc->cbl_base == NULL) 459 goto failmem; 460 461 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 462 M_NOWAIT | M_ZERO); 463 if (sc->fxp_stats == NULL) 464 goto failmem; 465 466 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 467 if (sc->mcsp == NULL) 468 goto failmem; 469 470 /* 471 * Pre-allocate our receive buffers. 472 */ 473 for (i = 0; i < FXP_NRFABUFS; i++) { 474 if (fxp_add_rfabuf(sc, NULL) != 0) { 475 goto failmem; 476 } 477 } 478 479 /* 480 * Find out how large of an SEEPROM we have. 481 */ 482 fxp_autosize_eeprom(sc); 483 484 /* 485 * Determine whether we must use the 503 serial interface. 486 */ 487 fxp_read_eeprom(sc, &data, 6, 1); 488 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 489 (data & FXP_PHY_SERIAL_ONLY)) 490 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 491 492 /* 493 * Create the sysctl tree 494 */ 495 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 496 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 497 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 498 if (sc->sysctl_tree == NULL) 499 goto fail; 500 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 501 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 502 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 503 "FXP driver receive interrupt microcode bundling delay"); 504 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 505 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 506 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 507 "FXP driver receive interrupt microcode bundle size limit"); 508 509 /* 510 * Pull in device tunables. 511 */ 512 sc->tunable_int_delay = TUNABLE_INT_DELAY; 513 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 514 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 515 "int_delay", &sc->tunable_int_delay); 516 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 517 "bundle_max", &sc->tunable_bundle_max); 518 519 /* 520 * Find out the chip revision; lump all 82557 revs together. 521 */ 522 fxp_read_eeprom(sc, &data, 5, 1); 523 if ((data >> 8) == 1) 524 sc->revision = FXP_REV_82557; 525 else 526 sc->revision = pci_get_revid(dev); 527 528 /* 529 * Enable workarounds for certain chip revision deficiencies. 530 * 531 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 532 * some systems based a normal 82559 design, have a defect where 533 * the chip can cause a PCI protocol violation if it receives 534 * a CU_RESUME command when it is entering the IDLE state. The 535 * workaround is to disable Dynamic Standby Mode, so the chip never 536 * deasserts CLKRUN#, and always remains in an active state. 537 * 538 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 539 */ 540 i = pci_get_device(dev); 541 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 542 sc->revision >= FXP_REV_82559_A0) { 543 fxp_read_eeprom(sc, &data, 10, 1); 544 if (data & 0x02) { /* STB enable */ 545 u_int16_t cksum; 546 int i; 547 548 device_printf(dev, 549 "Disabling dynamic standby mode in EEPROM\n"); 550 data &= ~0x02; 551 fxp_write_eeprom(sc, &data, 10, 1); 552 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 553 cksum = 0; 554 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 555 fxp_read_eeprom(sc, &data, i, 1); 556 cksum += data; 557 } 558 i = (1 << sc->eeprom_size) - 1; 559 cksum = 0xBABA - cksum; 560 fxp_read_eeprom(sc, &data, i, 1); 561 fxp_write_eeprom(sc, &cksum, i, 1); 562 device_printf(dev, 563 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 564 i, data, cksum); 565#if 1 566 /* 567 * If the user elects to continue, try the software 568 * workaround, as it is better than nothing. 569 */ 570 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 571#endif 572 } 573 } 574 575 /* 576 * If we are not a 82557 chip, we can enable extended features. 577 */ 578 if (sc->revision != FXP_REV_82557) { 579 /* 580 * If MWI is enabled in the PCI configuration, and there 581 * is a valid cacheline size (8 or 16 dwords), then tell 582 * the board to turn on MWI. 583 */ 584 if (val & PCIM_CMD_MWRICEN && 585 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 586 sc->flags |= FXP_FLAG_MWI_ENABLE; 587 588 /* turn on the extended TxCB feature */ 589 sc->flags |= FXP_FLAG_EXT_TXCB; 590 591 /* enable reception of long frames for VLAN */ 592 sc->flags |= FXP_FLAG_LONG_PKT_EN; 593 } 594 595 /* 596 * Read MAC address. 597 */ 598 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 599 device_printf(dev, "Ethernet address %6D%s\n", 600 sc->arpcom.ac_enaddr, ":", 601 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 602 if (bootverbose) { 603 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 604 pci_get_vendor(dev), pci_get_device(dev), 605 pci_get_subvendor(dev), pci_get_subdevice(dev), 606 pci_get_revid(dev)); 607 fxp_read_eeprom(sc, &data, 10, 1); 608 device_printf(dev, "Dynamic Standby mode is %s\n", 609 data & 0x02 ? "enabled" : "disabled"); 610 } 611 612 /* 613 * If this is only a 10Mbps device, then there is no MII, and 614 * the PHY will use a serial interface instead. 615 * 616 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 617 * doesn't have a programming interface of any sort. The 618 * media is sensed automatically based on how the link partner 619 * is configured. This is, in essence, manual configuration. 620 */ 621 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 622 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 623 fxp_serial_ifmedia_sts); 624 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 625 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 626 } else { 627 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 628 fxp_ifmedia_sts)) { 629 device_printf(dev, "MII without any PHY!\n"); 630 error = ENXIO; 631 goto fail; 632 } 633 } 634 635 ifp = &sc->arpcom.ac_if; 636 ifp->if_unit = device_get_unit(dev); 637 ifp->if_name = "fxp"; 638 ifp->if_output = ether_output; 639 ifp->if_baudrate = 100000000; 640 ifp->if_init = fxp_init; 641 ifp->if_softc = sc; 642 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 643 ifp->if_ioctl = fxp_ioctl; 644 ifp->if_start = fxp_start; 645 ifp->if_watchdog = fxp_watchdog; 646 647 /* 648 * Attach the interface. 649 */ 650 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 651 652 /* 653 * Tell the upper layer(s) we support long frames. 654 */ 655 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 656 ifp->if_capabilities |= IFCAP_VLAN_MTU; 657 658 /* 659 * Let the system queue as many packets as we have available 660 * TX descriptors. 661 */ 662 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 663 664 splx(s); 665 return (0); 666 667failmem: 668 device_printf(dev, "Failed to malloc memory\n"); 669 error = ENOMEM; 670fail: 671 splx(s); 672 fxp_release(sc); 673 return (error); 674} 675 676/* 677 * release all resources 678 */ 679static void 680fxp_release(struct fxp_softc *sc) 681{ 682 683 bus_generic_detach(sc->dev); 684 if (sc->miibus) 685 device_delete_child(sc->dev, sc->miibus); 686 687 if (sc->cbl_base) 688 free(sc->cbl_base, M_DEVBUF); 689 if (sc->fxp_stats) 690 free(sc->fxp_stats, M_DEVBUF); 691 if (sc->mcsp) 692 free(sc->mcsp, M_DEVBUF); 693 if (sc->rfa_headm) 694 m_freem(sc->rfa_headm); 695 696 if (sc->ih) 697 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 698 if (sc->irq) 699 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 700 if (sc->mem) 701 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 702 703 sysctl_ctx_free(&sc->sysctl_ctx); 704 705 mtx_destroy(&sc->sc_mtx); 706} 707 708/* 709 * Detach interface. 710 */ 711static int 712fxp_detach(device_t dev) 713{ 714 struct fxp_softc *sc = device_get_softc(dev); 715 int s; 716 717 /* disable interrupts */ 718 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 719 720 s = splimp(); 721 722 /* 723 * Stop DMA and drop transmit queue. 724 */ 725 fxp_stop(sc); 726 727 /* 728 * Close down routes etc. 729 */ 730 ether_ifdetach(&sc->arpcom.ac_if); 731 732 /* 733 * Free all media structures. 734 */ 735 ifmedia_removeall(&sc->sc_media); 736 737 splx(s); 738 739 /* Release our allocated resources. */ 740 fxp_release(sc); 741 742 return (0); 743} 744 745/* 746 * Device shutdown routine. Called at system shutdown after sync. The 747 * main purpose of this routine is to shut off receiver DMA so that 748 * kernel memory doesn't get clobbered during warmboot. 749 */ 750static int 751fxp_shutdown(device_t dev) 752{ 753 /* 754 * Make sure that DMA is disabled prior to reboot. Not doing 755 * do could allow DMA to corrupt kernel memory during the 756 * reboot before the driver initializes. 757 */ 758 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 759 return (0); 760} 761 762/* 763 * Device suspend routine. Stop the interface and save some PCI 764 * settings in case the BIOS doesn't restore them properly on 765 * resume. 766 */ 767static int 768fxp_suspend(device_t dev) 769{ 770 struct fxp_softc *sc = device_get_softc(dev); 771 int i, s; 772 773 s = splimp(); 774 775 fxp_stop(sc); 776 777 for (i = 0; i < 5; i++) 778 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 779 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 780 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 781 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 782 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 783 784 sc->suspended = 1; 785 786 splx(s); 787 return (0); 788} 789 790/* 791 * Device resume routine. Restore some PCI settings in case the BIOS 792 * doesn't, re-enable busmastering, and restart the interface if 793 * appropriate. 794 */ 795static int 796fxp_resume(device_t dev) 797{ 798 struct fxp_softc *sc = device_get_softc(dev); 799 struct ifnet *ifp = &sc->sc_if; 800 u_int16_t pci_command; 801 int i, s; 802 803 s = splimp(); 804 805 fxp_powerstate_d0(dev); 806 807 /* better way to do this? */ 808 for (i = 0; i < 5; i++) 809 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 810 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 811 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 812 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 813 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 814 815 /* reenable busmastering */ 816 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 817 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 818 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 819 820 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 821 DELAY(10); 822 823 /* reinitialize interface if necessary */ 824 if (ifp->if_flags & IFF_UP) 825 fxp_init(sc); 826 827 sc->suspended = 0; 828 829 splx(s); 830 return (0); 831} 832 833static void 834fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 835{ 836 u_int16_t reg; 837 int x; 838 839 /* 840 * Shift in data. 841 */ 842 for (x = 1 << (length - 1); x; x >>= 1) { 843 if (data & x) 844 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 845 else 846 reg = FXP_EEPROM_EECS; 847 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 848 DELAY(1); 849 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 850 DELAY(1); 851 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 852 DELAY(1); 853 } 854} 855 856/* 857 * Read from the serial EEPROM. Basically, you manually shift in 858 * the read opcode (one bit at a time) and then shift in the address, 859 * and then you shift out the data (all of this one bit at a time). 860 * The word size is 16 bits, so you have to provide the address for 861 * every 16 bits of data. 862 */ 863static u_int16_t 864fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 865{ 866 u_int16_t reg, data; 867 int x; 868 869 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 870 /* 871 * Shift in read opcode. 872 */ 873 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 874 /* 875 * Shift in address. 876 */ 877 data = 0; 878 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 879 if (offset & x) 880 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 881 else 882 reg = FXP_EEPROM_EECS; 883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 884 DELAY(1); 885 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 886 DELAY(1); 887 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 888 DELAY(1); 889 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 890 data++; 891 if (autosize && reg == 0) { 892 sc->eeprom_size = data; 893 break; 894 } 895 } 896 /* 897 * Shift out data. 898 */ 899 data = 0; 900 reg = FXP_EEPROM_EECS; 901 for (x = 1 << 15; x; x >>= 1) { 902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 903 DELAY(1); 904 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 905 data |= x; 906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 907 DELAY(1); 908 } 909 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 910 DELAY(1); 911 912 return (data); 913} 914 915static void 916fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 917{ 918 int i; 919 920 /* 921 * Erase/write enable. 922 */ 923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 924 fxp_eeprom_shiftin(sc, 0x4, 3); 925 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 926 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 927 DELAY(1); 928 /* 929 * Shift in write opcode, address, data. 930 */ 931 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 932 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 933 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 934 fxp_eeprom_shiftin(sc, data, 16); 935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 936 DELAY(1); 937 /* 938 * Wait for EEPROM to finish up. 939 */ 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 941 DELAY(1); 942 for (i = 0; i < 1000; i++) { 943 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 944 break; 945 DELAY(50); 946 } 947 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 948 DELAY(1); 949 /* 950 * Erase/write disable. 951 */ 952 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 953 fxp_eeprom_shiftin(sc, 0x4, 3); 954 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 956 DELAY(1); 957} 958 959/* 960 * From NetBSD: 961 * 962 * Figure out EEPROM size. 963 * 964 * 559's can have either 64-word or 256-word EEPROMs, the 558 965 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 966 * talks about the existance of 16 to 256 word EEPROMs. 967 * 968 * The only known sizes are 64 and 256, where the 256 version is used 969 * by CardBus cards to store CIS information. 970 * 971 * The address is shifted in msb-to-lsb, and after the last 972 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 973 * after which follows the actual data. We try to detect this zero, by 974 * probing the data-out bit in the EEPROM control register just after 975 * having shifted in a bit. If the bit is zero, we assume we've 976 * shifted enough address bits. The data-out should be tri-state, 977 * before this, which should translate to a logical one. 978 */ 979static void 980fxp_autosize_eeprom(struct fxp_softc *sc) 981{ 982 983 /* guess maximum size of 256 words */ 984 sc->eeprom_size = 8; 985 986 /* autosize */ 987 (void) fxp_eeprom_getword(sc, 0, 1); 988} 989 990static void 991fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 992{ 993 int i; 994 995 for (i = 0; i < words; i++) 996 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 997} 998 999static void 1000fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1001{ 1002 int i; 1003 1004 for (i = 0; i < words; i++) 1005 fxp_eeprom_putword(sc, offset + i, data[i]); 1006} 1007 1008/* 1009 * Start packet transmission on the interface. 1010 */ 1011static void 1012fxp_start(struct ifnet *ifp) 1013{ 1014 struct fxp_softc *sc = ifp->if_softc; 1015 struct fxp_cb_tx *txp; 1016 1017 /* 1018 * See if we need to suspend xmit until the multicast filter 1019 * has been reprogrammed (which can only be done at the head 1020 * of the command chain). 1021 */ 1022 if (sc->need_mcsetup) { 1023 return; 1024 } 1025 1026 txp = NULL; 1027 1028 /* 1029 * We're finished if there is nothing more to add to the list or if 1030 * we're all filled up with buffers to transmit. 1031 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1032 * a NOP command when needed. 1033 */ 1034 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1035 struct mbuf *m, *mb_head; 1036 int segment; 1037 1038 /* 1039 * Grab a packet to transmit. 1040 */ 1041 IF_DEQUEUE(&ifp->if_snd, mb_head); 1042 1043 /* 1044 * Get pointer to next available tx desc. 1045 */ 1046 txp = sc->cbl_last->next; 1047 1048 /* 1049 * Go through each of the mbufs in the chain and initialize 1050 * the transmit buffer descriptors with the physical address 1051 * and size of the mbuf. 1052 */ 1053tbdinit: 1054 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1055 if (m->m_len != 0) { 1056 if (segment == FXP_NTXSEG) 1057 break; 1058 txp->tbd[segment].tb_addr = 1059 vtophys(mtod(m, vm_offset_t)); 1060 txp->tbd[segment].tb_size = m->m_len; 1061 segment++; 1062 } 1063 } 1064 if (m != NULL) { 1065 struct mbuf *mn; 1066 1067 /* 1068 * We ran out of segments. We have to recopy this 1069 * mbuf chain first. Bail out if we can't get the 1070 * new buffers. 1071 */ 1072 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1073 if (mn == NULL) { 1074 m_freem(mb_head); 1075 break; 1076 } 1077 if (mb_head->m_pkthdr.len > MHLEN) { 1078 MCLGET(mn, M_DONTWAIT); 1079 if ((mn->m_flags & M_EXT) == 0) { 1080 m_freem(mn); 1081 m_freem(mb_head); 1082 break; 1083 } 1084 } 1085 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1086 mtod(mn, caddr_t)); 1087 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1088 m_freem(mb_head); 1089 mb_head = mn; 1090 goto tbdinit; 1091 } 1092 1093 txp->tbd_number = segment; 1094 txp->mb_head = mb_head; 1095 txp->cb_status = 0; 1096 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1097 txp->cb_command = 1098 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1099 FXP_CB_COMMAND_S; 1100 } else { 1101 txp->cb_command = 1102 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1103 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1104 /* 1105 * Set a 5 second timer just in case we don't hear 1106 * from the card again. 1107 */ 1108 ifp->if_timer = 5; 1109 } 1110 txp->tx_threshold = tx_threshold; 1111 1112 /* 1113 * Advance the end of list forward. 1114 */ 1115 1116#ifdef __alpha__ 1117 /* 1118 * On platforms which can't access memory in 16-bit 1119 * granularities, we must prevent the card from DMA'ing 1120 * up the status while we update the command field. 1121 * This could cause us to overwrite the completion status. 1122 */ 1123 atomic_clear_short(&sc->cbl_last->cb_command, 1124 FXP_CB_COMMAND_S); 1125#else 1126 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1127#endif /*__alpha__*/ 1128 sc->cbl_last = txp; 1129 1130 /* 1131 * Advance the beginning of the list forward if there are 1132 * no other packets queued (when nothing is queued, cbl_first 1133 * sits on the last TxCB that was sent out). 1134 */ 1135 if (sc->tx_queued == 0) 1136 sc->cbl_first = txp; 1137 1138 sc->tx_queued++; 1139 1140 /* 1141 * Pass packet to bpf if there is a listener. 1142 */ 1143 BPF_MTAP(ifp, mb_head); 1144 } 1145 1146 /* 1147 * We're finished. If we added to the list, issue a RESUME to get DMA 1148 * going again if suspended. 1149 */ 1150 if (txp != NULL) { 1151 fxp_scb_wait(sc); 1152 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1153 } 1154} 1155 1156static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1157 1158#ifdef DEVICE_POLLING 1159static poll_handler_t fxp_poll; 1160 1161static void 1162fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1163{ 1164 struct fxp_softc *sc = ifp->if_softc; 1165 u_int8_t statack; 1166 1167 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1169 return; 1170 } 1171 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1172 FXP_SCB_STATACK_FR; 1173 if (cmd == POLL_AND_CHECK_STATUS) { 1174 u_int8_t tmp; 1175 1176 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1177 if (tmp == 0xff || tmp == 0) 1178 return; /* nothing to do */ 1179 tmp &= ~statack; 1180 /* ack what we can */ 1181 if (tmp != 0) 1182 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1183 statack |= tmp; 1184 } 1185 fxp_intr_body(sc, statack, count); 1186} 1187#endif /* DEVICE_POLLING */ 1188 1189/* 1190 * Process interface interrupts. 1191 */ 1192static void 1193fxp_intr(void *xsc) 1194{ 1195 struct fxp_softc *sc = xsc; 1196 u_int8_t statack; 1197 1198#ifdef DEVICE_POLLING 1199 struct ifnet *ifp = &sc->sc_if; 1200 1201 if (ifp->if_flags & IFF_POLLING) 1202 return; 1203 if (ether_poll_register(fxp_poll, ifp)) { 1204 /* disable interrupts */ 1205 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1206 fxp_poll(ifp, 0, 1); 1207 return; 1208 } 1209#endif 1210 1211 if (sc->suspended) { 1212 return; 1213 } 1214 1215 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1216 /* 1217 * It should not be possible to have all bits set; the 1218 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1219 * all bits are set, this may indicate that the card has 1220 * been physically ejected, so ignore it. 1221 */ 1222 if (statack == 0xff) 1223 return; 1224 1225 /* 1226 * First ACK all the interrupts in this pass. 1227 */ 1228 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1229 fxp_intr_body(sc, statack, -1); 1230 } 1231} 1232 1233static void 1234fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1235{ 1236 struct ifnet *ifp = &sc->sc_if; 1237 struct mbuf *m; 1238 struct fxp_rfa *rfa; 1239 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1240 1241 if (rnr) 1242 fxp_rnr++; 1243#ifdef DEVICE_POLLING 1244 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1245 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1246 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1247 rnr = 1; 1248 } 1249#endif 1250 1251 /* 1252 * Free any finished transmit mbuf chains. 1253 * 1254 * Handle the CNA event likt a CXTNO event. It used to 1255 * be that this event (control unit not ready) was not 1256 * encountered, but it is now with the SMPng modifications. 1257 * The exact sequence of events that occur when the interface 1258 * is brought up are different now, and if this event 1259 * goes unhandled, the configuration/rxfilter setup sequence 1260 * can stall for several seconds. The result is that no 1261 * packets go out onto the wire for about 5 to 10 seconds 1262 * after the interface is ifconfig'ed for the first time. 1263 */ 1264 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1265 struct fxp_cb_tx *txp; 1266 1267 for (txp = sc->cbl_first; sc->tx_queued && 1268 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1269 txp = txp->next) { 1270 if (txp->mb_head != NULL) { 1271 m_freem(txp->mb_head); 1272 txp->mb_head = NULL; 1273 } 1274 sc->tx_queued--; 1275 } 1276 sc->cbl_first = txp; 1277 ifp->if_timer = 0; 1278 if (sc->tx_queued == 0) { 1279 if (sc->need_mcsetup) 1280 fxp_mc_setup(sc); 1281 } 1282 /* 1283 * Try to start more packets transmitting. 1284 */ 1285 if (ifp->if_snd.ifq_head != NULL) 1286 fxp_start(ifp); 1287 } 1288 1289 /* 1290 * Just return if nothing happened on the receive side. 1291 */ 1292 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1293 return; 1294 1295 /* 1296 * Process receiver interrupts. If a no-resource (RNR) 1297 * condition exists, get whatever packets we can and 1298 * re-start the receiver. 1299 * 1300 * When using polling, we do not process the list to completion, 1301 * so when we get an RNR interrupt we must defer the restart 1302 * until we hit the last buffer with the C bit set. 1303 * If we run out of cycles and rfa_headm has the C bit set, 1304 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1305 * that the info will be used in the subsequent polling cycle. 1306 */ 1307 for (;;) { 1308 m = sc->rfa_headm; 1309 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1310 RFA_ALIGNMENT_FUDGE); 1311 1312#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1313 if (count >= 0 && count-- == 0) { 1314 if (rnr) { 1315 /* Defer RNR processing until the next time. */ 1316 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1317 rnr = 0; 1318 } 1319 break; 1320 } 1321#endif /* DEVICE_POLLING */ 1322 1323 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1324 break; 1325 1326 /* 1327 * Remove first packet from the chain. 1328 */ 1329 sc->rfa_headm = m->m_next; 1330 m->m_next = NULL; 1331 1332 /* 1333 * Add a new buffer to the receive chain. 1334 * If this fails, the old buffer is recycled 1335 * instead. 1336 */ 1337 if (fxp_add_rfabuf(sc, m) == 0) { 1338 int total_len; 1339 1340 /* 1341 * Fetch packet length (the top 2 bits of 1342 * actual_size are flags set by the controller 1343 * upon completion), and drop the packet in case 1344 * of bogus length or CRC errors. 1345 */ 1346 total_len = rfa->actual_size & 0x3fff; 1347 if (total_len < sizeof(struct ether_header) || 1348 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1349 sizeof(struct fxp_rfa) || 1350 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1351 m_freem(m); 1352 continue; 1353 } 1354 1355 m->m_pkthdr.len = m->m_len = total_len; 1356 m->m_pkthdr.rcvif = ifp; 1357 1358 (*ifp->if_input)(ifp, m); 1359 } 1360 } 1361 if (rnr) { 1362 fxp_scb_wait(sc); 1363 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1364 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1365 RFA_ALIGNMENT_FUDGE); 1366 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1367 } 1368} 1369 1370/* 1371 * Update packet in/out/collision statistics. The i82557 doesn't 1372 * allow you to access these counters without doing a fairly 1373 * expensive DMA to get _all_ of the statistics it maintains, so 1374 * we do this operation here only once per second. The statistics 1375 * counters in the kernel are updated from the previous dump-stats 1376 * DMA and then a new dump-stats DMA is started. The on-chip 1377 * counters are zeroed when the DMA completes. If we can't start 1378 * the DMA immediately, we don't wait - we just prepare to read 1379 * them again next time. 1380 */ 1381static void 1382fxp_tick(void *xsc) 1383{ 1384 struct fxp_softc *sc = xsc; 1385 struct ifnet *ifp = &sc->sc_if; 1386 struct fxp_stats *sp = sc->fxp_stats; 1387 struct fxp_cb_tx *txp; 1388 int s; 1389 1390 ifp->if_opackets += sp->tx_good; 1391 ifp->if_collisions += sp->tx_total_collisions; 1392 if (sp->rx_good) { 1393 ifp->if_ipackets += sp->rx_good; 1394 sc->rx_idle_secs = 0; 1395 } else { 1396 /* 1397 * Receiver's been idle for another second. 1398 */ 1399 sc->rx_idle_secs++; 1400 } 1401 ifp->if_ierrors += 1402 sp->rx_crc_errors + 1403 sp->rx_alignment_errors + 1404 sp->rx_rnr_errors + 1405 sp->rx_overrun_errors; 1406 /* 1407 * If any transmit underruns occured, bump up the transmit 1408 * threshold by another 512 bytes (64 * 8). 1409 */ 1410 if (sp->tx_underruns) { 1411 ifp->if_oerrors += sp->tx_underruns; 1412 if (tx_threshold < 192) 1413 tx_threshold += 64; 1414 } 1415 s = splimp(); 1416 /* 1417 * Release any xmit buffers that have completed DMA. This isn't 1418 * strictly necessary to do here, but it's advantagous for mbufs 1419 * with external storage to be released in a timely manner rather 1420 * than being defered for a potentially long time. This limits 1421 * the delay to a maximum of one second. 1422 */ 1423 for (txp = sc->cbl_first; sc->tx_queued && 1424 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1425 txp = txp->next) { 1426 if (txp->mb_head != NULL) { 1427 m_freem(txp->mb_head); 1428 txp->mb_head = NULL; 1429 } 1430 sc->tx_queued--; 1431 } 1432 sc->cbl_first = txp; 1433 /* 1434 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1435 * then assume the receiver has locked up and attempt to clear 1436 * the condition by reprogramming the multicast filter. This is 1437 * a work-around for a bug in the 82557 where the receiver locks 1438 * up if it gets certain types of garbage in the syncronization 1439 * bits prior to the packet header. This bug is supposed to only 1440 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1441 * mode as well (perhaps due to a 10/100 speed transition). 1442 */ 1443 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1444 sc->rx_idle_secs = 0; 1445 fxp_mc_setup(sc); 1446 } 1447 /* 1448 * If there is no pending command, start another stats 1449 * dump. Otherwise punt for now. 1450 */ 1451 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1452 /* 1453 * Start another stats dump. 1454 */ 1455 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1456 } else { 1457 /* 1458 * A previous command is still waiting to be accepted. 1459 * Just zero our copy of the stats and wait for the 1460 * next timer event to update them. 1461 */ 1462 sp->tx_good = 0; 1463 sp->tx_underruns = 0; 1464 sp->tx_total_collisions = 0; 1465 1466 sp->rx_good = 0; 1467 sp->rx_crc_errors = 0; 1468 sp->rx_alignment_errors = 0; 1469 sp->rx_rnr_errors = 0; 1470 sp->rx_overrun_errors = 0; 1471 } 1472 if (sc->miibus != NULL) 1473 mii_tick(device_get_softc(sc->miibus)); 1474 splx(s); 1475 /* 1476 * Schedule another timeout one second from now. 1477 */ 1478 sc->stat_ch = timeout(fxp_tick, sc, hz); 1479} 1480 1481/* 1482 * Stop the interface. Cancels the statistics updater and resets 1483 * the interface. 1484 */ 1485static void 1486fxp_stop(struct fxp_softc *sc) 1487{ 1488 struct ifnet *ifp = &sc->sc_if; 1489 struct fxp_cb_tx *txp; 1490 int i; 1491 1492 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1493 ifp->if_timer = 0; 1494 1495#ifdef DEVICE_POLLING 1496 ether_poll_deregister(ifp); 1497#endif 1498 /* 1499 * Cancel stats updater. 1500 */ 1501 untimeout(fxp_tick, sc, sc->stat_ch); 1502 1503 /* 1504 * Issue software reset, which also unloads the microcode. 1505 */ 1506 sc->flags &= ~FXP_FLAG_UCODE; 1507 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1508 DELAY(50); 1509 1510 /* 1511 * Release any xmit buffers. 1512 */ 1513 txp = sc->cbl_base; 1514 if (txp != NULL) { 1515 for (i = 0; i < FXP_NTXCB; i++) { 1516 if (txp[i].mb_head != NULL) { 1517 m_freem(txp[i].mb_head); 1518 txp[i].mb_head = NULL; 1519 } 1520 } 1521 } 1522 sc->tx_queued = 0; 1523 1524 /* 1525 * Free all the receive buffers then reallocate/reinitialize 1526 */ 1527 if (sc->rfa_headm != NULL) 1528 m_freem(sc->rfa_headm); 1529 sc->rfa_headm = NULL; 1530 sc->rfa_tailm = NULL; 1531 for (i = 0; i < FXP_NRFABUFS; i++) { 1532 if (fxp_add_rfabuf(sc, NULL) != 0) { 1533 /* 1534 * This "can't happen" - we're at splimp() 1535 * and we just freed all the buffers we need 1536 * above. 1537 */ 1538 panic("fxp_stop: no buffers!"); 1539 } 1540 } 1541} 1542 1543/* 1544 * Watchdog/transmission transmit timeout handler. Called when a 1545 * transmission is started on the interface, but no interrupt is 1546 * received before the timeout. This usually indicates that the 1547 * card has wedged for some reason. 1548 */ 1549static void 1550fxp_watchdog(struct ifnet *ifp) 1551{ 1552 struct fxp_softc *sc = ifp->if_softc; 1553 1554 device_printf(sc->dev, "device timeout\n"); 1555 ifp->if_oerrors++; 1556 1557 fxp_init(sc); 1558} 1559 1560static void 1561fxp_init(void *xsc) 1562{ 1563 struct fxp_softc *sc = xsc; 1564 struct ifnet *ifp = &sc->sc_if; 1565 struct fxp_cb_config *cbp; 1566 struct fxp_cb_ias *cb_ias; 1567 struct fxp_cb_tx *txp; 1568 struct fxp_cb_mcs *mcsp; 1569 int i, prm, s; 1570 1571 s = splimp(); 1572 /* 1573 * Cancel any pending I/O 1574 */ 1575 fxp_stop(sc); 1576 1577 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1578 1579 /* 1580 * Initialize base of CBL and RFA memory. Loading with zero 1581 * sets it up for regular linear addressing. 1582 */ 1583 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1584 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1585 1586 fxp_scb_wait(sc); 1587 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1588 1589 /* 1590 * Initialize base of dump-stats buffer. 1591 */ 1592 fxp_scb_wait(sc); 1593 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1594 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1595 1596 /* 1597 * Attempt to load microcode if requested. 1598 */ 1599 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1600 fxp_load_ucode(sc); 1601 1602 /* 1603 * Initialize the multicast address list. 1604 */ 1605 if (fxp_mc_addrs(sc)) { 1606 mcsp = sc->mcsp; 1607 mcsp->cb_status = 0; 1608 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1609 mcsp->link_addr = -1; 1610 /* 1611 * Start the multicast setup command. 1612 */ 1613 fxp_scb_wait(sc); 1614 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1615 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1616 /* ...and wait for it to complete. */ 1617 fxp_dma_wait(&mcsp->cb_status, sc); 1618 } 1619 1620 /* 1621 * We temporarily use memory that contains the TxCB list to 1622 * construct the config CB. The TxCB list memory is rebuilt 1623 * later. 1624 */ 1625 cbp = (struct fxp_cb_config *) sc->cbl_base; 1626 1627 /* 1628 * This bcopy is kind of disgusting, but there are a bunch of must be 1629 * zero and must be one bits in this structure and this is the easiest 1630 * way to initialize them all to proper values. 1631 */ 1632 bcopy(fxp_cb_config_template, 1633 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1634 sizeof(fxp_cb_config_template)); 1635 1636 cbp->cb_status = 0; 1637 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1638 cbp->link_addr = -1; /* (no) next command */ 1639 cbp->byte_count = 22; /* (22) bytes to config */ 1640 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1641 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1642 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1643 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1644 cbp->type_enable = 0; /* actually reserved */ 1645 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1646 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1647 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1648 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1649 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1650 cbp->late_scb = 0; /* (don't) defer SCB update */ 1651 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1652 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1653 cbp->ci_int = 1; /* interrupt on CU idle */ 1654 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1655 cbp->ext_stats_dis = 1; /* disable extended counters */ 1656 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1657 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1658 cbp->disc_short_rx = !prm; /* discard short packets */ 1659 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1660 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1661 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1662 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1663 cbp->csma_dis = 0; /* (don't) disable link */ 1664 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1665 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1666 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1667 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1668 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1669 cbp->nsai = 1; /* (don't) disable source addr insert */ 1670 cbp->preamble_length = 2; /* (7 byte) preamble */ 1671 cbp->loopback = 0; /* (don't) loopback */ 1672 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1673 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1674 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1675 cbp->promiscuous = prm; /* promiscuous mode */ 1676 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1677 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1678 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1679 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1680 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1681 1682 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1683 cbp->padding = 1; /* (do) pad short tx packets */ 1684 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1685 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1686 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1687 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1688 /* must set wake_en in PMCSR also */ 1689 cbp->force_fdx = 0; /* (don't) force full duplex */ 1690 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1691 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1692 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1693 1694 if (sc->revision == FXP_REV_82557) { 1695 /* 1696 * The 82557 has no hardware flow control, the values 1697 * below are the defaults for the chip. 1698 */ 1699 cbp->fc_delay_lsb = 0; 1700 cbp->fc_delay_msb = 0x40; 1701 cbp->pri_fc_thresh = 3; 1702 cbp->tx_fc_dis = 0; 1703 cbp->rx_fc_restop = 0; 1704 cbp->rx_fc_restart = 0; 1705 cbp->fc_filter = 0; 1706 cbp->pri_fc_loc = 1; 1707 } else { 1708 cbp->fc_delay_lsb = 0x1f; 1709 cbp->fc_delay_msb = 0x01; 1710 cbp->pri_fc_thresh = 3; 1711 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1712 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1713 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1714 cbp->fc_filter = !prm; /* drop FC frames to host */ 1715 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1716 } 1717 1718 /* 1719 * Start the config command/DMA. 1720 */ 1721 fxp_scb_wait(sc); 1722 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1723 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1724 /* ...and wait for it to complete. */ 1725 fxp_dma_wait(&cbp->cb_status, sc); 1726 1727 /* 1728 * Now initialize the station address. Temporarily use the TxCB 1729 * memory area like we did above for the config CB. 1730 */ 1731 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1732 cb_ias->cb_status = 0; 1733 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1734 cb_ias->link_addr = -1; 1735 bcopy(sc->arpcom.ac_enaddr, 1736 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1737 sizeof(sc->arpcom.ac_enaddr)); 1738 1739 /* 1740 * Start the IAS (Individual Address Setup) command/DMA. 1741 */ 1742 fxp_scb_wait(sc); 1743 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1744 /* ...and wait for it to complete. */ 1745 fxp_dma_wait(&cb_ias->cb_status, sc); 1746 1747 /* 1748 * Initialize transmit control block (TxCB) list. 1749 */ 1750 1751 txp = sc->cbl_base; 1752 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1753 for (i = 0; i < FXP_NTXCB; i++) { 1754 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1755 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1756 txp[i].link_addr = 1757 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1758 if (sc->flags & FXP_FLAG_EXT_TXCB) 1759 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1760 else 1761 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1762 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1763 } 1764 /* 1765 * Set the suspend flag on the first TxCB and start the control 1766 * unit. It will execute the NOP and then suspend. 1767 */ 1768 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1769 sc->cbl_first = sc->cbl_last = txp; 1770 sc->tx_queued = 1; 1771 1772 fxp_scb_wait(sc); 1773 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1774 1775 /* 1776 * Initialize receiver buffer area - RFA. 1777 */ 1778 fxp_scb_wait(sc); 1779 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1780 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1781 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1782 1783 /* 1784 * Set current media. 1785 */ 1786 if (sc->miibus != NULL) 1787 mii_mediachg(device_get_softc(sc->miibus)); 1788 1789 ifp->if_flags |= IFF_RUNNING; 1790 ifp->if_flags &= ~IFF_OACTIVE; 1791 1792 /* 1793 * Enable interrupts. 1794 */ 1795#ifdef DEVICE_POLLING 1796 /* 1797 * ... but only do that if we are not polling. And because (presumably) 1798 * the default is interrupts on, we need to disable them explicitly! 1799 */ 1800 if ( ifp->if_flags & IFF_POLLING ) 1801 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1802 else 1803#endif /* DEVICE_POLLING */ 1804 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1805 splx(s); 1806 1807 /* 1808 * Start stats updater. 1809 */ 1810 sc->stat_ch = timeout(fxp_tick, sc, hz); 1811} 1812 1813static int 1814fxp_serial_ifmedia_upd(struct ifnet *ifp) 1815{ 1816 1817 return (0); 1818} 1819 1820static void 1821fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1822{ 1823 1824 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1825} 1826 1827/* 1828 * Change media according to request. 1829 */ 1830static int 1831fxp_ifmedia_upd(struct ifnet *ifp) 1832{ 1833 struct fxp_softc *sc = ifp->if_softc; 1834 struct mii_data *mii; 1835 1836 mii = device_get_softc(sc->miibus); 1837 mii_mediachg(mii); 1838 return (0); 1839} 1840 1841/* 1842 * Notify the world which media we're using. 1843 */ 1844static void 1845fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1846{ 1847 struct fxp_softc *sc = ifp->if_softc; 1848 struct mii_data *mii; 1849 1850 mii = device_get_softc(sc->miibus); 1851 mii_pollstat(mii); 1852 ifmr->ifm_active = mii->mii_media_active; 1853 ifmr->ifm_status = mii->mii_media_status; 1854 1855 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1856 sc->cu_resume_bug = 1; 1857 else 1858 sc->cu_resume_bug = 0; 1859} 1860 1861/* 1862 * Add a buffer to the end of the RFA buffer list. 1863 * Return 0 if successful, 1 for failure. A failure results in 1864 * adding the 'oldm' (if non-NULL) on to the end of the list - 1865 * tossing out its old contents and recycling it. 1866 * The RFA struct is stuck at the beginning of mbuf cluster and the 1867 * data pointer is fixed up to point just past it. 1868 */ 1869static int 1870fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1871{ 1872 u_int32_t v; 1873 struct mbuf *m; 1874 struct fxp_rfa *rfa, *p_rfa; 1875 1876 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1877 if (m == NULL) { /* try to recycle the old mbuf instead */ 1878 if (oldm == NULL) 1879 return 1; 1880 m = oldm; 1881 m->m_data = m->m_ext.ext_buf; 1882 } 1883 1884 /* 1885 * Move the data pointer up so that the incoming data packet 1886 * will be 32-bit aligned. 1887 */ 1888 m->m_data += RFA_ALIGNMENT_FUDGE; 1889 1890 /* 1891 * Get a pointer to the base of the mbuf cluster and move 1892 * data start past it. 1893 */ 1894 rfa = mtod(m, struct fxp_rfa *); 1895 m->m_data += sizeof(struct fxp_rfa); 1896 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1897 1898 /* 1899 * Initialize the rest of the RFA. Note that since the RFA 1900 * is misaligned, we cannot store values directly. Instead, 1901 * we use an optimized, inline copy. 1902 */ 1903 1904 rfa->rfa_status = 0; 1905 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1906 rfa->actual_size = 0; 1907 1908 v = -1; 1909 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1910 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1911 1912 /* 1913 * If there are other buffers already on the list, attach this 1914 * one to the end by fixing up the tail to point to this one. 1915 */ 1916 if (sc->rfa_headm != NULL) { 1917 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1918 RFA_ALIGNMENT_FUDGE); 1919 sc->rfa_tailm->m_next = m; 1920 v = vtophys(rfa); 1921 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1922 p_rfa->rfa_control = 0; 1923 } else { 1924 sc->rfa_headm = m; 1925 } 1926 sc->rfa_tailm = m; 1927 1928 return (m == oldm); 1929} 1930 1931static volatile int 1932fxp_miibus_readreg(device_t dev, int phy, int reg) 1933{ 1934 struct fxp_softc *sc = device_get_softc(dev); 1935 int count = 10000; 1936 int value; 1937 1938 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1939 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1940 1941 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1942 && count--) 1943 DELAY(10); 1944 1945 if (count <= 0) 1946 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1947 1948 return (value & 0xffff); 1949} 1950 1951static void 1952fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1953{ 1954 struct fxp_softc *sc = device_get_softc(dev); 1955 int count = 10000; 1956 1957 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1958 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1959 (value & 0xffff)); 1960 1961 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1962 count--) 1963 DELAY(10); 1964 1965 if (count <= 0) 1966 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1967} 1968 1969static int 1970fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1971{ 1972 struct fxp_softc *sc = ifp->if_softc; 1973 struct ifreq *ifr = (struct ifreq *)data; 1974 struct mii_data *mii; 1975 int s, error = 0; 1976 1977 s = splimp(); 1978 1979 switch (command) { 1980 case SIOCSIFFLAGS: 1981 if (ifp->if_flags & IFF_ALLMULTI) 1982 sc->flags |= FXP_FLAG_ALL_MCAST; 1983 else 1984 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1985 1986 /* 1987 * If interface is marked up and not running, then start it. 1988 * If it is marked down and running, stop it. 1989 * XXX If it's up then re-initialize it. This is so flags 1990 * such as IFF_PROMISC are handled. 1991 */ 1992 if (ifp->if_flags & IFF_UP) { 1993 fxp_init(sc); 1994 } else { 1995 if (ifp->if_flags & IFF_RUNNING) 1996 fxp_stop(sc); 1997 } 1998 break; 1999 2000 case SIOCADDMULTI: 2001 case SIOCDELMULTI: 2002 if (ifp->if_flags & IFF_ALLMULTI) 2003 sc->flags |= FXP_FLAG_ALL_MCAST; 2004 else 2005 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2006 /* 2007 * Multicast list has changed; set the hardware filter 2008 * accordingly. 2009 */ 2010 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2011 fxp_mc_setup(sc); 2012 /* 2013 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2014 * again rather than else {}. 2015 */ 2016 if (sc->flags & FXP_FLAG_ALL_MCAST) 2017 fxp_init(sc); 2018 error = 0; 2019 break; 2020 2021 case SIOCSIFMEDIA: 2022 case SIOCGIFMEDIA: 2023 if (sc->miibus != NULL) { 2024 mii = device_get_softc(sc->miibus); 2025 error = ifmedia_ioctl(ifp, ifr, 2026 &mii->mii_media, command); 2027 } else { 2028 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2029 } 2030 break; 2031 2032 default: 2033 error = ether_ioctl(ifp, command, data); 2034 } 2035 splx(s); 2036 return (error); 2037} 2038 2039/* 2040 * Fill in the multicast address list and return number of entries. 2041 */ 2042static int 2043fxp_mc_addrs(struct fxp_softc *sc) 2044{ 2045 struct fxp_cb_mcs *mcsp = sc->mcsp; 2046 struct ifnet *ifp = &sc->sc_if; 2047 struct ifmultiaddr *ifma; 2048 int nmcasts; 2049 2050 nmcasts = 0; 2051 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2052#if __FreeBSD_version < 500000 2053 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2054#else 2055 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2056#endif 2057 if (ifma->ifma_addr->sa_family != AF_LINK) 2058 continue; 2059 if (nmcasts >= MAXMCADDR) { 2060 sc->flags |= FXP_FLAG_ALL_MCAST; 2061 nmcasts = 0; 2062 break; 2063 } 2064 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2065 (void *)(uintptr_t)(volatile void *) 2066 &sc->mcsp->mc_addr[nmcasts][0], 6); 2067 nmcasts++; 2068 } 2069 } 2070 mcsp->mc_cnt = nmcasts * 6; 2071 return (nmcasts); 2072} 2073 2074/* 2075 * Program the multicast filter. 2076 * 2077 * We have an artificial restriction that the multicast setup command 2078 * must be the first command in the chain, so we take steps to ensure 2079 * this. By requiring this, it allows us to keep up the performance of 2080 * the pre-initialized command ring (esp. link pointers) by not actually 2081 * inserting the mcsetup command in the ring - i.e. its link pointer 2082 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2083 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2084 * lead into the regular TxCB ring when it completes. 2085 * 2086 * This function must be called at splimp. 2087 */ 2088static void 2089fxp_mc_setup(struct fxp_softc *sc) 2090{ 2091 struct fxp_cb_mcs *mcsp = sc->mcsp; 2092 struct ifnet *ifp = &sc->sc_if; 2093 int count; 2094 2095 /* 2096 * If there are queued commands, we must wait until they are all 2097 * completed. If we are already waiting, then add a NOP command 2098 * with interrupt option so that we're notified when all commands 2099 * have been completed - fxp_start() ensures that no additional 2100 * TX commands will be added when need_mcsetup is true. 2101 */ 2102 if (sc->tx_queued) { 2103 struct fxp_cb_tx *txp; 2104 2105 /* 2106 * need_mcsetup will be true if we are already waiting for the 2107 * NOP command to be completed (see below). In this case, bail. 2108 */ 2109 if (sc->need_mcsetup) 2110 return; 2111 sc->need_mcsetup = 1; 2112 2113 /* 2114 * Add a NOP command with interrupt so that we are notified 2115 * when all TX commands have been processed. 2116 */ 2117 txp = sc->cbl_last->next; 2118 txp->mb_head = NULL; 2119 txp->cb_status = 0; 2120 txp->cb_command = FXP_CB_COMMAND_NOP | 2121 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2122 /* 2123 * Advance the end of list forward. 2124 */ 2125 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2126 sc->cbl_last = txp; 2127 sc->tx_queued++; 2128 /* 2129 * Issue a resume in case the CU has just suspended. 2130 */ 2131 fxp_scb_wait(sc); 2132 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2133 /* 2134 * Set a 5 second timer just in case we don't hear from the 2135 * card again. 2136 */ 2137 ifp->if_timer = 5; 2138 2139 return; 2140 } 2141 sc->need_mcsetup = 0; 2142 2143 /* 2144 * Initialize multicast setup descriptor. 2145 */ 2146 mcsp->next = sc->cbl_base; 2147 mcsp->mb_head = NULL; 2148 mcsp->cb_status = 0; 2149 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2150 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2151 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2152 (void) fxp_mc_addrs(sc); 2153 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2154 sc->tx_queued = 1; 2155 2156 /* 2157 * Wait until command unit is not active. This should never 2158 * be the case when nothing is queued, but make sure anyway. 2159 */ 2160 count = 100; 2161 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2162 FXP_SCB_CUS_ACTIVE && --count) 2163 DELAY(10); 2164 if (count == 0) { 2165 device_printf(sc->dev, "command queue timeout\n"); 2166 return; 2167 } 2168 2169 /* 2170 * Start the multicast setup command. 2171 */ 2172 fxp_scb_wait(sc); 2173 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2174 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2175 2176 ifp->if_timer = 2; 2177 return; 2178} 2179 2180static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2181static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2182static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2183static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2184static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2185static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2186 2187#define UCODE(x) x, sizeof(x) 2188 2189struct ucode { 2190 u_int32_t revision; 2191 u_int32_t *ucode; 2192 int length; 2193 u_short int_delay_offset; 2194 u_short bundle_max_offset; 2195} ucode_table[] = { 2196 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2197 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2198 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2199 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2201 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2202 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2203 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2204 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2205 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2206 { 0, NULL, 0, 0, 0 } 2207}; 2208 2209static void 2210fxp_load_ucode(struct fxp_softc *sc) 2211{ 2212 struct ucode *uc; 2213 struct fxp_cb_ucode *cbp; 2214 2215 for (uc = ucode_table; uc->ucode != NULL; uc++) 2216 if (sc->revision == uc->revision) 2217 break; 2218 if (uc->ucode == NULL) 2219 return; 2220 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2221 cbp->cb_status = 0; 2222 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2223 cbp->link_addr = -1; /* (no) next command */ 2224 memcpy(cbp->ucode, uc->ucode, uc->length); 2225 if (uc->int_delay_offset) 2226 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2227 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2228 if (uc->bundle_max_offset) 2229 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2230 sc->tunable_bundle_max; 2231 /* 2232 * Download the ucode to the chip. 2233 */ 2234 fxp_scb_wait(sc); 2235 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2236 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2237 /* ...and wait for it to complete. */ 2238 fxp_dma_wait(&cbp->cb_status, sc); 2239 device_printf(sc->dev, 2240 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2241 sc->tunable_int_delay, 2242 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2243 sc->flags |= FXP_FLAG_UCODE; 2244} 2245 2246static int 2247sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2248{ 2249 int error, value; 2250 2251 value = *(int *)arg1; 2252 error = sysctl_handle_int(oidp, &value, 0, req); 2253 if (error || !req->newptr) 2254 return (error); 2255 if (value < low || value > high) 2256 return (EINVAL); 2257 *(int *)arg1 = value; 2258 return (0); 2259} 2260 2261/* 2262 * Interrupt delay is expressed in microseconds, a multiplier is used 2263 * to convert this to the appropriate clock ticks before using. 2264 */ 2265static int 2266sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2267{ 2268 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2269} 2270 2271static int 2272sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2273{ 2274 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2275} 2276