if_fxp.c revision 106554
11592Srgrimes/*- 250476Speter * Copyright (c) 1995, David Greenman 31592Srgrimes * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 441051Sdima * All rights reserved. 553909Speter * 653909Speter * Redistribution and use in source and binary forms, with or without 753909Speter * modification, are permitted provided that the following conditions 853909Speter * are met: 953909Speter * 1. Redistributions of source code must retain the above copyright 1053909Speter * notice unmodified, this list of conditions, and the following 1153909Speter * disclaimer. 1253909Speter * 2. Redistributions in binary form must reproduce the above copyright 1353909Speter * notice, this list of conditions and the following disclaimer in the 1453909Speter * documentation and/or other materials provided with the distribution. 1553909Speter * 1653909Speter * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1753909Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1853909Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1953909Speter * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2053909Speter * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2153909Speter * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2253909Speter * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2353909Speter * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2453909Speter * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2553909Speter * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2653909Speter * SUCH DAMAGE. 2753909Speter * 2853909Speter * $FreeBSD: head/sys/dev/fxp/if_fxp.c 106554 2002-11-07 16:04:07Z iedowse $ 2953909Speter */ 301592Srgrimes 3153909Speter/* 3253909Speter * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 3353909Speter */ 3453909Speter 3538101Speter#include <sys/param.h> 3638101Speter#include <sys/systm.h> 3738101Speter#include <sys/mbuf.h> 3838101Speter#include <sys/malloc.h> 3938632Sjb /* #include <sys/mutex.h> */ 4036932Speter#include <sys/kernel.h> 4136923Speter#include <sys/socket.h> 4238823Sjb#include <sys/sysctl.h> 4338632Sjb 4434195Sjdp#include <net/if.h> 4534195Sjdp#include <net/if_dl.h> 4634195Sjdp#include <net/if_media.h> 4751995Smarkm 4814078Sjoerg#ifdef NS 4914078Sjoerg#include <netns/ns.h> 5014078Sjoerg#include <netns/ns_if.h> 519962Smarkm#endif 521592Srgrimes 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <net/ethernet.h> 61#include <net/if_arp.h> 62 63#include <vm/vm.h> /* for vtophys */ 64#include <vm/pmap.h> /* for vtophys */ 65#include <machine/clock.h> /* for DELAY */ 66 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73#include <dev/mii/mii.h> 74#include <dev/mii/miivar.h> 75 76#include <dev/fxp/if_fxpreg.h> 77#include <dev/fxp/if_fxpvar.h> 78#include <dev/fxp/rcvbundl.h> 79 80MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81#include "miibus_if.h" 82 83/* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92#define RFA_ALIGNMENT_FUDGE 2 93 94/* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99static int tx_threshold = 64; 100 101/* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135}; 136 137struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140}; 141 142/* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0x1039, "Intel Pro/100 Ethernet" }, 163 { 0x103A, "Intel Pro/100 Ethernet" }, 164 { 0x103B, "Intel Pro/100 Ethernet" }, 165 { 0x103C, "Intel Pro/100 Ethernet" }, 166 { 0x103D, "Intel Pro/100 Ethernet" }, 167 { 0x103E, "Intel Pro/100 Ethernet" }, 168 { 0, NULL }, 169}; 170 171static int fxp_probe(device_t dev); 172static int fxp_attach(device_t dev); 173static int fxp_detach(device_t dev); 174static int fxp_shutdown(device_t dev); 175static int fxp_suspend(device_t dev); 176static int fxp_resume(device_t dev); 177 178static void fxp_intr(void *xsc); 179static void fxp_init(void *xsc); 180static void fxp_tick(void *xsc); 181static void fxp_powerstate_d0(device_t dev); 182static void fxp_start(struct ifnet *ifp); 183static void fxp_stop(struct fxp_softc *sc); 184static void fxp_release(struct fxp_softc *sc); 185static int fxp_ioctl(struct ifnet *ifp, u_long command, 186 caddr_t data); 187static void fxp_watchdog(struct ifnet *ifp); 188static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 189static int fxp_mc_addrs(struct fxp_softc *sc); 190static void fxp_mc_setup(struct fxp_softc *sc); 191static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 192 int autosize); 193static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 194 u_int16_t data); 195static void fxp_autosize_eeprom(struct fxp_softc *sc); 196static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 197 int offset, int words); 198static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 199 int offset, int words); 200static int fxp_ifmedia_upd(struct ifnet *ifp); 201static void fxp_ifmedia_sts(struct ifnet *ifp, 202 struct ifmediareq *ifmr); 203static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 204static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 205 struct ifmediareq *ifmr); 206static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 207static void fxp_miibus_writereg(device_t dev, int phy, int reg, 208 int value); 209static void fxp_load_ucode(struct fxp_softc *sc); 210static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 211 int low, int high); 212static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 213static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 214static __inline void fxp_lwcopy(volatile u_int32_t *src, 215 volatile u_int32_t *dst); 216static __inline void fxp_scb_wait(struct fxp_softc *sc); 217static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 218static __inline void fxp_dma_wait(volatile u_int16_t *status, 219 struct fxp_softc *sc); 220 221static device_method_t fxp_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, fxp_probe), 224 DEVMETHOD(device_attach, fxp_attach), 225 DEVMETHOD(device_detach, fxp_detach), 226 DEVMETHOD(device_shutdown, fxp_shutdown), 227 DEVMETHOD(device_suspend, fxp_suspend), 228 DEVMETHOD(device_resume, fxp_resume), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 232 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 233 234 { 0, 0 } 235}; 236 237static driver_t fxp_driver = { 238 "fxp", 239 fxp_methods, 240 sizeof(struct fxp_softc), 241}; 242 243static devclass_t fxp_devclass; 244 245DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 246DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 247DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 248 249static int fxp_rnr; 250SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 251 252/* 253 * Inline function to copy a 16-bit aligned 32-bit quantity. 254 */ 255static __inline void 256fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 257{ 258#ifdef __i386__ 259 *dst = *src; 260#else 261 volatile u_int16_t *a = (volatile u_int16_t *)src; 262 volatile u_int16_t *b = (volatile u_int16_t *)dst; 263 264 b[0] = a[0]; 265 b[1] = a[1]; 266#endif 267} 268 269/* 270 * Wait for the previous command to be accepted (but not necessarily 271 * completed). 272 */ 273static __inline void 274fxp_scb_wait(struct fxp_softc *sc) 275{ 276 int i = 10000; 277 278 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 279 DELAY(2); 280 if (i == 0) 281 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 282 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 283 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 284 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 285 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 286} 287 288static __inline void 289fxp_scb_cmd(struct fxp_softc *sc, int cmd) 290{ 291 292 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 293 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 294 fxp_scb_wait(sc); 295 } 296 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 297} 298 299static __inline void 300fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 301{ 302 int i = 10000; 303 304 while (!(*status & FXP_CB_STATUS_C) && --i) 305 DELAY(2); 306 if (i == 0) 307 device_printf(sc->dev, "DMA timeout\n"); 308} 309 310/* 311 * Return identification string if this is device is ours. 312 */ 313static int 314fxp_probe(device_t dev) 315{ 316 u_int16_t devid; 317 struct fxp_ident *ident; 318 319 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 320 devid = pci_get_device(dev); 321 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 322 if (ident->devid == devid) { 323 device_set_desc(dev, ident->name); 324 return (0); 325 } 326 } 327 } 328 return (ENXIO); 329} 330 331static void 332fxp_powerstate_d0(device_t dev) 333{ 334#if __FreeBSD_version >= 430002 335 u_int32_t iobase, membase, irq; 336 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 /* Save important PCI config data. */ 339 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 340 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 341 irq = pci_read_config(dev, PCIR_INTLINE, 4); 342 343 /* Reset the power state. */ 344 device_printf(dev, "chip is in D%d power mode " 345 "-- setting to D0\n", pci_get_powerstate(dev)); 346 347 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 348 349 /* Restore PCI config data. */ 350 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 351 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 352 pci_write_config(dev, PCIR_INTLINE, irq, 4); 353 } 354#endif 355} 356 357static int 358fxp_attach(device_t dev) 359{ 360 int error = 0; 361 struct fxp_softc *sc = device_get_softc(dev); 362 struct ifnet *ifp; 363 u_int32_t val; 364 u_int16_t data; 365 int i, rid, m1, m2, prefer_iomap; 366 int s; 367 368 bzero(sc, sizeof(*sc)); 369 sc->dev = dev; 370 callout_handle_init(&sc->stat_ch); 371 sysctl_ctx_init(&sc->sysctl_ctx); 372 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 373 MTX_DEF | MTX_RECURSE); 374 375 s = splimp(); 376 377 /* 378 * Enable bus mastering. Enable memory space too, in case 379 * BIOS/Prom forgot about it. 380 */ 381 val = pci_read_config(dev, PCIR_COMMAND, 2); 382 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 383 pci_write_config(dev, PCIR_COMMAND, val, 2); 384 val = pci_read_config(dev, PCIR_COMMAND, 2); 385 386 fxp_powerstate_d0(dev); 387 388 /* 389 * Figure out which we should try first - memory mapping or i/o mapping? 390 * We default to memory mapping. Then we accept an override from the 391 * command line. Then we check to see which one is enabled. 392 */ 393 m1 = PCIM_CMD_MEMEN; 394 m2 = PCIM_CMD_PORTEN; 395 prefer_iomap = 0; 396 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 397 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 398 m1 = PCIM_CMD_PORTEN; 399 m2 = PCIM_CMD_MEMEN; 400 } 401 402 if (val & m1) { 403 sc->rtp = 404 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 405 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 406 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 407 0, ~0, 1, RF_ACTIVE); 408 } 409 if (sc->mem == NULL && (val & m2)) { 410 sc->rtp = 411 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 413 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 414 0, ~0, 1, RF_ACTIVE); 415 } 416 417 if (!sc->mem) { 418 device_printf(dev, "could not map device registers\n"); 419 error = ENXIO; 420 goto fail; 421 } 422 if (bootverbose) { 423 device_printf(dev, "using %s space register mapping\n", 424 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 425 } 426 427 sc->sc_st = rman_get_bustag(sc->mem); 428 sc->sc_sh = rman_get_bushandle(sc->mem); 429 430 /* 431 * Allocate our interrupt. 432 */ 433 rid = 0; 434 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 435 RF_SHAREABLE | RF_ACTIVE); 436 if (sc->irq == NULL) { 437 device_printf(dev, "could not map interrupt\n"); 438 error = ENXIO; 439 goto fail; 440 } 441 442 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 443 fxp_intr, sc, &sc->ih); 444 if (error) { 445 device_printf(dev, "could not setup irq\n"); 446 goto fail; 447 } 448 449 /* 450 * Reset to a stable state. 451 */ 452 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 453 DELAY(10); 454 455 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 456 M_DEVBUF, M_NOWAIT | M_ZERO); 457 if (sc->cbl_base == NULL) 458 goto failmem; 459 460 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 461 M_NOWAIT | M_ZERO); 462 if (sc->fxp_stats == NULL) 463 goto failmem; 464 465 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 466 if (sc->mcsp == NULL) 467 goto failmem; 468 469 /* 470 * Pre-allocate our receive buffers. 471 */ 472 for (i = 0; i < FXP_NRFABUFS; i++) { 473 if (fxp_add_rfabuf(sc, NULL) != 0) { 474 goto failmem; 475 } 476 } 477 478 /* 479 * Find out how large of an SEEPROM we have. 480 */ 481 fxp_autosize_eeprom(sc); 482 483 /* 484 * Determine whether we must use the 503 serial interface. 485 */ 486 fxp_read_eeprom(sc, &data, 6, 1); 487 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 488 (data & FXP_PHY_SERIAL_ONLY)) 489 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 490 491 /* 492 * Create the sysctl tree 493 */ 494 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 495 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 496 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 497 if (sc->sysctl_tree == NULL) 498 goto fail; 499 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 500 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 501 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 502 "FXP driver receive interrupt microcode bundling delay"); 503 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 504 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 505 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 506 "FXP driver receive interrupt microcode bundle size limit"); 507 508 /* 509 * Pull in device tunables. 510 */ 511 sc->tunable_int_delay = TUNABLE_INT_DELAY; 512 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 513 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 514 "int_delay", &sc->tunable_int_delay); 515 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 516 "bundle_max", &sc->tunable_bundle_max); 517 518 /* 519 * Find out the chip revision; lump all 82557 revs together. 520 */ 521 fxp_read_eeprom(sc, &data, 5, 1); 522 if ((data >> 8) == 1) 523 sc->revision = FXP_REV_82557; 524 else 525 sc->revision = pci_get_revid(dev); 526 527 /* 528 * Enable workarounds for certain chip revision deficiencies. 529 * 530 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 531 * some systems based a normal 82559 design, have a defect where 532 * the chip can cause a PCI protocol violation if it receives 533 * a CU_RESUME command when it is entering the IDLE state. The 534 * workaround is to disable Dynamic Standby Mode, so the chip never 535 * deasserts CLKRUN#, and always remains in an active state. 536 * 537 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 538 */ 539 i = pci_get_device(dev); 540 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 541 sc->revision >= FXP_REV_82559_A0) { 542 fxp_read_eeprom(sc, &data, 10, 1); 543 if (data & 0x02) { /* STB enable */ 544 u_int16_t cksum; 545 int i; 546 547 device_printf(dev, 548 "Disabling dynamic standby mode in EEPROM\n"); 549 data &= ~0x02; 550 fxp_write_eeprom(sc, &data, 10, 1); 551 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 552 cksum = 0; 553 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 554 fxp_read_eeprom(sc, &data, i, 1); 555 cksum += data; 556 } 557 i = (1 << sc->eeprom_size) - 1; 558 cksum = 0xBABA - cksum; 559 fxp_read_eeprom(sc, &data, i, 1); 560 fxp_write_eeprom(sc, &cksum, i, 1); 561 device_printf(dev, 562 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 563 i, data, cksum); 564#if 1 565 /* 566 * If the user elects to continue, try the software 567 * workaround, as it is better than nothing. 568 */ 569 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 570#endif 571 } 572 } 573 574 /* 575 * If we are not a 82557 chip, we can enable extended features. 576 */ 577 if (sc->revision != FXP_REV_82557) { 578 /* 579 * If MWI is enabled in the PCI configuration, and there 580 * is a valid cacheline size (8 or 16 dwords), then tell 581 * the board to turn on MWI. 582 */ 583 if (val & PCIM_CMD_MWRICEN && 584 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 585 sc->flags |= FXP_FLAG_MWI_ENABLE; 586 587 /* turn on the extended TxCB feature */ 588 sc->flags |= FXP_FLAG_EXT_TXCB; 589 590 /* enable reception of long frames for VLAN */ 591 sc->flags |= FXP_FLAG_LONG_PKT_EN; 592 } 593 594 /* 595 * Read MAC address. 596 */ 597 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 598 device_printf(dev, "Ethernet address %6D%s\n", 599 sc->arpcom.ac_enaddr, ":", 600 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 601 if (bootverbose) { 602 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 603 pci_get_vendor(dev), pci_get_device(dev), 604 pci_get_subvendor(dev), pci_get_subdevice(dev), 605 pci_get_revid(dev)); 606 fxp_read_eeprom(sc, &data, 10, 1); 607 device_printf(dev, "Dynamic Standby mode is %s\n", 608 data & 0x02 ? "enabled" : "disabled"); 609 } 610 611 /* 612 * If this is only a 10Mbps device, then there is no MII, and 613 * the PHY will use a serial interface instead. 614 * 615 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 616 * doesn't have a programming interface of any sort. The 617 * media is sensed automatically based on how the link partner 618 * is configured. This is, in essence, manual configuration. 619 */ 620 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 621 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 622 fxp_serial_ifmedia_sts); 623 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 624 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 625 } else { 626 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 627 fxp_ifmedia_sts)) { 628 device_printf(dev, "MII without any PHY!\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 } 633 634 ifp = &sc->arpcom.ac_if; 635 ifp->if_unit = device_get_unit(dev); 636 ifp->if_name = "fxp"; 637 ifp->if_output = ether_output; 638 ifp->if_baudrate = 100000000; 639 ifp->if_init = fxp_init; 640 ifp->if_softc = sc; 641 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 642 ifp->if_ioctl = fxp_ioctl; 643 ifp->if_start = fxp_start; 644 ifp->if_watchdog = fxp_watchdog; 645 646 /* 647 * Attach the interface. 648 */ 649 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 650 651 /* 652 * Tell the upper layer(s) we support long frames. 653 */ 654 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 655 656 /* 657 * Let the system queue as many packets as we have available 658 * TX descriptors. 659 */ 660 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 661 662 splx(s); 663 return (0); 664 665failmem: 666 device_printf(dev, "Failed to malloc memory\n"); 667 error = ENOMEM; 668fail: 669 splx(s); 670 fxp_release(sc); 671 return (error); 672} 673 674/* 675 * release all resources 676 */ 677static void 678fxp_release(struct fxp_softc *sc) 679{ 680 681 bus_generic_detach(sc->dev); 682 if (sc->miibus) 683 device_delete_child(sc->dev, sc->miibus); 684 685 if (sc->cbl_base) 686 free(sc->cbl_base, M_DEVBUF); 687 if (sc->fxp_stats) 688 free(sc->fxp_stats, M_DEVBUF); 689 if (sc->mcsp) 690 free(sc->mcsp, M_DEVBUF); 691 if (sc->rfa_headm) 692 m_freem(sc->rfa_headm); 693 694 if (sc->ih) 695 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 696 if (sc->irq) 697 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 698 if (sc->mem) 699 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 700 701 sysctl_ctx_free(&sc->sysctl_ctx); 702 703 mtx_destroy(&sc->sc_mtx); 704} 705 706/* 707 * Detach interface. 708 */ 709static int 710fxp_detach(device_t dev) 711{ 712 struct fxp_softc *sc = device_get_softc(dev); 713 int s; 714 715 /* disable interrupts */ 716 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 717 718 s = splimp(); 719 720 /* 721 * Stop DMA and drop transmit queue. 722 */ 723 fxp_stop(sc); 724 725 /* 726 * Close down routes etc. 727 */ 728 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 729 730 /* 731 * Free all media structures. 732 */ 733 ifmedia_removeall(&sc->sc_media); 734 735 splx(s); 736 737 /* Release our allocated resources. */ 738 fxp_release(sc); 739 740 return (0); 741} 742 743/* 744 * Device shutdown routine. Called at system shutdown after sync. The 745 * main purpose of this routine is to shut off receiver DMA so that 746 * kernel memory doesn't get clobbered during warmboot. 747 */ 748static int 749fxp_shutdown(device_t dev) 750{ 751 /* 752 * Make sure that DMA is disabled prior to reboot. Not doing 753 * do could allow DMA to corrupt kernel memory during the 754 * reboot before the driver initializes. 755 */ 756 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 757 return (0); 758} 759 760/* 761 * Device suspend routine. Stop the interface and save some PCI 762 * settings in case the BIOS doesn't restore them properly on 763 * resume. 764 */ 765static int 766fxp_suspend(device_t dev) 767{ 768 struct fxp_softc *sc = device_get_softc(dev); 769 int i, s; 770 771 s = splimp(); 772 773 fxp_stop(sc); 774 775 for (i = 0; i < 5; i++) 776 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 777 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 778 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 779 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 780 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 781 782 sc->suspended = 1; 783 784 splx(s); 785 return (0); 786} 787 788/* 789 * Device resume routine. Restore some PCI settings in case the BIOS 790 * doesn't, re-enable busmastering, and restart the interface if 791 * appropriate. 792 */ 793static int 794fxp_resume(device_t dev) 795{ 796 struct fxp_softc *sc = device_get_softc(dev); 797 struct ifnet *ifp = &sc->sc_if; 798 u_int16_t pci_command; 799 int i, s; 800 801 s = splimp(); 802 803 fxp_powerstate_d0(dev); 804 805 /* better way to do this? */ 806 for (i = 0; i < 5; i++) 807 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 808 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 809 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 810 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 811 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 812 813 /* reenable busmastering */ 814 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 815 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 816 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 817 818 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 819 DELAY(10); 820 821 /* reinitialize interface if necessary */ 822 if (ifp->if_flags & IFF_UP) 823 fxp_init(sc); 824 825 sc->suspended = 0; 826 827 splx(s); 828 return (0); 829} 830 831static void 832fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 833{ 834 u_int16_t reg; 835 int x; 836 837 /* 838 * Shift in data. 839 */ 840 for (x = 1 << (length - 1); x; x >>= 1) { 841 if (data & x) 842 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 843 else 844 reg = FXP_EEPROM_EECS; 845 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 846 DELAY(1); 847 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 848 DELAY(1); 849 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 850 DELAY(1); 851 } 852} 853 854/* 855 * Read from the serial EEPROM. Basically, you manually shift in 856 * the read opcode (one bit at a time) and then shift in the address, 857 * and then you shift out the data (all of this one bit at a time). 858 * The word size is 16 bits, so you have to provide the address for 859 * every 16 bits of data. 860 */ 861static u_int16_t 862fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 863{ 864 u_int16_t reg, data; 865 int x; 866 867 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 868 /* 869 * Shift in read opcode. 870 */ 871 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 872 /* 873 * Shift in address. 874 */ 875 data = 0; 876 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 877 if (offset & x) 878 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 879 else 880 reg = FXP_EEPROM_EECS; 881 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 882 DELAY(1); 883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 884 DELAY(1); 885 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 886 DELAY(1); 887 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 888 data++; 889 if (autosize && reg == 0) { 890 sc->eeprom_size = data; 891 break; 892 } 893 } 894 /* 895 * Shift out data. 896 */ 897 data = 0; 898 reg = FXP_EEPROM_EECS; 899 for (x = 1 << 15; x; x >>= 1) { 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 901 DELAY(1); 902 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 903 data |= x; 904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 905 DELAY(1); 906 } 907 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 908 DELAY(1); 909 910 return (data); 911} 912 913static void 914fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 915{ 916 int i; 917 918 /* 919 * Erase/write enable. 920 */ 921 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 922 fxp_eeprom_shiftin(sc, 0x4, 3); 923 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 925 DELAY(1); 926 /* 927 * Shift in write opcode, address, data. 928 */ 929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 930 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 931 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 932 fxp_eeprom_shiftin(sc, data, 16); 933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 934 DELAY(1); 935 /* 936 * Wait for EEPROM to finish up. 937 */ 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 939 DELAY(1); 940 for (i = 0; i < 1000; i++) { 941 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 942 break; 943 DELAY(50); 944 } 945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 946 DELAY(1); 947 /* 948 * Erase/write disable. 949 */ 950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 951 fxp_eeprom_shiftin(sc, 0x4, 3); 952 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 954 DELAY(1); 955} 956 957/* 958 * From NetBSD: 959 * 960 * Figure out EEPROM size. 961 * 962 * 559's can have either 64-word or 256-word EEPROMs, the 558 963 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 964 * talks about the existance of 16 to 256 word EEPROMs. 965 * 966 * The only known sizes are 64 and 256, where the 256 version is used 967 * by CardBus cards to store CIS information. 968 * 969 * The address is shifted in msb-to-lsb, and after the last 970 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 971 * after which follows the actual data. We try to detect this zero, by 972 * probing the data-out bit in the EEPROM control register just after 973 * having shifted in a bit. If the bit is zero, we assume we've 974 * shifted enough address bits. The data-out should be tri-state, 975 * before this, which should translate to a logical one. 976 */ 977static void 978fxp_autosize_eeprom(struct fxp_softc *sc) 979{ 980 981 /* guess maximum size of 256 words */ 982 sc->eeprom_size = 8; 983 984 /* autosize */ 985 (void) fxp_eeprom_getword(sc, 0, 1); 986} 987 988static void 989fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 990{ 991 int i; 992 993 for (i = 0; i < words; i++) 994 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 995} 996 997static void 998fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 999{ 1000 int i; 1001 1002 for (i = 0; i < words; i++) 1003 fxp_eeprom_putword(sc, offset + i, data[i]); 1004} 1005 1006/* 1007 * Start packet transmission on the interface. 1008 */ 1009static void 1010fxp_start(struct ifnet *ifp) 1011{ 1012 struct fxp_softc *sc = ifp->if_softc; 1013 struct fxp_cb_tx *txp; 1014 1015 /* 1016 * See if we need to suspend xmit until the multicast filter 1017 * has been reprogrammed (which can only be done at the head 1018 * of the command chain). 1019 */ 1020 if (sc->need_mcsetup) { 1021 return; 1022 } 1023 1024 txp = NULL; 1025 1026 /* 1027 * We're finished if there is nothing more to add to the list or if 1028 * we're all filled up with buffers to transmit. 1029 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1030 * a NOP command when needed. 1031 */ 1032 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1033 struct mbuf *m, *mb_head; 1034 int segment; 1035 1036 /* 1037 * Grab a packet to transmit. 1038 */ 1039 IF_DEQUEUE(&ifp->if_snd, mb_head); 1040 1041 /* 1042 * Get pointer to next available tx desc. 1043 */ 1044 txp = sc->cbl_last->next; 1045 1046 /* 1047 * Go through each of the mbufs in the chain and initialize 1048 * the transmit buffer descriptors with the physical address 1049 * and size of the mbuf. 1050 */ 1051tbdinit: 1052 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1053 if (m->m_len != 0) { 1054 if (segment == FXP_NTXSEG) 1055 break; 1056 txp->tbd[segment].tb_addr = 1057 vtophys(mtod(m, vm_offset_t)); 1058 txp->tbd[segment].tb_size = m->m_len; 1059 segment++; 1060 } 1061 } 1062 if (m != NULL) { 1063 struct mbuf *mn; 1064 1065 /* 1066 * We ran out of segments. We have to recopy this 1067 * mbuf chain first. Bail out if we can't get the 1068 * new buffers. 1069 */ 1070 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1071 if (mn == NULL) { 1072 m_freem(mb_head); 1073 break; 1074 } 1075 if (mb_head->m_pkthdr.len > MHLEN) { 1076 MCLGET(mn, M_DONTWAIT); 1077 if ((mn->m_flags & M_EXT) == 0) { 1078 m_freem(mn); 1079 m_freem(mb_head); 1080 break; 1081 } 1082 } 1083 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1084 mtod(mn, caddr_t)); 1085 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1086 m_freem(mb_head); 1087 mb_head = mn; 1088 goto tbdinit; 1089 } 1090 1091 txp->tbd_number = segment; 1092 txp->mb_head = mb_head; 1093 txp->cb_status = 0; 1094 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1095 txp->cb_command = 1096 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1097 FXP_CB_COMMAND_S; 1098 } else { 1099 txp->cb_command = 1100 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1101 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1102 /* 1103 * Set a 5 second timer just in case we don't hear 1104 * from the card again. 1105 */ 1106 ifp->if_timer = 5; 1107 } 1108 txp->tx_threshold = tx_threshold; 1109 1110 /* 1111 * Advance the end of list forward. 1112 */ 1113 1114#ifdef __alpha__ 1115 /* 1116 * On platforms which can't access memory in 16-bit 1117 * granularities, we must prevent the card from DMA'ing 1118 * up the status while we update the command field. 1119 * This could cause us to overwrite the completion status. 1120 */ 1121 atomic_clear_short(&sc->cbl_last->cb_command, 1122 FXP_CB_COMMAND_S); 1123#else 1124 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1125#endif /*__alpha__*/ 1126 sc->cbl_last = txp; 1127 1128 /* 1129 * Advance the beginning of the list forward if there are 1130 * no other packets queued (when nothing is queued, cbl_first 1131 * sits on the last TxCB that was sent out). 1132 */ 1133 if (sc->tx_queued == 0) 1134 sc->cbl_first = txp; 1135 1136 sc->tx_queued++; 1137 1138 /* 1139 * Pass packet to bpf if there is a listener. 1140 */ 1141 if (ifp->if_bpf) 1142 bpf_mtap(ifp, mb_head); 1143 } 1144 1145 /* 1146 * We're finished. If we added to the list, issue a RESUME to get DMA 1147 * going again if suspended. 1148 */ 1149 if (txp != NULL) { 1150 fxp_scb_wait(sc); 1151 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1152 } 1153} 1154 1155static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1156 1157#ifdef DEVICE_POLLING 1158static poll_handler_t fxp_poll; 1159 1160static void 1161fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1162{ 1163 struct fxp_softc *sc = ifp->if_softc; 1164 u_int8_t statack; 1165 1166 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1167 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1168 return; 1169 } 1170 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1171 FXP_SCB_STATACK_FR; 1172 if (cmd == POLL_AND_CHECK_STATUS) { 1173 u_int8_t tmp; 1174 1175 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1176 if (tmp == 0xff || tmp == 0) 1177 return; /* nothing to do */ 1178 tmp &= ~statack; 1179 /* ack what we can */ 1180 if (tmp != 0) 1181 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1182 statack |= tmp; 1183 } 1184 fxp_intr_body(sc, statack, count); 1185} 1186#endif /* DEVICE_POLLING */ 1187 1188/* 1189 * Process interface interrupts. 1190 */ 1191static void 1192fxp_intr(void *xsc) 1193{ 1194 struct fxp_softc *sc = xsc; 1195 u_int8_t statack; 1196 1197#ifdef DEVICE_POLLING 1198 struct ifnet *ifp = &sc->sc_if; 1199 1200 if (ifp->if_flags & IFF_POLLING) 1201 return; 1202 if (ether_poll_register(fxp_poll, ifp)) { 1203 /* disable interrupts */ 1204 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1205 fxp_poll(ifp, 0, 1); 1206 return; 1207 } 1208#endif 1209 1210 if (sc->suspended) { 1211 return; 1212 } 1213 1214 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1215 /* 1216 * It should not be possible to have all bits set; the 1217 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1218 * all bits are set, this may indicate that the card has 1219 * been physically ejected, so ignore it. 1220 */ 1221 if (statack == 0xff) 1222 return; 1223 1224 /* 1225 * First ACK all the interrupts in this pass. 1226 */ 1227 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1228 fxp_intr_body(sc, statack, -1); 1229 } 1230} 1231 1232static void 1233fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1234{ 1235 struct ifnet *ifp = &sc->sc_if; 1236 struct mbuf *m; 1237 struct fxp_rfa *rfa; 1238 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1239 1240 if (rnr) 1241 fxp_rnr++; 1242#ifdef DEVICE_POLLING 1243 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1244 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1245 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1246 rnr = 1; 1247 } 1248#endif 1249 1250 /* 1251 * Free any finished transmit mbuf chains. 1252 * 1253 * Handle the CNA event likt a CXTNO event. It used to 1254 * be that this event (control unit not ready) was not 1255 * encountered, but it is now with the SMPng modifications. 1256 * The exact sequence of events that occur when the interface 1257 * is brought up are different now, and if this event 1258 * goes unhandled, the configuration/rxfilter setup sequence 1259 * can stall for several seconds. The result is that no 1260 * packets go out onto the wire for about 5 to 10 seconds 1261 * after the interface is ifconfig'ed for the first time. 1262 */ 1263 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1264 struct fxp_cb_tx *txp; 1265 1266 for (txp = sc->cbl_first; sc->tx_queued && 1267 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1268 txp = txp->next) { 1269 if (txp->mb_head != NULL) { 1270 m_freem(txp->mb_head); 1271 txp->mb_head = NULL; 1272 } 1273 sc->tx_queued--; 1274 } 1275 sc->cbl_first = txp; 1276 ifp->if_timer = 0; 1277 if (sc->tx_queued == 0) { 1278 if (sc->need_mcsetup) 1279 fxp_mc_setup(sc); 1280 } 1281 /* 1282 * Try to start more packets transmitting. 1283 */ 1284 if (ifp->if_snd.ifq_head != NULL) 1285 fxp_start(ifp); 1286 } 1287 1288 /* 1289 * Just return if nothing happened on the receive side. 1290 */ 1291 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1292 return; 1293 1294 /* 1295 * Process receiver interrupts. If a no-resource (RNR) 1296 * condition exists, get whatever packets we can and 1297 * re-start the receiver. 1298 * 1299 * When using polling, we do not process the list to completion, 1300 * so when we get an RNR interrupt we must defer the restart 1301 * until we hit the last buffer with the C bit set. 1302 * If we run out of cycles and rfa_headm has the C bit set, 1303 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1304 * that the info will be used in the subsequent polling cycle. 1305 */ 1306 for (;;) { 1307 m = sc->rfa_headm; 1308 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1309 RFA_ALIGNMENT_FUDGE); 1310 1311#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1312 if (count >= 0 && count-- == 0) { 1313 if (rnr) { 1314 /* Defer RNR processing until the next time. */ 1315 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1316 rnr = 0; 1317 } 1318 break; 1319 } 1320#endif /* DEVICE_POLLING */ 1321 1322 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1323 break; 1324 1325 /* 1326 * Remove first packet from the chain. 1327 */ 1328 sc->rfa_headm = m->m_next; 1329 m->m_next = NULL; 1330 1331 /* 1332 * Add a new buffer to the receive chain. 1333 * If this fails, the old buffer is recycled 1334 * instead. 1335 */ 1336 if (fxp_add_rfabuf(sc, m) == 0) { 1337 int total_len; 1338 1339 /* 1340 * Fetch packet length (the top 2 bits of 1341 * actual_size are flags set by the controller 1342 * upon completion), and drop the packet in case 1343 * of bogus length or CRC errors. 1344 */ 1345 total_len = rfa->actual_size & 0x3fff; 1346 if (total_len < sizeof(struct ether_header) || 1347 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1348 sizeof(struct fxp_rfa) || 1349 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1350 m_freem(m); 1351 continue; 1352 } 1353 1354 m->m_pkthdr.len = m->m_len = total_len; 1355 ether_input(ifp, NULL, m); 1356 } 1357 } 1358 if (rnr) { 1359 fxp_scb_wait(sc); 1360 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1361 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1362 RFA_ALIGNMENT_FUDGE); 1363 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1364 } 1365} 1366 1367/* 1368 * Update packet in/out/collision statistics. The i82557 doesn't 1369 * allow you to access these counters without doing a fairly 1370 * expensive DMA to get _all_ of the statistics it maintains, so 1371 * we do this operation here only once per second. The statistics 1372 * counters in the kernel are updated from the previous dump-stats 1373 * DMA and then a new dump-stats DMA is started. The on-chip 1374 * counters are zeroed when the DMA completes. If we can't start 1375 * the DMA immediately, we don't wait - we just prepare to read 1376 * them again next time. 1377 */ 1378static void 1379fxp_tick(void *xsc) 1380{ 1381 struct fxp_softc *sc = xsc; 1382 struct ifnet *ifp = &sc->sc_if; 1383 struct fxp_stats *sp = sc->fxp_stats; 1384 struct fxp_cb_tx *txp; 1385 int s; 1386 1387 ifp->if_opackets += sp->tx_good; 1388 ifp->if_collisions += sp->tx_total_collisions; 1389 if (sp->rx_good) { 1390 ifp->if_ipackets += sp->rx_good; 1391 sc->rx_idle_secs = 0; 1392 } else { 1393 /* 1394 * Receiver's been idle for another second. 1395 */ 1396 sc->rx_idle_secs++; 1397 } 1398 ifp->if_ierrors += 1399 sp->rx_crc_errors + 1400 sp->rx_alignment_errors + 1401 sp->rx_rnr_errors + 1402 sp->rx_overrun_errors; 1403 /* 1404 * If any transmit underruns occured, bump up the transmit 1405 * threshold by another 512 bytes (64 * 8). 1406 */ 1407 if (sp->tx_underruns) { 1408 ifp->if_oerrors += sp->tx_underruns; 1409 if (tx_threshold < 192) 1410 tx_threshold += 64; 1411 } 1412 s = splimp(); 1413 /* 1414 * Release any xmit buffers that have completed DMA. This isn't 1415 * strictly necessary to do here, but it's advantagous for mbufs 1416 * with external storage to be released in a timely manner rather 1417 * than being defered for a potentially long time. This limits 1418 * the delay to a maximum of one second. 1419 */ 1420 for (txp = sc->cbl_first; sc->tx_queued && 1421 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1422 txp = txp->next) { 1423 if (txp->mb_head != NULL) { 1424 m_freem(txp->mb_head); 1425 txp->mb_head = NULL; 1426 } 1427 sc->tx_queued--; 1428 } 1429 sc->cbl_first = txp; 1430 /* 1431 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1432 * then assume the receiver has locked up and attempt to clear 1433 * the condition by reprogramming the multicast filter. This is 1434 * a work-around for a bug in the 82557 where the receiver locks 1435 * up if it gets certain types of garbage in the syncronization 1436 * bits prior to the packet header. This bug is supposed to only 1437 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1438 * mode as well (perhaps due to a 10/100 speed transition). 1439 */ 1440 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1441 sc->rx_idle_secs = 0; 1442 fxp_mc_setup(sc); 1443 } 1444 /* 1445 * If there is no pending command, start another stats 1446 * dump. Otherwise punt for now. 1447 */ 1448 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1449 /* 1450 * Start another stats dump. 1451 */ 1452 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1453 } else { 1454 /* 1455 * A previous command is still waiting to be accepted. 1456 * Just zero our copy of the stats and wait for the 1457 * next timer event to update them. 1458 */ 1459 sp->tx_good = 0; 1460 sp->tx_underruns = 0; 1461 sp->tx_total_collisions = 0; 1462 1463 sp->rx_good = 0; 1464 sp->rx_crc_errors = 0; 1465 sp->rx_alignment_errors = 0; 1466 sp->rx_rnr_errors = 0; 1467 sp->rx_overrun_errors = 0; 1468 } 1469 if (sc->miibus != NULL) 1470 mii_tick(device_get_softc(sc->miibus)); 1471 splx(s); 1472 /* 1473 * Schedule another timeout one second from now. 1474 */ 1475 sc->stat_ch = timeout(fxp_tick, sc, hz); 1476} 1477 1478/* 1479 * Stop the interface. Cancels the statistics updater and resets 1480 * the interface. 1481 */ 1482static void 1483fxp_stop(struct fxp_softc *sc) 1484{ 1485 struct ifnet *ifp = &sc->sc_if; 1486 struct fxp_cb_tx *txp; 1487 int i; 1488 1489 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1490 ifp->if_timer = 0; 1491 1492#ifdef DEVICE_POLLING 1493 ether_poll_deregister(ifp); 1494#endif 1495 /* 1496 * Cancel stats updater. 1497 */ 1498 untimeout(fxp_tick, sc, sc->stat_ch); 1499 1500 /* 1501 * Issue software reset, which also unloads the microcode. 1502 */ 1503 sc->flags &= ~FXP_FLAG_UCODE; 1504 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1505 DELAY(50); 1506 1507 /* 1508 * Release any xmit buffers. 1509 */ 1510 txp = sc->cbl_base; 1511 if (txp != NULL) { 1512 for (i = 0; i < FXP_NTXCB; i++) { 1513 if (txp[i].mb_head != NULL) { 1514 m_freem(txp[i].mb_head); 1515 txp[i].mb_head = NULL; 1516 } 1517 } 1518 } 1519 sc->tx_queued = 0; 1520 1521 /* 1522 * Free all the receive buffers then reallocate/reinitialize 1523 */ 1524 if (sc->rfa_headm != NULL) 1525 m_freem(sc->rfa_headm); 1526 sc->rfa_headm = NULL; 1527 sc->rfa_tailm = NULL; 1528 for (i = 0; i < FXP_NRFABUFS; i++) { 1529 if (fxp_add_rfabuf(sc, NULL) != 0) { 1530 /* 1531 * This "can't happen" - we're at splimp() 1532 * and we just freed all the buffers we need 1533 * above. 1534 */ 1535 panic("fxp_stop: no buffers!"); 1536 } 1537 } 1538} 1539 1540/* 1541 * Watchdog/transmission transmit timeout handler. Called when a 1542 * transmission is started on the interface, but no interrupt is 1543 * received before the timeout. This usually indicates that the 1544 * card has wedged for some reason. 1545 */ 1546static void 1547fxp_watchdog(struct ifnet *ifp) 1548{ 1549 struct fxp_softc *sc = ifp->if_softc; 1550 1551 device_printf(sc->dev, "device timeout\n"); 1552 ifp->if_oerrors++; 1553 1554 fxp_init(sc); 1555} 1556 1557static void 1558fxp_init(void *xsc) 1559{ 1560 struct fxp_softc *sc = xsc; 1561 struct ifnet *ifp = &sc->sc_if; 1562 struct fxp_cb_config *cbp; 1563 struct fxp_cb_ias *cb_ias; 1564 struct fxp_cb_tx *txp; 1565 struct fxp_cb_mcs *mcsp; 1566 int i, prm, s; 1567 1568 s = splimp(); 1569 /* 1570 * Cancel any pending I/O 1571 */ 1572 fxp_stop(sc); 1573 1574 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1575 1576 /* 1577 * Initialize base of CBL and RFA memory. Loading with zero 1578 * sets it up for regular linear addressing. 1579 */ 1580 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1581 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1582 1583 fxp_scb_wait(sc); 1584 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1585 1586 /* 1587 * Initialize base of dump-stats buffer. 1588 */ 1589 fxp_scb_wait(sc); 1590 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1591 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1592 1593 /* 1594 * Attempt to load microcode if requested. 1595 */ 1596 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1597 fxp_load_ucode(sc); 1598 1599 /* 1600 * Initialize the multicast address list. 1601 */ 1602 if (fxp_mc_addrs(sc)) { 1603 mcsp = sc->mcsp; 1604 mcsp->cb_status = 0; 1605 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1606 mcsp->link_addr = -1; 1607 /* 1608 * Start the multicast setup command. 1609 */ 1610 fxp_scb_wait(sc); 1611 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1612 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1613 /* ...and wait for it to complete. */ 1614 fxp_dma_wait(&mcsp->cb_status, sc); 1615 } 1616 1617 /* 1618 * We temporarily use memory that contains the TxCB list to 1619 * construct the config CB. The TxCB list memory is rebuilt 1620 * later. 1621 */ 1622 cbp = (struct fxp_cb_config *) sc->cbl_base; 1623 1624 /* 1625 * This bcopy is kind of disgusting, but there are a bunch of must be 1626 * zero and must be one bits in this structure and this is the easiest 1627 * way to initialize them all to proper values. 1628 */ 1629 bcopy(fxp_cb_config_template, 1630 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1631 sizeof(fxp_cb_config_template)); 1632 1633 cbp->cb_status = 0; 1634 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1635 cbp->link_addr = -1; /* (no) next command */ 1636 cbp->byte_count = 22; /* (22) bytes to config */ 1637 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1638 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1639 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1640 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1641 cbp->type_enable = 0; /* actually reserved */ 1642 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1643 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1644 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1645 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1646 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1647 cbp->late_scb = 0; /* (don't) defer SCB update */ 1648 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1649 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1650 cbp->ci_int = 1; /* interrupt on CU idle */ 1651 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1652 cbp->ext_stats_dis = 1; /* disable extended counters */ 1653 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1654 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1655 cbp->disc_short_rx = !prm; /* discard short packets */ 1656 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1657 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1658 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1659 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1660 cbp->csma_dis = 0; /* (don't) disable link */ 1661 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1662 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1663 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1664 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1665 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1666 cbp->nsai = 1; /* (don't) disable source addr insert */ 1667 cbp->preamble_length = 2; /* (7 byte) preamble */ 1668 cbp->loopback = 0; /* (don't) loopback */ 1669 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1670 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1671 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1672 cbp->promiscuous = prm; /* promiscuous mode */ 1673 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1674 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1675 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1676 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1677 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1678 1679 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1680 cbp->padding = 1; /* (do) pad short tx packets */ 1681 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1682 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1683 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1684 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1685 /* must set wake_en in PMCSR also */ 1686 cbp->force_fdx = 0; /* (don't) force full duplex */ 1687 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1688 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1689 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1690 1691 if (sc->revision == FXP_REV_82557) { 1692 /* 1693 * The 82557 has no hardware flow control, the values 1694 * below are the defaults for the chip. 1695 */ 1696 cbp->fc_delay_lsb = 0; 1697 cbp->fc_delay_msb = 0x40; 1698 cbp->pri_fc_thresh = 3; 1699 cbp->tx_fc_dis = 0; 1700 cbp->rx_fc_restop = 0; 1701 cbp->rx_fc_restart = 0; 1702 cbp->fc_filter = 0; 1703 cbp->pri_fc_loc = 1; 1704 } else { 1705 cbp->fc_delay_lsb = 0x1f; 1706 cbp->fc_delay_msb = 0x01; 1707 cbp->pri_fc_thresh = 3; 1708 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1709 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1710 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1711 cbp->fc_filter = !prm; /* drop FC frames to host */ 1712 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1713 } 1714 1715 /* 1716 * Start the config command/DMA. 1717 */ 1718 fxp_scb_wait(sc); 1719 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1720 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1721 /* ...and wait for it to complete. */ 1722 fxp_dma_wait(&cbp->cb_status, sc); 1723 1724 /* 1725 * Now initialize the station address. Temporarily use the TxCB 1726 * memory area like we did above for the config CB. 1727 */ 1728 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1729 cb_ias->cb_status = 0; 1730 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1731 cb_ias->link_addr = -1; 1732 bcopy(sc->arpcom.ac_enaddr, 1733 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1734 sizeof(sc->arpcom.ac_enaddr)); 1735 1736 /* 1737 * Start the IAS (Individual Address Setup) command/DMA. 1738 */ 1739 fxp_scb_wait(sc); 1740 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1741 /* ...and wait for it to complete. */ 1742 fxp_dma_wait(&cb_ias->cb_status, sc); 1743 1744 /* 1745 * Initialize transmit control block (TxCB) list. 1746 */ 1747 1748 txp = sc->cbl_base; 1749 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1750 for (i = 0; i < FXP_NTXCB; i++) { 1751 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1752 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1753 txp[i].link_addr = 1754 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1755 if (sc->flags & FXP_FLAG_EXT_TXCB) 1756 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1757 else 1758 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1759 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1760 } 1761 /* 1762 * Set the suspend flag on the first TxCB and start the control 1763 * unit. It will execute the NOP and then suspend. 1764 */ 1765 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1766 sc->cbl_first = sc->cbl_last = txp; 1767 sc->tx_queued = 1; 1768 1769 fxp_scb_wait(sc); 1770 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1771 1772 /* 1773 * Initialize receiver buffer area - RFA. 1774 */ 1775 fxp_scb_wait(sc); 1776 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1777 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1778 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1779 1780 /* 1781 * Set current media. 1782 */ 1783 if (sc->miibus != NULL) 1784 mii_mediachg(device_get_softc(sc->miibus)); 1785 1786 ifp->if_flags |= IFF_RUNNING; 1787 ifp->if_flags &= ~IFF_OACTIVE; 1788 1789 /* 1790 * Enable interrupts. 1791 */ 1792#ifdef DEVICE_POLLING 1793 /* 1794 * ... but only do that if we are not polling. And because (presumably) 1795 * the default is interrupts on, we need to disable them explicitly! 1796 */ 1797 if ( ifp->if_flags & IFF_POLLING ) 1798 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1799 else 1800#endif /* DEVICE_POLLING */ 1801 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1802 splx(s); 1803 1804 /* 1805 * Start stats updater. 1806 */ 1807 sc->stat_ch = timeout(fxp_tick, sc, hz); 1808} 1809 1810static int 1811fxp_serial_ifmedia_upd(struct ifnet *ifp) 1812{ 1813 1814 return (0); 1815} 1816 1817static void 1818fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1819{ 1820 1821 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1822} 1823 1824/* 1825 * Change media according to request. 1826 */ 1827static int 1828fxp_ifmedia_upd(struct ifnet *ifp) 1829{ 1830 struct fxp_softc *sc = ifp->if_softc; 1831 struct mii_data *mii; 1832 1833 mii = device_get_softc(sc->miibus); 1834 mii_mediachg(mii); 1835 return (0); 1836} 1837 1838/* 1839 * Notify the world which media we're using. 1840 */ 1841static void 1842fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1843{ 1844 struct fxp_softc *sc = ifp->if_softc; 1845 struct mii_data *mii; 1846 1847 mii = device_get_softc(sc->miibus); 1848 mii_pollstat(mii); 1849 ifmr->ifm_active = mii->mii_media_active; 1850 ifmr->ifm_status = mii->mii_media_status; 1851 1852 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1853 sc->cu_resume_bug = 1; 1854 else 1855 sc->cu_resume_bug = 0; 1856} 1857 1858/* 1859 * Add a buffer to the end of the RFA buffer list. 1860 * Return 0 if successful, 1 for failure. A failure results in 1861 * adding the 'oldm' (if non-NULL) on to the end of the list - 1862 * tossing out its old contents and recycling it. 1863 * The RFA struct is stuck at the beginning of mbuf cluster and the 1864 * data pointer is fixed up to point just past it. 1865 */ 1866static int 1867fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1868{ 1869 u_int32_t v; 1870 struct mbuf *m; 1871 struct fxp_rfa *rfa, *p_rfa; 1872 1873 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1874 if (m == NULL) { /* try to recycle the old mbuf instead */ 1875 if (oldm == NULL) 1876 return 1; 1877 m = oldm; 1878 m->m_data = m->m_ext.ext_buf; 1879 } 1880 1881 /* 1882 * Move the data pointer up so that the incoming data packet 1883 * will be 32-bit aligned. 1884 */ 1885 m->m_data += RFA_ALIGNMENT_FUDGE; 1886 1887 /* 1888 * Get a pointer to the base of the mbuf cluster and move 1889 * data start past it. 1890 */ 1891 rfa = mtod(m, struct fxp_rfa *); 1892 m->m_data += sizeof(struct fxp_rfa); 1893 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1894 1895 /* 1896 * Initialize the rest of the RFA. Note that since the RFA 1897 * is misaligned, we cannot store values directly. Instead, 1898 * we use an optimized, inline copy. 1899 */ 1900 1901 rfa->rfa_status = 0; 1902 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1903 rfa->actual_size = 0; 1904 1905 v = -1; 1906 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1907 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1908 1909 /* 1910 * If there are other buffers already on the list, attach this 1911 * one to the end by fixing up the tail to point to this one. 1912 */ 1913 if (sc->rfa_headm != NULL) { 1914 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1915 RFA_ALIGNMENT_FUDGE); 1916 sc->rfa_tailm->m_next = m; 1917 v = vtophys(rfa); 1918 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1919 p_rfa->rfa_control = 0; 1920 } else { 1921 sc->rfa_headm = m; 1922 } 1923 sc->rfa_tailm = m; 1924 1925 return (m == oldm); 1926} 1927 1928static volatile int 1929fxp_miibus_readreg(device_t dev, int phy, int reg) 1930{ 1931 struct fxp_softc *sc = device_get_softc(dev); 1932 int count = 10000; 1933 int value; 1934 1935 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1936 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1937 1938 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1939 && count--) 1940 DELAY(10); 1941 1942 if (count <= 0) 1943 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1944 1945 return (value & 0xffff); 1946} 1947 1948static void 1949fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1950{ 1951 struct fxp_softc *sc = device_get_softc(dev); 1952 int count = 10000; 1953 1954 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1955 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1956 (value & 0xffff)); 1957 1958 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1959 count--) 1960 DELAY(10); 1961 1962 if (count <= 0) 1963 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1964} 1965 1966static int 1967fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1968{ 1969 struct fxp_softc *sc = ifp->if_softc; 1970 struct ifreq *ifr = (struct ifreq *)data; 1971 struct mii_data *mii; 1972 int s, error = 0; 1973 1974 s = splimp(); 1975 1976 switch (command) { 1977 case SIOCSIFADDR: 1978 case SIOCGIFADDR: 1979 case SIOCSIFMTU: 1980 error = ether_ioctl(ifp, command, data); 1981 break; 1982 1983 case SIOCSIFFLAGS: 1984 if (ifp->if_flags & IFF_ALLMULTI) 1985 sc->flags |= FXP_FLAG_ALL_MCAST; 1986 else 1987 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1988 1989 /* 1990 * If interface is marked up and not running, then start it. 1991 * If it is marked down and running, stop it. 1992 * XXX If it's up then re-initialize it. This is so flags 1993 * such as IFF_PROMISC are handled. 1994 */ 1995 if (ifp->if_flags & IFF_UP) { 1996 fxp_init(sc); 1997 } else { 1998 if (ifp->if_flags & IFF_RUNNING) 1999 fxp_stop(sc); 2000 } 2001 break; 2002 2003 case SIOCADDMULTI: 2004 case SIOCDELMULTI: 2005 if (ifp->if_flags & IFF_ALLMULTI) 2006 sc->flags |= FXP_FLAG_ALL_MCAST; 2007 else 2008 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2009 /* 2010 * Multicast list has changed; set the hardware filter 2011 * accordingly. 2012 */ 2013 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2014 fxp_mc_setup(sc); 2015 /* 2016 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2017 * again rather than else {}. 2018 */ 2019 if (sc->flags & FXP_FLAG_ALL_MCAST) 2020 fxp_init(sc); 2021 error = 0; 2022 break; 2023 2024 case SIOCSIFMEDIA: 2025 case SIOCGIFMEDIA: 2026 if (sc->miibus != NULL) { 2027 mii = device_get_softc(sc->miibus); 2028 error = ifmedia_ioctl(ifp, ifr, 2029 &mii->mii_media, command); 2030 } else { 2031 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2032 } 2033 break; 2034 2035 default: 2036 error = EINVAL; 2037 } 2038 splx(s); 2039 return (error); 2040} 2041 2042/* 2043 * Fill in the multicast address list and return number of entries. 2044 */ 2045static int 2046fxp_mc_addrs(struct fxp_softc *sc) 2047{ 2048 struct fxp_cb_mcs *mcsp = sc->mcsp; 2049 struct ifnet *ifp = &sc->sc_if; 2050 struct ifmultiaddr *ifma; 2051 int nmcasts; 2052 2053 nmcasts = 0; 2054 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2055#if __FreeBSD_version < 500000 2056 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2057#else 2058 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2059#endif 2060 if (ifma->ifma_addr->sa_family != AF_LINK) 2061 continue; 2062 if (nmcasts >= MAXMCADDR) { 2063 sc->flags |= FXP_FLAG_ALL_MCAST; 2064 nmcasts = 0; 2065 break; 2066 } 2067 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2068 (void *)(uintptr_t)(volatile void *) 2069 &sc->mcsp->mc_addr[nmcasts][0], 6); 2070 nmcasts++; 2071 } 2072 } 2073 mcsp->mc_cnt = nmcasts * 6; 2074 return (nmcasts); 2075} 2076 2077/* 2078 * Program the multicast filter. 2079 * 2080 * We have an artificial restriction that the multicast setup command 2081 * must be the first command in the chain, so we take steps to ensure 2082 * this. By requiring this, it allows us to keep up the performance of 2083 * the pre-initialized command ring (esp. link pointers) by not actually 2084 * inserting the mcsetup command in the ring - i.e. its link pointer 2085 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2086 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2087 * lead into the regular TxCB ring when it completes. 2088 * 2089 * This function must be called at splimp. 2090 */ 2091static void 2092fxp_mc_setup(struct fxp_softc *sc) 2093{ 2094 struct fxp_cb_mcs *mcsp = sc->mcsp; 2095 struct ifnet *ifp = &sc->sc_if; 2096 int count; 2097 2098 /* 2099 * If there are queued commands, we must wait until they are all 2100 * completed. If we are already waiting, then add a NOP command 2101 * with interrupt option so that we're notified when all commands 2102 * have been completed - fxp_start() ensures that no additional 2103 * TX commands will be added when need_mcsetup is true. 2104 */ 2105 if (sc->tx_queued) { 2106 struct fxp_cb_tx *txp; 2107 2108 /* 2109 * need_mcsetup will be true if we are already waiting for the 2110 * NOP command to be completed (see below). In this case, bail. 2111 */ 2112 if (sc->need_mcsetup) 2113 return; 2114 sc->need_mcsetup = 1; 2115 2116 /* 2117 * Add a NOP command with interrupt so that we are notified 2118 * when all TX commands have been processed. 2119 */ 2120 txp = sc->cbl_last->next; 2121 txp->mb_head = NULL; 2122 txp->cb_status = 0; 2123 txp->cb_command = FXP_CB_COMMAND_NOP | 2124 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2125 /* 2126 * Advance the end of list forward. 2127 */ 2128 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2129 sc->cbl_last = txp; 2130 sc->tx_queued++; 2131 /* 2132 * Issue a resume in case the CU has just suspended. 2133 */ 2134 fxp_scb_wait(sc); 2135 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2136 /* 2137 * Set a 5 second timer just in case we don't hear from the 2138 * card again. 2139 */ 2140 ifp->if_timer = 5; 2141 2142 return; 2143 } 2144 sc->need_mcsetup = 0; 2145 2146 /* 2147 * Initialize multicast setup descriptor. 2148 */ 2149 mcsp->next = sc->cbl_base; 2150 mcsp->mb_head = NULL; 2151 mcsp->cb_status = 0; 2152 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2153 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2154 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2155 (void) fxp_mc_addrs(sc); 2156 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2157 sc->tx_queued = 1; 2158 2159 /* 2160 * Wait until command unit is not active. This should never 2161 * be the case when nothing is queued, but make sure anyway. 2162 */ 2163 count = 100; 2164 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2165 FXP_SCB_CUS_ACTIVE && --count) 2166 DELAY(10); 2167 if (count == 0) { 2168 device_printf(sc->dev, "command queue timeout\n"); 2169 return; 2170 } 2171 2172 /* 2173 * Start the multicast setup command. 2174 */ 2175 fxp_scb_wait(sc); 2176 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2177 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2178 2179 ifp->if_timer = 2; 2180 return; 2181} 2182 2183static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2184static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2185static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2186static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2187static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2188static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2189 2190#define UCODE(x) x, sizeof(x) 2191 2192struct ucode { 2193 u_int32_t revision; 2194 u_int32_t *ucode; 2195 int length; 2196 u_short int_delay_offset; 2197 u_short bundle_max_offset; 2198} ucode_table[] = { 2199 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2200 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2201 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2202 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2203 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2204 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2205 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2206 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2207 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2208 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2209 { 0, NULL, 0, 0, 0 } 2210}; 2211 2212static void 2213fxp_load_ucode(struct fxp_softc *sc) 2214{ 2215 struct ucode *uc; 2216 struct fxp_cb_ucode *cbp; 2217 2218 for (uc = ucode_table; uc->ucode != NULL; uc++) 2219 if (sc->revision == uc->revision) 2220 break; 2221 if (uc->ucode == NULL) 2222 return; 2223 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2224 cbp->cb_status = 0; 2225 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2226 cbp->link_addr = -1; /* (no) next command */ 2227 memcpy(cbp->ucode, uc->ucode, uc->length); 2228 if (uc->int_delay_offset) 2229 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2230 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2231 if (uc->bundle_max_offset) 2232 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2233 sc->tunable_bundle_max; 2234 /* 2235 * Download the ucode to the chip. 2236 */ 2237 fxp_scb_wait(sc); 2238 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2239 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2240 /* ...and wait for it to complete. */ 2241 fxp_dma_wait(&cbp->cb_status, sc); 2242 device_printf(sc->dev, 2243 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2244 sc->tunable_int_delay, 2245 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2246 sc->flags |= FXP_FLAG_UCODE; 2247} 2248 2249static int 2250sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2251{ 2252 int error, value; 2253 2254 value = *(int *)arg1; 2255 error = sysctl_handle_int(oidp, &value, 0, req); 2256 if (error || !req->newptr) 2257 return (error); 2258 if (value < low || value > high) 2259 return (EINVAL); 2260 *(int *)arg1 = value; 2261 return (0); 2262} 2263 2264/* 2265 * Interrupt delay is expressed in microseconds, a multiplier is used 2266 * to convert this to the appropriate clock ticks before using. 2267 */ 2268static int 2269sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2270{ 2271 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2272} 2273 2274static int 2275sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2276{ 2277 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2278} 2279