if_fxp.c revision 102052
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 102052 2002-08-18 07:05:00Z sobomax $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/sysctl.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <net/ethernet.h> 61#include <net/if_arp.h> 62 63#include <vm/vm.h> /* for vtophys */ 64#include <vm/pmap.h> /* for vtophys */ 65#include <machine/clock.h> /* for DELAY */ 66 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73#include <dev/mii/mii.h> 74#include <dev/mii/miivar.h> 75 76#include <dev/fxp/if_fxpreg.h> 77#include <dev/fxp/if_fxpvar.h> 78#include <dev/fxp/rcvbundl.h> 79 80MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81#include "miibus_if.h" 82 83/* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92#define RFA_ALIGNMENT_FUDGE 2 93 94/* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99static int tx_threshold = 64; 100 101/* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135}; 136 137struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140}; 141 142/* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0x1039, "Intel Pro/100 Ethernet" }, 163 { 0x103A, "Intel Pro/100 Ethernet" }, 164 { 0, NULL }, 165}; 166 167static int fxp_probe(device_t dev); 168static int fxp_attach(device_t dev); 169static int fxp_detach(device_t dev); 170static int fxp_shutdown(device_t dev); 171static int fxp_suspend(device_t dev); 172static int fxp_resume(device_t dev); 173 174static void fxp_intr(void *xsc); 175static void fxp_init(void *xsc); 176static void fxp_tick(void *xsc); 177static void fxp_powerstate_d0(device_t dev); 178static void fxp_start(struct ifnet *ifp); 179static void fxp_stop(struct fxp_softc *sc); 180static void fxp_release(struct fxp_softc *sc); 181static int fxp_ioctl(struct ifnet *ifp, u_long command, 182 caddr_t data); 183static void fxp_watchdog(struct ifnet *ifp); 184static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 185static int fxp_mc_addrs(struct fxp_softc *sc); 186static void fxp_mc_setup(struct fxp_softc *sc); 187static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 188 int autosize); 189static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 190 u_int16_t data); 191static void fxp_autosize_eeprom(struct fxp_softc *sc); 192static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 193 int offset, int words); 194static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 195 int offset, int words); 196static int fxp_ifmedia_upd(struct ifnet *ifp); 197static void fxp_ifmedia_sts(struct ifnet *ifp, 198 struct ifmediareq *ifmr); 199static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 200static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 201 struct ifmediareq *ifmr); 202static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 203static void fxp_miibus_writereg(device_t dev, int phy, int reg, 204 int value); 205static void fxp_load_ucode(struct fxp_softc *sc); 206static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 207 int low, int high); 208static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 209static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 210static __inline void fxp_lwcopy(volatile u_int32_t *src, 211 volatile u_int32_t *dst); 212static __inline void fxp_scb_wait(struct fxp_softc *sc); 213static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 214static __inline void fxp_dma_wait(volatile u_int16_t *status, 215 struct fxp_softc *sc); 216 217static device_method_t fxp_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, fxp_probe), 220 DEVMETHOD(device_attach, fxp_attach), 221 DEVMETHOD(device_detach, fxp_detach), 222 DEVMETHOD(device_shutdown, fxp_shutdown), 223 DEVMETHOD(device_suspend, fxp_suspend), 224 DEVMETHOD(device_resume, fxp_resume), 225 226 /* MII interface */ 227 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 228 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 229 230 { 0, 0 } 231}; 232 233static driver_t fxp_driver = { 234 "fxp", 235 fxp_methods, 236 sizeof(struct fxp_softc), 237}; 238 239static devclass_t fxp_devclass; 240 241DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 242DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 243DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 244 245static int fxp_rnr; 246SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 247 248/* 249 * Inline function to copy a 16-bit aligned 32-bit quantity. 250 */ 251static __inline void 252fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 253{ 254#ifdef __i386__ 255 *dst = *src; 256#else 257 volatile u_int16_t *a = (volatile u_int16_t *)src; 258 volatile u_int16_t *b = (volatile u_int16_t *)dst; 259 260 b[0] = a[0]; 261 b[1] = a[1]; 262#endif 263} 264 265/* 266 * Wait for the previous command to be accepted (but not necessarily 267 * completed). 268 */ 269static __inline void 270fxp_scb_wait(struct fxp_softc *sc) 271{ 272 int i = 10000; 273 274 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 275 DELAY(2); 276 if (i == 0) 277 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 278 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 279 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 280 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 281 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 282} 283 284static __inline void 285fxp_scb_cmd(struct fxp_softc *sc, int cmd) 286{ 287 288 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 289 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 290 fxp_scb_wait(sc); 291 } 292 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 293} 294 295static __inline void 296fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 297{ 298 int i = 10000; 299 300 while (!(*status & FXP_CB_STATUS_C) && --i) 301 DELAY(2); 302 if (i == 0) 303 device_printf(sc->dev, "DMA timeout\n"); 304} 305 306/* 307 * Return identification string if this is device is ours. 308 */ 309static int 310fxp_probe(device_t dev) 311{ 312 u_int16_t devid; 313 struct fxp_ident *ident; 314 315 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 316 devid = pci_get_device(dev); 317 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 318 if (ident->devid == devid) { 319 device_set_desc(dev, ident->name); 320 return (0); 321 } 322 } 323 } 324 return (ENXIO); 325} 326 327static void 328fxp_powerstate_d0(device_t dev) 329{ 330#if __FreeBSD_version >= 430002 331 u_int32_t iobase, membase, irq; 332 333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 334 /* Save important PCI config data. */ 335 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 336 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 337 irq = pci_read_config(dev, PCIR_INTLINE, 4); 338 339 /* Reset the power state. */ 340 device_printf(dev, "chip is in D%d power mode " 341 "-- setting to D0\n", pci_get_powerstate(dev)); 342 343 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 344 345 /* Restore PCI config data. */ 346 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 347 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 348 pci_write_config(dev, PCIR_INTLINE, irq, 4); 349 } 350#endif 351} 352 353static int 354fxp_attach(device_t dev) 355{ 356 int error = 0; 357 struct fxp_softc *sc = device_get_softc(dev); 358 struct ifnet *ifp; 359 u_int32_t val; 360 u_int16_t data; 361 int i, rid, m1, m2, prefer_iomap; 362 int s; 363 364 bzero(sc, sizeof(*sc)); 365 sc->dev = dev; 366 callout_handle_init(&sc->stat_ch); 367 sysctl_ctx_init(&sc->sysctl_ctx); 368 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 369 MTX_DEF | MTX_RECURSE); 370 371 s = splimp(); 372 373 /* 374 * Enable bus mastering. Enable memory space too, in case 375 * BIOS/Prom forgot about it. 376 */ 377 val = pci_read_config(dev, PCIR_COMMAND, 2); 378 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 379 pci_write_config(dev, PCIR_COMMAND, val, 2); 380 val = pci_read_config(dev, PCIR_COMMAND, 2); 381 382 fxp_powerstate_d0(dev); 383 384 /* 385 * Figure out which we should try first - memory mapping or i/o mapping? 386 * We default to memory mapping. Then we accept an override from the 387 * command line. Then we check to see which one is enabled. 388 */ 389 m1 = PCIM_CMD_MEMEN; 390 m2 = PCIM_CMD_PORTEN; 391 prefer_iomap = 0; 392 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 393 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 394 m1 = PCIM_CMD_PORTEN; 395 m2 = PCIM_CMD_MEMEN; 396 } 397 398 if (val & m1) { 399 sc->rtp = 400 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 401 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 402 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 403 0, ~0, 1, RF_ACTIVE); 404 } 405 if (sc->mem == NULL && (val & m2)) { 406 sc->rtp = 407 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 408 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 409 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 410 0, ~0, 1, RF_ACTIVE); 411 } 412 413 if (!sc->mem) { 414 device_printf(dev, "could not map device registers\n"); 415 error = ENXIO; 416 goto fail; 417 } 418 if (bootverbose) { 419 device_printf(dev, "using %s space register mapping\n", 420 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 421 } 422 423 sc->sc_st = rman_get_bustag(sc->mem); 424 sc->sc_sh = rman_get_bushandle(sc->mem); 425 426 /* 427 * Allocate our interrupt. 428 */ 429 rid = 0; 430 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 431 RF_SHAREABLE | RF_ACTIVE); 432 if (sc->irq == NULL) { 433 device_printf(dev, "could not map interrupt\n"); 434 error = ENXIO; 435 goto fail; 436 } 437 438 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 439 fxp_intr, sc, &sc->ih); 440 if (error) { 441 device_printf(dev, "could not setup irq\n"); 442 goto fail; 443 } 444 445 /* 446 * Reset to a stable state. 447 */ 448 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 449 DELAY(10); 450 451 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 452 M_DEVBUF, M_NOWAIT | M_ZERO); 453 if (sc->cbl_base == NULL) 454 goto failmem; 455 456 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 457 M_NOWAIT | M_ZERO); 458 if (sc->fxp_stats == NULL) 459 goto failmem; 460 461 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 462 if (sc->mcsp == NULL) 463 goto failmem; 464 465 /* 466 * Pre-allocate our receive buffers. 467 */ 468 for (i = 0; i < FXP_NRFABUFS; i++) { 469 if (fxp_add_rfabuf(sc, NULL) != 0) { 470 goto failmem; 471 } 472 } 473 474 /* 475 * Find out how large of an SEEPROM we have. 476 */ 477 fxp_autosize_eeprom(sc); 478 479 /* 480 * Determine whether we must use the 503 serial interface. 481 */ 482 fxp_read_eeprom(sc, &data, 6, 1); 483 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 484 (data & FXP_PHY_SERIAL_ONLY)) 485 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 486 487 /* 488 * Create the sysctl tree 489 */ 490 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 491 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 492 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 493 if (sc->sysctl_tree == NULL) 494 goto fail; 495 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 496 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 497 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 498 "FXP driver receive interrupt microcode bundling delay"); 499 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 500 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 501 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 502 "FXP driver receive interrupt microcode bundle size limit"); 503 504 /* 505 * Pull in device tunables. 506 */ 507 sc->tunable_int_delay = TUNABLE_INT_DELAY; 508 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 509 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 510 "int_delay", &sc->tunable_int_delay); 511 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 512 "bundle_max", &sc->tunable_bundle_max); 513 514 /* 515 * Find out the chip revision; lump all 82557 revs together. 516 */ 517 fxp_read_eeprom(sc, &data, 5, 1); 518 if ((data >> 8) == 1) 519 sc->revision = FXP_REV_82557; 520 else 521 sc->revision = pci_get_revid(dev); 522 523 /* 524 * Enable workarounds for certain chip revision deficiencies. 525 * 526 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 527 * some systems based a normal 82559 design, have a defect where 528 * the chip can cause a PCI protocol violation if it receives 529 * a CU_RESUME command when it is entering the IDLE state. The 530 * workaround is to disable Dynamic Standby Mode, so the chip never 531 * deasserts CLKRUN#, and always remains in an active state. 532 * 533 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 534 */ 535 i = pci_get_device(dev); 536 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 537 sc->revision >= FXP_REV_82559_A0) { 538 fxp_read_eeprom(sc, &data, 10, 1); 539 if (data & 0x02) { /* STB enable */ 540 u_int16_t cksum; 541 int i; 542 543 device_printf(dev, 544 "Disabling dynamic standby mode in EEPROM\n"); 545 data &= ~0x02; 546 fxp_write_eeprom(sc, &data, 10, 1); 547 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 548 cksum = 0; 549 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 550 fxp_read_eeprom(sc, &data, i, 1); 551 cksum += data; 552 } 553 i = (1 << sc->eeprom_size) - 1; 554 cksum = 0xBABA - cksum; 555 fxp_read_eeprom(sc, &data, i, 1); 556 fxp_write_eeprom(sc, &cksum, i, 1); 557 device_printf(dev, 558 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 559 i, data, cksum); 560#if 1 561 /* 562 * If the user elects to continue, try the software 563 * workaround, as it is better than nothing. 564 */ 565 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 566#endif 567 } 568 } 569 570 /* 571 * If we are not a 82557 chip, we can enable extended features. 572 */ 573 if (sc->revision != FXP_REV_82557) { 574 /* 575 * If MWI is enabled in the PCI configuration, and there 576 * is a valid cacheline size (8 or 16 dwords), then tell 577 * the board to turn on MWI. 578 */ 579 if (val & PCIM_CMD_MWRICEN && 580 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 581 sc->flags |= FXP_FLAG_MWI_ENABLE; 582 583 /* turn on the extended TxCB feature */ 584 sc->flags |= FXP_FLAG_EXT_TXCB; 585 586 /* enable reception of long frames for VLAN */ 587 sc->flags |= FXP_FLAG_LONG_PKT_EN; 588 } 589 590 /* 591 * Read MAC address. 592 */ 593 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 594 device_printf(dev, "Ethernet address %6D%s\n", 595 sc->arpcom.ac_enaddr, ":", 596 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 597 if (bootverbose) { 598 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 599 pci_get_vendor(dev), pci_get_device(dev), 600 pci_get_subvendor(dev), pci_get_subdevice(dev), 601 pci_get_revid(dev)); 602 fxp_read_eeprom(sc, &data, 10, 1); 603 device_printf(dev, "Dynamic Standby mode is %s\n", 604 data & 0x02 ? "enabled" : "disabled"); 605 } 606 607 /* 608 * If this is only a 10Mbps device, then there is no MII, and 609 * the PHY will use a serial interface instead. 610 * 611 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 612 * doesn't have a programming interface of any sort. The 613 * media is sensed automatically based on how the link partner 614 * is configured. This is, in essence, manual configuration. 615 */ 616 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 617 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 618 fxp_serial_ifmedia_sts); 619 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 620 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 621 } else { 622 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 623 fxp_ifmedia_sts)) { 624 device_printf(dev, "MII without any PHY!\n"); 625 error = ENXIO; 626 goto fail; 627 } 628 } 629 630 ifp = &sc->arpcom.ac_if; 631 ifp->if_unit = device_get_unit(dev); 632 ifp->if_name = "fxp"; 633 ifp->if_output = ether_output; 634 ifp->if_baudrate = 100000000; 635 ifp->if_init = fxp_init; 636 ifp->if_softc = sc; 637 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 638 ifp->if_ioctl = fxp_ioctl; 639 ifp->if_start = fxp_start; 640 ifp->if_watchdog = fxp_watchdog; 641 642 /* 643 * Attach the interface. 644 */ 645 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 646 647 /* 648 * Tell the upper layer(s) we support long frames. 649 */ 650 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 651 652 /* 653 * Let the system queue as many packets as we have available 654 * TX descriptors. 655 */ 656 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 657 658 splx(s); 659 return (0); 660 661failmem: 662 device_printf(dev, "Failed to malloc memory\n"); 663 error = ENOMEM; 664fail: 665 splx(s); 666 fxp_release(sc); 667 return (error); 668} 669 670/* 671 * release all resources 672 */ 673static void 674fxp_release(struct fxp_softc *sc) 675{ 676 677 bus_generic_detach(sc->dev); 678 if (sc->miibus) 679 device_delete_child(sc->dev, sc->miibus); 680 681 if (sc->cbl_base) 682 free(sc->cbl_base, M_DEVBUF); 683 if (sc->fxp_stats) 684 free(sc->fxp_stats, M_DEVBUF); 685 if (sc->mcsp) 686 free(sc->mcsp, M_DEVBUF); 687 if (sc->rfa_headm) 688 m_freem(sc->rfa_headm); 689 690 if (sc->ih) 691 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 692 if (sc->irq) 693 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 694 if (sc->mem) 695 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 696 697 sysctl_ctx_free(&sc->sysctl_ctx); 698 699 mtx_destroy(&sc->sc_mtx); 700} 701 702/* 703 * Detach interface. 704 */ 705static int 706fxp_detach(device_t dev) 707{ 708 struct fxp_softc *sc = device_get_softc(dev); 709 int s; 710 711 /* disable interrupts */ 712 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 713 714 s = splimp(); 715 716 /* 717 * Stop DMA and drop transmit queue. 718 */ 719 fxp_stop(sc); 720 721 /* 722 * Close down routes etc. 723 */ 724 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 725 726 /* 727 * Free all media structures. 728 */ 729 ifmedia_removeall(&sc->sc_media); 730 731 splx(s); 732 733 /* Release our allocated resources. */ 734 fxp_release(sc); 735 736 return (0); 737} 738 739/* 740 * Device shutdown routine. Called at system shutdown after sync. The 741 * main purpose of this routine is to shut off receiver DMA so that 742 * kernel memory doesn't get clobbered during warmboot. 743 */ 744static int 745fxp_shutdown(device_t dev) 746{ 747 /* 748 * Make sure that DMA is disabled prior to reboot. Not doing 749 * do could allow DMA to corrupt kernel memory during the 750 * reboot before the driver initializes. 751 */ 752 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 753 return (0); 754} 755 756/* 757 * Device suspend routine. Stop the interface and save some PCI 758 * settings in case the BIOS doesn't restore them properly on 759 * resume. 760 */ 761static int 762fxp_suspend(device_t dev) 763{ 764 struct fxp_softc *sc = device_get_softc(dev); 765 int i, s; 766 767 s = splimp(); 768 769 fxp_stop(sc); 770 771 for (i = 0; i < 5; i++) 772 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 773 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 774 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 775 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 776 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 777 778 sc->suspended = 1; 779 780 splx(s); 781 return (0); 782} 783 784/* 785 * Device resume routine. Restore some PCI settings in case the BIOS 786 * doesn't, re-enable busmastering, and restart the interface if 787 * appropriate. 788 */ 789static int 790fxp_resume(device_t dev) 791{ 792 struct fxp_softc *sc = device_get_softc(dev); 793 struct ifnet *ifp = &sc->sc_if; 794 u_int16_t pci_command; 795 int i, s; 796 797 s = splimp(); 798 799 fxp_powerstate_d0(dev); 800 801 /* better way to do this? */ 802 for (i = 0; i < 5; i++) 803 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 804 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 805 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 806 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 807 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 808 809 /* reenable busmastering */ 810 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 811 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 812 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 813 814 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 815 DELAY(10); 816 817 /* reinitialize interface if necessary */ 818 if (ifp->if_flags & IFF_UP) 819 fxp_init(sc); 820 821 sc->suspended = 0; 822 823 splx(s); 824 return (0); 825} 826 827static void 828fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 829{ 830 u_int16_t reg; 831 int x; 832 833 /* 834 * Shift in data. 835 */ 836 for (x = 1 << (length - 1); x; x >>= 1) { 837 if (data & x) 838 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 839 else 840 reg = FXP_EEPROM_EECS; 841 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 842 DELAY(1); 843 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 844 DELAY(1); 845 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 846 DELAY(1); 847 } 848} 849 850/* 851 * Read from the serial EEPROM. Basically, you manually shift in 852 * the read opcode (one bit at a time) and then shift in the address, 853 * and then you shift out the data (all of this one bit at a time). 854 * The word size is 16 bits, so you have to provide the address for 855 * every 16 bits of data. 856 */ 857static u_int16_t 858fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 859{ 860 u_int16_t reg, data; 861 int x; 862 863 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 864 /* 865 * Shift in read opcode. 866 */ 867 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 868 /* 869 * Shift in address. 870 */ 871 data = 0; 872 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 873 if (offset & x) 874 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 875 else 876 reg = FXP_EEPROM_EECS; 877 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 878 DELAY(1); 879 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 880 DELAY(1); 881 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 882 DELAY(1); 883 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 884 data++; 885 if (autosize && reg == 0) { 886 sc->eeprom_size = data; 887 break; 888 } 889 } 890 /* 891 * Shift out data. 892 */ 893 data = 0; 894 reg = FXP_EEPROM_EECS; 895 for (x = 1 << 15; x; x >>= 1) { 896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 897 DELAY(1); 898 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 899 data |= x; 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 901 DELAY(1); 902 } 903 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 904 DELAY(1); 905 906 return (data); 907} 908 909static void 910fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 911{ 912 int i; 913 914 /* 915 * Erase/write enable. 916 */ 917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 918 fxp_eeprom_shiftin(sc, 0x4, 3); 919 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 921 DELAY(1); 922 /* 923 * Shift in write opcode, address, data. 924 */ 925 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 926 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 927 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 928 fxp_eeprom_shiftin(sc, data, 16); 929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 930 DELAY(1); 931 /* 932 * Wait for EEPROM to finish up. 933 */ 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 935 DELAY(1); 936 for (i = 0; i < 1000; i++) { 937 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 938 break; 939 DELAY(50); 940 } 941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 942 DELAY(1); 943 /* 944 * Erase/write disable. 945 */ 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 947 fxp_eeprom_shiftin(sc, 0x4, 3); 948 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 949 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 950 DELAY(1); 951} 952 953/* 954 * From NetBSD: 955 * 956 * Figure out EEPROM size. 957 * 958 * 559's can have either 64-word or 256-word EEPROMs, the 558 959 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 960 * talks about the existance of 16 to 256 word EEPROMs. 961 * 962 * The only known sizes are 64 and 256, where the 256 version is used 963 * by CardBus cards to store CIS information. 964 * 965 * The address is shifted in msb-to-lsb, and after the last 966 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 967 * after which follows the actual data. We try to detect this zero, by 968 * probing the data-out bit in the EEPROM control register just after 969 * having shifted in a bit. If the bit is zero, we assume we've 970 * shifted enough address bits. The data-out should be tri-state, 971 * before this, which should translate to a logical one. 972 */ 973static void 974fxp_autosize_eeprom(struct fxp_softc *sc) 975{ 976 977 /* guess maximum size of 256 words */ 978 sc->eeprom_size = 8; 979 980 /* autosize */ 981 (void) fxp_eeprom_getword(sc, 0, 1); 982} 983 984static void 985fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 986{ 987 int i; 988 989 for (i = 0; i < words; i++) 990 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 991} 992 993static void 994fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 995{ 996 int i; 997 998 for (i = 0; i < words; i++) 999 fxp_eeprom_putword(sc, offset + i, data[i]); 1000} 1001 1002/* 1003 * Start packet transmission on the interface. 1004 */ 1005static void 1006fxp_start(struct ifnet *ifp) 1007{ 1008 struct fxp_softc *sc = ifp->if_softc; 1009 struct fxp_cb_tx *txp; 1010 1011 /* 1012 * See if we need to suspend xmit until the multicast filter 1013 * has been reprogrammed (which can only be done at the head 1014 * of the command chain). 1015 */ 1016 if (sc->need_mcsetup) { 1017 return; 1018 } 1019 1020 txp = NULL; 1021 1022 /* 1023 * We're finished if there is nothing more to add to the list or if 1024 * we're all filled up with buffers to transmit. 1025 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1026 * a NOP command when needed. 1027 */ 1028 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1029 struct mbuf *m, *mb_head; 1030 int segment; 1031 1032 /* 1033 * Grab a packet to transmit. 1034 */ 1035 IF_DEQUEUE(&ifp->if_snd, mb_head); 1036 1037 /* 1038 * Get pointer to next available tx desc. 1039 */ 1040 txp = sc->cbl_last->next; 1041 1042 /* 1043 * Go through each of the mbufs in the chain and initialize 1044 * the transmit buffer descriptors with the physical address 1045 * and size of the mbuf. 1046 */ 1047tbdinit: 1048 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1049 if (m->m_len != 0) { 1050 if (segment == FXP_NTXSEG) 1051 break; 1052 txp->tbd[segment].tb_addr = 1053 vtophys(mtod(m, vm_offset_t)); 1054 txp->tbd[segment].tb_size = m->m_len; 1055 segment++; 1056 } 1057 } 1058 if (m != NULL) { 1059 struct mbuf *mn; 1060 1061 /* 1062 * We ran out of segments. We have to recopy this 1063 * mbuf chain first. Bail out if we can't get the 1064 * new buffers. 1065 */ 1066 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1067 if (mn == NULL) { 1068 m_freem(mb_head); 1069 break; 1070 } 1071 if (mb_head->m_pkthdr.len > MHLEN) { 1072 MCLGET(mn, M_DONTWAIT); 1073 if ((mn->m_flags & M_EXT) == 0) { 1074 m_freem(mn); 1075 m_freem(mb_head); 1076 break; 1077 } 1078 } 1079 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1080 mtod(mn, caddr_t)); 1081 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1082 m_freem(mb_head); 1083 mb_head = mn; 1084 goto tbdinit; 1085 } 1086 1087 txp->tbd_number = segment; 1088 txp->mb_head = mb_head; 1089 txp->cb_status = 0; 1090 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1091 txp->cb_command = 1092 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1093 FXP_CB_COMMAND_S; 1094 } else { 1095 txp->cb_command = 1096 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1097 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1098 /* 1099 * Set a 5 second timer just in case we don't hear 1100 * from the card again. 1101 */ 1102 ifp->if_timer = 5; 1103 } 1104 txp->tx_threshold = tx_threshold; 1105 1106 /* 1107 * Advance the end of list forward. 1108 */ 1109 1110#ifdef __alpha__ 1111 /* 1112 * On platforms which can't access memory in 16-bit 1113 * granularities, we must prevent the card from DMA'ing 1114 * up the status while we update the command field. 1115 * This could cause us to overwrite the completion status. 1116 */ 1117 atomic_clear_short(&sc->cbl_last->cb_command, 1118 FXP_CB_COMMAND_S); 1119#else 1120 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1121#endif /*__alpha__*/ 1122 sc->cbl_last = txp; 1123 1124 /* 1125 * Advance the beginning of the list forward if there are 1126 * no other packets queued (when nothing is queued, cbl_first 1127 * sits on the last TxCB that was sent out). 1128 */ 1129 if (sc->tx_queued == 0) 1130 sc->cbl_first = txp; 1131 1132 sc->tx_queued++; 1133 1134 /* 1135 * Pass packet to bpf if there is a listener. 1136 */ 1137 if (ifp->if_bpf) 1138 bpf_mtap(ifp, mb_head); 1139 } 1140 1141 /* 1142 * We're finished. If we added to the list, issue a RESUME to get DMA 1143 * going again if suspended. 1144 */ 1145 if (txp != NULL) { 1146 fxp_scb_wait(sc); 1147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1148 } 1149} 1150 1151static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1152 1153#ifdef DEVICE_POLLING 1154static poll_handler_t fxp_poll; 1155 1156static void 1157fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1158{ 1159 struct fxp_softc *sc = ifp->if_softc; 1160 u_int8_t statack; 1161 1162 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1163 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1164 return; 1165 } 1166 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1167 FXP_SCB_STATACK_FR; 1168 if (cmd == POLL_AND_CHECK_STATUS) { 1169 u_int8_t tmp; 1170 1171 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1172 if (tmp == 0xff || tmp == 0) 1173 return; /* nothing to do */ 1174 tmp &= ~statack; 1175 /* ack what we can */ 1176 if (tmp != 0) 1177 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1178 statack |= tmp; 1179 } 1180 fxp_intr_body(sc, statack, count); 1181} 1182#endif /* DEVICE_POLLING */ 1183 1184/* 1185 * Process interface interrupts. 1186 */ 1187static void 1188fxp_intr(void *xsc) 1189{ 1190 struct fxp_softc *sc = xsc; 1191 u_int8_t statack; 1192 1193#ifdef DEVICE_POLLING 1194 struct ifnet *ifp = &sc->sc_if; 1195 1196 if (ifp->if_flags & IFF_POLLING) 1197 return; 1198 if (ether_poll_register(fxp_poll, ifp)) { 1199 /* disable interrupts */ 1200 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1201 fxp_poll(ifp, 0, 1); 1202 return; 1203 } 1204#endif 1205 1206 if (sc->suspended) { 1207 return; 1208 } 1209 1210 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1211 /* 1212 * It should not be possible to have all bits set; the 1213 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1214 * all bits are set, this may indicate that the card has 1215 * been physically ejected, so ignore it. 1216 */ 1217 if (statack == 0xff) 1218 return; 1219 1220 /* 1221 * First ACK all the interrupts in this pass. 1222 */ 1223 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1224 fxp_intr_body(sc, statack, -1); 1225 } 1226} 1227 1228static void 1229fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1230{ 1231 struct ifnet *ifp = &sc->sc_if; 1232 struct mbuf *m; 1233 struct fxp_rfa *rfa; 1234 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1235 1236 if (rnr) 1237 fxp_rnr++; 1238 1239 /* 1240 * Free any finished transmit mbuf chains. 1241 * 1242 * Handle the CNA event likt a CXTNO event. It used to 1243 * be that this event (control unit not ready) was not 1244 * encountered, but it is now with the SMPng modifications. 1245 * The exact sequence of events that occur when the interface 1246 * is brought up are different now, and if this event 1247 * goes unhandled, the configuration/rxfilter setup sequence 1248 * can stall for several seconds. The result is that no 1249 * packets go out onto the wire for about 5 to 10 seconds 1250 * after the interface is ifconfig'ed for the first time. 1251 */ 1252 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1253 struct fxp_cb_tx *txp; 1254 1255 for (txp = sc->cbl_first; sc->tx_queued && 1256 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1257 txp = txp->next) { 1258 if (txp->mb_head != NULL) { 1259 m_freem(txp->mb_head); 1260 txp->mb_head = NULL; 1261 } 1262 sc->tx_queued--; 1263 } 1264 sc->cbl_first = txp; 1265 ifp->if_timer = 0; 1266 if (sc->tx_queued == 0) { 1267 if (sc->need_mcsetup) 1268 fxp_mc_setup(sc); 1269 } 1270 /* 1271 * Try to start more packets transmitting. 1272 */ 1273 if (ifp->if_snd.ifq_head != NULL) 1274 fxp_start(ifp); 1275 } 1276 1277 /* 1278 * Just return if nothing happened on the receive side. 1279 */ 1280 if ( (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) == 0) 1281 return; 1282 1283 /* 1284 * Process receiver interrupts. If a no-resource (RNR) 1285 * condition exists, get whatever packets we can and 1286 * re-start the receiver. 1287 * When using polling, we do not process the list to completion, 1288 * so when we get an RNR interrupt we must defer the restart 1289 * until we hit the last buffer with the C bit set. 1290 * If we run out of cycles and rfa_headm has the C bit set, 1291 * record the pending RNR in an unused status bit, so that the 1292 * info will be used in the subsequent polling cycle. 1293 */ 1294 1295#define FXP_RFA_RNRMARK 0x4000 /* used to mark a pending RNR intr */ 1296 1297 for (;;) { 1298 m = sc->rfa_headm; 1299 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1300 RFA_ALIGNMENT_FUDGE); 1301 1302#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1303 if (count >= 0 && count-- == 0) 1304 break; 1305#endif /* DEVICE_POLLING */ 1306 1307 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1308 break; 1309 1310 if (rfa->rfa_status & FXP_RFA_RNRMARK) 1311 rnr = 1; 1312 /* 1313 * Remove first packet from the chain. 1314 */ 1315 sc->rfa_headm = m->m_next; 1316 m->m_next = NULL; 1317 1318 /* 1319 * Add a new buffer to the receive chain. 1320 * If this fails, the old buffer is recycled 1321 * instead. 1322 */ 1323 if (fxp_add_rfabuf(sc, m) == 0) { 1324 int total_len; 1325 1326 /* 1327 * Fetch packet length (the top 2 bits of 1328 * actual_size are flags set by the controller 1329 * upon completion), and drop the packet in case 1330 * of bogus length or CRC errors. 1331 */ 1332 total_len = rfa->actual_size & 0x3fff; 1333 if (total_len < sizeof(struct ether_header) || 1334 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1335 sizeof(struct fxp_rfa) || 1336 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1337 m_freem(m); 1338 continue; 1339 } 1340 1341 m->m_pkthdr.len = m->m_len = total_len; 1342 ether_input(ifp, NULL, m); 1343 } 1344 } 1345 if (rnr) { 1346 if (rfa->rfa_status & FXP_RFA_STATUS_C) 1347 rfa->rfa_status |= FXP_RFA_RNRMARK; 1348 else { 1349 fxp_scb_wait(sc); 1350 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1351 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1352 RFA_ALIGNMENT_FUDGE); 1353 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1354 } 1355 } 1356} 1357 1358/* 1359 * Update packet in/out/collision statistics. The i82557 doesn't 1360 * allow you to access these counters without doing a fairly 1361 * expensive DMA to get _all_ of the statistics it maintains, so 1362 * we do this operation here only once per second. The statistics 1363 * counters in the kernel are updated from the previous dump-stats 1364 * DMA and then a new dump-stats DMA is started. The on-chip 1365 * counters are zeroed when the DMA completes. If we can't start 1366 * the DMA immediately, we don't wait - we just prepare to read 1367 * them again next time. 1368 */ 1369static void 1370fxp_tick(void *xsc) 1371{ 1372 struct fxp_softc *sc = xsc; 1373 struct ifnet *ifp = &sc->sc_if; 1374 struct fxp_stats *sp = sc->fxp_stats; 1375 struct fxp_cb_tx *txp; 1376 int s; 1377 1378 ifp->if_opackets += sp->tx_good; 1379 ifp->if_collisions += sp->tx_total_collisions; 1380 if (sp->rx_good) { 1381 ifp->if_ipackets += sp->rx_good; 1382 sc->rx_idle_secs = 0; 1383 } else { 1384 /* 1385 * Receiver's been idle for another second. 1386 */ 1387 sc->rx_idle_secs++; 1388 } 1389 ifp->if_ierrors += 1390 sp->rx_crc_errors + 1391 sp->rx_alignment_errors + 1392 sp->rx_rnr_errors + 1393 sp->rx_overrun_errors; 1394 /* 1395 * If any transmit underruns occured, bump up the transmit 1396 * threshold by another 512 bytes (64 * 8). 1397 */ 1398 if (sp->tx_underruns) { 1399 ifp->if_oerrors += sp->tx_underruns; 1400 if (tx_threshold < 192) 1401 tx_threshold += 64; 1402 } 1403 s = splimp(); 1404 /* 1405 * Release any xmit buffers that have completed DMA. This isn't 1406 * strictly necessary to do here, but it's advantagous for mbufs 1407 * with external storage to be released in a timely manner rather 1408 * than being defered for a potentially long time. This limits 1409 * the delay to a maximum of one second. 1410 */ 1411 for (txp = sc->cbl_first; sc->tx_queued && 1412 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1413 txp = txp->next) { 1414 if (txp->mb_head != NULL) { 1415 m_freem(txp->mb_head); 1416 txp->mb_head = NULL; 1417 } 1418 sc->tx_queued--; 1419 } 1420 sc->cbl_first = txp; 1421 /* 1422 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1423 * then assume the receiver has locked up and attempt to clear 1424 * the condition by reprogramming the multicast filter. This is 1425 * a work-around for a bug in the 82557 where the receiver locks 1426 * up if it gets certain types of garbage in the syncronization 1427 * bits prior to the packet header. This bug is supposed to only 1428 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1429 * mode as well (perhaps due to a 10/100 speed transition). 1430 */ 1431 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1432 sc->rx_idle_secs = 0; 1433 fxp_mc_setup(sc); 1434 } 1435 /* 1436 * If there is no pending command, start another stats 1437 * dump. Otherwise punt for now. 1438 */ 1439 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1440 /* 1441 * Start another stats dump. 1442 */ 1443 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1444 } else { 1445 /* 1446 * A previous command is still waiting to be accepted. 1447 * Just zero our copy of the stats and wait for the 1448 * next timer event to update them. 1449 */ 1450 sp->tx_good = 0; 1451 sp->tx_underruns = 0; 1452 sp->tx_total_collisions = 0; 1453 1454 sp->rx_good = 0; 1455 sp->rx_crc_errors = 0; 1456 sp->rx_alignment_errors = 0; 1457 sp->rx_rnr_errors = 0; 1458 sp->rx_overrun_errors = 0; 1459 } 1460 if (sc->miibus != NULL) 1461 mii_tick(device_get_softc(sc->miibus)); 1462 splx(s); 1463 /* 1464 * Schedule another timeout one second from now. 1465 */ 1466 sc->stat_ch = timeout(fxp_tick, sc, hz); 1467} 1468 1469/* 1470 * Stop the interface. Cancels the statistics updater and resets 1471 * the interface. 1472 */ 1473static void 1474fxp_stop(struct fxp_softc *sc) 1475{ 1476 struct ifnet *ifp = &sc->sc_if; 1477 struct fxp_cb_tx *txp; 1478 int i; 1479 1480 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1481 ifp->if_timer = 0; 1482 1483#ifdef DEVICE_POLLING 1484 ether_poll_deregister(ifp); 1485#endif 1486 /* 1487 * Cancel stats updater. 1488 */ 1489 untimeout(fxp_tick, sc, sc->stat_ch); 1490 1491 /* 1492 * Issue software reset, which also unloads the microcode. 1493 */ 1494 sc->flags &= ~FXP_FLAG_UCODE; 1495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1496 DELAY(50); 1497 1498 /* 1499 * Release any xmit buffers. 1500 */ 1501 txp = sc->cbl_base; 1502 if (txp != NULL) { 1503 for (i = 0; i < FXP_NTXCB; i++) { 1504 if (txp[i].mb_head != NULL) { 1505 m_freem(txp[i].mb_head); 1506 txp[i].mb_head = NULL; 1507 } 1508 } 1509 } 1510 sc->tx_queued = 0; 1511 1512 /* 1513 * Free all the receive buffers then reallocate/reinitialize 1514 */ 1515 if (sc->rfa_headm != NULL) 1516 m_freem(sc->rfa_headm); 1517 sc->rfa_headm = NULL; 1518 sc->rfa_tailm = NULL; 1519 for (i = 0; i < FXP_NRFABUFS; i++) { 1520 if (fxp_add_rfabuf(sc, NULL) != 0) { 1521 /* 1522 * This "can't happen" - we're at splimp() 1523 * and we just freed all the buffers we need 1524 * above. 1525 */ 1526 panic("fxp_stop: no buffers!"); 1527 } 1528 } 1529} 1530 1531/* 1532 * Watchdog/transmission transmit timeout handler. Called when a 1533 * transmission is started on the interface, but no interrupt is 1534 * received before the timeout. This usually indicates that the 1535 * card has wedged for some reason. 1536 */ 1537static void 1538fxp_watchdog(struct ifnet *ifp) 1539{ 1540 struct fxp_softc *sc = ifp->if_softc; 1541 1542 device_printf(sc->dev, "device timeout\n"); 1543 ifp->if_oerrors++; 1544 1545 fxp_init(sc); 1546} 1547 1548static void 1549fxp_init(void *xsc) 1550{ 1551 struct fxp_softc *sc = xsc; 1552 struct ifnet *ifp = &sc->sc_if; 1553 struct fxp_cb_config *cbp; 1554 struct fxp_cb_ias *cb_ias; 1555 struct fxp_cb_tx *txp; 1556 struct fxp_cb_mcs *mcsp; 1557 int i, prm, s; 1558 1559 s = splimp(); 1560 /* 1561 * Cancel any pending I/O 1562 */ 1563 fxp_stop(sc); 1564 1565 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1566 1567 /* 1568 * Initialize base of CBL and RFA memory. Loading with zero 1569 * sets it up for regular linear addressing. 1570 */ 1571 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1572 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1573 1574 fxp_scb_wait(sc); 1575 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1576 1577 /* 1578 * Initialize base of dump-stats buffer. 1579 */ 1580 fxp_scb_wait(sc); 1581 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1582 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1583 1584 /* 1585 * Attempt to load microcode if requested. 1586 */ 1587 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1588 fxp_load_ucode(sc); 1589 1590 /* 1591 * Initialize the multicast address list. 1592 */ 1593 if (fxp_mc_addrs(sc)) { 1594 mcsp = sc->mcsp; 1595 mcsp->cb_status = 0; 1596 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1597 mcsp->link_addr = -1; 1598 /* 1599 * Start the multicast setup command. 1600 */ 1601 fxp_scb_wait(sc); 1602 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1603 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1604 /* ...and wait for it to complete. */ 1605 fxp_dma_wait(&mcsp->cb_status, sc); 1606 } 1607 1608 /* 1609 * We temporarily use memory that contains the TxCB list to 1610 * construct the config CB. The TxCB list memory is rebuilt 1611 * later. 1612 */ 1613 cbp = (struct fxp_cb_config *) sc->cbl_base; 1614 1615 /* 1616 * This bcopy is kind of disgusting, but there are a bunch of must be 1617 * zero and must be one bits in this structure and this is the easiest 1618 * way to initialize them all to proper values. 1619 */ 1620 bcopy(fxp_cb_config_template, 1621 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1622 sizeof(fxp_cb_config_template)); 1623 1624 cbp->cb_status = 0; 1625 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1626 cbp->link_addr = -1; /* (no) next command */ 1627 cbp->byte_count = 22; /* (22) bytes to config */ 1628 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1629 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1630 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1631 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1632 cbp->type_enable = 0; /* actually reserved */ 1633 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1634 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1635 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1636 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1637 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1638 cbp->late_scb = 0; /* (don't) defer SCB update */ 1639 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1640 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1641 cbp->ci_int = 1; /* interrupt on CU idle */ 1642 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1643 cbp->ext_stats_dis = 1; /* disable extended counters */ 1644 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1645 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1646 cbp->disc_short_rx = !prm; /* discard short packets */ 1647 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1648 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1649 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1650 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1651 cbp->csma_dis = 0; /* (don't) disable link */ 1652 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1653 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1654 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1655 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1656 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1657 cbp->nsai = 1; /* (don't) disable source addr insert */ 1658 cbp->preamble_length = 2; /* (7 byte) preamble */ 1659 cbp->loopback = 0; /* (don't) loopback */ 1660 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1661 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1662 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1663 cbp->promiscuous = prm; /* promiscuous mode */ 1664 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1665 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1666 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1667 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1668 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1669 1670 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1671 cbp->padding = 1; /* (do) pad short tx packets */ 1672 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1673 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1674 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1675 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1676 /* must set wake_en in PMCSR also */ 1677 cbp->force_fdx = 0; /* (don't) force full duplex */ 1678 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1679 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1680 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1681 1682 if (sc->revision == FXP_REV_82557) { 1683 /* 1684 * The 82557 has no hardware flow control, the values 1685 * below are the defaults for the chip. 1686 */ 1687 cbp->fc_delay_lsb = 0; 1688 cbp->fc_delay_msb = 0x40; 1689 cbp->pri_fc_thresh = 3; 1690 cbp->tx_fc_dis = 0; 1691 cbp->rx_fc_restop = 0; 1692 cbp->rx_fc_restart = 0; 1693 cbp->fc_filter = 0; 1694 cbp->pri_fc_loc = 1; 1695 } else { 1696 cbp->fc_delay_lsb = 0x1f; 1697 cbp->fc_delay_msb = 0x01; 1698 cbp->pri_fc_thresh = 3; 1699 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1700 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1701 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1702 cbp->fc_filter = !prm; /* drop FC frames to host */ 1703 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1704 } 1705 1706 /* 1707 * Start the config command/DMA. 1708 */ 1709 fxp_scb_wait(sc); 1710 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1711 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1712 /* ...and wait for it to complete. */ 1713 fxp_dma_wait(&cbp->cb_status, sc); 1714 1715 /* 1716 * Now initialize the station address. Temporarily use the TxCB 1717 * memory area like we did above for the config CB. 1718 */ 1719 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1720 cb_ias->cb_status = 0; 1721 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1722 cb_ias->link_addr = -1; 1723 bcopy(sc->arpcom.ac_enaddr, 1724 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1725 sizeof(sc->arpcom.ac_enaddr)); 1726 1727 /* 1728 * Start the IAS (Individual Address Setup) command/DMA. 1729 */ 1730 fxp_scb_wait(sc); 1731 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1732 /* ...and wait for it to complete. */ 1733 fxp_dma_wait(&cb_ias->cb_status, sc); 1734 1735 /* 1736 * Initialize transmit control block (TxCB) list. 1737 */ 1738 1739 txp = sc->cbl_base; 1740 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1741 for (i = 0; i < FXP_NTXCB; i++) { 1742 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1743 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1744 txp[i].link_addr = 1745 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1746 if (sc->flags & FXP_FLAG_EXT_TXCB) 1747 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1748 else 1749 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1750 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1751 } 1752 /* 1753 * Set the suspend flag on the first TxCB and start the control 1754 * unit. It will execute the NOP and then suspend. 1755 */ 1756 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1757 sc->cbl_first = sc->cbl_last = txp; 1758 sc->tx_queued = 1; 1759 1760 fxp_scb_wait(sc); 1761 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1762 1763 /* 1764 * Initialize receiver buffer area - RFA. 1765 */ 1766 fxp_scb_wait(sc); 1767 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1768 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1769 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1770 1771 /* 1772 * Set current media. 1773 */ 1774 if (sc->miibus != NULL) 1775 mii_mediachg(device_get_softc(sc->miibus)); 1776 1777 ifp->if_flags |= IFF_RUNNING; 1778 ifp->if_flags &= ~IFF_OACTIVE; 1779 1780 /* 1781 * Enable interrupts. 1782 */ 1783#ifdef DEVICE_POLLING 1784 /* 1785 * ... but only do that if we are not polling. And because (presumably) 1786 * the default is interrupts on, we need to disable them explicitly! 1787 */ 1788 if ( ifp->if_flags & IFF_POLLING ) 1789 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1790 else 1791#endif /* DEVICE_POLLING */ 1792 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1793 splx(s); 1794 1795 /* 1796 * Start stats updater. 1797 */ 1798 sc->stat_ch = timeout(fxp_tick, sc, hz); 1799} 1800 1801static int 1802fxp_serial_ifmedia_upd(struct ifnet *ifp) 1803{ 1804 1805 return (0); 1806} 1807 1808static void 1809fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1810{ 1811 1812 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1813} 1814 1815/* 1816 * Change media according to request. 1817 */ 1818static int 1819fxp_ifmedia_upd(struct ifnet *ifp) 1820{ 1821 struct fxp_softc *sc = ifp->if_softc; 1822 struct mii_data *mii; 1823 1824 mii = device_get_softc(sc->miibus); 1825 mii_mediachg(mii); 1826 return (0); 1827} 1828 1829/* 1830 * Notify the world which media we're using. 1831 */ 1832static void 1833fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1834{ 1835 struct fxp_softc *sc = ifp->if_softc; 1836 struct mii_data *mii; 1837 1838 mii = device_get_softc(sc->miibus); 1839 mii_pollstat(mii); 1840 ifmr->ifm_active = mii->mii_media_active; 1841 ifmr->ifm_status = mii->mii_media_status; 1842 1843 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1844 sc->cu_resume_bug = 1; 1845 else 1846 sc->cu_resume_bug = 0; 1847} 1848 1849/* 1850 * Add a buffer to the end of the RFA buffer list. 1851 * Return 0 if successful, 1 for failure. A failure results in 1852 * adding the 'oldm' (if non-NULL) on to the end of the list - 1853 * tossing out its old contents and recycling it. 1854 * The RFA struct is stuck at the beginning of mbuf cluster and the 1855 * data pointer is fixed up to point just past it. 1856 */ 1857static int 1858fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1859{ 1860 u_int32_t v; 1861 struct mbuf *m; 1862 struct fxp_rfa *rfa, *p_rfa; 1863 1864 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1865 if (m == NULL) { /* try to recycle the old mbuf instead */ 1866 if (oldm == NULL) 1867 return 1; 1868 m = oldm; 1869 m->m_data = m->m_ext.ext_buf; 1870 } 1871 1872 /* 1873 * Move the data pointer up so that the incoming data packet 1874 * will be 32-bit aligned. 1875 */ 1876 m->m_data += RFA_ALIGNMENT_FUDGE; 1877 1878 /* 1879 * Get a pointer to the base of the mbuf cluster and move 1880 * data start past it. 1881 */ 1882 rfa = mtod(m, struct fxp_rfa *); 1883 m->m_data += sizeof(struct fxp_rfa); 1884 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1885 1886 /* 1887 * Initialize the rest of the RFA. Note that since the RFA 1888 * is misaligned, we cannot store values directly. Instead, 1889 * we use an optimized, inline copy. 1890 */ 1891 1892 rfa->rfa_status = 0; 1893 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1894 rfa->actual_size = 0; 1895 1896 v = -1; 1897 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1898 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1899 1900 /* 1901 * If there are other buffers already on the list, attach this 1902 * one to the end by fixing up the tail to point to this one. 1903 */ 1904 if (sc->rfa_headm != NULL) { 1905 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1906 RFA_ALIGNMENT_FUDGE); 1907 sc->rfa_tailm->m_next = m; 1908 v = vtophys(rfa); 1909 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1910 p_rfa->rfa_control = 0; 1911 } else { 1912 sc->rfa_headm = m; 1913 } 1914 sc->rfa_tailm = m; 1915 1916 return (m == oldm); 1917} 1918 1919static volatile int 1920fxp_miibus_readreg(device_t dev, int phy, int reg) 1921{ 1922 struct fxp_softc *sc = device_get_softc(dev); 1923 int count = 10000; 1924 int value; 1925 1926 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1927 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1928 1929 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1930 && count--) 1931 DELAY(10); 1932 1933 if (count <= 0) 1934 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1935 1936 return (value & 0xffff); 1937} 1938 1939static void 1940fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1941{ 1942 struct fxp_softc *sc = device_get_softc(dev); 1943 int count = 10000; 1944 1945 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1946 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1947 (value & 0xffff)); 1948 1949 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1950 count--) 1951 DELAY(10); 1952 1953 if (count <= 0) 1954 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1955} 1956 1957static int 1958fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1959{ 1960 struct fxp_softc *sc = ifp->if_softc; 1961 struct ifreq *ifr = (struct ifreq *)data; 1962 struct mii_data *mii; 1963 int s, error = 0; 1964 1965 s = splimp(); 1966 1967 switch (command) { 1968 case SIOCSIFADDR: 1969 case SIOCGIFADDR: 1970 case SIOCSIFMTU: 1971 error = ether_ioctl(ifp, command, data); 1972 break; 1973 1974 case SIOCSIFFLAGS: 1975 if (ifp->if_flags & IFF_ALLMULTI) 1976 sc->flags |= FXP_FLAG_ALL_MCAST; 1977 else 1978 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1979 1980 /* 1981 * If interface is marked up and not running, then start it. 1982 * If it is marked down and running, stop it. 1983 * XXX If it's up then re-initialize it. This is so flags 1984 * such as IFF_PROMISC are handled. 1985 */ 1986 if (ifp->if_flags & IFF_UP) { 1987 fxp_init(sc); 1988 } else { 1989 if (ifp->if_flags & IFF_RUNNING) 1990 fxp_stop(sc); 1991 } 1992 break; 1993 1994 case SIOCADDMULTI: 1995 case SIOCDELMULTI: 1996 if (ifp->if_flags & IFF_ALLMULTI) 1997 sc->flags |= FXP_FLAG_ALL_MCAST; 1998 else 1999 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2000 /* 2001 * Multicast list has changed; set the hardware filter 2002 * accordingly. 2003 */ 2004 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2005 fxp_mc_setup(sc); 2006 /* 2007 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2008 * again rather than else {}. 2009 */ 2010 if (sc->flags & FXP_FLAG_ALL_MCAST) 2011 fxp_init(sc); 2012 error = 0; 2013 break; 2014 2015 case SIOCSIFMEDIA: 2016 case SIOCGIFMEDIA: 2017 if (sc->miibus != NULL) { 2018 mii = device_get_softc(sc->miibus); 2019 error = ifmedia_ioctl(ifp, ifr, 2020 &mii->mii_media, command); 2021 } else { 2022 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2023 } 2024 break; 2025 2026 default: 2027 error = EINVAL; 2028 } 2029 splx(s); 2030 return (error); 2031} 2032 2033/* 2034 * Fill in the multicast address list and return number of entries. 2035 */ 2036static int 2037fxp_mc_addrs(struct fxp_softc *sc) 2038{ 2039 struct fxp_cb_mcs *mcsp = sc->mcsp; 2040 struct ifnet *ifp = &sc->sc_if; 2041 struct ifmultiaddr *ifma; 2042 int nmcasts; 2043 2044 nmcasts = 0; 2045 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2046#if __FreeBSD_version < 500000 2047 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2048#else 2049 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2050#endif 2051 if (ifma->ifma_addr->sa_family != AF_LINK) 2052 continue; 2053 if (nmcasts >= MAXMCADDR) { 2054 sc->flags |= FXP_FLAG_ALL_MCAST; 2055 nmcasts = 0; 2056 break; 2057 } 2058 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2059 (void *)(uintptr_t)(volatile void *) 2060 &sc->mcsp->mc_addr[nmcasts][0], 6); 2061 nmcasts++; 2062 } 2063 } 2064 mcsp->mc_cnt = nmcasts * 6; 2065 return (nmcasts); 2066} 2067 2068/* 2069 * Program the multicast filter. 2070 * 2071 * We have an artificial restriction that the multicast setup command 2072 * must be the first command in the chain, so we take steps to ensure 2073 * this. By requiring this, it allows us to keep up the performance of 2074 * the pre-initialized command ring (esp. link pointers) by not actually 2075 * inserting the mcsetup command in the ring - i.e. its link pointer 2076 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2077 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2078 * lead into the regular TxCB ring when it completes. 2079 * 2080 * This function must be called at splimp. 2081 */ 2082static void 2083fxp_mc_setup(struct fxp_softc *sc) 2084{ 2085 struct fxp_cb_mcs *mcsp = sc->mcsp; 2086 struct ifnet *ifp = &sc->sc_if; 2087 int count; 2088 2089 /* 2090 * If there are queued commands, we must wait until they are all 2091 * completed. If we are already waiting, then add a NOP command 2092 * with interrupt option so that we're notified when all commands 2093 * have been completed - fxp_start() ensures that no additional 2094 * TX commands will be added when need_mcsetup is true. 2095 */ 2096 if (sc->tx_queued) { 2097 struct fxp_cb_tx *txp; 2098 2099 /* 2100 * need_mcsetup will be true if we are already waiting for the 2101 * NOP command to be completed (see below). In this case, bail. 2102 */ 2103 if (sc->need_mcsetup) 2104 return; 2105 sc->need_mcsetup = 1; 2106 2107 /* 2108 * Add a NOP command with interrupt so that we are notified 2109 * when all TX commands have been processed. 2110 */ 2111 txp = sc->cbl_last->next; 2112 txp->mb_head = NULL; 2113 txp->cb_status = 0; 2114 txp->cb_command = FXP_CB_COMMAND_NOP | 2115 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2116 /* 2117 * Advance the end of list forward. 2118 */ 2119 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2120 sc->cbl_last = txp; 2121 sc->tx_queued++; 2122 /* 2123 * Issue a resume in case the CU has just suspended. 2124 */ 2125 fxp_scb_wait(sc); 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2127 /* 2128 * Set a 5 second timer just in case we don't hear from the 2129 * card again. 2130 */ 2131 ifp->if_timer = 5; 2132 2133 return; 2134 } 2135 sc->need_mcsetup = 0; 2136 2137 /* 2138 * Initialize multicast setup descriptor. 2139 */ 2140 mcsp->next = sc->cbl_base; 2141 mcsp->mb_head = NULL; 2142 mcsp->cb_status = 0; 2143 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2144 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2145 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2146 (void) fxp_mc_addrs(sc); 2147 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2148 sc->tx_queued = 1; 2149 2150 /* 2151 * Wait until command unit is not active. This should never 2152 * be the case when nothing is queued, but make sure anyway. 2153 */ 2154 count = 100; 2155 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2156 FXP_SCB_CUS_ACTIVE && --count) 2157 DELAY(10); 2158 if (count == 0) { 2159 device_printf(sc->dev, "command queue timeout\n"); 2160 return; 2161 } 2162 2163 /* 2164 * Start the multicast setup command. 2165 */ 2166 fxp_scb_wait(sc); 2167 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2168 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2169 2170 ifp->if_timer = 2; 2171 return; 2172} 2173 2174static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2175static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2176static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2177static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2178static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2179static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2180 2181#define UCODE(x) x, sizeof(x) 2182 2183struct ucode { 2184 u_int32_t revision; 2185 u_int32_t *ucode; 2186 int length; 2187 u_short int_delay_offset; 2188 u_short bundle_max_offset; 2189} ucode_table[] = { 2190 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2191 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2192 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2193 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2194 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2195 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2196 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2197 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2198 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2199 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 { 0, NULL, 0, 0, 0 } 2201}; 2202 2203static void 2204fxp_load_ucode(struct fxp_softc *sc) 2205{ 2206 struct ucode *uc; 2207 struct fxp_cb_ucode *cbp; 2208 2209 for (uc = ucode_table; uc->ucode != NULL; uc++) 2210 if (sc->revision == uc->revision) 2211 break; 2212 if (uc->ucode == NULL) 2213 return; 2214 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2215 cbp->cb_status = 0; 2216 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2217 cbp->link_addr = -1; /* (no) next command */ 2218 memcpy(cbp->ucode, uc->ucode, uc->length); 2219 if (uc->int_delay_offset) 2220 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2221 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2222 if (uc->bundle_max_offset) 2223 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2224 sc->tunable_bundle_max; 2225 /* 2226 * Download the ucode to the chip. 2227 */ 2228 fxp_scb_wait(sc); 2229 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2230 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2231 /* ...and wait for it to complete. */ 2232 fxp_dma_wait(&cbp->cb_status, sc); 2233 device_printf(sc->dev, 2234 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2235 sc->tunable_int_delay, 2236 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2237 sc->flags |= FXP_FLAG_UCODE; 2238} 2239 2240static int 2241sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2242{ 2243 int error, value; 2244 2245 value = *(int *)arg1; 2246 error = sysctl_handle_int(oidp, &value, 0, req); 2247 if (error || !req->newptr) 2248 return (error); 2249 if (value < low || value > high) 2250 return (EINVAL); 2251 *(int *)arg1 = value; 2252 return (0); 2253} 2254 2255/* 2256 * Interrupt delay is expressed in microseconds, a multiplier is used 2257 * to convert this to the appropriate clock ticks before using. 2258 */ 2259static int 2260sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2261{ 2262 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2263} 2264 2265static int 2266sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2267{ 2268 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2269} 2270