if_fxp.c revision 100846
1/*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 100846 2002-07-29 02:48:09Z luigi $ 29 */ 30 31/* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/sysctl.h> 43 44#include <net/if.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#ifdef NS 49#include <netns/ns.h> 50#include <netns/ns_if.h> 51#endif 52 53#include <net/bpf.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <net/ethernet.h> 61#include <net/if_arp.h> 62 63#include <vm/vm.h> /* for vtophys */ 64#include <vm/pmap.h> /* for vtophys */ 65#include <machine/clock.h> /* for DELAY */ 66 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69 70#include <pci/pcivar.h> 71#include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73#include <dev/mii/mii.h> 74#include <dev/mii/miivar.h> 75 76#include <dev/fxp/if_fxpreg.h> 77#include <dev/fxp/if_fxpvar.h> 78#include <dev/fxp/rcvbundl.h> 79 80MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81#include "miibus_if.h" 82 83/* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92#define RFA_ALIGNMENT_FUDGE 2 93 94/* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99static int tx_threshold = 64; 100 101/* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135}; 136 137struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140}; 141 142/* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0x1039, "Intel Pro/100 Ethernet" }, 163 { 0x103A, "Intel Pro/100 Ethernet" }, 164 { 0, NULL }, 165}; 166 167static int fxp_probe(device_t dev); 168static int fxp_attach(device_t dev); 169static int fxp_detach(device_t dev); 170static int fxp_shutdown(device_t dev); 171static int fxp_suspend(device_t dev); 172static int fxp_resume(device_t dev); 173 174static void fxp_intr(void *xsc); 175static void fxp_init(void *xsc); 176static void fxp_tick(void *xsc); 177static void fxp_powerstate_d0(device_t dev); 178static void fxp_start(struct ifnet *ifp); 179static void fxp_stop(struct fxp_softc *sc); 180static void fxp_release(struct fxp_softc *sc); 181static int fxp_ioctl(struct ifnet *ifp, u_long command, 182 caddr_t data); 183static void fxp_watchdog(struct ifnet *ifp); 184static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 185static int fxp_mc_addrs(struct fxp_softc *sc); 186static void fxp_mc_setup(struct fxp_softc *sc); 187static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 188 int autosize); 189static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 190 u_int16_t data); 191static void fxp_autosize_eeprom(struct fxp_softc *sc); 192static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 193 int offset, int words); 194static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 195 int offset, int words); 196static int fxp_ifmedia_upd(struct ifnet *ifp); 197static void fxp_ifmedia_sts(struct ifnet *ifp, 198 struct ifmediareq *ifmr); 199static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 200static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 201 struct ifmediareq *ifmr); 202static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 203static void fxp_miibus_writereg(device_t dev, int phy, int reg, 204 int value); 205static void fxp_load_ucode(struct fxp_softc *sc); 206static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 207 int low, int high); 208static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 209static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 210static __inline void fxp_lwcopy(volatile u_int32_t *src, 211 volatile u_int32_t *dst); 212static __inline void fxp_scb_wait(struct fxp_softc *sc); 213static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 214static __inline void fxp_dma_wait(volatile u_int16_t *status, 215 struct fxp_softc *sc); 216 217static device_method_t fxp_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, fxp_probe), 220 DEVMETHOD(device_attach, fxp_attach), 221 DEVMETHOD(device_detach, fxp_detach), 222 DEVMETHOD(device_shutdown, fxp_shutdown), 223 DEVMETHOD(device_suspend, fxp_suspend), 224 DEVMETHOD(device_resume, fxp_resume), 225 226 /* MII interface */ 227 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 228 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 229 230 { 0, 0 } 231}; 232 233static driver_t fxp_driver = { 234 "fxp", 235 fxp_methods, 236 sizeof(struct fxp_softc), 237}; 238 239static devclass_t fxp_devclass; 240 241DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 242DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 243DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 244 245/* 246 * Inline function to copy a 16-bit aligned 32-bit quantity. 247 */ 248static __inline void 249fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 250{ 251#ifdef __i386__ 252 *dst = *src; 253#else 254 volatile u_int16_t *a = (volatile u_int16_t *)src; 255 volatile u_int16_t *b = (volatile u_int16_t *)dst; 256 257 b[0] = a[0]; 258 b[1] = a[1]; 259#endif 260} 261 262/* 263 * Wait for the previous command to be accepted (but not necessarily 264 * completed). 265 */ 266static __inline void 267fxp_scb_wait(struct fxp_softc *sc) 268{ 269 int i = 10000; 270 271 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 272 DELAY(2); 273 if (i == 0) 274 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 275 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 276 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 277 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 278 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 279} 280 281static __inline void 282fxp_scb_cmd(struct fxp_softc *sc, int cmd) 283{ 284 285 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 286 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 287 fxp_scb_wait(sc); 288 } 289 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 290} 291 292static __inline void 293fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 294{ 295 int i = 10000; 296 297 while (!(*status & FXP_CB_STATUS_C) && --i) 298 DELAY(2); 299 if (i == 0) 300 device_printf(sc->dev, "DMA timeout\n"); 301} 302 303/* 304 * Return identification string if this is device is ours. 305 */ 306static int 307fxp_probe(device_t dev) 308{ 309 u_int16_t devid; 310 struct fxp_ident *ident; 311 312 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 313 devid = pci_get_device(dev); 314 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 315 if (ident->devid == devid) { 316 device_set_desc(dev, ident->name); 317 return (0); 318 } 319 } 320 } 321 return (ENXIO); 322} 323 324static void 325fxp_powerstate_d0(device_t dev) 326{ 327#if __FreeBSD_version >= 430002 328 u_int32_t iobase, membase, irq; 329 330 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 331 /* Save important PCI config data. */ 332 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 333 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 334 irq = pci_read_config(dev, PCIR_INTLINE, 4); 335 336 /* Reset the power state. */ 337 device_printf(dev, "chip is in D%d power mode " 338 "-- setting to D0\n", pci_get_powerstate(dev)); 339 340 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 341 342 /* Restore PCI config data. */ 343 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 344 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 345 pci_write_config(dev, PCIR_INTLINE, irq, 4); 346 } 347#endif 348} 349 350static int 351fxp_attach(device_t dev) 352{ 353 int error = 0; 354 struct fxp_softc *sc = device_get_softc(dev); 355 struct ifnet *ifp; 356 u_int32_t val; 357 u_int16_t data; 358 int i, rid, m1, m2, prefer_iomap; 359 int s; 360 361 bzero(sc, sizeof(*sc)); 362 sc->dev = dev; 363 callout_handle_init(&sc->stat_ch); 364 sysctl_ctx_init(&sc->sysctl_ctx); 365 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 366 MTX_DEF | MTX_RECURSE); 367 368 s = splimp(); 369 370 /* 371 * Enable bus mastering. Enable memory space too, in case 372 * BIOS/Prom forgot about it. 373 */ 374 val = pci_read_config(dev, PCIR_COMMAND, 2); 375 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 376 pci_write_config(dev, PCIR_COMMAND, val, 2); 377 val = pci_read_config(dev, PCIR_COMMAND, 2); 378 379 fxp_powerstate_d0(dev); 380 381 /* 382 * Figure out which we should try first - memory mapping or i/o mapping? 383 * We default to memory mapping. Then we accept an override from the 384 * command line. Then we check to see which one is enabled. 385 */ 386 m1 = PCIM_CMD_MEMEN; 387 m2 = PCIM_CMD_PORTEN; 388 prefer_iomap = 0; 389 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 390 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 391 m1 = PCIM_CMD_PORTEN; 392 m2 = PCIM_CMD_MEMEN; 393 } 394 395 if (val & m1) { 396 sc->rtp = 397 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 398 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 399 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 400 0, ~0, 1, RF_ACTIVE); 401 } 402 if (sc->mem == NULL && (val & m2)) { 403 sc->rtp = 404 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 405 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 406 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 407 0, ~0, 1, RF_ACTIVE); 408 } 409 410 if (!sc->mem) { 411 device_printf(dev, "could not map device registers\n"); 412 error = ENXIO; 413 goto fail; 414 } 415 if (bootverbose) { 416 device_printf(dev, "using %s space register mapping\n", 417 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 418 } 419 420 sc->sc_st = rman_get_bustag(sc->mem); 421 sc->sc_sh = rman_get_bushandle(sc->mem); 422 423 /* 424 * Allocate our interrupt. 425 */ 426 rid = 0; 427 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 428 RF_SHAREABLE | RF_ACTIVE); 429 if (sc->irq == NULL) { 430 device_printf(dev, "could not map interrupt\n"); 431 error = ENXIO; 432 goto fail; 433 } 434 435 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 436 fxp_intr, sc, &sc->ih); 437 if (error) { 438 device_printf(dev, "could not setup irq\n"); 439 goto fail; 440 } 441 442 /* 443 * Reset to a stable state. 444 */ 445 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 446 DELAY(10); 447 448 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 449 M_DEVBUF, M_NOWAIT | M_ZERO); 450 if (sc->cbl_base == NULL) 451 goto failmem; 452 453 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 454 M_NOWAIT | M_ZERO); 455 if (sc->fxp_stats == NULL) 456 goto failmem; 457 458 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 459 if (sc->mcsp == NULL) 460 goto failmem; 461 462 /* 463 * Pre-allocate our receive buffers. 464 */ 465 for (i = 0; i < FXP_NRFABUFS; i++) { 466 if (fxp_add_rfabuf(sc, NULL) != 0) { 467 goto failmem; 468 } 469 } 470 471 /* 472 * Find out how large of an SEEPROM we have. 473 */ 474 fxp_autosize_eeprom(sc); 475 476 /* 477 * Determine whether we must use the 503 serial interface. 478 */ 479 fxp_read_eeprom(sc, &data, 6, 1); 480 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 481 (data & FXP_PHY_SERIAL_ONLY)) 482 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 483 484 /* 485 * Create the sysctl tree 486 */ 487 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 488 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 489 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 490 if (sc->sysctl_tree == NULL) 491 goto fail; 492 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 493 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 494 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 495 "FXP driver receive interrupt microcode bundling delay"); 496 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 497 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 498 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 499 "FXP driver receive interrupt microcode bundle size limit"); 500 501 /* 502 * Pull in device tunables. 503 */ 504 sc->tunable_int_delay = TUNABLE_INT_DELAY; 505 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "int_delay", &sc->tunable_int_delay); 508 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 509 "bundle_max", &sc->tunable_bundle_max); 510 511 /* 512 * Find out the chip revision; lump all 82557 revs together. 513 */ 514 fxp_read_eeprom(sc, &data, 5, 1); 515 if ((data >> 8) == 1) 516 sc->revision = FXP_REV_82557; 517 else 518 sc->revision = pci_get_revid(dev); 519 520 /* 521 * Enable workarounds for certain chip revision deficiencies. 522 * 523 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 524 * some systems based a normal 82559 design, have a defect where 525 * the chip can cause a PCI protocol violation if it receives 526 * a CU_RESUME command when it is entering the IDLE state. The 527 * workaround is to disable Dynamic Standby Mode, so the chip never 528 * deasserts CLKRUN#, and always remains in an active state. 529 * 530 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 531 */ 532 i = pci_get_device(dev); 533 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 534 sc->revision >= FXP_REV_82559_A0) { 535 fxp_read_eeprom(sc, &data, 10, 1); 536 if (data & 0x02) { /* STB enable */ 537 u_int16_t cksum; 538 int i; 539 540 device_printf(dev, 541 "Disabling dynamic standby mode in EEPROM\n"); 542 data &= ~0x02; 543 fxp_write_eeprom(sc, &data, 10, 1); 544 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 545 cksum = 0; 546 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 547 fxp_read_eeprom(sc, &data, i, 1); 548 cksum += data; 549 } 550 i = (1 << sc->eeprom_size) - 1; 551 cksum = 0xBABA - cksum; 552 fxp_read_eeprom(sc, &data, i, 1); 553 fxp_write_eeprom(sc, &cksum, i, 1); 554 device_printf(dev, 555 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 556 i, data, cksum); 557#if 1 558 /* 559 * If the user elects to continue, try the software 560 * workaround, as it is better than nothing. 561 */ 562 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 563#endif 564 } 565 } 566 567 /* 568 * If we are not a 82557 chip, we can enable extended features. 569 */ 570 if (sc->revision != FXP_REV_82557) { 571 /* 572 * If MWI is enabled in the PCI configuration, and there 573 * is a valid cacheline size (8 or 16 dwords), then tell 574 * the board to turn on MWI. 575 */ 576 if (val & PCIM_CMD_MWRICEN && 577 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 578 sc->flags |= FXP_FLAG_MWI_ENABLE; 579 580 /* turn on the extended TxCB feature */ 581 sc->flags |= FXP_FLAG_EXT_TXCB; 582 583 /* enable reception of long frames for VLAN */ 584 sc->flags |= FXP_FLAG_LONG_PKT_EN; 585 } 586 587 /* 588 * Read MAC address. 589 */ 590 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 591 device_printf(dev, "Ethernet address %6D%s\n", 592 sc->arpcom.ac_enaddr, ":", 593 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 594 if (bootverbose) { 595 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 596 pci_get_vendor(dev), pci_get_device(dev), 597 pci_get_subvendor(dev), pci_get_subdevice(dev), 598 pci_get_revid(dev)); 599 fxp_read_eeprom(sc, &data, 10, 1); 600 device_printf(dev, "Dynamic Standby mode is %s\n", 601 data & 0x02 ? "enabled" : "disabled"); 602 } 603 604 /* 605 * If this is only a 10Mbps device, then there is no MII, and 606 * the PHY will use a serial interface instead. 607 * 608 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 609 * doesn't have a programming interface of any sort. The 610 * media is sensed automatically based on how the link partner 611 * is configured. This is, in essence, manual configuration. 612 */ 613 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 614 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 615 fxp_serial_ifmedia_sts); 616 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 617 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 618 } else { 619 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 620 fxp_ifmedia_sts)) { 621 device_printf(dev, "MII without any PHY!\n"); 622 error = ENXIO; 623 goto fail; 624 } 625 } 626 627 ifp = &sc->arpcom.ac_if; 628 ifp->if_unit = device_get_unit(dev); 629 ifp->if_name = "fxp"; 630 ifp->if_output = ether_output; 631 ifp->if_baudrate = 100000000; 632 ifp->if_init = fxp_init; 633 ifp->if_softc = sc; 634 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 635 ifp->if_ioctl = fxp_ioctl; 636 ifp->if_start = fxp_start; 637 ifp->if_watchdog = fxp_watchdog; 638 639 /* 640 * Attach the interface. 641 */ 642 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 643 644 /* 645 * Tell the upper layer(s) we support long frames. 646 */ 647 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 648 649 /* 650 * Let the system queue as many packets as we have available 651 * TX descriptors. 652 */ 653 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 654 655 splx(s); 656 return (0); 657 658failmem: 659 device_printf(dev, "Failed to malloc memory\n"); 660 error = ENOMEM; 661fail: 662 splx(s); 663 fxp_release(sc); 664 return (error); 665} 666 667/* 668 * release all resources 669 */ 670static void 671fxp_release(struct fxp_softc *sc) 672{ 673 674 bus_generic_detach(sc->dev); 675 if (sc->miibus) 676 device_delete_child(sc->dev, sc->miibus); 677 678 if (sc->cbl_base) 679 free(sc->cbl_base, M_DEVBUF); 680 if (sc->fxp_stats) 681 free(sc->fxp_stats, M_DEVBUF); 682 if (sc->mcsp) 683 free(sc->mcsp, M_DEVBUF); 684 if (sc->rfa_headm) 685 m_freem(sc->rfa_headm); 686 687 if (sc->ih) 688 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 689 if (sc->irq) 690 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 691 if (sc->mem) 692 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 693 694 sysctl_ctx_free(&sc->sysctl_ctx); 695 696 mtx_destroy(&sc->sc_mtx); 697} 698 699/* 700 * Detach interface. 701 */ 702static int 703fxp_detach(device_t dev) 704{ 705 struct fxp_softc *sc = device_get_softc(dev); 706 int s; 707 708 /* disable interrupts */ 709 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 710 711 s = splimp(); 712 713 /* 714 * Stop DMA and drop transmit queue. 715 */ 716 fxp_stop(sc); 717 718 /* 719 * Close down routes etc. 720 */ 721 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 722 723 /* 724 * Free all media structures. 725 */ 726 ifmedia_removeall(&sc->sc_media); 727 728 splx(s); 729 730 /* Release our allocated resources. */ 731 fxp_release(sc); 732 733 return (0); 734} 735 736/* 737 * Device shutdown routine. Called at system shutdown after sync. The 738 * main purpose of this routine is to shut off receiver DMA so that 739 * kernel memory doesn't get clobbered during warmboot. 740 */ 741static int 742fxp_shutdown(device_t dev) 743{ 744 /* 745 * Make sure that DMA is disabled prior to reboot. Not doing 746 * do could allow DMA to corrupt kernel memory during the 747 * reboot before the driver initializes. 748 */ 749 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 750 return (0); 751} 752 753/* 754 * Device suspend routine. Stop the interface and save some PCI 755 * settings in case the BIOS doesn't restore them properly on 756 * resume. 757 */ 758static int 759fxp_suspend(device_t dev) 760{ 761 struct fxp_softc *sc = device_get_softc(dev); 762 int i, s; 763 764 s = splimp(); 765 766 fxp_stop(sc); 767 768 for (i = 0; i < 5; i++) 769 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 770 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 771 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 772 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 773 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 774 775 sc->suspended = 1; 776 777 splx(s); 778 return (0); 779} 780 781/* 782 * Device resume routine. Restore some PCI settings in case the BIOS 783 * doesn't, re-enable busmastering, and restart the interface if 784 * appropriate. 785 */ 786static int 787fxp_resume(device_t dev) 788{ 789 struct fxp_softc *sc = device_get_softc(dev); 790 struct ifnet *ifp = &sc->sc_if; 791 u_int16_t pci_command; 792 int i, s; 793 794 s = splimp(); 795 796 fxp_powerstate_d0(dev); 797 798 /* better way to do this? */ 799 for (i = 0; i < 5; i++) 800 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 801 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 802 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 803 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 804 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 805 806 /* reenable busmastering */ 807 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 808 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 809 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 810 811 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 812 DELAY(10); 813 814 /* reinitialize interface if necessary */ 815 if (ifp->if_flags & IFF_UP) 816 fxp_init(sc); 817 818 sc->suspended = 0; 819 820 splx(s); 821 return (0); 822} 823 824static void 825fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 826{ 827 u_int16_t reg; 828 int x; 829 830 /* 831 * Shift in data. 832 */ 833 for (x = 1 << (length - 1); x; x >>= 1) { 834 if (data & x) 835 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 836 else 837 reg = FXP_EEPROM_EECS; 838 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 839 DELAY(1); 840 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 841 DELAY(1); 842 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 843 DELAY(1); 844 } 845} 846 847/* 848 * Read from the serial EEPROM. Basically, you manually shift in 849 * the read opcode (one bit at a time) and then shift in the address, 850 * and then you shift out the data (all of this one bit at a time). 851 * The word size is 16 bits, so you have to provide the address for 852 * every 16 bits of data. 853 */ 854static u_int16_t 855fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 856{ 857 u_int16_t reg, data; 858 int x; 859 860 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 861 /* 862 * Shift in read opcode. 863 */ 864 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 865 /* 866 * Shift in address. 867 */ 868 data = 0; 869 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 870 if (offset & x) 871 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 872 else 873 reg = FXP_EEPROM_EECS; 874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 875 DELAY(1); 876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 877 DELAY(1); 878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 879 DELAY(1); 880 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 881 data++; 882 if (autosize && reg == 0) { 883 sc->eeprom_size = data; 884 break; 885 } 886 } 887 /* 888 * Shift out data. 889 */ 890 data = 0; 891 reg = FXP_EEPROM_EECS; 892 for (x = 1 << 15; x; x >>= 1) { 893 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 894 DELAY(1); 895 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 896 data |= x; 897 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 898 DELAY(1); 899 } 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 901 DELAY(1); 902 903 return (data); 904} 905 906static void 907fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 908{ 909 int i; 910 911 /* 912 * Erase/write enable. 913 */ 914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 915 fxp_eeprom_shiftin(sc, 0x4, 3); 916 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 918 DELAY(1); 919 /* 920 * Shift in write opcode, address, data. 921 */ 922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 923 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 924 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 925 fxp_eeprom_shiftin(sc, data, 16); 926 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 927 DELAY(1); 928 /* 929 * Wait for EEPROM to finish up. 930 */ 931 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 932 DELAY(1); 933 for (i = 0; i < 1000; i++) { 934 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 935 break; 936 DELAY(50); 937 } 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 939 DELAY(1); 940 /* 941 * Erase/write disable. 942 */ 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 944 fxp_eeprom_shiftin(sc, 0x4, 3); 945 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 947 DELAY(1); 948} 949 950/* 951 * From NetBSD: 952 * 953 * Figure out EEPROM size. 954 * 955 * 559's can have either 64-word or 256-word EEPROMs, the 558 956 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 957 * talks about the existance of 16 to 256 word EEPROMs. 958 * 959 * The only known sizes are 64 and 256, where the 256 version is used 960 * by CardBus cards to store CIS information. 961 * 962 * The address is shifted in msb-to-lsb, and after the last 963 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 964 * after which follows the actual data. We try to detect this zero, by 965 * probing the data-out bit in the EEPROM control register just after 966 * having shifted in a bit. If the bit is zero, we assume we've 967 * shifted enough address bits. The data-out should be tri-state, 968 * before this, which should translate to a logical one. 969 */ 970static void 971fxp_autosize_eeprom(struct fxp_softc *sc) 972{ 973 974 /* guess maximum size of 256 words */ 975 sc->eeprom_size = 8; 976 977 /* autosize */ 978 (void) fxp_eeprom_getword(sc, 0, 1); 979} 980 981static void 982fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 983{ 984 int i; 985 986 for (i = 0; i < words; i++) 987 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 988} 989 990static void 991fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 992{ 993 int i; 994 995 for (i = 0; i < words; i++) 996 fxp_eeprom_putword(sc, offset + i, data[i]); 997} 998 999/* 1000 * Start packet transmission on the interface. 1001 */ 1002static void 1003fxp_start(struct ifnet *ifp) 1004{ 1005 struct fxp_softc *sc = ifp->if_softc; 1006 struct fxp_cb_tx *txp; 1007 1008 /* 1009 * See if we need to suspend xmit until the multicast filter 1010 * has been reprogrammed (which can only be done at the head 1011 * of the command chain). 1012 */ 1013 if (sc->need_mcsetup) { 1014 return; 1015 } 1016 1017 txp = NULL; 1018 1019 /* 1020 * We're finished if there is nothing more to add to the list or if 1021 * we're all filled up with buffers to transmit. 1022 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1023 * a NOP command when needed. 1024 */ 1025 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1026 struct mbuf *m, *mb_head; 1027 int segment; 1028 1029 /* 1030 * Grab a packet to transmit. 1031 */ 1032 IF_DEQUEUE(&ifp->if_snd, mb_head); 1033 1034 /* 1035 * Get pointer to next available tx desc. 1036 */ 1037 txp = sc->cbl_last->next; 1038 1039 /* 1040 * Go through each of the mbufs in the chain and initialize 1041 * the transmit buffer descriptors with the physical address 1042 * and size of the mbuf. 1043 */ 1044tbdinit: 1045 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1046 if (m->m_len != 0) { 1047 if (segment == FXP_NTXSEG) 1048 break; 1049 txp->tbd[segment].tb_addr = 1050 vtophys(mtod(m, vm_offset_t)); 1051 txp->tbd[segment].tb_size = m->m_len; 1052 segment++; 1053 } 1054 } 1055 if (m != NULL) { 1056 struct mbuf *mn; 1057 1058 /* 1059 * We ran out of segments. We have to recopy this 1060 * mbuf chain first. Bail out if we can't get the 1061 * new buffers. 1062 */ 1063 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1064 if (mn == NULL) { 1065 m_freem(mb_head); 1066 break; 1067 } 1068 if (mb_head->m_pkthdr.len > MHLEN) { 1069 MCLGET(mn, M_DONTWAIT); 1070 if ((mn->m_flags & M_EXT) == 0) { 1071 m_freem(mn); 1072 m_freem(mb_head); 1073 break; 1074 } 1075 } 1076 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1077 mtod(mn, caddr_t)); 1078 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1079 m_freem(mb_head); 1080 mb_head = mn; 1081 goto tbdinit; 1082 } 1083 1084 txp->tbd_number = segment; 1085 txp->mb_head = mb_head; 1086 txp->cb_status = 0; 1087 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1088 txp->cb_command = 1089 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1090 FXP_CB_COMMAND_S; 1091 } else { 1092 txp->cb_command = 1093 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1094 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1095 /* 1096 * Set a 5 second timer just in case we don't hear 1097 * from the card again. 1098 */ 1099 ifp->if_timer = 5; 1100 } 1101 txp->tx_threshold = tx_threshold; 1102 1103 /* 1104 * Advance the end of list forward. 1105 */ 1106 1107#ifdef __alpha__ 1108 /* 1109 * On platforms which can't access memory in 16-bit 1110 * granularities, we must prevent the card from DMA'ing 1111 * up the status while we update the command field. 1112 * This could cause us to overwrite the completion status. 1113 */ 1114 atomic_clear_short(&sc->cbl_last->cb_command, 1115 FXP_CB_COMMAND_S); 1116#else 1117 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1118#endif /*__alpha__*/ 1119 sc->cbl_last = txp; 1120 1121 /* 1122 * Advance the beginning of the list forward if there are 1123 * no other packets queued (when nothing is queued, cbl_first 1124 * sits on the last TxCB that was sent out). 1125 */ 1126 if (sc->tx_queued == 0) 1127 sc->cbl_first = txp; 1128 1129 sc->tx_queued++; 1130 1131 /* 1132 * Pass packet to bpf if there is a listener. 1133 */ 1134 if (ifp->if_bpf) 1135 bpf_mtap(ifp, mb_head); 1136 } 1137 1138 /* 1139 * We're finished. If we added to the list, issue a RESUME to get DMA 1140 * going again if suspended. 1141 */ 1142 if (txp != NULL) { 1143 fxp_scb_wait(sc); 1144 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1145 } 1146} 1147 1148static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1149 1150#ifdef DEVICE_POLLING 1151static poll_handler_t fxp_poll; 1152 1153static void 1154fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1155{ 1156 struct fxp_softc *sc = ifp->if_softc; 1157 u_int8_t statack; 1158 1159 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1160 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1161 return; 1162 } 1163 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1164 FXP_SCB_STATACK_FR; 1165 if (cmd == POLL_AND_CHECK_STATUS) { 1166 u_int8_t tmp; 1167 1168 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1169 if (tmp == 0xff || tmp == 0) 1170 return; /* nothing to do */ 1171 tmp &= ~statack; 1172 /* ack what we can */ 1173 if (tmp != 0) 1174 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1175 statack |= tmp; 1176 } 1177 fxp_intr_body(sc, statack, count); 1178} 1179#endif /* DEVICE_POLLING */ 1180 1181/* 1182 * Process interface interrupts. 1183 */ 1184static void 1185fxp_intr(void *xsc) 1186{ 1187 struct fxp_softc *sc = xsc; 1188 u_int8_t statack; 1189 1190#ifdef DEVICE_POLLING 1191 struct ifnet *ifp = &sc->sc_if; 1192 1193 if (ifp->if_ipending & IFF_POLLING) 1194 return; 1195 if (ether_poll_register(fxp_poll, ifp)) { 1196 /* disable interrupts */ 1197 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1198 fxp_poll(ifp, 0, 1); 1199 return; 1200 } 1201#endif 1202 1203 if (sc->suspended) { 1204 return; 1205 } 1206 1207 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1208 /* 1209 * It should not be possible to have all bits set; the 1210 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1211 * all bits are set, this may indicate that the card has 1212 * been physically ejected, so ignore it. 1213 */ 1214 if (statack == 0xff) 1215 return; 1216 1217 /* 1218 * First ACK all the interrupts in this pass. 1219 */ 1220 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1221 fxp_intr_body(sc, statack, -1); 1222 } 1223} 1224 1225static void 1226fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1227{ 1228 struct ifnet *ifp = &sc->sc_if; 1229 1230 /* 1231 * Free any finished transmit mbuf chains. 1232 * 1233 * Handle the CNA event likt a CXTNO event. It used to 1234 * be that this event (control unit not ready) was not 1235 * encountered, but it is now with the SMPng modifications. 1236 * The exact sequence of events that occur when the interface 1237 * is brought up are different now, and if this event 1238 * goes unhandled, the configuration/rxfilter setup sequence 1239 * can stall for several seconds. The result is that no 1240 * packets go out onto the wire for about 5 to 10 seconds 1241 * after the interface is ifconfig'ed for the first time. 1242 */ 1243 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1244 struct fxp_cb_tx *txp; 1245 1246 for (txp = sc->cbl_first; sc->tx_queued && 1247 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1248 txp = txp->next) { 1249 if (txp->mb_head != NULL) { 1250 m_freem(txp->mb_head); 1251 txp->mb_head = NULL; 1252 } 1253 sc->tx_queued--; 1254 } 1255 sc->cbl_first = txp; 1256 if (sc->tx_queued == 0) { 1257 ifp->if_timer = 0; 1258 if (sc->need_mcsetup) 1259 fxp_mc_setup(sc); 1260 } else 1261 ifp->if_timer = 5; 1262 1263 /* 1264 * Try to start more packets transmitting. 1265 */ 1266 if (ifp->if_snd.ifq_head != NULL) 1267 fxp_start(ifp); 1268 } 1269 /* 1270 * Process receiver interrupts. If a no-resource (RNR) 1271 * condition exists, get whatever packets we can and 1272 * re-start the receiver. 1273 */ 1274 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1275 struct mbuf *m; 1276 struct fxp_rfa *rfa; 1277rcvloop: 1278 m = sc->rfa_headm; 1279 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1280 RFA_ALIGNMENT_FUDGE); 1281 1282#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1283 if (count < 0 || count-- > 0) 1284#endif 1285 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1286 /* 1287 * Remove first packet from the chain. 1288 */ 1289 sc->rfa_headm = m->m_next; 1290 m->m_next = NULL; 1291 1292 /* 1293 * Add a new buffer to the receive chain. 1294 * If this fails, the old buffer is recycled 1295 * instead. 1296 */ 1297 if (fxp_add_rfabuf(sc, m) == 0) { 1298 struct ether_header *eh; 1299 int total_len; 1300 1301 total_len = rfa->actual_size & 1302 (MCLBYTES - 1); 1303 if (total_len < 1304 sizeof(struct ether_header)) { 1305 m_freem(m); 1306 goto rcvloop; 1307 } 1308 1309 /* 1310 * Drop the packet if it has CRC 1311 * errors. This test is only needed 1312 * when doing 802.1q VLAN on the 82557 1313 * chip. 1314 */ 1315 if (rfa->rfa_status & 1316 FXP_RFA_STATUS_CRC) { 1317 m_freem(m); 1318 goto rcvloop; 1319 } 1320 1321 m->m_pkthdr.rcvif = ifp; 1322 m->m_pkthdr.len = m->m_len = total_len; 1323 eh = mtod(m, struct ether_header *); 1324 m->m_data += 1325 sizeof(struct ether_header); 1326 m->m_len -= 1327 sizeof(struct ether_header); 1328 m->m_pkthdr.len = m->m_len; 1329 ether_input(ifp, eh, m); 1330 } 1331 goto rcvloop; 1332 } 1333 if (statack & FXP_SCB_STATACK_RNR) { 1334 fxp_scb_wait(sc); 1335 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1336 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1337 RFA_ALIGNMENT_FUDGE); 1338 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1339 } 1340 } 1341} 1342 1343/* 1344 * Update packet in/out/collision statistics. The i82557 doesn't 1345 * allow you to access these counters without doing a fairly 1346 * expensive DMA to get _all_ of the statistics it maintains, so 1347 * we do this operation here only once per second. The statistics 1348 * counters in the kernel are updated from the previous dump-stats 1349 * DMA and then a new dump-stats DMA is started. The on-chip 1350 * counters are zeroed when the DMA completes. If we can't start 1351 * the DMA immediately, we don't wait - we just prepare to read 1352 * them again next time. 1353 */ 1354static void 1355fxp_tick(void *xsc) 1356{ 1357 struct fxp_softc *sc = xsc; 1358 struct ifnet *ifp = &sc->sc_if; 1359 struct fxp_stats *sp = sc->fxp_stats; 1360 struct fxp_cb_tx *txp; 1361 int s; 1362 1363 ifp->if_opackets += sp->tx_good; 1364 ifp->if_collisions += sp->tx_total_collisions; 1365 if (sp->rx_good) { 1366 ifp->if_ipackets += sp->rx_good; 1367 sc->rx_idle_secs = 0; 1368 } else { 1369 /* 1370 * Receiver's been idle for another second. 1371 */ 1372 sc->rx_idle_secs++; 1373 } 1374 ifp->if_ierrors += 1375 sp->rx_crc_errors + 1376 sp->rx_alignment_errors + 1377 sp->rx_rnr_errors + 1378 sp->rx_overrun_errors; 1379 /* 1380 * If any transmit underruns occured, bump up the transmit 1381 * threshold by another 512 bytes (64 * 8). 1382 */ 1383 if (sp->tx_underruns) { 1384 ifp->if_oerrors += sp->tx_underruns; 1385 if (tx_threshold < 192) 1386 tx_threshold += 64; 1387 } 1388 s = splimp(); 1389 /* 1390 * Release any xmit buffers that have completed DMA. This isn't 1391 * strictly necessary to do here, but it's advantagous for mbufs 1392 * with external storage to be released in a timely manner rather 1393 * than being defered for a potentially long time. This limits 1394 * the delay to a maximum of one second. 1395 */ 1396 for (txp = sc->cbl_first; sc->tx_queued && 1397 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1398 txp = txp->next) { 1399 if (txp->mb_head != NULL) { 1400 m_freem(txp->mb_head); 1401 txp->mb_head = NULL; 1402 } 1403 sc->tx_queued--; 1404 } 1405 sc->cbl_first = txp; 1406 /* 1407 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1408 * then assume the receiver has locked up and attempt to clear 1409 * the condition by reprogramming the multicast filter. This is 1410 * a work-around for a bug in the 82557 where the receiver locks 1411 * up if it gets certain types of garbage in the syncronization 1412 * bits prior to the packet header. This bug is supposed to only 1413 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1414 * mode as well (perhaps due to a 10/100 speed transition). 1415 */ 1416 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1417 sc->rx_idle_secs = 0; 1418 fxp_mc_setup(sc); 1419 } 1420 /* 1421 * If there is no pending command, start another stats 1422 * dump. Otherwise punt for now. 1423 */ 1424 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1425 /* 1426 * Start another stats dump. 1427 */ 1428 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1429 } else { 1430 /* 1431 * A previous command is still waiting to be accepted. 1432 * Just zero our copy of the stats and wait for the 1433 * next timer event to update them. 1434 */ 1435 sp->tx_good = 0; 1436 sp->tx_underruns = 0; 1437 sp->tx_total_collisions = 0; 1438 1439 sp->rx_good = 0; 1440 sp->rx_crc_errors = 0; 1441 sp->rx_alignment_errors = 0; 1442 sp->rx_rnr_errors = 0; 1443 sp->rx_overrun_errors = 0; 1444 } 1445 if (sc->miibus != NULL) 1446 mii_tick(device_get_softc(sc->miibus)); 1447 splx(s); 1448 /* 1449 * Schedule another timeout one second from now. 1450 */ 1451 sc->stat_ch = timeout(fxp_tick, sc, hz); 1452} 1453 1454/* 1455 * Stop the interface. Cancels the statistics updater and resets 1456 * the interface. 1457 */ 1458static void 1459fxp_stop(struct fxp_softc *sc) 1460{ 1461 struct ifnet *ifp = &sc->sc_if; 1462 struct fxp_cb_tx *txp; 1463 int i; 1464 1465 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1466 ifp->if_timer = 0; 1467 1468#ifdef DEVICE_POLLING 1469 ether_poll_deregister(ifp); 1470#endif 1471 /* 1472 * Cancel stats updater. 1473 */ 1474 untimeout(fxp_tick, sc, sc->stat_ch); 1475 1476 /* 1477 * Issue software reset, which also unloads the microcode. 1478 */ 1479 sc->flags &= ~FXP_FLAG_UCODE; 1480 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1481 DELAY(50); 1482 1483 /* 1484 * Release any xmit buffers. 1485 */ 1486 txp = sc->cbl_base; 1487 if (txp != NULL) { 1488 for (i = 0; i < FXP_NTXCB; i++) { 1489 if (txp[i].mb_head != NULL) { 1490 m_freem(txp[i].mb_head); 1491 txp[i].mb_head = NULL; 1492 } 1493 } 1494 } 1495 sc->tx_queued = 0; 1496 1497 /* 1498 * Free all the receive buffers then reallocate/reinitialize 1499 */ 1500 if (sc->rfa_headm != NULL) 1501 m_freem(sc->rfa_headm); 1502 sc->rfa_headm = NULL; 1503 sc->rfa_tailm = NULL; 1504 for (i = 0; i < FXP_NRFABUFS; i++) { 1505 if (fxp_add_rfabuf(sc, NULL) != 0) { 1506 /* 1507 * This "can't happen" - we're at splimp() 1508 * and we just freed all the buffers we need 1509 * above. 1510 */ 1511 panic("fxp_stop: no buffers!"); 1512 } 1513 } 1514} 1515 1516/* 1517 * Watchdog/transmission transmit timeout handler. Called when a 1518 * transmission is started on the interface, but no interrupt is 1519 * received before the timeout. This usually indicates that the 1520 * card has wedged for some reason. 1521 */ 1522static void 1523fxp_watchdog(struct ifnet *ifp) 1524{ 1525 struct fxp_softc *sc = ifp->if_softc; 1526 1527 device_printf(sc->dev, "device timeout\n"); 1528 ifp->if_oerrors++; 1529 1530 fxp_init(sc); 1531} 1532 1533static void 1534fxp_init(void *xsc) 1535{ 1536 struct fxp_softc *sc = xsc; 1537 struct ifnet *ifp = &sc->sc_if; 1538 struct fxp_cb_config *cbp; 1539 struct fxp_cb_ias *cb_ias; 1540 struct fxp_cb_tx *txp; 1541 struct fxp_cb_mcs *mcsp; 1542 int i, prm, s; 1543 1544 s = splimp(); 1545 /* 1546 * Cancel any pending I/O 1547 */ 1548 fxp_stop(sc); 1549 1550 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1551 1552 /* 1553 * Initialize base of CBL and RFA memory. Loading with zero 1554 * sets it up for regular linear addressing. 1555 */ 1556 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1557 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1558 1559 fxp_scb_wait(sc); 1560 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1561 1562 /* 1563 * Initialize base of dump-stats buffer. 1564 */ 1565 fxp_scb_wait(sc); 1566 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1567 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1568 1569 /* 1570 * Attempt to load microcode if requested. 1571 */ 1572 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1573 fxp_load_ucode(sc); 1574 1575 /* 1576 * Initialize the multicast address list. 1577 */ 1578 if (fxp_mc_addrs(sc)) { 1579 mcsp = sc->mcsp; 1580 mcsp->cb_status = 0; 1581 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1582 mcsp->link_addr = -1; 1583 /* 1584 * Start the multicast setup command. 1585 */ 1586 fxp_scb_wait(sc); 1587 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1588 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1589 /* ...and wait for it to complete. */ 1590 fxp_dma_wait(&mcsp->cb_status, sc); 1591 } 1592 1593 /* 1594 * We temporarily use memory that contains the TxCB list to 1595 * construct the config CB. The TxCB list memory is rebuilt 1596 * later. 1597 */ 1598 cbp = (struct fxp_cb_config *) sc->cbl_base; 1599 1600 /* 1601 * This bcopy is kind of disgusting, but there are a bunch of must be 1602 * zero and must be one bits in this structure and this is the easiest 1603 * way to initialize them all to proper values. 1604 */ 1605 bcopy(fxp_cb_config_template, 1606 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1607 sizeof(fxp_cb_config_template)); 1608 1609 cbp->cb_status = 0; 1610 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1611 cbp->link_addr = -1; /* (no) next command */ 1612 cbp->byte_count = 22; /* (22) bytes to config */ 1613 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1614 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1615 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1616 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1617 cbp->type_enable = 0; /* actually reserved */ 1618 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1619 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1620 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1621 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1622 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1623 cbp->late_scb = 0; /* (don't) defer SCB update */ 1624 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1625 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1626 cbp->ci_int = 1; /* interrupt on CU idle */ 1627 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1628 cbp->ext_stats_dis = 1; /* disable extended counters */ 1629 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1630 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1631 cbp->disc_short_rx = !prm; /* discard short packets */ 1632 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1633 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1634 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1635 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1636 cbp->csma_dis = 0; /* (don't) disable link */ 1637 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1638 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1639 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1640 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1641 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1642 cbp->nsai = 1; /* (don't) disable source addr insert */ 1643 cbp->preamble_length = 2; /* (7 byte) preamble */ 1644 cbp->loopback = 0; /* (don't) loopback */ 1645 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1646 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1647 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1648 cbp->promiscuous = prm; /* promiscuous mode */ 1649 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1650 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1651 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1652 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1653 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1654 1655 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1656 cbp->padding = 1; /* (do) pad short tx packets */ 1657 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1658 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1659 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1660 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1661 /* must set wake_en in PMCSR also */ 1662 cbp->force_fdx = 0; /* (don't) force full duplex */ 1663 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1664 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1665 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1666 1667 if (sc->revision == FXP_REV_82557) { 1668 /* 1669 * The 82557 has no hardware flow control, the values 1670 * below are the defaults for the chip. 1671 */ 1672 cbp->fc_delay_lsb = 0; 1673 cbp->fc_delay_msb = 0x40; 1674 cbp->pri_fc_thresh = 3; 1675 cbp->tx_fc_dis = 0; 1676 cbp->rx_fc_restop = 0; 1677 cbp->rx_fc_restart = 0; 1678 cbp->fc_filter = 0; 1679 cbp->pri_fc_loc = 1; 1680 } else { 1681 cbp->fc_delay_lsb = 0x1f; 1682 cbp->fc_delay_msb = 0x01; 1683 cbp->pri_fc_thresh = 3; 1684 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1685 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1686 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1687 cbp->fc_filter = !prm; /* drop FC frames to host */ 1688 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1689 } 1690 1691 /* 1692 * Start the config command/DMA. 1693 */ 1694 fxp_scb_wait(sc); 1695 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1696 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1697 /* ...and wait for it to complete. */ 1698 fxp_dma_wait(&cbp->cb_status, sc); 1699 1700 /* 1701 * Now initialize the station address. Temporarily use the TxCB 1702 * memory area like we did above for the config CB. 1703 */ 1704 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1705 cb_ias->cb_status = 0; 1706 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1707 cb_ias->link_addr = -1; 1708 bcopy(sc->arpcom.ac_enaddr, 1709 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1710 sizeof(sc->arpcom.ac_enaddr)); 1711 1712 /* 1713 * Start the IAS (Individual Address Setup) command/DMA. 1714 */ 1715 fxp_scb_wait(sc); 1716 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1717 /* ...and wait for it to complete. */ 1718 fxp_dma_wait(&cb_ias->cb_status, sc); 1719 1720 /* 1721 * Initialize transmit control block (TxCB) list. 1722 */ 1723 1724 txp = sc->cbl_base; 1725 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1726 for (i = 0; i < FXP_NTXCB; i++) { 1727 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1728 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1729 txp[i].link_addr = 1730 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1731 if (sc->flags & FXP_FLAG_EXT_TXCB) 1732 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1733 else 1734 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1735 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1736 } 1737 /* 1738 * Set the suspend flag on the first TxCB and start the control 1739 * unit. It will execute the NOP and then suspend. 1740 */ 1741 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1742 sc->cbl_first = sc->cbl_last = txp; 1743 sc->tx_queued = 1; 1744 1745 fxp_scb_wait(sc); 1746 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1747 1748 /* 1749 * Initialize receiver buffer area - RFA. 1750 */ 1751 fxp_scb_wait(sc); 1752 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1753 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1754 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1755 1756 /* 1757 * Set current media. 1758 */ 1759 if (sc->miibus != NULL) 1760 mii_mediachg(device_get_softc(sc->miibus)); 1761 1762 ifp->if_flags |= IFF_RUNNING; 1763 ifp->if_flags &= ~IFF_OACTIVE; 1764 1765 /* 1766 * Enable interrupts. 1767 */ 1768 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1769 splx(s); 1770 1771 /* 1772 * Start stats updater. 1773 */ 1774 sc->stat_ch = timeout(fxp_tick, sc, hz); 1775} 1776 1777static int 1778fxp_serial_ifmedia_upd(struct ifnet *ifp) 1779{ 1780 1781 return (0); 1782} 1783 1784static void 1785fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1786{ 1787 1788 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1789} 1790 1791/* 1792 * Change media according to request. 1793 */ 1794static int 1795fxp_ifmedia_upd(struct ifnet *ifp) 1796{ 1797 struct fxp_softc *sc = ifp->if_softc; 1798 struct mii_data *mii; 1799 1800 mii = device_get_softc(sc->miibus); 1801 mii_mediachg(mii); 1802 return (0); 1803} 1804 1805/* 1806 * Notify the world which media we're using. 1807 */ 1808static void 1809fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1810{ 1811 struct fxp_softc *sc = ifp->if_softc; 1812 struct mii_data *mii; 1813 1814 mii = device_get_softc(sc->miibus); 1815 mii_pollstat(mii); 1816 ifmr->ifm_active = mii->mii_media_active; 1817 ifmr->ifm_status = mii->mii_media_status; 1818 1819 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1820 sc->cu_resume_bug = 1; 1821 else 1822 sc->cu_resume_bug = 0; 1823} 1824 1825/* 1826 * Add a buffer to the end of the RFA buffer list. 1827 * Return 0 if successful, 1 for failure. A failure results in 1828 * adding the 'oldm' (if non-NULL) on to the end of the list - 1829 * tossing out its old contents and recycling it. 1830 * The RFA struct is stuck at the beginning of mbuf cluster and the 1831 * data pointer is fixed up to point just past it. 1832 */ 1833static int 1834fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1835{ 1836 u_int32_t v; 1837 struct mbuf *m; 1838 struct fxp_rfa *rfa, *p_rfa; 1839 1840 MGETHDR(m, M_DONTWAIT, MT_DATA); 1841 if (m != NULL) { 1842 MCLGET(m, M_DONTWAIT); 1843 if ((m->m_flags & M_EXT) == 0) { 1844 m_freem(m); 1845 if (oldm == NULL) 1846 return 1; 1847 m = oldm; 1848 m->m_data = m->m_ext.ext_buf; 1849 } 1850 } else { 1851 if (oldm == NULL) 1852 return 1; 1853 m = oldm; 1854 m->m_data = m->m_ext.ext_buf; 1855 } 1856 1857 /* 1858 * Move the data pointer up so that the incoming data packet 1859 * will be 32-bit aligned. 1860 */ 1861 m->m_data += RFA_ALIGNMENT_FUDGE; 1862 1863 /* 1864 * Get a pointer to the base of the mbuf cluster and move 1865 * data start past it. 1866 */ 1867 rfa = mtod(m, struct fxp_rfa *); 1868 m->m_data += sizeof(struct fxp_rfa); 1869 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1870 1871 /* 1872 * Initialize the rest of the RFA. Note that since the RFA 1873 * is misaligned, we cannot store values directly. Instead, 1874 * we use an optimized, inline copy. 1875 */ 1876 1877 rfa->rfa_status = 0; 1878 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1879 rfa->actual_size = 0; 1880 1881 v = -1; 1882 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1883 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1884 1885 /* 1886 * If there are other buffers already on the list, attach this 1887 * one to the end by fixing up the tail to point to this one. 1888 */ 1889 if (sc->rfa_headm != NULL) { 1890 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1891 RFA_ALIGNMENT_FUDGE); 1892 sc->rfa_tailm->m_next = m; 1893 v = vtophys(rfa); 1894 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1895 p_rfa->rfa_control = 0; 1896 } else { 1897 sc->rfa_headm = m; 1898 } 1899 sc->rfa_tailm = m; 1900 1901 return (m == oldm); 1902} 1903 1904static volatile int 1905fxp_miibus_readreg(device_t dev, int phy, int reg) 1906{ 1907 struct fxp_softc *sc = device_get_softc(dev); 1908 int count = 10000; 1909 int value; 1910 1911 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1912 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1913 1914 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1915 && count--) 1916 DELAY(10); 1917 1918 if (count <= 0) 1919 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1920 1921 return (value & 0xffff); 1922} 1923 1924static void 1925fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1926{ 1927 struct fxp_softc *sc = device_get_softc(dev); 1928 int count = 10000; 1929 1930 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1931 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1932 (value & 0xffff)); 1933 1934 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1935 count--) 1936 DELAY(10); 1937 1938 if (count <= 0) 1939 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1940} 1941 1942static int 1943fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1944{ 1945 struct fxp_softc *sc = ifp->if_softc; 1946 struct ifreq *ifr = (struct ifreq *)data; 1947 struct mii_data *mii; 1948 int s, error = 0; 1949 1950 s = splimp(); 1951 1952 switch (command) { 1953 case SIOCSIFADDR: 1954 case SIOCGIFADDR: 1955 case SIOCSIFMTU: 1956 error = ether_ioctl(ifp, command, data); 1957 break; 1958 1959 case SIOCSIFFLAGS: 1960 if (ifp->if_flags & IFF_ALLMULTI) 1961 sc->flags |= FXP_FLAG_ALL_MCAST; 1962 else 1963 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1964 1965 /* 1966 * If interface is marked up and not running, then start it. 1967 * If it is marked down and running, stop it. 1968 * XXX If it's up then re-initialize it. This is so flags 1969 * such as IFF_PROMISC are handled. 1970 */ 1971 if (ifp->if_flags & IFF_UP) { 1972 fxp_init(sc); 1973 } else { 1974 if (ifp->if_flags & IFF_RUNNING) 1975 fxp_stop(sc); 1976 } 1977 break; 1978 1979 case SIOCADDMULTI: 1980 case SIOCDELMULTI: 1981 if (ifp->if_flags & IFF_ALLMULTI) 1982 sc->flags |= FXP_FLAG_ALL_MCAST; 1983 else 1984 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1985 /* 1986 * Multicast list has changed; set the hardware filter 1987 * accordingly. 1988 */ 1989 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 1990 fxp_mc_setup(sc); 1991 /* 1992 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 1993 * again rather than else {}. 1994 */ 1995 if (sc->flags & FXP_FLAG_ALL_MCAST) 1996 fxp_init(sc); 1997 error = 0; 1998 break; 1999 2000 case SIOCSIFMEDIA: 2001 case SIOCGIFMEDIA: 2002 if (sc->miibus != NULL) { 2003 mii = device_get_softc(sc->miibus); 2004 error = ifmedia_ioctl(ifp, ifr, 2005 &mii->mii_media, command); 2006 } else { 2007 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2008 } 2009 break; 2010 2011 default: 2012 error = EINVAL; 2013 } 2014 splx(s); 2015 return (error); 2016} 2017 2018/* 2019 * Fill in the multicast address list and return number of entries. 2020 */ 2021static int 2022fxp_mc_addrs(struct fxp_softc *sc) 2023{ 2024 struct fxp_cb_mcs *mcsp = sc->mcsp; 2025 struct ifnet *ifp = &sc->sc_if; 2026 struct ifmultiaddr *ifma; 2027 int nmcasts; 2028 2029 nmcasts = 0; 2030 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2031#if __FreeBSD_version < 500000 2032 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2033#else 2034 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2035#endif 2036 if (ifma->ifma_addr->sa_family != AF_LINK) 2037 continue; 2038 if (nmcasts >= MAXMCADDR) { 2039 sc->flags |= FXP_FLAG_ALL_MCAST; 2040 nmcasts = 0; 2041 break; 2042 } 2043 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2044 (void *)(uintptr_t)(volatile void *) 2045 &sc->mcsp->mc_addr[nmcasts][0], 6); 2046 nmcasts++; 2047 } 2048 } 2049 mcsp->mc_cnt = nmcasts * 6; 2050 return (nmcasts); 2051} 2052 2053/* 2054 * Program the multicast filter. 2055 * 2056 * We have an artificial restriction that the multicast setup command 2057 * must be the first command in the chain, so we take steps to ensure 2058 * this. By requiring this, it allows us to keep up the performance of 2059 * the pre-initialized command ring (esp. link pointers) by not actually 2060 * inserting the mcsetup command in the ring - i.e. its link pointer 2061 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2062 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2063 * lead into the regular TxCB ring when it completes. 2064 * 2065 * This function must be called at splimp. 2066 */ 2067static void 2068fxp_mc_setup(struct fxp_softc *sc) 2069{ 2070 struct fxp_cb_mcs *mcsp = sc->mcsp; 2071 struct ifnet *ifp = &sc->sc_if; 2072 int count; 2073 2074 /* 2075 * If there are queued commands, we must wait until they are all 2076 * completed. If we are already waiting, then add a NOP command 2077 * with interrupt option so that we're notified when all commands 2078 * have been completed - fxp_start() ensures that no additional 2079 * TX commands will be added when need_mcsetup is true. 2080 */ 2081 if (sc->tx_queued) { 2082 struct fxp_cb_tx *txp; 2083 2084 /* 2085 * need_mcsetup will be true if we are already waiting for the 2086 * NOP command to be completed (see below). In this case, bail. 2087 */ 2088 if (sc->need_mcsetup) 2089 return; 2090 sc->need_mcsetup = 1; 2091 2092 /* 2093 * Add a NOP command with interrupt so that we are notified 2094 * when all TX commands have been processed. 2095 */ 2096 txp = sc->cbl_last->next; 2097 txp->mb_head = NULL; 2098 txp->cb_status = 0; 2099 txp->cb_command = FXP_CB_COMMAND_NOP | 2100 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2101 /* 2102 * Advance the end of list forward. 2103 */ 2104 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2105 sc->cbl_last = txp; 2106 sc->tx_queued++; 2107 /* 2108 * Issue a resume in case the CU has just suspended. 2109 */ 2110 fxp_scb_wait(sc); 2111 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2112 /* 2113 * Set a 5 second timer just in case we don't hear from the 2114 * card again. 2115 */ 2116 ifp->if_timer = 5; 2117 2118 return; 2119 } 2120 sc->need_mcsetup = 0; 2121 2122 /* 2123 * Initialize multicast setup descriptor. 2124 */ 2125 mcsp->next = sc->cbl_base; 2126 mcsp->mb_head = NULL; 2127 mcsp->cb_status = 0; 2128 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2129 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2130 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2131 (void) fxp_mc_addrs(sc); 2132 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2133 sc->tx_queued = 1; 2134 2135 /* 2136 * Wait until command unit is not active. This should never 2137 * be the case when nothing is queued, but make sure anyway. 2138 */ 2139 count = 100; 2140 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2141 FXP_SCB_CUS_ACTIVE && --count) 2142 DELAY(10); 2143 if (count == 0) { 2144 device_printf(sc->dev, "command queue timeout\n"); 2145 return; 2146 } 2147 2148 /* 2149 * Start the multicast setup command. 2150 */ 2151 fxp_scb_wait(sc); 2152 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2153 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2154 2155 ifp->if_timer = 2; 2156 return; 2157} 2158 2159static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2160static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2161static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2162static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2163static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2164static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2165 2166#define UCODE(x) x, sizeof(x) 2167 2168struct ucode { 2169 u_int32_t revision; 2170 u_int32_t *ucode; 2171 int length; 2172 u_short int_delay_offset; 2173 u_short bundle_max_offset; 2174} ucode_table[] = { 2175 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2176 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2177 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2178 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2179 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2180 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2181 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2182 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2183 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2184 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2185 { 0, NULL, 0, 0, 0 } 2186}; 2187 2188static void 2189fxp_load_ucode(struct fxp_softc *sc) 2190{ 2191 struct ucode *uc; 2192 struct fxp_cb_ucode *cbp; 2193 2194 for (uc = ucode_table; uc->ucode != NULL; uc++) 2195 if (sc->revision == uc->revision) 2196 break; 2197 if (uc->ucode == NULL) 2198 return; 2199 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2200 cbp->cb_status = 0; 2201 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2202 cbp->link_addr = -1; /* (no) next command */ 2203 memcpy(cbp->ucode, uc->ucode, uc->length); 2204 if (uc->int_delay_offset) 2205 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2206 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2207 if (uc->bundle_max_offset) 2208 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2209 sc->tunable_bundle_max; 2210 /* 2211 * Download the ucode to the chip. 2212 */ 2213 fxp_scb_wait(sc); 2214 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2215 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2216 /* ...and wait for it to complete. */ 2217 fxp_dma_wait(&cbp->cb_status, sc); 2218 device_printf(sc->dev, 2219 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2220 sc->tunable_int_delay, 2221 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2222 sc->flags |= FXP_FLAG_UCODE; 2223} 2224 2225static int 2226sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2227{ 2228 int error, value; 2229 2230 value = *(int *)arg1; 2231 error = sysctl_handle_int(oidp, &value, 0, req); 2232 if (error || !req->newptr) 2233 return (error); 2234 if (value < low || value > high) 2235 return (EINVAL); 2236 *(int *)arg1 = value; 2237 return (0); 2238} 2239 2240/* 2241 * Interrupt delay is expressed in microseconds, a multiplier is used 2242 * to convert this to the appropriate clock ticks before using. 2243 */ 2244static int 2245sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2246{ 2247 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2248} 2249 2250static int 2251sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2252{ 2253 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2254} 2255